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adbmsFunctionTest/build/debug/Core/Src/system_stm32f3xx.lst

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EEPROM 24LC02 integration
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ARM GAS /tmp/cclMhFfC.s page 1
base code for voltage measurement
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1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "system_stm32f3xx.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .file 1 "Core/Src/system_stm32f3xx.c"
20 .section .text.SystemInit,"ax",%progbits
21 .align 1
22 .global SystemInit
23 .syntax unified
24 .thumb
25 .thumb_func
27 SystemInit:
28 .LFB123:
1:Core/Src/system_stm32f3xx.c **** /**
2:Core/Src/system_stm32f3xx.c **** ******************************************************************************
3:Core/Src/system_stm32f3xx.c **** * @file system_stm32f3xx.c
4:Core/Src/system_stm32f3xx.c **** * @author MCD Application Team
5:Core/Src/system_stm32f3xx.c **** * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
6:Core/Src/system_stm32f3xx.c **** *
7:Core/Src/system_stm32f3xx.c **** * 1. This file provides two functions and one global variable to be called from
8:Core/Src/system_stm32f3xx.c **** * user application:
9:Core/Src/system_stm32f3xx.c **** * - SystemInit(): This function is called at startup just after reset and
10:Core/Src/system_stm32f3xx.c **** * before branch to main program. This call is made inside
11:Core/Src/system_stm32f3xx.c **** * the "startup_stm32f3xx.s" file.
12:Core/Src/system_stm32f3xx.c **** *
13:Core/Src/system_stm32f3xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14:Core/Src/system_stm32f3xx.c **** * by the user application to setup the SysTick
15:Core/Src/system_stm32f3xx.c **** * timer or configure other parameters.
16:Core/Src/system_stm32f3xx.c **** *
17:Core/Src/system_stm32f3xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18:Core/Src/system_stm32f3xx.c **** * be called whenever the core clock is changed
19:Core/Src/system_stm32f3xx.c **** * during program execution.
20:Core/Src/system_stm32f3xx.c **** *
21:Core/Src/system_stm32f3xx.c **** * 2. After each device reset the HSI (8 MHz) is used as system clock source.
22:Core/Src/system_stm32f3xx.c **** * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
23:Core/Src/system_stm32f3xx.c **** * configure the system clock before to branch to main program.
24:Core/Src/system_stm32f3xx.c **** *
25:Core/Src/system_stm32f3xx.c **** * 3. This file configures the system clock as follows:
26:Core/Src/system_stm32f3xx.c **** *=============================================================================
27:Core/Src/system_stm32f3xx.c **** * Supported STM32F3xx device
28:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
29:Core/Src/system_stm32f3xx.c **** * System Clock source | HSI
30:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
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31:Core/Src/system_stm32f3xx.c **** * SYSCLK(Hz) | 8000000
32:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
33:Core/Src/system_stm32f3xx.c **** * HCLK(Hz) | 8000000
34:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
35:Core/Src/system_stm32f3xx.c **** * AHB Prescaler | 1
36:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
37:Core/Src/system_stm32f3xx.c **** * APB2 Prescaler | 1
38:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
39:Core/Src/system_stm32f3xx.c **** * APB1 Prescaler | 1
40:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
41:Core/Src/system_stm32f3xx.c **** * USB Clock | DISABLE
42:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
43:Core/Src/system_stm32f3xx.c **** *=============================================================================
44:Core/Src/system_stm32f3xx.c **** ******************************************************************************
45:Core/Src/system_stm32f3xx.c **** * @attention
46:Core/Src/system_stm32f3xx.c **** *
47:Core/Src/system_stm32f3xx.c **** * Copyright (c) 2016 STMicroelectronics.
48:Core/Src/system_stm32f3xx.c **** * All rights reserved.
49:Core/Src/system_stm32f3xx.c **** *
50:Core/Src/system_stm32f3xx.c **** * This software is licensed under terms that can be found in the LICENSE file
51:Core/Src/system_stm32f3xx.c **** * in the root directory of this software component.
52:Core/Src/system_stm32f3xx.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
53:Core/Src/system_stm32f3xx.c **** *
54:Core/Src/system_stm32f3xx.c **** ******************************************************************************
55:Core/Src/system_stm32f3xx.c **** */
56:Core/Src/system_stm32f3xx.c ****
57:Core/Src/system_stm32f3xx.c **** /** @addtogroup CMSIS
58:Core/Src/system_stm32f3xx.c **** * @{
59:Core/Src/system_stm32f3xx.c **** */
60:Core/Src/system_stm32f3xx.c ****
61:Core/Src/system_stm32f3xx.c **** /** @addtogroup stm32f3xx_system
62:Core/Src/system_stm32f3xx.c **** * @{
63:Core/Src/system_stm32f3xx.c **** */
64:Core/Src/system_stm32f3xx.c ****
65:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Includes
66:Core/Src/system_stm32f3xx.c **** * @{
67:Core/Src/system_stm32f3xx.c **** */
68:Core/Src/system_stm32f3xx.c ****
69:Core/Src/system_stm32f3xx.c **** #include "stm32f3xx.h"
70:Core/Src/system_stm32f3xx.c ****
71:Core/Src/system_stm32f3xx.c **** /**
72:Core/Src/system_stm32f3xx.c **** * @}
73:Core/Src/system_stm32f3xx.c **** */
74:Core/Src/system_stm32f3xx.c ****
75:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_TypesDefinitions
76:Core/Src/system_stm32f3xx.c **** * @{
77:Core/Src/system_stm32f3xx.c **** */
78:Core/Src/system_stm32f3xx.c ****
79:Core/Src/system_stm32f3xx.c **** /**
80:Core/Src/system_stm32f3xx.c **** * @}
81:Core/Src/system_stm32f3xx.c **** */
82:Core/Src/system_stm32f3xx.c ****
83:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Defines
84:Core/Src/system_stm32f3xx.c **** * @{
85:Core/Src/system_stm32f3xx.c **** */
86:Core/Src/system_stm32f3xx.c **** #if !defined (HSE_VALUE)
87:Core/Src/system_stm32f3xx.c **** #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
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88:Core/Src/system_stm32f3xx.c **** This value can be provided and adapted by the user
89:Core/Src/system_stm32f3xx.c **** #endif /* HSE_VALUE */
90:Core/Src/system_stm32f3xx.c ****
91:Core/Src/system_stm32f3xx.c **** #if !defined (HSI_VALUE)
92:Core/Src/system_stm32f3xx.c **** #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
93:Core/Src/system_stm32f3xx.c **** This value can be provided and adapted by the user
94:Core/Src/system_stm32f3xx.c **** #endif /* HSI_VALUE */
95:Core/Src/system_stm32f3xx.c ****
96:Core/Src/system_stm32f3xx.c **** /* Note: Following vector table addresses must be defined in line with linker
97:Core/Src/system_stm32f3xx.c **** configuration. */
98:Core/Src/system_stm32f3xx.c **** /*!< Uncomment the following line if you need to relocate the vector table
99:Core/Src/system_stm32f3xx.c **** anywhere in Flash or Sram, else the vector table is kept at the automatic
100:Core/Src/system_stm32f3xx.c **** remap of boot address selected */
101:Core/Src/system_stm32f3xx.c **** /* #define USER_VECT_TAB_ADDRESS */
102:Core/Src/system_stm32f3xx.c ****
103:Core/Src/system_stm32f3xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
104:Core/Src/system_stm32f3xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table
105:Core/Src/system_stm32f3xx.c **** in Sram else user remap will be done in Flash. */
106:Core/Src/system_stm32f3xx.c **** /* #define VECT_TAB_SRAM */
107:Core/Src/system_stm32f3xx.c **** #if defined(VECT_TAB_SRAM)
108:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
109:Core/Src/system_stm32f3xx.c **** This value must be a multiple of 0x200. */
110:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
111:Core/Src/system_stm32f3xx.c **** This value must be a multiple of 0x200. */
112:Core/Src/system_stm32f3xx.c **** #else
113:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
114:Core/Src/system_stm32f3xx.c **** This value must be a multiple of 0x200. */
115:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
116:Core/Src/system_stm32f3xx.c **** This value must be a multiple of 0x200. */
117:Core/Src/system_stm32f3xx.c **** #endif /* VECT_TAB_SRAM */
118:Core/Src/system_stm32f3xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
119:Core/Src/system_stm32f3xx.c ****
120:Core/Src/system_stm32f3xx.c **** /******************************************************************************/
121:Core/Src/system_stm32f3xx.c **** /**
122:Core/Src/system_stm32f3xx.c **** * @}
123:Core/Src/system_stm32f3xx.c **** */
124:Core/Src/system_stm32f3xx.c ****
125:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Macros
126:Core/Src/system_stm32f3xx.c **** * @{
127:Core/Src/system_stm32f3xx.c **** */
128:Core/Src/system_stm32f3xx.c ****
129:Core/Src/system_stm32f3xx.c **** /**
130:Core/Src/system_stm32f3xx.c **** * @}
131:Core/Src/system_stm32f3xx.c **** */
132:Core/Src/system_stm32f3xx.c ****
133:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Variables
134:Core/Src/system_stm32f3xx.c **** * @{
135:Core/Src/system_stm32f3xx.c **** */
136:Core/Src/system_stm32f3xx.c **** /* This variable is updated in three ways:
137:Core/Src/system_stm32f3xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate()
138:Core/Src/system_stm32f3xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
139:Core/Src/system_stm32f3xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
140:Core/Src/system_stm32f3xx.c **** Note: If you use this function to configure the system clock there is no need to
141:Core/Src/system_stm32f3xx.c **** call the 2 first functions listed above, since SystemCoreClock variable is
142:Core/Src/system_stm32f3xx.c **** updated automatically.
143:Core/Src/system_stm32f3xx.c **** */
144:Core/Src/system_stm32f3xx.c **** uint32_t SystemCoreClock = 8000000;
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145:Core/Src/system_stm32f3xx.c ****
146:Core/Src/system_stm32f3xx.c **** const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
147:Core/Src/system_stm32f3xx.c **** const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
148:Core/Src/system_stm32f3xx.c ****
149:Core/Src/system_stm32f3xx.c **** /**
150:Core/Src/system_stm32f3xx.c **** * @}
151:Core/Src/system_stm32f3xx.c **** */
152:Core/Src/system_stm32f3xx.c ****
153:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
154:Core/Src/system_stm32f3xx.c **** * @{
155:Core/Src/system_stm32f3xx.c **** */
156:Core/Src/system_stm32f3xx.c ****
157:Core/Src/system_stm32f3xx.c **** /**
158:Core/Src/system_stm32f3xx.c **** * @}
159:Core/Src/system_stm32f3xx.c **** */
160:Core/Src/system_stm32f3xx.c ****
161:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Functions
162:Core/Src/system_stm32f3xx.c **** * @{
163:Core/Src/system_stm32f3xx.c **** */
164:Core/Src/system_stm32f3xx.c ****
165:Core/Src/system_stm32f3xx.c **** /**
166:Core/Src/system_stm32f3xx.c **** * @brief Setup the microcontroller system
167:Core/Src/system_stm32f3xx.c **** * @param None
168:Core/Src/system_stm32f3xx.c **** * @retval None
169:Core/Src/system_stm32f3xx.c **** */
170:Core/Src/system_stm32f3xx.c **** void SystemInit(void)
171:Core/Src/system_stm32f3xx.c **** {
29 .loc 1 171 1 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 0
32 @ frame_needed = 0, uses_anonymous_args = 0
33 @ link register save eliminated.
172:Core/Src/system_stm32f3xx.c **** /* FPU settings --------------------------------------------------------------*/
173:Core/Src/system_stm32f3xx.c **** #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
174:Core/Src/system_stm32f3xx.c **** SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
34 .loc 1 174 3 view .LVU1
35 .loc 1 174 6 is_stmt 0 view .LVU2
36 0000 034A ldr r2, .L2
37 0002 D2F88830 ldr r3, [r2, #136]
38 .loc 1 174 14 view .LVU3
39 0006 43F47003 orr r3, r3, #15728640
40 000a C2F88830 str r3, [r2, #136]
175:Core/Src/system_stm32f3xx.c **** #endif
176:Core/Src/system_stm32f3xx.c ****
177:Core/Src/system_stm32f3xx.c **** /* Configure the Vector Table location -------------------------------------*/
178:Core/Src/system_stm32f3xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
179:Core/Src/system_stm32f3xx.c **** SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM
180:Core/Src/system_stm32f3xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
181:Core/Src/system_stm32f3xx.c **** }
41 .loc 1 181 1 view .LVU4
42 000e 7047 bx lr
43 .L3:
44 .align 2
45 .L2:
46 0010 00ED00E0 .word -536810240
47 .cfi_endproc
48 .LFE123:
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50 .section .text.SystemCoreClockUpdate,"ax",%progbits
51 .align 1
52 .global SystemCoreClockUpdate
53 .syntax unified
54 .thumb
55 .thumb_func
57 SystemCoreClockUpdate:
58 .LFB124:
182:Core/Src/system_stm32f3xx.c ****
183:Core/Src/system_stm32f3xx.c **** /**
184:Core/Src/system_stm32f3xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values.
185:Core/Src/system_stm32f3xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can
186:Core/Src/system_stm32f3xx.c **** * be used by the user application to setup the SysTick timer or configure
187:Core/Src/system_stm32f3xx.c **** * other parameters.
188:Core/Src/system_stm32f3xx.c **** *
189:Core/Src/system_stm32f3xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called
190:Core/Src/system_stm32f3xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration
191:Core/Src/system_stm32f3xx.c **** * based on this variable will be incorrect.
192:Core/Src/system_stm32f3xx.c **** *
193:Core/Src/system_stm32f3xx.c **** * @note - The system frequency computed by this function is not the real
194:Core/Src/system_stm32f3xx.c **** * frequency in the chip. It is calculated based on the predefined
195:Core/Src/system_stm32f3xx.c **** * constant and the selected clock source:
196:Core/Src/system_stm32f3xx.c **** *
197:Core/Src/system_stm32f3xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
198:Core/Src/system_stm32f3xx.c **** *
199:Core/Src/system_stm32f3xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
200:Core/Src/system_stm32f3xx.c **** *
201:Core/Src/system_stm32f3xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
202:Core/Src/system_stm32f3xx.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors.
203:Core/Src/system_stm32f3xx.c **** *
204:Core/Src/system_stm32f3xx.c **** * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
205:Core/Src/system_stm32f3xx.c **** * 8 MHz) but the real value may vary depending on the variations
206:Core/Src/system_stm32f3xx.c **** * in voltage and temperature.
207:Core/Src/system_stm32f3xx.c **** *
208:Core/Src/system_stm32f3xx.c **** * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
209:Core/Src/system_stm32f3xx.c **** * 8 MHz), user has to ensure that HSE_VALUE is same as the real
210:Core/Src/system_stm32f3xx.c **** * frequency of the crystal used. Otherwise, this function may
211:Core/Src/system_stm32f3xx.c **** * have wrong result.
212:Core/Src/system_stm32f3xx.c **** *
213:Core/Src/system_stm32f3xx.c **** * - The result of this function could be not correct when using fractional
214:Core/Src/system_stm32f3xx.c **** * value for HSE crystal.
215:Core/Src/system_stm32f3xx.c **** *
216:Core/Src/system_stm32f3xx.c **** * @param None
217:Core/Src/system_stm32f3xx.c **** * @retval None
218:Core/Src/system_stm32f3xx.c **** */
219:Core/Src/system_stm32f3xx.c **** void SystemCoreClockUpdate (void)
220:Core/Src/system_stm32f3xx.c **** {
59 .loc 1 220 1 is_stmt 1 view -0
60 .cfi_startproc
61 @ args = 0, pretend = 0, frame = 0
62 @ frame_needed = 0, uses_anonymous_args = 0
63 @ link register save eliminated.
221:Core/Src/system_stm32f3xx.c **** uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
64 .loc 1 221 3 view .LVU6
65 .LVL0:
222:Core/Src/system_stm32f3xx.c ****
223:Core/Src/system_stm32f3xx.c **** /* Get SYSCLK source -------------------------------------------------------*/
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224:Core/Src/system_stm32f3xx.c **** tmp = RCC->CFGR & RCC_CFGR_SWS;
66 .loc 1 224 3 view .LVU7
67 .loc 1 224 12 is_stmt 0 view .LVU8
68 0000 1D4B ldr r3, .L10
69 0002 5B68 ldr r3, [r3, #4]
70 .loc 1 224 7 view .LVU9
71 0004 03F00C03 and r3, r3, #12
72 .LVL1:
225:Core/Src/system_stm32f3xx.c ****
226:Core/Src/system_stm32f3xx.c **** switch (tmp)
73 .loc 1 226 3 is_stmt 1 view .LVU10
74 0008 042B cmp r3, #4
75 000a 11D0 beq .L5
76 000c 082B cmp r3, #8
77 000e 13D0 beq .L6
78 0010 002B cmp r3, #0
79 0012 2DD1 bne .L7
227:Core/Src/system_stm32f3xx.c **** {
228:Core/Src/system_stm32f3xx.c **** case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
229:Core/Src/system_stm32f3xx.c **** SystemCoreClock = HSI_VALUE;
80 .loc 1 229 7 view .LVU11
81 .loc 1 229 23 is_stmt 0 view .LVU12
82 0014 194B ldr r3, .L10+4
83 .LVL2:
84 .loc 1 229 23 view .LVU13
85 0016 1A4A ldr r2, .L10+8
86 0018 1A60 str r2, [r3]
230:Core/Src/system_stm32f3xx.c **** break;
87 .loc 1 230 7 is_stmt 1 view .LVU14
88 .LVL3:
89 .L8:
231:Core/Src/system_stm32f3xx.c **** case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
232:Core/Src/system_stm32f3xx.c **** SystemCoreClock = HSE_VALUE;
233:Core/Src/system_stm32f3xx.c **** break;
234:Core/Src/system_stm32f3xx.c **** case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
235:Core/Src/system_stm32f3xx.c **** /* Get PLL clock source and multiplication factor ----------------------*/
236:Core/Src/system_stm32f3xx.c **** pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
237:Core/Src/system_stm32f3xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
238:Core/Src/system_stm32f3xx.c **** pllmull = ( pllmull >> 18) + 2;
239:Core/Src/system_stm32f3xx.c ****
240:Core/Src/system_stm32f3xx.c **** #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
241:Core/Src/system_stm32f3xx.c **** predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
242:Core/Src/system_stm32f3xx.c **** if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
243:Core/Src/system_stm32f3xx.c **** {
244:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
245:Core/Src/system_stm32f3xx.c **** SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
246:Core/Src/system_stm32f3xx.c **** }
247:Core/Src/system_stm32f3xx.c **** else
248:Core/Src/system_stm32f3xx.c **** {
249:Core/Src/system_stm32f3xx.c **** /* HSI oscillator clock selected as PREDIV1 clock entry */
250:Core/Src/system_stm32f3xx.c **** SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
251:Core/Src/system_stm32f3xx.c **** }
252:Core/Src/system_stm32f3xx.c **** #else
253:Core/Src/system_stm32f3xx.c **** if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
254:Core/Src/system_stm32f3xx.c **** {
255:Core/Src/system_stm32f3xx.c **** /* HSI oscillator clock divided by 2 selected as PLL clock entry */
256:Core/Src/system_stm32f3xx.c **** SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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257:Core/Src/system_stm32f3xx.c **** }
258:Core/Src/system_stm32f3xx.c **** else
259:Core/Src/system_stm32f3xx.c **** {
260:Core/Src/system_stm32f3xx.c **** predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
261:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
262:Core/Src/system_stm32f3xx.c **** SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
263:Core/Src/system_stm32f3xx.c **** }
264:Core/Src/system_stm32f3xx.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
265:Core/Src/system_stm32f3xx.c **** break;
266:Core/Src/system_stm32f3xx.c **** default: /* HSI used as system clock */
267:Core/Src/system_stm32f3xx.c **** SystemCoreClock = HSI_VALUE;
268:Core/Src/system_stm32f3xx.c **** break;
269:Core/Src/system_stm32f3xx.c **** }
270:Core/Src/system_stm32f3xx.c **** /* Compute HCLK clock frequency ----------------*/
271:Core/Src/system_stm32f3xx.c **** /* Get HCLK prescaler */
272:Core/Src/system_stm32f3xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
90 .loc 1 272 3 view .LVU15
91 .loc 1 272 28 is_stmt 0 view .LVU16
92 001a 174B ldr r3, .L10
93 001c 5B68 ldr r3, [r3, #4]
94 .loc 1 272 52 view .LVU17
95 001e C3F30313 ubfx r3, r3, #4, #4
96 .loc 1 272 22 view .LVU18
97 0022 184A ldr r2, .L10+12
98 0024 D15C ldrb r1, [r2, r3] @ zero_extendqisi2
99 .LVL4:
273:Core/Src/system_stm32f3xx.c **** /* HCLK clock frequency */
274:Core/Src/system_stm32f3xx.c **** SystemCoreClock >>= tmp;
100 .loc 1 274 3 is_stmt 1 view .LVU19
101 .loc 1 274 19 is_stmt 0 view .LVU20
102 0026 154A ldr r2, .L10+4
103 0028 1368 ldr r3, [r2]
104 002a CB40 lsrs r3, r3, r1
105 002c 1360 str r3, [r2]
275:Core/Src/system_stm32f3xx.c **** }
106 .loc 1 275 1 view .LVU21
107 002e 7047 bx lr
108 .LVL5:
109 .L5:
232:Core/Src/system_stm32f3xx.c **** break;
110 .loc 1 232 7 is_stmt 1 view .LVU22
232:Core/Src/system_stm32f3xx.c **** break;
111 .loc 1 232 23 is_stmt 0 view .LVU23
112 0030 124B ldr r3, .L10+4
113 .LVL6:
232:Core/Src/system_stm32f3xx.c **** break;
114 .loc 1 232 23 view .LVU24
115 0032 134A ldr r2, .L10+8
116 0034 1A60 str r2, [r3]
233:Core/Src/system_stm32f3xx.c **** case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
117 .loc 1 233 7 is_stmt 1 view .LVU25
118 0036 F0E7 b .L8
119 .LVL7:
120 .L6:
236:Core/Src/system_stm32f3xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
121 .loc 1 236 7 view .LVU26
236:Core/Src/system_stm32f3xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
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122 .loc 1 236 20 is_stmt 0 view .LVU27
123 0038 0F4A ldr r2, .L10
124 003a 5368 ldr r3, [r2, #4]
125 .LVL8:
237:Core/Src/system_stm32f3xx.c **** pllmull = ( pllmull >> 18) + 2;
126 .loc 1 237 7 is_stmt 1 view .LVU28
237:Core/Src/system_stm32f3xx.c **** pllmull = ( pllmull >> 18) + 2;
127 .loc 1 237 22 is_stmt 0 view .LVU29
128 003c 5268 ldr r2, [r2, #4]
129 .LVL9:
238:Core/Src/system_stm32f3xx.c ****
130 .loc 1 238 7 is_stmt 1 view .LVU30
238:Core/Src/system_stm32f3xx.c ****
131 .loc 1 238 27 is_stmt 0 view .LVU31
132 003e C3F38343 ubfx r3, r3, #18, #4
133 .LVL10:
238:Core/Src/system_stm32f3xx.c ****
134 .loc 1 238 15 view .LVU32
135 0042 0233 adds r3, r3, #2
136 .LVL11:
253:Core/Src/system_stm32f3xx.c **** {
137 .loc 1 253 7 is_stmt 1 view .LVU33
253:Core/Src/system_stm32f3xx.c **** {
138 .loc 1 253 10 is_stmt 0 view .LVU34
139 0044 12F4803F tst r2, #65536
140 0048 05D1 bne .L9
256:Core/Src/system_stm32f3xx.c **** }
141 .loc 1 256 9 is_stmt 1 view .LVU35
256:Core/Src/system_stm32f3xx.c **** }
142 .loc 1 256 44 is_stmt 0 view .LVU36
143 004a 0F4A ldr r2, .L10+16
144 .LVL12:
256:Core/Src/system_stm32f3xx.c **** }
145 .loc 1 256 44 view .LVU37
146 004c 02FB03F3 mul r3, r2, r3
147 .LVL13:
256:Core/Src/system_stm32f3xx.c **** }
148 .loc 1 256 25 view .LVU38
149 0050 0A4A ldr r2, .L10+4
150 0052 1360 str r3, [r2]
151 0054 E1E7 b .L8
152 .LVL14:
153 .L9:
260:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
154 .loc 1 260 9 is_stmt 1 view .LVU39
260:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
155 .loc 1 260 28 is_stmt 0 view .LVU40
156 0056 084A ldr r2, .L10
157 .LVL15:
260:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
158 .loc 1 260 28 view .LVU41
159 0058 D16A ldr r1, [r2, #44]
260:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
160 .loc 1 260 36 view .LVU42
161 005a 01F00F01 and r1, r1, #15
260:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
162 .loc 1 260 22 view .LVU43
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163 005e 0131 adds r1, r1, #1
164 .LVL16:
262:Core/Src/system_stm32f3xx.c **** }
165 .loc 1 262 9 is_stmt 1 view .LVU44
262:Core/Src/system_stm32f3xx.c **** }
166 .loc 1 262 38 is_stmt 0 view .LVU45
167 0060 074A ldr r2, .L10+8
168 0062 B2FBF1F2 udiv r2, r2, r1
262:Core/Src/system_stm32f3xx.c **** }
169 .loc 1 262 54 view .LVU46
170 0066 02FB03F3 mul r3, r2, r3
171 .LVL17:
262:Core/Src/system_stm32f3xx.c **** }
172 .loc 1 262 25 view .LVU47
173 006a 044A ldr r2, .L10+4
174 006c 1360 str r3, [r2]
175 006e D4E7 b .L8
176 .LVL18:
177 .L7:
267:Core/Src/system_stm32f3xx.c **** break;
178 .loc 1 267 7 is_stmt 1 view .LVU48
267:Core/Src/system_stm32f3xx.c **** break;
179 .loc 1 267 23 is_stmt 0 view .LVU49
180 0070 024B ldr r3, .L10+4
181 .LVL19:
267:Core/Src/system_stm32f3xx.c **** break;
182 .loc 1 267 23 view .LVU50
183 0072 034A ldr r2, .L10+8
184 0074 1A60 str r2, [r3]
268:Core/Src/system_stm32f3xx.c **** }
185 .loc 1 268 7 is_stmt 1 view .LVU51
186 0076 D0E7 b .L8
187 .L11:
188 .align 2
189 .L10:
190 0078 00100240 .word 1073876992
191 007c 00000000 .word SystemCoreClock
192 0080 00127A00 .word 8000000
193 0084 00000000 .word AHBPrescTable
194 0088 00093D00 .word 4000000
195 .cfi_endproc
196 .LFE124:
198 .global APBPrescTable
199 .section .rodata.APBPrescTable,"a"
200 .align 2
203 APBPrescTable:
204 0000 00000000 .ascii "\000\000\000\000\001\002\003\004"
204 01020304
205 .global AHBPrescTable
206 .section .rodata.AHBPrescTable,"a"
207 .align 2
210 AHBPrescTable:
211 0000 00000000 .ascii "\000\000\000\000\000\000\000\000\001\002\003\004\006"
211 00000000
211 01020304
211 06
212 000d 070809 .ascii "\007\010\011"
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213 .global SystemCoreClock
214 .section .data.SystemCoreClock,"aw"
215 .align 2
218 SystemCoreClock:
219 0000 00127A00 .word 8000000
220 .text
221 .Letext0:
222 .file 2 "/home/chiangni/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-
223 .file 3 "/home/chiangni/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-
224 .file 4 "Drivers/CMSIS/Include/core_cm4.h"
225 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h"
226 .file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302x8.h"
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DEFINED SYMBOLS
*ABS*:00000000 system_stm32f3xx.c
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/tmp/cclMhFfC.s:21 .text.SystemInit:00000000 $t
/tmp/cclMhFfC.s:27 .text.SystemInit:00000000 SystemInit
/tmp/cclMhFfC.s:46 .text.SystemInit:00000010 $d
/tmp/cclMhFfC.s:51 .text.SystemCoreClockUpdate:00000000 $t
/tmp/cclMhFfC.s:57 .text.SystemCoreClockUpdate:00000000 SystemCoreClockUpdate
/tmp/cclMhFfC.s:190 .text.SystemCoreClockUpdate:00000078 $d
/tmp/cclMhFfC.s:218 .data.SystemCoreClock:00000000 SystemCoreClock
/tmp/cclMhFfC.s:210 .rodata.AHBPrescTable:00000000 AHBPrescTable
/tmp/cclMhFfC.s:203 .rodata.APBPrescTable:00000000 APBPrescTable
/tmp/cclMhFfC.s:200 .rodata.APBPrescTable:00000000 $d
/tmp/cclMhFfC.s:207 .rodata.AHBPrescTable:00000000 $d
/tmp/cclMhFfC.s:215 .data.SystemCoreClock:00000000 $d
base code for voltage measurement
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NO UNDEFINED SYMBOLS