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TTS
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TTS/Debug/TTS.list

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TTS.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000000c0 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00002418 080000c0 080000c0 000100c0 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000030 080024d8 080024d8 000124d8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08002508 08002508 0002000c 2**0
CONTENTS
4 .ARM 00000000 08002508 08002508 0002000c 2**0
CONTENTS
5 .preinit_array 00000000 08002508 08002508 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08002508 08002508 00012508 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 0800250c 0800250c 0001250c 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000000c 20000000 08002510 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000000cc 2000000c 0800251c 0002000c 2**2
ALLOC
10 ._user_heap_stack 00000600 200000d8 0800251c 000200d8 2**0
ALLOC
11 .ARM.attributes 00000028 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
12 .debug_info 00006e65 00000000 00000000 00020034 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00001643 00000000 00000000 00026e99 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000700 00000000 00000000 000284e0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 00000638 00000000 00000000 00028be0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00016f94 00000000 00000000 00029218 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00009911 00000000 00000000 000401ac 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000820c1 00000000 00000000 00049abd 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000050 00000000 00000000 000cbb7e 2**0
CONTENTS, READONLY
20 .debug_frame 000017c4 00000000 00000000 000cbbd0 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080000c0 <__do_global_dtors_aux>:
80000c0: b510 push {r4, lr}
80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>)
80000c4: 7823 ldrb r3, [r4, #0]
80000c6: 2b00 cmp r3, #0
80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a>
80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>)
80000cc: 2b00 cmp r3, #0
80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16>
80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>)
80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16>
80000d4: bf00 nop
80000d6: 2301 movs r3, #1
80000d8: 7023 strb r3, [r4, #0]
80000da: bd10 pop {r4, pc}
80000dc: 2000000c .word 0x2000000c
80000e0: 00000000 .word 0x00000000
80000e4: 080024c0 .word 0x080024c0
080000e8 <frame_dummy>:
80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc <frame_dummy+0x14>)
80000ea: b510 push {r4, lr}
80000ec: 2b00 cmp r3, #0
80000ee: d003 beq.n 80000f8 <frame_dummy+0x10>
80000f0: 4903 ldr r1, [pc, #12] ; (8000100 <frame_dummy+0x18>)
80000f2: 4804 ldr r0, [pc, #16] ; (8000104 <frame_dummy+0x1c>)
80000f4: e000 b.n 80000f8 <frame_dummy+0x10>
80000f6: bf00 nop
80000f8: bd10 pop {r4, pc}
80000fa: 46c0 nop ; (mov r8, r8)
80000fc: 00000000 .word 0x00000000
8000100: 20000010 .word 0x20000010
8000104: 080024c0 .word 0x080024c0
08000108 <__udivsi3>:
8000108: 2200 movs r2, #0
800010a: 0843 lsrs r3, r0, #1
800010c: 428b cmp r3, r1
800010e: d374 bcc.n 80001fa <__udivsi3+0xf2>
8000110: 0903 lsrs r3, r0, #4
8000112: 428b cmp r3, r1
8000114: d35f bcc.n 80001d6 <__udivsi3+0xce>
8000116: 0a03 lsrs r3, r0, #8
8000118: 428b cmp r3, r1
800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e>
800011c: 0b03 lsrs r3, r0, #12
800011e: 428b cmp r3, r1
8000120: d328 bcc.n 8000174 <__udivsi3+0x6c>
8000122: 0c03 lsrs r3, r0, #16
8000124: 428b cmp r3, r1
8000126: d30d bcc.n 8000144 <__udivsi3+0x3c>
8000128: 22ff movs r2, #255 ; 0xff
800012a: 0209 lsls r1, r1, #8
800012c: ba12 rev r2, r2
800012e: 0c03 lsrs r3, r0, #16
8000130: 428b cmp r3, r1
8000132: d302 bcc.n 800013a <__udivsi3+0x32>
8000134: 1212 asrs r2, r2, #8
8000136: 0209 lsls r1, r1, #8
8000138: d065 beq.n 8000206 <__udivsi3+0xfe>
800013a: 0b03 lsrs r3, r0, #12
800013c: 428b cmp r3, r1
800013e: d319 bcc.n 8000174 <__udivsi3+0x6c>
8000140: e000 b.n 8000144 <__udivsi3+0x3c>
8000142: 0a09 lsrs r1, r1, #8
8000144: 0bc3 lsrs r3, r0, #15
8000146: 428b cmp r3, r1
8000148: d301 bcc.n 800014e <__udivsi3+0x46>
800014a: 03cb lsls r3, r1, #15
800014c: 1ac0 subs r0, r0, r3
800014e: 4152 adcs r2, r2
8000150: 0b83 lsrs r3, r0, #14
8000152: 428b cmp r3, r1
8000154: d301 bcc.n 800015a <__udivsi3+0x52>
8000156: 038b lsls r3, r1, #14
8000158: 1ac0 subs r0, r0, r3
800015a: 4152 adcs r2, r2
800015c: 0b43 lsrs r3, r0, #13
800015e: 428b cmp r3, r1
8000160: d301 bcc.n 8000166 <__udivsi3+0x5e>
8000162: 034b lsls r3, r1, #13
8000164: 1ac0 subs r0, r0, r3
8000166: 4152 adcs r2, r2
8000168: 0b03 lsrs r3, r0, #12
800016a: 428b cmp r3, r1
800016c: d301 bcc.n 8000172 <__udivsi3+0x6a>
800016e: 030b lsls r3, r1, #12
8000170: 1ac0 subs r0, r0, r3
8000172: 4152 adcs r2, r2
8000174: 0ac3 lsrs r3, r0, #11
8000176: 428b cmp r3, r1
8000178: d301 bcc.n 800017e <__udivsi3+0x76>
800017a: 02cb lsls r3, r1, #11
800017c: 1ac0 subs r0, r0, r3
800017e: 4152 adcs r2, r2
8000180: 0a83 lsrs r3, r0, #10
8000182: 428b cmp r3, r1
8000184: d301 bcc.n 800018a <__udivsi3+0x82>
8000186: 028b lsls r3, r1, #10
8000188: 1ac0 subs r0, r0, r3
800018a: 4152 adcs r2, r2
800018c: 0a43 lsrs r3, r0, #9
800018e: 428b cmp r3, r1
8000190: d301 bcc.n 8000196 <__udivsi3+0x8e>
8000192: 024b lsls r3, r1, #9
8000194: 1ac0 subs r0, r0, r3
8000196: 4152 adcs r2, r2
8000198: 0a03 lsrs r3, r0, #8
800019a: 428b cmp r3, r1
800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a>
800019e: 020b lsls r3, r1, #8
80001a0: 1ac0 subs r0, r0, r3
80001a2: 4152 adcs r2, r2
80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a>
80001a6: 09c3 lsrs r3, r0, #7
80001a8: 428b cmp r3, r1
80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8>
80001ac: 01cb lsls r3, r1, #7
80001ae: 1ac0 subs r0, r0, r3
80001b0: 4152 adcs r2, r2
80001b2: 0983 lsrs r3, r0, #6
80001b4: 428b cmp r3, r1
80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4>
80001b8: 018b lsls r3, r1, #6
80001ba: 1ac0 subs r0, r0, r3
80001bc: 4152 adcs r2, r2
80001be: 0943 lsrs r3, r0, #5
80001c0: 428b cmp r3, r1
80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0>
80001c4: 014b lsls r3, r1, #5
80001c6: 1ac0 subs r0, r0, r3
80001c8: 4152 adcs r2, r2
80001ca: 0903 lsrs r3, r0, #4
80001cc: 428b cmp r3, r1
80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc>
80001d0: 010b lsls r3, r1, #4
80001d2: 1ac0 subs r0, r0, r3
80001d4: 4152 adcs r2, r2
80001d6: 08c3 lsrs r3, r0, #3
80001d8: 428b cmp r3, r1
80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8>
80001dc: 00cb lsls r3, r1, #3
80001de: 1ac0 subs r0, r0, r3
80001e0: 4152 adcs r2, r2
80001e2: 0883 lsrs r3, r0, #2
80001e4: 428b cmp r3, r1
80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4>
80001e8: 008b lsls r3, r1, #2
80001ea: 1ac0 subs r0, r0, r3
80001ec: 4152 adcs r2, r2
80001ee: 0843 lsrs r3, r0, #1
80001f0: 428b cmp r3, r1
80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0>
80001f4: 004b lsls r3, r1, #1
80001f6: 1ac0 subs r0, r0, r3
80001f8: 4152 adcs r2, r2
80001fa: 1a41 subs r1, r0, r1
80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8>
80001fe: 4601 mov r1, r0
8000200: 4152 adcs r2, r2
8000202: 4610 mov r0, r2
8000204: 4770 bx lr
8000206: e7ff b.n 8000208 <__udivsi3+0x100>
8000208: b501 push {r0, lr}
800020a: 2000 movs r0, #0
800020c: f000 f806 bl 800021c <__aeabi_idiv0>
8000210: bd02 pop {r1, pc}
8000212: 46c0 nop ; (mov r8, r8)
08000214 <__aeabi_uidivmod>:
8000214: 2900 cmp r1, #0
8000216: d0f7 beq.n 8000208 <__udivsi3+0x100>
8000218: e776 b.n 8000108 <__udivsi3>
800021a: 4770 bx lr
0800021c <__aeabi_idiv0>:
800021c: 4770 bx lr
800021e: 46c0 nop ; (mov r8, r8)
08000220 <HTPA_Init>:
* configuration to the respective registers.
* Afterwards the sensor is in idle and ready for conversion.
*
* @param *hi2c: Pointer to I2C Handle
*/
void HTPA_Init(I2C_HandleTypeDef *hi2c){
8000220: b580 push {r7, lr}
8000222: b082 sub sp, #8
8000224: af00 add r7, sp, #0
8000226: 6078 str r0, [r7, #4]
i2c_handle = *hi2c;
8000228: 4a17 ldr r2, [pc, #92] ; (8000288 <HTPA_Init+0x68>)
800022a: 687b ldr r3, [r7, #4]
800022c: 0010 movs r0, r2
800022e: 0019 movs r1, r3
8000230: 2354 movs r3, #84 ; 0x54
8000232: 001a movs r2, r3
8000234: f002 f932 bl 800249c <memcpy>
// Berechnung für clk / sample aus I2C parametern?
HTPA_WriteRegister(HTPA_SENSOR_CONFIG, 0x01); // wakeup
8000238: 2101 movs r1, #1
800023a: 2001 movs r0, #1
800023c: f000 f826 bl 800028c <HTPA_WriteRegister>
HTPA_WriteRegister(HTPA_SENSOR_TRIM_1, 0x0C);
8000240: 210c movs r1, #12
8000242: 2003 movs r0, #3
8000244: f000 f822 bl 800028c <HTPA_WriteRegister>
HTPA_WriteRegister(HTPA_SENSOR_TRIM_2, 0x0C);
8000248: 210c movs r1, #12
800024a: 2004 movs r0, #4
800024c: f000 f81e bl 800028c <HTPA_WriteRegister>
HTPA_WriteRegister(HTPA_SENSOR_TRIM_3, 0x0C);
8000250: 210c movs r1, #12
8000252: 2005 movs r0, #5
8000254: f000 f81a bl 800028c <HTPA_WriteRegister>
HTPA_WriteRegister(HTPA_SENSOR_TRIM_4, 0x14);
8000258: 2114 movs r1, #20
800025a: 2006 movs r0, #6
800025c: f000 f816 bl 800028c <HTPA_WriteRegister>
HTPA_WriteRegister(HTPA_SENSOR_TRIM_5, 0x0C);
8000260: 210c movs r1, #12
8000262: 2007 movs r0, #7
8000264: f000 f812 bl 800028c <HTPA_WriteRegister>
HTPA_WriteRegister(HTPA_SENSOR_TRIM_6, 0x0C);
8000268: 210c movs r1, #12
800026a: 2008 movs r0, #8
800026c: f000 f80e bl 800028c <HTPA_WriteRegister>
HTPA_WriteRegister(HTPA_SENSOR_TRIM_7, 0x88);
8000270: 2188 movs r1, #136 ; 0x88
8000272: 2009 movs r0, #9
8000274: f000 f80a bl 800028c <HTPA_WriteRegister>
HTPA_WriteRegister(HTPA_SENSOR_CONFIG, 0x09); // start sensor
8000278: 2109 movs r1, #9
800027a: 2001 movs r0, #1
800027c: f000 f806 bl 800028c <HTPA_WriteRegister>
}
8000280: 46c0 nop ; (mov r8, r8)
8000282: 46bd mov sp, r7
8000284: b002 add sp, #8
8000286: bd80 pop {r7, pc}
8000288: 20000028 .word 0x20000028
0800028c <HTPA_WriteRegister>:
* description
*
* @param register_address: address of register
* @param byte: byte to be written to register
*/
void HTPA_WriteRegister(uint8_t register_address, uint8_t byte){
800028c: b5b0 push {r4, r5, r7, lr}
800028e: b086 sub sp, #24
8000290: af02 add r7, sp, #8
8000292: 0002 movs r2, r0
8000294: 1dfb adds r3, r7, #7
8000296: 701a strb r2, [r3, #0]
8000298: 1dbb adds r3, r7, #6
800029a: 1c0a adds r2, r1, #0
800029c: 701a strb r2, [r3, #0]
uint8_t i2c_data = register_address;
800029e: 200e movs r0, #14
80002a0: 183b adds r3, r7, r0
80002a2: 1dfa adds r2, r7, #7
80002a4: 7812 ldrb r2, [r2, #0]
80002a6: 701a strb r2, [r3, #0]
uint8_t i2c_address = (HTPA_SENSOR_ADDRESS << 1);
80002a8: 240f movs r4, #15
80002aa: 193b adds r3, r7, r4
80002ac: 2234 movs r2, #52 ; 0x34
80002ae: 701a strb r2, [r3, #0]
i2c_address &= 0xFE; // set read/write bit to write (0)
80002b0: 193b adds r3, r7, r4
80002b2: 193a adds r2, r7, r4
80002b4: 7812 ldrb r2, [r2, #0]
80002b6: 2101 movs r1, #1
80002b8: 438a bics r2, r1
80002ba: 701a strb r2, [r3, #0]
HAL_I2C_Master_Transmit(&i2c_handle, i2c_address, &i2c_data, 1, I2C_MAX_DELAY);
80002bc: 193b adds r3, r7, r4
80002be: 781b ldrb r3, [r3, #0]
80002c0: b299 uxth r1, r3
80002c2: 0005 movs r5, r0
80002c4: 183a adds r2, r7, r0
80002c6: 480d ldr r0, [pc, #52] ; (80002fc <HTPA_WriteRegister+0x70>)
80002c8: 2301 movs r3, #1
80002ca: 425b negs r3, r3
80002cc: 9300 str r3, [sp, #0]
80002ce: 2301 movs r3, #1
80002d0: f000 fda2 bl 8000e18 <HAL_I2C_Master_Transmit>
i2c_data = byte;
80002d4: 0028 movs r0, r5
80002d6: 183b adds r3, r7, r0
80002d8: 1dba adds r2, r7, #6
80002da: 7812 ldrb r2, [r2, #0]
80002dc: 701a strb r2, [r3, #0]
HAL_I2C_Master_Transmit(&i2c_handle, i2c_address, &i2c_data, 1, I2C_MAX_DELAY);
80002de: 193b adds r3, r7, r4
80002e0: 781b ldrb r3, [r3, #0]
80002e2: b299 uxth r1, r3
80002e4: 183a adds r2, r7, r0
80002e6: 4805 ldr r0, [pc, #20] ; (80002fc <HTPA_WriteRegister+0x70>)
80002e8: 2301 movs r3, #1
80002ea: 425b negs r3, r3
80002ec: 9300 str r3, [sp, #0]
80002ee: 2301 movs r3, #1
80002f0: f000 fd92 bl 8000e18 <HAL_I2C_Master_Transmit>
}
80002f4: 46c0 nop ; (mov r8, r8)
80002f6: 46bd mov sp, r7
80002f8: b004 add sp, #16
80002fa: bdb0 pop {r4, r5, r7, pc}
80002fc: 20000028 .word 0x20000028
08000300 <HTPA_GetStatus>:
* Reads the sensors status register and stores the information in
* the HTPA_Statsu structure.
*
* @return HTPA_Status: status register struct
*/
HTPA_Status HTPA_GetStatus(void){
8000300: b590 push {r4, r7, lr}
8000302: b087 sub sp, #28
8000304: af02 add r7, sp, #8
HAL_StatusTypeDef i2c_status;
HTPA_Status status_return;
uint8_t i2c_data = HTPA_SENSOR_STATUS;
8000306: 1cfb adds r3, r7, #3
8000308: 2202 movs r2, #2
800030a: 701a strb r2, [r3, #0]
uint8_t i2c_address = (HTPA_SENSOR_ADDRESS << 1);
800030c: 240f movs r4, #15
800030e: 193b adds r3, r7, r4
8000310: 2234 movs r2, #52 ; 0x34
8000312: 701a strb r2, [r3, #0]
uint8_t i2c_readData = 0;
8000314: 1cbb adds r3, r7, #2
8000316: 2200 movs r2, #0
8000318: 701a strb r2, [r3, #0]
i2c_address &= 0xFE; // set read/write bit 0 to write (0)
800031a: 193b adds r3, r7, r4
800031c: 193a adds r2, r7, r4
800031e: 7812 ldrb r2, [r2, #0]
8000320: 2101 movs r1, #1
8000322: 438a bics r2, r1
8000324: 701a strb r2, [r3, #0]
HAL_I2C_Master_Transmit(&i2c_handle, i2c_address, &i2c_data, 1, I2C_MAX_DELAY);
8000326: 193b adds r3, r7, r4
8000328: 781b ldrb r3, [r3, #0]
800032a: b299 uxth r1, r3
800032c: 1cfa adds r2, r7, #3
800032e: 4831 ldr r0, [pc, #196] ; (80003f4 <HTPA_GetStatus+0xf4>)
8000330: 2301 movs r3, #1
8000332: 425b negs r3, r3
8000334: 9300 str r3, [sp, #0]
8000336: 2301 movs r3, #1
8000338: f000 fd6e bl 8000e18 <HAL_I2C_Master_Transmit>
i2c_address |= 0x01; // set read/write bit 0 to read (1)
800033c: 193b adds r3, r7, r4
800033e: 193a adds r2, r7, r4
8000340: 7812 ldrb r2, [r2, #0]
8000342: 2101 movs r1, #1
8000344: 430a orrs r2, r1
8000346: 701a strb r2, [r3, #0]
i2c_status = HAL_I2C_Master_Receive(&i2c_handle, i2c_address, &i2c_readData, 1, I2C_MAX_DELAY);
8000348: 193b adds r3, r7, r4
800034a: 781b ldrb r3, [r3, #0]
800034c: b299 uxth r1, r3
800034e: 230e movs r3, #14
8000350: 18fc adds r4, r7, r3
8000352: 1cba adds r2, r7, #2
8000354: 4827 ldr r0, [pc, #156] ; (80003f4 <HTPA_GetStatus+0xf4>)
8000356: 2301 movs r3, #1
8000358: 425b negs r3, r3
800035a: 9300 str r3, [sp, #0]
800035c: 2301 movs r3, #1
800035e: f000 fe63 bl 8001028 <HAL_I2C_Master_Receive>
8000362: 0003 movs r3, r0
8000364: 7023 strb r3, [r4, #0]
status_return.block = (i2c_readData >> 4) && 0xFC;
8000366: 1cbb adds r3, r7, #2
8000368: 781b ldrb r3, [r3, #0]
800036a: 091b lsrs r3, r3, #4
800036c: b2db uxtb r3, r3
800036e: 1e5a subs r2, r3, #1
8000370: 4193 sbcs r3, r2
8000372: b2db uxtb r3, r3
8000374: 001a movs r2, r3
8000376: 1d3b adds r3, r7, #4
8000378: 701a strb r2, [r3, #0]
status_return.vdd_meas = (i2c_readData >> 2) && 0xFE;
800037a: 1cbb adds r3, r7, #2
800037c: 781b ldrb r3, [r3, #0]
800037e: 089b lsrs r3, r3, #2
8000380: b2db uxtb r3, r3
8000382: 1e5a subs r2, r3, #1
8000384: 4193 sbcs r3, r2
8000386: b2da uxtb r2, r3
8000388: 1d3b adds r3, r7, #4
800038a: 705a strb r2, [r3, #1]
status_return.blind = (i2c_readData >> 1) && 0xFE;
800038c: 1cbb adds r3, r7, #2
800038e: 781b ldrb r3, [r3, #0]
8000390: 085b lsrs r3, r3, #1
8000392: b2db uxtb r3, r3
8000394: 1e5a subs r2, r3, #1
8000396: 4193 sbcs r3, r2
8000398: b2da uxtb r2, r3
800039a: 1d3b adds r3, r7, #4
800039c: 709a strb r2, [r3, #2]
status_return.eoc = i2c_readData && 0xFE;
800039e: 1cbb adds r3, r7, #2
80003a0: 781b ldrb r3, [r3, #0]
80003a2: 1e5a subs r2, r3, #1
80003a4: 4193 sbcs r3, r2
80003a6: b2da uxtb r2, r3
80003a8: 1d3b adds r3, r7, #4
80003aa: 70da strb r2, [r3, #3]
return status_return;
80003ac: 2108 movs r1, #8
80003ae: 187b adds r3, r7, r1
80003b0: 1d3a adds r2, r7, #4
80003b2: 6812 ldr r2, [r2, #0]
80003b4: 601a str r2, [r3, #0]
80003b6: 187a adds r2, r7, r1
80003b8: 2300 movs r3, #0
80003ba: 7811 ldrb r1, [r2, #0]
80003bc: 20ff movs r0, #255 ; 0xff
80003be: 4001 ands r1, r0
80003c0: 20ff movs r0, #255 ; 0xff
80003c2: 4383 bics r3, r0
80003c4: 430b orrs r3, r1
80003c6: 7851 ldrb r1, [r2, #1]
80003c8: 20ff movs r0, #255 ; 0xff
80003ca: 4001 ands r1, r0
80003cc: 0209 lsls r1, r1, #8
80003ce: 480a ldr r0, [pc, #40] ; (80003f8 <HTPA_GetStatus+0xf8>)
80003d0: 4003 ands r3, r0
80003d2: 430b orrs r3, r1
80003d4: 7891 ldrb r1, [r2, #2]
80003d6: 20ff movs r0, #255 ; 0xff
80003d8: 4001 ands r1, r0
80003da: 0409 lsls r1, r1, #16
80003dc: 4807 ldr r0, [pc, #28] ; (80003fc <HTPA_GetStatus+0xfc>)
80003de: 4003 ands r3, r0
80003e0: 430b orrs r3, r1
80003e2: 78d2 ldrb r2, [r2, #3]
80003e4: 0612 lsls r2, r2, #24
80003e6: 021b lsls r3, r3, #8
80003e8: 0a1b lsrs r3, r3, #8
80003ea: 4313 orrs r3, r2
}
80003ec: 0018 movs r0, r3
80003ee: 46bd mov sp, r7
80003f0: b005 add sp, #20
80003f2: bd90 pop {r4, r7, pc}
80003f4: 20000028 .word 0x20000028
80003f8: ffff00ff .word 0xffff00ff
80003fc: ff00ffff .word 0xff00ffff
08000400 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000400: b580 push {r7, lr}
8000402: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000404: f000 f9ce bl 80007a4 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000408: f000 f818 bl 800043c <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
800040c: f000 f8c0 bl 8000590 <MX_GPIO_Init>
MX_I2C1_Init();
8000410: f000 f876 bl 8000500 <MX_I2C1_Init>
/* USER CODE BEGIN 2 */
HTPA_Init(&hi2c1);
8000414: 4b07 ldr r3, [pc, #28] ; (8000434 <main+0x34>)
8000416: 0018 movs r0, r3
8000418: f7ff ff02 bl 8000220 <HTPA_Init>
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
temp_status = HTPA_GetStatus();
800041c: f7ff ff70 bl 8000300 <HTPA_GetStatus>
8000420: 0003 movs r3, r0
8000422: 001a movs r2, r3
8000424: 4b04 ldr r3, [pc, #16] ; (8000438 <main+0x38>)
8000426: 601a str r2, [r3, #0]
HAL_Delay(1000);
8000428: 23fa movs r3, #250 ; 0xfa
800042a: 009b lsls r3, r3, #2
800042c: 0018 movs r0, r3
800042e: f000 fa1d bl 800086c <HAL_Delay>
temp_status = HTPA_GetStatus();
8000432: e7f3 b.n 800041c <main+0x1c>
8000434: 2000007c .word 0x2000007c
8000438: 200000d0 .word 0x200000d0
0800043c <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
800043c: b590 push {r4, r7, lr}
800043e: b099 sub sp, #100 ; 0x64
8000440: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000442: 242c movs r4, #44 ; 0x2c
8000444: 193b adds r3, r7, r4
8000446: 0018 movs r0, r3
8000448: 2334 movs r3, #52 ; 0x34
800044a: 001a movs r2, r3
800044c: 2100 movs r1, #0
800044e: f002 f82e bl 80024ae <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000452: 231c movs r3, #28
8000454: 18fb adds r3, r7, r3
8000456: 0018 movs r0, r3
8000458: 2310 movs r3, #16
800045a: 001a movs r2, r3
800045c: 2100 movs r1, #0
800045e: f002 f826 bl 80024ae <memset>
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8000462: 1d3b adds r3, r7, #4
8000464: 0018 movs r0, r3
8000466: 2318 movs r3, #24
8000468: 001a movs r2, r3
800046a: 2100 movs r1, #0
800046c: f002 f81f bl 80024ae <memset>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
8000470: 0021 movs r1, r4
8000472: 187b adds r3, r7, r1
8000474: 2202 movs r2, #2
8000476: 601a str r2, [r3, #0]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000478: 187b adds r3, r7, r1
800047a: 2201 movs r2, #1
800047c: 60da str r2, [r3, #12]
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
800047e: 187b adds r3, r7, r1
8000480: 2210 movs r2, #16
8000482: 611a str r2, [r3, #16]
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000484: 187b adds r3, r7, r1
8000486: 2202 movs r2, #2
8000488: 625a str r2, [r3, #36] ; 0x24
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
800048a: 187b adds r3, r7, r1
800048c: 2280 movs r2, #128 ; 0x80
800048e: 0212 lsls r2, r2, #8
8000490: 629a str r2, [r3, #40] ; 0x28
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL2;
8000492: 187b adds r3, r7, r1
8000494: 2200 movs r2, #0
8000496: 62da str r2, [r3, #44] ; 0x2c
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
8000498: 187b adds r3, r7, r1
800049a: 2200 movs r2, #0
800049c: 631a str r2, [r3, #48] ; 0x30
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
800049e: 187b adds r3, r7, r1
80004a0: 0018 movs r0, r3
80004a2: f001 fa17 bl 80018d4 <HAL_RCC_OscConfig>
80004a6: 1e03 subs r3, r0, #0
80004a8: d001 beq.n 80004ae <SystemClock_Config+0x72>
{
Error_Handler();
80004aa: f000 f8a5 bl 80005f8 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80004ae: 211c movs r1, #28
80004b0: 187b adds r3, r7, r1
80004b2: 2207 movs r2, #7
80004b4: 601a str r2, [r3, #0]
|RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
80004b6: 187b adds r3, r7, r1
80004b8: 2202 movs r2, #2
80004ba: 605a str r2, [r3, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80004bc: 187b adds r3, r7, r1
80004be: 2200 movs r2, #0
80004c0: 609a str r2, [r3, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
80004c2: 187b adds r3, r7, r1
80004c4: 2200 movs r2, #0
80004c6: 60da str r2, [r3, #12]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
80004c8: 187b adds r3, r7, r1
80004ca: 2100 movs r1, #0
80004cc: 0018 movs r0, r3
80004ce: f001 fd87 bl 8001fe0 <HAL_RCC_ClockConfig>
80004d2: 1e03 subs r3, r0, #0
80004d4: d001 beq.n 80004da <SystemClock_Config+0x9e>
{
Error_Handler();
80004d6: f000 f88f bl 80005f8 <Error_Handler>
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
80004da: 1d3b adds r3, r7, #4
80004dc: 2220 movs r2, #32
80004de: 601a str r2, [r3, #0]
PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_SYSCLK;
80004e0: 1d3b adds r3, r7, #4
80004e2: 2210 movs r2, #16
80004e4: 60da str r2, [r3, #12]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
80004e6: 1d3b adds r3, r7, #4
80004e8: 0018 movs r0, r3
80004ea: f001 fec5 bl 8002278 <HAL_RCCEx_PeriphCLKConfig>
80004ee: 1e03 subs r3, r0, #0
80004f0: d001 beq.n 80004f6 <SystemClock_Config+0xba>
{
Error_Handler();
80004f2: f000 f881 bl 80005f8 <Error_Handler>
}
}
80004f6: 46c0 nop ; (mov r8, r8)
80004f8: 46bd mov sp, r7
80004fa: b019 add sp, #100 ; 0x64
80004fc: bd90 pop {r4, r7, pc}
...
08000500 <MX_I2C1_Init>:
* @brief I2C1 Initialization Function
* @param None
* @retval None
*/
static void MX_I2C1_Init(void)
{
8000500: b580 push {r7, lr}
8000502: af00 add r7, sp, #0
/* USER CODE END I2C1_Init 0 */
/* USER CODE BEGIN I2C1_Init 1 */
/* USER CODE END I2C1_Init 1 */
hi2c1.Instance = I2C1;
8000504: 4b1f ldr r3, [pc, #124] ; (8000584 <MX_I2C1_Init+0x84>)
8000506: 4a20 ldr r2, [pc, #128] ; (8000588 <MX_I2C1_Init+0x88>)
8000508: 601a str r2, [r3, #0]
hi2c1.Init.Timing = 0x00000107;
800050a: 4b1e ldr r3, [pc, #120] ; (8000584 <MX_I2C1_Init+0x84>)
800050c: 2208 movs r2, #8
800050e: 32ff adds r2, #255 ; 0xff
8000510: 605a str r2, [r3, #4]
hi2c1.Init.OwnAddress1 = 0;
8000512: 4b1c ldr r3, [pc, #112] ; (8000584 <MX_I2C1_Init+0x84>)
8000514: 2200 movs r2, #0
8000516: 609a str r2, [r3, #8]
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
8000518: 4b1a ldr r3, [pc, #104] ; (8000584 <MX_I2C1_Init+0x84>)
800051a: 2201 movs r2, #1
800051c: 60da str r2, [r3, #12]
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
800051e: 4b19 ldr r3, [pc, #100] ; (8000584 <MX_I2C1_Init+0x84>)
8000520: 2200 movs r2, #0
8000522: 611a str r2, [r3, #16]
hi2c1.Init.OwnAddress2 = 0;
8000524: 4b17 ldr r3, [pc, #92] ; (8000584 <MX_I2C1_Init+0x84>)
8000526: 2200 movs r2, #0
8000528: 615a str r2, [r3, #20]
hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
800052a: 4b16 ldr r3, [pc, #88] ; (8000584 <MX_I2C1_Init+0x84>)
800052c: 2200 movs r2, #0
800052e: 619a str r2, [r3, #24]
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
8000530: 4b14 ldr r3, [pc, #80] ; (8000584 <MX_I2C1_Init+0x84>)
8000532: 2200 movs r2, #0
8000534: 61da str r2, [r3, #28]
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
8000536: 4b13 ldr r3, [pc, #76] ; (8000584 <MX_I2C1_Init+0x84>)
8000538: 2200 movs r2, #0
800053a: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
800053c: 4b11 ldr r3, [pc, #68] ; (8000584 <MX_I2C1_Init+0x84>)
800053e: 0018 movs r0, r3
8000540: f000 fbd4 bl 8000cec <HAL_I2C_Init>
8000544: 1e03 subs r3, r0, #0
8000546: d001 beq.n 800054c <MX_I2C1_Init+0x4c>
{
Error_Handler();
8000548: f000 f856 bl 80005f8 <Error_Handler>
}
/** Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
800054c: 4b0d ldr r3, [pc, #52] ; (8000584 <MX_I2C1_Init+0x84>)
800054e: 2100 movs r1, #0
8000550: 0018 movs r0, r3
8000552: f001 f927 bl 80017a4 <HAL_I2CEx_ConfigAnalogFilter>
8000556: 1e03 subs r3, r0, #0
8000558: d001 beq.n 800055e <MX_I2C1_Init+0x5e>
{
Error_Handler();
800055a: f000 f84d bl 80005f8 <Error_Handler>
}
/** Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
800055e: 4b09 ldr r3, [pc, #36] ; (8000584 <MX_I2C1_Init+0x84>)
8000560: 2100 movs r1, #0
8000562: 0018 movs r0, r3
8000564: f001 f96a bl 800183c <HAL_I2CEx_ConfigDigitalFilter>
8000568: 1e03 subs r3, r0, #0
800056a: d001 beq.n 8000570 <MX_I2C1_Init+0x70>
{
Error_Handler();
800056c: f000 f844 bl 80005f8 <Error_Handler>
}
/** I2C Fast mode Plus enable
*/
__HAL_SYSCFG_FASTMODEPLUS_ENABLE(I2C_FASTMODEPLUS_I2C1);
8000570: 4b06 ldr r3, [pc, #24] ; (800058c <MX_I2C1_Init+0x8c>)
8000572: 681a ldr r2, [r3, #0]
8000574: 4b05 ldr r3, [pc, #20] ; (800058c <MX_I2C1_Init+0x8c>)
8000576: 2180 movs r1, #128 ; 0x80
8000578: 0349 lsls r1, r1, #13
800057a: 430a orrs r2, r1
800057c: 601a str r2, [r3, #0]
/* USER CODE BEGIN I2C1_Init 2 */
/* USER CODE END I2C1_Init 2 */
}
800057e: 46c0 nop ; (mov r8, r8)
8000580: 46bd mov sp, r7
8000582: bd80 pop {r7, pc}
8000584: 2000007c .word 0x2000007c
8000588: 40005400 .word 0x40005400
800058c: 40010000 .word 0x40010000
08000590 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000590: b580 push {r7, lr}
8000592: b084 sub sp, #16
8000594: af00 add r7, sp, #0
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOF_CLK_ENABLE();
8000596: 4b17 ldr r3, [pc, #92] ; (80005f4 <MX_GPIO_Init+0x64>)
8000598: 695a ldr r2, [r3, #20]
800059a: 4b16 ldr r3, [pc, #88] ; (80005f4 <MX_GPIO_Init+0x64>)
800059c: 2180 movs r1, #128 ; 0x80
800059e: 03c9 lsls r1, r1, #15
80005a0: 430a orrs r2, r1
80005a2: 615a str r2, [r3, #20]
80005a4: 4b13 ldr r3, [pc, #76] ; (80005f4 <MX_GPIO_Init+0x64>)
80005a6: 695a ldr r2, [r3, #20]
80005a8: 2380 movs r3, #128 ; 0x80
80005aa: 03db lsls r3, r3, #15
80005ac: 4013 ands r3, r2
80005ae: 60fb str r3, [r7, #12]
80005b0: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
80005b2: 4b10 ldr r3, [pc, #64] ; (80005f4 <MX_GPIO_Init+0x64>)
80005b4: 695a ldr r2, [r3, #20]
80005b6: 4b0f ldr r3, [pc, #60] ; (80005f4 <MX_GPIO_Init+0x64>)
80005b8: 2180 movs r1, #128 ; 0x80
80005ba: 0289 lsls r1, r1, #10
80005bc: 430a orrs r2, r1
80005be: 615a str r2, [r3, #20]
80005c0: 4b0c ldr r3, [pc, #48] ; (80005f4 <MX_GPIO_Init+0x64>)
80005c2: 695a ldr r2, [r3, #20]
80005c4: 2380 movs r3, #128 ; 0x80
80005c6: 029b lsls r3, r3, #10
80005c8: 4013 ands r3, r2
80005ca: 60bb str r3, [r7, #8]
80005cc: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
80005ce: 4b09 ldr r3, [pc, #36] ; (80005f4 <MX_GPIO_Init+0x64>)
80005d0: 695a ldr r2, [r3, #20]
80005d2: 4b08 ldr r3, [pc, #32] ; (80005f4 <MX_GPIO_Init+0x64>)
80005d4: 2180 movs r1, #128 ; 0x80
80005d6: 02c9 lsls r1, r1, #11
80005d8: 430a orrs r2, r1
80005da: 615a str r2, [r3, #20]
80005dc: 4b05 ldr r3, [pc, #20] ; (80005f4 <MX_GPIO_Init+0x64>)
80005de: 695a ldr r2, [r3, #20]
80005e0: 2380 movs r3, #128 ; 0x80
80005e2: 02db lsls r3, r3, #11
80005e4: 4013 ands r3, r2
80005e6: 607b str r3, [r7, #4]
80005e8: 687b ldr r3, [r7, #4]
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
80005ea: 46c0 nop ; (mov r8, r8)
80005ec: 46bd mov sp, r7
80005ee: b004 add sp, #16
80005f0: bd80 pop {r7, pc}
80005f2: 46c0 nop ; (mov r8, r8)
80005f4: 40021000 .word 0x40021000
080005f8 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80005f8: b580 push {r7, lr}
80005fa: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80005fc: b672 cpsid i
}
80005fe: 46c0 nop ; (mov r8, r8)
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000600: e7fe b.n 8000600 <Error_Handler+0x8>
...
08000604 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000604: b580 push {r7, lr}
8000606: b082 sub sp, #8
8000608: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
800060a: 4b0f ldr r3, [pc, #60] ; (8000648 <HAL_MspInit+0x44>)
800060c: 699a ldr r2, [r3, #24]
800060e: 4b0e ldr r3, [pc, #56] ; (8000648 <HAL_MspInit+0x44>)
8000610: 2101 movs r1, #1
8000612: 430a orrs r2, r1
8000614: 619a str r2, [r3, #24]
8000616: 4b0c ldr r3, [pc, #48] ; (8000648 <HAL_MspInit+0x44>)
8000618: 699b ldr r3, [r3, #24]
800061a: 2201 movs r2, #1
800061c: 4013 ands r3, r2
800061e: 607b str r3, [r7, #4]
8000620: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8000622: 4b09 ldr r3, [pc, #36] ; (8000648 <HAL_MspInit+0x44>)
8000624: 69da ldr r2, [r3, #28]
8000626: 4b08 ldr r3, [pc, #32] ; (8000648 <HAL_MspInit+0x44>)
8000628: 2180 movs r1, #128 ; 0x80
800062a: 0549 lsls r1, r1, #21
800062c: 430a orrs r2, r1
800062e: 61da str r2, [r3, #28]
8000630: 4b05 ldr r3, [pc, #20] ; (8000648 <HAL_MspInit+0x44>)
8000632: 69da ldr r2, [r3, #28]
8000634: 2380 movs r3, #128 ; 0x80
8000636: 055b lsls r3, r3, #21
8000638: 4013 ands r3, r2
800063a: 603b str r3, [r7, #0]
800063c: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800063e: 46c0 nop ; (mov r8, r8)
8000640: 46bd mov sp, r7
8000642: b002 add sp, #8
8000644: bd80 pop {r7, pc}
8000646: 46c0 nop ; (mov r8, r8)
8000648: 40021000 .word 0x40021000
0800064c <HAL_I2C_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
800064c: b590 push {r4, r7, lr}
800064e: b08b sub sp, #44 ; 0x2c
8000650: af00 add r7, sp, #0
8000652: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000654: 2414 movs r4, #20
8000656: 193b adds r3, r7, r4
8000658: 0018 movs r0, r3
800065a: 2314 movs r3, #20
800065c: 001a movs r2, r3
800065e: 2100 movs r1, #0
8000660: f001 ff25 bl 80024ae <memset>
if(hi2c->Instance==I2C1)
8000664: 687b ldr r3, [r7, #4]
8000666: 681b ldr r3, [r3, #0]
8000668: 4a1c ldr r2, [pc, #112] ; (80006dc <HAL_I2C_MspInit+0x90>)
800066a: 4293 cmp r3, r2
800066c: d131 bne.n 80006d2 <HAL_I2C_MspInit+0x86>
{
/* USER CODE BEGIN I2C1_MspInit 0 */
/* USER CODE END I2C1_MspInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
800066e: 4b1c ldr r3, [pc, #112] ; (80006e0 <HAL_I2C_MspInit+0x94>)
8000670: 695a ldr r2, [r3, #20]
8000672: 4b1b ldr r3, [pc, #108] ; (80006e0 <HAL_I2C_MspInit+0x94>)
8000674: 2180 movs r1, #128 ; 0x80
8000676: 02c9 lsls r1, r1, #11
8000678: 430a orrs r2, r1
800067a: 615a str r2, [r3, #20]
800067c: 4b18 ldr r3, [pc, #96] ; (80006e0 <HAL_I2C_MspInit+0x94>)
800067e: 695a ldr r2, [r3, #20]
8000680: 2380 movs r3, #128 ; 0x80
8000682: 02db lsls r3, r3, #11
8000684: 4013 ands r3, r2
8000686: 613b str r3, [r7, #16]
8000688: 693b ldr r3, [r7, #16]
/**I2C1 GPIO Configuration
PB6 ------> I2C1_SCL
PB7 ------> I2C1_SDA
*/
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
800068a: 0021 movs r1, r4
800068c: 187b adds r3, r7, r1
800068e: 22c0 movs r2, #192 ; 0xc0
8000690: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8000692: 187b adds r3, r7, r1
8000694: 2212 movs r2, #18
8000696: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000698: 187b adds r3, r7, r1
800069a: 2200 movs r2, #0
800069c: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
800069e: 187b adds r3, r7, r1
80006a0: 2203 movs r2, #3
80006a2: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF1_I2C1;
80006a4: 187b adds r3, r7, r1
80006a6: 2201 movs r2, #1
80006a8: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80006aa: 187b adds r3, r7, r1
80006ac: 4a0d ldr r2, [pc, #52] ; (80006e4 <HAL_I2C_MspInit+0x98>)
80006ae: 0019 movs r1, r3
80006b0: 0010 movs r0, r2
80006b2: f000 f9b3 bl 8000a1c <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_I2C1_CLK_ENABLE();
80006b6: 4b0a ldr r3, [pc, #40] ; (80006e0 <HAL_I2C_MspInit+0x94>)
80006b8: 69da ldr r2, [r3, #28]
80006ba: 4b09 ldr r3, [pc, #36] ; (80006e0 <HAL_I2C_MspInit+0x94>)
80006bc: 2180 movs r1, #128 ; 0x80
80006be: 0389 lsls r1, r1, #14
80006c0: 430a orrs r2, r1
80006c2: 61da str r2, [r3, #28]
80006c4: 4b06 ldr r3, [pc, #24] ; (80006e0 <HAL_I2C_MspInit+0x94>)
80006c6: 69da ldr r2, [r3, #28]
80006c8: 2380 movs r3, #128 ; 0x80
80006ca: 039b lsls r3, r3, #14
80006cc: 4013 ands r3, r2
80006ce: 60fb str r3, [r7, #12]
80006d0: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN I2C1_MspInit 1 */
/* USER CODE END I2C1_MspInit 1 */
}
}
80006d2: 46c0 nop ; (mov r8, r8)
80006d4: 46bd mov sp, r7
80006d6: b00b add sp, #44 ; 0x2c
80006d8: bd90 pop {r4, r7, pc}
80006da: 46c0 nop ; (mov r8, r8)
80006dc: 40005400 .word 0x40005400
80006e0: 40021000 .word 0x40021000
80006e4: 48000400 .word 0x48000400
080006e8 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
80006e8: b580 push {r7, lr}
80006ea: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
80006ec: e7fe b.n 80006ec <NMI_Handler+0x4>
080006ee <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
80006ee: b580 push {r7, lr}
80006f0: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
80006f2: e7fe b.n 80006f2 <HardFault_Handler+0x4>
080006f4 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
80006f4: b580 push {r7, lr}
80006f6: af00 add r7, sp, #0
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
80006f8: 46c0 nop ; (mov r8, r8)
80006fa: 46bd mov sp, r7
80006fc: bd80 pop {r7, pc}
080006fe <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
80006fe: b580 push {r7, lr}
8000700: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000702: 46c0 nop ; (mov r8, r8)
8000704: 46bd mov sp, r7
8000706: bd80 pop {r7, pc}
08000708 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000708: b580 push {r7, lr}
800070a: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
800070c: f000 f892 bl 8000834 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000710: 46c0 nop ; (mov r8, r8)
8000712: 46bd mov sp, r7
8000714: bd80 pop {r7, pc}
08000716 <SystemInit>:
* @brief Setup the microcontroller system
* @param None
* @retval None
*/
void SystemInit(void)
{
8000716: b580 push {r7, lr}
8000718: af00 add r7, sp, #0
before branch to main program. This call is made inside
the "startup_stm32f0xx.s" file.
User can setups the default system clock (System clock source, PLL Multiplier
and Divider factors, AHB/APBx prescalers and Flash settings).
*/
}
800071a: 46c0 nop ; (mov r8, r8)
800071c: 46bd mov sp, r7
800071e: bd80 pop {r7, pc}
08000720 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
8000720: 4813 ldr r0, [pc, #76] ; (8000770 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
8000722: 4685 mov sp, r0
/* Call the clock system initialization function.*/
bl SystemInit
8000724: f7ff fff7 bl 8000716 <SystemInit>
/*Check if boot space corresponds to test memory*/
LDR R0,=0x00000004
8000728: 4812 ldr r0, [pc, #72] ; (8000774 <LoopForever+0x6>)
LDR R1, [R0]
800072a: 6801 ldr r1, [r0, #0]
LSRS R1, R1, #24
800072c: 0e09 lsrs r1, r1, #24
LDR R2,=0x1F
800072e: 4a12 ldr r2, [pc, #72] ; (8000778 <LoopForever+0xa>)
CMP R1, R2
8000730: 4291 cmp r1, r2
BNE ApplicationStart
8000732: d105 bne.n 8000740 <ApplicationStart>
/*SYSCFG clock enable*/
LDR R0,=0x40021018
8000734: 4811 ldr r0, [pc, #68] ; (800077c <LoopForever+0xe>)
LDR R1,=0x00000001
8000736: 4912 ldr r1, [pc, #72] ; (8000780 <LoopForever+0x12>)
STR R1, [R0]
8000738: 6001 str r1, [r0, #0]
/*Set CFGR1 register with flash memory remap at address 0*/
LDR R0,=0x40010000
800073a: 4812 ldr r0, [pc, #72] ; (8000784 <LoopForever+0x16>)
LDR R1,=0x00000000
800073c: 4912 ldr r1, [pc, #72] ; (8000788 <LoopForever+0x1a>)
STR R1, [R0]
800073e: 6001 str r1, [r0, #0]
08000740 <ApplicationStart>:
ApplicationStart:
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000740: 4812 ldr r0, [pc, #72] ; (800078c <LoopForever+0x1e>)
ldr r1, =_edata
8000742: 4913 ldr r1, [pc, #76] ; (8000790 <LoopForever+0x22>)
ldr r2, =_sidata
8000744: 4a13 ldr r2, [pc, #76] ; (8000794 <LoopForever+0x26>)
movs r3, #0
8000746: 2300 movs r3, #0
b LoopCopyDataInit
8000748: e002 b.n 8000750 <LoopCopyDataInit>
0800074a <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
800074a: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
800074c: 50c4 str r4, [r0, r3]
adds r3, r3, #4
800074e: 3304 adds r3, #4
08000750 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000750: 18c4 adds r4, r0, r3
cmp r4, r1
8000752: 428c cmp r4, r1
bcc CopyDataInit
8000754: d3f9 bcc.n 800074a <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000756: 4a10 ldr r2, [pc, #64] ; (8000798 <LoopForever+0x2a>)
ldr r4, =_ebss
8000758: 4c10 ldr r4, [pc, #64] ; (800079c <LoopForever+0x2e>)
movs r3, #0
800075a: 2300 movs r3, #0
b LoopFillZerobss
800075c: e001 b.n 8000762 <LoopFillZerobss>
0800075e <FillZerobss>:
FillZerobss:
str r3, [r2]
800075e: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000760: 3204 adds r2, #4
08000762 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8000762: 42a2 cmp r2, r4
bcc FillZerobss
8000764: d3fb bcc.n 800075e <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8000766: f001 fe75 bl 8002454 <__libc_init_array>
/* Call the application's entry point.*/
bl main
800076a: f7ff fe49 bl 8000400 <main>
0800076e <LoopForever>:
LoopForever:
b LoopForever
800076e: e7fe b.n 800076e <LoopForever>
ldr r0, =_estack
8000770: 20001800 .word 0x20001800
LDR R0,=0x00000004
8000774: 00000004 .word 0x00000004
LDR R2,=0x1F
8000778: 0000001f .word 0x0000001f
LDR R0,=0x40021018
800077c: 40021018 .word 0x40021018
LDR R1,=0x00000001
8000780: 00000001 .word 0x00000001
LDR R0,=0x40010000
8000784: 40010000 .word 0x40010000
LDR R1,=0x00000000
8000788: 00000000 .word 0x00000000
ldr r0, =_sdata
800078c: 20000000 .word 0x20000000
ldr r1, =_edata
8000790: 2000000c .word 0x2000000c
ldr r2, =_sidata
8000794: 08002510 .word 0x08002510
ldr r2, =_sbss
8000798: 2000000c .word 0x2000000c
ldr r4, =_ebss
800079c: 200000d8 .word 0x200000d8
080007a0 <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80007a0: e7fe b.n 80007a0 <ADC1_IRQHandler>
...
080007a4 <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* The tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80007a4: b580 push {r7, lr}
80007a6: af00 add r7, sp, #0
/* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
80007a8: 4b07 ldr r3, [pc, #28] ; (80007c8 <HAL_Init+0x24>)
80007aa: 681a ldr r2, [r3, #0]
80007ac: 4b06 ldr r3, [pc, #24] ; (80007c8 <HAL_Init+0x24>)
80007ae: 2110 movs r1, #16
80007b0: 430a orrs r2, r1
80007b2: 601a str r2, [r3, #0]
#endif /* PREFETCH_ENABLE */
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
80007b4: 2003 movs r0, #3
80007b6: f000 f809 bl 80007cc <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
80007ba: f7ff ff23 bl 8000604 <HAL_MspInit>
/* Return function status */
return HAL_OK;
80007be: 2300 movs r3, #0
}
80007c0: 0018 movs r0, r3
80007c2: 46bd mov sp, r7
80007c4: bd80 pop {r7, pc}
80007c6: 46c0 nop ; (mov r8, r8)
80007c8: 40022000 .word 0x40022000
080007cc <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
80007cc: b590 push {r4, r7, lr}
80007ce: b083 sub sp, #12
80007d0: af00 add r7, sp, #0
80007d2: 6078 str r0, [r7, #4]
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
80007d4: 4b14 ldr r3, [pc, #80] ; (8000828 <HAL_InitTick+0x5c>)
80007d6: 681c ldr r4, [r3, #0]
80007d8: 4b14 ldr r3, [pc, #80] ; (800082c <HAL_InitTick+0x60>)
80007da: 781b ldrb r3, [r3, #0]
80007dc: 0019 movs r1, r3
80007de: 23fa movs r3, #250 ; 0xfa
80007e0: 0098 lsls r0, r3, #2
80007e2: f7ff fc91 bl 8000108 <__udivsi3>
80007e6: 0003 movs r3, r0
80007e8: 0019 movs r1, r3
80007ea: 0020 movs r0, r4
80007ec: f7ff fc8c bl 8000108 <__udivsi3>
80007f0: 0003 movs r3, r0
80007f2: 0018 movs r0, r3
80007f4: f000 f905 bl 8000a02 <HAL_SYSTICK_Config>
80007f8: 1e03 subs r3, r0, #0
80007fa: d001 beq.n 8000800 <HAL_InitTick+0x34>
{
return HAL_ERROR;
80007fc: 2301 movs r3, #1
80007fe: e00f b.n 8000820 <HAL_InitTick+0x54>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000800: 687b ldr r3, [r7, #4]
8000802: 2b03 cmp r3, #3
8000804: d80b bhi.n 800081e <HAL_InitTick+0x52>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000806: 6879 ldr r1, [r7, #4]
8000808: 2301 movs r3, #1
800080a: 425b negs r3, r3
800080c: 2200 movs r2, #0
800080e: 0018 movs r0, r3
8000810: f000 f8e2 bl 80009d8 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000814: 4b06 ldr r3, [pc, #24] ; (8000830 <HAL_InitTick+0x64>)
8000816: 687a ldr r2, [r7, #4]
8000818: 601a str r2, [r3, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
800081a: 2300 movs r3, #0
800081c: e000 b.n 8000820 <HAL_InitTick+0x54>
return HAL_ERROR;
800081e: 2301 movs r3, #1
}
8000820: 0018 movs r0, r3
8000822: 46bd mov sp, r7
8000824: b003 add sp, #12
8000826: bd90 pop {r4, r7, pc}
8000828: 20000000 .word 0x20000000
800082c: 20000008 .word 0x20000008
8000830: 20000004 .word 0x20000004
08000834 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000834: b580 push {r7, lr}
8000836: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000838: 4b05 ldr r3, [pc, #20] ; (8000850 <HAL_IncTick+0x1c>)
800083a: 781b ldrb r3, [r3, #0]
800083c: 001a movs r2, r3
800083e: 4b05 ldr r3, [pc, #20] ; (8000854 <HAL_IncTick+0x20>)
8000840: 681b ldr r3, [r3, #0]
8000842: 18d2 adds r2, r2, r3
8000844: 4b03 ldr r3, [pc, #12] ; (8000854 <HAL_IncTick+0x20>)
8000846: 601a str r2, [r3, #0]
}
8000848: 46c0 nop ; (mov r8, r8)
800084a: 46bd mov sp, r7
800084c: bd80 pop {r7, pc}
800084e: 46c0 nop ; (mov r8, r8)
8000850: 20000008 .word 0x20000008
8000854: 200000d4 .word 0x200000d4
08000858 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000858: b580 push {r7, lr}
800085a: af00 add r7, sp, #0
return uwTick;
800085c: 4b02 ldr r3, [pc, #8] ; (8000868 <HAL_GetTick+0x10>)
800085e: 681b ldr r3, [r3, #0]
}
8000860: 0018 movs r0, r3
8000862: 46bd mov sp, r7
8000864: bd80 pop {r7, pc}
8000866: 46c0 nop ; (mov r8, r8)
8000868: 200000d4 .word 0x200000d4
0800086c <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
800086c: b580 push {r7, lr}
800086e: b084 sub sp, #16
8000870: af00 add r7, sp, #0
8000872: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8000874: f7ff fff0 bl 8000858 <HAL_GetTick>
8000878: 0003 movs r3, r0
800087a: 60bb str r3, [r7, #8]
uint32_t wait = Delay;
800087c: 687b ldr r3, [r7, #4]
800087e: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
8000880: 68fb ldr r3, [r7, #12]
8000882: 3301 adds r3, #1
8000884: d005 beq.n 8000892 <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
8000886: 4b0a ldr r3, [pc, #40] ; (80008b0 <HAL_Delay+0x44>)
8000888: 781b ldrb r3, [r3, #0]
800088a: 001a movs r2, r3
800088c: 68fb ldr r3, [r7, #12]
800088e: 189b adds r3, r3, r2
8000890: 60fb str r3, [r7, #12]
}
while((HAL_GetTick() - tickstart) < wait)
8000892: 46c0 nop ; (mov r8, r8)
8000894: f7ff ffe0 bl 8000858 <HAL_GetTick>
8000898: 0002 movs r2, r0
800089a: 68bb ldr r3, [r7, #8]
800089c: 1ad3 subs r3, r2, r3
800089e: 68fa ldr r2, [r7, #12]
80008a0: 429a cmp r2, r3
80008a2: d8f7 bhi.n 8000894 <HAL_Delay+0x28>
{
}
}
80008a4: 46c0 nop ; (mov r8, r8)
80008a6: 46c0 nop ; (mov r8, r8)
80008a8: 46bd mov sp, r7
80008aa: b004 add sp, #16
80008ac: bd80 pop {r7, pc}
80008ae: 46c0 nop ; (mov r8, r8)
80008b0: 20000008 .word 0x20000008
080008b4 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
80008b4: b590 push {r4, r7, lr}
80008b6: b083 sub sp, #12
80008b8: af00 add r7, sp, #0
80008ba: 0002 movs r2, r0
80008bc: 6039 str r1, [r7, #0]
80008be: 1dfb adds r3, r7, #7
80008c0: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) >= 0)
80008c2: 1dfb adds r3, r7, #7
80008c4: 781b ldrb r3, [r3, #0]
80008c6: 2b7f cmp r3, #127 ; 0x7f
80008c8: d828 bhi.n 800091c <__NVIC_SetPriority+0x68>
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
80008ca: 4a2f ldr r2, [pc, #188] ; (8000988 <__NVIC_SetPriority+0xd4>)
80008cc: 1dfb adds r3, r7, #7
80008ce: 781b ldrb r3, [r3, #0]
80008d0: b25b sxtb r3, r3
80008d2: 089b lsrs r3, r3, #2
80008d4: 33c0 adds r3, #192 ; 0xc0
80008d6: 009b lsls r3, r3, #2
80008d8: 589b ldr r3, [r3, r2]
80008da: 1dfa adds r2, r7, #7
80008dc: 7812 ldrb r2, [r2, #0]
80008de: 0011 movs r1, r2
80008e0: 2203 movs r2, #3
80008e2: 400a ands r2, r1
80008e4: 00d2 lsls r2, r2, #3
80008e6: 21ff movs r1, #255 ; 0xff
80008e8: 4091 lsls r1, r2
80008ea: 000a movs r2, r1
80008ec: 43d2 mvns r2, r2
80008ee: 401a ands r2, r3
80008f0: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
80008f2: 683b ldr r3, [r7, #0]
80008f4: 019b lsls r3, r3, #6
80008f6: 22ff movs r2, #255 ; 0xff
80008f8: 401a ands r2, r3
80008fa: 1dfb adds r3, r7, #7
80008fc: 781b ldrb r3, [r3, #0]
80008fe: 0018 movs r0, r3
8000900: 2303 movs r3, #3
8000902: 4003 ands r3, r0
8000904: 00db lsls r3, r3, #3
8000906: 409a lsls r2, r3
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000908: 481f ldr r0, [pc, #124] ; (8000988 <__NVIC_SetPriority+0xd4>)
800090a: 1dfb adds r3, r7, #7
800090c: 781b ldrb r3, [r3, #0]
800090e: b25b sxtb r3, r3
8000910: 089b lsrs r3, r3, #2
8000912: 430a orrs r2, r1
8000914: 33c0 adds r3, #192 ; 0xc0
8000916: 009b lsls r3, r3, #2
8000918: 501a str r2, [r3, r0]
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
800091a: e031 b.n 8000980 <__NVIC_SetPriority+0xcc>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
800091c: 4a1b ldr r2, [pc, #108] ; (800098c <__NVIC_SetPriority+0xd8>)
800091e: 1dfb adds r3, r7, #7
8000920: 781b ldrb r3, [r3, #0]
8000922: 0019 movs r1, r3
8000924: 230f movs r3, #15
8000926: 400b ands r3, r1
8000928: 3b08 subs r3, #8
800092a: 089b lsrs r3, r3, #2
800092c: 3306 adds r3, #6
800092e: 009b lsls r3, r3, #2
8000930: 18d3 adds r3, r2, r3
8000932: 3304 adds r3, #4
8000934: 681b ldr r3, [r3, #0]
8000936: 1dfa adds r2, r7, #7
8000938: 7812 ldrb r2, [r2, #0]
800093a: 0011 movs r1, r2
800093c: 2203 movs r2, #3
800093e: 400a ands r2, r1
8000940: 00d2 lsls r2, r2, #3
8000942: 21ff movs r1, #255 ; 0xff
8000944: 4091 lsls r1, r2
8000946: 000a movs r2, r1
8000948: 43d2 mvns r2, r2
800094a: 401a ands r2, r3
800094c: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
800094e: 683b ldr r3, [r7, #0]
8000950: 019b lsls r3, r3, #6
8000952: 22ff movs r2, #255 ; 0xff
8000954: 401a ands r2, r3
8000956: 1dfb adds r3, r7, #7
8000958: 781b ldrb r3, [r3, #0]
800095a: 0018 movs r0, r3
800095c: 2303 movs r3, #3
800095e: 4003 ands r3, r0
8000960: 00db lsls r3, r3, #3
8000962: 409a lsls r2, r3
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000964: 4809 ldr r0, [pc, #36] ; (800098c <__NVIC_SetPriority+0xd8>)
8000966: 1dfb adds r3, r7, #7
8000968: 781b ldrb r3, [r3, #0]
800096a: 001c movs r4, r3
800096c: 230f movs r3, #15
800096e: 4023 ands r3, r4
8000970: 3b08 subs r3, #8
8000972: 089b lsrs r3, r3, #2
8000974: 430a orrs r2, r1
8000976: 3306 adds r3, #6
8000978: 009b lsls r3, r3, #2
800097a: 18c3 adds r3, r0, r3
800097c: 3304 adds r3, #4
800097e: 601a str r2, [r3, #0]
}
8000980: 46c0 nop ; (mov r8, r8)
8000982: 46bd mov sp, r7
8000984: b003 add sp, #12
8000986: bd90 pop {r4, r7, pc}
8000988: e000e100 .word 0xe000e100
800098c: e000ed00 .word 0xe000ed00
08000990 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8000990: b580 push {r7, lr}
8000992: b082 sub sp, #8
8000994: af00 add r7, sp, #0
8000996: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000998: 687b ldr r3, [r7, #4]
800099a: 1e5a subs r2, r3, #1
800099c: 2380 movs r3, #128 ; 0x80
800099e: 045b lsls r3, r3, #17
80009a0: 429a cmp r2, r3
80009a2: d301 bcc.n 80009a8 <SysTick_Config+0x18>
{
return (1UL); /* Reload value impossible */
80009a4: 2301 movs r3, #1
80009a6: e010 b.n 80009ca <SysTick_Config+0x3a>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
80009a8: 4b0a ldr r3, [pc, #40] ; (80009d4 <SysTick_Config+0x44>)
80009aa: 687a ldr r2, [r7, #4]
80009ac: 3a01 subs r2, #1
80009ae: 605a str r2, [r3, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
80009b0: 2301 movs r3, #1
80009b2: 425b negs r3, r3
80009b4: 2103 movs r1, #3
80009b6: 0018 movs r0, r3
80009b8: f7ff ff7c bl 80008b4 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
80009bc: 4b05 ldr r3, [pc, #20] ; (80009d4 <SysTick_Config+0x44>)
80009be: 2200 movs r2, #0
80009c0: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
80009c2: 4b04 ldr r3, [pc, #16] ; (80009d4 <SysTick_Config+0x44>)
80009c4: 2207 movs r2, #7
80009c6: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
80009c8: 2300 movs r3, #0
}
80009ca: 0018 movs r0, r3
80009cc: 46bd mov sp, r7
80009ce: b002 add sp, #8
80009d0: bd80 pop {r7, pc}
80009d2: 46c0 nop ; (mov r8, r8)
80009d4: e000e010 .word 0xe000e010
080009d8 <HAL_NVIC_SetPriority>:
* with stm32f0xx devices, this parameter is a dummy value and it is ignored, because
* no subpriority supported in Cortex M0 based products.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
80009d8: b580 push {r7, lr}
80009da: b084 sub sp, #16
80009dc: af00 add r7, sp, #0
80009de: 60b9 str r1, [r7, #8]
80009e0: 607a str r2, [r7, #4]
80009e2: 210f movs r1, #15
80009e4: 187b adds r3, r7, r1
80009e6: 1c02 adds r2, r0, #0
80009e8: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
NVIC_SetPriority(IRQn,PreemptPriority);
80009ea: 68ba ldr r2, [r7, #8]
80009ec: 187b adds r3, r7, r1
80009ee: 781b ldrb r3, [r3, #0]
80009f0: b25b sxtb r3, r3
80009f2: 0011 movs r1, r2
80009f4: 0018 movs r0, r3
80009f6: f7ff ff5d bl 80008b4 <__NVIC_SetPriority>
}
80009fa: 46c0 nop ; (mov r8, r8)
80009fc: 46bd mov sp, r7
80009fe: b004 add sp, #16
8000a00: bd80 pop {r7, pc}
08000a02 <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8000a02: b580 push {r7, lr}
8000a04: b082 sub sp, #8
8000a06: af00 add r7, sp, #0
8000a08: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8000a0a: 687b ldr r3, [r7, #4]
8000a0c: 0018 movs r0, r3
8000a0e: f7ff ffbf bl 8000990 <SysTick_Config>
8000a12: 0003 movs r3, r0
}
8000a14: 0018 movs r0, r3
8000a16: 46bd mov sp, r7
8000a18: b002 add sp, #8
8000a1a: bd80 pop {r7, pc}
08000a1c <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8000a1c: b580 push {r7, lr}
8000a1e: b086 sub sp, #24
8000a20: af00 add r7, sp, #0
8000a22: 6078 str r0, [r7, #4]
8000a24: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8000a26: 2300 movs r3, #0
8000a28: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
8000a2a: e149 b.n 8000cc0 <HAL_GPIO_Init+0x2a4>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
8000a2c: 683b ldr r3, [r7, #0]
8000a2e: 681b ldr r3, [r3, #0]
8000a30: 2101 movs r1, #1
8000a32: 697a ldr r2, [r7, #20]
8000a34: 4091 lsls r1, r2
8000a36: 000a movs r2, r1
8000a38: 4013 ands r3, r2
8000a3a: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8000a3c: 68fb ldr r3, [r7, #12]
8000a3e: 2b00 cmp r3, #0
8000a40: d100 bne.n 8000a44 <HAL_GPIO_Init+0x28>
8000a42: e13a b.n 8000cba <HAL_GPIO_Init+0x29e>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8000a44: 683b ldr r3, [r7, #0]
8000a46: 685b ldr r3, [r3, #4]
8000a48: 2203 movs r2, #3
8000a4a: 4013 ands r3, r2
8000a4c: 2b01 cmp r3, #1
8000a4e: d005 beq.n 8000a5c <HAL_GPIO_Init+0x40>
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8000a50: 683b ldr r3, [r7, #0]
8000a52: 685b ldr r3, [r3, #4]
8000a54: 2203 movs r2, #3
8000a56: 4013 ands r3, r2
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8000a58: 2b02 cmp r3, #2
8000a5a: d130 bne.n 8000abe <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8000a5c: 687b ldr r3, [r7, #4]
8000a5e: 689b ldr r3, [r3, #8]
8000a60: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
8000a62: 697b ldr r3, [r7, #20]
8000a64: 005b lsls r3, r3, #1
8000a66: 2203 movs r2, #3
8000a68: 409a lsls r2, r3
8000a6a: 0013 movs r3, r2
8000a6c: 43da mvns r2, r3
8000a6e: 693b ldr r3, [r7, #16]
8000a70: 4013 ands r3, r2
8000a72: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
8000a74: 683b ldr r3, [r7, #0]
8000a76: 68da ldr r2, [r3, #12]
8000a78: 697b ldr r3, [r7, #20]
8000a7a: 005b lsls r3, r3, #1
8000a7c: 409a lsls r2, r3
8000a7e: 0013 movs r3, r2
8000a80: 693a ldr r2, [r7, #16]
8000a82: 4313 orrs r3, r2
8000a84: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8000a86: 687b ldr r3, [r7, #4]
8000a88: 693a ldr r2, [r7, #16]
8000a8a: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8000a8c: 687b ldr r3, [r7, #4]
8000a8e: 685b ldr r3, [r3, #4]
8000a90: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8000a92: 2201 movs r2, #1
8000a94: 697b ldr r3, [r7, #20]
8000a96: 409a lsls r2, r3
8000a98: 0013 movs r3, r2
8000a9a: 43da mvns r2, r3
8000a9c: 693b ldr r3, [r7, #16]
8000a9e: 4013 ands r3, r2
8000aa0: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8000aa2: 683b ldr r3, [r7, #0]
8000aa4: 685b ldr r3, [r3, #4]
8000aa6: 091b lsrs r3, r3, #4
8000aa8: 2201 movs r2, #1
8000aaa: 401a ands r2, r3
8000aac: 697b ldr r3, [r7, #20]
8000aae: 409a lsls r2, r3
8000ab0: 0013 movs r3, r2
8000ab2: 693a ldr r2, [r7, #16]
8000ab4: 4313 orrs r3, r2
8000ab6: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8000ab8: 687b ldr r3, [r7, #4]
8000aba: 693a ldr r2, [r7, #16]
8000abc: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8000abe: 683b ldr r3, [r7, #0]
8000ac0: 685b ldr r3, [r3, #4]
8000ac2: 2203 movs r2, #3
8000ac4: 4013 ands r3, r2
8000ac6: 2b03 cmp r3, #3
8000ac8: d017 beq.n 8000afa <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8000aca: 687b ldr r3, [r7, #4]
8000acc: 68db ldr r3, [r3, #12]
8000ace: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
8000ad0: 697b ldr r3, [r7, #20]
8000ad2: 005b lsls r3, r3, #1
8000ad4: 2203 movs r2, #3
8000ad6: 409a lsls r2, r3
8000ad8: 0013 movs r3, r2
8000ada: 43da mvns r2, r3
8000adc: 693b ldr r3, [r7, #16]
8000ade: 4013 ands r3, r2
8000ae0: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2u));
8000ae2: 683b ldr r3, [r7, #0]
8000ae4: 689a ldr r2, [r3, #8]
8000ae6: 697b ldr r3, [r7, #20]
8000ae8: 005b lsls r3, r3, #1
8000aea: 409a lsls r2, r3
8000aec: 0013 movs r3, r2
8000aee: 693a ldr r2, [r7, #16]
8000af0: 4313 orrs r3, r2
8000af2: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
8000af4: 687b ldr r3, [r7, #4]
8000af6: 693a ldr r2, [r7, #16]
8000af8: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8000afa: 683b ldr r3, [r7, #0]
8000afc: 685b ldr r3, [r3, #4]
8000afe: 2203 movs r2, #3
8000b00: 4013 ands r3, r2
8000b02: 2b02 cmp r3, #2
8000b04: d123 bne.n 8000b4e <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
8000b06: 697b ldr r3, [r7, #20]
8000b08: 08da lsrs r2, r3, #3
8000b0a: 687b ldr r3, [r7, #4]
8000b0c: 3208 adds r2, #8
8000b0e: 0092 lsls r2, r2, #2
8000b10: 58d3 ldr r3, [r2, r3]
8000b12: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
8000b14: 697b ldr r3, [r7, #20]
8000b16: 2207 movs r2, #7
8000b18: 4013 ands r3, r2
8000b1a: 009b lsls r3, r3, #2
8000b1c: 220f movs r2, #15
8000b1e: 409a lsls r2, r3
8000b20: 0013 movs r3, r2
8000b22: 43da mvns r2, r3
8000b24: 693b ldr r3, [r7, #16]
8000b26: 4013 ands r3, r2
8000b28: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
8000b2a: 683b ldr r3, [r7, #0]
8000b2c: 691a ldr r2, [r3, #16]
8000b2e: 697b ldr r3, [r7, #20]
8000b30: 2107 movs r1, #7
8000b32: 400b ands r3, r1
8000b34: 009b lsls r3, r3, #2
8000b36: 409a lsls r2, r3
8000b38: 0013 movs r3, r2
8000b3a: 693a ldr r2, [r7, #16]
8000b3c: 4313 orrs r3, r2
8000b3e: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
8000b40: 697b ldr r3, [r7, #20]
8000b42: 08da lsrs r2, r3, #3
8000b44: 687b ldr r3, [r7, #4]
8000b46: 3208 adds r2, #8
8000b48: 0092 lsls r2, r2, #2
8000b4a: 6939 ldr r1, [r7, #16]
8000b4c: 50d1 str r1, [r2, r3]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8000b4e: 687b ldr r3, [r7, #4]
8000b50: 681b ldr r3, [r3, #0]
8000b52: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
8000b54: 697b ldr r3, [r7, #20]
8000b56: 005b lsls r3, r3, #1
8000b58: 2203 movs r2, #3
8000b5a: 409a lsls r2, r3
8000b5c: 0013 movs r3, r2
8000b5e: 43da mvns r2, r3
8000b60: 693b ldr r3, [r7, #16]
8000b62: 4013 ands r3, r2
8000b64: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
8000b66: 683b ldr r3, [r7, #0]
8000b68: 685b ldr r3, [r3, #4]
8000b6a: 2203 movs r2, #3
8000b6c: 401a ands r2, r3
8000b6e: 697b ldr r3, [r7, #20]
8000b70: 005b lsls r3, r3, #1
8000b72: 409a lsls r2, r3
8000b74: 0013 movs r3, r2
8000b76: 693a ldr r2, [r7, #16]
8000b78: 4313 orrs r3, r2
8000b7a: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8000b7c: 687b ldr r3, [r7, #4]
8000b7e: 693a ldr r2, [r7, #16]
8000b80: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8000b82: 683b ldr r3, [r7, #0]
8000b84: 685a ldr r2, [r3, #4]
8000b86: 23c0 movs r3, #192 ; 0xc0
8000b88: 029b lsls r3, r3, #10
8000b8a: 4013 ands r3, r2
8000b8c: d100 bne.n 8000b90 <HAL_GPIO_Init+0x174>
8000b8e: e094 b.n 8000cba <HAL_GPIO_Init+0x29e>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000b90: 4b51 ldr r3, [pc, #324] ; (8000cd8 <HAL_GPIO_Init+0x2bc>)
8000b92: 699a ldr r2, [r3, #24]
8000b94: 4b50 ldr r3, [pc, #320] ; (8000cd8 <HAL_GPIO_Init+0x2bc>)
8000b96: 2101 movs r1, #1
8000b98: 430a orrs r2, r1
8000b9a: 619a str r2, [r3, #24]
8000b9c: 4b4e ldr r3, [pc, #312] ; (8000cd8 <HAL_GPIO_Init+0x2bc>)
8000b9e: 699b ldr r3, [r3, #24]
8000ba0: 2201 movs r2, #1
8000ba2: 4013 ands r3, r2
8000ba4: 60bb str r3, [r7, #8]
8000ba6: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2u];
8000ba8: 4a4c ldr r2, [pc, #304] ; (8000cdc <HAL_GPIO_Init+0x2c0>)
8000baa: 697b ldr r3, [r7, #20]
8000bac: 089b lsrs r3, r3, #2
8000bae: 3302 adds r3, #2
8000bb0: 009b lsls r3, r3, #2
8000bb2: 589b ldr r3, [r3, r2]
8000bb4: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
8000bb6: 697b ldr r3, [r7, #20]
8000bb8: 2203 movs r2, #3
8000bba: 4013 ands r3, r2
8000bbc: 009b lsls r3, r3, #2
8000bbe: 220f movs r2, #15
8000bc0: 409a lsls r2, r3
8000bc2: 0013 movs r3, r2
8000bc4: 43da mvns r2, r3
8000bc6: 693b ldr r3, [r7, #16]
8000bc8: 4013 ands r3, r2
8000bca: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
8000bcc: 687a ldr r2, [r7, #4]
8000bce: 2390 movs r3, #144 ; 0x90
8000bd0: 05db lsls r3, r3, #23
8000bd2: 429a cmp r2, r3
8000bd4: d00d beq.n 8000bf2 <HAL_GPIO_Init+0x1d6>
8000bd6: 687b ldr r3, [r7, #4]
8000bd8: 4a41 ldr r2, [pc, #260] ; (8000ce0 <HAL_GPIO_Init+0x2c4>)
8000bda: 4293 cmp r3, r2
8000bdc: d007 beq.n 8000bee <HAL_GPIO_Init+0x1d2>
8000bde: 687b ldr r3, [r7, #4]
8000be0: 4a40 ldr r2, [pc, #256] ; (8000ce4 <HAL_GPIO_Init+0x2c8>)
8000be2: 4293 cmp r3, r2
8000be4: d101 bne.n 8000bea <HAL_GPIO_Init+0x1ce>
8000be6: 2302 movs r3, #2
8000be8: e004 b.n 8000bf4 <HAL_GPIO_Init+0x1d8>
8000bea: 2305 movs r3, #5
8000bec: e002 b.n 8000bf4 <HAL_GPIO_Init+0x1d8>
8000bee: 2301 movs r3, #1
8000bf0: e000 b.n 8000bf4 <HAL_GPIO_Init+0x1d8>
8000bf2: 2300 movs r3, #0
8000bf4: 697a ldr r2, [r7, #20]
8000bf6: 2103 movs r1, #3
8000bf8: 400a ands r2, r1
8000bfa: 0092 lsls r2, r2, #2
8000bfc: 4093 lsls r3, r2
8000bfe: 693a ldr r2, [r7, #16]
8000c00: 4313 orrs r3, r2
8000c02: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
8000c04: 4935 ldr r1, [pc, #212] ; (8000cdc <HAL_GPIO_Init+0x2c0>)
8000c06: 697b ldr r3, [r7, #20]
8000c08: 089b lsrs r3, r3, #2
8000c0a: 3302 adds r3, #2
8000c0c: 009b lsls r3, r3, #2
8000c0e: 693a ldr r2, [r7, #16]
8000c10: 505a str r2, [r3, r1]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8000c12: 4b35 ldr r3, [pc, #212] ; (8000ce8 <HAL_GPIO_Init+0x2cc>)
8000c14: 689b ldr r3, [r3, #8]
8000c16: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000c18: 68fb ldr r3, [r7, #12]
8000c1a: 43da mvns r2, r3
8000c1c: 693b ldr r3, [r7, #16]
8000c1e: 4013 ands r3, r2
8000c20: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
8000c22: 683b ldr r3, [r7, #0]
8000c24: 685a ldr r2, [r3, #4]
8000c26: 2380 movs r3, #128 ; 0x80
8000c28: 035b lsls r3, r3, #13
8000c2a: 4013 ands r3, r2
8000c2c: d003 beq.n 8000c36 <HAL_GPIO_Init+0x21a>
{
temp |= iocurrent;
8000c2e: 693a ldr r2, [r7, #16]
8000c30: 68fb ldr r3, [r7, #12]
8000c32: 4313 orrs r3, r2
8000c34: 613b str r3, [r7, #16]
}
EXTI->RTSR = temp;
8000c36: 4b2c ldr r3, [pc, #176] ; (8000ce8 <HAL_GPIO_Init+0x2cc>)
8000c38: 693a ldr r2, [r7, #16]
8000c3a: 609a str r2, [r3, #8]
temp = EXTI->FTSR;
8000c3c: 4b2a ldr r3, [pc, #168] ; (8000ce8 <HAL_GPIO_Init+0x2cc>)
8000c3e: 68db ldr r3, [r3, #12]
8000c40: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000c42: 68fb ldr r3, [r7, #12]
8000c44: 43da mvns r2, r3
8000c46: 693b ldr r3, [r7, #16]
8000c48: 4013 ands r3, r2
8000c4a: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
8000c4c: 683b ldr r3, [r7, #0]
8000c4e: 685a ldr r2, [r3, #4]
8000c50: 2380 movs r3, #128 ; 0x80
8000c52: 039b lsls r3, r3, #14
8000c54: 4013 ands r3, r2
8000c56: d003 beq.n 8000c60 <HAL_GPIO_Init+0x244>
{
temp |= iocurrent;
8000c58: 693a ldr r2, [r7, #16]
8000c5a: 68fb ldr r3, [r7, #12]
8000c5c: 4313 orrs r3, r2
8000c5e: 613b str r3, [r7, #16]
}
EXTI->FTSR = temp;
8000c60: 4b21 ldr r3, [pc, #132] ; (8000ce8 <HAL_GPIO_Init+0x2cc>)
8000c62: 693a ldr r2, [r7, #16]
8000c64: 60da str r2, [r3, #12]
/* Clear EXTI line configuration */
temp = EXTI->EMR;
8000c66: 4b20 ldr r3, [pc, #128] ; (8000ce8 <HAL_GPIO_Init+0x2cc>)
8000c68: 685b ldr r3, [r3, #4]
8000c6a: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000c6c: 68fb ldr r3, [r7, #12]
8000c6e: 43da mvns r2, r3
8000c70: 693b ldr r3, [r7, #16]
8000c72: 4013 ands r3, r2
8000c74: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8000c76: 683b ldr r3, [r7, #0]
8000c78: 685a ldr r2, [r3, #4]
8000c7a: 2380 movs r3, #128 ; 0x80
8000c7c: 029b lsls r3, r3, #10
8000c7e: 4013 ands r3, r2
8000c80: d003 beq.n 8000c8a <HAL_GPIO_Init+0x26e>
{
temp |= iocurrent;
8000c82: 693a ldr r2, [r7, #16]
8000c84: 68fb ldr r3, [r7, #12]
8000c86: 4313 orrs r3, r2
8000c88: 613b str r3, [r7, #16]
}
EXTI->EMR = temp;
8000c8a: 4b17 ldr r3, [pc, #92] ; (8000ce8 <HAL_GPIO_Init+0x2cc>)
8000c8c: 693a ldr r2, [r7, #16]
8000c8e: 605a str r2, [r3, #4]
temp = EXTI->IMR;
8000c90: 4b15 ldr r3, [pc, #84] ; (8000ce8 <HAL_GPIO_Init+0x2cc>)
8000c92: 681b ldr r3, [r3, #0]
8000c94: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000c96: 68fb ldr r3, [r7, #12]
8000c98: 43da mvns r2, r3
8000c9a: 693b ldr r3, [r7, #16]
8000c9c: 4013 ands r3, r2
8000c9e: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
8000ca0: 683b ldr r3, [r7, #0]
8000ca2: 685a ldr r2, [r3, #4]
8000ca4: 2380 movs r3, #128 ; 0x80
8000ca6: 025b lsls r3, r3, #9
8000ca8: 4013 ands r3, r2
8000caa: d003 beq.n 8000cb4 <HAL_GPIO_Init+0x298>
{
temp |= iocurrent;
8000cac: 693a ldr r2, [r7, #16]
8000cae: 68fb ldr r3, [r7, #12]
8000cb0: 4313 orrs r3, r2
8000cb2: 613b str r3, [r7, #16]
}
EXTI->IMR = temp;
8000cb4: 4b0c ldr r3, [pc, #48] ; (8000ce8 <HAL_GPIO_Init+0x2cc>)
8000cb6: 693a ldr r2, [r7, #16]
8000cb8: 601a str r2, [r3, #0]
}
}
position++;
8000cba: 697b ldr r3, [r7, #20]
8000cbc: 3301 adds r3, #1
8000cbe: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
8000cc0: 683b ldr r3, [r7, #0]
8000cc2: 681a ldr r2, [r3, #0]
8000cc4: 697b ldr r3, [r7, #20]
8000cc6: 40da lsrs r2, r3
8000cc8: 1e13 subs r3, r2, #0
8000cca: d000 beq.n 8000cce <HAL_GPIO_Init+0x2b2>
8000ccc: e6ae b.n 8000a2c <HAL_GPIO_Init+0x10>
}
}
8000cce: 46c0 nop ; (mov r8, r8)
8000cd0: 46c0 nop ; (mov r8, r8)
8000cd2: 46bd mov sp, r7
8000cd4: b006 add sp, #24
8000cd6: bd80 pop {r7, pc}
8000cd8: 40021000 .word 0x40021000
8000cdc: 40010000 .word 0x40010000
8000ce0: 48000400 .word 0x48000400
8000ce4: 48000800 .word 0x48000800
8000ce8: 40010400 .word 0x40010400
08000cec <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
8000cec: b580 push {r7, lr}
8000cee: b082 sub sp, #8
8000cf0: af00 add r7, sp, #0
8000cf2: 6078 str r0, [r7, #4]
/* Check the I2C handle allocation */
if (hi2c == NULL)
8000cf4: 687b ldr r3, [r7, #4]
8000cf6: 2b00 cmp r3, #0
8000cf8: d101 bne.n 8000cfe <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
8000cfa: 2301 movs r3, #1
8000cfc: e082 b.n 8000e04 <HAL_I2C_Init+0x118>
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
8000cfe: 687b ldr r3, [r7, #4]
8000d00: 2241 movs r2, #65 ; 0x41
8000d02: 5c9b ldrb r3, [r3, r2]
8000d04: b2db uxtb r3, r3
8000d06: 2b00 cmp r3, #0
8000d08: d107 bne.n 8000d1a <HAL_I2C_Init+0x2e>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
8000d0a: 687b ldr r3, [r7, #4]
8000d0c: 2240 movs r2, #64 ; 0x40
8000d0e: 2100 movs r1, #0
8000d10: 5499 strb r1, [r3, r2]
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
8000d12: 687b ldr r3, [r7, #4]
8000d14: 0018 movs r0, r3
8000d16: f7ff fc99 bl 800064c <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
8000d1a: 687b ldr r3, [r7, #4]
8000d1c: 2241 movs r2, #65 ; 0x41
8000d1e: 2124 movs r1, #36 ; 0x24
8000d20: 5499 strb r1, [r3, r2]
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8000d22: 687b ldr r3, [r7, #4]
8000d24: 681b ldr r3, [r3, #0]
8000d26: 681a ldr r2, [r3, #0]
8000d28: 687b ldr r3, [r7, #4]
8000d2a: 681b ldr r3, [r3, #0]
8000d2c: 2101 movs r1, #1
8000d2e: 438a bics r2, r1
8000d30: 601a str r2, [r3, #0]
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
/* Configure I2Cx: Frequency range */
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
8000d32: 687b ldr r3, [r7, #4]
8000d34: 685a ldr r2, [r3, #4]
8000d36: 687b ldr r3, [r7, #4]
8000d38: 681b ldr r3, [r3, #0]
8000d3a: 4934 ldr r1, [pc, #208] ; (8000e0c <HAL_I2C_Init+0x120>)
8000d3c: 400a ands r2, r1
8000d3e: 611a str r2, [r3, #16]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
8000d40: 687b ldr r3, [r7, #4]
8000d42: 681b ldr r3, [r3, #0]
8000d44: 689a ldr r2, [r3, #8]
8000d46: 687b ldr r3, [r7, #4]
8000d48: 681b ldr r3, [r3, #0]
8000d4a: 4931 ldr r1, [pc, #196] ; (8000e10 <HAL_I2C_Init+0x124>)
8000d4c: 400a ands r2, r1
8000d4e: 609a str r2, [r3, #8]
/* Configure I2Cx: Own Address1 and ack own address1 mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
8000d50: 687b ldr r3, [r7, #4]
8000d52: 68db ldr r3, [r3, #12]
8000d54: 2b01 cmp r3, #1
8000d56: d108 bne.n 8000d6a <HAL_I2C_Init+0x7e>
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
8000d58: 687b ldr r3, [r7, #4]
8000d5a: 689a ldr r2, [r3, #8]
8000d5c: 687b ldr r3, [r7, #4]
8000d5e: 681b ldr r3, [r3, #0]
8000d60: 2180 movs r1, #128 ; 0x80
8000d62: 0209 lsls r1, r1, #8
8000d64: 430a orrs r2, r1
8000d66: 609a str r2, [r3, #8]
8000d68: e007 b.n 8000d7a <HAL_I2C_Init+0x8e>
}
else /* I2C_ADDRESSINGMODE_10BIT */
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
8000d6a: 687b ldr r3, [r7, #4]
8000d6c: 689a ldr r2, [r3, #8]
8000d6e: 687b ldr r3, [r7, #4]
8000d70: 681b ldr r3, [r3, #0]
8000d72: 2184 movs r1, #132 ; 0x84
8000d74: 0209 lsls r1, r1, #8
8000d76: 430a orrs r2, r1
8000d78: 609a str r2, [r3, #8]
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
8000d7a: 687b ldr r3, [r7, #4]
8000d7c: 68db ldr r3, [r3, #12]
8000d7e: 2b02 cmp r3, #2
8000d80: d104 bne.n 8000d8c <HAL_I2C_Init+0xa0>
{
hi2c->Instance->CR2 = (I2C_CR2_ADD10);
8000d82: 687b ldr r3, [r7, #4]
8000d84: 681b ldr r3, [r3, #0]
8000d86: 2280 movs r2, #128 ; 0x80
8000d88: 0112 lsls r2, r2, #4
8000d8a: 605a str r2, [r3, #4]
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
8000d8c: 687b ldr r3, [r7, #4]
8000d8e: 681b ldr r3, [r3, #0]
8000d90: 685a ldr r2, [r3, #4]
8000d92: 687b ldr r3, [r7, #4]
8000d94: 681b ldr r3, [r3, #0]
8000d96: 491f ldr r1, [pc, #124] ; (8000e14 <HAL_I2C_Init+0x128>)
8000d98: 430a orrs r2, r1
8000d9a: 605a str r2, [r3, #4]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Disable Own Address2 before set the Own Address2 configuration */
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
8000d9c: 687b ldr r3, [r7, #4]
8000d9e: 681b ldr r3, [r3, #0]
8000da0: 68da ldr r2, [r3, #12]
8000da2: 687b ldr r3, [r7, #4]
8000da4: 681b ldr r3, [r3, #0]
8000da6: 491a ldr r1, [pc, #104] ; (8000e10 <HAL_I2C_Init+0x124>)
8000da8: 400a ands r2, r1
8000daa: 60da str r2, [r3, #12]
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
8000dac: 687b ldr r3, [r7, #4]
8000dae: 691a ldr r2, [r3, #16]
8000db0: 687b ldr r3, [r7, #4]
8000db2: 695b ldr r3, [r3, #20]
8000db4: 431a orrs r2, r3
8000db6: 0011 movs r1, r2
(hi2c->Init.OwnAddress2Masks << 8));
8000db8: 687b ldr r3, [r7, #4]
8000dba: 699b ldr r3, [r3, #24]
8000dbc: 021a lsls r2, r3, #8
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
8000dbe: 687b ldr r3, [r7, #4]
8000dc0: 681b ldr r3, [r3, #0]
8000dc2: 430a orrs r2, r1
8000dc4: 60da str r2, [r3, #12]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
8000dc6: 687b ldr r3, [r7, #4]
8000dc8: 69d9 ldr r1, [r3, #28]
8000dca: 687b ldr r3, [r7, #4]
8000dcc: 6a1a ldr r2, [r3, #32]
8000dce: 687b ldr r3, [r7, #4]
8000dd0: 681b ldr r3, [r3, #0]
8000dd2: 430a orrs r2, r1
8000dd4: 601a str r2, [r3, #0]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
8000dd6: 687b ldr r3, [r7, #4]
8000dd8: 681b ldr r3, [r3, #0]
8000dda: 681a ldr r2, [r3, #0]
8000ddc: 687b ldr r3, [r7, #4]
8000dde: 681b ldr r3, [r3, #0]
8000de0: 2101 movs r1, #1
8000de2: 430a orrs r2, r1
8000de4: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8000de6: 687b ldr r3, [r7, #4]
8000de8: 2200 movs r2, #0
8000dea: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8000dec: 687b ldr r3, [r7, #4]
8000dee: 2241 movs r2, #65 ; 0x41
8000df0: 2120 movs r1, #32
8000df2: 5499 strb r1, [r3, r2]
hi2c->PreviousState = I2C_STATE_NONE;
8000df4: 687b ldr r3, [r7, #4]
8000df6: 2200 movs r2, #0
8000df8: 631a str r2, [r3, #48] ; 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
8000dfa: 687b ldr r3, [r7, #4]
8000dfc: 2242 movs r2, #66 ; 0x42
8000dfe: 2100 movs r1, #0
8000e00: 5499 strb r1, [r3, r2]
return HAL_OK;
8000e02: 2300 movs r3, #0
}
8000e04: 0018 movs r0, r3
8000e06: 46bd mov sp, r7
8000e08: b002 add sp, #8
8000e0a: bd80 pop {r7, pc}
8000e0c: f0ffffff .word 0xf0ffffff
8000e10: ffff7fff .word 0xffff7fff
8000e14: 02008000 .word 0x02008000
08000e18 <HAL_I2C_Master_Transmit>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout)
{
8000e18: b590 push {r4, r7, lr}
8000e1a: b089 sub sp, #36 ; 0x24
8000e1c: af02 add r7, sp, #8
8000e1e: 60f8 str r0, [r7, #12]
8000e20: 0008 movs r0, r1
8000e22: 607a str r2, [r7, #4]
8000e24: 0019 movs r1, r3
8000e26: 230a movs r3, #10
8000e28: 18fb adds r3, r7, r3
8000e2a: 1c02 adds r2, r0, #0
8000e2c: 801a strh r2, [r3, #0]
8000e2e: 2308 movs r3, #8
8000e30: 18fb adds r3, r7, r3
8000e32: 1c0a adds r2, r1, #0
8000e34: 801a strh r2, [r3, #0]
uint32_t tickstart;
if (hi2c->State == HAL_I2C_STATE_READY)
8000e36: 68fb ldr r3, [r7, #12]
8000e38: 2241 movs r2, #65 ; 0x41
8000e3a: 5c9b ldrb r3, [r3, r2]
8000e3c: b2db uxtb r3, r3
8000e3e: 2b20 cmp r3, #32
8000e40: d000 beq.n 8000e44 <HAL_I2C_Master_Transmit+0x2c>
8000e42: e0e7 b.n 8001014 <HAL_I2C_Master_Transmit+0x1fc>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8000e44: 68fb ldr r3, [r7, #12]
8000e46: 2240 movs r2, #64 ; 0x40
8000e48: 5c9b ldrb r3, [r3, r2]
8000e4a: 2b01 cmp r3, #1
8000e4c: d101 bne.n 8000e52 <HAL_I2C_Master_Transmit+0x3a>
8000e4e: 2302 movs r3, #2
8000e50: e0e1 b.n 8001016 <HAL_I2C_Master_Transmit+0x1fe>
8000e52: 68fb ldr r3, [r7, #12]
8000e54: 2240 movs r2, #64 ; 0x40
8000e56: 2101 movs r1, #1
8000e58: 5499 strb r1, [r3, r2]
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
8000e5a: f7ff fcfd bl 8000858 <HAL_GetTick>
8000e5e: 0003 movs r3, r0
8000e60: 617b str r3, [r7, #20]
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
8000e62: 2380 movs r3, #128 ; 0x80
8000e64: 0219 lsls r1, r3, #8
8000e66: 68f8 ldr r0, [r7, #12]
8000e68: 697b ldr r3, [r7, #20]
8000e6a: 9300 str r3, [sp, #0]
8000e6c: 2319 movs r3, #25
8000e6e: 2201 movs r2, #1
8000e70: f000 fa04 bl 800127c <I2C_WaitOnFlagUntilTimeout>
8000e74: 1e03 subs r3, r0, #0
8000e76: d001 beq.n 8000e7c <HAL_I2C_Master_Transmit+0x64>
{
return HAL_ERROR;
8000e78: 2301 movs r3, #1
8000e7a: e0cc b.n 8001016 <HAL_I2C_Master_Transmit+0x1fe>
}
hi2c->State = HAL_I2C_STATE_BUSY_TX;
8000e7c: 68fb ldr r3, [r7, #12]
8000e7e: 2241 movs r2, #65 ; 0x41
8000e80: 2121 movs r1, #33 ; 0x21
8000e82: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_MASTER;
8000e84: 68fb ldr r3, [r7, #12]
8000e86: 2242 movs r2, #66 ; 0x42
8000e88: 2110 movs r1, #16
8000e8a: 5499 strb r1, [r3, r2]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8000e8c: 68fb ldr r3, [r7, #12]
8000e8e: 2200 movs r2, #0
8000e90: 645a str r2, [r3, #68] ; 0x44
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
8000e92: 68fb ldr r3, [r7, #12]
8000e94: 687a ldr r2, [r7, #4]
8000e96: 625a str r2, [r3, #36] ; 0x24
hi2c->XferCount = Size;
8000e98: 68fb ldr r3, [r7, #12]
8000e9a: 2208 movs r2, #8
8000e9c: 18ba adds r2, r7, r2
8000e9e: 8812 ldrh r2, [r2, #0]
8000ea0: 855a strh r2, [r3, #42] ; 0x2a
hi2c->XferISR = NULL;
8000ea2: 68fb ldr r3, [r7, #12]
8000ea4: 2200 movs r2, #0
8000ea6: 635a str r2, [r3, #52] ; 0x34
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
8000ea8: 68fb ldr r3, [r7, #12]
8000eaa: 8d5b ldrh r3, [r3, #42] ; 0x2a
8000eac: b29b uxth r3, r3
8000eae: 2bff cmp r3, #255 ; 0xff
8000eb0: d911 bls.n 8000ed6 <HAL_I2C_Master_Transmit+0xbe>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
8000eb2: 68fb ldr r3, [r7, #12]
8000eb4: 22ff movs r2, #255 ; 0xff
8000eb6: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
8000eb8: 68fb ldr r3, [r7, #12]
8000eba: 8d1b ldrh r3, [r3, #40] ; 0x28
8000ebc: b2da uxtb r2, r3
8000ebe: 2380 movs r3, #128 ; 0x80
8000ec0: 045c lsls r4, r3, #17
8000ec2: 230a movs r3, #10
8000ec4: 18fb adds r3, r7, r3
8000ec6: 8819 ldrh r1, [r3, #0]
8000ec8: 68f8 ldr r0, [r7, #12]
8000eca: 4b55 ldr r3, [pc, #340] ; (8001020 <HAL_I2C_Master_Transmit+0x208>)
8000ecc: 9300 str r3, [sp, #0]
8000ece: 0023 movs r3, r4
8000ed0: f000 fc2e bl 8001730 <I2C_TransferConfig>
8000ed4: e075 b.n 8000fc2 <HAL_I2C_Master_Transmit+0x1aa>
I2C_GENERATE_START_WRITE);
}
else
{
hi2c->XferSize = hi2c->XferCount;
8000ed6: 68fb ldr r3, [r7, #12]
8000ed8: 8d5b ldrh r3, [r3, #42] ; 0x2a
8000eda: b29a uxth r2, r3
8000edc: 68fb ldr r3, [r7, #12]
8000ede: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
8000ee0: 68fb ldr r3, [r7, #12]
8000ee2: 8d1b ldrh r3, [r3, #40] ; 0x28
8000ee4: b2da uxtb r2, r3
8000ee6: 2380 movs r3, #128 ; 0x80
8000ee8: 049c lsls r4, r3, #18
8000eea: 230a movs r3, #10
8000eec: 18fb adds r3, r7, r3
8000eee: 8819 ldrh r1, [r3, #0]
8000ef0: 68f8 ldr r0, [r7, #12]
8000ef2: 4b4b ldr r3, [pc, #300] ; (8001020 <HAL_I2C_Master_Transmit+0x208>)
8000ef4: 9300 str r3, [sp, #0]
8000ef6: 0023 movs r3, r4
8000ef8: f000 fc1a bl 8001730 <I2C_TransferConfig>
I2C_GENERATE_START_WRITE);
}
while (hi2c->XferCount > 0U)
8000efc: e061 b.n 8000fc2 <HAL_I2C_Master_Transmit+0x1aa>
{
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8000efe: 697a ldr r2, [r7, #20]
8000f00: 6ab9 ldr r1, [r7, #40] ; 0x28
8000f02: 68fb ldr r3, [r7, #12]
8000f04: 0018 movs r0, r3
8000f06: f000 fa07 bl 8001318 <I2C_WaitOnTXISFlagUntilTimeout>
8000f0a: 1e03 subs r3, r0, #0
8000f0c: d001 beq.n 8000f12 <HAL_I2C_Master_Transmit+0xfa>
{
return HAL_ERROR;
8000f0e: 2301 movs r3, #1
8000f10: e081 b.n 8001016 <HAL_I2C_Master_Transmit+0x1fe>
}
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
8000f12: 68fb ldr r3, [r7, #12]
8000f14: 6a5b ldr r3, [r3, #36] ; 0x24
8000f16: 781a ldrb r2, [r3, #0]
8000f18: 68fb ldr r3, [r7, #12]
8000f1a: 681b ldr r3, [r3, #0]
8000f1c: 629a str r2, [r3, #40] ; 0x28
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8000f1e: 68fb ldr r3, [r7, #12]
8000f20: 6a5b ldr r3, [r3, #36] ; 0x24
8000f22: 1c5a adds r2, r3, #1
8000f24: 68fb ldr r3, [r7, #12]
8000f26: 625a str r2, [r3, #36] ; 0x24
hi2c->XferCount--;
8000f28: 68fb ldr r3, [r7, #12]
8000f2a: 8d5b ldrh r3, [r3, #42] ; 0x2a
8000f2c: b29b uxth r3, r3
8000f2e: 3b01 subs r3, #1
8000f30: b29a uxth r2, r3
8000f32: 68fb ldr r3, [r7, #12]
8000f34: 855a strh r2, [r3, #42] ; 0x2a
hi2c->XferSize--;
8000f36: 68fb ldr r3, [r7, #12]
8000f38: 8d1b ldrh r3, [r3, #40] ; 0x28
8000f3a: 3b01 subs r3, #1
8000f3c: b29a uxth r2, r3
8000f3e: 68fb ldr r3, [r7, #12]
8000f40: 851a strh r2, [r3, #40] ; 0x28
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
8000f42: 68fb ldr r3, [r7, #12]
8000f44: 8d5b ldrh r3, [r3, #42] ; 0x2a
8000f46: b29b uxth r3, r3
8000f48: 2b00 cmp r3, #0
8000f4a: d03a beq.n 8000fc2 <HAL_I2C_Master_Transmit+0x1aa>
8000f4c: 68fb ldr r3, [r7, #12]
8000f4e: 8d1b ldrh r3, [r3, #40] ; 0x28
8000f50: 2b00 cmp r3, #0
8000f52: d136 bne.n 8000fc2 <HAL_I2C_Master_Transmit+0x1aa>
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
8000f54: 6aba ldr r2, [r7, #40] ; 0x28
8000f56: 68f8 ldr r0, [r7, #12]
8000f58: 697b ldr r3, [r7, #20]
8000f5a: 9300 str r3, [sp, #0]
8000f5c: 0013 movs r3, r2
8000f5e: 2200 movs r2, #0
8000f60: 2180 movs r1, #128 ; 0x80
8000f62: f000 f98b bl 800127c <I2C_WaitOnFlagUntilTimeout>
8000f66: 1e03 subs r3, r0, #0
8000f68: d001 beq.n 8000f6e <HAL_I2C_Master_Transmit+0x156>
{
return HAL_ERROR;
8000f6a: 2301 movs r3, #1
8000f6c: e053 b.n 8001016 <HAL_I2C_Master_Transmit+0x1fe>
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
8000f6e: 68fb ldr r3, [r7, #12]
8000f70: 8d5b ldrh r3, [r3, #42] ; 0x2a
8000f72: b29b uxth r3, r3
8000f74: 2bff cmp r3, #255 ; 0xff
8000f76: d911 bls.n 8000f9c <HAL_I2C_Master_Transmit+0x184>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
8000f78: 68fb ldr r3, [r7, #12]
8000f7a: 22ff movs r2, #255 ; 0xff
8000f7c: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
8000f7e: 68fb ldr r3, [r7, #12]
8000f80: 8d1b ldrh r3, [r3, #40] ; 0x28
8000f82: b2da uxtb r2, r3
8000f84: 2380 movs r3, #128 ; 0x80
8000f86: 045c lsls r4, r3, #17
8000f88: 230a movs r3, #10
8000f8a: 18fb adds r3, r7, r3
8000f8c: 8819 ldrh r1, [r3, #0]
8000f8e: 68f8 ldr r0, [r7, #12]
8000f90: 2300 movs r3, #0
8000f92: 9300 str r3, [sp, #0]
8000f94: 0023 movs r3, r4
8000f96: f000 fbcb bl 8001730 <I2C_TransferConfig>
8000f9a: e012 b.n 8000fc2 <HAL_I2C_Master_Transmit+0x1aa>
I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
8000f9c: 68fb ldr r3, [r7, #12]
8000f9e: 8d5b ldrh r3, [r3, #42] ; 0x2a
8000fa0: b29a uxth r2, r3
8000fa2: 68fb ldr r3, [r7, #12]
8000fa4: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
8000fa6: 68fb ldr r3, [r7, #12]
8000fa8: 8d1b ldrh r3, [r3, #40] ; 0x28
8000faa: b2da uxtb r2, r3
8000fac: 2380 movs r3, #128 ; 0x80
8000fae: 049c lsls r4, r3, #18
8000fb0: 230a movs r3, #10
8000fb2: 18fb adds r3, r7, r3
8000fb4: 8819 ldrh r1, [r3, #0]
8000fb6: 68f8 ldr r0, [r7, #12]
8000fb8: 2300 movs r3, #0
8000fba: 9300 str r3, [sp, #0]
8000fbc: 0023 movs r3, r4
8000fbe: f000 fbb7 bl 8001730 <I2C_TransferConfig>
while (hi2c->XferCount > 0U)
8000fc2: 68fb ldr r3, [r7, #12]
8000fc4: 8d5b ldrh r3, [r3, #42] ; 0x2a
8000fc6: b29b uxth r3, r3
8000fc8: 2b00 cmp r3, #0
8000fca: d198 bne.n 8000efe <HAL_I2C_Master_Transmit+0xe6>
}
}
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8000fcc: 697a ldr r2, [r7, #20]
8000fce: 6ab9 ldr r1, [r7, #40] ; 0x28
8000fd0: 68fb ldr r3, [r7, #12]
8000fd2: 0018 movs r0, r3
8000fd4: f000 f9e6 bl 80013a4 <I2C_WaitOnSTOPFlagUntilTimeout>
8000fd8: 1e03 subs r3, r0, #0
8000fda: d001 beq.n 8000fe0 <HAL_I2C_Master_Transmit+0x1c8>
{
return HAL_ERROR;
8000fdc: 2301 movs r3, #1
8000fde: e01a b.n 8001016 <HAL_I2C_Master_Transmit+0x1fe>
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
8000fe0: 68fb ldr r3, [r7, #12]
8000fe2: 681b ldr r3, [r3, #0]
8000fe4: 2220 movs r2, #32
8000fe6: 61da str r2, [r3, #28]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
8000fe8: 68fb ldr r3, [r7, #12]
8000fea: 681b ldr r3, [r3, #0]
8000fec: 685a ldr r2, [r3, #4]
8000fee: 68fb ldr r3, [r7, #12]
8000ff0: 681b ldr r3, [r3, #0]
8000ff2: 490c ldr r1, [pc, #48] ; (8001024 <HAL_I2C_Master_Transmit+0x20c>)
8000ff4: 400a ands r2, r1
8000ff6: 605a str r2, [r3, #4]
hi2c->State = HAL_I2C_STATE_READY;
8000ff8: 68fb ldr r3, [r7, #12]
8000ffa: 2241 movs r2, #65 ; 0x41
8000ffc: 2120 movs r1, #32
8000ffe: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_NONE;
8001000: 68fb ldr r3, [r7, #12]
8001002: 2242 movs r2, #66 ; 0x42
8001004: 2100 movs r1, #0
8001006: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8001008: 68fb ldr r3, [r7, #12]
800100a: 2240 movs r2, #64 ; 0x40
800100c: 2100 movs r1, #0
800100e: 5499 strb r1, [r3, r2]
return HAL_OK;
8001010: 2300 movs r3, #0
8001012: e000 b.n 8001016 <HAL_I2C_Master_Transmit+0x1fe>
}
else
{
return HAL_BUSY;
8001014: 2302 movs r3, #2
}
}
8001016: 0018 movs r0, r3
8001018: 46bd mov sp, r7
800101a: b007 add sp, #28
800101c: bd90 pop {r4, r7, pc}
800101e: 46c0 nop ; (mov r8, r8)
8001020: 80002000 .word 0x80002000
8001024: fe00e800 .word 0xfe00e800
08001028 <HAL_I2C_Master_Receive>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout)
{
8001028: b590 push {r4, r7, lr}
800102a: b089 sub sp, #36 ; 0x24
800102c: af02 add r7, sp, #8
800102e: 60f8 str r0, [r7, #12]
8001030: 0008 movs r0, r1
8001032: 607a str r2, [r7, #4]
8001034: 0019 movs r1, r3
8001036: 230a movs r3, #10
8001038: 18fb adds r3, r7, r3
800103a: 1c02 adds r2, r0, #0
800103c: 801a strh r2, [r3, #0]
800103e: 2308 movs r3, #8
8001040: 18fb adds r3, r7, r3
8001042: 1c0a adds r2, r1, #0
8001044: 801a strh r2, [r3, #0]
uint32_t tickstart;
if (hi2c->State == HAL_I2C_STATE_READY)
8001046: 68fb ldr r3, [r7, #12]
8001048: 2241 movs r2, #65 ; 0x41
800104a: 5c9b ldrb r3, [r3, r2]
800104c: b2db uxtb r3, r3
800104e: 2b20 cmp r3, #32
8001050: d000 beq.n 8001054 <HAL_I2C_Master_Receive+0x2c>
8001052: e0e8 b.n 8001226 <HAL_I2C_Master_Receive+0x1fe>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8001054: 68fb ldr r3, [r7, #12]
8001056: 2240 movs r2, #64 ; 0x40
8001058: 5c9b ldrb r3, [r3, r2]
800105a: 2b01 cmp r3, #1
800105c: d101 bne.n 8001062 <HAL_I2C_Master_Receive+0x3a>
800105e: 2302 movs r3, #2
8001060: e0e2 b.n 8001228 <HAL_I2C_Master_Receive+0x200>
8001062: 68fb ldr r3, [r7, #12]
8001064: 2240 movs r2, #64 ; 0x40
8001066: 2101 movs r1, #1
8001068: 5499 strb r1, [r3, r2]
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
800106a: f7ff fbf5 bl 8000858 <HAL_GetTick>
800106e: 0003 movs r3, r0
8001070: 617b str r3, [r7, #20]
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
8001072: 2380 movs r3, #128 ; 0x80
8001074: 0219 lsls r1, r3, #8
8001076: 68f8 ldr r0, [r7, #12]
8001078: 697b ldr r3, [r7, #20]
800107a: 9300 str r3, [sp, #0]
800107c: 2319 movs r3, #25
800107e: 2201 movs r2, #1
8001080: f000 f8fc bl 800127c <I2C_WaitOnFlagUntilTimeout>
8001084: 1e03 subs r3, r0, #0
8001086: d001 beq.n 800108c <HAL_I2C_Master_Receive+0x64>
{
return HAL_ERROR;
8001088: 2301 movs r3, #1
800108a: e0cd b.n 8001228 <HAL_I2C_Master_Receive+0x200>
}
hi2c->State = HAL_I2C_STATE_BUSY_RX;
800108c: 68fb ldr r3, [r7, #12]
800108e: 2241 movs r2, #65 ; 0x41
8001090: 2122 movs r1, #34 ; 0x22
8001092: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_MASTER;
8001094: 68fb ldr r3, [r7, #12]
8001096: 2242 movs r2, #66 ; 0x42
8001098: 2110 movs r1, #16
800109a: 5499 strb r1, [r3, r2]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
800109c: 68fb ldr r3, [r7, #12]
800109e: 2200 movs r2, #0
80010a0: 645a str r2, [r3, #68] ; 0x44
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
80010a2: 68fb ldr r3, [r7, #12]
80010a4: 687a ldr r2, [r7, #4]
80010a6: 625a str r2, [r3, #36] ; 0x24
hi2c->XferCount = Size;
80010a8: 68fb ldr r3, [r7, #12]
80010aa: 2208 movs r2, #8
80010ac: 18ba adds r2, r7, r2
80010ae: 8812 ldrh r2, [r2, #0]
80010b0: 855a strh r2, [r3, #42] ; 0x2a
hi2c->XferISR = NULL;
80010b2: 68fb ldr r3, [r7, #12]
80010b4: 2200 movs r2, #0
80010b6: 635a str r2, [r3, #52] ; 0x34
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
80010b8: 68fb ldr r3, [r7, #12]
80010ba: 8d5b ldrh r3, [r3, #42] ; 0x2a
80010bc: b29b uxth r3, r3
80010be: 2bff cmp r3, #255 ; 0xff
80010c0: d911 bls.n 80010e6 <HAL_I2C_Master_Receive+0xbe>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
80010c2: 68fb ldr r3, [r7, #12]
80010c4: 22ff movs r2, #255 ; 0xff
80010c6: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
80010c8: 68fb ldr r3, [r7, #12]
80010ca: 8d1b ldrh r3, [r3, #40] ; 0x28
80010cc: b2da uxtb r2, r3
80010ce: 2380 movs r3, #128 ; 0x80
80010d0: 045c lsls r4, r3, #17
80010d2: 230a movs r3, #10
80010d4: 18fb adds r3, r7, r3
80010d6: 8819 ldrh r1, [r3, #0]
80010d8: 68f8 ldr r0, [r7, #12]
80010da: 4b55 ldr r3, [pc, #340] ; (8001230 <HAL_I2C_Master_Receive+0x208>)
80010dc: 9300 str r3, [sp, #0]
80010de: 0023 movs r3, r4
80010e0: f000 fb26 bl 8001730 <I2C_TransferConfig>
80010e4: e076 b.n 80011d4 <HAL_I2C_Master_Receive+0x1ac>
I2C_GENERATE_START_READ);
}
else
{
hi2c->XferSize = hi2c->XferCount;
80010e6: 68fb ldr r3, [r7, #12]
80010e8: 8d5b ldrh r3, [r3, #42] ; 0x2a
80010ea: b29a uxth r2, r3
80010ec: 68fb ldr r3, [r7, #12]
80010ee: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
80010f0: 68fb ldr r3, [r7, #12]
80010f2: 8d1b ldrh r3, [r3, #40] ; 0x28
80010f4: b2da uxtb r2, r3
80010f6: 2380 movs r3, #128 ; 0x80
80010f8: 049c lsls r4, r3, #18
80010fa: 230a movs r3, #10
80010fc: 18fb adds r3, r7, r3
80010fe: 8819 ldrh r1, [r3, #0]
8001100: 68f8 ldr r0, [r7, #12]
8001102: 4b4b ldr r3, [pc, #300] ; (8001230 <HAL_I2C_Master_Receive+0x208>)
8001104: 9300 str r3, [sp, #0]
8001106: 0023 movs r3, r4
8001108: f000 fb12 bl 8001730 <I2C_TransferConfig>
I2C_GENERATE_START_READ);
}
while (hi2c->XferCount > 0U)
800110c: e062 b.n 80011d4 <HAL_I2C_Master_Receive+0x1ac>
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
800110e: 697a ldr r2, [r7, #20]
8001110: 6ab9 ldr r1, [r7, #40] ; 0x28
8001112: 68fb ldr r3, [r7, #12]
8001114: 0018 movs r0, r3
8001116: f000 f989 bl 800142c <I2C_WaitOnRXNEFlagUntilTimeout>
800111a: 1e03 subs r3, r0, #0
800111c: d001 beq.n 8001122 <HAL_I2C_Master_Receive+0xfa>
{
return HAL_ERROR;
800111e: 2301 movs r3, #1
8001120: e082 b.n 8001228 <HAL_I2C_Master_Receive+0x200>
}
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
8001122: 68fb ldr r3, [r7, #12]
8001124: 681b ldr r3, [r3, #0]
8001126: 6a5a ldr r2, [r3, #36] ; 0x24
8001128: 68fb ldr r3, [r7, #12]
800112a: 6a5b ldr r3, [r3, #36] ; 0x24
800112c: b2d2 uxtb r2, r2
800112e: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8001130: 68fb ldr r3, [r7, #12]
8001132: 6a5b ldr r3, [r3, #36] ; 0x24
8001134: 1c5a adds r2, r3, #1
8001136: 68fb ldr r3, [r7, #12]
8001138: 625a str r2, [r3, #36] ; 0x24
hi2c->XferSize--;
800113a: 68fb ldr r3, [r7, #12]
800113c: 8d1b ldrh r3, [r3, #40] ; 0x28
800113e: 3b01 subs r3, #1
8001140: b29a uxth r2, r3
8001142: 68fb ldr r3, [r7, #12]
8001144: 851a strh r2, [r3, #40] ; 0x28
hi2c->XferCount--;
8001146: 68fb ldr r3, [r7, #12]
8001148: 8d5b ldrh r3, [r3, #42] ; 0x2a
800114a: b29b uxth r3, r3
800114c: 3b01 subs r3, #1
800114e: b29a uxth r2, r3
8001150: 68fb ldr r3, [r7, #12]
8001152: 855a strh r2, [r3, #42] ; 0x2a
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
8001154: 68fb ldr r3, [r7, #12]
8001156: 8d5b ldrh r3, [r3, #42] ; 0x2a
8001158: b29b uxth r3, r3
800115a: 2b00 cmp r3, #0
800115c: d03a beq.n 80011d4 <HAL_I2C_Master_Receive+0x1ac>
800115e: 68fb ldr r3, [r7, #12]
8001160: 8d1b ldrh r3, [r3, #40] ; 0x28
8001162: 2b00 cmp r3, #0
8001164: d136 bne.n 80011d4 <HAL_I2C_Master_Receive+0x1ac>
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
8001166: 6aba ldr r2, [r7, #40] ; 0x28
8001168: 68f8 ldr r0, [r7, #12]
800116a: 697b ldr r3, [r7, #20]
800116c: 9300 str r3, [sp, #0]
800116e: 0013 movs r3, r2
8001170: 2200 movs r2, #0
8001172: 2180 movs r1, #128 ; 0x80
8001174: f000 f882 bl 800127c <I2C_WaitOnFlagUntilTimeout>
8001178: 1e03 subs r3, r0, #0
800117a: d001 beq.n 8001180 <HAL_I2C_Master_Receive+0x158>
{
return HAL_ERROR;
800117c: 2301 movs r3, #1
800117e: e053 b.n 8001228 <HAL_I2C_Master_Receive+0x200>
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
8001180: 68fb ldr r3, [r7, #12]
8001182: 8d5b ldrh r3, [r3, #42] ; 0x2a
8001184: b29b uxth r3, r3
8001186: 2bff cmp r3, #255 ; 0xff
8001188: d911 bls.n 80011ae <HAL_I2C_Master_Receive+0x186>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
800118a: 68fb ldr r3, [r7, #12]
800118c: 22ff movs r2, #255 ; 0xff
800118e: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
8001190: 68fb ldr r3, [r7, #12]
8001192: 8d1b ldrh r3, [r3, #40] ; 0x28
8001194: b2da uxtb r2, r3
8001196: 2380 movs r3, #128 ; 0x80
8001198: 045c lsls r4, r3, #17
800119a: 230a movs r3, #10
800119c: 18fb adds r3, r7, r3
800119e: 8819 ldrh r1, [r3, #0]
80011a0: 68f8 ldr r0, [r7, #12]
80011a2: 2300 movs r3, #0
80011a4: 9300 str r3, [sp, #0]
80011a6: 0023 movs r3, r4
80011a8: f000 fac2 bl 8001730 <I2C_TransferConfig>
80011ac: e012 b.n 80011d4 <HAL_I2C_Master_Receive+0x1ac>
I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
80011ae: 68fb ldr r3, [r7, #12]
80011b0: 8d5b ldrh r3, [r3, #42] ; 0x2a
80011b2: b29a uxth r2, r3
80011b4: 68fb ldr r3, [r7, #12]
80011b6: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
80011b8: 68fb ldr r3, [r7, #12]
80011ba: 8d1b ldrh r3, [r3, #40] ; 0x28
80011bc: b2da uxtb r2, r3
80011be: 2380 movs r3, #128 ; 0x80
80011c0: 049c lsls r4, r3, #18
80011c2: 230a movs r3, #10
80011c4: 18fb adds r3, r7, r3
80011c6: 8819 ldrh r1, [r3, #0]
80011c8: 68f8 ldr r0, [r7, #12]
80011ca: 2300 movs r3, #0
80011cc: 9300 str r3, [sp, #0]
80011ce: 0023 movs r3, r4
80011d0: f000 faae bl 8001730 <I2C_TransferConfig>
while (hi2c->XferCount > 0U)
80011d4: 68fb ldr r3, [r7, #12]
80011d6: 8d5b ldrh r3, [r3, #42] ; 0x2a
80011d8: b29b uxth r3, r3
80011da: 2b00 cmp r3, #0
80011dc: d197 bne.n 800110e <HAL_I2C_Master_Receive+0xe6>
}
}
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
80011de: 697a ldr r2, [r7, #20]
80011e0: 6ab9 ldr r1, [r7, #40] ; 0x28
80011e2: 68fb ldr r3, [r7, #12]
80011e4: 0018 movs r0, r3
80011e6: f000 f8dd bl 80013a4 <I2C_WaitOnSTOPFlagUntilTimeout>
80011ea: 1e03 subs r3, r0, #0
80011ec: d001 beq.n 80011f2 <HAL_I2C_Master_Receive+0x1ca>
{
return HAL_ERROR;
80011ee: 2301 movs r3, #1
80011f0: e01a b.n 8001228 <HAL_I2C_Master_Receive+0x200>
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
80011f2: 68fb ldr r3, [r7, #12]
80011f4: 681b ldr r3, [r3, #0]
80011f6: 2220 movs r2, #32
80011f8: 61da str r2, [r3, #28]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
80011fa: 68fb ldr r3, [r7, #12]
80011fc: 681b ldr r3, [r3, #0]
80011fe: 685a ldr r2, [r3, #4]
8001200: 68fb ldr r3, [r7, #12]
8001202: 681b ldr r3, [r3, #0]
8001204: 490b ldr r1, [pc, #44] ; (8001234 <HAL_I2C_Master_Receive+0x20c>)
8001206: 400a ands r2, r1
8001208: 605a str r2, [r3, #4]
hi2c->State = HAL_I2C_STATE_READY;
800120a: 68fb ldr r3, [r7, #12]
800120c: 2241 movs r2, #65 ; 0x41
800120e: 2120 movs r1, #32
8001210: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_NONE;
8001212: 68fb ldr r3, [r7, #12]
8001214: 2242 movs r2, #66 ; 0x42
8001216: 2100 movs r1, #0
8001218: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800121a: 68fb ldr r3, [r7, #12]
800121c: 2240 movs r2, #64 ; 0x40
800121e: 2100 movs r1, #0
8001220: 5499 strb r1, [r3, r2]
return HAL_OK;
8001222: 2300 movs r3, #0
8001224: e000 b.n 8001228 <HAL_I2C_Master_Receive+0x200>
}
else
{
return HAL_BUSY;
8001226: 2302 movs r3, #2
}
}
8001228: 0018 movs r0, r3
800122a: 46bd mov sp, r7
800122c: b007 add sp, #28
800122e: bd90 pop {r4, r7, pc}
8001230: 80002400 .word 0x80002400
8001234: fe00e800 .word 0xfe00e800
08001238 <I2C_Flush_TXDR>:
* @brief I2C Tx data register flush process.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
{
8001238: b580 push {r7, lr}
800123a: b082 sub sp, #8
800123c: af00 add r7, sp, #0
800123e: 6078 str r0, [r7, #4]
/* If a pending TXIS flag is set */
/* Write a dummy data in TXDR to clear it */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
8001240: 687b ldr r3, [r7, #4]
8001242: 681b ldr r3, [r3, #0]
8001244: 699b ldr r3, [r3, #24]
8001246: 2202 movs r2, #2
8001248: 4013 ands r3, r2
800124a: 2b02 cmp r3, #2
800124c: d103 bne.n 8001256 <I2C_Flush_TXDR+0x1e>
{
hi2c->Instance->TXDR = 0x00U;
800124e: 687b ldr r3, [r7, #4]
8001250: 681b ldr r3, [r3, #0]
8001252: 2200 movs r2, #0
8001254: 629a str r2, [r3, #40] ; 0x28
}
/* Flush TX register if not empty */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
8001256: 687b ldr r3, [r7, #4]
8001258: 681b ldr r3, [r3, #0]
800125a: 699b ldr r3, [r3, #24]
800125c: 2201 movs r2, #1
800125e: 4013 ands r3, r2
8001260: 2b01 cmp r3, #1
8001262: d007 beq.n 8001274 <I2C_Flush_TXDR+0x3c>
{
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
8001264: 687b ldr r3, [r7, #4]
8001266: 681b ldr r3, [r3, #0]
8001268: 699a ldr r2, [r3, #24]
800126a: 687b ldr r3, [r7, #4]
800126c: 681b ldr r3, [r3, #0]
800126e: 2101 movs r1, #1
8001270: 430a orrs r2, r1
8001272: 619a str r2, [r3, #24]
}
}
8001274: 46c0 nop ; (mov r8, r8)
8001276: 46bd mov sp, r7
8001278: b002 add sp, #8
800127a: bd80 pop {r7, pc}
0800127c <I2C_WaitOnFlagUntilTimeout>:
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
uint32_t Timeout, uint32_t Tickstart)
{
800127c: b580 push {r7, lr}
800127e: b084 sub sp, #16
8001280: af00 add r7, sp, #0
8001282: 60f8 str r0, [r7, #12]
8001284: 60b9 str r1, [r7, #8]
8001286: 603b str r3, [r7, #0]
8001288: 1dfb adds r3, r7, #7
800128a: 701a strb r2, [r3, #0]
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
800128c: e030 b.n 80012f0 <I2C_WaitOnFlagUntilTimeout+0x74>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
800128e: 683b ldr r3, [r7, #0]
8001290: 3301 adds r3, #1
8001292: d02d beq.n 80012f0 <I2C_WaitOnFlagUntilTimeout+0x74>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8001294: f7ff fae0 bl 8000858 <HAL_GetTick>
8001298: 0002 movs r2, r0
800129a: 69bb ldr r3, [r7, #24]
800129c: 1ad3 subs r3, r2, r3
800129e: 683a ldr r2, [r7, #0]
80012a0: 429a cmp r2, r3
80012a2: d302 bcc.n 80012aa <I2C_WaitOnFlagUntilTimeout+0x2e>
80012a4: 683b ldr r3, [r7, #0]
80012a6: 2b00 cmp r3, #0
80012a8: d122 bne.n 80012f0 <I2C_WaitOnFlagUntilTimeout+0x74>
{
if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
80012aa: 68fb ldr r3, [r7, #12]
80012ac: 681b ldr r3, [r3, #0]
80012ae: 699b ldr r3, [r3, #24]
80012b0: 68ba ldr r2, [r7, #8]
80012b2: 4013 ands r3, r2
80012b4: 68ba ldr r2, [r7, #8]
80012b6: 1ad3 subs r3, r2, r3
80012b8: 425a negs r2, r3
80012ba: 4153 adcs r3, r2
80012bc: b2db uxtb r3, r3
80012be: 001a movs r2, r3
80012c0: 1dfb adds r3, r7, #7
80012c2: 781b ldrb r3, [r3, #0]
80012c4: 429a cmp r2, r3
80012c6: d113 bne.n 80012f0 <I2C_WaitOnFlagUntilTimeout+0x74>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
80012c8: 68fb ldr r3, [r7, #12]
80012ca: 6c5b ldr r3, [r3, #68] ; 0x44
80012cc: 2220 movs r2, #32
80012ce: 431a orrs r2, r3
80012d0: 68fb ldr r3, [r7, #12]
80012d2: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
80012d4: 68fb ldr r3, [r7, #12]
80012d6: 2241 movs r2, #65 ; 0x41
80012d8: 2120 movs r1, #32
80012da: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_NONE;
80012dc: 68fb ldr r3, [r7, #12]
80012de: 2242 movs r2, #66 ; 0x42
80012e0: 2100 movs r1, #0
80012e2: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80012e4: 68fb ldr r3, [r7, #12]
80012e6: 2240 movs r2, #64 ; 0x40
80012e8: 2100 movs r1, #0
80012ea: 5499 strb r1, [r3, r2]
return HAL_ERROR;
80012ec: 2301 movs r3, #1
80012ee: e00f b.n 8001310 <I2C_WaitOnFlagUntilTimeout+0x94>
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
80012f0: 68fb ldr r3, [r7, #12]
80012f2: 681b ldr r3, [r3, #0]
80012f4: 699b ldr r3, [r3, #24]
80012f6: 68ba ldr r2, [r7, #8]
80012f8: 4013 ands r3, r2
80012fa: 68ba ldr r2, [r7, #8]
80012fc: 1ad3 subs r3, r2, r3
80012fe: 425a negs r2, r3
8001300: 4153 adcs r3, r2
8001302: b2db uxtb r3, r3
8001304: 001a movs r2, r3
8001306: 1dfb adds r3, r7, #7
8001308: 781b ldrb r3, [r3, #0]
800130a: 429a cmp r2, r3
800130c: d0bf beq.n 800128e <I2C_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
800130e: 2300 movs r3, #0
}
8001310: 0018 movs r0, r3
8001312: 46bd mov sp, r7
8001314: b004 add sp, #16
8001316: bd80 pop {r7, pc}
08001318 <I2C_WaitOnTXISFlagUntilTimeout>:
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart)
{
8001318: b580 push {r7, lr}
800131a: b084 sub sp, #16
800131c: af00 add r7, sp, #0
800131e: 60f8 str r0, [r7, #12]
8001320: 60b9 str r1, [r7, #8]
8001322: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
8001324: e032 b.n 800138c <I2C_WaitOnTXISFlagUntilTimeout+0x74>
{
/* Check if an error is detected */
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
8001326: 687a ldr r2, [r7, #4]
8001328: 68b9 ldr r1, [r7, #8]
800132a: 68fb ldr r3, [r7, #12]
800132c: 0018 movs r0, r3
800132e: f000 f8ff bl 8001530 <I2C_IsErrorOccurred>
8001332: 1e03 subs r3, r0, #0
8001334: d001 beq.n 800133a <I2C_WaitOnTXISFlagUntilTimeout+0x22>
{
return HAL_ERROR;
8001336: 2301 movs r3, #1
8001338: e030 b.n 800139c <I2C_WaitOnTXISFlagUntilTimeout+0x84>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
800133a: 68bb ldr r3, [r7, #8]
800133c: 3301 adds r3, #1
800133e: d025 beq.n 800138c <I2C_WaitOnTXISFlagUntilTimeout+0x74>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8001340: f7ff fa8a bl 8000858 <HAL_GetTick>
8001344: 0002 movs r2, r0
8001346: 687b ldr r3, [r7, #4]
8001348: 1ad3 subs r3, r2, r3
800134a: 68ba ldr r2, [r7, #8]
800134c: 429a cmp r2, r3
800134e: d302 bcc.n 8001356 <I2C_WaitOnTXISFlagUntilTimeout+0x3e>
8001350: 68bb ldr r3, [r7, #8]
8001352: 2b00 cmp r3, #0
8001354: d11a bne.n 800138c <I2C_WaitOnTXISFlagUntilTimeout+0x74>
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
8001356: 68fb ldr r3, [r7, #12]
8001358: 681b ldr r3, [r3, #0]
800135a: 699b ldr r3, [r3, #24]
800135c: 2202 movs r2, #2
800135e: 4013 ands r3, r2
8001360: 2b02 cmp r3, #2
8001362: d013 beq.n 800138c <I2C_WaitOnTXISFlagUntilTimeout+0x74>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8001364: 68fb ldr r3, [r7, #12]
8001366: 6c5b ldr r3, [r3, #68] ; 0x44
8001368: 2220 movs r2, #32
800136a: 431a orrs r2, r3
800136c: 68fb ldr r3, [r7, #12]
800136e: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8001370: 68fb ldr r3, [r7, #12]
8001372: 2241 movs r2, #65 ; 0x41
8001374: 2120 movs r1, #32
8001376: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_NONE;
8001378: 68fb ldr r3, [r7, #12]
800137a: 2242 movs r2, #66 ; 0x42
800137c: 2100 movs r1, #0
800137e: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8001380: 68fb ldr r3, [r7, #12]
8001382: 2240 movs r2, #64 ; 0x40
8001384: 2100 movs r1, #0
8001386: 5499 strb r1, [r3, r2]
return HAL_ERROR;
8001388: 2301 movs r3, #1
800138a: e007 b.n 800139c <I2C_WaitOnTXISFlagUntilTimeout+0x84>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
800138c: 68fb ldr r3, [r7, #12]
800138e: 681b ldr r3, [r3, #0]
8001390: 699b ldr r3, [r3, #24]
8001392: 2202 movs r2, #2
8001394: 4013 ands r3, r2
8001396: 2b02 cmp r3, #2
8001398: d1c5 bne.n 8001326 <I2C_WaitOnTXISFlagUntilTimeout+0xe>
}
}
}
}
return HAL_OK;
800139a: 2300 movs r3, #0
}
800139c: 0018 movs r0, r3
800139e: 46bd mov sp, r7
80013a0: b004 add sp, #16
80013a2: bd80 pop {r7, pc}
080013a4 <I2C_WaitOnSTOPFlagUntilTimeout>:
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart)
{
80013a4: b580 push {r7, lr}
80013a6: b084 sub sp, #16
80013a8: af00 add r7, sp, #0
80013aa: 60f8 str r0, [r7, #12]
80013ac: 60b9 str r1, [r7, #8]
80013ae: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
80013b0: e02f b.n 8001412 <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
{
/* Check if an error is detected */
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
80013b2: 687a ldr r2, [r7, #4]
80013b4: 68b9 ldr r1, [r7, #8]
80013b6: 68fb ldr r3, [r7, #12]
80013b8: 0018 movs r0, r3
80013ba: f000 f8b9 bl 8001530 <I2C_IsErrorOccurred>
80013be: 1e03 subs r3, r0, #0
80013c0: d001 beq.n 80013c6 <I2C_WaitOnSTOPFlagUntilTimeout+0x22>
{
return HAL_ERROR;
80013c2: 2301 movs r3, #1
80013c4: e02d b.n 8001422 <I2C_WaitOnSTOPFlagUntilTimeout+0x7e>
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
80013c6: f7ff fa47 bl 8000858 <HAL_GetTick>
80013ca: 0002 movs r2, r0
80013cc: 687b ldr r3, [r7, #4]
80013ce: 1ad3 subs r3, r2, r3
80013d0: 68ba ldr r2, [r7, #8]
80013d2: 429a cmp r2, r3
80013d4: d302 bcc.n 80013dc <I2C_WaitOnSTOPFlagUntilTimeout+0x38>
80013d6: 68bb ldr r3, [r7, #8]
80013d8: 2b00 cmp r3, #0
80013da: d11a bne.n 8001412 <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
80013dc: 68fb ldr r3, [r7, #12]
80013de: 681b ldr r3, [r3, #0]
80013e0: 699b ldr r3, [r3, #24]
80013e2: 2220 movs r2, #32
80013e4: 4013 ands r3, r2
80013e6: 2b20 cmp r3, #32
80013e8: d013 beq.n 8001412 <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
80013ea: 68fb ldr r3, [r7, #12]
80013ec: 6c5b ldr r3, [r3, #68] ; 0x44
80013ee: 2220 movs r2, #32
80013f0: 431a orrs r2, r3
80013f2: 68fb ldr r3, [r7, #12]
80013f4: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
80013f6: 68fb ldr r3, [r7, #12]
80013f8: 2241 movs r2, #65 ; 0x41
80013fa: 2120 movs r1, #32
80013fc: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_NONE;
80013fe: 68fb ldr r3, [r7, #12]
8001400: 2242 movs r2, #66 ; 0x42
8001402: 2100 movs r1, #0
8001404: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8001406: 68fb ldr r3, [r7, #12]
8001408: 2240 movs r2, #64 ; 0x40
800140a: 2100 movs r1, #0
800140c: 5499 strb r1, [r3, r2]
return HAL_ERROR;
800140e: 2301 movs r3, #1
8001410: e007 b.n 8001422 <I2C_WaitOnSTOPFlagUntilTimeout+0x7e>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8001412: 68fb ldr r3, [r7, #12]
8001414: 681b ldr r3, [r3, #0]
8001416: 699b ldr r3, [r3, #24]
8001418: 2220 movs r2, #32
800141a: 4013 ands r3, r2
800141c: 2b20 cmp r3, #32
800141e: d1c8 bne.n 80013b2 <I2C_WaitOnSTOPFlagUntilTimeout+0xe>
}
}
}
return HAL_OK;
8001420: 2300 movs r3, #0
}
8001422: 0018 movs r0, r3
8001424: 46bd mov sp, r7
8001426: b004 add sp, #16
8001428: bd80 pop {r7, pc}
...
0800142c <I2C_WaitOnRXNEFlagUntilTimeout>:
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart)
{
800142c: b580 push {r7, lr}
800142e: b084 sub sp, #16
8001430: af00 add r7, sp, #0
8001432: 60f8 str r0, [r7, #12]
8001434: 60b9 str r1, [r7, #8]
8001436: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
8001438: e06b b.n 8001512 <I2C_WaitOnRXNEFlagUntilTimeout+0xe6>
{
/* Check if an error is detected */
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
800143a: 687a ldr r2, [r7, #4]
800143c: 68b9 ldr r1, [r7, #8]
800143e: 68fb ldr r3, [r7, #12]
8001440: 0018 movs r0, r3
8001442: f000 f875 bl 8001530 <I2C_IsErrorOccurred>
8001446: 1e03 subs r3, r0, #0
8001448: d001 beq.n 800144e <I2C_WaitOnRXNEFlagUntilTimeout+0x22>
{
return HAL_ERROR;
800144a: 2301 movs r3, #1
800144c: e069 b.n 8001522 <I2C_WaitOnRXNEFlagUntilTimeout+0xf6>
}
/* Check if a STOPF is detected */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
800144e: 68fb ldr r3, [r7, #12]
8001450: 681b ldr r3, [r3, #0]
8001452: 699b ldr r3, [r3, #24]
8001454: 2220 movs r2, #32
8001456: 4013 ands r3, r2
8001458: 2b20 cmp r3, #32
800145a: d138 bne.n 80014ce <I2C_WaitOnRXNEFlagUntilTimeout+0xa2>
{
/* Check if an RXNE is pending */
/* Store Last receive data if any */
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
800145c: 68fb ldr r3, [r7, #12]
800145e: 681b ldr r3, [r3, #0]
8001460: 699b ldr r3, [r3, #24]
8001462: 2204 movs r2, #4
8001464: 4013 ands r3, r2
8001466: 2b04 cmp r3, #4
8001468: d105 bne.n 8001476 <I2C_WaitOnRXNEFlagUntilTimeout+0x4a>
800146a: 68fb ldr r3, [r7, #12]
800146c: 8d1b ldrh r3, [r3, #40] ; 0x28
800146e: 2b00 cmp r3, #0
8001470: d001 beq.n 8001476 <I2C_WaitOnRXNEFlagUntilTimeout+0x4a>
{
/* Return HAL_OK */
/* The Reading of data from RXDR will be done in caller function */
return HAL_OK;
8001472: 2300 movs r3, #0
8001474: e055 b.n 8001522 <I2C_WaitOnRXNEFlagUntilTimeout+0xf6>
}
else
{
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
8001476: 68fb ldr r3, [r7, #12]
8001478: 681b ldr r3, [r3, #0]
800147a: 699b ldr r3, [r3, #24]
800147c: 2210 movs r2, #16
800147e: 4013 ands r3, r2
8001480: 2b10 cmp r3, #16
8001482: d107 bne.n 8001494 <I2C_WaitOnRXNEFlagUntilTimeout+0x68>
{
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8001484: 68fb ldr r3, [r7, #12]
8001486: 681b ldr r3, [r3, #0]
8001488: 2210 movs r2, #16
800148a: 61da str r2, [r3, #28]
hi2c->ErrorCode = HAL_I2C_ERROR_AF;
800148c: 68fb ldr r3, [r7, #12]
800148e: 2204 movs r2, #4
8001490: 645a str r2, [r3, #68] ; 0x44
8001492: e002 b.n 800149a <I2C_WaitOnRXNEFlagUntilTimeout+0x6e>
}
else
{
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8001494: 68fb ldr r3, [r7, #12]
8001496: 2200 movs r2, #0
8001498: 645a str r2, [r3, #68] ; 0x44
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
800149a: 68fb ldr r3, [r7, #12]
800149c: 681b ldr r3, [r3, #0]
800149e: 2220 movs r2, #32
80014a0: 61da str r2, [r3, #28]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
80014a2: 68fb ldr r3, [r7, #12]
80014a4: 681b ldr r3, [r3, #0]
80014a6: 685a ldr r2, [r3, #4]
80014a8: 68fb ldr r3, [r7, #12]
80014aa: 681b ldr r3, [r3, #0]
80014ac: 491f ldr r1, [pc, #124] ; (800152c <I2C_WaitOnRXNEFlagUntilTimeout+0x100>)
80014ae: 400a ands r2, r1
80014b0: 605a str r2, [r3, #4]
hi2c->State = HAL_I2C_STATE_READY;
80014b2: 68fb ldr r3, [r7, #12]
80014b4: 2241 movs r2, #65 ; 0x41
80014b6: 2120 movs r1, #32
80014b8: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_NONE;
80014ba: 68fb ldr r3, [r7, #12]
80014bc: 2242 movs r2, #66 ; 0x42
80014be: 2100 movs r1, #0
80014c0: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80014c2: 68fb ldr r3, [r7, #12]
80014c4: 2240 movs r2, #64 ; 0x40
80014c6: 2100 movs r1, #0
80014c8: 5499 strb r1, [r3, r2]
return HAL_ERROR;
80014ca: 2301 movs r3, #1
80014cc: e029 b.n 8001522 <I2C_WaitOnRXNEFlagUntilTimeout+0xf6>
}
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
80014ce: f7ff f9c3 bl 8000858 <HAL_GetTick>
80014d2: 0002 movs r2, r0
80014d4: 687b ldr r3, [r7, #4]
80014d6: 1ad3 subs r3, r2, r3
80014d8: 68ba ldr r2, [r7, #8]
80014da: 429a cmp r2, r3
80014dc: d302 bcc.n 80014e4 <I2C_WaitOnRXNEFlagUntilTimeout+0xb8>
80014de: 68bb ldr r3, [r7, #8]
80014e0: 2b00 cmp r3, #0
80014e2: d116 bne.n 8001512 <I2C_WaitOnRXNEFlagUntilTimeout+0xe6>
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
80014e4: 68fb ldr r3, [r7, #12]
80014e6: 681b ldr r3, [r3, #0]
80014e8: 699b ldr r3, [r3, #24]
80014ea: 2204 movs r2, #4
80014ec: 4013 ands r3, r2
80014ee: 2b04 cmp r3, #4
80014f0: d00f beq.n 8001512 <I2C_WaitOnRXNEFlagUntilTimeout+0xe6>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
80014f2: 68fb ldr r3, [r7, #12]
80014f4: 6c5b ldr r3, [r3, #68] ; 0x44
80014f6: 2220 movs r2, #32
80014f8: 431a orrs r2, r3
80014fa: 68fb ldr r3, [r7, #12]
80014fc: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
80014fe: 68fb ldr r3, [r7, #12]
8001500: 2241 movs r2, #65 ; 0x41
8001502: 2120 movs r1, #32
8001504: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8001506: 68fb ldr r3, [r7, #12]
8001508: 2240 movs r2, #64 ; 0x40
800150a: 2100 movs r1, #0
800150c: 5499 strb r1, [r3, r2]
return HAL_ERROR;
800150e: 2301 movs r3, #1
8001510: e007 b.n 8001522 <I2C_WaitOnRXNEFlagUntilTimeout+0xf6>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
8001512: 68fb ldr r3, [r7, #12]
8001514: 681b ldr r3, [r3, #0]
8001516: 699b ldr r3, [r3, #24]
8001518: 2204 movs r2, #4
800151a: 4013 ands r3, r2
800151c: 2b04 cmp r3, #4
800151e: d18c bne.n 800143a <I2C_WaitOnRXNEFlagUntilTimeout+0xe>
}
}
}
return HAL_OK;
8001520: 2300 movs r3, #0
}
8001522: 0018 movs r0, r3
8001524: 46bd mov sp, r7
8001526: b004 add sp, #16
8001528: bd80 pop {r7, pc}
800152a: 46c0 nop ; (mov r8, r8)
800152c: fe00e800 .word 0xfe00e800
08001530 <I2C_IsErrorOccurred>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8001530: b590 push {r4, r7, lr}
8001532: b08b sub sp, #44 ; 0x2c
8001534: af00 add r7, sp, #0
8001536: 60f8 str r0, [r7, #12]
8001538: 60b9 str r1, [r7, #8]
800153a: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
800153c: 2327 movs r3, #39 ; 0x27
800153e: 18fb adds r3, r7, r3
8001540: 2200 movs r2, #0
8001542: 701a strb r2, [r3, #0]
uint32_t itflag = hi2c->Instance->ISR;
8001544: 68fb ldr r3, [r7, #12]
8001546: 681b ldr r3, [r3, #0]
8001548: 699b ldr r3, [r3, #24]
800154a: 61bb str r3, [r7, #24]
uint32_t error_code = 0;
800154c: 2300 movs r3, #0
800154e: 623b str r3, [r7, #32]
uint32_t tickstart = Tickstart;
8001550: 687b ldr r3, [r7, #4]
8001552: 61fb str r3, [r7, #28]
uint32_t tmp1;
HAL_I2C_ModeTypeDef tmp2;
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
8001554: 69bb ldr r3, [r7, #24]
8001556: 2210 movs r2, #16
8001558: 4013 ands r3, r2
800155a: d100 bne.n 800155e <I2C_IsErrorOccurred+0x2e>
800155c: e082 b.n 8001664 <I2C_IsErrorOccurred+0x134>
{
/* Clear NACKF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
800155e: 68fb ldr r3, [r7, #12]
8001560: 681b ldr r3, [r3, #0]
8001562: 2210 movs r2, #16
8001564: 61da str r2, [r3, #28]
/* Wait until STOP Flag is set or timeout occurred */
/* AutoEnd should be initiate after AF */
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
8001566: e060 b.n 800162a <I2C_IsErrorOccurred+0xfa>
8001568: 2427 movs r4, #39 ; 0x27
800156a: 193b adds r3, r7, r4
800156c: 193a adds r2, r7, r4
800156e: 7812 ldrb r2, [r2, #0]
8001570: 701a strb r2, [r3, #0]
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8001572: 68bb ldr r3, [r7, #8]
8001574: 3301 adds r3, #1
8001576: d058 beq.n 800162a <I2C_IsErrorOccurred+0xfa>
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
8001578: f7ff f96e bl 8000858 <HAL_GetTick>
800157c: 0002 movs r2, r0
800157e: 69fb ldr r3, [r7, #28]
8001580: 1ad3 subs r3, r2, r3
8001582: 68ba ldr r2, [r7, #8]
8001584: 429a cmp r2, r3
8001586: d306 bcc.n 8001596 <I2C_IsErrorOccurred+0x66>
8001588: 193b adds r3, r7, r4
800158a: 193a adds r2, r7, r4
800158c: 7812 ldrb r2, [r2, #0]
800158e: 701a strb r2, [r3, #0]
8001590: 68bb ldr r3, [r7, #8]
8001592: 2b00 cmp r3, #0
8001594: d149 bne.n 800162a <I2C_IsErrorOccurred+0xfa>
{
tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
8001596: 68fb ldr r3, [r7, #12]
8001598: 681b ldr r3, [r3, #0]
800159a: 685a ldr r2, [r3, #4]
800159c: 2380 movs r3, #128 ; 0x80
800159e: 01db lsls r3, r3, #7
80015a0: 4013 ands r3, r2
80015a2: 617b str r3, [r7, #20]
tmp2 = hi2c->Mode;
80015a4: 2013 movs r0, #19
80015a6: 183b adds r3, r7, r0
80015a8: 68fa ldr r2, [r7, #12]
80015aa: 2142 movs r1, #66 ; 0x42
80015ac: 5c52 ldrb r2, [r2, r1]
80015ae: 701a strb r2, [r3, #0]
/* In case of I2C still busy, try to regenerate a STOP manually */
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
80015b0: 68fb ldr r3, [r7, #12]
80015b2: 681b ldr r3, [r3, #0]
80015b4: 699a ldr r2, [r3, #24]
80015b6: 2380 movs r3, #128 ; 0x80
80015b8: 021b lsls r3, r3, #8
80015ba: 401a ands r2, r3
80015bc: 2380 movs r3, #128 ; 0x80
80015be: 021b lsls r3, r3, #8
80015c0: 429a cmp r2, r3
80015c2: d126 bne.n 8001612 <I2C_IsErrorOccurred+0xe2>
80015c4: 697a ldr r2, [r7, #20]
80015c6: 2380 movs r3, #128 ; 0x80
80015c8: 01db lsls r3, r3, #7
80015ca: 429a cmp r2, r3
80015cc: d021 beq.n 8001612 <I2C_IsErrorOccurred+0xe2>
(tmp1 != I2C_CR2_STOP) && \
80015ce: 183b adds r3, r7, r0
80015d0: 781b ldrb r3, [r3, #0]
80015d2: 2b20 cmp r3, #32
80015d4: d01d beq.n 8001612 <I2C_IsErrorOccurred+0xe2>
(tmp2 != HAL_I2C_MODE_SLAVE))
{
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
80015d6: 68fb ldr r3, [r7, #12]
80015d8: 681b ldr r3, [r3, #0]
80015da: 685a ldr r2, [r3, #4]
80015dc: 68fb ldr r3, [r7, #12]
80015de: 681b ldr r3, [r3, #0]
80015e0: 2180 movs r1, #128 ; 0x80
80015e2: 01c9 lsls r1, r1, #7
80015e4: 430a orrs r2, r1
80015e6: 605a str r2, [r3, #4]
/* Update Tick with new reference */
tickstart = HAL_GetTick();
80015e8: f7ff f936 bl 8000858 <HAL_GetTick>
80015ec: 0003 movs r3, r0
80015ee: 61fb str r3, [r7, #28]
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
80015f0: e00f b.n 8001612 <I2C_IsErrorOccurred+0xe2>
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
80015f2: f7ff f931 bl 8000858 <HAL_GetTick>
80015f6: 0002 movs r2, r0
80015f8: 69fb ldr r3, [r7, #28]
80015fa: 1ad3 subs r3, r2, r3
80015fc: 2b19 cmp r3, #25
80015fe: d908 bls.n 8001612 <I2C_IsErrorOccurred+0xe2>
{
error_code |= HAL_I2C_ERROR_TIMEOUT;
8001600: 6a3b ldr r3, [r7, #32]
8001602: 2220 movs r2, #32
8001604: 4313 orrs r3, r2
8001606: 623b str r3, [r7, #32]
status = HAL_ERROR;
8001608: 2327 movs r3, #39 ; 0x27
800160a: 18fb adds r3, r7, r3
800160c: 2201 movs r2, #1
800160e: 701a strb r2, [r3, #0]
break;
8001610: e00b b.n 800162a <I2C_IsErrorOccurred+0xfa>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8001612: 68fb ldr r3, [r7, #12]
8001614: 681b ldr r3, [r3, #0]
8001616: 699b ldr r3, [r3, #24]
8001618: 2220 movs r2, #32
800161a: 4013 ands r3, r2
800161c: 2127 movs r1, #39 ; 0x27
800161e: 187a adds r2, r7, r1
8001620: 1879 adds r1, r7, r1
8001622: 7809 ldrb r1, [r1, #0]
8001624: 7011 strb r1, [r2, #0]
8001626: 2b20 cmp r3, #32
8001628: d1e3 bne.n 80015f2 <I2C_IsErrorOccurred+0xc2>
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
800162a: 68fb ldr r3, [r7, #12]
800162c: 681b ldr r3, [r3, #0]
800162e: 699b ldr r3, [r3, #24]
8001630: 2220 movs r2, #32
8001632: 4013 ands r3, r2
8001634: 2b20 cmp r3, #32
8001636: d004 beq.n 8001642 <I2C_IsErrorOccurred+0x112>
8001638: 2327 movs r3, #39 ; 0x27
800163a: 18fb adds r3, r7, r3
800163c: 781b ldrb r3, [r3, #0]
800163e: 2b00 cmp r3, #0
8001640: d092 beq.n 8001568 <I2C_IsErrorOccurred+0x38>
}
}
}
/* In case STOP Flag is detected, clear it */
if (status == HAL_OK)
8001642: 2327 movs r3, #39 ; 0x27
8001644: 18fb adds r3, r7, r3
8001646: 781b ldrb r3, [r3, #0]
8001648: 2b00 cmp r3, #0
800164a: d103 bne.n 8001654 <I2C_IsErrorOccurred+0x124>
{
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
800164c: 68fb ldr r3, [r7, #12]
800164e: 681b ldr r3, [r3, #0]
8001650: 2220 movs r2, #32
8001652: 61da str r2, [r3, #28]
}
error_code |= HAL_I2C_ERROR_AF;
8001654: 6a3b ldr r3, [r7, #32]
8001656: 2204 movs r2, #4
8001658: 4313 orrs r3, r2
800165a: 623b str r3, [r7, #32]
status = HAL_ERROR;
800165c: 2327 movs r3, #39 ; 0x27
800165e: 18fb adds r3, r7, r3
8001660: 2201 movs r2, #1
8001662: 701a strb r2, [r3, #0]
}
/* Refresh Content of Status register */
itflag = hi2c->Instance->ISR;
8001664: 68fb ldr r3, [r7, #12]
8001666: 681b ldr r3, [r3, #0]
8001668: 699b ldr r3, [r3, #24]
800166a: 61bb str r3, [r7, #24]
/* Then verify if an additional errors occurs */
/* Check if a Bus error occurred */
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
800166c: 69ba ldr r2, [r7, #24]
800166e: 2380 movs r3, #128 ; 0x80
8001670: 005b lsls r3, r3, #1
8001672: 4013 ands r3, r2
8001674: d00c beq.n 8001690 <I2C_IsErrorOccurred+0x160>
{
error_code |= HAL_I2C_ERROR_BERR;
8001676: 6a3b ldr r3, [r7, #32]
8001678: 2201 movs r2, #1
800167a: 4313 orrs r3, r2
800167c: 623b str r3, [r7, #32]
/* Clear BERR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
800167e: 68fb ldr r3, [r7, #12]
8001680: 681b ldr r3, [r3, #0]
8001682: 2280 movs r2, #128 ; 0x80
8001684: 0052 lsls r2, r2, #1
8001686: 61da str r2, [r3, #28]
status = HAL_ERROR;
8001688: 2327 movs r3, #39 ; 0x27
800168a: 18fb adds r3, r7, r3
800168c: 2201 movs r2, #1
800168e: 701a strb r2, [r3, #0]
}
/* Check if an Over-Run/Under-Run error occurred */
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
8001690: 69ba ldr r2, [r7, #24]
8001692: 2380 movs r3, #128 ; 0x80
8001694: 00db lsls r3, r3, #3
8001696: 4013 ands r3, r2
8001698: d00c beq.n 80016b4 <I2C_IsErrorOccurred+0x184>
{
error_code |= HAL_I2C_ERROR_OVR;
800169a: 6a3b ldr r3, [r7, #32]
800169c: 2208 movs r2, #8
800169e: 4313 orrs r3, r2
80016a0: 623b str r3, [r7, #32]
/* Clear OVR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
80016a2: 68fb ldr r3, [r7, #12]
80016a4: 681b ldr r3, [r3, #0]
80016a6: 2280 movs r2, #128 ; 0x80
80016a8: 00d2 lsls r2, r2, #3
80016aa: 61da str r2, [r3, #28]
status = HAL_ERROR;
80016ac: 2327 movs r3, #39 ; 0x27
80016ae: 18fb adds r3, r7, r3
80016b0: 2201 movs r2, #1
80016b2: 701a strb r2, [r3, #0]
}
/* Check if an Arbitration Loss error occurred */
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
80016b4: 69ba ldr r2, [r7, #24]
80016b6: 2380 movs r3, #128 ; 0x80
80016b8: 009b lsls r3, r3, #2
80016ba: 4013 ands r3, r2
80016bc: d00c beq.n 80016d8 <I2C_IsErrorOccurred+0x1a8>
{
error_code |= HAL_I2C_ERROR_ARLO;
80016be: 6a3b ldr r3, [r7, #32]
80016c0: 2202 movs r2, #2
80016c2: 4313 orrs r3, r2
80016c4: 623b str r3, [r7, #32]
/* Clear ARLO flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
80016c6: 68fb ldr r3, [r7, #12]
80016c8: 681b ldr r3, [r3, #0]
80016ca: 2280 movs r2, #128 ; 0x80
80016cc: 0092 lsls r2, r2, #2
80016ce: 61da str r2, [r3, #28]
status = HAL_ERROR;
80016d0: 2327 movs r3, #39 ; 0x27
80016d2: 18fb adds r3, r7, r3
80016d4: 2201 movs r2, #1
80016d6: 701a strb r2, [r3, #0]
}
if (status != HAL_OK)
80016d8: 2327 movs r3, #39 ; 0x27
80016da: 18fb adds r3, r7, r3
80016dc: 781b ldrb r3, [r3, #0]
80016de: 2b00 cmp r3, #0
80016e0: d01d beq.n 800171e <I2C_IsErrorOccurred+0x1ee>
{
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
80016e2: 68fb ldr r3, [r7, #12]
80016e4: 0018 movs r0, r3
80016e6: f7ff fda7 bl 8001238 <I2C_Flush_TXDR>
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
80016ea: 68fb ldr r3, [r7, #12]
80016ec: 681b ldr r3, [r3, #0]
80016ee: 685a ldr r2, [r3, #4]
80016f0: 68fb ldr r3, [r7, #12]
80016f2: 681b ldr r3, [r3, #0]
80016f4: 490d ldr r1, [pc, #52] ; (800172c <I2C_IsErrorOccurred+0x1fc>)
80016f6: 400a ands r2, r1
80016f8: 605a str r2, [r3, #4]
hi2c->ErrorCode |= error_code;
80016fa: 68fb ldr r3, [r7, #12]
80016fc: 6c5a ldr r2, [r3, #68] ; 0x44
80016fe: 6a3b ldr r3, [r7, #32]
8001700: 431a orrs r2, r3
8001702: 68fb ldr r3, [r7, #12]
8001704: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8001706: 68fb ldr r3, [r7, #12]
8001708: 2241 movs r2, #65 ; 0x41
800170a: 2120 movs r1, #32
800170c: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_NONE;
800170e: 68fb ldr r3, [r7, #12]
8001710: 2242 movs r2, #66 ; 0x42
8001712: 2100 movs r1, #0
8001714: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8001716: 68fb ldr r3, [r7, #12]
8001718: 2240 movs r2, #64 ; 0x40
800171a: 2100 movs r1, #0
800171c: 5499 strb r1, [r3, r2]
}
return status;
800171e: 2327 movs r3, #39 ; 0x27
8001720: 18fb adds r3, r7, r3
8001722: 781b ldrb r3, [r3, #0]
}
8001724: 0018 movs r0, r3
8001726: 46bd mov sp, r7
8001728: b00b add sp, #44 ; 0x2c
800172a: bd90 pop {r4, r7, pc}
800172c: fe00e800 .word 0xfe00e800
08001730 <I2C_TransferConfig>:
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
uint32_t Request)
{
8001730: b590 push {r4, r7, lr}
8001732: b087 sub sp, #28
8001734: af00 add r7, sp, #0
8001736: 60f8 str r0, [r7, #12]
8001738: 0008 movs r0, r1
800173a: 0011 movs r1, r2
800173c: 607b str r3, [r7, #4]
800173e: 240a movs r4, #10
8001740: 193b adds r3, r7, r4
8001742: 1c02 adds r2, r0, #0
8001744: 801a strh r2, [r3, #0]
8001746: 2009 movs r0, #9
8001748: 183b adds r3, r7, r0
800174a: 1c0a adds r2, r1, #0
800174c: 701a strb r2, [r3, #0]
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request));
/* Declaration of tmp to prevent undefined behavior of volatile usage */
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
800174e: 193b adds r3, r7, r4
8001750: 881b ldrh r3, [r3, #0]
8001752: 059b lsls r3, r3, #22
8001754: 0d9a lsrs r2, r3, #22
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
8001756: 183b adds r3, r7, r0
8001758: 781b ldrb r3, [r3, #0]
800175a: 0419 lsls r1, r3, #16
800175c: 23ff movs r3, #255 ; 0xff
800175e: 041b lsls r3, r3, #16
8001760: 400b ands r3, r1
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
8001762: 431a orrs r2, r3
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
8001764: 687b ldr r3, [r7, #4]
8001766: 431a orrs r2, r3
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
8001768: 6abb ldr r3, [r7, #40] ; 0x28
800176a: 4313 orrs r3, r2
800176c: 005b lsls r3, r3, #1
800176e: 085b lsrs r3, r3, #1
8001770: 617b str r3, [r7, #20]
(uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
/* update CR2 register */
MODIFY_REG(hi2c->Instance->CR2, \
8001772: 68fb ldr r3, [r7, #12]
8001774: 681b ldr r3, [r3, #0]
8001776: 685b ldr r3, [r3, #4]
8001778: 6aba ldr r2, [r7, #40] ; 0x28
800177a: 0d51 lsrs r1, r2, #21
800177c: 2280 movs r2, #128 ; 0x80
800177e: 00d2 lsls r2, r2, #3
8001780: 400a ands r2, r1
8001782: 4907 ldr r1, [pc, #28] ; (80017a0 <I2C_TransferConfig+0x70>)
8001784: 430a orrs r2, r1
8001786: 43d2 mvns r2, r2
8001788: 401a ands r2, r3
800178a: 0011 movs r1, r2
800178c: 68fb ldr r3, [r7, #12]
800178e: 681b ldr r3, [r3, #0]
8001790: 697a ldr r2, [r7, #20]
8001792: 430a orrs r2, r1
8001794: 605a str r2, [r3, #4]
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
I2C_CR2_START | I2C_CR2_STOP)), tmp);
}
8001796: 46c0 nop ; (mov r8, r8)
8001798: 46bd mov sp, r7
800179a: b007 add sp, #28
800179c: bd90 pop {r4, r7, pc}
800179e: 46c0 nop ; (mov r8, r8)
80017a0: 03ff63ff .word 0x03ff63ff
080017a4 <HAL_I2CEx_ConfigAnalogFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
80017a4: b580 push {r7, lr}
80017a6: b082 sub sp, #8
80017a8: af00 add r7, sp, #0
80017aa: 6078 str r0, [r7, #4]
80017ac: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
80017ae: 687b ldr r3, [r7, #4]
80017b0: 2241 movs r2, #65 ; 0x41
80017b2: 5c9b ldrb r3, [r3, r2]
80017b4: b2db uxtb r3, r3
80017b6: 2b20 cmp r3, #32
80017b8: d138 bne.n 800182c <HAL_I2CEx_ConfigAnalogFilter+0x88>
{
/* Process Locked */
__HAL_LOCK(hi2c);
80017ba: 687b ldr r3, [r7, #4]
80017bc: 2240 movs r2, #64 ; 0x40
80017be: 5c9b ldrb r3, [r3, r2]
80017c0: 2b01 cmp r3, #1
80017c2: d101 bne.n 80017c8 <HAL_I2CEx_ConfigAnalogFilter+0x24>
80017c4: 2302 movs r3, #2
80017c6: e032 b.n 800182e <HAL_I2CEx_ConfigAnalogFilter+0x8a>
80017c8: 687b ldr r3, [r7, #4]
80017ca: 2240 movs r2, #64 ; 0x40
80017cc: 2101 movs r1, #1
80017ce: 5499 strb r1, [r3, r2]
hi2c->State = HAL_I2C_STATE_BUSY;
80017d0: 687b ldr r3, [r7, #4]
80017d2: 2241 movs r2, #65 ; 0x41
80017d4: 2124 movs r1, #36 ; 0x24
80017d6: 5499 strb r1, [r3, r2]
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
80017d8: 687b ldr r3, [r7, #4]
80017da: 681b ldr r3, [r3, #0]
80017dc: 681a ldr r2, [r3, #0]
80017de: 687b ldr r3, [r7, #4]
80017e0: 681b ldr r3, [r3, #0]
80017e2: 2101 movs r1, #1
80017e4: 438a bics r2, r1
80017e6: 601a str r2, [r3, #0]
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
80017e8: 687b ldr r3, [r7, #4]
80017ea: 681b ldr r3, [r3, #0]
80017ec: 681a ldr r2, [r3, #0]
80017ee: 687b ldr r3, [r7, #4]
80017f0: 681b ldr r3, [r3, #0]
80017f2: 4911 ldr r1, [pc, #68] ; (8001838 <HAL_I2CEx_ConfigAnalogFilter+0x94>)
80017f4: 400a ands r2, r1
80017f6: 601a str r2, [r3, #0]
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
80017f8: 687b ldr r3, [r7, #4]
80017fa: 681b ldr r3, [r3, #0]
80017fc: 6819 ldr r1, [r3, #0]
80017fe: 687b ldr r3, [r7, #4]
8001800: 681b ldr r3, [r3, #0]
8001802: 683a ldr r2, [r7, #0]
8001804: 430a orrs r2, r1
8001806: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
8001808: 687b ldr r3, [r7, #4]
800180a: 681b ldr r3, [r3, #0]
800180c: 681a ldr r2, [r3, #0]
800180e: 687b ldr r3, [r7, #4]
8001810: 681b ldr r3, [r3, #0]
8001812: 2101 movs r1, #1
8001814: 430a orrs r2, r1
8001816: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
8001818: 687b ldr r3, [r7, #4]
800181a: 2241 movs r2, #65 ; 0x41
800181c: 2120 movs r1, #32
800181e: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8001820: 687b ldr r3, [r7, #4]
8001822: 2240 movs r2, #64 ; 0x40
8001824: 2100 movs r1, #0
8001826: 5499 strb r1, [r3, r2]
return HAL_OK;
8001828: 2300 movs r3, #0
800182a: e000 b.n 800182e <HAL_I2CEx_ConfigAnalogFilter+0x8a>
}
else
{
return HAL_BUSY;
800182c: 2302 movs r3, #2
}
}
800182e: 0018 movs r0, r3
8001830: 46bd mov sp, r7
8001832: b002 add sp, #8
8001834: bd80 pop {r7, pc}
8001836: 46c0 nop ; (mov r8, r8)
8001838: ffffefff .word 0xffffefff
0800183c <HAL_I2CEx_ConfigDigitalFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
800183c: b580 push {r7, lr}
800183e: b084 sub sp, #16
8001840: af00 add r7, sp, #0
8001842: 6078 str r0, [r7, #4]
8001844: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
8001846: 687b ldr r3, [r7, #4]
8001848: 2241 movs r2, #65 ; 0x41
800184a: 5c9b ldrb r3, [r3, r2]
800184c: b2db uxtb r3, r3
800184e: 2b20 cmp r3, #32
8001850: d139 bne.n 80018c6 <HAL_I2CEx_ConfigDigitalFilter+0x8a>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8001852: 687b ldr r3, [r7, #4]
8001854: 2240 movs r2, #64 ; 0x40
8001856: 5c9b ldrb r3, [r3, r2]
8001858: 2b01 cmp r3, #1
800185a: d101 bne.n 8001860 <HAL_I2CEx_ConfigDigitalFilter+0x24>
800185c: 2302 movs r3, #2
800185e: e033 b.n 80018c8 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
8001860: 687b ldr r3, [r7, #4]
8001862: 2240 movs r2, #64 ; 0x40
8001864: 2101 movs r1, #1
8001866: 5499 strb r1, [r3, r2]
hi2c->State = HAL_I2C_STATE_BUSY;
8001868: 687b ldr r3, [r7, #4]
800186a: 2241 movs r2, #65 ; 0x41
800186c: 2124 movs r1, #36 ; 0x24
800186e: 5499 strb r1, [r3, r2]
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8001870: 687b ldr r3, [r7, #4]
8001872: 681b ldr r3, [r3, #0]
8001874: 681a ldr r2, [r3, #0]
8001876: 687b ldr r3, [r7, #4]
8001878: 681b ldr r3, [r3, #0]
800187a: 2101 movs r1, #1
800187c: 438a bics r2, r1
800187e: 601a str r2, [r3, #0]
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
8001880: 687b ldr r3, [r7, #4]
8001882: 681b ldr r3, [r3, #0]
8001884: 681b ldr r3, [r3, #0]
8001886: 60fb str r3, [r7, #12]
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
8001888: 68fb ldr r3, [r7, #12]
800188a: 4a11 ldr r2, [pc, #68] ; (80018d0 <HAL_I2CEx_ConfigDigitalFilter+0x94>)
800188c: 4013 ands r3, r2
800188e: 60fb str r3, [r7, #12]
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
8001890: 683b ldr r3, [r7, #0]
8001892: 021b lsls r3, r3, #8
8001894: 68fa ldr r2, [r7, #12]
8001896: 4313 orrs r3, r2
8001898: 60fb str r3, [r7, #12]
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
800189a: 687b ldr r3, [r7, #4]
800189c: 681b ldr r3, [r3, #0]
800189e: 68fa ldr r2, [r7, #12]
80018a0: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
80018a2: 687b ldr r3, [r7, #4]
80018a4: 681b ldr r3, [r3, #0]
80018a6: 681a ldr r2, [r3, #0]
80018a8: 687b ldr r3, [r7, #4]
80018aa: 681b ldr r3, [r3, #0]
80018ac: 2101 movs r1, #1
80018ae: 430a orrs r2, r1
80018b0: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
80018b2: 687b ldr r3, [r7, #4]
80018b4: 2241 movs r2, #65 ; 0x41
80018b6: 2120 movs r1, #32
80018b8: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80018ba: 687b ldr r3, [r7, #4]
80018bc: 2240 movs r2, #64 ; 0x40
80018be: 2100 movs r1, #0
80018c0: 5499 strb r1, [r3, r2]
return HAL_OK;
80018c2: 2300 movs r3, #0
80018c4: e000 b.n 80018c8 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
}
else
{
return HAL_BUSY;
80018c6: 2302 movs r3, #2
}
}
80018c8: 0018 movs r0, r3
80018ca: 46bd mov sp, r7
80018cc: b004 add sp, #16
80018ce: bd80 pop {r7, pc}
80018d0: fffff0ff .word 0xfffff0ff
080018d4 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
80018d4: b580 push {r7, lr}
80018d6: b088 sub sp, #32
80018d8: af00 add r7, sp, #0
80018da: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
uint32_t pll_config2;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
80018dc: 687b ldr r3, [r7, #4]
80018de: 2b00 cmp r3, #0
80018e0: d102 bne.n 80018e8 <HAL_RCC_OscConfig+0x14>
{
return HAL_ERROR;
80018e2: 2301 movs r3, #1
80018e4: f000 fb76 bl 8001fd4 <HAL_RCC_OscConfig+0x700>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
80018e8: 687b ldr r3, [r7, #4]
80018ea: 681b ldr r3, [r3, #0]
80018ec: 2201 movs r2, #1
80018ee: 4013 ands r3, r2
80018f0: d100 bne.n 80018f4 <HAL_RCC_OscConfig+0x20>
80018f2: e08e b.n 8001a12 <HAL_RCC_OscConfig+0x13e>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
80018f4: 4bc5 ldr r3, [pc, #788] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
80018f6: 685b ldr r3, [r3, #4]
80018f8: 220c movs r2, #12
80018fa: 4013 ands r3, r2
80018fc: 2b04 cmp r3, #4
80018fe: d00e beq.n 800191e <HAL_RCC_OscConfig+0x4a>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8001900: 4bc2 ldr r3, [pc, #776] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001902: 685b ldr r3, [r3, #4]
8001904: 220c movs r2, #12
8001906: 4013 ands r3, r2
8001908: 2b08 cmp r3, #8
800190a: d117 bne.n 800193c <HAL_RCC_OscConfig+0x68>
800190c: 4bbf ldr r3, [pc, #764] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
800190e: 685a ldr r2, [r3, #4]
8001910: 23c0 movs r3, #192 ; 0xc0
8001912: 025b lsls r3, r3, #9
8001914: 401a ands r2, r3
8001916: 2380 movs r3, #128 ; 0x80
8001918: 025b lsls r3, r3, #9
800191a: 429a cmp r2, r3
800191c: d10e bne.n 800193c <HAL_RCC_OscConfig+0x68>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
800191e: 4bbb ldr r3, [pc, #748] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001920: 681a ldr r2, [r3, #0]
8001922: 2380 movs r3, #128 ; 0x80
8001924: 029b lsls r3, r3, #10
8001926: 4013 ands r3, r2
8001928: d100 bne.n 800192c <HAL_RCC_OscConfig+0x58>
800192a: e071 b.n 8001a10 <HAL_RCC_OscConfig+0x13c>
800192c: 687b ldr r3, [r7, #4]
800192e: 685b ldr r3, [r3, #4]
8001930: 2b00 cmp r3, #0
8001932: d000 beq.n 8001936 <HAL_RCC_OscConfig+0x62>
8001934: e06c b.n 8001a10 <HAL_RCC_OscConfig+0x13c>
{
return HAL_ERROR;
8001936: 2301 movs r3, #1
8001938: f000 fb4c bl 8001fd4 <HAL_RCC_OscConfig+0x700>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
800193c: 687b ldr r3, [r7, #4]
800193e: 685b ldr r3, [r3, #4]
8001940: 2b01 cmp r3, #1
8001942: d107 bne.n 8001954 <HAL_RCC_OscConfig+0x80>
8001944: 4bb1 ldr r3, [pc, #708] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001946: 681a ldr r2, [r3, #0]
8001948: 4bb0 ldr r3, [pc, #704] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
800194a: 2180 movs r1, #128 ; 0x80
800194c: 0249 lsls r1, r1, #9
800194e: 430a orrs r2, r1
8001950: 601a str r2, [r3, #0]
8001952: e02f b.n 80019b4 <HAL_RCC_OscConfig+0xe0>
8001954: 687b ldr r3, [r7, #4]
8001956: 685b ldr r3, [r3, #4]
8001958: 2b00 cmp r3, #0
800195a: d10c bne.n 8001976 <HAL_RCC_OscConfig+0xa2>
800195c: 4bab ldr r3, [pc, #684] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
800195e: 681a ldr r2, [r3, #0]
8001960: 4baa ldr r3, [pc, #680] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001962: 49ab ldr r1, [pc, #684] ; (8001c10 <HAL_RCC_OscConfig+0x33c>)
8001964: 400a ands r2, r1
8001966: 601a str r2, [r3, #0]
8001968: 4ba8 ldr r3, [pc, #672] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
800196a: 681a ldr r2, [r3, #0]
800196c: 4ba7 ldr r3, [pc, #668] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
800196e: 49a9 ldr r1, [pc, #676] ; (8001c14 <HAL_RCC_OscConfig+0x340>)
8001970: 400a ands r2, r1
8001972: 601a str r2, [r3, #0]
8001974: e01e b.n 80019b4 <HAL_RCC_OscConfig+0xe0>
8001976: 687b ldr r3, [r7, #4]
8001978: 685b ldr r3, [r3, #4]
800197a: 2b05 cmp r3, #5
800197c: d10e bne.n 800199c <HAL_RCC_OscConfig+0xc8>
800197e: 4ba3 ldr r3, [pc, #652] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001980: 681a ldr r2, [r3, #0]
8001982: 4ba2 ldr r3, [pc, #648] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001984: 2180 movs r1, #128 ; 0x80
8001986: 02c9 lsls r1, r1, #11
8001988: 430a orrs r2, r1
800198a: 601a str r2, [r3, #0]
800198c: 4b9f ldr r3, [pc, #636] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
800198e: 681a ldr r2, [r3, #0]
8001990: 4b9e ldr r3, [pc, #632] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001992: 2180 movs r1, #128 ; 0x80
8001994: 0249 lsls r1, r1, #9
8001996: 430a orrs r2, r1
8001998: 601a str r2, [r3, #0]
800199a: e00b b.n 80019b4 <HAL_RCC_OscConfig+0xe0>
800199c: 4b9b ldr r3, [pc, #620] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
800199e: 681a ldr r2, [r3, #0]
80019a0: 4b9a ldr r3, [pc, #616] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
80019a2: 499b ldr r1, [pc, #620] ; (8001c10 <HAL_RCC_OscConfig+0x33c>)
80019a4: 400a ands r2, r1
80019a6: 601a str r2, [r3, #0]
80019a8: 4b98 ldr r3, [pc, #608] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
80019aa: 681a ldr r2, [r3, #0]
80019ac: 4b97 ldr r3, [pc, #604] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
80019ae: 4999 ldr r1, [pc, #612] ; (8001c14 <HAL_RCC_OscConfig+0x340>)
80019b0: 400a ands r2, r1
80019b2: 601a str r2, [r3, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
80019b4: 687b ldr r3, [r7, #4]
80019b6: 685b ldr r3, [r3, #4]
80019b8: 2b00 cmp r3, #0
80019ba: d014 beq.n 80019e6 <HAL_RCC_OscConfig+0x112>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80019bc: f7fe ff4c bl 8000858 <HAL_GetTick>
80019c0: 0003 movs r3, r0
80019c2: 61bb str r3, [r7, #24]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80019c4: e008 b.n 80019d8 <HAL_RCC_OscConfig+0x104>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
80019c6: f7fe ff47 bl 8000858 <HAL_GetTick>
80019ca: 0002 movs r2, r0
80019cc: 69bb ldr r3, [r7, #24]
80019ce: 1ad3 subs r3, r2, r3
80019d0: 2b64 cmp r3, #100 ; 0x64
80019d2: d901 bls.n 80019d8 <HAL_RCC_OscConfig+0x104>
{
return HAL_TIMEOUT;
80019d4: 2303 movs r3, #3
80019d6: e2fd b.n 8001fd4 <HAL_RCC_OscConfig+0x700>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80019d8: 4b8c ldr r3, [pc, #560] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
80019da: 681a ldr r2, [r3, #0]
80019dc: 2380 movs r3, #128 ; 0x80
80019de: 029b lsls r3, r3, #10
80019e0: 4013 ands r3, r2
80019e2: d0f0 beq.n 80019c6 <HAL_RCC_OscConfig+0xf2>
80019e4: e015 b.n 8001a12 <HAL_RCC_OscConfig+0x13e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80019e6: f7fe ff37 bl 8000858 <HAL_GetTick>
80019ea: 0003 movs r3, r0
80019ec: 61bb str r3, [r7, #24]
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80019ee: e008 b.n 8001a02 <HAL_RCC_OscConfig+0x12e>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
80019f0: f7fe ff32 bl 8000858 <HAL_GetTick>
80019f4: 0002 movs r2, r0
80019f6: 69bb ldr r3, [r7, #24]
80019f8: 1ad3 subs r3, r2, r3
80019fa: 2b64 cmp r3, #100 ; 0x64
80019fc: d901 bls.n 8001a02 <HAL_RCC_OscConfig+0x12e>
{
return HAL_TIMEOUT;
80019fe: 2303 movs r3, #3
8001a00: e2e8 b.n 8001fd4 <HAL_RCC_OscConfig+0x700>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8001a02: 4b82 ldr r3, [pc, #520] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001a04: 681a ldr r2, [r3, #0]
8001a06: 2380 movs r3, #128 ; 0x80
8001a08: 029b lsls r3, r3, #10
8001a0a: 4013 ands r3, r2
8001a0c: d1f0 bne.n 80019f0 <HAL_RCC_OscConfig+0x11c>
8001a0e: e000 b.n 8001a12 <HAL_RCC_OscConfig+0x13e>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001a10: 46c0 nop ; (mov r8, r8)
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8001a12: 687b ldr r3, [r7, #4]
8001a14: 681b ldr r3, [r3, #0]
8001a16: 2202 movs r2, #2
8001a18: 4013 ands r3, r2
8001a1a: d100 bne.n 8001a1e <HAL_RCC_OscConfig+0x14a>
8001a1c: e06c b.n 8001af8 <HAL_RCC_OscConfig+0x224>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8001a1e: 4b7b ldr r3, [pc, #492] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001a20: 685b ldr r3, [r3, #4]
8001a22: 220c movs r2, #12
8001a24: 4013 ands r3, r2
8001a26: d00e beq.n 8001a46 <HAL_RCC_OscConfig+0x172>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
8001a28: 4b78 ldr r3, [pc, #480] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001a2a: 685b ldr r3, [r3, #4]
8001a2c: 220c movs r2, #12
8001a2e: 4013 ands r3, r2
8001a30: 2b08 cmp r3, #8
8001a32: d11f bne.n 8001a74 <HAL_RCC_OscConfig+0x1a0>
8001a34: 4b75 ldr r3, [pc, #468] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001a36: 685a ldr r2, [r3, #4]
8001a38: 23c0 movs r3, #192 ; 0xc0
8001a3a: 025b lsls r3, r3, #9
8001a3c: 401a ands r2, r3
8001a3e: 2380 movs r3, #128 ; 0x80
8001a40: 021b lsls r3, r3, #8
8001a42: 429a cmp r2, r3
8001a44: d116 bne.n 8001a74 <HAL_RCC_OscConfig+0x1a0>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8001a46: 4b71 ldr r3, [pc, #452] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001a48: 681b ldr r3, [r3, #0]
8001a4a: 2202 movs r2, #2
8001a4c: 4013 ands r3, r2
8001a4e: d005 beq.n 8001a5c <HAL_RCC_OscConfig+0x188>
8001a50: 687b ldr r3, [r7, #4]
8001a52: 68db ldr r3, [r3, #12]
8001a54: 2b01 cmp r3, #1
8001a56: d001 beq.n 8001a5c <HAL_RCC_OscConfig+0x188>
{
return HAL_ERROR;
8001a58: 2301 movs r3, #1
8001a5a: e2bb b.n 8001fd4 <HAL_RCC_OscConfig+0x700>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001a5c: 4b6b ldr r3, [pc, #428] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001a5e: 681b ldr r3, [r3, #0]
8001a60: 22f8 movs r2, #248 ; 0xf8
8001a62: 4393 bics r3, r2
8001a64: 0019 movs r1, r3
8001a66: 687b ldr r3, [r7, #4]
8001a68: 691b ldr r3, [r3, #16]
8001a6a: 00da lsls r2, r3, #3
8001a6c: 4b67 ldr r3, [pc, #412] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001a6e: 430a orrs r2, r1
8001a70: 601a str r2, [r3, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8001a72: e041 b.n 8001af8 <HAL_RCC_OscConfig+0x224>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8001a74: 687b ldr r3, [r7, #4]
8001a76: 68db ldr r3, [r3, #12]
8001a78: 2b00 cmp r3, #0
8001a7a: d024 beq.n 8001ac6 <HAL_RCC_OscConfig+0x1f2>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8001a7c: 4b63 ldr r3, [pc, #396] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001a7e: 681a ldr r2, [r3, #0]
8001a80: 4b62 ldr r3, [pc, #392] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001a82: 2101 movs r1, #1
8001a84: 430a orrs r2, r1
8001a86: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001a88: f7fe fee6 bl 8000858 <HAL_GetTick>
8001a8c: 0003 movs r3, r0
8001a8e: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001a90: e008 b.n 8001aa4 <HAL_RCC_OscConfig+0x1d0>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8001a92: f7fe fee1 bl 8000858 <HAL_GetTick>
8001a96: 0002 movs r2, r0
8001a98: 69bb ldr r3, [r7, #24]
8001a9a: 1ad3 subs r3, r2, r3
8001a9c: 2b02 cmp r3, #2
8001a9e: d901 bls.n 8001aa4 <HAL_RCC_OscConfig+0x1d0>
{
return HAL_TIMEOUT;
8001aa0: 2303 movs r3, #3
8001aa2: e297 b.n 8001fd4 <HAL_RCC_OscConfig+0x700>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001aa4: 4b59 ldr r3, [pc, #356] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001aa6: 681b ldr r3, [r3, #0]
8001aa8: 2202 movs r2, #2
8001aaa: 4013 ands r3, r2
8001aac: d0f1 beq.n 8001a92 <HAL_RCC_OscConfig+0x1be>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001aae: 4b57 ldr r3, [pc, #348] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001ab0: 681b ldr r3, [r3, #0]
8001ab2: 22f8 movs r2, #248 ; 0xf8
8001ab4: 4393 bics r3, r2
8001ab6: 0019 movs r1, r3
8001ab8: 687b ldr r3, [r7, #4]
8001aba: 691b ldr r3, [r3, #16]
8001abc: 00da lsls r2, r3, #3
8001abe: 4b53 ldr r3, [pc, #332] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001ac0: 430a orrs r2, r1
8001ac2: 601a str r2, [r3, #0]
8001ac4: e018 b.n 8001af8 <HAL_RCC_OscConfig+0x224>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8001ac6: 4b51 ldr r3, [pc, #324] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001ac8: 681a ldr r2, [r3, #0]
8001aca: 4b50 ldr r3, [pc, #320] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001acc: 2101 movs r1, #1
8001ace: 438a bics r2, r1
8001ad0: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001ad2: f7fe fec1 bl 8000858 <HAL_GetTick>
8001ad6: 0003 movs r3, r0
8001ad8: 61bb str r3, [r7, #24]
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001ada: e008 b.n 8001aee <HAL_RCC_OscConfig+0x21a>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8001adc: f7fe febc bl 8000858 <HAL_GetTick>
8001ae0: 0002 movs r2, r0
8001ae2: 69bb ldr r3, [r7, #24]
8001ae4: 1ad3 subs r3, r2, r3
8001ae6: 2b02 cmp r3, #2
8001ae8: d901 bls.n 8001aee <HAL_RCC_OscConfig+0x21a>
{
return HAL_TIMEOUT;
8001aea: 2303 movs r3, #3
8001aec: e272 b.n 8001fd4 <HAL_RCC_OscConfig+0x700>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001aee: 4b47 ldr r3, [pc, #284] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001af0: 681b ldr r3, [r3, #0]
8001af2: 2202 movs r2, #2
8001af4: 4013 ands r3, r2
8001af6: d1f1 bne.n 8001adc <HAL_RCC_OscConfig+0x208>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8001af8: 687b ldr r3, [r7, #4]
8001afa: 681b ldr r3, [r3, #0]
8001afc: 2208 movs r2, #8
8001afe: 4013 ands r3, r2
8001b00: d036 beq.n 8001b70 <HAL_RCC_OscConfig+0x29c>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8001b02: 687b ldr r3, [r7, #4]
8001b04: 69db ldr r3, [r3, #28]
8001b06: 2b00 cmp r3, #0
8001b08: d019 beq.n 8001b3e <HAL_RCC_OscConfig+0x26a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8001b0a: 4b40 ldr r3, [pc, #256] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001b0c: 6a5a ldr r2, [r3, #36] ; 0x24
8001b0e: 4b3f ldr r3, [pc, #252] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001b10: 2101 movs r1, #1
8001b12: 430a orrs r2, r1
8001b14: 625a str r2, [r3, #36] ; 0x24
/* Get Start Tick */
tickstart = HAL_GetTick();
8001b16: f7fe fe9f bl 8000858 <HAL_GetTick>
8001b1a: 0003 movs r3, r0
8001b1c: 61bb str r3, [r7, #24]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001b1e: e008 b.n 8001b32 <HAL_RCC_OscConfig+0x25e>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8001b20: f7fe fe9a bl 8000858 <HAL_GetTick>
8001b24: 0002 movs r2, r0
8001b26: 69bb ldr r3, [r7, #24]
8001b28: 1ad3 subs r3, r2, r3
8001b2a: 2b02 cmp r3, #2
8001b2c: d901 bls.n 8001b32 <HAL_RCC_OscConfig+0x25e>
{
return HAL_TIMEOUT;
8001b2e: 2303 movs r3, #3
8001b30: e250 b.n 8001fd4 <HAL_RCC_OscConfig+0x700>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001b32: 4b36 ldr r3, [pc, #216] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001b34: 6a5b ldr r3, [r3, #36] ; 0x24
8001b36: 2202 movs r2, #2
8001b38: 4013 ands r3, r2
8001b3a: d0f1 beq.n 8001b20 <HAL_RCC_OscConfig+0x24c>
8001b3c: e018 b.n 8001b70 <HAL_RCC_OscConfig+0x29c>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8001b3e: 4b33 ldr r3, [pc, #204] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001b40: 6a5a ldr r2, [r3, #36] ; 0x24
8001b42: 4b32 ldr r3, [pc, #200] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001b44: 2101 movs r1, #1
8001b46: 438a bics r2, r1
8001b48: 625a str r2, [r3, #36] ; 0x24
/* Get Start Tick */
tickstart = HAL_GetTick();
8001b4a: f7fe fe85 bl 8000858 <HAL_GetTick>
8001b4e: 0003 movs r3, r0
8001b50: 61bb str r3, [r7, #24]
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8001b52: e008 b.n 8001b66 <HAL_RCC_OscConfig+0x292>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8001b54: f7fe fe80 bl 8000858 <HAL_GetTick>
8001b58: 0002 movs r2, r0
8001b5a: 69bb ldr r3, [r7, #24]
8001b5c: 1ad3 subs r3, r2, r3
8001b5e: 2b02 cmp r3, #2
8001b60: d901 bls.n 8001b66 <HAL_RCC_OscConfig+0x292>
{
return HAL_TIMEOUT;
8001b62: 2303 movs r3, #3
8001b64: e236 b.n 8001fd4 <HAL_RCC_OscConfig+0x700>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8001b66: 4b29 ldr r3, [pc, #164] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001b68: 6a5b ldr r3, [r3, #36] ; 0x24
8001b6a: 2202 movs r2, #2
8001b6c: 4013 ands r3, r2
8001b6e: d1f1 bne.n 8001b54 <HAL_RCC_OscConfig+0x280>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8001b70: 687b ldr r3, [r7, #4]
8001b72: 681b ldr r3, [r3, #0]
8001b74: 2204 movs r2, #4
8001b76: 4013 ands r3, r2
8001b78: d100 bne.n 8001b7c <HAL_RCC_OscConfig+0x2a8>
8001b7a: e0b5 b.n 8001ce8 <HAL_RCC_OscConfig+0x414>
{
FlagStatus pwrclkchanged = RESET;
8001b7c: 201f movs r0, #31
8001b7e: 183b adds r3, r7, r0
8001b80: 2200 movs r2, #0
8001b82: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8001b84: 4b21 ldr r3, [pc, #132] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001b86: 69da ldr r2, [r3, #28]
8001b88: 2380 movs r3, #128 ; 0x80
8001b8a: 055b lsls r3, r3, #21
8001b8c: 4013 ands r3, r2
8001b8e: d110 bne.n 8001bb2 <HAL_RCC_OscConfig+0x2de>
{
__HAL_RCC_PWR_CLK_ENABLE();
8001b90: 4b1e ldr r3, [pc, #120] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001b92: 69da ldr r2, [r3, #28]
8001b94: 4b1d ldr r3, [pc, #116] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001b96: 2180 movs r1, #128 ; 0x80
8001b98: 0549 lsls r1, r1, #21
8001b9a: 430a orrs r2, r1
8001b9c: 61da str r2, [r3, #28]
8001b9e: 4b1b ldr r3, [pc, #108] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001ba0: 69da ldr r2, [r3, #28]
8001ba2: 2380 movs r3, #128 ; 0x80
8001ba4: 055b lsls r3, r3, #21
8001ba6: 4013 ands r3, r2
8001ba8: 60fb str r3, [r7, #12]
8001baa: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
8001bac: 183b adds r3, r7, r0
8001bae: 2201 movs r2, #1
8001bb0: 701a strb r2, [r3, #0]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001bb2: 4b19 ldr r3, [pc, #100] ; (8001c18 <HAL_RCC_OscConfig+0x344>)
8001bb4: 681a ldr r2, [r3, #0]
8001bb6: 2380 movs r3, #128 ; 0x80
8001bb8: 005b lsls r3, r3, #1
8001bba: 4013 ands r3, r2
8001bbc: d11a bne.n 8001bf4 <HAL_RCC_OscConfig+0x320>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8001bbe: 4b16 ldr r3, [pc, #88] ; (8001c18 <HAL_RCC_OscConfig+0x344>)
8001bc0: 681a ldr r2, [r3, #0]
8001bc2: 4b15 ldr r3, [pc, #84] ; (8001c18 <HAL_RCC_OscConfig+0x344>)
8001bc4: 2180 movs r1, #128 ; 0x80
8001bc6: 0049 lsls r1, r1, #1
8001bc8: 430a orrs r2, r1
8001bca: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8001bcc: f7fe fe44 bl 8000858 <HAL_GetTick>
8001bd0: 0003 movs r3, r0
8001bd2: 61bb str r3, [r7, #24]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001bd4: e008 b.n 8001be8 <HAL_RCC_OscConfig+0x314>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8001bd6: f7fe fe3f bl 8000858 <HAL_GetTick>
8001bda: 0002 movs r2, r0
8001bdc: 69bb ldr r3, [r7, #24]
8001bde: 1ad3 subs r3, r2, r3
8001be0: 2b64 cmp r3, #100 ; 0x64
8001be2: d901 bls.n 8001be8 <HAL_RCC_OscConfig+0x314>
{
return HAL_TIMEOUT;
8001be4: 2303 movs r3, #3
8001be6: e1f5 b.n 8001fd4 <HAL_RCC_OscConfig+0x700>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001be8: 4b0b ldr r3, [pc, #44] ; (8001c18 <HAL_RCC_OscConfig+0x344>)
8001bea: 681a ldr r2, [r3, #0]
8001bec: 2380 movs r3, #128 ; 0x80
8001bee: 005b lsls r3, r3, #1
8001bf0: 4013 ands r3, r2
8001bf2: d0f0 beq.n 8001bd6 <HAL_RCC_OscConfig+0x302>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8001bf4: 687b ldr r3, [r7, #4]
8001bf6: 689b ldr r3, [r3, #8]
8001bf8: 2b01 cmp r3, #1
8001bfa: d10f bne.n 8001c1c <HAL_RCC_OscConfig+0x348>
8001bfc: 4b03 ldr r3, [pc, #12] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001bfe: 6a1a ldr r2, [r3, #32]
8001c00: 4b02 ldr r3, [pc, #8] ; (8001c0c <HAL_RCC_OscConfig+0x338>)
8001c02: 2101 movs r1, #1
8001c04: 430a orrs r2, r1
8001c06: 621a str r2, [r3, #32]
8001c08: e036 b.n 8001c78 <HAL_RCC_OscConfig+0x3a4>
8001c0a: 46c0 nop ; (mov r8, r8)
8001c0c: 40021000 .word 0x40021000
8001c10: fffeffff .word 0xfffeffff
8001c14: fffbffff .word 0xfffbffff
8001c18: 40007000 .word 0x40007000
8001c1c: 687b ldr r3, [r7, #4]
8001c1e: 689b ldr r3, [r3, #8]
8001c20: 2b00 cmp r3, #0
8001c22: d10c bne.n 8001c3e <HAL_RCC_OscConfig+0x36a>
8001c24: 4bca ldr r3, [pc, #808] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001c26: 6a1a ldr r2, [r3, #32]
8001c28: 4bc9 ldr r3, [pc, #804] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001c2a: 2101 movs r1, #1
8001c2c: 438a bics r2, r1
8001c2e: 621a str r2, [r3, #32]
8001c30: 4bc7 ldr r3, [pc, #796] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001c32: 6a1a ldr r2, [r3, #32]
8001c34: 4bc6 ldr r3, [pc, #792] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001c36: 2104 movs r1, #4
8001c38: 438a bics r2, r1
8001c3a: 621a str r2, [r3, #32]
8001c3c: e01c b.n 8001c78 <HAL_RCC_OscConfig+0x3a4>
8001c3e: 687b ldr r3, [r7, #4]
8001c40: 689b ldr r3, [r3, #8]
8001c42: 2b05 cmp r3, #5
8001c44: d10c bne.n 8001c60 <HAL_RCC_OscConfig+0x38c>
8001c46: 4bc2 ldr r3, [pc, #776] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001c48: 6a1a ldr r2, [r3, #32]
8001c4a: 4bc1 ldr r3, [pc, #772] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001c4c: 2104 movs r1, #4
8001c4e: 430a orrs r2, r1
8001c50: 621a str r2, [r3, #32]
8001c52: 4bbf ldr r3, [pc, #764] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001c54: 6a1a ldr r2, [r3, #32]
8001c56: 4bbe ldr r3, [pc, #760] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001c58: 2101 movs r1, #1
8001c5a: 430a orrs r2, r1
8001c5c: 621a str r2, [r3, #32]
8001c5e: e00b b.n 8001c78 <HAL_RCC_OscConfig+0x3a4>
8001c60: 4bbb ldr r3, [pc, #748] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001c62: 6a1a ldr r2, [r3, #32]
8001c64: 4bba ldr r3, [pc, #744] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001c66: 2101 movs r1, #1
8001c68: 438a bics r2, r1
8001c6a: 621a str r2, [r3, #32]
8001c6c: 4bb8 ldr r3, [pc, #736] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001c6e: 6a1a ldr r2, [r3, #32]
8001c70: 4bb7 ldr r3, [pc, #732] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001c72: 2104 movs r1, #4
8001c74: 438a bics r2, r1
8001c76: 621a str r2, [r3, #32]
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8001c78: 687b ldr r3, [r7, #4]
8001c7a: 689b ldr r3, [r3, #8]
8001c7c: 2b00 cmp r3, #0
8001c7e: d014 beq.n 8001caa <HAL_RCC_OscConfig+0x3d6>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001c80: f7fe fdea bl 8000858 <HAL_GetTick>
8001c84: 0003 movs r3, r0
8001c86: 61bb str r3, [r7, #24]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001c88: e009 b.n 8001c9e <HAL_RCC_OscConfig+0x3ca>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001c8a: f7fe fde5 bl 8000858 <HAL_GetTick>
8001c8e: 0002 movs r2, r0
8001c90: 69bb ldr r3, [r7, #24]
8001c92: 1ad3 subs r3, r2, r3
8001c94: 4aaf ldr r2, [pc, #700] ; (8001f54 <HAL_RCC_OscConfig+0x680>)
8001c96: 4293 cmp r3, r2
8001c98: d901 bls.n 8001c9e <HAL_RCC_OscConfig+0x3ca>
{
return HAL_TIMEOUT;
8001c9a: 2303 movs r3, #3
8001c9c: e19a b.n 8001fd4 <HAL_RCC_OscConfig+0x700>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001c9e: 4bac ldr r3, [pc, #688] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001ca0: 6a1b ldr r3, [r3, #32]
8001ca2: 2202 movs r2, #2
8001ca4: 4013 ands r3, r2
8001ca6: d0f0 beq.n 8001c8a <HAL_RCC_OscConfig+0x3b6>
8001ca8: e013 b.n 8001cd2 <HAL_RCC_OscConfig+0x3fe>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001caa: f7fe fdd5 bl 8000858 <HAL_GetTick>
8001cae: 0003 movs r3, r0
8001cb0: 61bb str r3, [r7, #24]
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001cb2: e009 b.n 8001cc8 <HAL_RCC_OscConfig+0x3f4>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001cb4: f7fe fdd0 bl 8000858 <HAL_GetTick>
8001cb8: 0002 movs r2, r0
8001cba: 69bb ldr r3, [r7, #24]
8001cbc: 1ad3 subs r3, r2, r3
8001cbe: 4aa5 ldr r2, [pc, #660] ; (8001f54 <HAL_RCC_OscConfig+0x680>)
8001cc0: 4293 cmp r3, r2
8001cc2: d901 bls.n 8001cc8 <HAL_RCC_OscConfig+0x3f4>
{
return HAL_TIMEOUT;
8001cc4: 2303 movs r3, #3
8001cc6: e185 b.n 8001fd4 <HAL_RCC_OscConfig+0x700>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001cc8: 4ba1 ldr r3, [pc, #644] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001cca: 6a1b ldr r3, [r3, #32]
8001ccc: 2202 movs r2, #2
8001cce: 4013 ands r3, r2
8001cd0: d1f0 bne.n 8001cb4 <HAL_RCC_OscConfig+0x3e0>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
8001cd2: 231f movs r3, #31
8001cd4: 18fb adds r3, r7, r3
8001cd6: 781b ldrb r3, [r3, #0]
8001cd8: 2b01 cmp r3, #1
8001cda: d105 bne.n 8001ce8 <HAL_RCC_OscConfig+0x414>
{
__HAL_RCC_PWR_CLK_DISABLE();
8001cdc: 4b9c ldr r3, [pc, #624] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001cde: 69da ldr r2, [r3, #28]
8001ce0: 4b9b ldr r3, [pc, #620] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001ce2: 499d ldr r1, [pc, #628] ; (8001f58 <HAL_RCC_OscConfig+0x684>)
8001ce4: 400a ands r2, r1
8001ce6: 61da str r2, [r3, #28]
}
}
/*----------------------------- HSI14 Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
8001ce8: 687b ldr r3, [r7, #4]
8001cea: 681b ldr r3, [r3, #0]
8001cec: 2210 movs r2, #16
8001cee: 4013 ands r3, r2
8001cf0: d063 beq.n 8001dba <HAL_RCC_OscConfig+0x4e6>
/* Check the parameters */
assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));
/* Check the HSI14 State */
if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
8001cf2: 687b ldr r3, [r7, #4]
8001cf4: 695b ldr r3, [r3, #20]
8001cf6: 2b01 cmp r3, #1
8001cf8: d12a bne.n 8001d50 <HAL_RCC_OscConfig+0x47c>
{
/* Disable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_DISABLE();
8001cfa: 4b95 ldr r3, [pc, #596] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001cfc: 6b5a ldr r2, [r3, #52] ; 0x34
8001cfe: 4b94 ldr r3, [pc, #592] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001d00: 2104 movs r1, #4
8001d02: 430a orrs r2, r1
8001d04: 635a str r2, [r3, #52] ; 0x34
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI14_ENABLE();
8001d06: 4b92 ldr r3, [pc, #584] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001d08: 6b5a ldr r2, [r3, #52] ; 0x34
8001d0a: 4b91 ldr r3, [pc, #580] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001d0c: 2101 movs r1, #1
8001d0e: 430a orrs r2, r1
8001d10: 635a str r2, [r3, #52] ; 0x34
/* Get Start Tick */
tickstart = HAL_GetTick();
8001d12: f7fe fda1 bl 8000858 <HAL_GetTick>
8001d16: 0003 movs r3, r0
8001d18: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
8001d1a: e008 b.n 8001d2e <HAL_RCC_OscConfig+0x45a>
{
if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
8001d1c: f7fe fd9c bl 8000858 <HAL_GetTick>
8001d20: 0002 movs r2, r0
8001d22: 69bb ldr r3, [r7, #24]
8001d24: 1ad3 subs r3, r2, r3
8001d26: 2b02 cmp r3, #2
8001d28: d901 bls.n 8001d2e <HAL_RCC_OscConfig+0x45a>
{
return HAL_TIMEOUT;
8001d2a: 2303 movs r3, #3
8001d2c: e152 b.n 8001fd4 <HAL_RCC_OscConfig+0x700>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
8001d2e: 4b88 ldr r3, [pc, #544] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001d30: 6b5b ldr r3, [r3, #52] ; 0x34
8001d32: 2202 movs r2, #2
8001d34: 4013 ands r3, r2
8001d36: d0f1 beq.n 8001d1c <HAL_RCC_OscConfig+0x448>
}
}
/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
8001d38: 4b85 ldr r3, [pc, #532] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001d3a: 6b5b ldr r3, [r3, #52] ; 0x34
8001d3c: 22f8 movs r2, #248 ; 0xf8
8001d3e: 4393 bics r3, r2
8001d40: 0019 movs r1, r3
8001d42: 687b ldr r3, [r7, #4]
8001d44: 699b ldr r3, [r3, #24]
8001d46: 00da lsls r2, r3, #3
8001d48: 4b81 ldr r3, [pc, #516] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001d4a: 430a orrs r2, r1
8001d4c: 635a str r2, [r3, #52] ; 0x34
8001d4e: e034 b.n 8001dba <HAL_RCC_OscConfig+0x4e6>
}
else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
8001d50: 687b ldr r3, [r7, #4]
8001d52: 695b ldr r3, [r3, #20]
8001d54: 3305 adds r3, #5
8001d56: d111 bne.n 8001d7c <HAL_RCC_OscConfig+0x4a8>
{
/* Enable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_ENABLE();
8001d58: 4b7d ldr r3, [pc, #500] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001d5a: 6b5a ldr r2, [r3, #52] ; 0x34
8001d5c: 4b7c ldr r3, [pc, #496] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001d5e: 2104 movs r1, #4
8001d60: 438a bics r2, r1
8001d62: 635a str r2, [r3, #52] ; 0x34
/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
8001d64: 4b7a ldr r3, [pc, #488] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001d66: 6b5b ldr r3, [r3, #52] ; 0x34
8001d68: 22f8 movs r2, #248 ; 0xf8
8001d6a: 4393 bics r3, r2
8001d6c: 0019 movs r1, r3
8001d6e: 687b ldr r3, [r7, #4]
8001d70: 699b ldr r3, [r3, #24]
8001d72: 00da lsls r2, r3, #3
8001d74: 4b76 ldr r3, [pc, #472] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001d76: 430a orrs r2, r1
8001d78: 635a str r2, [r3, #52] ; 0x34
8001d7a: e01e b.n 8001dba <HAL_RCC_OscConfig+0x4e6>
}
else
{
/* Disable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_DISABLE();
8001d7c: 4b74 ldr r3, [pc, #464] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001d7e: 6b5a ldr r2, [r3, #52] ; 0x34
8001d80: 4b73 ldr r3, [pc, #460] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001d82: 2104 movs r1, #4
8001d84: 430a orrs r2, r1
8001d86: 635a str r2, [r3, #52] ; 0x34
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI14_DISABLE();
8001d88: 4b71 ldr r3, [pc, #452] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001d8a: 6b5a ldr r2, [r3, #52] ; 0x34
8001d8c: 4b70 ldr r3, [pc, #448] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001d8e: 2101 movs r1, #1
8001d90: 438a bics r2, r1
8001d92: 635a str r2, [r3, #52] ; 0x34
/* Get Start Tick */
tickstart = HAL_GetTick();
8001d94: f7fe fd60 bl 8000858 <HAL_GetTick>
8001d98: 0003 movs r3, r0
8001d9a: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
8001d9c: e008 b.n 8001db0 <HAL_RCC_OscConfig+0x4dc>
{
if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
8001d9e: f7fe fd5b bl 8000858 <HAL_GetTick>
8001da2: 0002 movs r2, r0
8001da4: 69bb ldr r3, [r7, #24]
8001da6: 1ad3 subs r3, r2, r3
8001da8: 2b02 cmp r3, #2
8001daa: d901 bls.n 8001db0 <HAL_RCC_OscConfig+0x4dc>
{
return HAL_TIMEOUT;
8001dac: 2303 movs r3, #3
8001dae: e111 b.n 8001fd4 <HAL_RCC_OscConfig+0x700>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
8001db0: 4b67 ldr r3, [pc, #412] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001db2: 6b5b ldr r3, [r3, #52] ; 0x34
8001db4: 2202 movs r2, #2
8001db6: 4013 ands r3, r2
8001db8: d1f1 bne.n 8001d9e <HAL_RCC_OscConfig+0x4ca>
}
}
#if defined(RCC_HSI48_SUPPORT)
/*----------------------------- HSI48 Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
8001dba: 687b ldr r3, [r7, #4]
8001dbc: 681b ldr r3, [r3, #0]
8001dbe: 2220 movs r2, #32
8001dc0: 4013 ands r3, r2
8001dc2: d05c beq.n 8001e7e <HAL_RCC_OscConfig+0x5aa>
{
/* Check the parameters */
assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
/* When the HSI48 is used as system clock it is not allowed to be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) ||
8001dc4: 4b62 ldr r3, [pc, #392] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001dc6: 685b ldr r3, [r3, #4]
8001dc8: 220c movs r2, #12
8001dca: 4013 ands r3, r2
8001dcc: 2b0c cmp r3, #12
8001dce: d00e beq.n 8001dee <HAL_RCC_OscConfig+0x51a>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48)))
8001dd0: 4b5f ldr r3, [pc, #380] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001dd2: 685b ldr r3, [r3, #4]
8001dd4: 220c movs r2, #12
8001dd6: 4013 ands r3, r2
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) ||
8001dd8: 2b08 cmp r3, #8
8001dda: d114 bne.n 8001e06 <HAL_RCC_OscConfig+0x532>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48)))
8001ddc: 4b5c ldr r3, [pc, #368] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001dde: 685a ldr r2, [r3, #4]
8001de0: 23c0 movs r3, #192 ; 0xc0
8001de2: 025b lsls r3, r3, #9
8001de4: 401a ands r2, r3
8001de6: 23c0 movs r3, #192 ; 0xc0
8001de8: 025b lsls r3, r3, #9
8001dea: 429a cmp r2, r3
8001dec: d10b bne.n 8001e06 <HAL_RCC_OscConfig+0x532>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON))
8001dee: 4b58 ldr r3, [pc, #352] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001df0: 6b5a ldr r2, [r3, #52] ; 0x34
8001df2: 2380 movs r3, #128 ; 0x80
8001df4: 029b lsls r3, r3, #10
8001df6: 4013 ands r3, r2
8001df8: d040 beq.n 8001e7c <HAL_RCC_OscConfig+0x5a8>
8001dfa: 687b ldr r3, [r7, #4]
8001dfc: 6a1b ldr r3, [r3, #32]
8001dfe: 2b01 cmp r3, #1
8001e00: d03c beq.n 8001e7c <HAL_RCC_OscConfig+0x5a8>
{
return HAL_ERROR;
8001e02: 2301 movs r3, #1
8001e04: e0e6 b.n 8001fd4 <HAL_RCC_OscConfig+0x700>
}
}
else
{
/* Check the HSI48 State */
if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
8001e06: 687b ldr r3, [r7, #4]
8001e08: 6a1b ldr r3, [r3, #32]
8001e0a: 2b00 cmp r3, #0
8001e0c: d01b beq.n 8001e46 <HAL_RCC_OscConfig+0x572>
{
/* Enable the Internal High Speed oscillator (HSI48). */
__HAL_RCC_HSI48_ENABLE();
8001e0e: 4b50 ldr r3, [pc, #320] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001e10: 6b5a ldr r2, [r3, #52] ; 0x34
8001e12: 4b4f ldr r3, [pc, #316] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001e14: 2180 movs r1, #128 ; 0x80
8001e16: 0249 lsls r1, r1, #9
8001e18: 430a orrs r2, r1
8001e1a: 635a str r2, [r3, #52] ; 0x34
/* Get Start Tick */
tickstart = HAL_GetTick();
8001e1c: f7fe fd1c bl 8000858 <HAL_GetTick>
8001e20: 0003 movs r3, r0
8001e22: 61bb str r3, [r7, #24]
/* Wait till HSI48 is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
8001e24: e008 b.n 8001e38 <HAL_RCC_OscConfig+0x564>
{
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
8001e26: f7fe fd17 bl 8000858 <HAL_GetTick>
8001e2a: 0002 movs r2, r0
8001e2c: 69bb ldr r3, [r7, #24]
8001e2e: 1ad3 subs r3, r2, r3
8001e30: 2b02 cmp r3, #2
8001e32: d901 bls.n 8001e38 <HAL_RCC_OscConfig+0x564>
{
return HAL_TIMEOUT;
8001e34: 2303 movs r3, #3
8001e36: e0cd b.n 8001fd4 <HAL_RCC_OscConfig+0x700>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
8001e38: 4b45 ldr r3, [pc, #276] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001e3a: 6b5a ldr r2, [r3, #52] ; 0x34
8001e3c: 2380 movs r3, #128 ; 0x80
8001e3e: 029b lsls r3, r3, #10
8001e40: 4013 ands r3, r2
8001e42: d0f0 beq.n 8001e26 <HAL_RCC_OscConfig+0x552>
8001e44: e01b b.n 8001e7e <HAL_RCC_OscConfig+0x5aa>
}
}
else
{
/* Disable the Internal High Speed oscillator (HSI48). */
__HAL_RCC_HSI48_DISABLE();
8001e46: 4b42 ldr r3, [pc, #264] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001e48: 6b5a ldr r2, [r3, #52] ; 0x34
8001e4a: 4b41 ldr r3, [pc, #260] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001e4c: 4943 ldr r1, [pc, #268] ; (8001f5c <HAL_RCC_OscConfig+0x688>)
8001e4e: 400a ands r2, r1
8001e50: 635a str r2, [r3, #52] ; 0x34
/* Get Start Tick */
tickstart = HAL_GetTick();
8001e52: f7fe fd01 bl 8000858 <HAL_GetTick>
8001e56: 0003 movs r3, r0
8001e58: 61bb str r3, [r7, #24]
/* Wait till HSI48 is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET)
8001e5a: e008 b.n 8001e6e <HAL_RCC_OscConfig+0x59a>
{
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
8001e5c: f7fe fcfc bl 8000858 <HAL_GetTick>
8001e60: 0002 movs r2, r0
8001e62: 69bb ldr r3, [r7, #24]
8001e64: 1ad3 subs r3, r2, r3
8001e66: 2b02 cmp r3, #2
8001e68: d901 bls.n 8001e6e <HAL_RCC_OscConfig+0x59a>
{
return HAL_TIMEOUT;
8001e6a: 2303 movs r3, #3
8001e6c: e0b2 b.n 8001fd4 <HAL_RCC_OscConfig+0x700>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET)
8001e6e: 4b38 ldr r3, [pc, #224] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001e70: 6b5a ldr r2, [r3, #52] ; 0x34
8001e72: 2380 movs r3, #128 ; 0x80
8001e74: 029b lsls r3, r3, #10
8001e76: 4013 ands r3, r2
8001e78: d1f0 bne.n 8001e5c <HAL_RCC_OscConfig+0x588>
8001e7a: e000 b.n 8001e7e <HAL_RCC_OscConfig+0x5aa>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON))
8001e7c: 46c0 nop ; (mov r8, r8)
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8001e7e: 687b ldr r3, [r7, #4]
8001e80: 6a5b ldr r3, [r3, #36] ; 0x24
8001e82: 2b00 cmp r3, #0
8001e84: d100 bne.n 8001e88 <HAL_RCC_OscConfig+0x5b4>
8001e86: e0a4 b.n 8001fd2 <HAL_RCC_OscConfig+0x6fe>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8001e88: 4b31 ldr r3, [pc, #196] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001e8a: 685b ldr r3, [r3, #4]
8001e8c: 220c movs r2, #12
8001e8e: 4013 ands r3, r2
8001e90: 2b08 cmp r3, #8
8001e92: d100 bne.n 8001e96 <HAL_RCC_OscConfig+0x5c2>
8001e94: e078 b.n 8001f88 <HAL_RCC_OscConfig+0x6b4>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8001e96: 687b ldr r3, [r7, #4]
8001e98: 6a5b ldr r3, [r3, #36] ; 0x24
8001e9a: 2b02 cmp r3, #2
8001e9c: d14c bne.n 8001f38 <HAL_RCC_OscConfig+0x664>
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001e9e: 4b2c ldr r3, [pc, #176] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001ea0: 681a ldr r2, [r3, #0]
8001ea2: 4b2b ldr r3, [pc, #172] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001ea4: 492e ldr r1, [pc, #184] ; (8001f60 <HAL_RCC_OscConfig+0x68c>)
8001ea6: 400a ands r2, r1
8001ea8: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001eaa: f7fe fcd5 bl 8000858 <HAL_GetTick>
8001eae: 0003 movs r3, r0
8001eb0: 61bb str r3, [r7, #24]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001eb2: e008 b.n 8001ec6 <HAL_RCC_OscConfig+0x5f2>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001eb4: f7fe fcd0 bl 8000858 <HAL_GetTick>
8001eb8: 0002 movs r2, r0
8001eba: 69bb ldr r3, [r7, #24]
8001ebc: 1ad3 subs r3, r2, r3
8001ebe: 2b02 cmp r3, #2
8001ec0: d901 bls.n 8001ec6 <HAL_RCC_OscConfig+0x5f2>
{
return HAL_TIMEOUT;
8001ec2: 2303 movs r3, #3
8001ec4: e086 b.n 8001fd4 <HAL_RCC_OscConfig+0x700>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001ec6: 4b22 ldr r3, [pc, #136] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001ec8: 681a ldr r2, [r3, #0]
8001eca: 2380 movs r3, #128 ; 0x80
8001ecc: 049b lsls r3, r3, #18
8001ece: 4013 ands r3, r2
8001ed0: d1f0 bne.n 8001eb4 <HAL_RCC_OscConfig+0x5e0>
}
}
/* Configure the main PLL clock source, predivider and multiplication factor. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8001ed2: 4b1f ldr r3, [pc, #124] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001ed4: 6adb ldr r3, [r3, #44] ; 0x2c
8001ed6: 220f movs r2, #15
8001ed8: 4393 bics r3, r2
8001eda: 0019 movs r1, r3
8001edc: 687b ldr r3, [r7, #4]
8001ede: 6b1a ldr r2, [r3, #48] ; 0x30
8001ee0: 4b1b ldr r3, [pc, #108] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001ee2: 430a orrs r2, r1
8001ee4: 62da str r2, [r3, #44] ; 0x2c
8001ee6: 4b1a ldr r3, [pc, #104] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001ee8: 685b ldr r3, [r3, #4]
8001eea: 4a1e ldr r2, [pc, #120] ; (8001f64 <HAL_RCC_OscConfig+0x690>)
8001eec: 4013 ands r3, r2
8001eee: 0019 movs r1, r3
8001ef0: 687b ldr r3, [r7, #4]
8001ef2: 6ada ldr r2, [r3, #44] ; 0x2c
8001ef4: 687b ldr r3, [r7, #4]
8001ef6: 6a9b ldr r3, [r3, #40] ; 0x28
8001ef8: 431a orrs r2, r3
8001efa: 4b15 ldr r3, [pc, #84] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001efc: 430a orrs r2, r1
8001efe: 605a str r2, [r3, #4]
RCC_OscInitStruct->PLL.PREDIV,
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8001f00: 4b13 ldr r3, [pc, #76] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001f02: 681a ldr r2, [r3, #0]
8001f04: 4b12 ldr r3, [pc, #72] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001f06: 2180 movs r1, #128 ; 0x80
8001f08: 0449 lsls r1, r1, #17
8001f0a: 430a orrs r2, r1
8001f0c: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001f0e: f7fe fca3 bl 8000858 <HAL_GetTick>
8001f12: 0003 movs r3, r0
8001f14: 61bb str r3, [r7, #24]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001f16: e008 b.n 8001f2a <HAL_RCC_OscConfig+0x656>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001f18: f7fe fc9e bl 8000858 <HAL_GetTick>
8001f1c: 0002 movs r2, r0
8001f1e: 69bb ldr r3, [r7, #24]
8001f20: 1ad3 subs r3, r2, r3
8001f22: 2b02 cmp r3, #2
8001f24: d901 bls.n 8001f2a <HAL_RCC_OscConfig+0x656>
{
return HAL_TIMEOUT;
8001f26: 2303 movs r3, #3
8001f28: e054 b.n 8001fd4 <HAL_RCC_OscConfig+0x700>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001f2a: 4b09 ldr r3, [pc, #36] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001f2c: 681a ldr r2, [r3, #0]
8001f2e: 2380 movs r3, #128 ; 0x80
8001f30: 049b lsls r3, r3, #18
8001f32: 4013 ands r3, r2
8001f34: d0f0 beq.n 8001f18 <HAL_RCC_OscConfig+0x644>
8001f36: e04c b.n 8001fd2 <HAL_RCC_OscConfig+0x6fe>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001f38: 4b05 ldr r3, [pc, #20] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001f3a: 681a ldr r2, [r3, #0]
8001f3c: 4b04 ldr r3, [pc, #16] ; (8001f50 <HAL_RCC_OscConfig+0x67c>)
8001f3e: 4908 ldr r1, [pc, #32] ; (8001f60 <HAL_RCC_OscConfig+0x68c>)
8001f40: 400a ands r2, r1
8001f42: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001f44: f7fe fc88 bl 8000858 <HAL_GetTick>
8001f48: 0003 movs r3, r0
8001f4a: 61bb str r3, [r7, #24]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001f4c: e015 b.n 8001f7a <HAL_RCC_OscConfig+0x6a6>
8001f4e: 46c0 nop ; (mov r8, r8)
8001f50: 40021000 .word 0x40021000
8001f54: 00001388 .word 0x00001388
8001f58: efffffff .word 0xefffffff
8001f5c: fffeffff .word 0xfffeffff
8001f60: feffffff .word 0xfeffffff
8001f64: ffc27fff .word 0xffc27fff
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001f68: f7fe fc76 bl 8000858 <HAL_GetTick>
8001f6c: 0002 movs r2, r0
8001f6e: 69bb ldr r3, [r7, #24]
8001f70: 1ad3 subs r3, r2, r3
8001f72: 2b02 cmp r3, #2
8001f74: d901 bls.n 8001f7a <HAL_RCC_OscConfig+0x6a6>
{
return HAL_TIMEOUT;
8001f76: 2303 movs r3, #3
8001f78: e02c b.n 8001fd4 <HAL_RCC_OscConfig+0x700>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001f7a: 4b18 ldr r3, [pc, #96] ; (8001fdc <HAL_RCC_OscConfig+0x708>)
8001f7c: 681a ldr r2, [r3, #0]
8001f7e: 2380 movs r3, #128 ; 0x80
8001f80: 049b lsls r3, r3, #18
8001f82: 4013 ands r3, r2
8001f84: d1f0 bne.n 8001f68 <HAL_RCC_OscConfig+0x694>
8001f86: e024 b.n 8001fd2 <HAL_RCC_OscConfig+0x6fe>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8001f88: 687b ldr r3, [r7, #4]
8001f8a: 6a5b ldr r3, [r3, #36] ; 0x24
8001f8c: 2b01 cmp r3, #1
8001f8e: d101 bne.n 8001f94 <HAL_RCC_OscConfig+0x6c0>
{
return HAL_ERROR;
8001f90: 2301 movs r3, #1
8001f92: e01f b.n 8001fd4 <HAL_RCC_OscConfig+0x700>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8001f94: 4b11 ldr r3, [pc, #68] ; (8001fdc <HAL_RCC_OscConfig+0x708>)
8001f96: 685b ldr r3, [r3, #4]
8001f98: 617b str r3, [r7, #20]
pll_config2 = RCC->CFGR2;
8001f9a: 4b10 ldr r3, [pc, #64] ; (8001fdc <HAL_RCC_OscConfig+0x708>)
8001f9c: 6adb ldr r3, [r3, #44] ; 0x2c
8001f9e: 613b str r3, [r7, #16]
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001fa0: 697a ldr r2, [r7, #20]
8001fa2: 23c0 movs r3, #192 ; 0xc0
8001fa4: 025b lsls r3, r3, #9
8001fa6: 401a ands r2, r3
8001fa8: 687b ldr r3, [r7, #4]
8001faa: 6a9b ldr r3, [r3, #40] ; 0x28
8001fac: 429a cmp r2, r3
8001fae: d10e bne.n 8001fce <HAL_RCC_OscConfig+0x6fa>
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
8001fb0: 693b ldr r3, [r7, #16]
8001fb2: 220f movs r2, #15
8001fb4: 401a ands r2, r3
8001fb6: 687b ldr r3, [r7, #4]
8001fb8: 6b1b ldr r3, [r3, #48] ; 0x30
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001fba: 429a cmp r2, r3
8001fbc: d107 bne.n 8001fce <HAL_RCC_OscConfig+0x6fa>
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL))
8001fbe: 697a ldr r2, [r7, #20]
8001fc0: 23f0 movs r3, #240 ; 0xf0
8001fc2: 039b lsls r3, r3, #14
8001fc4: 401a ands r2, r3
8001fc6: 687b ldr r3, [r7, #4]
8001fc8: 6adb ldr r3, [r3, #44] ; 0x2c
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
8001fca: 429a cmp r2, r3
8001fcc: d001 beq.n 8001fd2 <HAL_RCC_OscConfig+0x6fe>
{
return HAL_ERROR;
8001fce: 2301 movs r3, #1
8001fd0: e000 b.n 8001fd4 <HAL_RCC_OscConfig+0x700>
}
}
}
}
return HAL_OK;
8001fd2: 2300 movs r3, #0
}
8001fd4: 0018 movs r0, r3
8001fd6: 46bd mov sp, r7
8001fd8: b008 add sp, #32
8001fda: bd80 pop {r7, pc}
8001fdc: 40021000 .word 0x40021000
08001fe0 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8001fe0: b580 push {r7, lr}
8001fe2: b084 sub sp, #16
8001fe4: af00 add r7, sp, #0
8001fe6: 6078 str r0, [r7, #4]
8001fe8: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8001fea: 687b ldr r3, [r7, #4]
8001fec: 2b00 cmp r3, #0
8001fee: d101 bne.n 8001ff4 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8001ff0: 2301 movs r3, #1
8001ff2: e0bf b.n 8002174 <HAL_RCC_ClockConfig+0x194>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8001ff4: 4b61 ldr r3, [pc, #388] ; (800217c <HAL_RCC_ClockConfig+0x19c>)
8001ff6: 681b ldr r3, [r3, #0]
8001ff8: 2201 movs r2, #1
8001ffa: 4013 ands r3, r2
8001ffc: 683a ldr r2, [r7, #0]
8001ffe: 429a cmp r2, r3
8002000: d911 bls.n 8002026 <HAL_RCC_ClockConfig+0x46>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002002: 4b5e ldr r3, [pc, #376] ; (800217c <HAL_RCC_ClockConfig+0x19c>)
8002004: 681b ldr r3, [r3, #0]
8002006: 2201 movs r2, #1
8002008: 4393 bics r3, r2
800200a: 0019 movs r1, r3
800200c: 4b5b ldr r3, [pc, #364] ; (800217c <HAL_RCC_ClockConfig+0x19c>)
800200e: 683a ldr r2, [r7, #0]
8002010: 430a orrs r2, r1
8002012: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8002014: 4b59 ldr r3, [pc, #356] ; (800217c <HAL_RCC_ClockConfig+0x19c>)
8002016: 681b ldr r3, [r3, #0]
8002018: 2201 movs r2, #1
800201a: 4013 ands r3, r2
800201c: 683a ldr r2, [r7, #0]
800201e: 429a cmp r2, r3
8002020: d001 beq.n 8002026 <HAL_RCC_ClockConfig+0x46>
{
return HAL_ERROR;
8002022: 2301 movs r3, #1
8002024: e0a6 b.n 8002174 <HAL_RCC_ClockConfig+0x194>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8002026: 687b ldr r3, [r7, #4]
8002028: 681b ldr r3, [r3, #0]
800202a: 2202 movs r2, #2
800202c: 4013 ands r3, r2
800202e: d015 beq.n 800205c <HAL_RCC_ClockConfig+0x7c>
{
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002030: 687b ldr r3, [r7, #4]
8002032: 681b ldr r3, [r3, #0]
8002034: 2204 movs r2, #4
8002036: 4013 ands r3, r2
8002038: d006 beq.n 8002048 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
800203a: 4b51 ldr r3, [pc, #324] ; (8002180 <HAL_RCC_ClockConfig+0x1a0>)
800203c: 685a ldr r2, [r3, #4]
800203e: 4b50 ldr r3, [pc, #320] ; (8002180 <HAL_RCC_ClockConfig+0x1a0>)
8002040: 21e0 movs r1, #224 ; 0xe0
8002042: 00c9 lsls r1, r1, #3
8002044: 430a orrs r2, r1
8002046: 605a str r2, [r3, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8002048: 4b4d ldr r3, [pc, #308] ; (8002180 <HAL_RCC_ClockConfig+0x1a0>)
800204a: 685b ldr r3, [r3, #4]
800204c: 22f0 movs r2, #240 ; 0xf0
800204e: 4393 bics r3, r2
8002050: 0019 movs r1, r3
8002052: 687b ldr r3, [r7, #4]
8002054: 689a ldr r2, [r3, #8]
8002056: 4b4a ldr r3, [pc, #296] ; (8002180 <HAL_RCC_ClockConfig+0x1a0>)
8002058: 430a orrs r2, r1
800205a: 605a str r2, [r3, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
800205c: 687b ldr r3, [r7, #4]
800205e: 681b ldr r3, [r3, #0]
8002060: 2201 movs r2, #1
8002062: 4013 ands r3, r2
8002064: d04c beq.n 8002100 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8002066: 687b ldr r3, [r7, #4]
8002068: 685b ldr r3, [r3, #4]
800206a: 2b01 cmp r3, #1
800206c: d107 bne.n 800207e <HAL_RCC_ClockConfig+0x9e>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800206e: 4b44 ldr r3, [pc, #272] ; (8002180 <HAL_RCC_ClockConfig+0x1a0>)
8002070: 681a ldr r2, [r3, #0]
8002072: 2380 movs r3, #128 ; 0x80
8002074: 029b lsls r3, r3, #10
8002076: 4013 ands r3, r2
8002078: d120 bne.n 80020bc <HAL_RCC_ClockConfig+0xdc>
{
return HAL_ERROR;
800207a: 2301 movs r3, #1
800207c: e07a b.n 8002174 <HAL_RCC_ClockConfig+0x194>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
800207e: 687b ldr r3, [r7, #4]
8002080: 685b ldr r3, [r3, #4]
8002082: 2b02 cmp r3, #2
8002084: d107 bne.n 8002096 <HAL_RCC_ClockConfig+0xb6>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002086: 4b3e ldr r3, [pc, #248] ; (8002180 <HAL_RCC_ClockConfig+0x1a0>)
8002088: 681a ldr r2, [r3, #0]
800208a: 2380 movs r3, #128 ; 0x80
800208c: 049b lsls r3, r3, #18
800208e: 4013 ands r3, r2
8002090: d114 bne.n 80020bc <HAL_RCC_ClockConfig+0xdc>
{
return HAL_ERROR;
8002092: 2301 movs r3, #1
8002094: e06e b.n 8002174 <HAL_RCC_ClockConfig+0x194>
}
}
#if defined(RCC_CFGR_SWS_HSI48)
/* HSI48 is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
8002096: 687b ldr r3, [r7, #4]
8002098: 685b ldr r3, [r3, #4]
800209a: 2b03 cmp r3, #3
800209c: d107 bne.n 80020ae <HAL_RCC_ClockConfig+0xce>
{
/* Check the HSI48 ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
800209e: 4b38 ldr r3, [pc, #224] ; (8002180 <HAL_RCC_ClockConfig+0x1a0>)
80020a0: 6b5a ldr r2, [r3, #52] ; 0x34
80020a2: 2380 movs r3, #128 ; 0x80
80020a4: 029b lsls r3, r3, #10
80020a6: 4013 ands r3, r2
80020a8: d108 bne.n 80020bc <HAL_RCC_ClockConfig+0xdc>
{
return HAL_ERROR;
80020aa: 2301 movs r3, #1
80020ac: e062 b.n 8002174 <HAL_RCC_ClockConfig+0x194>
#endif /* RCC_CFGR_SWS_HSI48 */
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80020ae: 4b34 ldr r3, [pc, #208] ; (8002180 <HAL_RCC_ClockConfig+0x1a0>)
80020b0: 681b ldr r3, [r3, #0]
80020b2: 2202 movs r2, #2
80020b4: 4013 ands r3, r2
80020b6: d101 bne.n 80020bc <HAL_RCC_ClockConfig+0xdc>
{
return HAL_ERROR;
80020b8: 2301 movs r3, #1
80020ba: e05b b.n 8002174 <HAL_RCC_ClockConfig+0x194>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
80020bc: 4b30 ldr r3, [pc, #192] ; (8002180 <HAL_RCC_ClockConfig+0x1a0>)
80020be: 685b ldr r3, [r3, #4]
80020c0: 2203 movs r2, #3
80020c2: 4393 bics r3, r2
80020c4: 0019 movs r1, r3
80020c6: 687b ldr r3, [r7, #4]
80020c8: 685a ldr r2, [r3, #4]
80020ca: 4b2d ldr r3, [pc, #180] ; (8002180 <HAL_RCC_ClockConfig+0x1a0>)
80020cc: 430a orrs r2, r1
80020ce: 605a str r2, [r3, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
80020d0: f7fe fbc2 bl 8000858 <HAL_GetTick>
80020d4: 0003 movs r3, r0
80020d6: 60fb str r3, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80020d8: e009 b.n 80020ee <HAL_RCC_ClockConfig+0x10e>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
80020da: f7fe fbbd bl 8000858 <HAL_GetTick>
80020de: 0002 movs r2, r0
80020e0: 68fb ldr r3, [r7, #12]
80020e2: 1ad3 subs r3, r2, r3
80020e4: 4a27 ldr r2, [pc, #156] ; (8002184 <HAL_RCC_ClockConfig+0x1a4>)
80020e6: 4293 cmp r3, r2
80020e8: d901 bls.n 80020ee <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
80020ea: 2303 movs r3, #3
80020ec: e042 b.n 8002174 <HAL_RCC_ClockConfig+0x194>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80020ee: 4b24 ldr r3, [pc, #144] ; (8002180 <HAL_RCC_ClockConfig+0x1a0>)
80020f0: 685b ldr r3, [r3, #4]
80020f2: 220c movs r2, #12
80020f4: 401a ands r2, r3
80020f6: 687b ldr r3, [r7, #4]
80020f8: 685b ldr r3, [r3, #4]
80020fa: 009b lsls r3, r3, #2
80020fc: 429a cmp r2, r3
80020fe: d1ec bne.n 80020da <HAL_RCC_ClockConfig+0xfa>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8002100: 4b1e ldr r3, [pc, #120] ; (800217c <HAL_RCC_ClockConfig+0x19c>)
8002102: 681b ldr r3, [r3, #0]
8002104: 2201 movs r2, #1
8002106: 4013 ands r3, r2
8002108: 683a ldr r2, [r7, #0]
800210a: 429a cmp r2, r3
800210c: d211 bcs.n 8002132 <HAL_RCC_ClockConfig+0x152>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800210e: 4b1b ldr r3, [pc, #108] ; (800217c <HAL_RCC_ClockConfig+0x19c>)
8002110: 681b ldr r3, [r3, #0]
8002112: 2201 movs r2, #1
8002114: 4393 bics r3, r2
8002116: 0019 movs r1, r3
8002118: 4b18 ldr r3, [pc, #96] ; (800217c <HAL_RCC_ClockConfig+0x19c>)
800211a: 683a ldr r2, [r7, #0]
800211c: 430a orrs r2, r1
800211e: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8002120: 4b16 ldr r3, [pc, #88] ; (800217c <HAL_RCC_ClockConfig+0x19c>)
8002122: 681b ldr r3, [r3, #0]
8002124: 2201 movs r2, #1
8002126: 4013 ands r3, r2
8002128: 683a ldr r2, [r7, #0]
800212a: 429a cmp r2, r3
800212c: d001 beq.n 8002132 <HAL_RCC_ClockConfig+0x152>
{
return HAL_ERROR;
800212e: 2301 movs r3, #1
8002130: e020 b.n 8002174 <HAL_RCC_ClockConfig+0x194>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002132: 687b ldr r3, [r7, #4]
8002134: 681b ldr r3, [r3, #0]
8002136: 2204 movs r2, #4
8002138: 4013 ands r3, r2
800213a: d009 beq.n 8002150 <HAL_RCC_ClockConfig+0x170>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
800213c: 4b10 ldr r3, [pc, #64] ; (8002180 <HAL_RCC_ClockConfig+0x1a0>)
800213e: 685b ldr r3, [r3, #4]
8002140: 4a11 ldr r2, [pc, #68] ; (8002188 <HAL_RCC_ClockConfig+0x1a8>)
8002142: 4013 ands r3, r2
8002144: 0019 movs r1, r3
8002146: 687b ldr r3, [r7, #4]
8002148: 68da ldr r2, [r3, #12]
800214a: 4b0d ldr r3, [pc, #52] ; (8002180 <HAL_RCC_ClockConfig+0x1a0>)
800214c: 430a orrs r2, r1
800214e: 605a str r2, [r3, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
8002150: f000 f820 bl 8002194 <HAL_RCC_GetSysClockFreq>
8002154: 0001 movs r1, r0
8002156: 4b0a ldr r3, [pc, #40] ; (8002180 <HAL_RCC_ClockConfig+0x1a0>)
8002158: 685b ldr r3, [r3, #4]
800215a: 091b lsrs r3, r3, #4
800215c: 220f movs r2, #15
800215e: 4013 ands r3, r2
8002160: 4a0a ldr r2, [pc, #40] ; (800218c <HAL_RCC_ClockConfig+0x1ac>)
8002162: 5cd3 ldrb r3, [r2, r3]
8002164: 000a movs r2, r1
8002166: 40da lsrs r2, r3
8002168: 4b09 ldr r3, [pc, #36] ; (8002190 <HAL_RCC_ClockConfig+0x1b0>)
800216a: 601a str r2, [r3, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
800216c: 2003 movs r0, #3
800216e: f7fe fb2d bl 80007cc <HAL_InitTick>
return HAL_OK;
8002172: 2300 movs r3, #0
}
8002174: 0018 movs r0, r3
8002176: 46bd mov sp, r7
8002178: b004 add sp, #16
800217a: bd80 pop {r7, pc}
800217c: 40022000 .word 0x40022000
8002180: 40021000 .word 0x40021000
8002184: 00001388 .word 0x00001388
8002188: fffff8ff .word 0xfffff8ff
800218c: 080024d8 .word 0x080024d8
8002190: 20000000 .word 0x20000000
08002194 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8002194: b580 push {r7, lr}
8002196: b086 sub sp, #24
8002198: af00 add r7, sp, #0
static const uint8_t aPLLMULFactorTable[16U] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,
10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
static const uint8_t aPredivFactorTable[16U] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U,
9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
800219a: 2300 movs r3, #0
800219c: 60fb str r3, [r7, #12]
800219e: 2300 movs r3, #0
80021a0: 60bb str r3, [r7, #8]
80021a2: 2300 movs r3, #0
80021a4: 617b str r3, [r7, #20]
80021a6: 2300 movs r3, #0
80021a8: 607b str r3, [r7, #4]
uint32_t sysclockfreq = 0U;
80021aa: 2300 movs r3, #0
80021ac: 613b str r3, [r7, #16]
tmpreg = RCC->CFGR;
80021ae: 4b2d ldr r3, [pc, #180] ; (8002264 <HAL_RCC_GetSysClockFreq+0xd0>)
80021b0: 685b ldr r3, [r3, #4]
80021b2: 60fb str r3, [r7, #12]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
80021b4: 68fb ldr r3, [r7, #12]
80021b6: 220c movs r2, #12
80021b8: 4013 ands r3, r2
80021ba: 2b0c cmp r3, #12
80021bc: d046 beq.n 800224c <HAL_RCC_GetSysClockFreq+0xb8>
80021be: d848 bhi.n 8002252 <HAL_RCC_GetSysClockFreq+0xbe>
80021c0: 2b04 cmp r3, #4
80021c2: d002 beq.n 80021ca <HAL_RCC_GetSysClockFreq+0x36>
80021c4: 2b08 cmp r3, #8
80021c6: d003 beq.n 80021d0 <HAL_RCC_GetSysClockFreq+0x3c>
80021c8: e043 b.n 8002252 <HAL_RCC_GetSysClockFreq+0xbe>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
80021ca: 4b27 ldr r3, [pc, #156] ; (8002268 <HAL_RCC_GetSysClockFreq+0xd4>)
80021cc: 613b str r3, [r7, #16]
break;
80021ce: e043 b.n 8002258 <HAL_RCC_GetSysClockFreq+0xc4>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
80021d0: 68fb ldr r3, [r7, #12]
80021d2: 0c9b lsrs r3, r3, #18
80021d4: 220f movs r2, #15
80021d6: 4013 ands r3, r2
80021d8: 4a24 ldr r2, [pc, #144] ; (800226c <HAL_RCC_GetSysClockFreq+0xd8>)
80021da: 5cd3 ldrb r3, [r2, r3]
80021dc: 607b str r3, [r7, #4]
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
80021de: 4b21 ldr r3, [pc, #132] ; (8002264 <HAL_RCC_GetSysClockFreq+0xd0>)
80021e0: 6adb ldr r3, [r3, #44] ; 0x2c
80021e2: 220f movs r2, #15
80021e4: 4013 ands r3, r2
80021e6: 4a22 ldr r2, [pc, #136] ; (8002270 <HAL_RCC_GetSysClockFreq+0xdc>)
80021e8: 5cd3 ldrb r3, [r2, r3]
80021ea: 60bb str r3, [r7, #8]
if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
80021ec: 68fa ldr r2, [r7, #12]
80021ee: 23c0 movs r3, #192 ; 0xc0
80021f0: 025b lsls r3, r3, #9
80021f2: 401a ands r2, r3
80021f4: 2380 movs r3, #128 ; 0x80
80021f6: 025b lsls r3, r3, #9
80021f8: 429a cmp r2, r3
80021fa: d109 bne.n 8002210 <HAL_RCC_GetSysClockFreq+0x7c>
{
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
80021fc: 68b9 ldr r1, [r7, #8]
80021fe: 481a ldr r0, [pc, #104] ; (8002268 <HAL_RCC_GetSysClockFreq+0xd4>)
8002200: f7fd ff82 bl 8000108 <__udivsi3>
8002204: 0003 movs r3, r0
8002206: 001a movs r2, r3
8002208: 687b ldr r3, [r7, #4]
800220a: 4353 muls r3, r2
800220c: 617b str r3, [r7, #20]
800220e: e01a b.n 8002246 <HAL_RCC_GetSysClockFreq+0xb2>
}
#if defined(RCC_CFGR_PLLSRC_HSI48_PREDIV)
else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48)
8002210: 68fa ldr r2, [r7, #12]
8002212: 23c0 movs r3, #192 ; 0xc0
8002214: 025b lsls r3, r3, #9
8002216: 401a ands r2, r3
8002218: 23c0 movs r3, #192 ; 0xc0
800221a: 025b lsls r3, r3, #9
800221c: 429a cmp r2, r3
800221e: d109 bne.n 8002234 <HAL_RCC_GetSysClockFreq+0xa0>
{
/* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSI48_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
8002220: 68b9 ldr r1, [r7, #8]
8002222: 4814 ldr r0, [pc, #80] ; (8002274 <HAL_RCC_GetSysClockFreq+0xe0>)
8002224: f7fd ff70 bl 8000108 <__udivsi3>
8002228: 0003 movs r3, r0
800222a: 001a movs r2, r3
800222c: 687b ldr r3, [r7, #4]
800222e: 4353 muls r3, r2
8002230: 617b str r3, [r7, #20]
8002232: e008 b.n 8002246 <HAL_RCC_GetSysClockFreq+0xb2>
#endif /* RCC_CFGR_PLLSRC_HSI48_PREDIV */
else
{
#if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC))
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
8002234: 68b9 ldr r1, [r7, #8]
8002236: 480c ldr r0, [pc, #48] ; (8002268 <HAL_RCC_GetSysClockFreq+0xd4>)
8002238: f7fd ff66 bl 8000108 <__udivsi3>
800223c: 0003 movs r3, r0
800223e: 001a movs r2, r3
8002240: 687b ldr r3, [r7, #4]
8002242: 4353 muls r3, r2
8002244: 617b str r3, [r7, #20]
#else
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
#endif
}
sysclockfreq = pllclk;
8002246: 697b ldr r3, [r7, #20]
8002248: 613b str r3, [r7, #16]
break;
800224a: e005 b.n 8002258 <HAL_RCC_GetSysClockFreq+0xc4>
}
#if defined(RCC_CFGR_SWS_HSI48)
case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */
{
sysclockfreq = HSI48_VALUE;
800224c: 4b09 ldr r3, [pc, #36] ; (8002274 <HAL_RCC_GetSysClockFreq+0xe0>)
800224e: 613b str r3, [r7, #16]
break;
8002250: e002 b.n 8002258 <HAL_RCC_GetSysClockFreq+0xc4>
}
#endif /* RCC_CFGR_SWS_HSI48 */
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
8002252: 4b05 ldr r3, [pc, #20] ; (8002268 <HAL_RCC_GetSysClockFreq+0xd4>)
8002254: 613b str r3, [r7, #16]
break;
8002256: 46c0 nop ; (mov r8, r8)
}
}
return sysclockfreq;
8002258: 693b ldr r3, [r7, #16]
}
800225a: 0018 movs r0, r3
800225c: 46bd mov sp, r7
800225e: b006 add sp, #24
8002260: bd80 pop {r7, pc}
8002262: 46c0 nop ; (mov r8, r8)
8002264: 40021000 .word 0x40021000
8002268: 007a1200 .word 0x007a1200
800226c: 080024e8 .word 0x080024e8
8002270: 080024f8 .word 0x080024f8
8002274: 02dc6c00 .word 0x02dc6c00
08002278 <HAL_RCCEx_PeriphCLKConfig>:
* the backup registers) and RCC_BDCR register are set to their reset values.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8002278: b580 push {r7, lr}
800227a: b086 sub sp, #24
800227c: af00 add r7, sp, #0
800227e: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
8002280: 2300 movs r3, #0
8002282: 613b str r3, [r7, #16]
uint32_t temp_reg = 0U;
8002284: 2300 movs r3, #0
8002286: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*---------------------------- RTC configuration -------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
8002288: 687b ldr r3, [r7, #4]
800228a: 681a ldr r2, [r3, #0]
800228c: 2380 movs r3, #128 ; 0x80
800228e: 025b lsls r3, r3, #9
8002290: 4013 ands r3, r2
8002292: d100 bne.n 8002296 <HAL_RCCEx_PeriphCLKConfig+0x1e>
8002294: e08e b.n 80023b4 <HAL_RCCEx_PeriphCLKConfig+0x13c>
{
/* check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
FlagStatus pwrclkchanged = RESET;
8002296: 2017 movs r0, #23
8002298: 183b adds r3, r7, r0
800229a: 2200 movs r2, #0
800229c: 701a strb r2, [r3, #0]
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
800229e: 4b67 ldr r3, [pc, #412] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
80022a0: 69da ldr r2, [r3, #28]
80022a2: 2380 movs r3, #128 ; 0x80
80022a4: 055b lsls r3, r3, #21
80022a6: 4013 ands r3, r2
80022a8: d110 bne.n 80022cc <HAL_RCCEx_PeriphCLKConfig+0x54>
{
__HAL_RCC_PWR_CLK_ENABLE();
80022aa: 4b64 ldr r3, [pc, #400] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
80022ac: 69da ldr r2, [r3, #28]
80022ae: 4b63 ldr r3, [pc, #396] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
80022b0: 2180 movs r1, #128 ; 0x80
80022b2: 0549 lsls r1, r1, #21
80022b4: 430a orrs r2, r1
80022b6: 61da str r2, [r3, #28]
80022b8: 4b60 ldr r3, [pc, #384] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
80022ba: 69da ldr r2, [r3, #28]
80022bc: 2380 movs r3, #128 ; 0x80
80022be: 055b lsls r3, r3, #21
80022c0: 4013 ands r3, r2
80022c2: 60bb str r3, [r7, #8]
80022c4: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
80022c6: 183b adds r3, r7, r0
80022c8: 2201 movs r2, #1
80022ca: 701a strb r2, [r3, #0]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80022cc: 4b5c ldr r3, [pc, #368] ; (8002440 <HAL_RCCEx_PeriphCLKConfig+0x1c8>)
80022ce: 681a ldr r2, [r3, #0]
80022d0: 2380 movs r3, #128 ; 0x80
80022d2: 005b lsls r3, r3, #1
80022d4: 4013 ands r3, r2
80022d6: d11a bne.n 800230e <HAL_RCCEx_PeriphCLKConfig+0x96>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
80022d8: 4b59 ldr r3, [pc, #356] ; (8002440 <HAL_RCCEx_PeriphCLKConfig+0x1c8>)
80022da: 681a ldr r2, [r3, #0]
80022dc: 4b58 ldr r3, [pc, #352] ; (8002440 <HAL_RCCEx_PeriphCLKConfig+0x1c8>)
80022de: 2180 movs r1, #128 ; 0x80
80022e0: 0049 lsls r1, r1, #1
80022e2: 430a orrs r2, r1
80022e4: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80022e6: f7fe fab7 bl 8000858 <HAL_GetTick>
80022ea: 0003 movs r3, r0
80022ec: 613b str r3, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80022ee: e008 b.n 8002302 <HAL_RCCEx_PeriphCLKConfig+0x8a>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80022f0: f7fe fab2 bl 8000858 <HAL_GetTick>
80022f4: 0002 movs r2, r0
80022f6: 693b ldr r3, [r7, #16]
80022f8: 1ad3 subs r3, r2, r3
80022fa: 2b64 cmp r3, #100 ; 0x64
80022fc: d901 bls.n 8002302 <HAL_RCCEx_PeriphCLKConfig+0x8a>
{
return HAL_TIMEOUT;
80022fe: 2303 movs r3, #3
8002300: e097 b.n 8002432 <HAL_RCCEx_PeriphCLKConfig+0x1ba>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8002302: 4b4f ldr r3, [pc, #316] ; (8002440 <HAL_RCCEx_PeriphCLKConfig+0x1c8>)
8002304: 681a ldr r2, [r3, #0]
8002306: 2380 movs r3, #128 ; 0x80
8002308: 005b lsls r3, r3, #1
800230a: 4013 ands r3, r2
800230c: d0f0 beq.n 80022f0 <HAL_RCCEx_PeriphCLKConfig+0x78>
}
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
800230e: 4b4b ldr r3, [pc, #300] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
8002310: 6a1a ldr r2, [r3, #32]
8002312: 23c0 movs r3, #192 ; 0xc0
8002314: 009b lsls r3, r3, #2
8002316: 4013 ands r3, r2
8002318: 60fb str r3, [r7, #12]
if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
800231a: 68fb ldr r3, [r7, #12]
800231c: 2b00 cmp r3, #0
800231e: d034 beq.n 800238a <HAL_RCCEx_PeriphCLKConfig+0x112>
8002320: 687b ldr r3, [r7, #4]
8002322: 685a ldr r2, [r3, #4]
8002324: 23c0 movs r3, #192 ; 0xc0
8002326: 009b lsls r3, r3, #2
8002328: 4013 ands r3, r2
800232a: 68fa ldr r2, [r7, #12]
800232c: 429a cmp r2, r3
800232e: d02c beq.n 800238a <HAL_RCCEx_PeriphCLKConfig+0x112>
{
/* Store the content of BDCR register before the reset of Backup Domain */
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
8002330: 4b42 ldr r3, [pc, #264] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
8002332: 6a1b ldr r3, [r3, #32]
8002334: 4a43 ldr r2, [pc, #268] ; (8002444 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
8002336: 4013 ands r3, r2
8002338: 60fb str r3, [r7, #12]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
800233a: 4b40 ldr r3, [pc, #256] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
800233c: 6a1a ldr r2, [r3, #32]
800233e: 4b3f ldr r3, [pc, #252] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
8002340: 2180 movs r1, #128 ; 0x80
8002342: 0249 lsls r1, r1, #9
8002344: 430a orrs r2, r1
8002346: 621a str r2, [r3, #32]
__HAL_RCC_BACKUPRESET_RELEASE();
8002348: 4b3c ldr r3, [pc, #240] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
800234a: 6a1a ldr r2, [r3, #32]
800234c: 4b3b ldr r3, [pc, #236] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
800234e: 493e ldr r1, [pc, #248] ; (8002448 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002350: 400a ands r2, r1
8002352: 621a str r2, [r3, #32]
/* Restore the Content of BDCR register */
RCC->BDCR = temp_reg;
8002354: 4b39 ldr r3, [pc, #228] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
8002356: 68fa ldr r2, [r7, #12]
8002358: 621a str r2, [r3, #32]
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
800235a: 68fb ldr r3, [r7, #12]
800235c: 2201 movs r2, #1
800235e: 4013 ands r3, r2
8002360: d013 beq.n 800238a <HAL_RCCEx_PeriphCLKConfig+0x112>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002362: f7fe fa79 bl 8000858 <HAL_GetTick>
8002366: 0003 movs r3, r0
8002368: 613b str r3, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800236a: e009 b.n 8002380 <HAL_RCCEx_PeriphCLKConfig+0x108>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800236c: f7fe fa74 bl 8000858 <HAL_GetTick>
8002370: 0002 movs r2, r0
8002372: 693b ldr r3, [r7, #16]
8002374: 1ad3 subs r3, r2, r3
8002376: 4a35 ldr r2, [pc, #212] ; (800244c <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
8002378: 4293 cmp r3, r2
800237a: d901 bls.n 8002380 <HAL_RCCEx_PeriphCLKConfig+0x108>
{
return HAL_TIMEOUT;
800237c: 2303 movs r3, #3
800237e: e058 b.n 8002432 <HAL_RCCEx_PeriphCLKConfig+0x1ba>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8002380: 4b2e ldr r3, [pc, #184] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
8002382: 6a1b ldr r3, [r3, #32]
8002384: 2202 movs r2, #2
8002386: 4013 ands r3, r2
8002388: d0f0 beq.n 800236c <HAL_RCCEx_PeriphCLKConfig+0xf4>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
800238a: 4b2c ldr r3, [pc, #176] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
800238c: 6a1b ldr r3, [r3, #32]
800238e: 4a2d ldr r2, [pc, #180] ; (8002444 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
8002390: 4013 ands r3, r2
8002392: 0019 movs r1, r3
8002394: 687b ldr r3, [r7, #4]
8002396: 685a ldr r2, [r3, #4]
8002398: 4b28 ldr r3, [pc, #160] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
800239a: 430a orrs r2, r1
800239c: 621a str r2, [r3, #32]
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
800239e: 2317 movs r3, #23
80023a0: 18fb adds r3, r7, r3
80023a2: 781b ldrb r3, [r3, #0]
80023a4: 2b01 cmp r3, #1
80023a6: d105 bne.n 80023b4 <HAL_RCCEx_PeriphCLKConfig+0x13c>
{
__HAL_RCC_PWR_CLK_DISABLE();
80023a8: 4b24 ldr r3, [pc, #144] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
80023aa: 69da ldr r2, [r3, #28]
80023ac: 4b23 ldr r3, [pc, #140] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
80023ae: 4928 ldr r1, [pc, #160] ; (8002450 <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
80023b0: 400a ands r2, r1
80023b2: 61da str r2, [r3, #28]
}
}
/*------------------------------- USART1 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
80023b4: 687b ldr r3, [r7, #4]
80023b6: 681b ldr r3, [r3, #0]
80023b8: 2201 movs r2, #1
80023ba: 4013 ands r3, r2
80023bc: d009 beq.n 80023d2 <HAL_RCCEx_PeriphCLKConfig+0x15a>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
80023be: 4b1f ldr r3, [pc, #124] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
80023c0: 6b1b ldr r3, [r3, #48] ; 0x30
80023c2: 2203 movs r2, #3
80023c4: 4393 bics r3, r2
80023c6: 0019 movs r1, r3
80023c8: 687b ldr r3, [r7, #4]
80023ca: 689a ldr r2, [r3, #8]
80023cc: 4b1b ldr r3, [pc, #108] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
80023ce: 430a orrs r2, r1
80023d0: 631a str r2, [r3, #48] ; 0x30
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
}
#endif /* STM32F091xC || STM32F098xx */
/*------------------------------ I2C1 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
80023d2: 687b ldr r3, [r7, #4]
80023d4: 681b ldr r3, [r3, #0]
80023d6: 2220 movs r2, #32
80023d8: 4013 ands r3, r2
80023da: d009 beq.n 80023f0 <HAL_RCCEx_PeriphCLKConfig+0x178>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
80023dc: 4b17 ldr r3, [pc, #92] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
80023de: 6b1b ldr r3, [r3, #48] ; 0x30
80023e0: 2210 movs r2, #16
80023e2: 4393 bics r3, r2
80023e4: 0019 movs r1, r3
80023e6: 687b ldr r3, [r7, #4]
80023e8: 68da ldr r2, [r3, #12]
80023ea: 4b14 ldr r3, [pc, #80] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
80023ec: 430a orrs r2, r1
80023ee: 631a str r2, [r3, #48] ; 0x30
}
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6)
/*------------------------------ USB Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
80023f0: 687b ldr r3, [r7, #4]
80023f2: 681a ldr r2, [r3, #0]
80023f4: 2380 movs r3, #128 ; 0x80
80023f6: 029b lsls r3, r3, #10
80023f8: 4013 ands r3, r2
80023fa: d009 beq.n 8002410 <HAL_RCCEx_PeriphCLKConfig+0x198>
{
/* Check the parameters */
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
/* Configure the USB clock source */
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
80023fc: 4b0f ldr r3, [pc, #60] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
80023fe: 6b1b ldr r3, [r3, #48] ; 0x30
8002400: 2280 movs r2, #128 ; 0x80
8002402: 4393 bics r3, r2
8002404: 0019 movs r1, r3
8002406: 687b ldr r3, [r7, #4]
8002408: 695a ldr r2, [r3, #20]
800240a: 4b0c ldr r3, [pc, #48] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
800240c: 430a orrs r2, r1
800240e: 631a str r2, [r3, #48] ; 0x30
#if defined(STM32F042x6) || defined(STM32F048xx)\
|| defined(STM32F051x8) || defined(STM32F058xx)\
|| defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|| defined(STM32F091xC) || defined(STM32F098xx)
/*------------------------------ CEC clock Configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
8002410: 687b ldr r3, [r7, #4]
8002412: 681a ldr r2, [r3, #0]
8002414: 2380 movs r3, #128 ; 0x80
8002416: 00db lsls r3, r3, #3
8002418: 4013 ands r3, r2
800241a: d009 beq.n 8002430 <HAL_RCCEx_PeriphCLKConfig+0x1b8>
{
/* Check the parameters */
assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
/* Configure the CEC clock source */
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
800241c: 4b07 ldr r3, [pc, #28] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
800241e: 6b1b ldr r3, [r3, #48] ; 0x30
8002420: 2240 movs r2, #64 ; 0x40
8002422: 4393 bics r3, r2
8002424: 0019 movs r1, r3
8002426: 687b ldr r3, [r7, #4]
8002428: 691a ldr r2, [r3, #16]
800242a: 4b04 ldr r3, [pc, #16] ; (800243c <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
800242c: 430a orrs r2, r1
800242e: 631a str r2, [r3, #48] ; 0x30
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
return HAL_OK;
8002430: 2300 movs r3, #0
}
8002432: 0018 movs r0, r3
8002434: 46bd mov sp, r7
8002436: b006 add sp, #24
8002438: bd80 pop {r7, pc}
800243a: 46c0 nop ; (mov r8, r8)
800243c: 40021000 .word 0x40021000
8002440: 40007000 .word 0x40007000
8002444: fffffcff .word 0xfffffcff
8002448: fffeffff .word 0xfffeffff
800244c: 00001388 .word 0x00001388
8002450: efffffff .word 0xefffffff
08002454 <__libc_init_array>:
8002454: b570 push {r4, r5, r6, lr}
8002456: 2600 movs r6, #0
8002458: 4d0c ldr r5, [pc, #48] ; (800248c <__libc_init_array+0x38>)
800245a: 4c0d ldr r4, [pc, #52] ; (8002490 <__libc_init_array+0x3c>)
800245c: 1b64 subs r4, r4, r5
800245e: 10a4 asrs r4, r4, #2
8002460: 42a6 cmp r6, r4
8002462: d109 bne.n 8002478 <__libc_init_array+0x24>
8002464: 2600 movs r6, #0
8002466: f000 f82b bl 80024c0 <_init>
800246a: 4d0a ldr r5, [pc, #40] ; (8002494 <__libc_init_array+0x40>)
800246c: 4c0a ldr r4, [pc, #40] ; (8002498 <__libc_init_array+0x44>)
800246e: 1b64 subs r4, r4, r5
8002470: 10a4 asrs r4, r4, #2
8002472: 42a6 cmp r6, r4
8002474: d105 bne.n 8002482 <__libc_init_array+0x2e>
8002476: bd70 pop {r4, r5, r6, pc}
8002478: 00b3 lsls r3, r6, #2
800247a: 58eb ldr r3, [r5, r3]
800247c: 4798 blx r3
800247e: 3601 adds r6, #1
8002480: e7ee b.n 8002460 <__libc_init_array+0xc>
8002482: 00b3 lsls r3, r6, #2
8002484: 58eb ldr r3, [r5, r3]
8002486: 4798 blx r3
8002488: 3601 adds r6, #1
800248a: e7f2 b.n 8002472 <__libc_init_array+0x1e>
800248c: 08002508 .word 0x08002508
8002490: 08002508 .word 0x08002508
8002494: 08002508 .word 0x08002508
8002498: 0800250c .word 0x0800250c
0800249c <memcpy>:
800249c: 2300 movs r3, #0
800249e: b510 push {r4, lr}
80024a0: 429a cmp r2, r3
80024a2: d100 bne.n 80024a6 <memcpy+0xa>
80024a4: bd10 pop {r4, pc}
80024a6: 5ccc ldrb r4, [r1, r3]
80024a8: 54c4 strb r4, [r0, r3]
80024aa: 3301 adds r3, #1
80024ac: e7f8 b.n 80024a0 <memcpy+0x4>
080024ae <memset>:
80024ae: 0003 movs r3, r0
80024b0: 1882 adds r2, r0, r2
80024b2: 4293 cmp r3, r2
80024b4: d100 bne.n 80024b8 <memset+0xa>
80024b6: 4770 bx lr
80024b8: 7019 strb r1, [r3, #0]
80024ba: 3301 adds r3, #1
80024bc: e7f9 b.n 80024b2 <memset+0x4>
...
080024c0 <_init>:
80024c0: b5f8 push {r3, r4, r5, r6, r7, lr}
80024c2: 46c0 nop ; (mov r8, r8)
80024c4: bcf8 pop {r3, r4, r5, r6, r7}
80024c6: bc08 pop {r3}
80024c8: 469e mov lr, r3
80024ca: 4770 bx lr
080024cc <_fini>:
80024cc: b5f8 push {r3, r4, r5, r6, r7, lr}
80024ce: 46c0 nop ; (mov r8, r8)
80024d0: bcf8 pop {r3, r4, r5, r6, r7}
80024d2: bc08 pop {r3}
80024d4: 469e mov lr, r3
80024d6: 4770 bx lr
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