TTS.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000000c0 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00001b0c 080000c0 080000c0 000100c0 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000030 08001bcc 08001bcc 00011bcc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08001bfc 08001bfc 0002000c 2**0 CONTENTS 4 .ARM 00000000 08001bfc 08001bfc 0002000c 2**0 CONTENTS 5 .preinit_array 00000000 08001bfc 08001bfc 0002000c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08001bfc 08001bfc 00011bfc 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08001c00 08001c00 00011c00 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 0000000c 20000000 08001c04 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 0000009c 2000000c 08001c10 0002000c 2**2 ALLOC 10 ._user_heap_stack 00000600 200000a8 08001c10 000200a8 2**0 ALLOC 11 .ARM.attributes 00000028 00000000 00000000 0002000c 2**0 CONTENTS, READONLY 12 .debug_info 00007d0d 00000000 00000000 00020034 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00001674 00000000 00000000 00027d41 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00000818 00000000 00000000 000293b8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_ranges 00000750 00000000 00000000 00029bd0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00001505 00000000 00000000 0002a320 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0000a45a 00000000 00000000 0002b825 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 00084768 00000000 00000000 00035c7f 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000050 00000000 00000000 000ba3e7 2**0 CONTENTS, READONLY 20 .debug_frame 00001bf4 00000000 00000000 000ba438 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080000c0 <__do_global_dtors_aux>: 80000c0: b510 push {r4, lr} 80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>) 80000c4: 7823 ldrb r3, [r4, #0] 80000c6: 2b00 cmp r3, #0 80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a> 80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>) 80000cc: 2b00 cmp r3, #0 80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16> 80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>) 80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16> 80000d4: bf00 nop 80000d6: 2301 movs r3, #1 80000d8: 7023 strb r3, [r4, #0] 80000da: bd10 pop {r4, pc} 80000dc: 2000000c .word 0x2000000c 80000e0: 00000000 .word 0x00000000 80000e4: 08001bb4 .word 0x08001bb4 080000e8 : 80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc ) 80000ea: b510 push {r4, lr} 80000ec: 2b00 cmp r3, #0 80000ee: d003 beq.n 80000f8 80000f0: 4903 ldr r1, [pc, #12] ; (8000100 ) 80000f2: 4804 ldr r0, [pc, #16] ; (8000104 ) 80000f4: e000 b.n 80000f8 80000f6: bf00 nop 80000f8: bd10 pop {r4, pc} 80000fa: 46c0 nop ; (mov r8, r8) 80000fc: 00000000 .word 0x00000000 8000100: 20000010 .word 0x20000010 8000104: 08001bb4 .word 0x08001bb4 08000108 <__udivsi3>: 8000108: 2200 movs r2, #0 800010a: 0843 lsrs r3, r0, #1 800010c: 428b cmp r3, r1 800010e: d374 bcc.n 80001fa <__udivsi3+0xf2> 8000110: 0903 lsrs r3, r0, #4 8000112: 428b cmp r3, r1 8000114: d35f bcc.n 80001d6 <__udivsi3+0xce> 8000116: 0a03 lsrs r3, r0, #8 8000118: 428b cmp r3, r1 800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e> 800011c: 0b03 lsrs r3, r0, #12 800011e: 428b cmp r3, r1 8000120: d328 bcc.n 8000174 <__udivsi3+0x6c> 8000122: 0c03 lsrs r3, r0, #16 8000124: 428b cmp r3, r1 8000126: d30d bcc.n 8000144 <__udivsi3+0x3c> 8000128: 22ff movs r2, #255 ; 0xff 800012a: 0209 lsls r1, r1, #8 800012c: ba12 rev r2, r2 800012e: 0c03 lsrs r3, r0, #16 8000130: 428b cmp r3, r1 8000132: d302 bcc.n 800013a <__udivsi3+0x32> 8000134: 1212 asrs r2, r2, #8 8000136: 0209 lsls r1, r1, #8 8000138: d065 beq.n 8000206 <__udivsi3+0xfe> 800013a: 0b03 lsrs r3, r0, #12 800013c: 428b cmp r3, r1 800013e: d319 bcc.n 8000174 <__udivsi3+0x6c> 8000140: e000 b.n 8000144 <__udivsi3+0x3c> 8000142: 0a09 lsrs r1, r1, #8 8000144: 0bc3 lsrs r3, r0, #15 8000146: 428b cmp r3, r1 8000148: d301 bcc.n 800014e <__udivsi3+0x46> 800014a: 03cb lsls r3, r1, #15 800014c: 1ac0 subs r0, r0, r3 800014e: 4152 adcs r2, r2 8000150: 0b83 lsrs r3, r0, #14 8000152: 428b cmp r3, r1 8000154: d301 bcc.n 800015a <__udivsi3+0x52> 8000156: 038b lsls r3, r1, #14 8000158: 1ac0 subs r0, r0, r3 800015a: 4152 adcs r2, r2 800015c: 0b43 lsrs r3, r0, #13 800015e: 428b cmp r3, r1 8000160: d301 bcc.n 8000166 <__udivsi3+0x5e> 8000162: 034b lsls r3, r1, #13 8000164: 1ac0 subs r0, r0, r3 8000166: 4152 adcs r2, r2 8000168: 0b03 lsrs r3, r0, #12 800016a: 428b cmp r3, r1 800016c: d301 bcc.n 8000172 <__udivsi3+0x6a> 800016e: 030b lsls r3, r1, #12 8000170: 1ac0 subs r0, r0, r3 8000172: 4152 adcs r2, r2 8000174: 0ac3 lsrs r3, r0, #11 8000176: 428b cmp r3, r1 8000178: d301 bcc.n 800017e <__udivsi3+0x76> 800017a: 02cb lsls r3, r1, #11 800017c: 1ac0 subs r0, r0, r3 800017e: 4152 adcs r2, r2 8000180: 0a83 lsrs r3, r0, #10 8000182: 428b cmp r3, r1 8000184: d301 bcc.n 800018a <__udivsi3+0x82> 8000186: 028b lsls r3, r1, #10 8000188: 1ac0 subs r0, r0, r3 800018a: 4152 adcs r2, r2 800018c: 0a43 lsrs r3, r0, #9 800018e: 428b cmp r3, r1 8000190: d301 bcc.n 8000196 <__udivsi3+0x8e> 8000192: 024b lsls r3, r1, #9 8000194: 1ac0 subs r0, r0, r3 8000196: 4152 adcs r2, r2 8000198: 0a03 lsrs r3, r0, #8 800019a: 428b cmp r3, r1 800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a> 800019e: 020b lsls r3, r1, #8 80001a0: 1ac0 subs r0, r0, r3 80001a2: 4152 adcs r2, r2 80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a> 80001a6: 09c3 lsrs r3, r0, #7 80001a8: 428b cmp r3, r1 80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8> 80001ac: 01cb lsls r3, r1, #7 80001ae: 1ac0 subs r0, r0, r3 80001b0: 4152 adcs r2, r2 80001b2: 0983 lsrs r3, r0, #6 80001b4: 428b cmp r3, r1 80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4> 80001b8: 018b lsls r3, r1, #6 80001ba: 1ac0 subs r0, r0, r3 80001bc: 4152 adcs r2, r2 80001be: 0943 lsrs r3, r0, #5 80001c0: 428b cmp r3, r1 80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0> 80001c4: 014b lsls r3, r1, #5 80001c6: 1ac0 subs r0, r0, r3 80001c8: 4152 adcs r2, r2 80001ca: 0903 lsrs r3, r0, #4 80001cc: 428b cmp r3, r1 80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc> 80001d0: 010b lsls r3, r1, #4 80001d2: 1ac0 subs r0, r0, r3 80001d4: 4152 adcs r2, r2 80001d6: 08c3 lsrs r3, r0, #3 80001d8: 428b cmp r3, r1 80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8> 80001dc: 00cb lsls r3, r1, #3 80001de: 1ac0 subs r0, r0, r3 80001e0: 4152 adcs r2, r2 80001e2: 0883 lsrs r3, r0, #2 80001e4: 428b cmp r3, r1 80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4> 80001e8: 008b lsls r3, r1, #2 80001ea: 1ac0 subs r0, r0, r3 80001ec: 4152 adcs r2, r2 80001ee: 0843 lsrs r3, r0, #1 80001f0: 428b cmp r3, r1 80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0> 80001f4: 004b lsls r3, r1, #1 80001f6: 1ac0 subs r0, r0, r3 80001f8: 4152 adcs r2, r2 80001fa: 1a41 subs r1, r0, r1 80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8> 80001fe: 4601 mov r1, r0 8000200: 4152 adcs r2, r2 8000202: 4610 mov r0, r2 8000204: 4770 bx lr 8000206: e7ff b.n 8000208 <__udivsi3+0x100> 8000208: b501 push {r0, lr} 800020a: 2000 movs r0, #0 800020c: f000 f806 bl 800021c <__aeabi_idiv0> 8000210: bd02 pop {r1, pc} 8000212: 46c0 nop ; (mov r8, r8) 08000214 <__aeabi_uidivmod>: 8000214: 2900 cmp r1, #0 8000216: d0f7 beq.n 8000208 <__udivsi3+0x100> 8000218: e776 b.n 8000108 <__udivsi3> 800021a: 4770 bx lr 0800021c <__aeabi_idiv0>: 800021c: 4770 bx lr 800021e: 46c0 nop ; (mov r8, r8) 08000220
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000220: b580 push {r7, lr} 8000222: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000224: f000 fa2e bl 8000684 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000228: f000 f807 bl 800023a /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800022c: f000 f8d2 bl 80003d4 MX_CAN_Init(); 8000230: f000 f85a bl 80002e8 MX_I2C1_Init(); 8000234: f000 f88e bl 8000354 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8000238: e7fe b.n 8000238 0800023a : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800023a: b590 push {r4, r7, lr} 800023c: b099 sub sp, #100 ; 0x64 800023e: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000240: 242c movs r4, #44 ; 0x2c 8000242: 193b adds r3, r7, r4 8000244: 0018 movs r0, r3 8000246: 2334 movs r3, #52 ; 0x34 8000248: 001a movs r2, r3 800024a: 2100 movs r1, #0 800024c: f001 fcaa bl 8001ba4 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000250: 231c movs r3, #28 8000252: 18fb adds r3, r7, r3 8000254: 0018 movs r0, r3 8000256: 2310 movs r3, #16 8000258: 001a movs r2, r3 800025a: 2100 movs r1, #0 800025c: f001 fca2 bl 8001ba4 RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8000260: 1d3b adds r3, r7, #4 8000262: 0018 movs r0, r3 8000264: 2318 movs r3, #24 8000266: 001a movs r2, r3 8000268: 2100 movs r1, #0 800026a: f001 fc9b bl 8001ba4 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 800026e: 0021 movs r1, r4 8000270: 187b adds r3, r7, r1 8000272: 2202 movs r2, #2 8000274: 601a str r2, [r3, #0] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8000276: 187b adds r3, r7, r1 8000278: 2201 movs r2, #1 800027a: 60da str r2, [r3, #12] RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 800027c: 187b adds r3, r7, r1 800027e: 2210 movs r2, #16 8000280: 611a str r2, [r3, #16] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 8000282: 187b adds r3, r7, r1 8000284: 2200 movs r2, #0 8000286: 625a str r2, [r3, #36] ; 0x24 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000288: 187b adds r3, r7, r1 800028a: 0018 movs r0, r3 800028c: f000 fea6 bl 8000fdc 8000290: 1e03 subs r3, r0, #0 8000292: d001 beq.n 8000298 { Error_Handler(); 8000294: f000 f8d2 bl 800043c } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000298: 211c movs r1, #28 800029a: 187b adds r3, r7, r1 800029c: 2207 movs r2, #7 800029e: 601a str r2, [r3, #0] |RCC_CLOCKTYPE_PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; 80002a0: 187b adds r3, r7, r1 80002a2: 2200 movs r2, #0 80002a4: 605a str r2, [r3, #4] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80002a6: 187b adds r3, r7, r1 80002a8: 2200 movs r2, #0 80002aa: 609a str r2, [r3, #8] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 80002ac: 187b adds r3, r7, r1 80002ae: 2200 movs r2, #0 80002b0: 60da str r2, [r3, #12] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 80002b2: 187b adds r3, r7, r1 80002b4: 2100 movs r1, #0 80002b6: 0018 movs r0, r3 80002b8: f001 fa16 bl 80016e8 80002bc: 1e03 subs r3, r0, #0 80002be: d001 beq.n 80002c4 { Error_Handler(); 80002c0: f000 f8bc bl 800043c } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1; 80002c4: 1d3b adds r3, r7, #4 80002c6: 2220 movs r2, #32 80002c8: 601a str r2, [r3, #0] PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_HSI; 80002ca: 1d3b adds r3, r7, #4 80002cc: 2200 movs r2, #0 80002ce: 60da str r2, [r3, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 80002d0: 1d3b adds r3, r7, #4 80002d2: 0018 movs r0, r3 80002d4: f001 fb54 bl 8001980 80002d8: 1e03 subs r3, r0, #0 80002da: d001 beq.n 80002e0 { Error_Handler(); 80002dc: f000 f8ae bl 800043c } } 80002e0: 46c0 nop ; (mov r8, r8) 80002e2: 46bd mov sp, r7 80002e4: b019 add sp, #100 ; 0x64 80002e6: bd90 pop {r4, r7, pc} 080002e8 : * @brief CAN Initialization Function * @param None * @retval None */ static void MX_CAN_Init(void) { 80002e8: b580 push {r7, lr} 80002ea: af00 add r7, sp, #0 /* USER CODE END CAN_Init 0 */ /* USER CODE BEGIN CAN_Init 1 */ /* USER CODE END CAN_Init 1 */ hcan.Instance = CAN; 80002ec: 4b17 ldr r3, [pc, #92] ; (800034c ) 80002ee: 4a18 ldr r2, [pc, #96] ; (8000350 ) 80002f0: 601a str r2, [r3, #0] hcan.Init.Prescaler = 16; 80002f2: 4b16 ldr r3, [pc, #88] ; (800034c ) 80002f4: 2210 movs r2, #16 80002f6: 605a str r2, [r3, #4] hcan.Init.Mode = CAN_MODE_NORMAL; 80002f8: 4b14 ldr r3, [pc, #80] ; (800034c ) 80002fa: 2200 movs r2, #0 80002fc: 609a str r2, [r3, #8] hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; 80002fe: 4b13 ldr r3, [pc, #76] ; (800034c ) 8000300: 2200 movs r2, #0 8000302: 60da str r2, [r3, #12] hcan.Init.TimeSeg1 = CAN_BS1_1TQ; 8000304: 4b11 ldr r3, [pc, #68] ; (800034c ) 8000306: 2200 movs r2, #0 8000308: 611a str r2, [r3, #16] hcan.Init.TimeSeg2 = CAN_BS2_1TQ; 800030a: 4b10 ldr r3, [pc, #64] ; (800034c ) 800030c: 2200 movs r2, #0 800030e: 615a str r2, [r3, #20] hcan.Init.TimeTriggeredMode = DISABLE; 8000310: 4b0e ldr r3, [pc, #56] ; (800034c ) 8000312: 2200 movs r2, #0 8000314: 761a strb r2, [r3, #24] hcan.Init.AutoBusOff = DISABLE; 8000316: 4b0d ldr r3, [pc, #52] ; (800034c ) 8000318: 2200 movs r2, #0 800031a: 765a strb r2, [r3, #25] hcan.Init.AutoWakeUp = DISABLE; 800031c: 4b0b ldr r3, [pc, #44] ; (800034c ) 800031e: 2200 movs r2, #0 8000320: 769a strb r2, [r3, #26] hcan.Init.AutoRetransmission = DISABLE; 8000322: 4b0a ldr r3, [pc, #40] ; (800034c ) 8000324: 2200 movs r2, #0 8000326: 76da strb r2, [r3, #27] hcan.Init.ReceiveFifoLocked = DISABLE; 8000328: 4b08 ldr r3, [pc, #32] ; (800034c ) 800032a: 2200 movs r2, #0 800032c: 771a strb r2, [r3, #28] hcan.Init.TransmitFifoPriority = DISABLE; 800032e: 4b07 ldr r3, [pc, #28] ; (800034c ) 8000330: 2200 movs r2, #0 8000332: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan) != HAL_OK) 8000334: 4b05 ldr r3, [pc, #20] ; (800034c ) 8000336: 0018 movs r0, r3 8000338: f000 fa08 bl 800074c 800033c: 1e03 subs r3, r0, #0 800033e: d001 beq.n 8000344 { Error_Handler(); 8000340: f000 f87c bl 800043c } /* USER CODE BEGIN CAN_Init 2 */ /* USER CODE END CAN_Init 2 */ } 8000344: 46c0 nop ; (mov r8, r8) 8000346: 46bd mov sp, r7 8000348: bd80 pop {r7, pc} 800034a: 46c0 nop ; (mov r8, r8) 800034c: 20000028 .word 0x20000028 8000350: 40006400 .word 0x40006400 08000354 : * @brief I2C1 Initialization Function * @param None * @retval None */ static void MX_I2C1_Init(void) { 8000354: b580 push {r7, lr} 8000356: af00 add r7, sp, #0 /* USER CODE END I2C1_Init 0 */ /* USER CODE BEGIN I2C1_Init 1 */ /* USER CODE END I2C1_Init 1 */ hi2c1.Instance = I2C1; 8000358: 4b1b ldr r3, [pc, #108] ; (80003c8 ) 800035a: 4a1c ldr r2, [pc, #112] ; (80003cc ) 800035c: 601a str r2, [r3, #0] hi2c1.Init.Timing = 0x2000090E; 800035e: 4b1a ldr r3, [pc, #104] ; (80003c8 ) 8000360: 4a1b ldr r2, [pc, #108] ; (80003d0 ) 8000362: 605a str r2, [r3, #4] hi2c1.Init.OwnAddress1 = 0; 8000364: 4b18 ldr r3, [pc, #96] ; (80003c8 ) 8000366: 2200 movs r2, #0 8000368: 609a str r2, [r3, #8] hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 800036a: 4b17 ldr r3, [pc, #92] ; (80003c8 ) 800036c: 2201 movs r2, #1 800036e: 60da str r2, [r3, #12] hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8000370: 4b15 ldr r3, [pc, #84] ; (80003c8 ) 8000372: 2200 movs r2, #0 8000374: 611a str r2, [r3, #16] hi2c1.Init.OwnAddress2 = 0; 8000376: 4b14 ldr r3, [pc, #80] ; (80003c8 ) 8000378: 2200 movs r2, #0 800037a: 615a str r2, [r3, #20] hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; 800037c: 4b12 ldr r3, [pc, #72] ; (80003c8 ) 800037e: 2200 movs r2, #0 8000380: 619a str r2, [r3, #24] hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 8000382: 4b11 ldr r3, [pc, #68] ; (80003c8 ) 8000384: 2200 movs r2, #0 8000386: 61da str r2, [r3, #28] hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 8000388: 4b0f ldr r3, [pc, #60] ; (80003c8 ) 800038a: 2200 movs r2, #0 800038c: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c1) != HAL_OK) 800038e: 4b0e ldr r3, [pc, #56] ; (80003c8 ) 8000390: 0018 movs r0, r3 8000392: f000 fcf5 bl 8000d80 8000396: 1e03 subs r3, r0, #0 8000398: d001 beq.n 800039e { Error_Handler(); 800039a: f000 f84f bl 800043c } /** Configure Analogue filter */ if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) 800039e: 4b0a ldr r3, [pc, #40] ; (80003c8 ) 80003a0: 2100 movs r1, #0 80003a2: 0018 movs r0, r3 80003a4: f000 fd82 bl 8000eac 80003a8: 1e03 subs r3, r0, #0 80003aa: d001 beq.n 80003b0 { Error_Handler(); 80003ac: f000 f846 bl 800043c } /** Configure Digital filter */ if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) 80003b0: 4b05 ldr r3, [pc, #20] ; (80003c8 ) 80003b2: 2100 movs r1, #0 80003b4: 0018 movs r0, r3 80003b6: f000 fdc5 bl 8000f44 80003ba: 1e03 subs r3, r0, #0 80003bc: d001 beq.n 80003c2 { Error_Handler(); 80003be: f000 f83d bl 800043c } /* USER CODE BEGIN I2C1_Init 2 */ /* USER CODE END I2C1_Init 2 */ } 80003c2: 46c0 nop ; (mov r8, r8) 80003c4: 46bd mov sp, r7 80003c6: bd80 pop {r7, pc} 80003c8: 20000050 .word 0x20000050 80003cc: 40005400 .word 0x40005400 80003d0: 2000090e .word 0x2000090e 080003d4 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 80003d4: b580 push {r7, lr} 80003d6: b084 sub sp, #16 80003d8: af00 add r7, sp, #0 /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); 80003da: 4b17 ldr r3, [pc, #92] ; (8000438 ) 80003dc: 695a ldr r2, [r3, #20] 80003de: 4b16 ldr r3, [pc, #88] ; (8000438 ) 80003e0: 2180 movs r1, #128 ; 0x80 80003e2: 03c9 lsls r1, r1, #15 80003e4: 430a orrs r2, r1 80003e6: 615a str r2, [r3, #20] 80003e8: 4b13 ldr r3, [pc, #76] ; (8000438 ) 80003ea: 695a ldr r2, [r3, #20] 80003ec: 2380 movs r3, #128 ; 0x80 80003ee: 03db lsls r3, r3, #15 80003f0: 4013 ands r3, r2 80003f2: 60fb str r3, [r7, #12] 80003f4: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 80003f6: 4b10 ldr r3, [pc, #64] ; (8000438 ) 80003f8: 695a ldr r2, [r3, #20] 80003fa: 4b0f ldr r3, [pc, #60] ; (8000438 ) 80003fc: 2180 movs r1, #128 ; 0x80 80003fe: 0289 lsls r1, r1, #10 8000400: 430a orrs r2, r1 8000402: 615a str r2, [r3, #20] 8000404: 4b0c ldr r3, [pc, #48] ; (8000438 ) 8000406: 695a ldr r2, [r3, #20] 8000408: 2380 movs r3, #128 ; 0x80 800040a: 029b lsls r3, r3, #10 800040c: 4013 ands r3, r2 800040e: 60bb str r3, [r7, #8] 8000410: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000412: 4b09 ldr r3, [pc, #36] ; (8000438 ) 8000414: 695a ldr r2, [r3, #20] 8000416: 4b08 ldr r3, [pc, #32] ; (8000438 ) 8000418: 2180 movs r1, #128 ; 0x80 800041a: 02c9 lsls r1, r1, #11 800041c: 430a orrs r2, r1 800041e: 615a str r2, [r3, #20] 8000420: 4b05 ldr r3, [pc, #20] ; (8000438 ) 8000422: 695a ldr r2, [r3, #20] 8000424: 2380 movs r3, #128 ; 0x80 8000426: 02db lsls r3, r3, #11 8000428: 4013 ands r3, r2 800042a: 607b str r3, [r7, #4] 800042c: 687b ldr r3, [r7, #4] } 800042e: 46c0 nop ; (mov r8, r8) 8000430: 46bd mov sp, r7 8000432: b004 add sp, #16 8000434: bd80 pop {r7, pc} 8000436: 46c0 nop ; (mov r8, r8) 8000438: 40021000 .word 0x40021000 0800043c : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 800043c: b580 push {r7, lr} 800043e: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000440: b672 cpsid i } 8000442: 46c0 nop ; (mov r8, r8) /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000444: e7fe b.n 8000444 ... 08000448 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000448: b580 push {r7, lr} 800044a: b082 sub sp, #8 800044c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800044e: 4b0f ldr r3, [pc, #60] ; (800048c ) 8000450: 699a ldr r2, [r3, #24] 8000452: 4b0e ldr r3, [pc, #56] ; (800048c ) 8000454: 2101 movs r1, #1 8000456: 430a orrs r2, r1 8000458: 619a str r2, [r3, #24] 800045a: 4b0c ldr r3, [pc, #48] ; (800048c ) 800045c: 699b ldr r3, [r3, #24] 800045e: 2201 movs r2, #1 8000460: 4013 ands r3, r2 8000462: 607b str r3, [r7, #4] 8000464: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8000466: 4b09 ldr r3, [pc, #36] ; (800048c ) 8000468: 69da ldr r2, [r3, #28] 800046a: 4b08 ldr r3, [pc, #32] ; (800048c ) 800046c: 2180 movs r1, #128 ; 0x80 800046e: 0549 lsls r1, r1, #21 8000470: 430a orrs r2, r1 8000472: 61da str r2, [r3, #28] 8000474: 4b05 ldr r3, [pc, #20] ; (800048c ) 8000476: 69da ldr r2, [r3, #28] 8000478: 2380 movs r3, #128 ; 0x80 800047a: 055b lsls r3, r3, #21 800047c: 4013 ands r3, r2 800047e: 603b str r3, [r7, #0] 8000480: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000482: 46c0 nop ; (mov r8, r8) 8000484: 46bd mov sp, r7 8000486: b002 add sp, #8 8000488: bd80 pop {r7, pc} 800048a: 46c0 nop ; (mov r8, r8) 800048c: 40021000 .word 0x40021000 08000490 : * This function configures the hardware resources used in this example * @param hcan: CAN handle pointer * @retval None */ void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) { 8000490: b590 push {r4, r7, lr} 8000492: b08b sub sp, #44 ; 0x2c 8000494: af00 add r7, sp, #0 8000496: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000498: 2414 movs r4, #20 800049a: 193b adds r3, r7, r4 800049c: 0018 movs r0, r3 800049e: 2314 movs r3, #20 80004a0: 001a movs r2, r3 80004a2: 2100 movs r1, #0 80004a4: f001 fb7e bl 8001ba4 if(hcan->Instance==CAN) 80004a8: 687b ldr r3, [r7, #4] 80004aa: 681b ldr r3, [r3, #0] 80004ac: 4a1d ldr r2, [pc, #116] ; (8000524 ) 80004ae: 4293 cmp r3, r2 80004b0: d133 bne.n 800051a { /* USER CODE BEGIN CAN_MspInit 0 */ /* USER CODE END CAN_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CAN1_CLK_ENABLE(); 80004b2: 4b1d ldr r3, [pc, #116] ; (8000528 ) 80004b4: 69da ldr r2, [r3, #28] 80004b6: 4b1c ldr r3, [pc, #112] ; (8000528 ) 80004b8: 2180 movs r1, #128 ; 0x80 80004ba: 0489 lsls r1, r1, #18 80004bc: 430a orrs r2, r1 80004be: 61da str r2, [r3, #28] 80004c0: 4b19 ldr r3, [pc, #100] ; (8000528 ) 80004c2: 69da ldr r2, [r3, #28] 80004c4: 2380 movs r3, #128 ; 0x80 80004c6: 049b lsls r3, r3, #18 80004c8: 4013 ands r3, r2 80004ca: 613b str r3, [r7, #16] 80004cc: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 80004ce: 4b16 ldr r3, [pc, #88] ; (8000528 ) 80004d0: 695a ldr r2, [r3, #20] 80004d2: 4b15 ldr r3, [pc, #84] ; (8000528 ) 80004d4: 2180 movs r1, #128 ; 0x80 80004d6: 0289 lsls r1, r1, #10 80004d8: 430a orrs r2, r1 80004da: 615a str r2, [r3, #20] 80004dc: 4b12 ldr r3, [pc, #72] ; (8000528 ) 80004de: 695a ldr r2, [r3, #20] 80004e0: 2380 movs r3, #128 ; 0x80 80004e2: 029b lsls r3, r3, #10 80004e4: 4013 ands r3, r2 80004e6: 60fb str r3, [r7, #12] 80004e8: 68fb ldr r3, [r7, #12] /**CAN GPIO Configuration PA11 ------> CAN_RX PA12 ------> CAN_TX */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; 80004ea: 193b adds r3, r7, r4 80004ec: 22c0 movs r2, #192 ; 0xc0 80004ee: 0152 lsls r2, r2, #5 80004f0: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80004f2: 0021 movs r1, r4 80004f4: 187b adds r3, r7, r1 80004f6: 2202 movs r2, #2 80004f8: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 80004fa: 187b adds r3, r7, r1 80004fc: 2200 movs r2, #0 80004fe: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000500: 187b adds r3, r7, r1 8000502: 2203 movs r2, #3 8000504: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF4_CAN; 8000506: 187b adds r3, r7, r1 8000508: 2204 movs r2, #4 800050a: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800050c: 187a adds r2, r7, r1 800050e: 2390 movs r3, #144 ; 0x90 8000510: 05db lsls r3, r3, #23 8000512: 0011 movs r1, r2 8000514: 0018 movs r0, r3 8000516: f000 facb bl 8000ab0 /* USER CODE BEGIN CAN_MspInit 1 */ /* USER CODE END CAN_MspInit 1 */ } } 800051a: 46c0 nop ; (mov r8, r8) 800051c: 46bd mov sp, r7 800051e: b00b add sp, #44 ; 0x2c 8000520: bd90 pop {r4, r7, pc} 8000522: 46c0 nop ; (mov r8, r8) 8000524: 40006400 .word 0x40006400 8000528: 40021000 .word 0x40021000 0800052c : * This function configures the hardware resources used in this example * @param hi2c: I2C handle pointer * @retval None */ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) { 800052c: b590 push {r4, r7, lr} 800052e: b08b sub sp, #44 ; 0x2c 8000530: af00 add r7, sp, #0 8000532: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000534: 2414 movs r4, #20 8000536: 193b adds r3, r7, r4 8000538: 0018 movs r0, r3 800053a: 2314 movs r3, #20 800053c: 001a movs r2, r3 800053e: 2100 movs r1, #0 8000540: f001 fb30 bl 8001ba4 if(hi2c->Instance==I2C1) 8000544: 687b ldr r3, [r7, #4] 8000546: 681b ldr r3, [r3, #0] 8000548: 4a1c ldr r2, [pc, #112] ; (80005bc ) 800054a: 4293 cmp r3, r2 800054c: d132 bne.n 80005b4 { /* USER CODE BEGIN I2C1_MspInit 0 */ /* USER CODE END I2C1_MspInit 0 */ __HAL_RCC_GPIOB_CLK_ENABLE(); 800054e: 4b1c ldr r3, [pc, #112] ; (80005c0 ) 8000550: 695a ldr r2, [r3, #20] 8000552: 4b1b ldr r3, [pc, #108] ; (80005c0 ) 8000554: 2180 movs r1, #128 ; 0x80 8000556: 02c9 lsls r1, r1, #11 8000558: 430a orrs r2, r1 800055a: 615a str r2, [r3, #20] 800055c: 4b18 ldr r3, [pc, #96] ; (80005c0 ) 800055e: 695a ldr r2, [r3, #20] 8000560: 2380 movs r3, #128 ; 0x80 8000562: 02db lsls r3, r3, #11 8000564: 4013 ands r3, r2 8000566: 613b str r3, [r7, #16] 8000568: 693b ldr r3, [r7, #16] /**I2C1 GPIO Configuration PB7 ------> I2C1_SDA PB8 ------> I2C1_SCL */ GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8; 800056a: 193b adds r3, r7, r4 800056c: 22c0 movs r2, #192 ; 0xc0 800056e: 0052 lsls r2, r2, #1 8000570: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8000572: 0021 movs r1, r4 8000574: 187b adds r3, r7, r1 8000576: 2212 movs r2, #18 8000578: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 800057a: 187b adds r3, r7, r1 800057c: 2200 movs r2, #0 800057e: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000580: 187b adds r3, r7, r1 8000582: 2203 movs r2, #3 8000584: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF1_I2C1; 8000586: 187b adds r3, r7, r1 8000588: 2201 movs r2, #1 800058a: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800058c: 187b adds r3, r7, r1 800058e: 4a0d ldr r2, [pc, #52] ; (80005c4 ) 8000590: 0019 movs r1, r3 8000592: 0010 movs r0, r2 8000594: f000 fa8c bl 8000ab0 /* Peripheral clock enable */ __HAL_RCC_I2C1_CLK_ENABLE(); 8000598: 4b09 ldr r3, [pc, #36] ; (80005c0 ) 800059a: 69da ldr r2, [r3, #28] 800059c: 4b08 ldr r3, [pc, #32] ; (80005c0 ) 800059e: 2180 movs r1, #128 ; 0x80 80005a0: 0389 lsls r1, r1, #14 80005a2: 430a orrs r2, r1 80005a4: 61da str r2, [r3, #28] 80005a6: 4b06 ldr r3, [pc, #24] ; (80005c0 ) 80005a8: 69da ldr r2, [r3, #28] 80005aa: 2380 movs r3, #128 ; 0x80 80005ac: 039b lsls r3, r3, #14 80005ae: 4013 ands r3, r2 80005b0: 60fb str r3, [r7, #12] 80005b2: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN I2C1_MspInit 1 */ /* USER CODE END I2C1_MspInit 1 */ } } 80005b4: 46c0 nop ; (mov r8, r8) 80005b6: 46bd mov sp, r7 80005b8: b00b add sp, #44 ; 0x2c 80005ba: bd90 pop {r4, r7, pc} 80005bc: 40005400 .word 0x40005400 80005c0: 40021000 .word 0x40021000 80005c4: 48000400 .word 0x48000400 080005c8 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80005c8: b580 push {r7, lr} 80005ca: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80005cc: e7fe b.n 80005cc 080005ce : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80005ce: b580 push {r7, lr} 80005d0: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80005d2: e7fe b.n 80005d2 080005d4 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80005d4: b580 push {r7, lr} 80005d6: af00 add r7, sp, #0 /* USER CODE END SVC_IRQn 0 */ /* USER CODE BEGIN SVC_IRQn 1 */ /* USER CODE END SVC_IRQn 1 */ } 80005d8: 46c0 nop ; (mov r8, r8) 80005da: 46bd mov sp, r7 80005dc: bd80 pop {r7, pc} 080005de : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 80005de: b580 push {r7, lr} 80005e0: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 80005e2: 46c0 nop ; (mov r8, r8) 80005e4: 46bd mov sp, r7 80005e6: bd80 pop {r7, pc} 080005e8 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 80005e8: b580 push {r7, lr} 80005ea: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 80005ec: f000 f892 bl 8000714 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 80005f0: 46c0 nop ; (mov r8, r8) 80005f2: 46bd mov sp, r7 80005f4: bd80 pop {r7, pc} 080005f6 : * @brief Setup the microcontroller system * @param None * @retval None */ void SystemInit(void) { 80005f6: b580 push {r7, lr} 80005f8: af00 add r7, sp, #0 before branch to main program. This call is made inside the "startup_stm32f0xx.s" file. User can setups the default system clock (System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings). */ } 80005fa: 46c0 nop ; (mov r8, r8) 80005fc: 46bd mov sp, r7 80005fe: bd80 pop {r7, pc} 08000600 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 8000600: 4813 ldr r0, [pc, #76] ; (8000650 ) mov sp, r0 /* set stack pointer */ 8000602: 4685 mov sp, r0 /* Call the clock system initialization function.*/ bl SystemInit 8000604: f7ff fff7 bl 80005f6 /*Check if boot space corresponds to test memory*/ LDR R0,=0x00000004 8000608: 4812 ldr r0, [pc, #72] ; (8000654 ) LDR R1, [R0] 800060a: 6801 ldr r1, [r0, #0] LSRS R1, R1, #24 800060c: 0e09 lsrs r1, r1, #24 LDR R2,=0x1F 800060e: 4a12 ldr r2, [pc, #72] ; (8000658 ) CMP R1, R2 8000610: 4291 cmp r1, r2 BNE ApplicationStart 8000612: d105 bne.n 8000620 /*SYSCFG clock enable*/ LDR R0,=0x40021018 8000614: 4811 ldr r0, [pc, #68] ; (800065c ) LDR R1,=0x00000001 8000616: 4912 ldr r1, [pc, #72] ; (8000660 ) STR R1, [R0] 8000618: 6001 str r1, [r0, #0] /*Set CFGR1 register with flash memory remap at address 0*/ LDR R0,=0x40010000 800061a: 4812 ldr r0, [pc, #72] ; (8000664 ) LDR R1,=0x00000000 800061c: 4912 ldr r1, [pc, #72] ; (8000668 ) STR R1, [R0] 800061e: 6001 str r1, [r0, #0] 08000620 : ApplicationStart: /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8000620: 4812 ldr r0, [pc, #72] ; (800066c ) ldr r1, =_edata 8000622: 4913 ldr r1, [pc, #76] ; (8000670 ) ldr r2, =_sidata 8000624: 4a13 ldr r2, [pc, #76] ; (8000674 ) movs r3, #0 8000626: 2300 movs r3, #0 b LoopCopyDataInit 8000628: e002 b.n 8000630 0800062a : CopyDataInit: ldr r4, [r2, r3] 800062a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800062c: 50c4 str r4, [r0, r3] adds r3, r3, #4 800062e: 3304 adds r3, #4 08000630 : LoopCopyDataInit: adds r4, r0, r3 8000630: 18c4 adds r4, r0, r3 cmp r4, r1 8000632: 428c cmp r4, r1 bcc CopyDataInit 8000634: d3f9 bcc.n 800062a /* Zero fill the bss segment. */ ldr r2, =_sbss 8000636: 4a10 ldr r2, [pc, #64] ; (8000678 ) ldr r4, =_ebss 8000638: 4c10 ldr r4, [pc, #64] ; (800067c ) movs r3, #0 800063a: 2300 movs r3, #0 b LoopFillZerobss 800063c: e001 b.n 8000642 0800063e : FillZerobss: str r3, [r2] 800063e: 6013 str r3, [r2, #0] adds r2, r2, #4 8000640: 3204 adds r2, #4 08000642 : LoopFillZerobss: cmp r2, r4 8000642: 42a2 cmp r2, r4 bcc FillZerobss 8000644: d3fb bcc.n 800063e /* Call static constructors */ bl __libc_init_array 8000646: f001 fa89 bl 8001b5c <__libc_init_array> /* Call the application's entry point.*/ bl main 800064a: f7ff fde9 bl 8000220
0800064e : LoopForever: b LoopForever 800064e: e7fe b.n 800064e ldr r0, =_estack 8000650: 20001800 .word 0x20001800 LDR R0,=0x00000004 8000654: 00000004 .word 0x00000004 LDR R2,=0x1F 8000658: 0000001f .word 0x0000001f LDR R0,=0x40021018 800065c: 40021018 .word 0x40021018 LDR R1,=0x00000001 8000660: 00000001 .word 0x00000001 LDR R0,=0x40010000 8000664: 40010000 .word 0x40010000 LDR R1,=0x00000000 8000668: 00000000 .word 0x00000000 ldr r0, =_sdata 800066c: 20000000 .word 0x20000000 ldr r1, =_edata 8000670: 2000000c .word 0x2000000c ldr r2, =_sidata 8000674: 08001c04 .word 0x08001c04 ldr r2, =_sbss 8000678: 2000000c .word 0x2000000c ldr r4, =_ebss 800067c: 200000a8 .word 0x200000a8 08000680 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000680: e7fe b.n 8000680 ... 08000684 : * In the default implementation,Systick is used as source of time base. * The tick variable is incremented each 1ms in its ISR. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8000684: b580 push {r7, lr} 8000686: af00 add r7, sp, #0 /* Configure Flash prefetch */ #if (PREFETCH_ENABLE != 0) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8000688: 4b07 ldr r3, [pc, #28] ; (80006a8 ) 800068a: 681a ldr r2, [r3, #0] 800068c: 4b06 ldr r3, [pc, #24] ; (80006a8 ) 800068e: 2110 movs r1, #16 8000690: 430a orrs r2, r1 8000692: 601a str r2, [r3, #0] #endif /* PREFETCH_ENABLE */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8000694: 2003 movs r0, #3 8000696: f000 f809 bl 80006ac /* Init the low level hardware */ HAL_MspInit(); 800069a: f7ff fed5 bl 8000448 /* Return function status */ return HAL_OK; 800069e: 2300 movs r3, #0 } 80006a0: 0018 movs r0, r3 80006a2: 46bd mov sp, r7 80006a4: bd80 pop {r7, pc} 80006a6: 46c0 nop ; (mov r8, r8) 80006a8: 40022000 .word 0x40022000 080006ac : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80006ac: b590 push {r4, r7, lr} 80006ae: b083 sub sp, #12 80006b0: af00 add r7, sp, #0 80006b2: 6078 str r0, [r7, #4] /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 80006b4: 4b14 ldr r3, [pc, #80] ; (8000708 ) 80006b6: 681c ldr r4, [r3, #0] 80006b8: 4b14 ldr r3, [pc, #80] ; (800070c ) 80006ba: 781b ldrb r3, [r3, #0] 80006bc: 0019 movs r1, r3 80006be: 23fa movs r3, #250 ; 0xfa 80006c0: 0098 lsls r0, r3, #2 80006c2: f7ff fd21 bl 8000108 <__udivsi3> 80006c6: 0003 movs r3, r0 80006c8: 0019 movs r1, r3 80006ca: 0020 movs r0, r4 80006cc: f7ff fd1c bl 8000108 <__udivsi3> 80006d0: 0003 movs r3, r0 80006d2: 0018 movs r0, r3 80006d4: f000 f9df bl 8000a96 80006d8: 1e03 subs r3, r0, #0 80006da: d001 beq.n 80006e0 { return HAL_ERROR; 80006dc: 2301 movs r3, #1 80006de: e00f b.n 8000700 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80006e0: 687b ldr r3, [r7, #4] 80006e2: 2b03 cmp r3, #3 80006e4: d80b bhi.n 80006fe { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80006e6: 6879 ldr r1, [r7, #4] 80006e8: 2301 movs r3, #1 80006ea: 425b negs r3, r3 80006ec: 2200 movs r2, #0 80006ee: 0018 movs r0, r3 80006f0: f000 f9bc bl 8000a6c uwTickPrio = TickPriority; 80006f4: 4b06 ldr r3, [pc, #24] ; (8000710 ) 80006f6: 687a ldr r2, [r7, #4] 80006f8: 601a str r2, [r3, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 80006fa: 2300 movs r3, #0 80006fc: e000 b.n 8000700 return HAL_ERROR; 80006fe: 2301 movs r3, #1 } 8000700: 0018 movs r0, r3 8000702: 46bd mov sp, r7 8000704: b003 add sp, #12 8000706: bd90 pop {r4, r7, pc} 8000708: 20000000 .word 0x20000000 800070c: 20000008 .word 0x20000008 8000710: 20000004 .word 0x20000004 08000714 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8000714: b580 push {r7, lr} 8000716: af00 add r7, sp, #0 uwTick += uwTickFreq; 8000718: 4b05 ldr r3, [pc, #20] ; (8000730 ) 800071a: 781b ldrb r3, [r3, #0] 800071c: 001a movs r2, r3 800071e: 4b05 ldr r3, [pc, #20] ; (8000734 ) 8000720: 681b ldr r3, [r3, #0] 8000722: 18d2 adds r2, r2, r3 8000724: 4b03 ldr r3, [pc, #12] ; (8000734 ) 8000726: 601a str r2, [r3, #0] } 8000728: 46c0 nop ; (mov r8, r8) 800072a: 46bd mov sp, r7 800072c: bd80 pop {r7, pc} 800072e: 46c0 nop ; (mov r8, r8) 8000730: 20000008 .word 0x20000008 8000734: 200000a4 .word 0x200000a4 08000738 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8000738: b580 push {r7, lr} 800073a: af00 add r7, sp, #0 return uwTick; 800073c: 4b02 ldr r3, [pc, #8] ; (8000748 ) 800073e: 681b ldr r3, [r3, #0] } 8000740: 0018 movs r0, r3 8000742: 46bd mov sp, r7 8000744: bd80 pop {r7, pc} 8000746: 46c0 nop ; (mov r8, r8) 8000748: 200000a4 .word 0x200000a4 0800074c : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { 800074c: b580 push {r7, lr} 800074e: b084 sub sp, #16 8000750: af00 add r7, sp, #0 8000752: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) 8000754: 687b ldr r3, [r7, #4] 8000756: 2b00 cmp r3, #0 8000758: d101 bne.n 800075e { return HAL_ERROR; 800075a: 2301 movs r3, #1 800075c: e0f0 b.n 8000940 /* Init the low level hardware: CLOCK, NVIC */ hcan->MspInitCallback(hcan); } #else if (hcan->State == HAL_CAN_STATE_RESET) 800075e: 687b ldr r3, [r7, #4] 8000760: 2220 movs r2, #32 8000762: 5c9b ldrb r3, [r3, r2] 8000764: b2db uxtb r3, r3 8000766: 2b00 cmp r3, #0 8000768: d103 bne.n 8000772 { /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); 800076a: 687b ldr r3, [r7, #4] 800076c: 0018 movs r0, r3 800076e: f7ff fe8f bl 8000490 } #endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 8000772: 687b ldr r3, [r7, #4] 8000774: 681b ldr r3, [r3, #0] 8000776: 681a ldr r2, [r3, #0] 8000778: 687b ldr r3, [r7, #4] 800077a: 681b ldr r3, [r3, #0] 800077c: 2101 movs r1, #1 800077e: 430a orrs r2, r1 8000780: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8000782: f7ff ffd9 bl 8000738 8000786: 0003 movs r3, r0 8000788: 60fb str r3, [r7, #12] /* Wait initialisation acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800078a: e013 b.n 80007b4 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800078c: f7ff ffd4 bl 8000738 8000790: 0002 movs r2, r0 8000792: 68fb ldr r3, [r7, #12] 8000794: 1ad3 subs r3, r2, r3 8000796: 2b0a cmp r3, #10 8000798: d90c bls.n 80007b4 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800079a: 687b ldr r3, [r7, #4] 800079c: 6a5b ldr r3, [r3, #36] ; 0x24 800079e: 2280 movs r2, #128 ; 0x80 80007a0: 0292 lsls r2, r2, #10 80007a2: 431a orrs r2, r3 80007a4: 687b ldr r3, [r7, #4] 80007a6: 625a str r2, [r3, #36] ; 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 80007a8: 687b ldr r3, [r7, #4] 80007aa: 2220 movs r2, #32 80007ac: 2105 movs r1, #5 80007ae: 5499 strb r1, [r3, r2] return HAL_ERROR; 80007b0: 2301 movs r3, #1 80007b2: e0c5 b.n 8000940 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 80007b4: 687b ldr r3, [r7, #4] 80007b6: 681b ldr r3, [r3, #0] 80007b8: 685b ldr r3, [r3, #4] 80007ba: 2201 movs r2, #1 80007bc: 4013 ands r3, r2 80007be: d0e5 beq.n 800078c } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 80007c0: 687b ldr r3, [r7, #4] 80007c2: 681b ldr r3, [r3, #0] 80007c4: 681a ldr r2, [r3, #0] 80007c6: 687b ldr r3, [r7, #4] 80007c8: 681b ldr r3, [r3, #0] 80007ca: 2102 movs r1, #2 80007cc: 438a bics r2, r1 80007ce: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 80007d0: f7ff ffb2 bl 8000738 80007d4: 0003 movs r3, r0 80007d6: 60fb str r3, [r7, #12] /* Check Sleep mode leave acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 80007d8: e013 b.n 8000802 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 80007da: f7ff ffad bl 8000738 80007de: 0002 movs r2, r0 80007e0: 68fb ldr r3, [r7, #12] 80007e2: 1ad3 subs r3, r2, r3 80007e4: 2b0a cmp r3, #10 80007e6: d90c bls.n 8000802 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 80007e8: 687b ldr r3, [r7, #4] 80007ea: 6a5b ldr r3, [r3, #36] ; 0x24 80007ec: 2280 movs r2, #128 ; 0x80 80007ee: 0292 lsls r2, r2, #10 80007f0: 431a orrs r2, r3 80007f2: 687b ldr r3, [r7, #4] 80007f4: 625a str r2, [r3, #36] ; 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 80007f6: 687b ldr r3, [r7, #4] 80007f8: 2220 movs r2, #32 80007fa: 2105 movs r1, #5 80007fc: 5499 strb r1, [r3, r2] return HAL_ERROR; 80007fe: 2301 movs r3, #1 8000800: e09e b.n 8000940 while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 8000802: 687b ldr r3, [r7, #4] 8000804: 681b ldr r3, [r3, #0] 8000806: 685b ldr r3, [r3, #4] 8000808: 2202 movs r2, #2 800080a: 4013 ands r3, r2 800080c: d1e5 bne.n 80007da } } /* Set the time triggered communication mode */ if (hcan->Init.TimeTriggeredMode == ENABLE) 800080e: 687b ldr r3, [r7, #4] 8000810: 7e1b ldrb r3, [r3, #24] 8000812: 2b01 cmp r3, #1 8000814: d108 bne.n 8000828 { SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 8000816: 687b ldr r3, [r7, #4] 8000818: 681b ldr r3, [r3, #0] 800081a: 681a ldr r2, [r3, #0] 800081c: 687b ldr r3, [r7, #4] 800081e: 681b ldr r3, [r3, #0] 8000820: 2180 movs r1, #128 ; 0x80 8000822: 430a orrs r2, r1 8000824: 601a str r2, [r3, #0] 8000826: e007 b.n 8000838 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 8000828: 687b ldr r3, [r7, #4] 800082a: 681b ldr r3, [r3, #0] 800082c: 681a ldr r2, [r3, #0] 800082e: 687b ldr r3, [r7, #4] 8000830: 681b ldr r3, [r3, #0] 8000832: 2180 movs r1, #128 ; 0x80 8000834: 438a bics r2, r1 8000836: 601a str r2, [r3, #0] } /* Set the automatic bus-off management */ if (hcan->Init.AutoBusOff == ENABLE) 8000838: 687b ldr r3, [r7, #4] 800083a: 7e5b ldrb r3, [r3, #25] 800083c: 2b01 cmp r3, #1 800083e: d108 bne.n 8000852 { SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 8000840: 687b ldr r3, [r7, #4] 8000842: 681b ldr r3, [r3, #0] 8000844: 681a ldr r2, [r3, #0] 8000846: 687b ldr r3, [r7, #4] 8000848: 681b ldr r3, [r3, #0] 800084a: 2140 movs r1, #64 ; 0x40 800084c: 430a orrs r2, r1 800084e: 601a str r2, [r3, #0] 8000850: e007 b.n 8000862 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 8000852: 687b ldr r3, [r7, #4] 8000854: 681b ldr r3, [r3, #0] 8000856: 681a ldr r2, [r3, #0] 8000858: 687b ldr r3, [r7, #4] 800085a: 681b ldr r3, [r3, #0] 800085c: 2140 movs r1, #64 ; 0x40 800085e: 438a bics r2, r1 8000860: 601a str r2, [r3, #0] } /* Set the automatic wake-up mode */ if (hcan->Init.AutoWakeUp == ENABLE) 8000862: 687b ldr r3, [r7, #4] 8000864: 7e9b ldrb r3, [r3, #26] 8000866: 2b01 cmp r3, #1 8000868: d108 bne.n 800087c { SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800086a: 687b ldr r3, [r7, #4] 800086c: 681b ldr r3, [r3, #0] 800086e: 681a ldr r2, [r3, #0] 8000870: 687b ldr r3, [r7, #4] 8000872: 681b ldr r3, [r3, #0] 8000874: 2120 movs r1, #32 8000876: 430a orrs r2, r1 8000878: 601a str r2, [r3, #0] 800087a: e007 b.n 800088c } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800087c: 687b ldr r3, [r7, #4] 800087e: 681b ldr r3, [r3, #0] 8000880: 681a ldr r2, [r3, #0] 8000882: 687b ldr r3, [r7, #4] 8000884: 681b ldr r3, [r3, #0] 8000886: 2120 movs r1, #32 8000888: 438a bics r2, r1 800088a: 601a str r2, [r3, #0] } /* Set the automatic retransmission */ if (hcan->Init.AutoRetransmission == ENABLE) 800088c: 687b ldr r3, [r7, #4] 800088e: 7edb ldrb r3, [r3, #27] 8000890: 2b01 cmp r3, #1 8000892: d108 bne.n 80008a6 { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); 8000894: 687b ldr r3, [r7, #4] 8000896: 681b ldr r3, [r3, #0] 8000898: 681a ldr r2, [r3, #0] 800089a: 687b ldr r3, [r7, #4] 800089c: 681b ldr r3, [r3, #0] 800089e: 2110 movs r1, #16 80008a0: 438a bics r2, r1 80008a2: 601a str r2, [r3, #0] 80008a4: e007 b.n 80008b6 } else { SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); 80008a6: 687b ldr r3, [r7, #4] 80008a8: 681b ldr r3, [r3, #0] 80008aa: 681a ldr r2, [r3, #0] 80008ac: 687b ldr r3, [r7, #4] 80008ae: 681b ldr r3, [r3, #0] 80008b0: 2110 movs r1, #16 80008b2: 430a orrs r2, r1 80008b4: 601a str r2, [r3, #0] } /* Set the receive FIFO locked mode */ if (hcan->Init.ReceiveFifoLocked == ENABLE) 80008b6: 687b ldr r3, [r7, #4] 80008b8: 7f1b ldrb r3, [r3, #28] 80008ba: 2b01 cmp r3, #1 80008bc: d108 bne.n 80008d0 { SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 80008be: 687b ldr r3, [r7, #4] 80008c0: 681b ldr r3, [r3, #0] 80008c2: 681a ldr r2, [r3, #0] 80008c4: 687b ldr r3, [r7, #4] 80008c6: 681b ldr r3, [r3, #0] 80008c8: 2108 movs r1, #8 80008ca: 430a orrs r2, r1 80008cc: 601a str r2, [r3, #0] 80008ce: e007 b.n 80008e0 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 80008d0: 687b ldr r3, [r7, #4] 80008d2: 681b ldr r3, [r3, #0] 80008d4: 681a ldr r2, [r3, #0] 80008d6: 687b ldr r3, [r7, #4] 80008d8: 681b ldr r3, [r3, #0] 80008da: 2108 movs r1, #8 80008dc: 438a bics r2, r1 80008de: 601a str r2, [r3, #0] } /* Set the transmit FIFO priority */ if (hcan->Init.TransmitFifoPriority == ENABLE) 80008e0: 687b ldr r3, [r7, #4] 80008e2: 7f5b ldrb r3, [r3, #29] 80008e4: 2b01 cmp r3, #1 80008e6: d108 bne.n 80008fa { SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 80008e8: 687b ldr r3, [r7, #4] 80008ea: 681b ldr r3, [r3, #0] 80008ec: 681a ldr r2, [r3, #0] 80008ee: 687b ldr r3, [r7, #4] 80008f0: 681b ldr r3, [r3, #0] 80008f2: 2104 movs r1, #4 80008f4: 430a orrs r2, r1 80008f6: 601a str r2, [r3, #0] 80008f8: e007 b.n 800090a } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 80008fa: 687b ldr r3, [r7, #4] 80008fc: 681b ldr r3, [r3, #0] 80008fe: 681a ldr r2, [r3, #0] 8000900: 687b ldr r3, [r7, #4] 8000902: 681b ldr r3, [r3, #0] 8000904: 2104 movs r1, #4 8000906: 438a bics r2, r1 8000908: 601a str r2, [r3, #0] } /* Set the bit timing register */ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | 800090a: 687b ldr r3, [r7, #4] 800090c: 689a ldr r2, [r3, #8] 800090e: 687b ldr r3, [r7, #4] 8000910: 68db ldr r3, [r3, #12] 8000912: 431a orrs r2, r3 8000914: 687b ldr r3, [r7, #4] 8000916: 691b ldr r3, [r3, #16] 8000918: 431a orrs r2, r3 800091a: 687b ldr r3, [r7, #4] 800091c: 695b ldr r3, [r3, #20] 800091e: 431a orrs r2, r3 8000920: 0011 movs r1, r2 8000922: 687b ldr r3, [r7, #4] 8000924: 685b ldr r3, [r3, #4] 8000926: 1e5a subs r2, r3, #1 8000928: 687b ldr r3, [r7, #4] 800092a: 681b ldr r3, [r3, #0] 800092c: 430a orrs r2, r1 800092e: 61da str r2, [r3, #28] hcan->Init.TimeSeg1 | hcan->Init.TimeSeg2 | (hcan->Init.Prescaler - 1U))); /* Initialize the error code */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 8000930: 687b ldr r3, [r7, #4] 8000932: 2200 movs r2, #0 8000934: 625a str r2, [r3, #36] ; 0x24 /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; 8000936: 687b ldr r3, [r7, #4] 8000938: 2220 movs r2, #32 800093a: 2101 movs r1, #1 800093c: 5499 strb r1, [r3, r2] /* Return function status */ return HAL_OK; 800093e: 2300 movs r3, #0 } 8000940: 0018 movs r0, r3 8000942: 46bd mov sp, r7 8000944: b004 add sp, #16 8000946: bd80 pop {r7, pc} 08000948 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8000948: b590 push {r4, r7, lr} 800094a: b083 sub sp, #12 800094c: af00 add r7, sp, #0 800094e: 0002 movs r2, r0 8000950: 6039 str r1, [r7, #0] 8000952: 1dfb adds r3, r7, #7 8000954: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 8000956: 1dfb adds r3, r7, #7 8000958: 781b ldrb r3, [r3, #0] 800095a: 2b7f cmp r3, #127 ; 0x7f 800095c: d828 bhi.n 80009b0 <__NVIC_SetPriority+0x68> { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 800095e: 4a2f ldr r2, [pc, #188] ; (8000a1c <__NVIC_SetPriority+0xd4>) 8000960: 1dfb adds r3, r7, #7 8000962: 781b ldrb r3, [r3, #0] 8000964: b25b sxtb r3, r3 8000966: 089b lsrs r3, r3, #2 8000968: 33c0 adds r3, #192 ; 0xc0 800096a: 009b lsls r3, r3, #2 800096c: 589b ldr r3, [r3, r2] 800096e: 1dfa adds r2, r7, #7 8000970: 7812 ldrb r2, [r2, #0] 8000972: 0011 movs r1, r2 8000974: 2203 movs r2, #3 8000976: 400a ands r2, r1 8000978: 00d2 lsls r2, r2, #3 800097a: 21ff movs r1, #255 ; 0xff 800097c: 4091 lsls r1, r2 800097e: 000a movs r2, r1 8000980: 43d2 mvns r2, r2 8000982: 401a ands r2, r3 8000984: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 8000986: 683b ldr r3, [r7, #0] 8000988: 019b lsls r3, r3, #6 800098a: 22ff movs r2, #255 ; 0xff 800098c: 401a ands r2, r3 800098e: 1dfb adds r3, r7, #7 8000990: 781b ldrb r3, [r3, #0] 8000992: 0018 movs r0, r3 8000994: 2303 movs r3, #3 8000996: 4003 ands r3, r0 8000998: 00db lsls r3, r3, #3 800099a: 409a lsls r2, r3 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 800099c: 481f ldr r0, [pc, #124] ; (8000a1c <__NVIC_SetPriority+0xd4>) 800099e: 1dfb adds r3, r7, #7 80009a0: 781b ldrb r3, [r3, #0] 80009a2: b25b sxtb r3, r3 80009a4: 089b lsrs r3, r3, #2 80009a6: 430a orrs r2, r1 80009a8: 33c0 adds r3, #192 ; 0xc0 80009aa: 009b lsls r3, r3, #2 80009ac: 501a str r2, [r3, r0] else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } 80009ae: e031 b.n 8000a14 <__NVIC_SetPriority+0xcc> SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 80009b0: 4a1b ldr r2, [pc, #108] ; (8000a20 <__NVIC_SetPriority+0xd8>) 80009b2: 1dfb adds r3, r7, #7 80009b4: 781b ldrb r3, [r3, #0] 80009b6: 0019 movs r1, r3 80009b8: 230f movs r3, #15 80009ba: 400b ands r3, r1 80009bc: 3b08 subs r3, #8 80009be: 089b lsrs r3, r3, #2 80009c0: 3306 adds r3, #6 80009c2: 009b lsls r3, r3, #2 80009c4: 18d3 adds r3, r2, r3 80009c6: 3304 adds r3, #4 80009c8: 681b ldr r3, [r3, #0] 80009ca: 1dfa adds r2, r7, #7 80009cc: 7812 ldrb r2, [r2, #0] 80009ce: 0011 movs r1, r2 80009d0: 2203 movs r2, #3 80009d2: 400a ands r2, r1 80009d4: 00d2 lsls r2, r2, #3 80009d6: 21ff movs r1, #255 ; 0xff 80009d8: 4091 lsls r1, r2 80009da: 000a movs r2, r1 80009dc: 43d2 mvns r2, r2 80009de: 401a ands r2, r3 80009e0: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 80009e2: 683b ldr r3, [r7, #0] 80009e4: 019b lsls r3, r3, #6 80009e6: 22ff movs r2, #255 ; 0xff 80009e8: 401a ands r2, r3 80009ea: 1dfb adds r3, r7, #7 80009ec: 781b ldrb r3, [r3, #0] 80009ee: 0018 movs r0, r3 80009f0: 2303 movs r3, #3 80009f2: 4003 ands r3, r0 80009f4: 00db lsls r3, r3, #3 80009f6: 409a lsls r2, r3 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 80009f8: 4809 ldr r0, [pc, #36] ; (8000a20 <__NVIC_SetPriority+0xd8>) 80009fa: 1dfb adds r3, r7, #7 80009fc: 781b ldrb r3, [r3, #0] 80009fe: 001c movs r4, r3 8000a00: 230f movs r3, #15 8000a02: 4023 ands r3, r4 8000a04: 3b08 subs r3, #8 8000a06: 089b lsrs r3, r3, #2 8000a08: 430a orrs r2, r1 8000a0a: 3306 adds r3, #6 8000a0c: 009b lsls r3, r3, #2 8000a0e: 18c3 adds r3, r0, r3 8000a10: 3304 adds r3, #4 8000a12: 601a str r2, [r3, #0] } 8000a14: 46c0 nop ; (mov r8, r8) 8000a16: 46bd mov sp, r7 8000a18: b003 add sp, #12 8000a1a: bd90 pop {r4, r7, pc} 8000a1c: e000e100 .word 0xe000e100 8000a20: e000ed00 .word 0xe000ed00 08000a24 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8000a24: b580 push {r7, lr} 8000a26: b082 sub sp, #8 8000a28: af00 add r7, sp, #0 8000a2a: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8000a2c: 687b ldr r3, [r7, #4] 8000a2e: 1e5a subs r2, r3, #1 8000a30: 2380 movs r3, #128 ; 0x80 8000a32: 045b lsls r3, r3, #17 8000a34: 429a cmp r2, r3 8000a36: d301 bcc.n 8000a3c { return (1UL); /* Reload value impossible */ 8000a38: 2301 movs r3, #1 8000a3a: e010 b.n 8000a5e } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8000a3c: 4b0a ldr r3, [pc, #40] ; (8000a68 ) 8000a3e: 687a ldr r2, [r7, #4] 8000a40: 3a01 subs r2, #1 8000a42: 605a str r2, [r3, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8000a44: 2301 movs r3, #1 8000a46: 425b negs r3, r3 8000a48: 2103 movs r1, #3 8000a4a: 0018 movs r0, r3 8000a4c: f7ff ff7c bl 8000948 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8000a50: 4b05 ldr r3, [pc, #20] ; (8000a68 ) 8000a52: 2200 movs r2, #0 8000a54: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8000a56: 4b04 ldr r3, [pc, #16] ; (8000a68 ) 8000a58: 2207 movs r2, #7 8000a5a: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8000a5c: 2300 movs r3, #0 } 8000a5e: 0018 movs r0, r3 8000a60: 46bd mov sp, r7 8000a62: b002 add sp, #8 8000a64: bd80 pop {r7, pc} 8000a66: 46c0 nop ; (mov r8, r8) 8000a68: e000e010 .word 0xe000e010 08000a6c : * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because * no subpriority supported in Cortex M0 based products. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8000a6c: b580 push {r7, lr} 8000a6e: b084 sub sp, #16 8000a70: af00 add r7, sp, #0 8000a72: 60b9 str r1, [r7, #8] 8000a74: 607a str r2, [r7, #4] 8000a76: 210f movs r1, #15 8000a78: 187b adds r3, r7, r1 8000a7a: 1c02 adds r2, r0, #0 8000a7c: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); NVIC_SetPriority(IRQn,PreemptPriority); 8000a7e: 68ba ldr r2, [r7, #8] 8000a80: 187b adds r3, r7, r1 8000a82: 781b ldrb r3, [r3, #0] 8000a84: b25b sxtb r3, r3 8000a86: 0011 movs r1, r2 8000a88: 0018 movs r0, r3 8000a8a: f7ff ff5d bl 8000948 <__NVIC_SetPriority> } 8000a8e: 46c0 nop ; (mov r8, r8) 8000a90: 46bd mov sp, r7 8000a92: b004 add sp, #16 8000a94: bd80 pop {r7, pc} 08000a96 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8000a96: b580 push {r7, lr} 8000a98: b082 sub sp, #8 8000a9a: af00 add r7, sp, #0 8000a9c: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8000a9e: 687b ldr r3, [r7, #4] 8000aa0: 0018 movs r0, r3 8000aa2: f7ff ffbf bl 8000a24 8000aa6: 0003 movs r3, r0 } 8000aa8: 0018 movs r0, r3 8000aaa: 46bd mov sp, r7 8000aac: b002 add sp, #8 8000aae: bd80 pop {r7, pc} 08000ab0 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8000ab0: b580 push {r7, lr} 8000ab2: b086 sub sp, #24 8000ab4: af00 add r7, sp, #0 8000ab6: 6078 str r0, [r7, #4] 8000ab8: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8000aba: 2300 movs r3, #0 8000abc: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8000abe: e149 b.n 8000d54 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); 8000ac0: 683b ldr r3, [r7, #0] 8000ac2: 681b ldr r3, [r3, #0] 8000ac4: 2101 movs r1, #1 8000ac6: 697a ldr r2, [r7, #20] 8000ac8: 4091 lsls r1, r2 8000aca: 000a movs r2, r1 8000acc: 4013 ands r3, r2 8000ace: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 8000ad0: 68fb ldr r3, [r7, #12] 8000ad2: 2b00 cmp r3, #0 8000ad4: d100 bne.n 8000ad8 8000ad6: e13a b.n 8000d4e { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 8000ad8: 683b ldr r3, [r7, #0] 8000ada: 685b ldr r3, [r3, #4] 8000adc: 2203 movs r2, #3 8000ade: 4013 ands r3, r2 8000ae0: 2b01 cmp r3, #1 8000ae2: d005 beq.n 8000af0 ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8000ae4: 683b ldr r3, [r7, #0] 8000ae6: 685b ldr r3, [r3, #4] 8000ae8: 2203 movs r2, #3 8000aea: 4013 ands r3, r2 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 8000aec: 2b02 cmp r3, #2 8000aee: d130 bne.n 8000b52 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8000af0: 687b ldr r3, [r7, #4] 8000af2: 689b ldr r3, [r3, #8] 8000af4: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); 8000af6: 697b ldr r3, [r7, #20] 8000af8: 005b lsls r3, r3, #1 8000afa: 2203 movs r2, #3 8000afc: 409a lsls r2, r3 8000afe: 0013 movs r3, r2 8000b00: 43da mvns r2, r3 8000b02: 693b ldr r3, [r7, #16] 8000b04: 4013 ands r3, r2 8000b06: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); 8000b08: 683b ldr r3, [r7, #0] 8000b0a: 68da ldr r2, [r3, #12] 8000b0c: 697b ldr r3, [r7, #20] 8000b0e: 005b lsls r3, r3, #1 8000b10: 409a lsls r2, r3 8000b12: 0013 movs r3, r2 8000b14: 693a ldr r2, [r7, #16] 8000b16: 4313 orrs r3, r2 8000b18: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 8000b1a: 687b ldr r3, [r7, #4] 8000b1c: 693a ldr r2, [r7, #16] 8000b1e: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8000b20: 687b ldr r3, [r7, #4] 8000b22: 685b ldr r3, [r3, #4] 8000b24: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 8000b26: 2201 movs r2, #1 8000b28: 697b ldr r3, [r7, #20] 8000b2a: 409a lsls r2, r3 8000b2c: 0013 movs r3, r2 8000b2e: 43da mvns r2, r3 8000b30: 693b ldr r3, [r7, #16] 8000b32: 4013 ands r3, r2 8000b34: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8000b36: 683b ldr r3, [r7, #0] 8000b38: 685b ldr r3, [r3, #4] 8000b3a: 091b lsrs r3, r3, #4 8000b3c: 2201 movs r2, #1 8000b3e: 401a ands r2, r3 8000b40: 697b ldr r3, [r7, #20] 8000b42: 409a lsls r2, r3 8000b44: 0013 movs r3, r2 8000b46: 693a ldr r2, [r7, #16] 8000b48: 4313 orrs r3, r2 8000b4a: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 8000b4c: 687b ldr r3, [r7, #4] 8000b4e: 693a ldr r2, [r7, #16] 8000b50: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8000b52: 683b ldr r3, [r7, #0] 8000b54: 685b ldr r3, [r3, #4] 8000b56: 2203 movs r2, #3 8000b58: 4013 ands r3, r2 8000b5a: 2b03 cmp r3, #3 8000b5c: d017 beq.n 8000b8e { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8000b5e: 687b ldr r3, [r7, #4] 8000b60: 68db ldr r3, [r3, #12] 8000b62: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); 8000b64: 697b ldr r3, [r7, #20] 8000b66: 005b lsls r3, r3, #1 8000b68: 2203 movs r2, #3 8000b6a: 409a lsls r2, r3 8000b6c: 0013 movs r3, r2 8000b6e: 43da mvns r2, r3 8000b70: 693b ldr r3, [r7, #16] 8000b72: 4013 ands r3, r2 8000b74: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2u)); 8000b76: 683b ldr r3, [r7, #0] 8000b78: 689a ldr r2, [r3, #8] 8000b7a: 697b ldr r3, [r7, #20] 8000b7c: 005b lsls r3, r3, #1 8000b7e: 409a lsls r2, r3 8000b80: 0013 movs r3, r2 8000b82: 693a ldr r2, [r7, #16] 8000b84: 4313 orrs r3, r2 8000b86: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 8000b88: 687b ldr r3, [r7, #4] 8000b8a: 693a ldr r2, [r7, #16] 8000b8c: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8000b8e: 683b ldr r3, [r7, #0] 8000b90: 685b ldr r3, [r3, #4] 8000b92: 2203 movs r2, #3 8000b94: 4013 ands r3, r2 8000b96: 2b02 cmp r3, #2 8000b98: d123 bne.n 8000be2 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; 8000b9a: 697b ldr r3, [r7, #20] 8000b9c: 08da lsrs r2, r3, #3 8000b9e: 687b ldr r3, [r7, #4] 8000ba0: 3208 adds r2, #8 8000ba2: 0092 lsls r2, r2, #2 8000ba4: 58d3 ldr r3, [r2, r3] 8000ba6: 613b str r3, [r7, #16] temp &= ~(0xFu << ((position & 0x07u) * 4u)); 8000ba8: 697b ldr r3, [r7, #20] 8000baa: 2207 movs r2, #7 8000bac: 4013 ands r3, r2 8000bae: 009b lsls r3, r3, #2 8000bb0: 220f movs r2, #15 8000bb2: 409a lsls r2, r3 8000bb4: 0013 movs r3, r2 8000bb6: 43da mvns r2, r3 8000bb8: 693b ldr r3, [r7, #16] 8000bba: 4013 ands r3, r2 8000bbc: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); 8000bbe: 683b ldr r3, [r7, #0] 8000bc0: 691a ldr r2, [r3, #16] 8000bc2: 697b ldr r3, [r7, #20] 8000bc4: 2107 movs r1, #7 8000bc6: 400b ands r3, r1 8000bc8: 009b lsls r3, r3, #2 8000bca: 409a lsls r2, r3 8000bcc: 0013 movs r3, r2 8000bce: 693a ldr r2, [r7, #16] 8000bd0: 4313 orrs r3, r2 8000bd2: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; 8000bd4: 697b ldr r3, [r7, #20] 8000bd6: 08da lsrs r2, r3, #3 8000bd8: 687b ldr r3, [r7, #4] 8000bda: 3208 adds r2, #8 8000bdc: 0092 lsls r2, r2, #2 8000bde: 6939 ldr r1, [r7, #16] 8000be0: 50d1 str r1, [r2, r3] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8000be2: 687b ldr r3, [r7, #4] 8000be4: 681b ldr r3, [r3, #0] 8000be6: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); 8000be8: 697b ldr r3, [r7, #20] 8000bea: 005b lsls r3, r3, #1 8000bec: 2203 movs r2, #3 8000bee: 409a lsls r2, r3 8000bf0: 0013 movs r3, r2 8000bf2: 43da mvns r2, r3 8000bf4: 693b ldr r3, [r7, #16] 8000bf6: 4013 ands r3, r2 8000bf8: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 8000bfa: 683b ldr r3, [r7, #0] 8000bfc: 685b ldr r3, [r3, #4] 8000bfe: 2203 movs r2, #3 8000c00: 401a ands r2, r3 8000c02: 697b ldr r3, [r7, #20] 8000c04: 005b lsls r3, r3, #1 8000c06: 409a lsls r2, r3 8000c08: 0013 movs r3, r2 8000c0a: 693a ldr r2, [r7, #16] 8000c0c: 4313 orrs r3, r2 8000c0e: 613b str r3, [r7, #16] GPIOx->MODER = temp; 8000c10: 687b ldr r3, [r7, #4] 8000c12: 693a ldr r2, [r7, #16] 8000c14: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 8000c16: 683b ldr r3, [r7, #0] 8000c18: 685a ldr r2, [r3, #4] 8000c1a: 23c0 movs r3, #192 ; 0xc0 8000c1c: 029b lsls r3, r3, #10 8000c1e: 4013 ands r3, r2 8000c20: d100 bne.n 8000c24 8000c22: e094 b.n 8000d4e { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000c24: 4b51 ldr r3, [pc, #324] ; (8000d6c ) 8000c26: 699a ldr r2, [r3, #24] 8000c28: 4b50 ldr r3, [pc, #320] ; (8000d6c ) 8000c2a: 2101 movs r1, #1 8000c2c: 430a orrs r2, r1 8000c2e: 619a str r2, [r3, #24] 8000c30: 4b4e ldr r3, [pc, #312] ; (8000d6c ) 8000c32: 699b ldr r3, [r3, #24] 8000c34: 2201 movs r2, #1 8000c36: 4013 ands r3, r2 8000c38: 60bb str r3, [r7, #8] 8000c3a: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2u]; 8000c3c: 4a4c ldr r2, [pc, #304] ; (8000d70 ) 8000c3e: 697b ldr r3, [r7, #20] 8000c40: 089b lsrs r3, r3, #2 8000c42: 3302 adds r3, #2 8000c44: 009b lsls r3, r3, #2 8000c46: 589b ldr r3, [r3, r2] 8000c48: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (4u * (position & 0x03u))); 8000c4a: 697b ldr r3, [r7, #20] 8000c4c: 2203 movs r2, #3 8000c4e: 4013 ands r3, r2 8000c50: 009b lsls r3, r3, #2 8000c52: 220f movs r2, #15 8000c54: 409a lsls r2, r3 8000c56: 0013 movs r3, r2 8000c58: 43da mvns r2, r3 8000c5a: 693b ldr r3, [r7, #16] 8000c5c: 4013 ands r3, r2 8000c5e: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); 8000c60: 687a ldr r2, [r7, #4] 8000c62: 2390 movs r3, #144 ; 0x90 8000c64: 05db lsls r3, r3, #23 8000c66: 429a cmp r2, r3 8000c68: d00d beq.n 8000c86 8000c6a: 687b ldr r3, [r7, #4] 8000c6c: 4a41 ldr r2, [pc, #260] ; (8000d74 ) 8000c6e: 4293 cmp r3, r2 8000c70: d007 beq.n 8000c82 8000c72: 687b ldr r3, [r7, #4] 8000c74: 4a40 ldr r2, [pc, #256] ; (8000d78 ) 8000c76: 4293 cmp r3, r2 8000c78: d101 bne.n 8000c7e 8000c7a: 2302 movs r3, #2 8000c7c: e004 b.n 8000c88 8000c7e: 2305 movs r3, #5 8000c80: e002 b.n 8000c88 8000c82: 2301 movs r3, #1 8000c84: e000 b.n 8000c88 8000c86: 2300 movs r3, #0 8000c88: 697a ldr r2, [r7, #20] 8000c8a: 2103 movs r1, #3 8000c8c: 400a ands r2, r1 8000c8e: 0092 lsls r2, r2, #2 8000c90: 4093 lsls r3, r2 8000c92: 693a ldr r2, [r7, #16] 8000c94: 4313 orrs r3, r2 8000c96: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2u] = temp; 8000c98: 4935 ldr r1, [pc, #212] ; (8000d70 ) 8000c9a: 697b ldr r3, [r7, #20] 8000c9c: 089b lsrs r3, r3, #2 8000c9e: 3302 adds r3, #2 8000ca0: 009b lsls r3, r3, #2 8000ca2: 693a ldr r2, [r7, #16] 8000ca4: 505a str r2, [r3, r1] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 8000ca6: 4b35 ldr r3, [pc, #212] ; (8000d7c ) 8000ca8: 689b ldr r3, [r3, #8] 8000caa: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8000cac: 68fb ldr r3, [r7, #12] 8000cae: 43da mvns r2, r3 8000cb0: 693b ldr r3, [r7, #16] 8000cb2: 4013 ands r3, r2 8000cb4: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) 8000cb6: 683b ldr r3, [r7, #0] 8000cb8: 685a ldr r2, [r3, #4] 8000cba: 2380 movs r3, #128 ; 0x80 8000cbc: 035b lsls r3, r3, #13 8000cbe: 4013 ands r3, r2 8000cc0: d003 beq.n 8000cca { temp |= iocurrent; 8000cc2: 693a ldr r2, [r7, #16] 8000cc4: 68fb ldr r3, [r7, #12] 8000cc6: 4313 orrs r3, r2 8000cc8: 613b str r3, [r7, #16] } EXTI->RTSR = temp; 8000cca: 4b2c ldr r3, [pc, #176] ; (8000d7c ) 8000ccc: 693a ldr r2, [r7, #16] 8000cce: 609a str r2, [r3, #8] temp = EXTI->FTSR; 8000cd0: 4b2a ldr r3, [pc, #168] ; (8000d7c ) 8000cd2: 68db ldr r3, [r3, #12] 8000cd4: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8000cd6: 68fb ldr r3, [r7, #12] 8000cd8: 43da mvns r2, r3 8000cda: 693b ldr r3, [r7, #16] 8000cdc: 4013 ands r3, r2 8000cde: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) 8000ce0: 683b ldr r3, [r7, #0] 8000ce2: 685a ldr r2, [r3, #4] 8000ce4: 2380 movs r3, #128 ; 0x80 8000ce6: 039b lsls r3, r3, #14 8000ce8: 4013 ands r3, r2 8000cea: d003 beq.n 8000cf4 { temp |= iocurrent; 8000cec: 693a ldr r2, [r7, #16] 8000cee: 68fb ldr r3, [r7, #12] 8000cf0: 4313 orrs r3, r2 8000cf2: 613b str r3, [r7, #16] } EXTI->FTSR = temp; 8000cf4: 4b21 ldr r3, [pc, #132] ; (8000d7c ) 8000cf6: 693a ldr r2, [r7, #16] 8000cf8: 60da str r2, [r3, #12] /* Clear EXTI line configuration */ temp = EXTI->EMR; 8000cfa: 4b20 ldr r3, [pc, #128] ; (8000d7c ) 8000cfc: 685b ldr r3, [r3, #4] 8000cfe: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8000d00: 68fb ldr r3, [r7, #12] 8000d02: 43da mvns r2, r3 8000d04: 693b ldr r3, [r7, #16] 8000d06: 4013 ands r3, r2 8000d08: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_EVT) != 0x00u) 8000d0a: 683b ldr r3, [r7, #0] 8000d0c: 685a ldr r2, [r3, #4] 8000d0e: 2380 movs r3, #128 ; 0x80 8000d10: 029b lsls r3, r3, #10 8000d12: 4013 ands r3, r2 8000d14: d003 beq.n 8000d1e { temp |= iocurrent; 8000d16: 693a ldr r2, [r7, #16] 8000d18: 68fb ldr r3, [r7, #12] 8000d1a: 4313 orrs r3, r2 8000d1c: 613b str r3, [r7, #16] } EXTI->EMR = temp; 8000d1e: 4b17 ldr r3, [pc, #92] ; (8000d7c ) 8000d20: 693a ldr r2, [r7, #16] 8000d22: 605a str r2, [r3, #4] temp = EXTI->IMR; 8000d24: 4b15 ldr r3, [pc, #84] ; (8000d7c ) 8000d26: 681b ldr r3, [r3, #0] 8000d28: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8000d2a: 68fb ldr r3, [r7, #12] 8000d2c: 43da mvns r2, r3 8000d2e: 693b ldr r3, [r7, #16] 8000d30: 4013 ands r3, r2 8000d32: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_IT) != 0x00u) 8000d34: 683b ldr r3, [r7, #0] 8000d36: 685a ldr r2, [r3, #4] 8000d38: 2380 movs r3, #128 ; 0x80 8000d3a: 025b lsls r3, r3, #9 8000d3c: 4013 ands r3, r2 8000d3e: d003 beq.n 8000d48 { temp |= iocurrent; 8000d40: 693a ldr r2, [r7, #16] 8000d42: 68fb ldr r3, [r7, #12] 8000d44: 4313 orrs r3, r2 8000d46: 613b str r3, [r7, #16] } EXTI->IMR = temp; 8000d48: 4b0c ldr r3, [pc, #48] ; (8000d7c ) 8000d4a: 693a ldr r2, [r7, #16] 8000d4c: 601a str r2, [r3, #0] } } position++; 8000d4e: 697b ldr r3, [r7, #20] 8000d50: 3301 adds r3, #1 8000d52: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) 8000d54: 683b ldr r3, [r7, #0] 8000d56: 681a ldr r2, [r3, #0] 8000d58: 697b ldr r3, [r7, #20] 8000d5a: 40da lsrs r2, r3 8000d5c: 1e13 subs r3, r2, #0 8000d5e: d000 beq.n 8000d62 8000d60: e6ae b.n 8000ac0 } } 8000d62: 46c0 nop ; (mov r8, r8) 8000d64: 46c0 nop ; (mov r8, r8) 8000d66: 46bd mov sp, r7 8000d68: b006 add sp, #24 8000d6a: bd80 pop {r7, pc} 8000d6c: 40021000 .word 0x40021000 8000d70: 40010000 .word 0x40010000 8000d74: 48000400 .word 0x48000400 8000d78: 48000800 .word 0x48000800 8000d7c: 40010400 .word 0x40010400 08000d80 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 8000d80: b580 push {r7, lr} 8000d82: b082 sub sp, #8 8000d84: af00 add r7, sp, #0 8000d86: 6078 str r0, [r7, #4] /* Check the I2C handle allocation */ if (hi2c == NULL) 8000d88: 687b ldr r3, [r7, #4] 8000d8a: 2b00 cmp r3, #0 8000d8c: d101 bne.n 8000d92 { return HAL_ERROR; 8000d8e: 2301 movs r3, #1 8000d90: e082 b.n 8000e98 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 8000d92: 687b ldr r3, [r7, #4] 8000d94: 2241 movs r2, #65 ; 0x41 8000d96: 5c9b ldrb r3, [r3, r2] 8000d98: b2db uxtb r3, r3 8000d9a: 2b00 cmp r3, #0 8000d9c: d107 bne.n 8000dae { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 8000d9e: 687b ldr r3, [r7, #4] 8000da0: 2240 movs r2, #64 ; 0x40 8000da2: 2100 movs r1, #0 8000da4: 5499 strb r1, [r3, r2] /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2C_MspInit(hi2c); 8000da6: 687b ldr r3, [r7, #4] 8000da8: 0018 movs r0, r3 8000daa: f7ff fbbf bl 800052c #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 8000dae: 687b ldr r3, [r7, #4] 8000db0: 2241 movs r2, #65 ; 0x41 8000db2: 2124 movs r1, #36 ; 0x24 8000db4: 5499 strb r1, [r3, r2] /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8000db6: 687b ldr r3, [r7, #4] 8000db8: 681b ldr r3, [r3, #0] 8000dba: 681a ldr r2, [r3, #0] 8000dbc: 687b ldr r3, [r7, #4] 8000dbe: 681b ldr r3, [r3, #0] 8000dc0: 2101 movs r1, #1 8000dc2: 438a bics r2, r1 8000dc4: 601a str r2, [r3, #0] /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ /* Configure I2Cx: Frequency range */ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; 8000dc6: 687b ldr r3, [r7, #4] 8000dc8: 685a ldr r2, [r3, #4] 8000dca: 687b ldr r3, [r7, #4] 8000dcc: 681b ldr r3, [r3, #0] 8000dce: 4934 ldr r1, [pc, #208] ; (8000ea0 ) 8000dd0: 400a ands r2, r1 8000dd2: 611a str r2, [r3, #16] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Disable Own Address1 before set the Own Address1 configuration */ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; 8000dd4: 687b ldr r3, [r7, #4] 8000dd6: 681b ldr r3, [r3, #0] 8000dd8: 689a ldr r2, [r3, #8] 8000dda: 687b ldr r3, [r7, #4] 8000ddc: 681b ldr r3, [r3, #0] 8000dde: 4931 ldr r1, [pc, #196] ; (8000ea4 ) 8000de0: 400a ands r2, r1 8000de2: 609a str r2, [r3, #8] /* Configure I2Cx: Own Address1 and ack own address1 mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) 8000de4: 687b ldr r3, [r7, #4] 8000de6: 68db ldr r3, [r3, #12] 8000de8: 2b01 cmp r3, #1 8000dea: d108 bne.n 8000dfe { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); 8000dec: 687b ldr r3, [r7, #4] 8000dee: 689a ldr r2, [r3, #8] 8000df0: 687b ldr r3, [r7, #4] 8000df2: 681b ldr r3, [r3, #0] 8000df4: 2180 movs r1, #128 ; 0x80 8000df6: 0209 lsls r1, r1, #8 8000df8: 430a orrs r2, r1 8000dfa: 609a str r2, [r3, #8] 8000dfc: e007 b.n 8000e0e } else /* I2C_ADDRESSINGMODE_10BIT */ { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); 8000dfe: 687b ldr r3, [r7, #4] 8000e00: 689a ldr r2, [r3, #8] 8000e02: 687b ldr r3, [r7, #4] 8000e04: 681b ldr r3, [r3, #0] 8000e06: 2184 movs r1, #132 ; 0x84 8000e08: 0209 lsls r1, r1, #8 8000e0a: 430a orrs r2, r1 8000e0c: 609a str r2, [r3, #8] } /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Addressing Master mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) 8000e0e: 687b ldr r3, [r7, #4] 8000e10: 68db ldr r3, [r3, #12] 8000e12: 2b02 cmp r3, #2 8000e14: d104 bne.n 8000e20 { hi2c->Instance->CR2 = (I2C_CR2_ADD10); 8000e16: 687b ldr r3, [r7, #4] 8000e18: 681b ldr r3, [r3, #0] 8000e1a: 2280 movs r2, #128 ; 0x80 8000e1c: 0112 lsls r2, r2, #4 8000e1e: 605a str r2, [r3, #4] } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); 8000e20: 687b ldr r3, [r7, #4] 8000e22: 681b ldr r3, [r3, #0] 8000e24: 685a ldr r2, [r3, #4] 8000e26: 687b ldr r3, [r7, #4] 8000e28: 681b ldr r3, [r3, #0] 8000e2a: 491f ldr r1, [pc, #124] ; (8000ea8 ) 8000e2c: 430a orrs r2, r1 8000e2e: 605a str r2, [r3, #4] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Disable Own Address2 before set the Own Address2 configuration */ hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; 8000e30: 687b ldr r3, [r7, #4] 8000e32: 681b ldr r3, [r3, #0] 8000e34: 68da ldr r2, [r3, #12] 8000e36: 687b ldr r3, [r7, #4] 8000e38: 681b ldr r3, [r3, #0] 8000e3a: 491a ldr r1, [pc, #104] ; (8000ea4 ) 8000e3c: 400a ands r2, r1 8000e3e: 60da str r2, [r3, #12] /* Configure I2Cx: Dual mode and Own Address2 */ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ 8000e40: 687b ldr r3, [r7, #4] 8000e42: 691a ldr r2, [r3, #16] 8000e44: 687b ldr r3, [r7, #4] 8000e46: 695b ldr r3, [r3, #20] 8000e48: 431a orrs r2, r3 8000e4a: 0011 movs r1, r2 (hi2c->Init.OwnAddress2Masks << 8)); 8000e4c: 687b ldr r3, [r7, #4] 8000e4e: 699b ldr r3, [r3, #24] 8000e50: 021a lsls r2, r3, #8 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ 8000e52: 687b ldr r3, [r7, #4] 8000e54: 681b ldr r3, [r3, #0] 8000e56: 430a orrs r2, r1 8000e58: 60da str r2, [r3, #12] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); 8000e5a: 687b ldr r3, [r7, #4] 8000e5c: 69d9 ldr r1, [r3, #28] 8000e5e: 687b ldr r3, [r7, #4] 8000e60: 6a1a ldr r2, [r3, #32] 8000e62: 687b ldr r3, [r7, #4] 8000e64: 681b ldr r3, [r3, #0] 8000e66: 430a orrs r2, r1 8000e68: 601a str r2, [r3, #0] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8000e6a: 687b ldr r3, [r7, #4] 8000e6c: 681b ldr r3, [r3, #0] 8000e6e: 681a ldr r2, [r3, #0] 8000e70: 687b ldr r3, [r7, #4] 8000e72: 681b ldr r3, [r3, #0] 8000e74: 2101 movs r1, #1 8000e76: 430a orrs r2, r1 8000e78: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8000e7a: 687b ldr r3, [r7, #4] 8000e7c: 2200 movs r2, #0 8000e7e: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; 8000e80: 687b ldr r3, [r7, #4] 8000e82: 2241 movs r2, #65 ; 0x41 8000e84: 2120 movs r1, #32 8000e86: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 8000e88: 687b ldr r3, [r7, #4] 8000e8a: 2200 movs r2, #0 8000e8c: 631a str r2, [r3, #48] ; 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8000e8e: 687b ldr r3, [r7, #4] 8000e90: 2242 movs r2, #66 ; 0x42 8000e92: 2100 movs r1, #0 8000e94: 5499 strb r1, [r3, r2] return HAL_OK; 8000e96: 2300 movs r3, #0 } 8000e98: 0018 movs r0, r3 8000e9a: 46bd mov sp, r7 8000e9c: b002 add sp, #8 8000e9e: bd80 pop {r7, pc} 8000ea0: f0ffffff .word 0xf0ffffff 8000ea4: ffff7fff .word 0xffff7fff 8000ea8: 02008000 .word 0x02008000 08000eac : * the configuration information for the specified I2Cx peripheral. * @param AnalogFilter New state of the Analog filter. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) { 8000eac: b580 push {r7, lr} 8000eae: b082 sub sp, #8 8000eb0: af00 add r7, sp, #0 8000eb2: 6078 str r0, [r7, #4] 8000eb4: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 8000eb6: 687b ldr r3, [r7, #4] 8000eb8: 2241 movs r2, #65 ; 0x41 8000eba: 5c9b ldrb r3, [r3, r2] 8000ebc: b2db uxtb r3, r3 8000ebe: 2b20 cmp r3, #32 8000ec0: d138 bne.n 8000f34 { /* Process Locked */ __HAL_LOCK(hi2c); 8000ec2: 687b ldr r3, [r7, #4] 8000ec4: 2240 movs r2, #64 ; 0x40 8000ec6: 5c9b ldrb r3, [r3, r2] 8000ec8: 2b01 cmp r3, #1 8000eca: d101 bne.n 8000ed0 8000ecc: 2302 movs r3, #2 8000ece: e032 b.n 8000f36 8000ed0: 687b ldr r3, [r7, #4] 8000ed2: 2240 movs r2, #64 ; 0x40 8000ed4: 2101 movs r1, #1 8000ed6: 5499 strb r1, [r3, r2] hi2c->State = HAL_I2C_STATE_BUSY; 8000ed8: 687b ldr r3, [r7, #4] 8000eda: 2241 movs r2, #65 ; 0x41 8000edc: 2124 movs r1, #36 ; 0x24 8000ede: 5499 strb r1, [r3, r2] /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8000ee0: 687b ldr r3, [r7, #4] 8000ee2: 681b ldr r3, [r3, #0] 8000ee4: 681a ldr r2, [r3, #0] 8000ee6: 687b ldr r3, [r7, #4] 8000ee8: 681b ldr r3, [r3, #0] 8000eea: 2101 movs r1, #1 8000eec: 438a bics r2, r1 8000eee: 601a str r2, [r3, #0] /* Reset I2Cx ANOFF bit */ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); 8000ef0: 687b ldr r3, [r7, #4] 8000ef2: 681b ldr r3, [r3, #0] 8000ef4: 681a ldr r2, [r3, #0] 8000ef6: 687b ldr r3, [r7, #4] 8000ef8: 681b ldr r3, [r3, #0] 8000efa: 4911 ldr r1, [pc, #68] ; (8000f40 ) 8000efc: 400a ands r2, r1 8000efe: 601a str r2, [r3, #0] /* Set analog filter bit*/ hi2c->Instance->CR1 |= AnalogFilter; 8000f00: 687b ldr r3, [r7, #4] 8000f02: 681b ldr r3, [r3, #0] 8000f04: 6819 ldr r1, [r3, #0] 8000f06: 687b ldr r3, [r7, #4] 8000f08: 681b ldr r3, [r3, #0] 8000f0a: 683a ldr r2, [r7, #0] 8000f0c: 430a orrs r2, r1 8000f0e: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); 8000f10: 687b ldr r3, [r7, #4] 8000f12: 681b ldr r3, [r3, #0] 8000f14: 681a ldr r2, [r3, #0] 8000f16: 687b ldr r3, [r7, #4] 8000f18: 681b ldr r3, [r3, #0] 8000f1a: 2101 movs r1, #1 8000f1c: 430a orrs r2, r1 8000f1e: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 8000f20: 687b ldr r3, [r7, #4] 8000f22: 2241 movs r2, #65 ; 0x41 8000f24: 2120 movs r1, #32 8000f26: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8000f28: 687b ldr r3, [r7, #4] 8000f2a: 2240 movs r2, #64 ; 0x40 8000f2c: 2100 movs r1, #0 8000f2e: 5499 strb r1, [r3, r2] return HAL_OK; 8000f30: 2300 movs r3, #0 8000f32: e000 b.n 8000f36 } else { return HAL_BUSY; 8000f34: 2302 movs r3, #2 } } 8000f36: 0018 movs r0, r3 8000f38: 46bd mov sp, r7 8000f3a: b002 add sp, #8 8000f3c: bd80 pop {r7, pc} 8000f3e: 46c0 nop ; (mov r8, r8) 8000f40: ffffefff .word 0xffffefff 08000f44 : * the configuration information for the specified I2Cx peripheral. * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { 8000f44: b580 push {r7, lr} 8000f46: b084 sub sp, #16 8000f48: af00 add r7, sp, #0 8000f4a: 6078 str r0, [r7, #4] 8000f4c: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 8000f4e: 687b ldr r3, [r7, #4] 8000f50: 2241 movs r2, #65 ; 0x41 8000f52: 5c9b ldrb r3, [r3, r2] 8000f54: b2db uxtb r3, r3 8000f56: 2b20 cmp r3, #32 8000f58: d139 bne.n 8000fce { /* Process Locked */ __HAL_LOCK(hi2c); 8000f5a: 687b ldr r3, [r7, #4] 8000f5c: 2240 movs r2, #64 ; 0x40 8000f5e: 5c9b ldrb r3, [r3, r2] 8000f60: 2b01 cmp r3, #1 8000f62: d101 bne.n 8000f68 8000f64: 2302 movs r3, #2 8000f66: e033 b.n 8000fd0 8000f68: 687b ldr r3, [r7, #4] 8000f6a: 2240 movs r2, #64 ; 0x40 8000f6c: 2101 movs r1, #1 8000f6e: 5499 strb r1, [r3, r2] hi2c->State = HAL_I2C_STATE_BUSY; 8000f70: 687b ldr r3, [r7, #4] 8000f72: 2241 movs r2, #65 ; 0x41 8000f74: 2124 movs r1, #36 ; 0x24 8000f76: 5499 strb r1, [r3, r2] /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8000f78: 687b ldr r3, [r7, #4] 8000f7a: 681b ldr r3, [r3, #0] 8000f7c: 681a ldr r2, [r3, #0] 8000f7e: 687b ldr r3, [r7, #4] 8000f80: 681b ldr r3, [r3, #0] 8000f82: 2101 movs r1, #1 8000f84: 438a bics r2, r1 8000f86: 601a str r2, [r3, #0] /* Get the old register value */ tmpreg = hi2c->Instance->CR1; 8000f88: 687b ldr r3, [r7, #4] 8000f8a: 681b ldr r3, [r3, #0] 8000f8c: 681b ldr r3, [r3, #0] 8000f8e: 60fb str r3, [r7, #12] /* Reset I2Cx DNF bits [11:8] */ tmpreg &= ~(I2C_CR1_DNF); 8000f90: 68fb ldr r3, [r7, #12] 8000f92: 4a11 ldr r2, [pc, #68] ; (8000fd8 ) 8000f94: 4013 ands r3, r2 8000f96: 60fb str r3, [r7, #12] /* Set I2Cx DNF coefficient */ tmpreg |= DigitalFilter << 8U; 8000f98: 683b ldr r3, [r7, #0] 8000f9a: 021b lsls r3, r3, #8 8000f9c: 68fa ldr r2, [r7, #12] 8000f9e: 4313 orrs r3, r2 8000fa0: 60fb str r3, [r7, #12] /* Store the new register value */ hi2c->Instance->CR1 = tmpreg; 8000fa2: 687b ldr r3, [r7, #4] 8000fa4: 681b ldr r3, [r3, #0] 8000fa6: 68fa ldr r2, [r7, #12] 8000fa8: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); 8000faa: 687b ldr r3, [r7, #4] 8000fac: 681b ldr r3, [r3, #0] 8000fae: 681a ldr r2, [r3, #0] 8000fb0: 687b ldr r3, [r7, #4] 8000fb2: 681b ldr r3, [r3, #0] 8000fb4: 2101 movs r1, #1 8000fb6: 430a orrs r2, r1 8000fb8: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 8000fba: 687b ldr r3, [r7, #4] 8000fbc: 2241 movs r2, #65 ; 0x41 8000fbe: 2120 movs r1, #32 8000fc0: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8000fc2: 687b ldr r3, [r7, #4] 8000fc4: 2240 movs r2, #64 ; 0x40 8000fc6: 2100 movs r1, #0 8000fc8: 5499 strb r1, [r3, r2] return HAL_OK; 8000fca: 2300 movs r3, #0 8000fcc: e000 b.n 8000fd0 } else { return HAL_BUSY; 8000fce: 2302 movs r3, #2 } } 8000fd0: 0018 movs r0, r3 8000fd2: 46bd mov sp, r7 8000fd4: b004 add sp, #16 8000fd6: bd80 pop {r7, pc} 8000fd8: fffff0ff .word 0xfffff0ff 08000fdc : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8000fdc: b580 push {r7, lr} 8000fde: b088 sub sp, #32 8000fe0: af00 add r7, sp, #0 8000fe2: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; uint32_t pll_config2; /* Check Null pointer */ if(RCC_OscInitStruct == NULL) 8000fe4: 687b ldr r3, [r7, #4] 8000fe6: 2b00 cmp r3, #0 8000fe8: d102 bne.n 8000ff0 { return HAL_ERROR; 8000fea: 2301 movs r3, #1 8000fec: f000 fb76 bl 80016dc /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8000ff0: 687b ldr r3, [r7, #4] 8000ff2: 681b ldr r3, [r3, #0] 8000ff4: 2201 movs r2, #1 8000ff6: 4013 ands r3, r2 8000ff8: d100 bne.n 8000ffc 8000ffa: e08e b.n 800111a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8000ffc: 4bc5 ldr r3, [pc, #788] ; (8001314 ) 8000ffe: 685b ldr r3, [r3, #4] 8001000: 220c movs r2, #12 8001002: 4013 ands r3, r2 8001004: 2b04 cmp r3, #4 8001006: d00e beq.n 8001026 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8001008: 4bc2 ldr r3, [pc, #776] ; (8001314 ) 800100a: 685b ldr r3, [r3, #4] 800100c: 220c movs r2, #12 800100e: 4013 ands r3, r2 8001010: 2b08 cmp r3, #8 8001012: d117 bne.n 8001044 8001014: 4bbf ldr r3, [pc, #764] ; (8001314 ) 8001016: 685a ldr r2, [r3, #4] 8001018: 23c0 movs r3, #192 ; 0xc0 800101a: 025b lsls r3, r3, #9 800101c: 401a ands r2, r3 800101e: 2380 movs r3, #128 ; 0x80 8001020: 025b lsls r3, r3, #9 8001022: 429a cmp r2, r3 8001024: d10e bne.n 8001044 { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8001026: 4bbb ldr r3, [pc, #748] ; (8001314 ) 8001028: 681a ldr r2, [r3, #0] 800102a: 2380 movs r3, #128 ; 0x80 800102c: 029b lsls r3, r3, #10 800102e: 4013 ands r3, r2 8001030: d100 bne.n 8001034 8001032: e071 b.n 8001118 8001034: 687b ldr r3, [r7, #4] 8001036: 685b ldr r3, [r3, #4] 8001038: 2b00 cmp r3, #0 800103a: d000 beq.n 800103e 800103c: e06c b.n 8001118 { return HAL_ERROR; 800103e: 2301 movs r3, #1 8001040: f000 fb4c bl 80016dc } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8001044: 687b ldr r3, [r7, #4] 8001046: 685b ldr r3, [r3, #4] 8001048: 2b01 cmp r3, #1 800104a: d107 bne.n 800105c 800104c: 4bb1 ldr r3, [pc, #708] ; (8001314 ) 800104e: 681a ldr r2, [r3, #0] 8001050: 4bb0 ldr r3, [pc, #704] ; (8001314 ) 8001052: 2180 movs r1, #128 ; 0x80 8001054: 0249 lsls r1, r1, #9 8001056: 430a orrs r2, r1 8001058: 601a str r2, [r3, #0] 800105a: e02f b.n 80010bc 800105c: 687b ldr r3, [r7, #4] 800105e: 685b ldr r3, [r3, #4] 8001060: 2b00 cmp r3, #0 8001062: d10c bne.n 800107e 8001064: 4bab ldr r3, [pc, #684] ; (8001314 ) 8001066: 681a ldr r2, [r3, #0] 8001068: 4baa ldr r3, [pc, #680] ; (8001314 ) 800106a: 49ab ldr r1, [pc, #684] ; (8001318 ) 800106c: 400a ands r2, r1 800106e: 601a str r2, [r3, #0] 8001070: 4ba8 ldr r3, [pc, #672] ; (8001314 ) 8001072: 681a ldr r2, [r3, #0] 8001074: 4ba7 ldr r3, [pc, #668] ; (8001314 ) 8001076: 49a9 ldr r1, [pc, #676] ; (800131c ) 8001078: 400a ands r2, r1 800107a: 601a str r2, [r3, #0] 800107c: e01e b.n 80010bc 800107e: 687b ldr r3, [r7, #4] 8001080: 685b ldr r3, [r3, #4] 8001082: 2b05 cmp r3, #5 8001084: d10e bne.n 80010a4 8001086: 4ba3 ldr r3, [pc, #652] ; (8001314 ) 8001088: 681a ldr r2, [r3, #0] 800108a: 4ba2 ldr r3, [pc, #648] ; (8001314 ) 800108c: 2180 movs r1, #128 ; 0x80 800108e: 02c9 lsls r1, r1, #11 8001090: 430a orrs r2, r1 8001092: 601a str r2, [r3, #0] 8001094: 4b9f ldr r3, [pc, #636] ; (8001314 ) 8001096: 681a ldr r2, [r3, #0] 8001098: 4b9e ldr r3, [pc, #632] ; (8001314 ) 800109a: 2180 movs r1, #128 ; 0x80 800109c: 0249 lsls r1, r1, #9 800109e: 430a orrs r2, r1 80010a0: 601a str r2, [r3, #0] 80010a2: e00b b.n 80010bc 80010a4: 4b9b ldr r3, [pc, #620] ; (8001314 ) 80010a6: 681a ldr r2, [r3, #0] 80010a8: 4b9a ldr r3, [pc, #616] ; (8001314 ) 80010aa: 499b ldr r1, [pc, #620] ; (8001318 ) 80010ac: 400a ands r2, r1 80010ae: 601a str r2, [r3, #0] 80010b0: 4b98 ldr r3, [pc, #608] ; (8001314 ) 80010b2: 681a ldr r2, [r3, #0] 80010b4: 4b97 ldr r3, [pc, #604] ; (8001314 ) 80010b6: 4999 ldr r1, [pc, #612] ; (800131c ) 80010b8: 400a ands r2, r1 80010ba: 601a str r2, [r3, #0] /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 80010bc: 687b ldr r3, [r7, #4] 80010be: 685b ldr r3, [r3, #4] 80010c0: 2b00 cmp r3, #0 80010c2: d014 beq.n 80010ee { /* Get Start Tick */ tickstart = HAL_GetTick(); 80010c4: f7ff fb38 bl 8000738 80010c8: 0003 movs r3, r0 80010ca: 61bb str r3, [r7, #24] /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80010cc: e008 b.n 80010e0 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 80010ce: f7ff fb33 bl 8000738 80010d2: 0002 movs r2, r0 80010d4: 69bb ldr r3, [r7, #24] 80010d6: 1ad3 subs r3, r2, r3 80010d8: 2b64 cmp r3, #100 ; 0x64 80010da: d901 bls.n 80010e0 { return HAL_TIMEOUT; 80010dc: 2303 movs r3, #3 80010de: e2fd b.n 80016dc while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80010e0: 4b8c ldr r3, [pc, #560] ; (8001314 ) 80010e2: 681a ldr r2, [r3, #0] 80010e4: 2380 movs r3, #128 ; 0x80 80010e6: 029b lsls r3, r3, #10 80010e8: 4013 ands r3, r2 80010ea: d0f0 beq.n 80010ce 80010ec: e015 b.n 800111a } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 80010ee: f7ff fb23 bl 8000738 80010f2: 0003 movs r3, r0 80010f4: 61bb str r3, [r7, #24] /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 80010f6: e008 b.n 800110a { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 80010f8: f7ff fb1e bl 8000738 80010fc: 0002 movs r2, r0 80010fe: 69bb ldr r3, [r7, #24] 8001100: 1ad3 subs r3, r2, r3 8001102: 2b64 cmp r3, #100 ; 0x64 8001104: d901 bls.n 800110a { return HAL_TIMEOUT; 8001106: 2303 movs r3, #3 8001108: e2e8 b.n 80016dc while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800110a: 4b82 ldr r3, [pc, #520] ; (8001314 ) 800110c: 681a ldr r2, [r3, #0] 800110e: 2380 movs r3, #128 ; 0x80 8001110: 029b lsls r3, r3, #10 8001112: 4013 ands r3, r2 8001114: d1f0 bne.n 80010f8 8001116: e000 b.n 800111a if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8001118: 46c0 nop ; (mov r8, r8) } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800111a: 687b ldr r3, [r7, #4] 800111c: 681b ldr r3, [r3, #0] 800111e: 2202 movs r2, #2 8001120: 4013 ands r3, r2 8001122: d100 bne.n 8001126 8001124: e06c b.n 8001200 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8001126: 4b7b ldr r3, [pc, #492] ; (8001314 ) 8001128: 685b ldr r3, [r3, #4] 800112a: 220c movs r2, #12 800112c: 4013 ands r3, r2 800112e: d00e beq.n 800114e || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) 8001130: 4b78 ldr r3, [pc, #480] ; (8001314 ) 8001132: 685b ldr r3, [r3, #4] 8001134: 220c movs r2, #12 8001136: 4013 ands r3, r2 8001138: 2b08 cmp r3, #8 800113a: d11f bne.n 800117c 800113c: 4b75 ldr r3, [pc, #468] ; (8001314 ) 800113e: 685a ldr r2, [r3, #4] 8001140: 23c0 movs r3, #192 ; 0xc0 8001142: 025b lsls r3, r3, #9 8001144: 401a ands r2, r3 8001146: 2380 movs r3, #128 ; 0x80 8001148: 021b lsls r3, r3, #8 800114a: 429a cmp r2, r3 800114c: d116 bne.n 800117c { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 800114e: 4b71 ldr r3, [pc, #452] ; (8001314 ) 8001150: 681b ldr r3, [r3, #0] 8001152: 2202 movs r2, #2 8001154: 4013 ands r3, r2 8001156: d005 beq.n 8001164 8001158: 687b ldr r3, [r7, #4] 800115a: 68db ldr r3, [r3, #12] 800115c: 2b01 cmp r3, #1 800115e: d001 beq.n 8001164 { return HAL_ERROR; 8001160: 2301 movs r3, #1 8001162: e2bb b.n 80016dc } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8001164: 4b6b ldr r3, [pc, #428] ; (8001314 ) 8001166: 681b ldr r3, [r3, #0] 8001168: 22f8 movs r2, #248 ; 0xf8 800116a: 4393 bics r3, r2 800116c: 0019 movs r1, r3 800116e: 687b ldr r3, [r7, #4] 8001170: 691b ldr r3, [r3, #16] 8001172: 00da lsls r2, r3, #3 8001174: 4b67 ldr r3, [pc, #412] ; (8001314 ) 8001176: 430a orrs r2, r1 8001178: 601a str r2, [r3, #0] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 800117a: e041 b.n 8001200 } } else { /* Check the HSI State */ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 800117c: 687b ldr r3, [r7, #4] 800117e: 68db ldr r3, [r3, #12] 8001180: 2b00 cmp r3, #0 8001182: d024 beq.n 80011ce { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8001184: 4b63 ldr r3, [pc, #396] ; (8001314 ) 8001186: 681a ldr r2, [r3, #0] 8001188: 4b62 ldr r3, [pc, #392] ; (8001314 ) 800118a: 2101 movs r1, #1 800118c: 430a orrs r2, r1 800118e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001190: f7ff fad2 bl 8000738 8001194: 0003 movs r3, r0 8001196: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001198: e008 b.n 80011ac { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 800119a: f7ff facd bl 8000738 800119e: 0002 movs r2, r0 80011a0: 69bb ldr r3, [r7, #24] 80011a2: 1ad3 subs r3, r2, r3 80011a4: 2b02 cmp r3, #2 80011a6: d901 bls.n 80011ac { return HAL_TIMEOUT; 80011a8: 2303 movs r3, #3 80011aa: e297 b.n 80016dc while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80011ac: 4b59 ldr r3, [pc, #356] ; (8001314 ) 80011ae: 681b ldr r3, [r3, #0] 80011b0: 2202 movs r2, #2 80011b2: 4013 ands r3, r2 80011b4: d0f1 beq.n 800119a } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80011b6: 4b57 ldr r3, [pc, #348] ; (8001314 ) 80011b8: 681b ldr r3, [r3, #0] 80011ba: 22f8 movs r2, #248 ; 0xf8 80011bc: 4393 bics r3, r2 80011be: 0019 movs r1, r3 80011c0: 687b ldr r3, [r7, #4] 80011c2: 691b ldr r3, [r3, #16] 80011c4: 00da lsls r2, r3, #3 80011c6: 4b53 ldr r3, [pc, #332] ; (8001314 ) 80011c8: 430a orrs r2, r1 80011ca: 601a str r2, [r3, #0] 80011cc: e018 b.n 8001200 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 80011ce: 4b51 ldr r3, [pc, #324] ; (8001314 ) 80011d0: 681a ldr r2, [r3, #0] 80011d2: 4b50 ldr r3, [pc, #320] ; (8001314 ) 80011d4: 2101 movs r1, #1 80011d6: 438a bics r2, r1 80011d8: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80011da: f7ff faad bl 8000738 80011de: 0003 movs r3, r0 80011e0: 61bb str r3, [r7, #24] /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 80011e2: e008 b.n 80011f6 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 80011e4: f7ff faa8 bl 8000738 80011e8: 0002 movs r2, r0 80011ea: 69bb ldr r3, [r7, #24] 80011ec: 1ad3 subs r3, r2, r3 80011ee: 2b02 cmp r3, #2 80011f0: d901 bls.n 80011f6 { return HAL_TIMEOUT; 80011f2: 2303 movs r3, #3 80011f4: e272 b.n 80016dc while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 80011f6: 4b47 ldr r3, [pc, #284] ; (8001314 ) 80011f8: 681b ldr r3, [r3, #0] 80011fa: 2202 movs r2, #2 80011fc: 4013 ands r3, r2 80011fe: d1f1 bne.n 80011e4 } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8001200: 687b ldr r3, [r7, #4] 8001202: 681b ldr r3, [r3, #0] 8001204: 2208 movs r2, #8 8001206: 4013 ands r3, r2 8001208: d036 beq.n 8001278 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 800120a: 687b ldr r3, [r7, #4] 800120c: 69db ldr r3, [r3, #28] 800120e: 2b00 cmp r3, #0 8001210: d019 beq.n 8001246 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8001212: 4b40 ldr r3, [pc, #256] ; (8001314 ) 8001214: 6a5a ldr r2, [r3, #36] ; 0x24 8001216: 4b3f ldr r3, [pc, #252] ; (8001314 ) 8001218: 2101 movs r1, #1 800121a: 430a orrs r2, r1 800121c: 625a str r2, [r3, #36] ; 0x24 /* Get Start Tick */ tickstart = HAL_GetTick(); 800121e: f7ff fa8b bl 8000738 8001222: 0003 movs r3, r0 8001224: 61bb str r3, [r7, #24] /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8001226: e008 b.n 800123a { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8001228: f7ff fa86 bl 8000738 800122c: 0002 movs r2, r0 800122e: 69bb ldr r3, [r7, #24] 8001230: 1ad3 subs r3, r2, r3 8001232: 2b02 cmp r3, #2 8001234: d901 bls.n 800123a { return HAL_TIMEOUT; 8001236: 2303 movs r3, #3 8001238: e250 b.n 80016dc while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800123a: 4b36 ldr r3, [pc, #216] ; (8001314 ) 800123c: 6a5b ldr r3, [r3, #36] ; 0x24 800123e: 2202 movs r2, #2 8001240: 4013 ands r3, r2 8001242: d0f1 beq.n 8001228 8001244: e018 b.n 8001278 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8001246: 4b33 ldr r3, [pc, #204] ; (8001314 ) 8001248: 6a5a ldr r2, [r3, #36] ; 0x24 800124a: 4b32 ldr r3, [pc, #200] ; (8001314 ) 800124c: 2101 movs r1, #1 800124e: 438a bics r2, r1 8001250: 625a str r2, [r3, #36] ; 0x24 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001252: f7ff fa71 bl 8000738 8001256: 0003 movs r3, r0 8001258: 61bb str r3, [r7, #24] /* Wait till LSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800125a: e008 b.n 800126e { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 800125c: f7ff fa6c bl 8000738 8001260: 0002 movs r2, r0 8001262: 69bb ldr r3, [r7, #24] 8001264: 1ad3 subs r3, r2, r3 8001266: 2b02 cmp r3, #2 8001268: d901 bls.n 800126e { return HAL_TIMEOUT; 800126a: 2303 movs r3, #3 800126c: e236 b.n 80016dc while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800126e: 4b29 ldr r3, [pc, #164] ; (8001314 ) 8001270: 6a5b ldr r3, [r3, #36] ; 0x24 8001272: 2202 movs r2, #2 8001274: 4013 ands r3, r2 8001276: d1f1 bne.n 800125c } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8001278: 687b ldr r3, [r7, #4] 800127a: 681b ldr r3, [r3, #0] 800127c: 2204 movs r2, #4 800127e: 4013 ands r3, r2 8001280: d100 bne.n 8001284 8001282: e0b5 b.n 80013f0 { FlagStatus pwrclkchanged = RESET; 8001284: 201f movs r0, #31 8001286: 183b adds r3, r7, r0 8001288: 2200 movs r2, #0 800128a: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 800128c: 4b21 ldr r3, [pc, #132] ; (8001314 ) 800128e: 69da ldr r2, [r3, #28] 8001290: 2380 movs r3, #128 ; 0x80 8001292: 055b lsls r3, r3, #21 8001294: 4013 ands r3, r2 8001296: d110 bne.n 80012ba { __HAL_RCC_PWR_CLK_ENABLE(); 8001298: 4b1e ldr r3, [pc, #120] ; (8001314 ) 800129a: 69da ldr r2, [r3, #28] 800129c: 4b1d ldr r3, [pc, #116] ; (8001314 ) 800129e: 2180 movs r1, #128 ; 0x80 80012a0: 0549 lsls r1, r1, #21 80012a2: 430a orrs r2, r1 80012a4: 61da str r2, [r3, #28] 80012a6: 4b1b ldr r3, [pc, #108] ; (8001314 ) 80012a8: 69da ldr r2, [r3, #28] 80012aa: 2380 movs r3, #128 ; 0x80 80012ac: 055b lsls r3, r3, #21 80012ae: 4013 ands r3, r2 80012b0: 60fb str r3, [r7, #12] 80012b2: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 80012b4: 183b adds r3, r7, r0 80012b6: 2201 movs r2, #1 80012b8: 701a strb r2, [r3, #0] } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80012ba: 4b19 ldr r3, [pc, #100] ; (8001320 ) 80012bc: 681a ldr r2, [r3, #0] 80012be: 2380 movs r3, #128 ; 0x80 80012c0: 005b lsls r3, r3, #1 80012c2: 4013 ands r3, r2 80012c4: d11a bne.n 80012fc { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 80012c6: 4b16 ldr r3, [pc, #88] ; (8001320 ) 80012c8: 681a ldr r2, [r3, #0] 80012ca: 4b15 ldr r3, [pc, #84] ; (8001320 ) 80012cc: 2180 movs r1, #128 ; 0x80 80012ce: 0049 lsls r1, r1, #1 80012d0: 430a orrs r2, r1 80012d2: 601a str r2, [r3, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80012d4: f7ff fa30 bl 8000738 80012d8: 0003 movs r3, r0 80012da: 61bb str r3, [r7, #24] while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80012dc: e008 b.n 80012f0 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80012de: f7ff fa2b bl 8000738 80012e2: 0002 movs r2, r0 80012e4: 69bb ldr r3, [r7, #24] 80012e6: 1ad3 subs r3, r2, r3 80012e8: 2b64 cmp r3, #100 ; 0x64 80012ea: d901 bls.n 80012f0 { return HAL_TIMEOUT; 80012ec: 2303 movs r3, #3 80012ee: e1f5 b.n 80016dc while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80012f0: 4b0b ldr r3, [pc, #44] ; (8001320 ) 80012f2: 681a ldr r2, [r3, #0] 80012f4: 2380 movs r3, #128 ; 0x80 80012f6: 005b lsls r3, r3, #1 80012f8: 4013 ands r3, r2 80012fa: d0f0 beq.n 80012de } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 80012fc: 687b ldr r3, [r7, #4] 80012fe: 689b ldr r3, [r3, #8] 8001300: 2b01 cmp r3, #1 8001302: d10f bne.n 8001324 8001304: 4b03 ldr r3, [pc, #12] ; (8001314 ) 8001306: 6a1a ldr r2, [r3, #32] 8001308: 4b02 ldr r3, [pc, #8] ; (8001314 ) 800130a: 2101 movs r1, #1 800130c: 430a orrs r2, r1 800130e: 621a str r2, [r3, #32] 8001310: e036 b.n 8001380 8001312: 46c0 nop ; (mov r8, r8) 8001314: 40021000 .word 0x40021000 8001318: fffeffff .word 0xfffeffff 800131c: fffbffff .word 0xfffbffff 8001320: 40007000 .word 0x40007000 8001324: 687b ldr r3, [r7, #4] 8001326: 689b ldr r3, [r3, #8] 8001328: 2b00 cmp r3, #0 800132a: d10c bne.n 8001346 800132c: 4bca ldr r3, [pc, #808] ; (8001658 ) 800132e: 6a1a ldr r2, [r3, #32] 8001330: 4bc9 ldr r3, [pc, #804] ; (8001658 ) 8001332: 2101 movs r1, #1 8001334: 438a bics r2, r1 8001336: 621a str r2, [r3, #32] 8001338: 4bc7 ldr r3, [pc, #796] ; (8001658 ) 800133a: 6a1a ldr r2, [r3, #32] 800133c: 4bc6 ldr r3, [pc, #792] ; (8001658 ) 800133e: 2104 movs r1, #4 8001340: 438a bics r2, r1 8001342: 621a str r2, [r3, #32] 8001344: e01c b.n 8001380 8001346: 687b ldr r3, [r7, #4] 8001348: 689b ldr r3, [r3, #8] 800134a: 2b05 cmp r3, #5 800134c: d10c bne.n 8001368 800134e: 4bc2 ldr r3, [pc, #776] ; (8001658 ) 8001350: 6a1a ldr r2, [r3, #32] 8001352: 4bc1 ldr r3, [pc, #772] ; (8001658 ) 8001354: 2104 movs r1, #4 8001356: 430a orrs r2, r1 8001358: 621a str r2, [r3, #32] 800135a: 4bbf ldr r3, [pc, #764] ; (8001658 ) 800135c: 6a1a ldr r2, [r3, #32] 800135e: 4bbe ldr r3, [pc, #760] ; (8001658 ) 8001360: 2101 movs r1, #1 8001362: 430a orrs r2, r1 8001364: 621a str r2, [r3, #32] 8001366: e00b b.n 8001380 8001368: 4bbb ldr r3, [pc, #748] ; (8001658 ) 800136a: 6a1a ldr r2, [r3, #32] 800136c: 4bba ldr r3, [pc, #744] ; (8001658 ) 800136e: 2101 movs r1, #1 8001370: 438a bics r2, r1 8001372: 621a str r2, [r3, #32] 8001374: 4bb8 ldr r3, [pc, #736] ; (8001658 ) 8001376: 6a1a ldr r2, [r3, #32] 8001378: 4bb7 ldr r3, [pc, #732] ; (8001658 ) 800137a: 2104 movs r1, #4 800137c: 438a bics r2, r1 800137e: 621a str r2, [r3, #32] /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8001380: 687b ldr r3, [r7, #4] 8001382: 689b ldr r3, [r3, #8] 8001384: 2b00 cmp r3, #0 8001386: d014 beq.n 80013b2 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001388: f7ff f9d6 bl 8000738 800138c: 0003 movs r3, r0 800138e: 61bb str r3, [r7, #24] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8001390: e009 b.n 80013a6 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8001392: f7ff f9d1 bl 8000738 8001396: 0002 movs r2, r0 8001398: 69bb ldr r3, [r7, #24] 800139a: 1ad3 subs r3, r2, r3 800139c: 4aaf ldr r2, [pc, #700] ; (800165c ) 800139e: 4293 cmp r3, r2 80013a0: d901 bls.n 80013a6 { return HAL_TIMEOUT; 80013a2: 2303 movs r3, #3 80013a4: e19a b.n 80016dc while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80013a6: 4bac ldr r3, [pc, #688] ; (8001658 ) 80013a8: 6a1b ldr r3, [r3, #32] 80013aa: 2202 movs r2, #2 80013ac: 4013 ands r3, r2 80013ae: d0f0 beq.n 8001392 80013b0: e013 b.n 80013da } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 80013b2: f7ff f9c1 bl 8000738 80013b6: 0003 movs r3, r0 80013b8: 61bb str r3, [r7, #24] /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80013ba: e009 b.n 80013d0 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 80013bc: f7ff f9bc bl 8000738 80013c0: 0002 movs r2, r0 80013c2: 69bb ldr r3, [r7, #24] 80013c4: 1ad3 subs r3, r2, r3 80013c6: 4aa5 ldr r2, [pc, #660] ; (800165c ) 80013c8: 4293 cmp r3, r2 80013ca: d901 bls.n 80013d0 { return HAL_TIMEOUT; 80013cc: 2303 movs r3, #3 80013ce: e185 b.n 80016dc while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80013d0: 4ba1 ldr r3, [pc, #644] ; (8001658 ) 80013d2: 6a1b ldr r3, [r3, #32] 80013d4: 2202 movs r2, #2 80013d6: 4013 ands r3, r2 80013d8: d1f0 bne.n 80013bc } } } /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) 80013da: 231f movs r3, #31 80013dc: 18fb adds r3, r7, r3 80013de: 781b ldrb r3, [r3, #0] 80013e0: 2b01 cmp r3, #1 80013e2: d105 bne.n 80013f0 { __HAL_RCC_PWR_CLK_DISABLE(); 80013e4: 4b9c ldr r3, [pc, #624] ; (8001658 ) 80013e6: 69da ldr r2, [r3, #28] 80013e8: 4b9b ldr r3, [pc, #620] ; (8001658 ) 80013ea: 499d ldr r1, [pc, #628] ; (8001660 ) 80013ec: 400a ands r2, r1 80013ee: 61da str r2, [r3, #28] } } /*----------------------------- HSI14 Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) 80013f0: 687b ldr r3, [r7, #4] 80013f2: 681b ldr r3, [r3, #0] 80013f4: 2210 movs r2, #16 80013f6: 4013 ands r3, r2 80013f8: d063 beq.n 80014c2 /* Check the parameters */ assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue)); /* Check the HSI14 State */ if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON) 80013fa: 687b ldr r3, [r7, #4] 80013fc: 695b ldr r3, [r3, #20] 80013fe: 2b01 cmp r3, #1 8001400: d12a bne.n 8001458 { /* Disable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_DISABLE(); 8001402: 4b95 ldr r3, [pc, #596] ; (8001658 ) 8001404: 6b5a ldr r2, [r3, #52] ; 0x34 8001406: 4b94 ldr r3, [pc, #592] ; (8001658 ) 8001408: 2104 movs r1, #4 800140a: 430a orrs r2, r1 800140c: 635a str r2, [r3, #52] ; 0x34 /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI14_ENABLE(); 800140e: 4b92 ldr r3, [pc, #584] ; (8001658 ) 8001410: 6b5a ldr r2, [r3, #52] ; 0x34 8001412: 4b91 ldr r3, [pc, #580] ; (8001658 ) 8001414: 2101 movs r1, #1 8001416: 430a orrs r2, r1 8001418: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 800141a: f7ff f98d bl 8000738 800141e: 0003 movs r3, r0 8001420: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) 8001422: e008 b.n 8001436 { if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) 8001424: f7ff f988 bl 8000738 8001428: 0002 movs r2, r0 800142a: 69bb ldr r3, [r7, #24] 800142c: 1ad3 subs r3, r2, r3 800142e: 2b02 cmp r3, #2 8001430: d901 bls.n 8001436 { return HAL_TIMEOUT; 8001432: 2303 movs r3, #3 8001434: e152 b.n 80016dc while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) 8001436: 4b88 ldr r3, [pc, #544] ; (8001658 ) 8001438: 6b5b ldr r3, [r3, #52] ; 0x34 800143a: 2202 movs r2, #2 800143c: 4013 ands r3, r2 800143e: d0f1 beq.n 8001424 } } /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); 8001440: 4b85 ldr r3, [pc, #532] ; (8001658 ) 8001442: 6b5b ldr r3, [r3, #52] ; 0x34 8001444: 22f8 movs r2, #248 ; 0xf8 8001446: 4393 bics r3, r2 8001448: 0019 movs r1, r3 800144a: 687b ldr r3, [r7, #4] 800144c: 699b ldr r3, [r3, #24] 800144e: 00da lsls r2, r3, #3 8001450: 4b81 ldr r3, [pc, #516] ; (8001658 ) 8001452: 430a orrs r2, r1 8001454: 635a str r2, [r3, #52] ; 0x34 8001456: e034 b.n 80014c2 } else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL) 8001458: 687b ldr r3, [r7, #4] 800145a: 695b ldr r3, [r3, #20] 800145c: 3305 adds r3, #5 800145e: d111 bne.n 8001484 { /* Enable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_ENABLE(); 8001460: 4b7d ldr r3, [pc, #500] ; (8001658 ) 8001462: 6b5a ldr r2, [r3, #52] ; 0x34 8001464: 4b7c ldr r3, [pc, #496] ; (8001658 ) 8001466: 2104 movs r1, #4 8001468: 438a bics r2, r1 800146a: 635a str r2, [r3, #52] ; 0x34 /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); 800146c: 4b7a ldr r3, [pc, #488] ; (8001658 ) 800146e: 6b5b ldr r3, [r3, #52] ; 0x34 8001470: 22f8 movs r2, #248 ; 0xf8 8001472: 4393 bics r3, r2 8001474: 0019 movs r1, r3 8001476: 687b ldr r3, [r7, #4] 8001478: 699b ldr r3, [r3, #24] 800147a: 00da lsls r2, r3, #3 800147c: 4b76 ldr r3, [pc, #472] ; (8001658 ) 800147e: 430a orrs r2, r1 8001480: 635a str r2, [r3, #52] ; 0x34 8001482: e01e b.n 80014c2 } else { /* Disable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_DISABLE(); 8001484: 4b74 ldr r3, [pc, #464] ; (8001658 ) 8001486: 6b5a ldr r2, [r3, #52] ; 0x34 8001488: 4b73 ldr r3, [pc, #460] ; (8001658 ) 800148a: 2104 movs r1, #4 800148c: 430a orrs r2, r1 800148e: 635a str r2, [r3, #52] ; 0x34 /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI14_DISABLE(); 8001490: 4b71 ldr r3, [pc, #452] ; (8001658 ) 8001492: 6b5a ldr r2, [r3, #52] ; 0x34 8001494: 4b70 ldr r3, [pc, #448] ; (8001658 ) 8001496: 2101 movs r1, #1 8001498: 438a bics r2, r1 800149a: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 800149c: f7ff f94c bl 8000738 80014a0: 0003 movs r3, r0 80014a2: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) 80014a4: e008 b.n 80014b8 { if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) 80014a6: f7ff f947 bl 8000738 80014aa: 0002 movs r2, r0 80014ac: 69bb ldr r3, [r7, #24] 80014ae: 1ad3 subs r3, r2, r3 80014b0: 2b02 cmp r3, #2 80014b2: d901 bls.n 80014b8 { return HAL_TIMEOUT; 80014b4: 2303 movs r3, #3 80014b6: e111 b.n 80016dc while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) 80014b8: 4b67 ldr r3, [pc, #412] ; (8001658 ) 80014ba: 6b5b ldr r3, [r3, #52] ; 0x34 80014bc: 2202 movs r2, #2 80014be: 4013 ands r3, r2 80014c0: d1f1 bne.n 80014a6 } } #if defined(RCC_HSI48_SUPPORT) /*----------------------------- HSI48 Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 80014c2: 687b ldr r3, [r7, #4] 80014c4: 681b ldr r3, [r3, #0] 80014c6: 2220 movs r2, #32 80014c8: 4013 ands r3, r2 80014ca: d05c beq.n 8001586 { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* When the HSI48 is used as system clock it is not allowed to be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) || 80014cc: 4b62 ldr r3, [pc, #392] ; (8001658 ) 80014ce: 685b ldr r3, [r3, #4] 80014d0: 220c movs r2, #12 80014d2: 4013 ands r3, r2 80014d4: 2b0c cmp r3, #12 80014d6: d00e beq.n 80014f6 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48))) 80014d8: 4b5f ldr r3, [pc, #380] ; (8001658 ) 80014da: 685b ldr r3, [r3, #4] 80014dc: 220c movs r2, #12 80014de: 4013 ands r3, r2 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) || 80014e0: 2b08 cmp r3, #8 80014e2: d114 bne.n 800150e ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48))) 80014e4: 4b5c ldr r3, [pc, #368] ; (8001658 ) 80014e6: 685a ldr r2, [r3, #4] 80014e8: 23c0 movs r3, #192 ; 0xc0 80014ea: 025b lsls r3, r3, #9 80014ec: 401a ands r2, r3 80014ee: 23c0 movs r3, #192 ; 0xc0 80014f0: 025b lsls r3, r3, #9 80014f2: 429a cmp r2, r3 80014f4: d10b bne.n 800150e { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON)) 80014f6: 4b58 ldr r3, [pc, #352] ; (8001658 ) 80014f8: 6b5a ldr r2, [r3, #52] ; 0x34 80014fa: 2380 movs r3, #128 ; 0x80 80014fc: 029b lsls r3, r3, #10 80014fe: 4013 ands r3, r2 8001500: d040 beq.n 8001584 8001502: 687b ldr r3, [r7, #4] 8001504: 6a1b ldr r3, [r3, #32] 8001506: 2b01 cmp r3, #1 8001508: d03c beq.n 8001584 { return HAL_ERROR; 800150a: 2301 movs r3, #1 800150c: e0e6 b.n 80016dc } } else { /* Check the HSI48 State */ if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) 800150e: 687b ldr r3, [r7, #4] 8001510: 6a1b ldr r3, [r3, #32] 8001512: 2b00 cmp r3, #0 8001514: d01b beq.n 800154e { /* Enable the Internal High Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 8001516: 4b50 ldr r3, [pc, #320] ; (8001658 ) 8001518: 6b5a ldr r2, [r3, #52] ; 0x34 800151a: 4b4f ldr r3, [pc, #316] ; (8001658 ) 800151c: 2180 movs r1, #128 ; 0x80 800151e: 0249 lsls r1, r1, #9 8001520: 430a orrs r2, r1 8001522: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001524: f7ff f908 bl 8000738 8001528: 0003 movs r3, r0 800152a: 61bb str r3, [r7, #24] /* Wait till HSI48 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) 800152c: e008 b.n 8001540 { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800152e: f7ff f903 bl 8000738 8001532: 0002 movs r2, r0 8001534: 69bb ldr r3, [r7, #24] 8001536: 1ad3 subs r3, r2, r3 8001538: 2b02 cmp r3, #2 800153a: d901 bls.n 8001540 { return HAL_TIMEOUT; 800153c: 2303 movs r3, #3 800153e: e0cd b.n 80016dc while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) 8001540: 4b45 ldr r3, [pc, #276] ; (8001658 ) 8001542: 6b5a ldr r2, [r3, #52] ; 0x34 8001544: 2380 movs r3, #128 ; 0x80 8001546: 029b lsls r3, r3, #10 8001548: 4013 ands r3, r2 800154a: d0f0 beq.n 800152e 800154c: e01b b.n 8001586 } } else { /* Disable the Internal High Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 800154e: 4b42 ldr r3, [pc, #264] ; (8001658 ) 8001550: 6b5a ldr r2, [r3, #52] ; 0x34 8001552: 4b41 ldr r3, [pc, #260] ; (8001658 ) 8001554: 4943 ldr r1, [pc, #268] ; (8001664 ) 8001556: 400a ands r2, r1 8001558: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 800155a: f7ff f8ed bl 8000738 800155e: 0003 movs r3, r0 8001560: 61bb str r3, [r7, #24] /* Wait till HSI48 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) 8001562: e008 b.n 8001576 { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 8001564: f7ff f8e8 bl 8000738 8001568: 0002 movs r2, r0 800156a: 69bb ldr r3, [r7, #24] 800156c: 1ad3 subs r3, r2, r3 800156e: 2b02 cmp r3, #2 8001570: d901 bls.n 8001576 { return HAL_TIMEOUT; 8001572: 2303 movs r3, #3 8001574: e0b2 b.n 80016dc while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) 8001576: 4b38 ldr r3, [pc, #224] ; (8001658 ) 8001578: 6b5a ldr r2, [r3, #52] ; 0x34 800157a: 2380 movs r3, #128 ; 0x80 800157c: 029b lsls r3, r3, #10 800157e: 4013 ands r3, r2 8001580: d1f0 bne.n 8001564 8001582: e000 b.n 8001586 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON)) 8001584: 46c0 nop ; (mov r8, r8) #endif /* RCC_HSI48_SUPPORT */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8001586: 687b ldr r3, [r7, #4] 8001588: 6a5b ldr r3, [r3, #36] ; 0x24 800158a: 2b00 cmp r3, #0 800158c: d100 bne.n 8001590 800158e: e0a4 b.n 80016da { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8001590: 4b31 ldr r3, [pc, #196] ; (8001658 ) 8001592: 685b ldr r3, [r3, #4] 8001594: 220c movs r2, #12 8001596: 4013 ands r3, r2 8001598: 2b08 cmp r3, #8 800159a: d100 bne.n 800159e 800159c: e078 b.n 8001690 { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 800159e: 687b ldr r3, [r7, #4] 80015a0: 6a5b ldr r3, [r3, #36] ; 0x24 80015a2: 2b02 cmp r3, #2 80015a4: d14c bne.n 8001640 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80015a6: 4b2c ldr r3, [pc, #176] ; (8001658 ) 80015a8: 681a ldr r2, [r3, #0] 80015aa: 4b2b ldr r3, [pc, #172] ; (8001658 ) 80015ac: 492e ldr r1, [pc, #184] ; (8001668 ) 80015ae: 400a ands r2, r1 80015b0: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80015b2: f7ff f8c1 bl 8000738 80015b6: 0003 movs r3, r0 80015b8: 61bb str r3, [r7, #24] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80015ba: e008 b.n 80015ce { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 80015bc: f7ff f8bc bl 8000738 80015c0: 0002 movs r2, r0 80015c2: 69bb ldr r3, [r7, #24] 80015c4: 1ad3 subs r3, r2, r3 80015c6: 2b02 cmp r3, #2 80015c8: d901 bls.n 80015ce { return HAL_TIMEOUT; 80015ca: 2303 movs r3, #3 80015cc: e086 b.n 80016dc while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80015ce: 4b22 ldr r3, [pc, #136] ; (8001658 ) 80015d0: 681a ldr r2, [r3, #0] 80015d2: 2380 movs r3, #128 ; 0x80 80015d4: 049b lsls r3, r3, #18 80015d6: 4013 ands r3, r2 80015d8: d1f0 bne.n 80015bc } } /* Configure the main PLL clock source, predivider and multiplication factor. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80015da: 4b1f ldr r3, [pc, #124] ; (8001658 ) 80015dc: 6adb ldr r3, [r3, #44] ; 0x2c 80015de: 220f movs r2, #15 80015e0: 4393 bics r3, r2 80015e2: 0019 movs r1, r3 80015e4: 687b ldr r3, [r7, #4] 80015e6: 6b1a ldr r2, [r3, #48] ; 0x30 80015e8: 4b1b ldr r3, [pc, #108] ; (8001658 ) 80015ea: 430a orrs r2, r1 80015ec: 62da str r2, [r3, #44] ; 0x2c 80015ee: 4b1a ldr r3, [pc, #104] ; (8001658 ) 80015f0: 685b ldr r3, [r3, #4] 80015f2: 4a1e ldr r2, [pc, #120] ; (800166c ) 80015f4: 4013 ands r3, r2 80015f6: 0019 movs r1, r3 80015f8: 687b ldr r3, [r7, #4] 80015fa: 6ada ldr r2, [r3, #44] ; 0x2c 80015fc: 687b ldr r3, [r7, #4] 80015fe: 6a9b ldr r3, [r3, #40] ; 0x28 8001600: 431a orrs r2, r3 8001602: 4b15 ldr r3, [pc, #84] ; (8001658 ) 8001604: 430a orrs r2, r1 8001606: 605a str r2, [r3, #4] RCC_OscInitStruct->PLL.PREDIV, RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8001608: 4b13 ldr r3, [pc, #76] ; (8001658 ) 800160a: 681a ldr r2, [r3, #0] 800160c: 4b12 ldr r3, [pc, #72] ; (8001658 ) 800160e: 2180 movs r1, #128 ; 0x80 8001610: 0449 lsls r1, r1, #17 8001612: 430a orrs r2, r1 8001614: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001616: f7ff f88f bl 8000738 800161a: 0003 movs r3, r0 800161c: 61bb str r3, [r7, #24] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800161e: e008 b.n 8001632 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001620: f7ff f88a bl 8000738 8001624: 0002 movs r2, r0 8001626: 69bb ldr r3, [r7, #24] 8001628: 1ad3 subs r3, r2, r3 800162a: 2b02 cmp r3, #2 800162c: d901 bls.n 8001632 { return HAL_TIMEOUT; 800162e: 2303 movs r3, #3 8001630: e054 b.n 80016dc while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001632: 4b09 ldr r3, [pc, #36] ; (8001658 ) 8001634: 681a ldr r2, [r3, #0] 8001636: 2380 movs r3, #128 ; 0x80 8001638: 049b lsls r3, r3, #18 800163a: 4013 ands r3, r2 800163c: d0f0 beq.n 8001620 800163e: e04c b.n 80016da } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8001640: 4b05 ldr r3, [pc, #20] ; (8001658 ) 8001642: 681a ldr r2, [r3, #0] 8001644: 4b04 ldr r3, [pc, #16] ; (8001658 ) 8001646: 4908 ldr r1, [pc, #32] ; (8001668 ) 8001648: 400a ands r2, r1 800164a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800164c: f7ff f874 bl 8000738 8001650: 0003 movs r3, r0 8001652: 61bb str r3, [r7, #24] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001654: e015 b.n 8001682 8001656: 46c0 nop ; (mov r8, r8) 8001658: 40021000 .word 0x40021000 800165c: 00001388 .word 0x00001388 8001660: efffffff .word 0xefffffff 8001664: fffeffff .word 0xfffeffff 8001668: feffffff .word 0xfeffffff 800166c: ffc27fff .word 0xffc27fff { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001670: f7ff f862 bl 8000738 8001674: 0002 movs r2, r0 8001676: 69bb ldr r3, [r7, #24] 8001678: 1ad3 subs r3, r2, r3 800167a: 2b02 cmp r3, #2 800167c: d901 bls.n 8001682 { return HAL_TIMEOUT; 800167e: 2303 movs r3, #3 8001680: e02c b.n 80016dc while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001682: 4b18 ldr r3, [pc, #96] ; (80016e4 ) 8001684: 681a ldr r2, [r3, #0] 8001686: 2380 movs r3, #128 ; 0x80 8001688: 049b lsls r3, r3, #18 800168a: 4013 ands r3, r2 800168c: d1f0 bne.n 8001670 800168e: e024 b.n 80016da } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8001690: 687b ldr r3, [r7, #4] 8001692: 6a5b ldr r3, [r3, #36] ; 0x24 8001694: 2b01 cmp r3, #1 8001696: d101 bne.n 800169c { return HAL_ERROR; 8001698: 2301 movs r3, #1 800169a: e01f b.n 80016dc } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 800169c: 4b11 ldr r3, [pc, #68] ; (80016e4 ) 800169e: 685b ldr r3, [r3, #4] 80016a0: 617b str r3, [r7, #20] pll_config2 = RCC->CFGR2; 80016a2: 4b10 ldr r3, [pc, #64] ; (80016e4 ) 80016a4: 6adb ldr r3, [r3, #44] ; 0x2c 80016a6: 613b str r3, [r7, #16] if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80016a8: 697a ldr r2, [r7, #20] 80016aa: 23c0 movs r3, #192 ; 0xc0 80016ac: 025b lsls r3, r3, #9 80016ae: 401a ands r2, r3 80016b0: 687b ldr r3, [r7, #4] 80016b2: 6a9b ldr r3, [r3, #40] ; 0x28 80016b4: 429a cmp r2, r3 80016b6: d10e bne.n 80016d6 (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || 80016b8: 693b ldr r3, [r7, #16] 80016ba: 220f movs r2, #15 80016bc: 401a ands r2, r3 80016be: 687b ldr r3, [r7, #4] 80016c0: 6b1b ldr r3, [r3, #48] ; 0x30 if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80016c2: 429a cmp r2, r3 80016c4: d107 bne.n 80016d6 (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) 80016c6: 697a ldr r2, [r7, #20] 80016c8: 23f0 movs r3, #240 ; 0xf0 80016ca: 039b lsls r3, r3, #14 80016cc: 401a ands r2, r3 80016ce: 687b ldr r3, [r7, #4] 80016d0: 6adb ldr r3, [r3, #44] ; 0x2c (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || 80016d2: 429a cmp r2, r3 80016d4: d001 beq.n 80016da { return HAL_ERROR; 80016d6: 2301 movs r3, #1 80016d8: e000 b.n 80016dc } } } } return HAL_OK; 80016da: 2300 movs r3, #0 } 80016dc: 0018 movs r0, r3 80016de: 46bd mov sp, r7 80016e0: b008 add sp, #32 80016e2: bd80 pop {r7, pc} 80016e4: 40021000 .word 0x40021000 080016e8 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 80016e8: b580 push {r7, lr} 80016ea: b084 sub sp, #16 80016ec: af00 add r7, sp, #0 80016ee: 6078 str r0, [r7, #4] 80016f0: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) 80016f2: 687b ldr r3, [r7, #4] 80016f4: 2b00 cmp r3, #0 80016f6: d101 bne.n 80016fc { return HAL_ERROR; 80016f8: 2301 movs r3, #1 80016fa: e0bf b.n 800187c /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 80016fc: 4b61 ldr r3, [pc, #388] ; (8001884 ) 80016fe: 681b ldr r3, [r3, #0] 8001700: 2201 movs r2, #1 8001702: 4013 ands r3, r2 8001704: 683a ldr r2, [r7, #0] 8001706: 429a cmp r2, r3 8001708: d911 bls.n 800172e { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800170a: 4b5e ldr r3, [pc, #376] ; (8001884 ) 800170c: 681b ldr r3, [r3, #0] 800170e: 2201 movs r2, #1 8001710: 4393 bics r3, r2 8001712: 0019 movs r1, r3 8001714: 4b5b ldr r3, [pc, #364] ; (8001884 ) 8001716: 683a ldr r2, [r7, #0] 8001718: 430a orrs r2, r1 800171a: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 800171c: 4b59 ldr r3, [pc, #356] ; (8001884 ) 800171e: 681b ldr r3, [r3, #0] 8001720: 2201 movs r2, #1 8001722: 4013 ands r3, r2 8001724: 683a ldr r2, [r7, #0] 8001726: 429a cmp r2, r3 8001728: d001 beq.n 800172e { return HAL_ERROR; 800172a: 2301 movs r3, #1 800172c: e0a6 b.n 800187c } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800172e: 687b ldr r3, [r7, #4] 8001730: 681b ldr r3, [r3, #0] 8001732: 2202 movs r2, #2 8001734: 4013 ands r3, r2 8001736: d015 beq.n 8001764 { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8001738: 687b ldr r3, [r7, #4] 800173a: 681b ldr r3, [r3, #0] 800173c: 2204 movs r2, #4 800173e: 4013 ands r3, r2 8001740: d006 beq.n 8001750 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); 8001742: 4b51 ldr r3, [pc, #324] ; (8001888 ) 8001744: 685a ldr r2, [r3, #4] 8001746: 4b50 ldr r3, [pc, #320] ; (8001888 ) 8001748: 21e0 movs r1, #224 ; 0xe0 800174a: 00c9 lsls r1, r1, #3 800174c: 430a orrs r2, r1 800174e: 605a str r2, [r3, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8001750: 4b4d ldr r3, [pc, #308] ; (8001888 ) 8001752: 685b ldr r3, [r3, #4] 8001754: 22f0 movs r2, #240 ; 0xf0 8001756: 4393 bics r3, r2 8001758: 0019 movs r1, r3 800175a: 687b ldr r3, [r7, #4] 800175c: 689a ldr r2, [r3, #8] 800175e: 4b4a ldr r3, [pc, #296] ; (8001888 ) 8001760: 430a orrs r2, r1 8001762: 605a str r2, [r3, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8001764: 687b ldr r3, [r7, #4] 8001766: 681b ldr r3, [r3, #0] 8001768: 2201 movs r2, #1 800176a: 4013 ands r3, r2 800176c: d04c beq.n 8001808 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 800176e: 687b ldr r3, [r7, #4] 8001770: 685b ldr r3, [r3, #4] 8001772: 2b01 cmp r3, #1 8001774: d107 bne.n 8001786 { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001776: 4b44 ldr r3, [pc, #272] ; (8001888 ) 8001778: 681a ldr r2, [r3, #0] 800177a: 2380 movs r3, #128 ; 0x80 800177c: 029b lsls r3, r3, #10 800177e: 4013 ands r3, r2 8001780: d120 bne.n 80017c4 { return HAL_ERROR; 8001782: 2301 movs r3, #1 8001784: e07a b.n 800187c } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8001786: 687b ldr r3, [r7, #4] 8001788: 685b ldr r3, [r3, #4] 800178a: 2b02 cmp r3, #2 800178c: d107 bne.n 800179e { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800178e: 4b3e ldr r3, [pc, #248] ; (8001888 ) 8001790: 681a ldr r2, [r3, #0] 8001792: 2380 movs r3, #128 ; 0x80 8001794: 049b lsls r3, r3, #18 8001796: 4013 ands r3, r2 8001798: d114 bne.n 80017c4 { return HAL_ERROR; 800179a: 2301 movs r3, #1 800179c: e06e b.n 800187c } } #if defined(RCC_CFGR_SWS_HSI48) /* HSI48 is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) 800179e: 687b ldr r3, [r7, #4] 80017a0: 685b ldr r3, [r3, #4] 80017a2: 2b03 cmp r3, #3 80017a4: d107 bne.n 80017b6 { /* Check the HSI48 ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) 80017a6: 4b38 ldr r3, [pc, #224] ; (8001888 ) 80017a8: 6b5a ldr r2, [r3, #52] ; 0x34 80017aa: 2380 movs r3, #128 ; 0x80 80017ac: 029b lsls r3, r3, #10 80017ae: 4013 ands r3, r2 80017b0: d108 bne.n 80017c4 { return HAL_ERROR; 80017b2: 2301 movs r3, #1 80017b4: e062 b.n 800187c #endif /* RCC_CFGR_SWS_HSI48 */ /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80017b6: 4b34 ldr r3, [pc, #208] ; (8001888 ) 80017b8: 681b ldr r3, [r3, #0] 80017ba: 2202 movs r2, #2 80017bc: 4013 ands r3, r2 80017be: d101 bne.n 80017c4 { return HAL_ERROR; 80017c0: 2301 movs r3, #1 80017c2: e05b b.n 800187c } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 80017c4: 4b30 ldr r3, [pc, #192] ; (8001888 ) 80017c6: 685b ldr r3, [r3, #4] 80017c8: 2203 movs r2, #3 80017ca: 4393 bics r3, r2 80017cc: 0019 movs r1, r3 80017ce: 687b ldr r3, [r7, #4] 80017d0: 685a ldr r2, [r3, #4] 80017d2: 4b2d ldr r3, [pc, #180] ; (8001888 ) 80017d4: 430a orrs r2, r1 80017d6: 605a str r2, [r3, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 80017d8: f7fe ffae bl 8000738 80017dc: 0003 movs r3, r0 80017de: 60fb str r3, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80017e0: e009 b.n 80017f6 { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 80017e2: f7fe ffa9 bl 8000738 80017e6: 0002 movs r2, r0 80017e8: 68fb ldr r3, [r7, #12] 80017ea: 1ad3 subs r3, r2, r3 80017ec: 4a27 ldr r2, [pc, #156] ; (800188c ) 80017ee: 4293 cmp r3, r2 80017f0: d901 bls.n 80017f6 { return HAL_TIMEOUT; 80017f2: 2303 movs r3, #3 80017f4: e042 b.n 800187c while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80017f6: 4b24 ldr r3, [pc, #144] ; (8001888 ) 80017f8: 685b ldr r3, [r3, #4] 80017fa: 220c movs r2, #12 80017fc: 401a ands r2, r3 80017fe: 687b ldr r3, [r7, #4] 8001800: 685b ldr r3, [r3, #4] 8001802: 009b lsls r3, r3, #2 8001804: 429a cmp r2, r3 8001806: d1ec bne.n 80017e2 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 8001808: 4b1e ldr r3, [pc, #120] ; (8001884 ) 800180a: 681b ldr r3, [r3, #0] 800180c: 2201 movs r2, #1 800180e: 4013 ands r3, r2 8001810: 683a ldr r2, [r7, #0] 8001812: 429a cmp r2, r3 8001814: d211 bcs.n 800183a { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8001816: 4b1b ldr r3, [pc, #108] ; (8001884 ) 8001818: 681b ldr r3, [r3, #0] 800181a: 2201 movs r2, #1 800181c: 4393 bics r3, r2 800181e: 0019 movs r1, r3 8001820: 4b18 ldr r3, [pc, #96] ; (8001884 ) 8001822: 683a ldr r2, [r7, #0] 8001824: 430a orrs r2, r1 8001826: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8001828: 4b16 ldr r3, [pc, #88] ; (8001884 ) 800182a: 681b ldr r3, [r3, #0] 800182c: 2201 movs r2, #1 800182e: 4013 ands r3, r2 8001830: 683a ldr r2, [r7, #0] 8001832: 429a cmp r2, r3 8001834: d001 beq.n 800183a { return HAL_ERROR; 8001836: 2301 movs r3, #1 8001838: e020 b.n 800187c } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800183a: 687b ldr r3, [r7, #4] 800183c: 681b ldr r3, [r3, #0] 800183e: 2204 movs r2, #4 8001840: 4013 ands r3, r2 8001842: d009 beq.n 8001858 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); 8001844: 4b10 ldr r3, [pc, #64] ; (8001888 ) 8001846: 685b ldr r3, [r3, #4] 8001848: 4a11 ldr r2, [pc, #68] ; (8001890 ) 800184a: 4013 ands r3, r2 800184c: 0019 movs r1, r3 800184e: 687b ldr r3, [r7, #4] 8001850: 68da ldr r2, [r3, #12] 8001852: 4b0d ldr r3, [pc, #52] ; (8001888 ) 8001854: 430a orrs r2, r1 8001856: 605a str r2, [r3, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; 8001858: f000 f820 bl 800189c 800185c: 0001 movs r1, r0 800185e: 4b0a ldr r3, [pc, #40] ; (8001888 ) 8001860: 685b ldr r3, [r3, #4] 8001862: 091b lsrs r3, r3, #4 8001864: 220f movs r2, #15 8001866: 4013 ands r3, r2 8001868: 4a0a ldr r2, [pc, #40] ; (8001894 ) 800186a: 5cd3 ldrb r3, [r2, r3] 800186c: 000a movs r2, r1 800186e: 40da lsrs r2, r3 8001870: 4b09 ldr r3, [pc, #36] ; (8001898 ) 8001872: 601a str r2, [r3, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); 8001874: 2003 movs r0, #3 8001876: f7fe ff19 bl 80006ac return HAL_OK; 800187a: 2300 movs r3, #0 } 800187c: 0018 movs r0, r3 800187e: 46bd mov sp, r7 8001880: b004 add sp, #16 8001882: bd80 pop {r7, pc} 8001884: 40022000 .word 0x40022000 8001888: 40021000 .word 0x40021000 800188c: 00001388 .word 0x00001388 8001890: fffff8ff .word 0xfffff8ff 8001894: 08001bcc .word 0x08001bcc 8001898: 20000000 .word 0x20000000 0800189c : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 800189c: b580 push {r7, lr} 800189e: b086 sub sp, #24 80018a0: af00 add r7, sp, #0 static const uint8_t aPLLMULFactorTable[16U] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; static const uint8_t aPredivFactorTable[16U] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 80018a2: 2300 movs r3, #0 80018a4: 60fb str r3, [r7, #12] 80018a6: 2300 movs r3, #0 80018a8: 60bb str r3, [r7, #8] 80018aa: 2300 movs r3, #0 80018ac: 617b str r3, [r7, #20] 80018ae: 2300 movs r3, #0 80018b0: 607b str r3, [r7, #4] uint32_t sysclockfreq = 0U; 80018b2: 2300 movs r3, #0 80018b4: 613b str r3, [r7, #16] tmpreg = RCC->CFGR; 80018b6: 4b2d ldr r3, [pc, #180] ; (800196c ) 80018b8: 685b ldr r3, [r3, #4] 80018ba: 60fb str r3, [r7, #12] /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 80018bc: 68fb ldr r3, [r7, #12] 80018be: 220c movs r2, #12 80018c0: 4013 ands r3, r2 80018c2: 2b0c cmp r3, #12 80018c4: d046 beq.n 8001954 80018c6: d848 bhi.n 800195a 80018c8: 2b04 cmp r3, #4 80018ca: d002 beq.n 80018d2 80018cc: 2b08 cmp r3, #8 80018ce: d003 beq.n 80018d8 80018d0: e043 b.n 800195a { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 80018d2: 4b27 ldr r3, [pc, #156] ; (8001970 ) 80018d4: 613b str r3, [r7, #16] break; 80018d6: e043 b.n 8001960 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER]; 80018d8: 68fb ldr r3, [r7, #12] 80018da: 0c9b lsrs r3, r3, #18 80018dc: 220f movs r2, #15 80018de: 4013 ands r3, r2 80018e0: 4a24 ldr r2, [pc, #144] ; (8001974 ) 80018e2: 5cd3 ldrb r3, [r2, r3] 80018e4: 607b str r3, [r7, #4] prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER]; 80018e6: 4b21 ldr r3, [pc, #132] ; (800196c ) 80018e8: 6adb ldr r3, [r3, #44] ; 0x2c 80018ea: 220f movs r2, #15 80018ec: 4013 ands r3, r2 80018ee: 4a22 ldr r2, [pc, #136] ; (8001978 ) 80018f0: 5cd3 ldrb r3, [r2, r3] 80018f2: 60bb str r3, [r7, #8] if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE) 80018f4: 68fa ldr r2, [r7, #12] 80018f6: 23c0 movs r3, #192 ; 0xc0 80018f8: 025b lsls r3, r3, #9 80018fa: 401a ands r2, r3 80018fc: 2380 movs r3, #128 ; 0x80 80018fe: 025b lsls r3, r3, #9 8001900: 429a cmp r2, r3 8001902: d109 bne.n 8001918 { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); 8001904: 68b9 ldr r1, [r7, #8] 8001906: 481a ldr r0, [pc, #104] ; (8001970 ) 8001908: f7fe fbfe bl 8000108 <__udivsi3> 800190c: 0003 movs r3, r0 800190e: 001a movs r2, r3 8001910: 687b ldr r3, [r7, #4] 8001912: 4353 muls r3, r2 8001914: 617b str r3, [r7, #20] 8001916: e01a b.n 800194e } #if defined(RCC_CFGR_PLLSRC_HSI48_PREDIV) else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48) 8001918: 68fa ldr r2, [r7, #12] 800191a: 23c0 movs r3, #192 ; 0xc0 800191c: 025b lsls r3, r3, #9 800191e: 401a ands r2, r3 8001920: 23c0 movs r3, #192 ; 0xc0 8001922: 025b lsls r3, r3, #9 8001924: 429a cmp r2, r3 8001926: d109 bne.n 800193c { /* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSI48_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); 8001928: 68b9 ldr r1, [r7, #8] 800192a: 4814 ldr r0, [pc, #80] ; (800197c ) 800192c: f7fe fbec bl 8000108 <__udivsi3> 8001930: 0003 movs r3, r0 8001932: 001a movs r2, r3 8001934: 687b ldr r3, [r7, #4] 8001936: 4353 muls r3, r2 8001938: 617b str r3, [r7, #20] 800193a: e008 b.n 800194e #endif /* RCC_CFGR_PLLSRC_HSI48_PREDIV */ else { #if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)) /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); 800193c: 68b9 ldr r1, [r7, #8] 800193e: 480c ldr r0, [pc, #48] ; (8001970 ) 8001940: f7fe fbe2 bl 8000108 <__udivsi3> 8001944: 0003 movs r3, r0 8001946: 001a movs r2, r3 8001948: 687b ldr r3, [r7, #4] 800194a: 4353 muls r3, r2 800194c: 617b str r3, [r7, #20] #else /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); #endif } sysclockfreq = pllclk; 800194e: 697b ldr r3, [r7, #20] 8001950: 613b str r3, [r7, #16] break; 8001952: e005 b.n 8001960 } #if defined(RCC_CFGR_SWS_HSI48) case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */ { sysclockfreq = HSI48_VALUE; 8001954: 4b09 ldr r3, [pc, #36] ; (800197c ) 8001956: 613b str r3, [r7, #16] break; 8001958: e002 b.n 8001960 } #endif /* RCC_CFGR_SWS_HSI48 */ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 800195a: 4b05 ldr r3, [pc, #20] ; (8001970 ) 800195c: 613b str r3, [r7, #16] break; 800195e: 46c0 nop ; (mov r8, r8) } } return sysclockfreq; 8001960: 693b ldr r3, [r7, #16] } 8001962: 0018 movs r0, r3 8001964: 46bd mov sp, r7 8001966: b006 add sp, #24 8001968: bd80 pop {r7, pc} 800196a: 46c0 nop ; (mov r8, r8) 800196c: 40021000 .word 0x40021000 8001970: 007a1200 .word 0x007a1200 8001974: 08001bdc .word 0x08001bdc 8001978: 08001bec .word 0x08001bec 800197c: 02dc6c00 .word 0x02dc6c00 08001980 : * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8001980: b580 push {r7, lr} 8001982: b086 sub sp, #24 8001984: af00 add r7, sp, #0 8001986: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8001988: 2300 movs r3, #0 800198a: 613b str r3, [r7, #16] uint32_t temp_reg = 0U; 800198c: 2300 movs r3, #0 800198e: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*---------------------------- RTC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) 8001990: 687b ldr r3, [r7, #4] 8001992: 681a ldr r2, [r3, #0] 8001994: 2380 movs r3, #128 ; 0x80 8001996: 025b lsls r3, r3, #9 8001998: 4013 ands r3, r2 800199a: d100 bne.n 800199e 800199c: e08e b.n 8001abc { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); FlagStatus pwrclkchanged = RESET; 800199e: 2017 movs r0, #23 80019a0: 183b adds r3, r7, r0 80019a2: 2200 movs r2, #0 80019a4: 701a strb r2, [r3, #0] /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 80019a6: 4b67 ldr r3, [pc, #412] ; (8001b44 ) 80019a8: 69da ldr r2, [r3, #28] 80019aa: 2380 movs r3, #128 ; 0x80 80019ac: 055b lsls r3, r3, #21 80019ae: 4013 ands r3, r2 80019b0: d110 bne.n 80019d4 { __HAL_RCC_PWR_CLK_ENABLE(); 80019b2: 4b64 ldr r3, [pc, #400] ; (8001b44 ) 80019b4: 69da ldr r2, [r3, #28] 80019b6: 4b63 ldr r3, [pc, #396] ; (8001b44 ) 80019b8: 2180 movs r1, #128 ; 0x80 80019ba: 0549 lsls r1, r1, #21 80019bc: 430a orrs r2, r1 80019be: 61da str r2, [r3, #28] 80019c0: 4b60 ldr r3, [pc, #384] ; (8001b44 ) 80019c2: 69da ldr r2, [r3, #28] 80019c4: 2380 movs r3, #128 ; 0x80 80019c6: 055b lsls r3, r3, #21 80019c8: 4013 ands r3, r2 80019ca: 60bb str r3, [r7, #8] 80019cc: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 80019ce: 183b adds r3, r7, r0 80019d0: 2201 movs r2, #1 80019d2: 701a strb r2, [r3, #0] } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80019d4: 4b5c ldr r3, [pc, #368] ; (8001b48 ) 80019d6: 681a ldr r2, [r3, #0] 80019d8: 2380 movs r3, #128 ; 0x80 80019da: 005b lsls r3, r3, #1 80019dc: 4013 ands r3, r2 80019de: d11a bne.n 8001a16 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 80019e0: 4b59 ldr r3, [pc, #356] ; (8001b48 ) 80019e2: 681a ldr r2, [r3, #0] 80019e4: 4b58 ldr r3, [pc, #352] ; (8001b48 ) 80019e6: 2180 movs r1, #128 ; 0x80 80019e8: 0049 lsls r1, r1, #1 80019ea: 430a orrs r2, r1 80019ec: 601a str r2, [r3, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80019ee: f7fe fea3 bl 8000738 80019f2: 0003 movs r3, r0 80019f4: 613b str r3, [r7, #16] while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80019f6: e008 b.n 8001a0a { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80019f8: f7fe fe9e bl 8000738 80019fc: 0002 movs r2, r0 80019fe: 693b ldr r3, [r7, #16] 8001a00: 1ad3 subs r3, r2, r3 8001a02: 2b64 cmp r3, #100 ; 0x64 8001a04: d901 bls.n 8001a0a { return HAL_TIMEOUT; 8001a06: 2303 movs r3, #3 8001a08: e097 b.n 8001b3a while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001a0a: 4b4f ldr r3, [pc, #316] ; (8001b48 ) 8001a0c: 681a ldr r2, [r3, #0] 8001a0e: 2380 movs r3, #128 ; 0x80 8001a10: 005b lsls r3, r3, #1 8001a12: 4013 ands r3, r2 8001a14: d0f0 beq.n 80019f8 } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 8001a16: 4b4b ldr r3, [pc, #300] ; (8001b44 ) 8001a18: 6a1a ldr r2, [r3, #32] 8001a1a: 23c0 movs r3, #192 ; 0xc0 8001a1c: 009b lsls r3, r3, #2 8001a1e: 4013 ands r3, r2 8001a20: 60fb str r3, [r7, #12] if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8001a22: 68fb ldr r3, [r7, #12] 8001a24: 2b00 cmp r3, #0 8001a26: d034 beq.n 8001a92 8001a28: 687b ldr r3, [r7, #4] 8001a2a: 685a ldr r2, [r3, #4] 8001a2c: 23c0 movs r3, #192 ; 0xc0 8001a2e: 009b lsls r3, r3, #2 8001a30: 4013 ands r3, r2 8001a32: 68fa ldr r2, [r7, #12] 8001a34: 429a cmp r2, r3 8001a36: d02c beq.n 8001a92 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8001a38: 4b42 ldr r3, [pc, #264] ; (8001b44 ) 8001a3a: 6a1b ldr r3, [r3, #32] 8001a3c: 4a43 ldr r2, [pc, #268] ; (8001b4c ) 8001a3e: 4013 ands r3, r2 8001a40: 60fb str r3, [r7, #12] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8001a42: 4b40 ldr r3, [pc, #256] ; (8001b44 ) 8001a44: 6a1a ldr r2, [r3, #32] 8001a46: 4b3f ldr r3, [pc, #252] ; (8001b44 ) 8001a48: 2180 movs r1, #128 ; 0x80 8001a4a: 0249 lsls r1, r1, #9 8001a4c: 430a orrs r2, r1 8001a4e: 621a str r2, [r3, #32] __HAL_RCC_BACKUPRESET_RELEASE(); 8001a50: 4b3c ldr r3, [pc, #240] ; (8001b44 ) 8001a52: 6a1a ldr r2, [r3, #32] 8001a54: 4b3b ldr r3, [pc, #236] ; (8001b44 ) 8001a56: 493e ldr r1, [pc, #248] ; (8001b50 ) 8001a58: 400a ands r2, r1 8001a5a: 621a str r2, [r3, #32] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 8001a5c: 4b39 ldr r3, [pc, #228] ; (8001b44 ) 8001a5e: 68fa ldr r2, [r7, #12] 8001a60: 621a str r2, [r3, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8001a62: 68fb ldr r3, [r7, #12] 8001a64: 2201 movs r2, #1 8001a66: 4013 ands r3, r2 8001a68: d013 beq.n 8001a92 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001a6a: f7fe fe65 bl 8000738 8001a6e: 0003 movs r3, r0 8001a70: 613b str r3, [r7, #16] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8001a72: e009 b.n 8001a88 { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8001a74: f7fe fe60 bl 8000738 8001a78: 0002 movs r2, r0 8001a7a: 693b ldr r3, [r7, #16] 8001a7c: 1ad3 subs r3, r2, r3 8001a7e: 4a35 ldr r2, [pc, #212] ; (8001b54 ) 8001a80: 4293 cmp r3, r2 8001a82: d901 bls.n 8001a88 { return HAL_TIMEOUT; 8001a84: 2303 movs r3, #3 8001a86: e058 b.n 8001b3a while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8001a88: 4b2e ldr r3, [pc, #184] ; (8001b44 ) 8001a8a: 6a1b ldr r3, [r3, #32] 8001a8c: 2202 movs r2, #2 8001a8e: 4013 ands r3, r2 8001a90: d0f0 beq.n 8001a74 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8001a92: 4b2c ldr r3, [pc, #176] ; (8001b44 ) 8001a94: 6a1b ldr r3, [r3, #32] 8001a96: 4a2d ldr r2, [pc, #180] ; (8001b4c ) 8001a98: 4013 ands r3, r2 8001a9a: 0019 movs r1, r3 8001a9c: 687b ldr r3, [r7, #4] 8001a9e: 685a ldr r2, [r3, #4] 8001aa0: 4b28 ldr r3, [pc, #160] ; (8001b44 ) 8001aa2: 430a orrs r2, r1 8001aa4: 621a str r2, [r3, #32] /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) 8001aa6: 2317 movs r3, #23 8001aa8: 18fb adds r3, r7, r3 8001aaa: 781b ldrb r3, [r3, #0] 8001aac: 2b01 cmp r3, #1 8001aae: d105 bne.n 8001abc { __HAL_RCC_PWR_CLK_DISABLE(); 8001ab0: 4b24 ldr r3, [pc, #144] ; (8001b44 ) 8001ab2: 69da ldr r2, [r3, #28] 8001ab4: 4b23 ldr r3, [pc, #140] ; (8001b44 ) 8001ab6: 4928 ldr r1, [pc, #160] ; (8001b58 ) 8001ab8: 400a ands r2, r1 8001aba: 61da str r2, [r3, #28] } } /*------------------------------- USART1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 8001abc: 687b ldr r3, [r7, #4] 8001abe: 681b ldr r3, [r3, #0] 8001ac0: 2201 movs r2, #1 8001ac2: 4013 ands r3, r2 8001ac4: d009 beq.n 8001ada { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 8001ac6: 4b1f ldr r3, [pc, #124] ; (8001b44 ) 8001ac8: 6b1b ldr r3, [r3, #48] ; 0x30 8001aca: 2203 movs r2, #3 8001acc: 4393 bics r3, r2 8001ace: 0019 movs r1, r3 8001ad0: 687b ldr r3, [r7, #4] 8001ad2: 689a ldr r2, [r3, #8] 8001ad4: 4b1b ldr r3, [pc, #108] ; (8001b44 ) 8001ad6: 430a orrs r2, r1 8001ad8: 631a str r2, [r3, #48] ; 0x30 __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); } #endif /* STM32F091xC || STM32F098xx */ /*------------------------------ I2C1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 8001ada: 687b ldr r3, [r7, #4] 8001adc: 681b ldr r3, [r3, #0] 8001ade: 2220 movs r2, #32 8001ae0: 4013 ands r3, r2 8001ae2: d009 beq.n 8001af8 { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 8001ae4: 4b17 ldr r3, [pc, #92] ; (8001b44 ) 8001ae6: 6b1b ldr r3, [r3, #48] ; 0x30 8001ae8: 2210 movs r2, #16 8001aea: 4393 bics r3, r2 8001aec: 0019 movs r1, r3 8001aee: 687b ldr r3, [r7, #4] 8001af0: 68da ldr r2, [r3, #12] 8001af2: 4b14 ldr r3, [pc, #80] ; (8001b44 ) 8001af4: 430a orrs r2, r1 8001af6: 631a str r2, [r3, #48] ; 0x30 } #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6) /*------------------------------ USB Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 8001af8: 687b ldr r3, [r7, #4] 8001afa: 681a ldr r2, [r3, #0] 8001afc: 2380 movs r3, #128 ; 0x80 8001afe: 029b lsls r3, r3, #10 8001b00: 4013 ands r3, r2 8001b02: d009 beq.n 8001b18 { /* Check the parameters */ assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8001b04: 4b0f ldr r3, [pc, #60] ; (8001b44 ) 8001b06: 6b1b ldr r3, [r3, #48] ; 0x30 8001b08: 2280 movs r2, #128 ; 0x80 8001b0a: 4393 bics r3, r2 8001b0c: 0019 movs r1, r3 8001b0e: 687b ldr r3, [r7, #4] 8001b10: 695a ldr r2, [r3, #20] 8001b12: 4b0c ldr r3, [pc, #48] ; (8001b44 ) 8001b14: 430a orrs r2, r1 8001b16: 631a str r2, [r3, #48] ; 0x30 #if defined(STM32F042x6) || defined(STM32F048xx)\ || defined(STM32F051x8) || defined(STM32F058xx)\ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ || defined(STM32F091xC) || defined(STM32F098xx) /*------------------------------ CEC clock Configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 8001b18: 687b ldr r3, [r7, #4] 8001b1a: 681a ldr r2, [r3, #0] 8001b1c: 2380 movs r3, #128 ; 0x80 8001b1e: 00db lsls r3, r3, #3 8001b20: 4013 ands r3, r2 8001b22: d009 beq.n 8001b38 { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 8001b24: 4b07 ldr r3, [pc, #28] ; (8001b44 ) 8001b26: 6b1b ldr r3, [r3, #48] ; 0x30 8001b28: 2240 movs r2, #64 ; 0x40 8001b2a: 4393 bics r3, r2 8001b2c: 0019 movs r1, r3 8001b2e: 687b ldr r3, [r7, #4] 8001b30: 691a ldr r2, [r3, #16] 8001b32: 4b04 ldr r3, [pc, #16] ; (8001b44 ) 8001b34: 430a orrs r2, r1 8001b36: 631a str r2, [r3, #48] ; 0x30 #endif /* STM32F042x6 || STM32F048xx || */ /* STM32F051x8 || STM32F058xx || */ /* STM32F071xB || STM32F072xB || STM32F078xx || */ /* STM32F091xC || STM32F098xx */ return HAL_OK; 8001b38: 2300 movs r3, #0 } 8001b3a: 0018 movs r0, r3 8001b3c: 46bd mov sp, r7 8001b3e: b006 add sp, #24 8001b40: bd80 pop {r7, pc} 8001b42: 46c0 nop ; (mov r8, r8) 8001b44: 40021000 .word 0x40021000 8001b48: 40007000 .word 0x40007000 8001b4c: fffffcff .word 0xfffffcff 8001b50: fffeffff .word 0xfffeffff 8001b54: 00001388 .word 0x00001388 8001b58: efffffff .word 0xefffffff 08001b5c <__libc_init_array>: 8001b5c: b570 push {r4, r5, r6, lr} 8001b5e: 2600 movs r6, #0 8001b60: 4d0c ldr r5, [pc, #48] ; (8001b94 <__libc_init_array+0x38>) 8001b62: 4c0d ldr r4, [pc, #52] ; (8001b98 <__libc_init_array+0x3c>) 8001b64: 1b64 subs r4, r4, r5 8001b66: 10a4 asrs r4, r4, #2 8001b68: 42a6 cmp r6, r4 8001b6a: d109 bne.n 8001b80 <__libc_init_array+0x24> 8001b6c: 2600 movs r6, #0 8001b6e: f000 f821 bl 8001bb4 <_init> 8001b72: 4d0a ldr r5, [pc, #40] ; (8001b9c <__libc_init_array+0x40>) 8001b74: 4c0a ldr r4, [pc, #40] ; (8001ba0 <__libc_init_array+0x44>) 8001b76: 1b64 subs r4, r4, r5 8001b78: 10a4 asrs r4, r4, #2 8001b7a: 42a6 cmp r6, r4 8001b7c: d105 bne.n 8001b8a <__libc_init_array+0x2e> 8001b7e: bd70 pop {r4, r5, r6, pc} 8001b80: 00b3 lsls r3, r6, #2 8001b82: 58eb ldr r3, [r5, r3] 8001b84: 4798 blx r3 8001b86: 3601 adds r6, #1 8001b88: e7ee b.n 8001b68 <__libc_init_array+0xc> 8001b8a: 00b3 lsls r3, r6, #2 8001b8c: 58eb ldr r3, [r5, r3] 8001b8e: 4798 blx r3 8001b90: 3601 adds r6, #1 8001b92: e7f2 b.n 8001b7a <__libc_init_array+0x1e> 8001b94: 08001bfc .word 0x08001bfc 8001b98: 08001bfc .word 0x08001bfc 8001b9c: 08001bfc .word 0x08001bfc 8001ba0: 08001c00 .word 0x08001c00 08001ba4 : 8001ba4: 0003 movs r3, r0 8001ba6: 1882 adds r2, r0, r2 8001ba8: 4293 cmp r3, r2 8001baa: d100 bne.n 8001bae 8001bac: 4770 bx lr 8001bae: 7019 strb r1, [r3, #0] 8001bb0: 3301 adds r3, #1 8001bb2: e7f9 b.n 8001ba8 08001bb4 <_init>: 8001bb4: b5f8 push {r3, r4, r5, r6, r7, lr} 8001bb6: 46c0 nop ; (mov r8, r8) 8001bb8: bcf8 pop {r3, r4, r5, r6, r7} 8001bba: bc08 pop {r3} 8001bbc: 469e mov lr, r3 8001bbe: 4770 bx lr 08001bc0 <_fini>: 8001bc0: b5f8 push {r3, r4, r5, r6, r7, lr} 8001bc2: 46c0 nop ; (mov r8, r8) 8001bc4: bcf8 pop {r3, r4, r5, r6, r7} 8001bc6: bc08 pop {r3} 8001bc8: 469e mov lr, r3 8001bca: 4770 bx lr