TTS.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000000c0 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 000023d4 080000c0 080000c0 000100c0 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000030 08002494 08002494 00012494 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 080024c4 080024c4 0002000c 2**0 CONTENTS 4 .ARM 00000000 080024c4 080024c4 0002000c 2**0 CONTENTS 5 .preinit_array 00000000 080024c4 080024c4 0002000c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 080024c4 080024c4 000124c4 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 080024c8 080024c8 000124c8 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 0000000c 20000000 080024cc 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 000000cc 2000000c 080024d8 0002000c 2**2 ALLOC 10 ._user_heap_stack 00000600 200000d8 080024d8 000200d8 2**0 ALLOC 11 .ARM.attributes 00000028 00000000 00000000 0002000c 2**0 CONTENTS, READONLY 12 .debug_info 00006dd4 00000000 00000000 00020034 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00001631 00000000 00000000 00026e08 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00000700 00000000 00000000 00028440 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_ranges 00000638 00000000 00000000 00028b40 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00016f94 00000000 00000000 00029178 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0000993d 00000000 00000000 0004010c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000820ba 00000000 00000000 00049a49 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000050 00000000 00000000 000cbb03 2**0 CONTENTS, READONLY 20 .debug_frame 000017c4 00000000 00000000 000cbb54 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080000c0 <__do_global_dtors_aux>: 80000c0: b510 push {r4, lr} 80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>) 80000c4: 7823 ldrb r3, [r4, #0] 80000c6: 2b00 cmp r3, #0 80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a> 80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>) 80000cc: 2b00 cmp r3, #0 80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16> 80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>) 80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16> 80000d4: bf00 nop 80000d6: 2301 movs r3, #1 80000d8: 7023 strb r3, [r4, #0] 80000da: bd10 pop {r4, pc} 80000dc: 2000000c .word 0x2000000c 80000e0: 00000000 .word 0x00000000 80000e4: 0800247c .word 0x0800247c 080000e8 : 80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc ) 80000ea: b510 push {r4, lr} 80000ec: 2b00 cmp r3, #0 80000ee: d003 beq.n 80000f8 80000f0: 4903 ldr r1, [pc, #12] ; (8000100 ) 80000f2: 4804 ldr r0, [pc, #16] ; (8000104 ) 80000f4: e000 b.n 80000f8 80000f6: bf00 nop 80000f8: bd10 pop {r4, pc} 80000fa: 46c0 nop ; (mov r8, r8) 80000fc: 00000000 .word 0x00000000 8000100: 20000010 .word 0x20000010 8000104: 0800247c .word 0x0800247c 08000108 <__udivsi3>: 8000108: 2200 movs r2, #0 800010a: 0843 lsrs r3, r0, #1 800010c: 428b cmp r3, r1 800010e: d374 bcc.n 80001fa <__udivsi3+0xf2> 8000110: 0903 lsrs r3, r0, #4 8000112: 428b cmp r3, r1 8000114: d35f bcc.n 80001d6 <__udivsi3+0xce> 8000116: 0a03 lsrs r3, r0, #8 8000118: 428b cmp r3, r1 800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e> 800011c: 0b03 lsrs r3, r0, #12 800011e: 428b cmp r3, r1 8000120: d328 bcc.n 8000174 <__udivsi3+0x6c> 8000122: 0c03 lsrs r3, r0, #16 8000124: 428b cmp r3, r1 8000126: d30d bcc.n 8000144 <__udivsi3+0x3c> 8000128: 22ff movs r2, #255 ; 0xff 800012a: 0209 lsls r1, r1, #8 800012c: ba12 rev r2, r2 800012e: 0c03 lsrs r3, r0, #16 8000130: 428b cmp r3, r1 8000132: d302 bcc.n 800013a <__udivsi3+0x32> 8000134: 1212 asrs r2, r2, #8 8000136: 0209 lsls r1, r1, #8 8000138: d065 beq.n 8000206 <__udivsi3+0xfe> 800013a: 0b03 lsrs r3, r0, #12 800013c: 428b cmp r3, r1 800013e: d319 bcc.n 8000174 <__udivsi3+0x6c> 8000140: e000 b.n 8000144 <__udivsi3+0x3c> 8000142: 0a09 lsrs r1, r1, #8 8000144: 0bc3 lsrs r3, r0, #15 8000146: 428b cmp r3, r1 8000148: d301 bcc.n 800014e <__udivsi3+0x46> 800014a: 03cb lsls r3, r1, #15 800014c: 1ac0 subs r0, r0, r3 800014e: 4152 adcs r2, r2 8000150: 0b83 lsrs r3, r0, #14 8000152: 428b cmp r3, r1 8000154: d301 bcc.n 800015a <__udivsi3+0x52> 8000156: 038b lsls r3, r1, #14 8000158: 1ac0 subs r0, r0, r3 800015a: 4152 adcs r2, r2 800015c: 0b43 lsrs r3, r0, #13 800015e: 428b cmp r3, r1 8000160: d301 bcc.n 8000166 <__udivsi3+0x5e> 8000162: 034b lsls r3, r1, #13 8000164: 1ac0 subs r0, r0, r3 8000166: 4152 adcs r2, r2 8000168: 0b03 lsrs r3, r0, #12 800016a: 428b cmp r3, r1 800016c: d301 bcc.n 8000172 <__udivsi3+0x6a> 800016e: 030b lsls r3, r1, #12 8000170: 1ac0 subs r0, r0, r3 8000172: 4152 adcs r2, r2 8000174: 0ac3 lsrs r3, r0, #11 8000176: 428b cmp r3, r1 8000178: d301 bcc.n 800017e <__udivsi3+0x76> 800017a: 02cb lsls r3, r1, #11 800017c: 1ac0 subs r0, r0, r3 800017e: 4152 adcs r2, r2 8000180: 0a83 lsrs r3, r0, #10 8000182: 428b cmp r3, r1 8000184: d301 bcc.n 800018a <__udivsi3+0x82> 8000186: 028b lsls r3, r1, #10 8000188: 1ac0 subs r0, r0, r3 800018a: 4152 adcs r2, r2 800018c: 0a43 lsrs r3, r0, #9 800018e: 428b cmp r3, r1 8000190: d301 bcc.n 8000196 <__udivsi3+0x8e> 8000192: 024b lsls r3, r1, #9 8000194: 1ac0 subs r0, r0, r3 8000196: 4152 adcs r2, r2 8000198: 0a03 lsrs r3, r0, #8 800019a: 428b cmp r3, r1 800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a> 800019e: 020b lsls r3, r1, #8 80001a0: 1ac0 subs r0, r0, r3 80001a2: 4152 adcs r2, r2 80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a> 80001a6: 09c3 lsrs r3, r0, #7 80001a8: 428b cmp r3, r1 80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8> 80001ac: 01cb lsls r3, r1, #7 80001ae: 1ac0 subs r0, r0, r3 80001b0: 4152 adcs r2, r2 80001b2: 0983 lsrs r3, r0, #6 80001b4: 428b cmp r3, r1 80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4> 80001b8: 018b lsls r3, r1, #6 80001ba: 1ac0 subs r0, r0, r3 80001bc: 4152 adcs r2, r2 80001be: 0943 lsrs r3, r0, #5 80001c0: 428b cmp r3, r1 80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0> 80001c4: 014b lsls r3, r1, #5 80001c6: 1ac0 subs r0, r0, r3 80001c8: 4152 adcs r2, r2 80001ca: 0903 lsrs r3, r0, #4 80001cc: 428b cmp r3, r1 80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc> 80001d0: 010b lsls r3, r1, #4 80001d2: 1ac0 subs r0, r0, r3 80001d4: 4152 adcs r2, r2 80001d6: 08c3 lsrs r3, r0, #3 80001d8: 428b cmp r3, r1 80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8> 80001dc: 00cb lsls r3, r1, #3 80001de: 1ac0 subs r0, r0, r3 80001e0: 4152 adcs r2, r2 80001e2: 0883 lsrs r3, r0, #2 80001e4: 428b cmp r3, r1 80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4> 80001e8: 008b lsls r3, r1, #2 80001ea: 1ac0 subs r0, r0, r3 80001ec: 4152 adcs r2, r2 80001ee: 0843 lsrs r3, r0, #1 80001f0: 428b cmp r3, r1 80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0> 80001f4: 004b lsls r3, r1, #1 80001f6: 1ac0 subs r0, r0, r3 80001f8: 4152 adcs r2, r2 80001fa: 1a41 subs r1, r0, r1 80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8> 80001fe: 4601 mov r1, r0 8000200: 4152 adcs r2, r2 8000202: 4610 mov r0, r2 8000204: 4770 bx lr 8000206: e7ff b.n 8000208 <__udivsi3+0x100> 8000208: b501 push {r0, lr} 800020a: 2000 movs r0, #0 800020c: f000 f806 bl 800021c <__aeabi_idiv0> 8000210: bd02 pop {r1, pc} 8000212: 46c0 nop ; (mov r8, r8) 08000214 <__aeabi_uidivmod>: 8000214: 2900 cmp r1, #0 8000216: d0f7 beq.n 8000208 <__udivsi3+0x100> 8000218: e776 b.n 8000108 <__udivsi3> 800021a: 4770 bx lr 0800021c <__aeabi_idiv0>: 800021c: 4770 bx lr 800021e: 46c0 nop ; (mov r8, r8) 08000220 : * configuration to the respective registers. * Afterwards the sensor is in idle and ready for conversion. * * @param *hi2c: Pointer to I2C Handle */ void HTPA_Init(I2C_HandleTypeDef *hi2c){ 8000220: b580 push {r7, lr} 8000222: b082 sub sp, #8 8000224: af00 add r7, sp, #0 8000226: 6078 str r0, [r7, #4] i2c_handle = *hi2c; 8000228: 4a15 ldr r2, [pc, #84] ; (8000280 ) 800022a: 687b ldr r3, [r7, #4] 800022c: 0010 movs r0, r2 800022e: 0019 movs r1, r3 8000230: 2354 movs r3, #84 ; 0x54 8000232: 001a movs r2, r3 8000234: f002 f910 bl 8002458 // Berechnung für clk / sample aus I2C parametern? HTPA_WriteRegister(HTPA_SENSOR_CONFIG, 0x01); // Wakeup 8000238: 2101 movs r1, #1 800023a: 2001 movs r0, #1 800023c: f000 f822 bl 8000284 HTPA_WriteRegister(HTPA_SENSOR_TRIM_1, 0x0C); 8000240: 210c movs r1, #12 8000242: 2003 movs r0, #3 8000244: f000 f81e bl 8000284 HTPA_WriteRegister(HTPA_SENSOR_TRIM_2, 0x0C); 8000248: 210c movs r1, #12 800024a: 2004 movs r0, #4 800024c: f000 f81a bl 8000284 HTPA_WriteRegister(HTPA_SENSOR_TRIM_3, 0x0C); 8000250: 210c movs r1, #12 8000252: 2005 movs r0, #5 8000254: f000 f816 bl 8000284 HTPA_WriteRegister(HTPA_SENSOR_TRIM_4, 0x14); 8000258: 2114 movs r1, #20 800025a: 2006 movs r0, #6 800025c: f000 f812 bl 8000284 HTPA_WriteRegister(HTPA_SENSOR_TRIM_5, 0x0C); 8000260: 210c movs r1, #12 8000262: 2007 movs r0, #7 8000264: f000 f80e bl 8000284 HTPA_WriteRegister(HTPA_SENSOR_TRIM_6, 0x0C); 8000268: 210c movs r1, #12 800026a: 2008 movs r0, #8 800026c: f000 f80a bl 8000284 HTPA_WriteRegister(HTPA_SENSOR_TRIM_7, 0x88); 8000270: 2188 movs r1, #136 ; 0x88 8000272: 2009 movs r0, #9 8000274: f000 f806 bl 8000284 } 8000278: 46c0 nop ; (mov r8, r8) 800027a: 46bd mov sp, r7 800027c: b002 add sp, #8 800027e: bd80 pop {r7, pc} 8000280: 20000028 .word 0x20000028 08000284 : * description * * @param register_address: address of register * @param byte: byte to be written to register */ void HTPA_WriteRegister(uint8_t register_address, uint8_t byte){ 8000284: b5b0 push {r4, r5, r7, lr} 8000286: b086 sub sp, #24 8000288: af02 add r7, sp, #8 800028a: 0002 movs r2, r0 800028c: 1dfb adds r3, r7, #7 800028e: 701a strb r2, [r3, #0] 8000290: 1dbb adds r3, r7, #6 8000292: 1c0a adds r2, r1, #0 8000294: 701a strb r2, [r3, #0] uint8_t i2c_data = register_address; 8000296: 200e movs r0, #14 8000298: 183b adds r3, r7, r0 800029a: 1dfa adds r2, r7, #7 800029c: 7812 ldrb r2, [r2, #0] 800029e: 701a strb r2, [r3, #0] uint8_t i2c_address = (HTPA_SENSOR_ADDRESS << 1); 80002a0: 240f movs r4, #15 80002a2: 193b adds r3, r7, r4 80002a4: 2234 movs r2, #52 ; 0x34 80002a6: 701a strb r2, [r3, #0] i2c_address &= 0xFE; // set read/write bit to write (0) 80002a8: 193b adds r3, r7, r4 80002aa: 193a adds r2, r7, r4 80002ac: 7812 ldrb r2, [r2, #0] 80002ae: 2101 movs r1, #1 80002b0: 438a bics r2, r1 80002b2: 701a strb r2, [r3, #0] HAL_I2C_Master_Transmit(&i2c_handle, i2c_address, &i2c_data, 1, I2C_MAX_DELAY); 80002b4: 193b adds r3, r7, r4 80002b6: 781b ldrb r3, [r3, #0] 80002b8: b299 uxth r1, r3 80002ba: 0005 movs r5, r0 80002bc: 183a adds r2, r7, r0 80002be: 480d ldr r0, [pc, #52] ; (80002f4 ) 80002c0: 2301 movs r3, #1 80002c2: 425b negs r3, r3 80002c4: 9300 str r3, [sp, #0] 80002c6: 2301 movs r3, #1 80002c8: f000 fd84 bl 8000dd4 i2c_data = byte; 80002cc: 0028 movs r0, r5 80002ce: 183b adds r3, r7, r0 80002d0: 1dba adds r2, r7, #6 80002d2: 7812 ldrb r2, [r2, #0] 80002d4: 701a strb r2, [r3, #0] HAL_I2C_Master_Transmit(&i2c_handle, i2c_address, &i2c_data, 1, I2C_MAX_DELAY); 80002d6: 193b adds r3, r7, r4 80002d8: 781b ldrb r3, [r3, #0] 80002da: b299 uxth r1, r3 80002dc: 183a adds r2, r7, r0 80002de: 4805 ldr r0, [pc, #20] ; (80002f4 ) 80002e0: 2301 movs r3, #1 80002e2: 425b negs r3, r3 80002e4: 9300 str r3, [sp, #0] 80002e6: 2301 movs r3, #1 80002e8: f000 fd74 bl 8000dd4 } 80002ec: 46c0 nop ; (mov r8, r8) 80002ee: 46bd mov sp, r7 80002f0: b004 add sp, #16 80002f2: bdb0 pop {r4, r5, r7, pc} 80002f4: 20000028 .word 0x20000028 080002f8 : * Reads the sensors status register and stores the information in * the HTPA_Statsu structure. * * @return HTPA_Status: status register struct */ HTPA_Status HTPA_GetStatus(void){ 80002f8: b590 push {r4, r7, lr} 80002fa: b087 sub sp, #28 80002fc: af02 add r7, sp, #8 HTPA_Status status_return; uint8_t i2c_data = HTPA_SENSOR_STATUS; 80002fe: 1cfb adds r3, r7, #3 8000300: 2202 movs r2, #2 8000302: 701a strb r2, [r3, #0] uint8_t i2c_address = (HTPA_SENSOR_ADDRESS << 1); 8000304: 240f movs r4, #15 8000306: 193b adds r3, r7, r4 8000308: 2234 movs r2, #52 ; 0x34 800030a: 701a strb r2, [r3, #0] uint8_t i2c_readData = 0; 800030c: 1cbb adds r3, r7, #2 800030e: 2200 movs r2, #0 8000310: 701a strb r2, [r3, #0] i2c_address &= 0xFE; // set read/write bit 0 to write (0) 8000312: 193b adds r3, r7, r4 8000314: 193a adds r2, r7, r4 8000316: 7812 ldrb r2, [r2, #0] 8000318: 2101 movs r1, #1 800031a: 438a bics r2, r1 800031c: 701a strb r2, [r3, #0] HAL_I2C_Master_Transmit(&i2c_handle, i2c_address, &i2c_data, 1, I2C_MAX_DELAY); 800031e: 193b adds r3, r7, r4 8000320: 781b ldrb r3, [r3, #0] 8000322: b299 uxth r1, r3 8000324: 1cfa adds r2, r7, #3 8000326: 482f ldr r0, [pc, #188] ; (80003e4 ) 8000328: 2301 movs r3, #1 800032a: 425b negs r3, r3 800032c: 9300 str r3, [sp, #0] 800032e: 2301 movs r3, #1 8000330: f000 fd50 bl 8000dd4 i2c_address |= 0x01; // set read/write bit 0 to read (1) 8000334: 193b adds r3, r7, r4 8000336: 193a adds r2, r7, r4 8000338: 7812 ldrb r2, [r2, #0] 800033a: 2101 movs r1, #1 800033c: 430a orrs r2, r1 800033e: 701a strb r2, [r3, #0] HAL_I2C_Master_Receive(&i2c_handle, i2c_address, &i2c_readData, 1, I2C_MAX_DELAY); 8000340: 193b adds r3, r7, r4 8000342: 781b ldrb r3, [r3, #0] 8000344: b299 uxth r1, r3 8000346: 1cba adds r2, r7, #2 8000348: 4826 ldr r0, [pc, #152] ; (80003e4 ) 800034a: 2301 movs r3, #1 800034c: 425b negs r3, r3 800034e: 9300 str r3, [sp, #0] 8000350: 2301 movs r3, #1 8000352: f000 fe47 bl 8000fe4 status_return.block = (i2c_readData >> 4) && 0xFC; 8000356: 1cbb adds r3, r7, #2 8000358: 781b ldrb r3, [r3, #0] 800035a: 091b lsrs r3, r3, #4 800035c: b2db uxtb r3, r3 800035e: 1e5a subs r2, r3, #1 8000360: 4193 sbcs r3, r2 8000362: b2db uxtb r3, r3 8000364: 001a movs r2, r3 8000366: 1d3b adds r3, r7, #4 8000368: 701a strb r2, [r3, #0] status_return.vdd_meas = (i2c_readData >> 2) && 0xFE; 800036a: 1cbb adds r3, r7, #2 800036c: 781b ldrb r3, [r3, #0] 800036e: 089b lsrs r3, r3, #2 8000370: b2db uxtb r3, r3 8000372: 1e5a subs r2, r3, #1 8000374: 4193 sbcs r3, r2 8000376: b2da uxtb r2, r3 8000378: 1d3b adds r3, r7, #4 800037a: 705a strb r2, [r3, #1] status_return.blind = (i2c_readData >> 1) && 0xFE; 800037c: 1cbb adds r3, r7, #2 800037e: 781b ldrb r3, [r3, #0] 8000380: 085b lsrs r3, r3, #1 8000382: b2db uxtb r3, r3 8000384: 1e5a subs r2, r3, #1 8000386: 4193 sbcs r3, r2 8000388: b2da uxtb r2, r3 800038a: 1d3b adds r3, r7, #4 800038c: 709a strb r2, [r3, #2] status_return.eoc = i2c_readData && 0xFE; 800038e: 1cbb adds r3, r7, #2 8000390: 781b ldrb r3, [r3, #0] 8000392: 1e5a subs r2, r3, #1 8000394: 4193 sbcs r3, r2 8000396: b2da uxtb r2, r3 8000398: 1d3b adds r3, r7, #4 800039a: 70da strb r2, [r3, #3] return status_return; 800039c: 2108 movs r1, #8 800039e: 187b adds r3, r7, r1 80003a0: 1d3a adds r2, r7, #4 80003a2: 6812 ldr r2, [r2, #0] 80003a4: 601a str r2, [r3, #0] 80003a6: 187a adds r2, r7, r1 80003a8: 2300 movs r3, #0 80003aa: 7811 ldrb r1, [r2, #0] 80003ac: 20ff movs r0, #255 ; 0xff 80003ae: 4001 ands r1, r0 80003b0: 20ff movs r0, #255 ; 0xff 80003b2: 4383 bics r3, r0 80003b4: 430b orrs r3, r1 80003b6: 7851 ldrb r1, [r2, #1] 80003b8: 20ff movs r0, #255 ; 0xff 80003ba: 4001 ands r1, r0 80003bc: 0209 lsls r1, r1, #8 80003be: 480a ldr r0, [pc, #40] ; (80003e8 ) 80003c0: 4003 ands r3, r0 80003c2: 430b orrs r3, r1 80003c4: 7891 ldrb r1, [r2, #2] 80003c6: 20ff movs r0, #255 ; 0xff 80003c8: 4001 ands r1, r0 80003ca: 0409 lsls r1, r1, #16 80003cc: 4807 ldr r0, [pc, #28] ; (80003ec ) 80003ce: 4003 ands r3, r0 80003d0: 430b orrs r3, r1 80003d2: 78d2 ldrb r2, [r2, #3] 80003d4: 0612 lsls r2, r2, #24 80003d6: 021b lsls r3, r3, #8 80003d8: 0a1b lsrs r3, r3, #8 80003da: 4313 orrs r3, r2 } 80003dc: 0018 movs r0, r3 80003de: 46bd mov sp, r7 80003e0: b005 add sp, #20 80003e2: bd90 pop {r4, r7, pc} 80003e4: 20000028 .word 0x20000028 80003e8: ffff00ff .word 0xffff00ff 80003ec: ff00ffff .word 0xff00ffff 080003f0
: /** * @brief The application entry point. * @retval int */ int main(void) { 80003f0: b580 push {r7, lr} 80003f2: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80003f4: f000 f9b4 bl 8000760 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80003f8: f000 f81e bl 8000438 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 80003fc: f000 f8b4 bl 8000568 MX_I2C1_Init(); 8000400: f000 f872 bl 80004e8 /* USER CODE BEGIN 2 */ HTPA_Init(&hi2c1); 8000404: 4b0a ldr r3, [pc, #40] ; (8000430 ) 8000406: 0018 movs r0, r3 8000408: f7ff ff0a bl 8000220 htpa_status_test.vdd_meas = 1; 800040c: 4b09 ldr r3, [pc, #36] ; (8000434 ) 800040e: 2201 movs r2, #1 8000410: 705a strb r2, [r3, #1] htpa_status_test.block = 3; 8000412: 4b08 ldr r3, [pc, #32] ; (8000434 ) 8000414: 2203 movs r2, #3 8000416: 701a strb r2, [r3, #0] /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { htpa_status_test = HTPA_GetStatus(); 8000418: f7ff ff6e bl 80002f8 800041c: 0003 movs r3, r0 800041e: 001a movs r2, r3 8000420: 4b04 ldr r3, [pc, #16] ; (8000434 ) 8000422: 601a str r2, [r3, #0] HAL_Delay(1000); 8000424: 23fa movs r3, #250 ; 0xfa 8000426: 009b lsls r3, r3, #2 8000428: 0018 movs r0, r3 800042a: f000 f9fd bl 8000828 htpa_status_test = HTPA_GetStatus(); 800042e: e7f3 b.n 8000418 8000430: 2000007c .word 0x2000007c 8000434: 200000d0 .word 0x200000d0 08000438 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000438: b590 push {r4, r7, lr} 800043a: b099 sub sp, #100 ; 0x64 800043c: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800043e: 242c movs r4, #44 ; 0x2c 8000440: 193b adds r3, r7, r4 8000442: 0018 movs r0, r3 8000444: 2334 movs r3, #52 ; 0x34 8000446: 001a movs r2, r3 8000448: 2100 movs r1, #0 800044a: f002 f80e bl 800246a RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800044e: 231c movs r3, #28 8000450: 18fb adds r3, r7, r3 8000452: 0018 movs r0, r3 8000454: 2310 movs r3, #16 8000456: 001a movs r2, r3 8000458: 2100 movs r1, #0 800045a: f002 f806 bl 800246a RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 800045e: 1d3b adds r3, r7, #4 8000460: 0018 movs r0, r3 8000462: 2318 movs r3, #24 8000464: 001a movs r2, r3 8000466: 2100 movs r1, #0 8000468: f001 ffff bl 800246a /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 800046c: 0021 movs r1, r4 800046e: 187b adds r3, r7, r1 8000470: 2202 movs r2, #2 8000472: 601a str r2, [r3, #0] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8000474: 187b adds r3, r7, r1 8000476: 2201 movs r2, #1 8000478: 60da str r2, [r3, #12] RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 800047a: 187b adds r3, r7, r1 800047c: 2210 movs r2, #16 800047e: 611a str r2, [r3, #16] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 8000480: 187b adds r3, r7, r1 8000482: 2200 movs r2, #0 8000484: 625a str r2, [r3, #36] ; 0x24 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000486: 187b adds r3, r7, r1 8000488: 0018 movs r0, r3 800048a: f001 fa01 bl 8001890 800048e: 1e03 subs r3, r0, #0 8000490: d001 beq.n 8000496 { Error_Handler(); 8000492: f000 f88f bl 80005b4 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000496: 211c movs r1, #28 8000498: 187b adds r3, r7, r1 800049a: 2207 movs r2, #7 800049c: 601a str r2, [r3, #0] |RCC_CLOCKTYPE_PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; 800049e: 187b adds r3, r7, r1 80004a0: 2200 movs r2, #0 80004a2: 605a str r2, [r3, #4] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80004a4: 187b adds r3, r7, r1 80004a6: 2200 movs r2, #0 80004a8: 609a str r2, [r3, #8] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 80004aa: 187b adds r3, r7, r1 80004ac: 2200 movs r2, #0 80004ae: 60da str r2, [r3, #12] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 80004b0: 187b adds r3, r7, r1 80004b2: 2100 movs r1, #0 80004b4: 0018 movs r0, r3 80004b6: f001 fd71 bl 8001f9c 80004ba: 1e03 subs r3, r0, #0 80004bc: d001 beq.n 80004c2 { Error_Handler(); 80004be: f000 f879 bl 80005b4 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1; 80004c2: 1d3b adds r3, r7, #4 80004c4: 2220 movs r2, #32 80004c6: 601a str r2, [r3, #0] PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_HSI; 80004c8: 1d3b adds r3, r7, #4 80004ca: 2200 movs r2, #0 80004cc: 60da str r2, [r3, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 80004ce: 1d3b adds r3, r7, #4 80004d0: 0018 movs r0, r3 80004d2: f001 feaf bl 8002234 80004d6: 1e03 subs r3, r0, #0 80004d8: d001 beq.n 80004de { Error_Handler(); 80004da: f000 f86b bl 80005b4 } } 80004de: 46c0 nop ; (mov r8, r8) 80004e0: 46bd mov sp, r7 80004e2: b019 add sp, #100 ; 0x64 80004e4: bd90 pop {r4, r7, pc} ... 080004e8 : * @brief I2C1 Initialization Function * @param None * @retval None */ static void MX_I2C1_Init(void) { 80004e8: b580 push {r7, lr} 80004ea: af00 add r7, sp, #0 /* USER CODE END I2C1_Init 0 */ /* USER CODE BEGIN I2C1_Init 1 */ /* USER CODE END I2C1_Init 1 */ hi2c1.Instance = I2C1; 80004ec: 4b1b ldr r3, [pc, #108] ; (800055c ) 80004ee: 4a1c ldr r2, [pc, #112] ; (8000560 ) 80004f0: 601a str r2, [r3, #0] hi2c1.Init.Timing = 0x2000090E; 80004f2: 4b1a ldr r3, [pc, #104] ; (800055c ) 80004f4: 4a1b ldr r2, [pc, #108] ; (8000564 ) 80004f6: 605a str r2, [r3, #4] hi2c1.Init.OwnAddress1 = 0; 80004f8: 4b18 ldr r3, [pc, #96] ; (800055c ) 80004fa: 2200 movs r2, #0 80004fc: 609a str r2, [r3, #8] hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 80004fe: 4b17 ldr r3, [pc, #92] ; (800055c ) 8000500: 2201 movs r2, #1 8000502: 60da str r2, [r3, #12] hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8000504: 4b15 ldr r3, [pc, #84] ; (800055c ) 8000506: 2200 movs r2, #0 8000508: 611a str r2, [r3, #16] hi2c1.Init.OwnAddress2 = 0; 800050a: 4b14 ldr r3, [pc, #80] ; (800055c ) 800050c: 2200 movs r2, #0 800050e: 615a str r2, [r3, #20] hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; 8000510: 4b12 ldr r3, [pc, #72] ; (800055c ) 8000512: 2200 movs r2, #0 8000514: 619a str r2, [r3, #24] hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 8000516: 4b11 ldr r3, [pc, #68] ; (800055c ) 8000518: 2200 movs r2, #0 800051a: 61da str r2, [r3, #28] hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 800051c: 4b0f ldr r3, [pc, #60] ; (800055c ) 800051e: 2200 movs r2, #0 8000520: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c1) != HAL_OK) 8000522: 4b0e ldr r3, [pc, #56] ; (800055c ) 8000524: 0018 movs r0, r3 8000526: f000 fbbf bl 8000ca8 800052a: 1e03 subs r3, r0, #0 800052c: d001 beq.n 8000532 { Error_Handler(); 800052e: f000 f841 bl 80005b4 } /** Configure Analogue filter */ if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) 8000532: 4b0a ldr r3, [pc, #40] ; (800055c ) 8000534: 2100 movs r1, #0 8000536: 0018 movs r0, r3 8000538: f001 f912 bl 8001760 800053c: 1e03 subs r3, r0, #0 800053e: d001 beq.n 8000544 { Error_Handler(); 8000540: f000 f838 bl 80005b4 } /** Configure Digital filter */ if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) 8000544: 4b05 ldr r3, [pc, #20] ; (800055c ) 8000546: 2100 movs r1, #0 8000548: 0018 movs r0, r3 800054a: f001 f955 bl 80017f8 800054e: 1e03 subs r3, r0, #0 8000550: d001 beq.n 8000556 { Error_Handler(); 8000552: f000 f82f bl 80005b4 } /* USER CODE BEGIN I2C1_Init 2 */ /* USER CODE END I2C1_Init 2 */ } 8000556: 46c0 nop ; (mov r8, r8) 8000558: 46bd mov sp, r7 800055a: bd80 pop {r7, pc} 800055c: 2000007c .word 0x2000007c 8000560: 40005400 .word 0x40005400 8000564: 2000090e .word 0x2000090e 08000568 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8000568: b580 push {r7, lr} 800056a: b082 sub sp, #8 800056c: af00 add r7, sp, #0 /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); 800056e: 4b10 ldr r3, [pc, #64] ; (80005b0 ) 8000570: 695a ldr r2, [r3, #20] 8000572: 4b0f ldr r3, [pc, #60] ; (80005b0 ) 8000574: 2180 movs r1, #128 ; 0x80 8000576: 03c9 lsls r1, r1, #15 8000578: 430a orrs r2, r1 800057a: 615a str r2, [r3, #20] 800057c: 4b0c ldr r3, [pc, #48] ; (80005b0 ) 800057e: 695a ldr r2, [r3, #20] 8000580: 2380 movs r3, #128 ; 0x80 8000582: 03db lsls r3, r3, #15 8000584: 4013 ands r3, r2 8000586: 607b str r3, [r7, #4] 8000588: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOA_CLK_ENABLE(); 800058a: 4b09 ldr r3, [pc, #36] ; (80005b0 ) 800058c: 695a ldr r2, [r3, #20] 800058e: 4b08 ldr r3, [pc, #32] ; (80005b0 ) 8000590: 2180 movs r1, #128 ; 0x80 8000592: 0289 lsls r1, r1, #10 8000594: 430a orrs r2, r1 8000596: 615a str r2, [r3, #20] 8000598: 4b05 ldr r3, [pc, #20] ; (80005b0 ) 800059a: 695a ldr r2, [r3, #20] 800059c: 2380 movs r3, #128 ; 0x80 800059e: 029b lsls r3, r3, #10 80005a0: 4013 ands r3, r2 80005a2: 603b str r3, [r7, #0] 80005a4: 683b ldr r3, [r7, #0] } 80005a6: 46c0 nop ; (mov r8, r8) 80005a8: 46bd mov sp, r7 80005aa: b002 add sp, #8 80005ac: bd80 pop {r7, pc} 80005ae: 46c0 nop ; (mov r8, r8) 80005b0: 40021000 .word 0x40021000 080005b4 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 80005b4: b580 push {r7, lr} 80005b6: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 80005b8: b672 cpsid i } 80005ba: 46c0 nop ; (mov r8, r8) /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 80005bc: e7fe b.n 80005bc ... 080005c0 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 80005c0: b580 push {r7, lr} 80005c2: b082 sub sp, #8 80005c4: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 80005c6: 4b0f ldr r3, [pc, #60] ; (8000604 ) 80005c8: 699a ldr r2, [r3, #24] 80005ca: 4b0e ldr r3, [pc, #56] ; (8000604 ) 80005cc: 2101 movs r1, #1 80005ce: 430a orrs r2, r1 80005d0: 619a str r2, [r3, #24] 80005d2: 4b0c ldr r3, [pc, #48] ; (8000604 ) 80005d4: 699b ldr r3, [r3, #24] 80005d6: 2201 movs r2, #1 80005d8: 4013 ands r3, r2 80005da: 607b str r3, [r7, #4] 80005dc: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 80005de: 4b09 ldr r3, [pc, #36] ; (8000604 ) 80005e0: 69da ldr r2, [r3, #28] 80005e2: 4b08 ldr r3, [pc, #32] ; (8000604 ) 80005e4: 2180 movs r1, #128 ; 0x80 80005e6: 0549 lsls r1, r1, #21 80005e8: 430a orrs r2, r1 80005ea: 61da str r2, [r3, #28] 80005ec: 4b05 ldr r3, [pc, #20] ; (8000604 ) 80005ee: 69da ldr r2, [r3, #28] 80005f0: 2380 movs r3, #128 ; 0x80 80005f2: 055b lsls r3, r3, #21 80005f4: 4013 ands r3, r2 80005f6: 603b str r3, [r7, #0] 80005f8: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80005fa: 46c0 nop ; (mov r8, r8) 80005fc: 46bd mov sp, r7 80005fe: b002 add sp, #8 8000600: bd80 pop {r7, pc} 8000602: 46c0 nop ; (mov r8, r8) 8000604: 40021000 .word 0x40021000 08000608 : * This function configures the hardware resources used in this example * @param hi2c: I2C handle pointer * @retval None */ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) { 8000608: b590 push {r4, r7, lr} 800060a: b08b sub sp, #44 ; 0x2c 800060c: af00 add r7, sp, #0 800060e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000610: 2414 movs r4, #20 8000612: 193b adds r3, r7, r4 8000614: 0018 movs r0, r3 8000616: 2314 movs r3, #20 8000618: 001a movs r2, r3 800061a: 2100 movs r1, #0 800061c: f001 ff25 bl 800246a if(hi2c->Instance==I2C1) 8000620: 687b ldr r3, [r7, #4] 8000622: 681b ldr r3, [r3, #0] 8000624: 4a1c ldr r2, [pc, #112] ; (8000698 ) 8000626: 4293 cmp r3, r2 8000628: d131 bne.n 800068e { /* USER CODE BEGIN I2C1_MspInit 0 */ /* USER CODE END I2C1_MspInit 0 */ __HAL_RCC_GPIOF_CLK_ENABLE(); 800062a: 4b1c ldr r3, [pc, #112] ; (800069c ) 800062c: 695a ldr r2, [r3, #20] 800062e: 4b1b ldr r3, [pc, #108] ; (800069c ) 8000630: 2180 movs r1, #128 ; 0x80 8000632: 03c9 lsls r1, r1, #15 8000634: 430a orrs r2, r1 8000636: 615a str r2, [r3, #20] 8000638: 4b18 ldr r3, [pc, #96] ; (800069c ) 800063a: 695a ldr r2, [r3, #20] 800063c: 2380 movs r3, #128 ; 0x80 800063e: 03db lsls r3, r3, #15 8000640: 4013 ands r3, r2 8000642: 613b str r3, [r7, #16] 8000644: 693b ldr r3, [r7, #16] /**I2C1 GPIO Configuration PF0-OSC_IN ------> I2C1_SDA PF1-OSC_OUT ------> I2C1_SCL */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8000646: 0021 movs r1, r4 8000648: 187b adds r3, r7, r1 800064a: 2203 movs r2, #3 800064c: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 800064e: 187b adds r3, r7, r1 8000650: 2212 movs r2, #18 8000652: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000654: 187b adds r3, r7, r1 8000656: 2200 movs r2, #0 8000658: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800065a: 187b adds r3, r7, r1 800065c: 2203 movs r2, #3 800065e: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF1_I2C1; 8000660: 187b adds r3, r7, r1 8000662: 2201 movs r2, #1 8000664: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 8000666: 187b adds r3, r7, r1 8000668: 4a0d ldr r2, [pc, #52] ; (80006a0 ) 800066a: 0019 movs r1, r3 800066c: 0010 movs r0, r2 800066e: f000 f9b3 bl 80009d8 /* Peripheral clock enable */ __HAL_RCC_I2C1_CLK_ENABLE(); 8000672: 4b0a ldr r3, [pc, #40] ; (800069c ) 8000674: 69da ldr r2, [r3, #28] 8000676: 4b09 ldr r3, [pc, #36] ; (800069c ) 8000678: 2180 movs r1, #128 ; 0x80 800067a: 0389 lsls r1, r1, #14 800067c: 430a orrs r2, r1 800067e: 61da str r2, [r3, #28] 8000680: 4b06 ldr r3, [pc, #24] ; (800069c ) 8000682: 69da ldr r2, [r3, #28] 8000684: 2380 movs r3, #128 ; 0x80 8000686: 039b lsls r3, r3, #14 8000688: 4013 ands r3, r2 800068a: 60fb str r3, [r7, #12] 800068c: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN I2C1_MspInit 1 */ /* USER CODE END I2C1_MspInit 1 */ } } 800068e: 46c0 nop ; (mov r8, r8) 8000690: 46bd mov sp, r7 8000692: b00b add sp, #44 ; 0x2c 8000694: bd90 pop {r4, r7, pc} 8000696: 46c0 nop ; (mov r8, r8) 8000698: 40005400 .word 0x40005400 800069c: 40021000 .word 0x40021000 80006a0: 48001400 .word 0x48001400 080006a4 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80006a4: b580 push {r7, lr} 80006a6: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80006a8: e7fe b.n 80006a8 080006aa : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80006aa: b580 push {r7, lr} 80006ac: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80006ae: e7fe b.n 80006ae 080006b0 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80006b0: b580 push {r7, lr} 80006b2: af00 add r7, sp, #0 /* USER CODE END SVC_IRQn 0 */ /* USER CODE BEGIN SVC_IRQn 1 */ /* USER CODE END SVC_IRQn 1 */ } 80006b4: 46c0 nop ; (mov r8, r8) 80006b6: 46bd mov sp, r7 80006b8: bd80 pop {r7, pc} 080006ba : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 80006ba: b580 push {r7, lr} 80006bc: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 80006be: 46c0 nop ; (mov r8, r8) 80006c0: 46bd mov sp, r7 80006c2: bd80 pop {r7, pc} 080006c4 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 80006c4: b580 push {r7, lr} 80006c6: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 80006c8: f000 f892 bl 80007f0 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 80006cc: 46c0 nop ; (mov r8, r8) 80006ce: 46bd mov sp, r7 80006d0: bd80 pop {r7, pc} 080006d2 : * @brief Setup the microcontroller system * @param None * @retval None */ void SystemInit(void) { 80006d2: b580 push {r7, lr} 80006d4: af00 add r7, sp, #0 before branch to main program. This call is made inside the "startup_stm32f0xx.s" file. User can setups the default system clock (System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings). */ } 80006d6: 46c0 nop ; (mov r8, r8) 80006d8: 46bd mov sp, r7 80006da: bd80 pop {r7, pc} 080006dc : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 80006dc: 4813 ldr r0, [pc, #76] ; (800072c ) mov sp, r0 /* set stack pointer */ 80006de: 4685 mov sp, r0 /* Call the clock system initialization function.*/ bl SystemInit 80006e0: f7ff fff7 bl 80006d2 /*Check if boot space corresponds to test memory*/ LDR R0,=0x00000004 80006e4: 4812 ldr r0, [pc, #72] ; (8000730 ) LDR R1, [R0] 80006e6: 6801 ldr r1, [r0, #0] LSRS R1, R1, #24 80006e8: 0e09 lsrs r1, r1, #24 LDR R2,=0x1F 80006ea: 4a12 ldr r2, [pc, #72] ; (8000734 ) CMP R1, R2 80006ec: 4291 cmp r1, r2 BNE ApplicationStart 80006ee: d105 bne.n 80006fc /*SYSCFG clock enable*/ LDR R0,=0x40021018 80006f0: 4811 ldr r0, [pc, #68] ; (8000738 ) LDR R1,=0x00000001 80006f2: 4912 ldr r1, [pc, #72] ; (800073c ) STR R1, [R0] 80006f4: 6001 str r1, [r0, #0] /*Set CFGR1 register with flash memory remap at address 0*/ LDR R0,=0x40010000 80006f6: 4812 ldr r0, [pc, #72] ; (8000740 ) LDR R1,=0x00000000 80006f8: 4912 ldr r1, [pc, #72] ; (8000744 ) STR R1, [R0] 80006fa: 6001 str r1, [r0, #0] 080006fc : ApplicationStart: /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80006fc: 4812 ldr r0, [pc, #72] ; (8000748 ) ldr r1, =_edata 80006fe: 4913 ldr r1, [pc, #76] ; (800074c ) ldr r2, =_sidata 8000700: 4a13 ldr r2, [pc, #76] ; (8000750 ) movs r3, #0 8000702: 2300 movs r3, #0 b LoopCopyDataInit 8000704: e002 b.n 800070c 08000706 : CopyDataInit: ldr r4, [r2, r3] 8000706: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8000708: 50c4 str r4, [r0, r3] adds r3, r3, #4 800070a: 3304 adds r3, #4 0800070c : LoopCopyDataInit: adds r4, r0, r3 800070c: 18c4 adds r4, r0, r3 cmp r4, r1 800070e: 428c cmp r4, r1 bcc CopyDataInit 8000710: d3f9 bcc.n 8000706 /* Zero fill the bss segment. */ ldr r2, =_sbss 8000712: 4a10 ldr r2, [pc, #64] ; (8000754 ) ldr r4, =_ebss 8000714: 4c10 ldr r4, [pc, #64] ; (8000758 ) movs r3, #0 8000716: 2300 movs r3, #0 b LoopFillZerobss 8000718: e001 b.n 800071e 0800071a : FillZerobss: str r3, [r2] 800071a: 6013 str r3, [r2, #0] adds r2, r2, #4 800071c: 3204 adds r2, #4 0800071e : LoopFillZerobss: cmp r2, r4 800071e: 42a2 cmp r2, r4 bcc FillZerobss 8000720: d3fb bcc.n 800071a /* Call static constructors */ bl __libc_init_array 8000722: f001 fe75 bl 8002410 <__libc_init_array> /* Call the application's entry point.*/ bl main 8000726: f7ff fe63 bl 80003f0
0800072a : LoopForever: b LoopForever 800072a: e7fe b.n 800072a ldr r0, =_estack 800072c: 20001800 .word 0x20001800 LDR R0,=0x00000004 8000730: 00000004 .word 0x00000004 LDR R2,=0x1F 8000734: 0000001f .word 0x0000001f LDR R0,=0x40021018 8000738: 40021018 .word 0x40021018 LDR R1,=0x00000001 800073c: 00000001 .word 0x00000001 LDR R0,=0x40010000 8000740: 40010000 .word 0x40010000 LDR R1,=0x00000000 8000744: 00000000 .word 0x00000000 ldr r0, =_sdata 8000748: 20000000 .word 0x20000000 ldr r1, =_edata 800074c: 2000000c .word 0x2000000c ldr r2, =_sidata 8000750: 080024cc .word 0x080024cc ldr r2, =_sbss 8000754: 2000000c .word 0x2000000c ldr r4, =_ebss 8000758: 200000d8 .word 0x200000d8 0800075c : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 800075c: e7fe b.n 800075c ... 08000760 : * In the default implementation,Systick is used as source of time base. * The tick variable is incremented each 1ms in its ISR. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8000760: b580 push {r7, lr} 8000762: af00 add r7, sp, #0 /* Configure Flash prefetch */ #if (PREFETCH_ENABLE != 0) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8000764: 4b07 ldr r3, [pc, #28] ; (8000784 ) 8000766: 681a ldr r2, [r3, #0] 8000768: 4b06 ldr r3, [pc, #24] ; (8000784 ) 800076a: 2110 movs r1, #16 800076c: 430a orrs r2, r1 800076e: 601a str r2, [r3, #0] #endif /* PREFETCH_ENABLE */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8000770: 2003 movs r0, #3 8000772: f000 f809 bl 8000788 /* Init the low level hardware */ HAL_MspInit(); 8000776: f7ff ff23 bl 80005c0 /* Return function status */ return HAL_OK; 800077a: 2300 movs r3, #0 } 800077c: 0018 movs r0, r3 800077e: 46bd mov sp, r7 8000780: bd80 pop {r7, pc} 8000782: 46c0 nop ; (mov r8, r8) 8000784: 40022000 .word 0x40022000 08000788 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8000788: b590 push {r4, r7, lr} 800078a: b083 sub sp, #12 800078c: af00 add r7, sp, #0 800078e: 6078 str r0, [r7, #4] /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8000790: 4b14 ldr r3, [pc, #80] ; (80007e4 ) 8000792: 681c ldr r4, [r3, #0] 8000794: 4b14 ldr r3, [pc, #80] ; (80007e8 ) 8000796: 781b ldrb r3, [r3, #0] 8000798: 0019 movs r1, r3 800079a: 23fa movs r3, #250 ; 0xfa 800079c: 0098 lsls r0, r3, #2 800079e: f7ff fcb3 bl 8000108 <__udivsi3> 80007a2: 0003 movs r3, r0 80007a4: 0019 movs r1, r3 80007a6: 0020 movs r0, r4 80007a8: f7ff fcae bl 8000108 <__udivsi3> 80007ac: 0003 movs r3, r0 80007ae: 0018 movs r0, r3 80007b0: f000 f905 bl 80009be 80007b4: 1e03 subs r3, r0, #0 80007b6: d001 beq.n 80007bc { return HAL_ERROR; 80007b8: 2301 movs r3, #1 80007ba: e00f b.n 80007dc } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80007bc: 687b ldr r3, [r7, #4] 80007be: 2b03 cmp r3, #3 80007c0: d80b bhi.n 80007da { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80007c2: 6879 ldr r1, [r7, #4] 80007c4: 2301 movs r3, #1 80007c6: 425b negs r3, r3 80007c8: 2200 movs r2, #0 80007ca: 0018 movs r0, r3 80007cc: f000 f8e2 bl 8000994 uwTickPrio = TickPriority; 80007d0: 4b06 ldr r3, [pc, #24] ; (80007ec ) 80007d2: 687a ldr r2, [r7, #4] 80007d4: 601a str r2, [r3, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 80007d6: 2300 movs r3, #0 80007d8: e000 b.n 80007dc return HAL_ERROR; 80007da: 2301 movs r3, #1 } 80007dc: 0018 movs r0, r3 80007de: 46bd mov sp, r7 80007e0: b003 add sp, #12 80007e2: bd90 pop {r4, r7, pc} 80007e4: 20000000 .word 0x20000000 80007e8: 20000008 .word 0x20000008 80007ec: 20000004 .word 0x20000004 080007f0 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80007f0: b580 push {r7, lr} 80007f2: af00 add r7, sp, #0 uwTick += uwTickFreq; 80007f4: 4b05 ldr r3, [pc, #20] ; (800080c ) 80007f6: 781b ldrb r3, [r3, #0] 80007f8: 001a movs r2, r3 80007fa: 4b05 ldr r3, [pc, #20] ; (8000810 ) 80007fc: 681b ldr r3, [r3, #0] 80007fe: 18d2 adds r2, r2, r3 8000800: 4b03 ldr r3, [pc, #12] ; (8000810 ) 8000802: 601a str r2, [r3, #0] } 8000804: 46c0 nop ; (mov r8, r8) 8000806: 46bd mov sp, r7 8000808: bd80 pop {r7, pc} 800080a: 46c0 nop ; (mov r8, r8) 800080c: 20000008 .word 0x20000008 8000810: 200000d4 .word 0x200000d4 08000814 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8000814: b580 push {r7, lr} 8000816: af00 add r7, sp, #0 return uwTick; 8000818: 4b02 ldr r3, [pc, #8] ; (8000824 ) 800081a: 681b ldr r3, [r3, #0] } 800081c: 0018 movs r0, r3 800081e: 46bd mov sp, r7 8000820: bd80 pop {r7, pc} 8000822: 46c0 nop ; (mov r8, r8) 8000824: 200000d4 .word 0x200000d4 08000828 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8000828: b580 push {r7, lr} 800082a: b084 sub sp, #16 800082c: af00 add r7, sp, #0 800082e: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8000830: f7ff fff0 bl 8000814 8000834: 0003 movs r3, r0 8000836: 60bb str r3, [r7, #8] uint32_t wait = Delay; 8000838: 687b ldr r3, [r7, #4] 800083a: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 800083c: 68fb ldr r3, [r7, #12] 800083e: 3301 adds r3, #1 8000840: d005 beq.n 800084e { wait += (uint32_t)(uwTickFreq); 8000842: 4b0a ldr r3, [pc, #40] ; (800086c ) 8000844: 781b ldrb r3, [r3, #0] 8000846: 001a movs r2, r3 8000848: 68fb ldr r3, [r7, #12] 800084a: 189b adds r3, r3, r2 800084c: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 800084e: 46c0 nop ; (mov r8, r8) 8000850: f7ff ffe0 bl 8000814 8000854: 0002 movs r2, r0 8000856: 68bb ldr r3, [r7, #8] 8000858: 1ad3 subs r3, r2, r3 800085a: 68fa ldr r2, [r7, #12] 800085c: 429a cmp r2, r3 800085e: d8f7 bhi.n 8000850 { } } 8000860: 46c0 nop ; (mov r8, r8) 8000862: 46c0 nop ; (mov r8, r8) 8000864: 46bd mov sp, r7 8000866: b004 add sp, #16 8000868: bd80 pop {r7, pc} 800086a: 46c0 nop ; (mov r8, r8) 800086c: 20000008 .word 0x20000008 08000870 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8000870: b590 push {r4, r7, lr} 8000872: b083 sub sp, #12 8000874: af00 add r7, sp, #0 8000876: 0002 movs r2, r0 8000878: 6039 str r1, [r7, #0] 800087a: 1dfb adds r3, r7, #7 800087c: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 800087e: 1dfb adds r3, r7, #7 8000880: 781b ldrb r3, [r3, #0] 8000882: 2b7f cmp r3, #127 ; 0x7f 8000884: d828 bhi.n 80008d8 <__NVIC_SetPriority+0x68> { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8000886: 4a2f ldr r2, [pc, #188] ; (8000944 <__NVIC_SetPriority+0xd4>) 8000888: 1dfb adds r3, r7, #7 800088a: 781b ldrb r3, [r3, #0] 800088c: b25b sxtb r3, r3 800088e: 089b lsrs r3, r3, #2 8000890: 33c0 adds r3, #192 ; 0xc0 8000892: 009b lsls r3, r3, #2 8000894: 589b ldr r3, [r3, r2] 8000896: 1dfa adds r2, r7, #7 8000898: 7812 ldrb r2, [r2, #0] 800089a: 0011 movs r1, r2 800089c: 2203 movs r2, #3 800089e: 400a ands r2, r1 80008a0: 00d2 lsls r2, r2, #3 80008a2: 21ff movs r1, #255 ; 0xff 80008a4: 4091 lsls r1, r2 80008a6: 000a movs r2, r1 80008a8: 43d2 mvns r2, r2 80008aa: 401a ands r2, r3 80008ac: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 80008ae: 683b ldr r3, [r7, #0] 80008b0: 019b lsls r3, r3, #6 80008b2: 22ff movs r2, #255 ; 0xff 80008b4: 401a ands r2, r3 80008b6: 1dfb adds r3, r7, #7 80008b8: 781b ldrb r3, [r3, #0] 80008ba: 0018 movs r0, r3 80008bc: 2303 movs r3, #3 80008be: 4003 ands r3, r0 80008c0: 00db lsls r3, r3, #3 80008c2: 409a lsls r2, r3 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 80008c4: 481f ldr r0, [pc, #124] ; (8000944 <__NVIC_SetPriority+0xd4>) 80008c6: 1dfb adds r3, r7, #7 80008c8: 781b ldrb r3, [r3, #0] 80008ca: b25b sxtb r3, r3 80008cc: 089b lsrs r3, r3, #2 80008ce: 430a orrs r2, r1 80008d0: 33c0 adds r3, #192 ; 0xc0 80008d2: 009b lsls r3, r3, #2 80008d4: 501a str r2, [r3, r0] else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } 80008d6: e031 b.n 800093c <__NVIC_SetPriority+0xcc> SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 80008d8: 4a1b ldr r2, [pc, #108] ; (8000948 <__NVIC_SetPriority+0xd8>) 80008da: 1dfb adds r3, r7, #7 80008dc: 781b ldrb r3, [r3, #0] 80008de: 0019 movs r1, r3 80008e0: 230f movs r3, #15 80008e2: 400b ands r3, r1 80008e4: 3b08 subs r3, #8 80008e6: 089b lsrs r3, r3, #2 80008e8: 3306 adds r3, #6 80008ea: 009b lsls r3, r3, #2 80008ec: 18d3 adds r3, r2, r3 80008ee: 3304 adds r3, #4 80008f0: 681b ldr r3, [r3, #0] 80008f2: 1dfa adds r2, r7, #7 80008f4: 7812 ldrb r2, [r2, #0] 80008f6: 0011 movs r1, r2 80008f8: 2203 movs r2, #3 80008fa: 400a ands r2, r1 80008fc: 00d2 lsls r2, r2, #3 80008fe: 21ff movs r1, #255 ; 0xff 8000900: 4091 lsls r1, r2 8000902: 000a movs r2, r1 8000904: 43d2 mvns r2, r2 8000906: 401a ands r2, r3 8000908: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 800090a: 683b ldr r3, [r7, #0] 800090c: 019b lsls r3, r3, #6 800090e: 22ff movs r2, #255 ; 0xff 8000910: 401a ands r2, r3 8000912: 1dfb adds r3, r7, #7 8000914: 781b ldrb r3, [r3, #0] 8000916: 0018 movs r0, r3 8000918: 2303 movs r3, #3 800091a: 4003 ands r3, r0 800091c: 00db lsls r3, r3, #3 800091e: 409a lsls r2, r3 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8000920: 4809 ldr r0, [pc, #36] ; (8000948 <__NVIC_SetPriority+0xd8>) 8000922: 1dfb adds r3, r7, #7 8000924: 781b ldrb r3, [r3, #0] 8000926: 001c movs r4, r3 8000928: 230f movs r3, #15 800092a: 4023 ands r3, r4 800092c: 3b08 subs r3, #8 800092e: 089b lsrs r3, r3, #2 8000930: 430a orrs r2, r1 8000932: 3306 adds r3, #6 8000934: 009b lsls r3, r3, #2 8000936: 18c3 adds r3, r0, r3 8000938: 3304 adds r3, #4 800093a: 601a str r2, [r3, #0] } 800093c: 46c0 nop ; (mov r8, r8) 800093e: 46bd mov sp, r7 8000940: b003 add sp, #12 8000942: bd90 pop {r4, r7, pc} 8000944: e000e100 .word 0xe000e100 8000948: e000ed00 .word 0xe000ed00 0800094c : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 800094c: b580 push {r7, lr} 800094e: b082 sub sp, #8 8000950: af00 add r7, sp, #0 8000952: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8000954: 687b ldr r3, [r7, #4] 8000956: 1e5a subs r2, r3, #1 8000958: 2380 movs r3, #128 ; 0x80 800095a: 045b lsls r3, r3, #17 800095c: 429a cmp r2, r3 800095e: d301 bcc.n 8000964 { return (1UL); /* Reload value impossible */ 8000960: 2301 movs r3, #1 8000962: e010 b.n 8000986 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8000964: 4b0a ldr r3, [pc, #40] ; (8000990 ) 8000966: 687a ldr r2, [r7, #4] 8000968: 3a01 subs r2, #1 800096a: 605a str r2, [r3, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800096c: 2301 movs r3, #1 800096e: 425b negs r3, r3 8000970: 2103 movs r1, #3 8000972: 0018 movs r0, r3 8000974: f7ff ff7c bl 8000870 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8000978: 4b05 ldr r3, [pc, #20] ; (8000990 ) 800097a: 2200 movs r2, #0 800097c: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800097e: 4b04 ldr r3, [pc, #16] ; (8000990 ) 8000980: 2207 movs r2, #7 8000982: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8000984: 2300 movs r3, #0 } 8000986: 0018 movs r0, r3 8000988: 46bd mov sp, r7 800098a: b002 add sp, #8 800098c: bd80 pop {r7, pc} 800098e: 46c0 nop ; (mov r8, r8) 8000990: e000e010 .word 0xe000e010 08000994 : * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because * no subpriority supported in Cortex M0 based products. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8000994: b580 push {r7, lr} 8000996: b084 sub sp, #16 8000998: af00 add r7, sp, #0 800099a: 60b9 str r1, [r7, #8] 800099c: 607a str r2, [r7, #4] 800099e: 210f movs r1, #15 80009a0: 187b adds r3, r7, r1 80009a2: 1c02 adds r2, r0, #0 80009a4: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); NVIC_SetPriority(IRQn,PreemptPriority); 80009a6: 68ba ldr r2, [r7, #8] 80009a8: 187b adds r3, r7, r1 80009aa: 781b ldrb r3, [r3, #0] 80009ac: b25b sxtb r3, r3 80009ae: 0011 movs r1, r2 80009b0: 0018 movs r0, r3 80009b2: f7ff ff5d bl 8000870 <__NVIC_SetPriority> } 80009b6: 46c0 nop ; (mov r8, r8) 80009b8: 46bd mov sp, r7 80009ba: b004 add sp, #16 80009bc: bd80 pop {r7, pc} 080009be : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 80009be: b580 push {r7, lr} 80009c0: b082 sub sp, #8 80009c2: af00 add r7, sp, #0 80009c4: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 80009c6: 687b ldr r3, [r7, #4] 80009c8: 0018 movs r0, r3 80009ca: f7ff ffbf bl 800094c 80009ce: 0003 movs r3, r0 } 80009d0: 0018 movs r0, r3 80009d2: 46bd mov sp, r7 80009d4: b002 add sp, #8 80009d6: bd80 pop {r7, pc} 080009d8 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 80009d8: b580 push {r7, lr} 80009da: b086 sub sp, #24 80009dc: af00 add r7, sp, #0 80009de: 6078 str r0, [r7, #4] 80009e0: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 80009e2: 2300 movs r3, #0 80009e4: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 80009e6: e149 b.n 8000c7c { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); 80009e8: 683b ldr r3, [r7, #0] 80009ea: 681b ldr r3, [r3, #0] 80009ec: 2101 movs r1, #1 80009ee: 697a ldr r2, [r7, #20] 80009f0: 4091 lsls r1, r2 80009f2: 000a movs r2, r1 80009f4: 4013 ands r3, r2 80009f6: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 80009f8: 68fb ldr r3, [r7, #12] 80009fa: 2b00 cmp r3, #0 80009fc: d100 bne.n 8000a00 80009fe: e13a b.n 8000c76 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 8000a00: 683b ldr r3, [r7, #0] 8000a02: 685b ldr r3, [r3, #4] 8000a04: 2203 movs r2, #3 8000a06: 4013 ands r3, r2 8000a08: 2b01 cmp r3, #1 8000a0a: d005 beq.n 8000a18 ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8000a0c: 683b ldr r3, [r7, #0] 8000a0e: 685b ldr r3, [r3, #4] 8000a10: 2203 movs r2, #3 8000a12: 4013 ands r3, r2 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 8000a14: 2b02 cmp r3, #2 8000a16: d130 bne.n 8000a7a { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8000a18: 687b ldr r3, [r7, #4] 8000a1a: 689b ldr r3, [r3, #8] 8000a1c: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); 8000a1e: 697b ldr r3, [r7, #20] 8000a20: 005b lsls r3, r3, #1 8000a22: 2203 movs r2, #3 8000a24: 409a lsls r2, r3 8000a26: 0013 movs r3, r2 8000a28: 43da mvns r2, r3 8000a2a: 693b ldr r3, [r7, #16] 8000a2c: 4013 ands r3, r2 8000a2e: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); 8000a30: 683b ldr r3, [r7, #0] 8000a32: 68da ldr r2, [r3, #12] 8000a34: 697b ldr r3, [r7, #20] 8000a36: 005b lsls r3, r3, #1 8000a38: 409a lsls r2, r3 8000a3a: 0013 movs r3, r2 8000a3c: 693a ldr r2, [r7, #16] 8000a3e: 4313 orrs r3, r2 8000a40: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 8000a42: 687b ldr r3, [r7, #4] 8000a44: 693a ldr r2, [r7, #16] 8000a46: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8000a48: 687b ldr r3, [r7, #4] 8000a4a: 685b ldr r3, [r3, #4] 8000a4c: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 8000a4e: 2201 movs r2, #1 8000a50: 697b ldr r3, [r7, #20] 8000a52: 409a lsls r2, r3 8000a54: 0013 movs r3, r2 8000a56: 43da mvns r2, r3 8000a58: 693b ldr r3, [r7, #16] 8000a5a: 4013 ands r3, r2 8000a5c: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8000a5e: 683b ldr r3, [r7, #0] 8000a60: 685b ldr r3, [r3, #4] 8000a62: 091b lsrs r3, r3, #4 8000a64: 2201 movs r2, #1 8000a66: 401a ands r2, r3 8000a68: 697b ldr r3, [r7, #20] 8000a6a: 409a lsls r2, r3 8000a6c: 0013 movs r3, r2 8000a6e: 693a ldr r2, [r7, #16] 8000a70: 4313 orrs r3, r2 8000a72: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 8000a74: 687b ldr r3, [r7, #4] 8000a76: 693a ldr r2, [r7, #16] 8000a78: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8000a7a: 683b ldr r3, [r7, #0] 8000a7c: 685b ldr r3, [r3, #4] 8000a7e: 2203 movs r2, #3 8000a80: 4013 ands r3, r2 8000a82: 2b03 cmp r3, #3 8000a84: d017 beq.n 8000ab6 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8000a86: 687b ldr r3, [r7, #4] 8000a88: 68db ldr r3, [r3, #12] 8000a8a: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); 8000a8c: 697b ldr r3, [r7, #20] 8000a8e: 005b lsls r3, r3, #1 8000a90: 2203 movs r2, #3 8000a92: 409a lsls r2, r3 8000a94: 0013 movs r3, r2 8000a96: 43da mvns r2, r3 8000a98: 693b ldr r3, [r7, #16] 8000a9a: 4013 ands r3, r2 8000a9c: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2u)); 8000a9e: 683b ldr r3, [r7, #0] 8000aa0: 689a ldr r2, [r3, #8] 8000aa2: 697b ldr r3, [r7, #20] 8000aa4: 005b lsls r3, r3, #1 8000aa6: 409a lsls r2, r3 8000aa8: 0013 movs r3, r2 8000aaa: 693a ldr r2, [r7, #16] 8000aac: 4313 orrs r3, r2 8000aae: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 8000ab0: 687b ldr r3, [r7, #4] 8000ab2: 693a ldr r2, [r7, #16] 8000ab4: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8000ab6: 683b ldr r3, [r7, #0] 8000ab8: 685b ldr r3, [r3, #4] 8000aba: 2203 movs r2, #3 8000abc: 4013 ands r3, r2 8000abe: 2b02 cmp r3, #2 8000ac0: d123 bne.n 8000b0a /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; 8000ac2: 697b ldr r3, [r7, #20] 8000ac4: 08da lsrs r2, r3, #3 8000ac6: 687b ldr r3, [r7, #4] 8000ac8: 3208 adds r2, #8 8000aca: 0092 lsls r2, r2, #2 8000acc: 58d3 ldr r3, [r2, r3] 8000ace: 613b str r3, [r7, #16] temp &= ~(0xFu << ((position & 0x07u) * 4u)); 8000ad0: 697b ldr r3, [r7, #20] 8000ad2: 2207 movs r2, #7 8000ad4: 4013 ands r3, r2 8000ad6: 009b lsls r3, r3, #2 8000ad8: 220f movs r2, #15 8000ada: 409a lsls r2, r3 8000adc: 0013 movs r3, r2 8000ade: 43da mvns r2, r3 8000ae0: 693b ldr r3, [r7, #16] 8000ae2: 4013 ands r3, r2 8000ae4: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); 8000ae6: 683b ldr r3, [r7, #0] 8000ae8: 691a ldr r2, [r3, #16] 8000aea: 697b ldr r3, [r7, #20] 8000aec: 2107 movs r1, #7 8000aee: 400b ands r3, r1 8000af0: 009b lsls r3, r3, #2 8000af2: 409a lsls r2, r3 8000af4: 0013 movs r3, r2 8000af6: 693a ldr r2, [r7, #16] 8000af8: 4313 orrs r3, r2 8000afa: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; 8000afc: 697b ldr r3, [r7, #20] 8000afe: 08da lsrs r2, r3, #3 8000b00: 687b ldr r3, [r7, #4] 8000b02: 3208 adds r2, #8 8000b04: 0092 lsls r2, r2, #2 8000b06: 6939 ldr r1, [r7, #16] 8000b08: 50d1 str r1, [r2, r3] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8000b0a: 687b ldr r3, [r7, #4] 8000b0c: 681b ldr r3, [r3, #0] 8000b0e: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); 8000b10: 697b ldr r3, [r7, #20] 8000b12: 005b lsls r3, r3, #1 8000b14: 2203 movs r2, #3 8000b16: 409a lsls r2, r3 8000b18: 0013 movs r3, r2 8000b1a: 43da mvns r2, r3 8000b1c: 693b ldr r3, [r7, #16] 8000b1e: 4013 ands r3, r2 8000b20: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 8000b22: 683b ldr r3, [r7, #0] 8000b24: 685b ldr r3, [r3, #4] 8000b26: 2203 movs r2, #3 8000b28: 401a ands r2, r3 8000b2a: 697b ldr r3, [r7, #20] 8000b2c: 005b lsls r3, r3, #1 8000b2e: 409a lsls r2, r3 8000b30: 0013 movs r3, r2 8000b32: 693a ldr r2, [r7, #16] 8000b34: 4313 orrs r3, r2 8000b36: 613b str r3, [r7, #16] GPIOx->MODER = temp; 8000b38: 687b ldr r3, [r7, #4] 8000b3a: 693a ldr r2, [r7, #16] 8000b3c: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 8000b3e: 683b ldr r3, [r7, #0] 8000b40: 685a ldr r2, [r3, #4] 8000b42: 23c0 movs r3, #192 ; 0xc0 8000b44: 029b lsls r3, r3, #10 8000b46: 4013 ands r3, r2 8000b48: d100 bne.n 8000b4c 8000b4a: e094 b.n 8000c76 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000b4c: 4b51 ldr r3, [pc, #324] ; (8000c94 ) 8000b4e: 699a ldr r2, [r3, #24] 8000b50: 4b50 ldr r3, [pc, #320] ; (8000c94 ) 8000b52: 2101 movs r1, #1 8000b54: 430a orrs r2, r1 8000b56: 619a str r2, [r3, #24] 8000b58: 4b4e ldr r3, [pc, #312] ; (8000c94 ) 8000b5a: 699b ldr r3, [r3, #24] 8000b5c: 2201 movs r2, #1 8000b5e: 4013 ands r3, r2 8000b60: 60bb str r3, [r7, #8] 8000b62: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2u]; 8000b64: 4a4c ldr r2, [pc, #304] ; (8000c98 ) 8000b66: 697b ldr r3, [r7, #20] 8000b68: 089b lsrs r3, r3, #2 8000b6a: 3302 adds r3, #2 8000b6c: 009b lsls r3, r3, #2 8000b6e: 589b ldr r3, [r3, r2] 8000b70: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (4u * (position & 0x03u))); 8000b72: 697b ldr r3, [r7, #20] 8000b74: 2203 movs r2, #3 8000b76: 4013 ands r3, r2 8000b78: 009b lsls r3, r3, #2 8000b7a: 220f movs r2, #15 8000b7c: 409a lsls r2, r3 8000b7e: 0013 movs r3, r2 8000b80: 43da mvns r2, r3 8000b82: 693b ldr r3, [r7, #16] 8000b84: 4013 ands r3, r2 8000b86: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); 8000b88: 687a ldr r2, [r7, #4] 8000b8a: 2390 movs r3, #144 ; 0x90 8000b8c: 05db lsls r3, r3, #23 8000b8e: 429a cmp r2, r3 8000b90: d00d beq.n 8000bae 8000b92: 687b ldr r3, [r7, #4] 8000b94: 4a41 ldr r2, [pc, #260] ; (8000c9c ) 8000b96: 4293 cmp r3, r2 8000b98: d007 beq.n 8000baa 8000b9a: 687b ldr r3, [r7, #4] 8000b9c: 4a40 ldr r2, [pc, #256] ; (8000ca0 ) 8000b9e: 4293 cmp r3, r2 8000ba0: d101 bne.n 8000ba6 8000ba2: 2302 movs r3, #2 8000ba4: e004 b.n 8000bb0 8000ba6: 2305 movs r3, #5 8000ba8: e002 b.n 8000bb0 8000baa: 2301 movs r3, #1 8000bac: e000 b.n 8000bb0 8000bae: 2300 movs r3, #0 8000bb0: 697a ldr r2, [r7, #20] 8000bb2: 2103 movs r1, #3 8000bb4: 400a ands r2, r1 8000bb6: 0092 lsls r2, r2, #2 8000bb8: 4093 lsls r3, r2 8000bba: 693a ldr r2, [r7, #16] 8000bbc: 4313 orrs r3, r2 8000bbe: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2u] = temp; 8000bc0: 4935 ldr r1, [pc, #212] ; (8000c98 ) 8000bc2: 697b ldr r3, [r7, #20] 8000bc4: 089b lsrs r3, r3, #2 8000bc6: 3302 adds r3, #2 8000bc8: 009b lsls r3, r3, #2 8000bca: 693a ldr r2, [r7, #16] 8000bcc: 505a str r2, [r3, r1] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 8000bce: 4b35 ldr r3, [pc, #212] ; (8000ca4 ) 8000bd0: 689b ldr r3, [r3, #8] 8000bd2: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8000bd4: 68fb ldr r3, [r7, #12] 8000bd6: 43da mvns r2, r3 8000bd8: 693b ldr r3, [r7, #16] 8000bda: 4013 ands r3, r2 8000bdc: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) 8000bde: 683b ldr r3, [r7, #0] 8000be0: 685a ldr r2, [r3, #4] 8000be2: 2380 movs r3, #128 ; 0x80 8000be4: 035b lsls r3, r3, #13 8000be6: 4013 ands r3, r2 8000be8: d003 beq.n 8000bf2 { temp |= iocurrent; 8000bea: 693a ldr r2, [r7, #16] 8000bec: 68fb ldr r3, [r7, #12] 8000bee: 4313 orrs r3, r2 8000bf0: 613b str r3, [r7, #16] } EXTI->RTSR = temp; 8000bf2: 4b2c ldr r3, [pc, #176] ; (8000ca4 ) 8000bf4: 693a ldr r2, [r7, #16] 8000bf6: 609a str r2, [r3, #8] temp = EXTI->FTSR; 8000bf8: 4b2a ldr r3, [pc, #168] ; (8000ca4 ) 8000bfa: 68db ldr r3, [r3, #12] 8000bfc: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8000bfe: 68fb ldr r3, [r7, #12] 8000c00: 43da mvns r2, r3 8000c02: 693b ldr r3, [r7, #16] 8000c04: 4013 ands r3, r2 8000c06: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) 8000c08: 683b ldr r3, [r7, #0] 8000c0a: 685a ldr r2, [r3, #4] 8000c0c: 2380 movs r3, #128 ; 0x80 8000c0e: 039b lsls r3, r3, #14 8000c10: 4013 ands r3, r2 8000c12: d003 beq.n 8000c1c { temp |= iocurrent; 8000c14: 693a ldr r2, [r7, #16] 8000c16: 68fb ldr r3, [r7, #12] 8000c18: 4313 orrs r3, r2 8000c1a: 613b str r3, [r7, #16] } EXTI->FTSR = temp; 8000c1c: 4b21 ldr r3, [pc, #132] ; (8000ca4 ) 8000c1e: 693a ldr r2, [r7, #16] 8000c20: 60da str r2, [r3, #12] /* Clear EXTI line configuration */ temp = EXTI->EMR; 8000c22: 4b20 ldr r3, [pc, #128] ; (8000ca4 ) 8000c24: 685b ldr r3, [r3, #4] 8000c26: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8000c28: 68fb ldr r3, [r7, #12] 8000c2a: 43da mvns r2, r3 8000c2c: 693b ldr r3, [r7, #16] 8000c2e: 4013 ands r3, r2 8000c30: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_EVT) != 0x00u) 8000c32: 683b ldr r3, [r7, #0] 8000c34: 685a ldr r2, [r3, #4] 8000c36: 2380 movs r3, #128 ; 0x80 8000c38: 029b lsls r3, r3, #10 8000c3a: 4013 ands r3, r2 8000c3c: d003 beq.n 8000c46 { temp |= iocurrent; 8000c3e: 693a ldr r2, [r7, #16] 8000c40: 68fb ldr r3, [r7, #12] 8000c42: 4313 orrs r3, r2 8000c44: 613b str r3, [r7, #16] } EXTI->EMR = temp; 8000c46: 4b17 ldr r3, [pc, #92] ; (8000ca4 ) 8000c48: 693a ldr r2, [r7, #16] 8000c4a: 605a str r2, [r3, #4] temp = EXTI->IMR; 8000c4c: 4b15 ldr r3, [pc, #84] ; (8000ca4 ) 8000c4e: 681b ldr r3, [r3, #0] 8000c50: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8000c52: 68fb ldr r3, [r7, #12] 8000c54: 43da mvns r2, r3 8000c56: 693b ldr r3, [r7, #16] 8000c58: 4013 ands r3, r2 8000c5a: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_IT) != 0x00u) 8000c5c: 683b ldr r3, [r7, #0] 8000c5e: 685a ldr r2, [r3, #4] 8000c60: 2380 movs r3, #128 ; 0x80 8000c62: 025b lsls r3, r3, #9 8000c64: 4013 ands r3, r2 8000c66: d003 beq.n 8000c70 { temp |= iocurrent; 8000c68: 693a ldr r2, [r7, #16] 8000c6a: 68fb ldr r3, [r7, #12] 8000c6c: 4313 orrs r3, r2 8000c6e: 613b str r3, [r7, #16] } EXTI->IMR = temp; 8000c70: 4b0c ldr r3, [pc, #48] ; (8000ca4 ) 8000c72: 693a ldr r2, [r7, #16] 8000c74: 601a str r2, [r3, #0] } } position++; 8000c76: 697b ldr r3, [r7, #20] 8000c78: 3301 adds r3, #1 8000c7a: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) 8000c7c: 683b ldr r3, [r7, #0] 8000c7e: 681a ldr r2, [r3, #0] 8000c80: 697b ldr r3, [r7, #20] 8000c82: 40da lsrs r2, r3 8000c84: 1e13 subs r3, r2, #0 8000c86: d000 beq.n 8000c8a 8000c88: e6ae b.n 80009e8 } } 8000c8a: 46c0 nop ; (mov r8, r8) 8000c8c: 46c0 nop ; (mov r8, r8) 8000c8e: 46bd mov sp, r7 8000c90: b006 add sp, #24 8000c92: bd80 pop {r7, pc} 8000c94: 40021000 .word 0x40021000 8000c98: 40010000 .word 0x40010000 8000c9c: 48000400 .word 0x48000400 8000ca0: 48000800 .word 0x48000800 8000ca4: 40010400 .word 0x40010400 08000ca8 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 8000ca8: b580 push {r7, lr} 8000caa: b082 sub sp, #8 8000cac: af00 add r7, sp, #0 8000cae: 6078 str r0, [r7, #4] /* Check the I2C handle allocation */ if (hi2c == NULL) 8000cb0: 687b ldr r3, [r7, #4] 8000cb2: 2b00 cmp r3, #0 8000cb4: d101 bne.n 8000cba { return HAL_ERROR; 8000cb6: 2301 movs r3, #1 8000cb8: e082 b.n 8000dc0 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 8000cba: 687b ldr r3, [r7, #4] 8000cbc: 2241 movs r2, #65 ; 0x41 8000cbe: 5c9b ldrb r3, [r3, r2] 8000cc0: b2db uxtb r3, r3 8000cc2: 2b00 cmp r3, #0 8000cc4: d107 bne.n 8000cd6 { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 8000cc6: 687b ldr r3, [r7, #4] 8000cc8: 2240 movs r2, #64 ; 0x40 8000cca: 2100 movs r1, #0 8000ccc: 5499 strb r1, [r3, r2] /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2C_MspInit(hi2c); 8000cce: 687b ldr r3, [r7, #4] 8000cd0: 0018 movs r0, r3 8000cd2: f7ff fc99 bl 8000608 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 8000cd6: 687b ldr r3, [r7, #4] 8000cd8: 2241 movs r2, #65 ; 0x41 8000cda: 2124 movs r1, #36 ; 0x24 8000cdc: 5499 strb r1, [r3, r2] /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8000cde: 687b ldr r3, [r7, #4] 8000ce0: 681b ldr r3, [r3, #0] 8000ce2: 681a ldr r2, [r3, #0] 8000ce4: 687b ldr r3, [r7, #4] 8000ce6: 681b ldr r3, [r3, #0] 8000ce8: 2101 movs r1, #1 8000cea: 438a bics r2, r1 8000cec: 601a str r2, [r3, #0] /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ /* Configure I2Cx: Frequency range */ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; 8000cee: 687b ldr r3, [r7, #4] 8000cf0: 685a ldr r2, [r3, #4] 8000cf2: 687b ldr r3, [r7, #4] 8000cf4: 681b ldr r3, [r3, #0] 8000cf6: 4934 ldr r1, [pc, #208] ; (8000dc8 ) 8000cf8: 400a ands r2, r1 8000cfa: 611a str r2, [r3, #16] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Disable Own Address1 before set the Own Address1 configuration */ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; 8000cfc: 687b ldr r3, [r7, #4] 8000cfe: 681b ldr r3, [r3, #0] 8000d00: 689a ldr r2, [r3, #8] 8000d02: 687b ldr r3, [r7, #4] 8000d04: 681b ldr r3, [r3, #0] 8000d06: 4931 ldr r1, [pc, #196] ; (8000dcc ) 8000d08: 400a ands r2, r1 8000d0a: 609a str r2, [r3, #8] /* Configure I2Cx: Own Address1 and ack own address1 mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) 8000d0c: 687b ldr r3, [r7, #4] 8000d0e: 68db ldr r3, [r3, #12] 8000d10: 2b01 cmp r3, #1 8000d12: d108 bne.n 8000d26 { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); 8000d14: 687b ldr r3, [r7, #4] 8000d16: 689a ldr r2, [r3, #8] 8000d18: 687b ldr r3, [r7, #4] 8000d1a: 681b ldr r3, [r3, #0] 8000d1c: 2180 movs r1, #128 ; 0x80 8000d1e: 0209 lsls r1, r1, #8 8000d20: 430a orrs r2, r1 8000d22: 609a str r2, [r3, #8] 8000d24: e007 b.n 8000d36 } else /* I2C_ADDRESSINGMODE_10BIT */ { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); 8000d26: 687b ldr r3, [r7, #4] 8000d28: 689a ldr r2, [r3, #8] 8000d2a: 687b ldr r3, [r7, #4] 8000d2c: 681b ldr r3, [r3, #0] 8000d2e: 2184 movs r1, #132 ; 0x84 8000d30: 0209 lsls r1, r1, #8 8000d32: 430a orrs r2, r1 8000d34: 609a str r2, [r3, #8] } /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Addressing Master mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) 8000d36: 687b ldr r3, [r7, #4] 8000d38: 68db ldr r3, [r3, #12] 8000d3a: 2b02 cmp r3, #2 8000d3c: d104 bne.n 8000d48 { hi2c->Instance->CR2 = (I2C_CR2_ADD10); 8000d3e: 687b ldr r3, [r7, #4] 8000d40: 681b ldr r3, [r3, #0] 8000d42: 2280 movs r2, #128 ; 0x80 8000d44: 0112 lsls r2, r2, #4 8000d46: 605a str r2, [r3, #4] } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); 8000d48: 687b ldr r3, [r7, #4] 8000d4a: 681b ldr r3, [r3, #0] 8000d4c: 685a ldr r2, [r3, #4] 8000d4e: 687b ldr r3, [r7, #4] 8000d50: 681b ldr r3, [r3, #0] 8000d52: 491f ldr r1, [pc, #124] ; (8000dd0 ) 8000d54: 430a orrs r2, r1 8000d56: 605a str r2, [r3, #4] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Disable Own Address2 before set the Own Address2 configuration */ hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; 8000d58: 687b ldr r3, [r7, #4] 8000d5a: 681b ldr r3, [r3, #0] 8000d5c: 68da ldr r2, [r3, #12] 8000d5e: 687b ldr r3, [r7, #4] 8000d60: 681b ldr r3, [r3, #0] 8000d62: 491a ldr r1, [pc, #104] ; (8000dcc ) 8000d64: 400a ands r2, r1 8000d66: 60da str r2, [r3, #12] /* Configure I2Cx: Dual mode and Own Address2 */ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ 8000d68: 687b ldr r3, [r7, #4] 8000d6a: 691a ldr r2, [r3, #16] 8000d6c: 687b ldr r3, [r7, #4] 8000d6e: 695b ldr r3, [r3, #20] 8000d70: 431a orrs r2, r3 8000d72: 0011 movs r1, r2 (hi2c->Init.OwnAddress2Masks << 8)); 8000d74: 687b ldr r3, [r7, #4] 8000d76: 699b ldr r3, [r3, #24] 8000d78: 021a lsls r2, r3, #8 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ 8000d7a: 687b ldr r3, [r7, #4] 8000d7c: 681b ldr r3, [r3, #0] 8000d7e: 430a orrs r2, r1 8000d80: 60da str r2, [r3, #12] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); 8000d82: 687b ldr r3, [r7, #4] 8000d84: 69d9 ldr r1, [r3, #28] 8000d86: 687b ldr r3, [r7, #4] 8000d88: 6a1a ldr r2, [r3, #32] 8000d8a: 687b ldr r3, [r7, #4] 8000d8c: 681b ldr r3, [r3, #0] 8000d8e: 430a orrs r2, r1 8000d90: 601a str r2, [r3, #0] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8000d92: 687b ldr r3, [r7, #4] 8000d94: 681b ldr r3, [r3, #0] 8000d96: 681a ldr r2, [r3, #0] 8000d98: 687b ldr r3, [r7, #4] 8000d9a: 681b ldr r3, [r3, #0] 8000d9c: 2101 movs r1, #1 8000d9e: 430a orrs r2, r1 8000da0: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8000da2: 687b ldr r3, [r7, #4] 8000da4: 2200 movs r2, #0 8000da6: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; 8000da8: 687b ldr r3, [r7, #4] 8000daa: 2241 movs r2, #65 ; 0x41 8000dac: 2120 movs r1, #32 8000dae: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 8000db0: 687b ldr r3, [r7, #4] 8000db2: 2200 movs r2, #0 8000db4: 631a str r2, [r3, #48] ; 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8000db6: 687b ldr r3, [r7, #4] 8000db8: 2242 movs r2, #66 ; 0x42 8000dba: 2100 movs r1, #0 8000dbc: 5499 strb r1, [r3, r2] return HAL_OK; 8000dbe: 2300 movs r3, #0 } 8000dc0: 0018 movs r0, r3 8000dc2: 46bd mov sp, r7 8000dc4: b002 add sp, #8 8000dc6: bd80 pop {r7, pc} 8000dc8: f0ffffff .word 0xf0ffffff 8000dcc: ffff7fff .word 0xffff7fff 8000dd0: 02008000 .word 0x02008000 08000dd4 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8000dd4: b590 push {r4, r7, lr} 8000dd6: b089 sub sp, #36 ; 0x24 8000dd8: af02 add r7, sp, #8 8000dda: 60f8 str r0, [r7, #12] 8000ddc: 0008 movs r0, r1 8000dde: 607a str r2, [r7, #4] 8000de0: 0019 movs r1, r3 8000de2: 230a movs r3, #10 8000de4: 18fb adds r3, r7, r3 8000de6: 1c02 adds r2, r0, #0 8000de8: 801a strh r2, [r3, #0] 8000dea: 2308 movs r3, #8 8000dec: 18fb adds r3, r7, r3 8000dee: 1c0a adds r2, r1, #0 8000df0: 801a strh r2, [r3, #0] uint32_t tickstart; if (hi2c->State == HAL_I2C_STATE_READY) 8000df2: 68fb ldr r3, [r7, #12] 8000df4: 2241 movs r2, #65 ; 0x41 8000df6: 5c9b ldrb r3, [r3, r2] 8000df8: b2db uxtb r3, r3 8000dfa: 2b20 cmp r3, #32 8000dfc: d000 beq.n 8000e00 8000dfe: e0e7 b.n 8000fd0 { /* Process Locked */ __HAL_LOCK(hi2c); 8000e00: 68fb ldr r3, [r7, #12] 8000e02: 2240 movs r2, #64 ; 0x40 8000e04: 5c9b ldrb r3, [r3, r2] 8000e06: 2b01 cmp r3, #1 8000e08: d101 bne.n 8000e0e 8000e0a: 2302 movs r3, #2 8000e0c: e0e1 b.n 8000fd2 8000e0e: 68fb ldr r3, [r7, #12] 8000e10: 2240 movs r2, #64 ; 0x40 8000e12: 2101 movs r1, #1 8000e14: 5499 strb r1, [r3, r2] /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 8000e16: f7ff fcfd bl 8000814 8000e1a: 0003 movs r3, r0 8000e1c: 617b str r3, [r7, #20] if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) 8000e1e: 2380 movs r3, #128 ; 0x80 8000e20: 0219 lsls r1, r3, #8 8000e22: 68f8 ldr r0, [r7, #12] 8000e24: 697b ldr r3, [r7, #20] 8000e26: 9300 str r3, [sp, #0] 8000e28: 2319 movs r3, #25 8000e2a: 2201 movs r2, #1 8000e2c: f000 fa04 bl 8001238 8000e30: 1e03 subs r3, r0, #0 8000e32: d001 beq.n 8000e38 { return HAL_ERROR; 8000e34: 2301 movs r3, #1 8000e36: e0cc b.n 8000fd2 } hi2c->State = HAL_I2C_STATE_BUSY_TX; 8000e38: 68fb ldr r3, [r7, #12] 8000e3a: 2241 movs r2, #65 ; 0x41 8000e3c: 2121 movs r1, #33 ; 0x21 8000e3e: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_MASTER; 8000e40: 68fb ldr r3, [r7, #12] 8000e42: 2242 movs r2, #66 ; 0x42 8000e44: 2110 movs r1, #16 8000e46: 5499 strb r1, [r3, r2] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8000e48: 68fb ldr r3, [r7, #12] 8000e4a: 2200 movs r2, #0 8000e4c: 645a str r2, [r3, #68] ; 0x44 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 8000e4e: 68fb ldr r3, [r7, #12] 8000e50: 687a ldr r2, [r7, #4] 8000e52: 625a str r2, [r3, #36] ; 0x24 hi2c->XferCount = Size; 8000e54: 68fb ldr r3, [r7, #12] 8000e56: 2208 movs r2, #8 8000e58: 18ba adds r2, r7, r2 8000e5a: 8812 ldrh r2, [r2, #0] 8000e5c: 855a strh r2, [r3, #42] ; 0x2a hi2c->XferISR = NULL; 8000e5e: 68fb ldr r3, [r7, #12] 8000e60: 2200 movs r2, #0 8000e62: 635a str r2, [r3, #52] ; 0x34 /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hi2c->XferCount > MAX_NBYTE_SIZE) 8000e64: 68fb ldr r3, [r7, #12] 8000e66: 8d5b ldrh r3, [r3, #42] ; 0x2a 8000e68: b29b uxth r3, r3 8000e6a: 2bff cmp r3, #255 ; 0xff 8000e6c: d911 bls.n 8000e92 { hi2c->XferSize = MAX_NBYTE_SIZE; 8000e6e: 68fb ldr r3, [r7, #12] 8000e70: 22ff movs r2, #255 ; 0xff 8000e72: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, 8000e74: 68fb ldr r3, [r7, #12] 8000e76: 8d1b ldrh r3, [r3, #40] ; 0x28 8000e78: b2da uxtb r2, r3 8000e7a: 2380 movs r3, #128 ; 0x80 8000e7c: 045c lsls r4, r3, #17 8000e7e: 230a movs r3, #10 8000e80: 18fb adds r3, r7, r3 8000e82: 8819 ldrh r1, [r3, #0] 8000e84: 68f8 ldr r0, [r7, #12] 8000e86: 4b55 ldr r3, [pc, #340] ; (8000fdc ) 8000e88: 9300 str r3, [sp, #0] 8000e8a: 0023 movs r3, r4 8000e8c: f000 fc2e bl 80016ec 8000e90: e075 b.n 8000f7e I2C_GENERATE_START_WRITE); } else { hi2c->XferSize = hi2c->XferCount; 8000e92: 68fb ldr r3, [r7, #12] 8000e94: 8d5b ldrh r3, [r3, #42] ; 0x2a 8000e96: b29a uxth r2, r3 8000e98: 68fb ldr r3, [r7, #12] 8000e9a: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, 8000e9c: 68fb ldr r3, [r7, #12] 8000e9e: 8d1b ldrh r3, [r3, #40] ; 0x28 8000ea0: b2da uxtb r2, r3 8000ea2: 2380 movs r3, #128 ; 0x80 8000ea4: 049c lsls r4, r3, #18 8000ea6: 230a movs r3, #10 8000ea8: 18fb adds r3, r7, r3 8000eaa: 8819 ldrh r1, [r3, #0] 8000eac: 68f8 ldr r0, [r7, #12] 8000eae: 4b4b ldr r3, [pc, #300] ; (8000fdc ) 8000eb0: 9300 str r3, [sp, #0] 8000eb2: 0023 movs r3, r4 8000eb4: f000 fc1a bl 80016ec I2C_GENERATE_START_WRITE); } while (hi2c->XferCount > 0U) 8000eb8: e061 b.n 8000f7e { /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 8000eba: 697a ldr r2, [r7, #20] 8000ebc: 6ab9 ldr r1, [r7, #40] ; 0x28 8000ebe: 68fb ldr r3, [r7, #12] 8000ec0: 0018 movs r0, r3 8000ec2: f000 fa07 bl 80012d4 8000ec6: 1e03 subs r3, r0, #0 8000ec8: d001 beq.n 8000ece { return HAL_ERROR; 8000eca: 2301 movs r3, #1 8000ecc: e081 b.n 8000fd2 } /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; 8000ece: 68fb ldr r3, [r7, #12] 8000ed0: 6a5b ldr r3, [r3, #36] ; 0x24 8000ed2: 781a ldrb r2, [r3, #0] 8000ed4: 68fb ldr r3, [r7, #12] 8000ed6: 681b ldr r3, [r3, #0] 8000ed8: 629a str r2, [r3, #40] ; 0x28 /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8000eda: 68fb ldr r3, [r7, #12] 8000edc: 6a5b ldr r3, [r3, #36] ; 0x24 8000ede: 1c5a adds r2, r3, #1 8000ee0: 68fb ldr r3, [r7, #12] 8000ee2: 625a str r2, [r3, #36] ; 0x24 hi2c->XferCount--; 8000ee4: 68fb ldr r3, [r7, #12] 8000ee6: 8d5b ldrh r3, [r3, #42] ; 0x2a 8000ee8: b29b uxth r3, r3 8000eea: 3b01 subs r3, #1 8000eec: b29a uxth r2, r3 8000eee: 68fb ldr r3, [r7, #12] 8000ef0: 855a strh r2, [r3, #42] ; 0x2a hi2c->XferSize--; 8000ef2: 68fb ldr r3, [r7, #12] 8000ef4: 8d1b ldrh r3, [r3, #40] ; 0x28 8000ef6: 3b01 subs r3, #1 8000ef8: b29a uxth r2, r3 8000efa: 68fb ldr r3, [r7, #12] 8000efc: 851a strh r2, [r3, #40] ; 0x28 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) 8000efe: 68fb ldr r3, [r7, #12] 8000f00: 8d5b ldrh r3, [r3, #42] ; 0x2a 8000f02: b29b uxth r3, r3 8000f04: 2b00 cmp r3, #0 8000f06: d03a beq.n 8000f7e 8000f08: 68fb ldr r3, [r7, #12] 8000f0a: 8d1b ldrh r3, [r3, #40] ; 0x28 8000f0c: 2b00 cmp r3, #0 8000f0e: d136 bne.n 8000f7e { /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) 8000f10: 6aba ldr r2, [r7, #40] ; 0x28 8000f12: 68f8 ldr r0, [r7, #12] 8000f14: 697b ldr r3, [r7, #20] 8000f16: 9300 str r3, [sp, #0] 8000f18: 0013 movs r3, r2 8000f1a: 2200 movs r2, #0 8000f1c: 2180 movs r1, #128 ; 0x80 8000f1e: f000 f98b bl 8001238 8000f22: 1e03 subs r3, r0, #0 8000f24: d001 beq.n 8000f2a { return HAL_ERROR; 8000f26: 2301 movs r3, #1 8000f28: e053 b.n 8000fd2 } if (hi2c->XferCount > MAX_NBYTE_SIZE) 8000f2a: 68fb ldr r3, [r7, #12] 8000f2c: 8d5b ldrh r3, [r3, #42] ; 0x2a 8000f2e: b29b uxth r3, r3 8000f30: 2bff cmp r3, #255 ; 0xff 8000f32: d911 bls.n 8000f58 { hi2c->XferSize = MAX_NBYTE_SIZE; 8000f34: 68fb ldr r3, [r7, #12] 8000f36: 22ff movs r2, #255 ; 0xff 8000f38: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, 8000f3a: 68fb ldr r3, [r7, #12] 8000f3c: 8d1b ldrh r3, [r3, #40] ; 0x28 8000f3e: b2da uxtb r2, r3 8000f40: 2380 movs r3, #128 ; 0x80 8000f42: 045c lsls r4, r3, #17 8000f44: 230a movs r3, #10 8000f46: 18fb adds r3, r7, r3 8000f48: 8819 ldrh r1, [r3, #0] 8000f4a: 68f8 ldr r0, [r7, #12] 8000f4c: 2300 movs r3, #0 8000f4e: 9300 str r3, [sp, #0] 8000f50: 0023 movs r3, r4 8000f52: f000 fbcb bl 80016ec 8000f56: e012 b.n 8000f7e I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; 8000f58: 68fb ldr r3, [r7, #12] 8000f5a: 8d5b ldrh r3, [r3, #42] ; 0x2a 8000f5c: b29a uxth r2, r3 8000f5e: 68fb ldr r3, [r7, #12] 8000f60: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, 8000f62: 68fb ldr r3, [r7, #12] 8000f64: 8d1b ldrh r3, [r3, #40] ; 0x28 8000f66: b2da uxtb r2, r3 8000f68: 2380 movs r3, #128 ; 0x80 8000f6a: 049c lsls r4, r3, #18 8000f6c: 230a movs r3, #10 8000f6e: 18fb adds r3, r7, r3 8000f70: 8819 ldrh r1, [r3, #0] 8000f72: 68f8 ldr r0, [r7, #12] 8000f74: 2300 movs r3, #0 8000f76: 9300 str r3, [sp, #0] 8000f78: 0023 movs r3, r4 8000f7a: f000 fbb7 bl 80016ec while (hi2c->XferCount > 0U) 8000f7e: 68fb ldr r3, [r7, #12] 8000f80: 8d5b ldrh r3, [r3, #42] ; 0x2a 8000f82: b29b uxth r3, r3 8000f84: 2b00 cmp r3, #0 8000f86: d198 bne.n 8000eba } } /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 8000f88: 697a ldr r2, [r7, #20] 8000f8a: 6ab9 ldr r1, [r7, #40] ; 0x28 8000f8c: 68fb ldr r3, [r7, #12] 8000f8e: 0018 movs r0, r3 8000f90: f000 f9e6 bl 8001360 8000f94: 1e03 subs r3, r0, #0 8000f96: d001 beq.n 8000f9c { return HAL_ERROR; 8000f98: 2301 movs r3, #1 8000f9a: e01a b.n 8000fd2 } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 8000f9c: 68fb ldr r3, [r7, #12] 8000f9e: 681b ldr r3, [r3, #0] 8000fa0: 2220 movs r2, #32 8000fa2: 61da str r2, [r3, #28] /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 8000fa4: 68fb ldr r3, [r7, #12] 8000fa6: 681b ldr r3, [r3, #0] 8000fa8: 685a ldr r2, [r3, #4] 8000faa: 68fb ldr r3, [r7, #12] 8000fac: 681b ldr r3, [r3, #0] 8000fae: 490c ldr r1, [pc, #48] ; (8000fe0 ) 8000fb0: 400a ands r2, r1 8000fb2: 605a str r2, [r3, #4] hi2c->State = HAL_I2C_STATE_READY; 8000fb4: 68fb ldr r3, [r7, #12] 8000fb6: 2241 movs r2, #65 ; 0x41 8000fb8: 2120 movs r1, #32 8000fba: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_NONE; 8000fbc: 68fb ldr r3, [r7, #12] 8000fbe: 2242 movs r2, #66 ; 0x42 8000fc0: 2100 movs r1, #0 8000fc2: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8000fc4: 68fb ldr r3, [r7, #12] 8000fc6: 2240 movs r2, #64 ; 0x40 8000fc8: 2100 movs r1, #0 8000fca: 5499 strb r1, [r3, r2] return HAL_OK; 8000fcc: 2300 movs r3, #0 8000fce: e000 b.n 8000fd2 } else { return HAL_BUSY; 8000fd0: 2302 movs r3, #2 } } 8000fd2: 0018 movs r0, r3 8000fd4: 46bd mov sp, r7 8000fd6: b007 add sp, #28 8000fd8: bd90 pop {r4, r7, pc} 8000fda: 46c0 nop ; (mov r8, r8) 8000fdc: 80002000 .word 0x80002000 8000fe0: fe00e800 .word 0xfe00e800 08000fe4 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8000fe4: b590 push {r4, r7, lr} 8000fe6: b089 sub sp, #36 ; 0x24 8000fe8: af02 add r7, sp, #8 8000fea: 60f8 str r0, [r7, #12] 8000fec: 0008 movs r0, r1 8000fee: 607a str r2, [r7, #4] 8000ff0: 0019 movs r1, r3 8000ff2: 230a movs r3, #10 8000ff4: 18fb adds r3, r7, r3 8000ff6: 1c02 adds r2, r0, #0 8000ff8: 801a strh r2, [r3, #0] 8000ffa: 2308 movs r3, #8 8000ffc: 18fb adds r3, r7, r3 8000ffe: 1c0a adds r2, r1, #0 8001000: 801a strh r2, [r3, #0] uint32_t tickstart; if (hi2c->State == HAL_I2C_STATE_READY) 8001002: 68fb ldr r3, [r7, #12] 8001004: 2241 movs r2, #65 ; 0x41 8001006: 5c9b ldrb r3, [r3, r2] 8001008: b2db uxtb r3, r3 800100a: 2b20 cmp r3, #32 800100c: d000 beq.n 8001010 800100e: e0e8 b.n 80011e2 { /* Process Locked */ __HAL_LOCK(hi2c); 8001010: 68fb ldr r3, [r7, #12] 8001012: 2240 movs r2, #64 ; 0x40 8001014: 5c9b ldrb r3, [r3, r2] 8001016: 2b01 cmp r3, #1 8001018: d101 bne.n 800101e 800101a: 2302 movs r3, #2 800101c: e0e2 b.n 80011e4 800101e: 68fb ldr r3, [r7, #12] 8001020: 2240 movs r2, #64 ; 0x40 8001022: 2101 movs r1, #1 8001024: 5499 strb r1, [r3, r2] /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 8001026: f7ff fbf5 bl 8000814 800102a: 0003 movs r3, r0 800102c: 617b str r3, [r7, #20] if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) 800102e: 2380 movs r3, #128 ; 0x80 8001030: 0219 lsls r1, r3, #8 8001032: 68f8 ldr r0, [r7, #12] 8001034: 697b ldr r3, [r7, #20] 8001036: 9300 str r3, [sp, #0] 8001038: 2319 movs r3, #25 800103a: 2201 movs r2, #1 800103c: f000 f8fc bl 8001238 8001040: 1e03 subs r3, r0, #0 8001042: d001 beq.n 8001048 { return HAL_ERROR; 8001044: 2301 movs r3, #1 8001046: e0cd b.n 80011e4 } hi2c->State = HAL_I2C_STATE_BUSY_RX; 8001048: 68fb ldr r3, [r7, #12] 800104a: 2241 movs r2, #65 ; 0x41 800104c: 2122 movs r1, #34 ; 0x22 800104e: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_MASTER; 8001050: 68fb ldr r3, [r7, #12] 8001052: 2242 movs r2, #66 ; 0x42 8001054: 2110 movs r1, #16 8001056: 5499 strb r1, [r3, r2] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8001058: 68fb ldr r3, [r7, #12] 800105a: 2200 movs r2, #0 800105c: 645a str r2, [r3, #68] ; 0x44 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 800105e: 68fb ldr r3, [r7, #12] 8001060: 687a ldr r2, [r7, #4] 8001062: 625a str r2, [r3, #36] ; 0x24 hi2c->XferCount = Size; 8001064: 68fb ldr r3, [r7, #12] 8001066: 2208 movs r2, #8 8001068: 18ba adds r2, r7, r2 800106a: 8812 ldrh r2, [r2, #0] 800106c: 855a strh r2, [r3, #42] ; 0x2a hi2c->XferISR = NULL; 800106e: 68fb ldr r3, [r7, #12] 8001070: 2200 movs r2, #0 8001072: 635a str r2, [r3, #52] ; 0x34 /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hi2c->XferCount > MAX_NBYTE_SIZE) 8001074: 68fb ldr r3, [r7, #12] 8001076: 8d5b ldrh r3, [r3, #42] ; 0x2a 8001078: b29b uxth r3, r3 800107a: 2bff cmp r3, #255 ; 0xff 800107c: d911 bls.n 80010a2 { hi2c->XferSize = MAX_NBYTE_SIZE; 800107e: 68fb ldr r3, [r7, #12] 8001080: 22ff movs r2, #255 ; 0xff 8001082: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, 8001084: 68fb ldr r3, [r7, #12] 8001086: 8d1b ldrh r3, [r3, #40] ; 0x28 8001088: b2da uxtb r2, r3 800108a: 2380 movs r3, #128 ; 0x80 800108c: 045c lsls r4, r3, #17 800108e: 230a movs r3, #10 8001090: 18fb adds r3, r7, r3 8001092: 8819 ldrh r1, [r3, #0] 8001094: 68f8 ldr r0, [r7, #12] 8001096: 4b55 ldr r3, [pc, #340] ; (80011ec ) 8001098: 9300 str r3, [sp, #0] 800109a: 0023 movs r3, r4 800109c: f000 fb26 bl 80016ec 80010a0: e076 b.n 8001190 I2C_GENERATE_START_READ); } else { hi2c->XferSize = hi2c->XferCount; 80010a2: 68fb ldr r3, [r7, #12] 80010a4: 8d5b ldrh r3, [r3, #42] ; 0x2a 80010a6: b29a uxth r2, r3 80010a8: 68fb ldr r3, [r7, #12] 80010aa: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, 80010ac: 68fb ldr r3, [r7, #12] 80010ae: 8d1b ldrh r3, [r3, #40] ; 0x28 80010b0: b2da uxtb r2, r3 80010b2: 2380 movs r3, #128 ; 0x80 80010b4: 049c lsls r4, r3, #18 80010b6: 230a movs r3, #10 80010b8: 18fb adds r3, r7, r3 80010ba: 8819 ldrh r1, [r3, #0] 80010bc: 68f8 ldr r0, [r7, #12] 80010be: 4b4b ldr r3, [pc, #300] ; (80011ec ) 80010c0: 9300 str r3, [sp, #0] 80010c2: 0023 movs r3, r4 80010c4: f000 fb12 bl 80016ec I2C_GENERATE_START_READ); } while (hi2c->XferCount > 0U) 80010c8: e062 b.n 8001190 { /* Wait until RXNE flag is set */ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 80010ca: 697a ldr r2, [r7, #20] 80010cc: 6ab9 ldr r1, [r7, #40] ; 0x28 80010ce: 68fb ldr r3, [r7, #12] 80010d0: 0018 movs r0, r3 80010d2: f000 f989 bl 80013e8 80010d6: 1e03 subs r3, r0, #0 80010d8: d001 beq.n 80010de { return HAL_ERROR; 80010da: 2301 movs r3, #1 80010dc: e082 b.n 80011e4 } /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; 80010de: 68fb ldr r3, [r7, #12] 80010e0: 681b ldr r3, [r3, #0] 80010e2: 6a5a ldr r2, [r3, #36] ; 0x24 80010e4: 68fb ldr r3, [r7, #12] 80010e6: 6a5b ldr r3, [r3, #36] ; 0x24 80010e8: b2d2 uxtb r2, r2 80010ea: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80010ec: 68fb ldr r3, [r7, #12] 80010ee: 6a5b ldr r3, [r3, #36] ; 0x24 80010f0: 1c5a adds r2, r3, #1 80010f2: 68fb ldr r3, [r7, #12] 80010f4: 625a str r2, [r3, #36] ; 0x24 hi2c->XferSize--; 80010f6: 68fb ldr r3, [r7, #12] 80010f8: 8d1b ldrh r3, [r3, #40] ; 0x28 80010fa: 3b01 subs r3, #1 80010fc: b29a uxth r2, r3 80010fe: 68fb ldr r3, [r7, #12] 8001100: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 8001102: 68fb ldr r3, [r7, #12] 8001104: 8d5b ldrh r3, [r3, #42] ; 0x2a 8001106: b29b uxth r3, r3 8001108: 3b01 subs r3, #1 800110a: b29a uxth r2, r3 800110c: 68fb ldr r3, [r7, #12] 800110e: 855a strh r2, [r3, #42] ; 0x2a if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) 8001110: 68fb ldr r3, [r7, #12] 8001112: 8d5b ldrh r3, [r3, #42] ; 0x2a 8001114: b29b uxth r3, r3 8001116: 2b00 cmp r3, #0 8001118: d03a beq.n 8001190 800111a: 68fb ldr r3, [r7, #12] 800111c: 8d1b ldrh r3, [r3, #40] ; 0x28 800111e: 2b00 cmp r3, #0 8001120: d136 bne.n 8001190 { /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) 8001122: 6aba ldr r2, [r7, #40] ; 0x28 8001124: 68f8 ldr r0, [r7, #12] 8001126: 697b ldr r3, [r7, #20] 8001128: 9300 str r3, [sp, #0] 800112a: 0013 movs r3, r2 800112c: 2200 movs r2, #0 800112e: 2180 movs r1, #128 ; 0x80 8001130: f000 f882 bl 8001238 8001134: 1e03 subs r3, r0, #0 8001136: d001 beq.n 800113c { return HAL_ERROR; 8001138: 2301 movs r3, #1 800113a: e053 b.n 80011e4 } if (hi2c->XferCount > MAX_NBYTE_SIZE) 800113c: 68fb ldr r3, [r7, #12] 800113e: 8d5b ldrh r3, [r3, #42] ; 0x2a 8001140: b29b uxth r3, r3 8001142: 2bff cmp r3, #255 ; 0xff 8001144: d911 bls.n 800116a { hi2c->XferSize = MAX_NBYTE_SIZE; 8001146: 68fb ldr r3, [r7, #12] 8001148: 22ff movs r2, #255 ; 0xff 800114a: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, 800114c: 68fb ldr r3, [r7, #12] 800114e: 8d1b ldrh r3, [r3, #40] ; 0x28 8001150: b2da uxtb r2, r3 8001152: 2380 movs r3, #128 ; 0x80 8001154: 045c lsls r4, r3, #17 8001156: 230a movs r3, #10 8001158: 18fb adds r3, r7, r3 800115a: 8819 ldrh r1, [r3, #0] 800115c: 68f8 ldr r0, [r7, #12] 800115e: 2300 movs r3, #0 8001160: 9300 str r3, [sp, #0] 8001162: 0023 movs r3, r4 8001164: f000 fac2 bl 80016ec 8001168: e012 b.n 8001190 I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; 800116a: 68fb ldr r3, [r7, #12] 800116c: 8d5b ldrh r3, [r3, #42] ; 0x2a 800116e: b29a uxth r2, r3 8001170: 68fb ldr r3, [r7, #12] 8001172: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, 8001174: 68fb ldr r3, [r7, #12] 8001176: 8d1b ldrh r3, [r3, #40] ; 0x28 8001178: b2da uxtb r2, r3 800117a: 2380 movs r3, #128 ; 0x80 800117c: 049c lsls r4, r3, #18 800117e: 230a movs r3, #10 8001180: 18fb adds r3, r7, r3 8001182: 8819 ldrh r1, [r3, #0] 8001184: 68f8 ldr r0, [r7, #12] 8001186: 2300 movs r3, #0 8001188: 9300 str r3, [sp, #0] 800118a: 0023 movs r3, r4 800118c: f000 faae bl 80016ec while (hi2c->XferCount > 0U) 8001190: 68fb ldr r3, [r7, #12] 8001192: 8d5b ldrh r3, [r3, #42] ; 0x2a 8001194: b29b uxth r3, r3 8001196: 2b00 cmp r3, #0 8001198: d197 bne.n 80010ca } } /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 800119a: 697a ldr r2, [r7, #20] 800119c: 6ab9 ldr r1, [r7, #40] ; 0x28 800119e: 68fb ldr r3, [r7, #12] 80011a0: 0018 movs r0, r3 80011a2: f000 f8dd bl 8001360 80011a6: 1e03 subs r3, r0, #0 80011a8: d001 beq.n 80011ae { return HAL_ERROR; 80011aa: 2301 movs r3, #1 80011ac: e01a b.n 80011e4 } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 80011ae: 68fb ldr r3, [r7, #12] 80011b0: 681b ldr r3, [r3, #0] 80011b2: 2220 movs r2, #32 80011b4: 61da str r2, [r3, #28] /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 80011b6: 68fb ldr r3, [r7, #12] 80011b8: 681b ldr r3, [r3, #0] 80011ba: 685a ldr r2, [r3, #4] 80011bc: 68fb ldr r3, [r7, #12] 80011be: 681b ldr r3, [r3, #0] 80011c0: 490b ldr r1, [pc, #44] ; (80011f0 ) 80011c2: 400a ands r2, r1 80011c4: 605a str r2, [r3, #4] hi2c->State = HAL_I2C_STATE_READY; 80011c6: 68fb ldr r3, [r7, #12] 80011c8: 2241 movs r2, #65 ; 0x41 80011ca: 2120 movs r1, #32 80011cc: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_NONE; 80011ce: 68fb ldr r3, [r7, #12] 80011d0: 2242 movs r2, #66 ; 0x42 80011d2: 2100 movs r1, #0 80011d4: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80011d6: 68fb ldr r3, [r7, #12] 80011d8: 2240 movs r2, #64 ; 0x40 80011da: 2100 movs r1, #0 80011dc: 5499 strb r1, [r3, r2] return HAL_OK; 80011de: 2300 movs r3, #0 80011e0: e000 b.n 80011e4 } else { return HAL_BUSY; 80011e2: 2302 movs r3, #2 } } 80011e4: 0018 movs r0, r3 80011e6: 46bd mov sp, r7 80011e8: b007 add sp, #28 80011ea: bd90 pop {r4, r7, pc} 80011ec: 80002400 .word 0x80002400 80011f0: fe00e800 .word 0xfe00e800 080011f4 : * @brief I2C Tx data register flush process. * @param hi2c I2C handle. * @retval None */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) { 80011f4: b580 push {r7, lr} 80011f6: b082 sub sp, #8 80011f8: af00 add r7, sp, #0 80011fa: 6078 str r0, [r7, #4] /* If a pending TXIS flag is set */ /* Write a dummy data in TXDR to clear it */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) 80011fc: 687b ldr r3, [r7, #4] 80011fe: 681b ldr r3, [r3, #0] 8001200: 699b ldr r3, [r3, #24] 8001202: 2202 movs r2, #2 8001204: 4013 ands r3, r2 8001206: 2b02 cmp r3, #2 8001208: d103 bne.n 8001212 { hi2c->Instance->TXDR = 0x00U; 800120a: 687b ldr r3, [r7, #4] 800120c: 681b ldr r3, [r3, #0] 800120e: 2200 movs r2, #0 8001210: 629a str r2, [r3, #40] ; 0x28 } /* Flush TX register if not empty */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) 8001212: 687b ldr r3, [r7, #4] 8001214: 681b ldr r3, [r3, #0] 8001216: 699b ldr r3, [r3, #24] 8001218: 2201 movs r2, #1 800121a: 4013 ands r3, r2 800121c: 2b01 cmp r3, #1 800121e: d007 beq.n 8001230 { __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); 8001220: 687b ldr r3, [r7, #4] 8001222: 681b ldr r3, [r3, #0] 8001224: 699a ldr r2, [r3, #24] 8001226: 687b ldr r3, [r7, #4] 8001228: 681b ldr r3, [r3, #0] 800122a: 2101 movs r1, #1 800122c: 430a orrs r2, r1 800122e: 619a str r2, [r3, #24] } } 8001230: 46c0 nop ; (mov r8, r8) 8001232: 46bd mov sp, r7 8001234: b002 add sp, #8 8001236: bd80 pop {r7, pc} 08001238 : * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) { 8001238: b580 push {r7, lr} 800123a: b084 sub sp, #16 800123c: af00 add r7, sp, #0 800123e: 60f8 str r0, [r7, #12] 8001240: 60b9 str r1, [r7, #8] 8001242: 603b str r3, [r7, #0] 8001244: 1dfb adds r3, r7, #7 8001246: 701a strb r2, [r3, #0] while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) 8001248: e030 b.n 80012ac { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 800124a: 683b ldr r3, [r7, #0] 800124c: 3301 adds r3, #1 800124e: d02d beq.n 80012ac { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8001250: f7ff fae0 bl 8000814 8001254: 0002 movs r2, r0 8001256: 69bb ldr r3, [r7, #24] 8001258: 1ad3 subs r3, r2, r3 800125a: 683a ldr r2, [r7, #0] 800125c: 429a cmp r2, r3 800125e: d302 bcc.n 8001266 8001260: 683b ldr r3, [r7, #0] 8001262: 2b00 cmp r3, #0 8001264: d122 bne.n 80012ac { if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) 8001266: 68fb ldr r3, [r7, #12] 8001268: 681b ldr r3, [r3, #0] 800126a: 699b ldr r3, [r3, #24] 800126c: 68ba ldr r2, [r7, #8] 800126e: 4013 ands r3, r2 8001270: 68ba ldr r2, [r7, #8] 8001272: 1ad3 subs r3, r2, r3 8001274: 425a negs r2, r3 8001276: 4153 adcs r3, r2 8001278: b2db uxtb r3, r3 800127a: 001a movs r2, r3 800127c: 1dfb adds r3, r7, #7 800127e: 781b ldrb r3, [r3, #0] 8001280: 429a cmp r2, r3 8001282: d113 bne.n 80012ac { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 8001284: 68fb ldr r3, [r7, #12] 8001286: 6c5b ldr r3, [r3, #68] ; 0x44 8001288: 2220 movs r2, #32 800128a: 431a orrs r2, r3 800128c: 68fb ldr r3, [r7, #12] 800128e: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; 8001290: 68fb ldr r3, [r7, #12] 8001292: 2241 movs r2, #65 ; 0x41 8001294: 2120 movs r1, #32 8001296: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_NONE; 8001298: 68fb ldr r3, [r7, #12] 800129a: 2242 movs r2, #66 ; 0x42 800129c: 2100 movs r1, #0 800129e: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80012a0: 68fb ldr r3, [r7, #12] 80012a2: 2240 movs r2, #64 ; 0x40 80012a4: 2100 movs r1, #0 80012a6: 5499 strb r1, [r3, r2] return HAL_ERROR; 80012a8: 2301 movs r3, #1 80012aa: e00f b.n 80012cc while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) 80012ac: 68fb ldr r3, [r7, #12] 80012ae: 681b ldr r3, [r3, #0] 80012b0: 699b ldr r3, [r3, #24] 80012b2: 68ba ldr r2, [r7, #8] 80012b4: 4013 ands r3, r2 80012b6: 68ba ldr r2, [r7, #8] 80012b8: 1ad3 subs r3, r2, r3 80012ba: 425a negs r2, r3 80012bc: 4153 adcs r3, r2 80012be: b2db uxtb r3, r3 80012c0: 001a movs r2, r3 80012c2: 1dfb adds r3, r7, #7 80012c4: 781b ldrb r3, [r3, #0] 80012c6: 429a cmp r2, r3 80012c8: d0bf beq.n 800124a } } } } return HAL_OK; 80012ca: 2300 movs r3, #0 } 80012cc: 0018 movs r0, r3 80012ce: 46bd mov sp, r7 80012d0: b004 add sp, #16 80012d2: bd80 pop {r7, pc} 080012d4 : * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { 80012d4: b580 push {r7, lr} 80012d6: b084 sub sp, #16 80012d8: af00 add r7, sp, #0 80012da: 60f8 str r0, [r7, #12] 80012dc: 60b9 str r1, [r7, #8] 80012de: 607a str r2, [r7, #4] while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) 80012e0: e032 b.n 8001348 { /* Check if an error is detected */ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) 80012e2: 687a ldr r2, [r7, #4] 80012e4: 68b9 ldr r1, [r7, #8] 80012e6: 68fb ldr r3, [r7, #12] 80012e8: 0018 movs r0, r3 80012ea: f000 f8ff bl 80014ec 80012ee: 1e03 subs r3, r0, #0 80012f0: d001 beq.n 80012f6 { return HAL_ERROR; 80012f2: 2301 movs r3, #1 80012f4: e030 b.n 8001358 } /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 80012f6: 68bb ldr r3, [r7, #8] 80012f8: 3301 adds r3, #1 80012fa: d025 beq.n 8001348 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 80012fc: f7ff fa8a bl 8000814 8001300: 0002 movs r2, r0 8001302: 687b ldr r3, [r7, #4] 8001304: 1ad3 subs r3, r2, r3 8001306: 68ba ldr r2, [r7, #8] 8001308: 429a cmp r2, r3 800130a: d302 bcc.n 8001312 800130c: 68bb ldr r3, [r7, #8] 800130e: 2b00 cmp r3, #0 8001310: d11a bne.n 8001348 { if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) 8001312: 68fb ldr r3, [r7, #12] 8001314: 681b ldr r3, [r3, #0] 8001316: 699b ldr r3, [r3, #24] 8001318: 2202 movs r2, #2 800131a: 4013 ands r3, r2 800131c: 2b02 cmp r3, #2 800131e: d013 beq.n 8001348 { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 8001320: 68fb ldr r3, [r7, #12] 8001322: 6c5b ldr r3, [r3, #68] ; 0x44 8001324: 2220 movs r2, #32 8001326: 431a orrs r2, r3 8001328: 68fb ldr r3, [r7, #12] 800132a: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; 800132c: 68fb ldr r3, [r7, #12] 800132e: 2241 movs r2, #65 ; 0x41 8001330: 2120 movs r1, #32 8001332: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_NONE; 8001334: 68fb ldr r3, [r7, #12] 8001336: 2242 movs r2, #66 ; 0x42 8001338: 2100 movs r1, #0 800133a: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800133c: 68fb ldr r3, [r7, #12] 800133e: 2240 movs r2, #64 ; 0x40 8001340: 2100 movs r1, #0 8001342: 5499 strb r1, [r3, r2] return HAL_ERROR; 8001344: 2301 movs r3, #1 8001346: e007 b.n 8001358 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) 8001348: 68fb ldr r3, [r7, #12] 800134a: 681b ldr r3, [r3, #0] 800134c: 699b ldr r3, [r3, #24] 800134e: 2202 movs r2, #2 8001350: 4013 ands r3, r2 8001352: 2b02 cmp r3, #2 8001354: d1c5 bne.n 80012e2 } } } } return HAL_OK; 8001356: 2300 movs r3, #0 } 8001358: 0018 movs r0, r3 800135a: 46bd mov sp, r7 800135c: b004 add sp, #16 800135e: bd80 pop {r7, pc} 08001360 : * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { 8001360: b580 push {r7, lr} 8001362: b084 sub sp, #16 8001364: af00 add r7, sp, #0 8001366: 60f8 str r0, [r7, #12] 8001368: 60b9 str r1, [r7, #8] 800136a: 607a str r2, [r7, #4] while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) 800136c: e02f b.n 80013ce { /* Check if an error is detected */ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) 800136e: 687a ldr r2, [r7, #4] 8001370: 68b9 ldr r1, [r7, #8] 8001372: 68fb ldr r3, [r7, #12] 8001374: 0018 movs r0, r3 8001376: f000 f8b9 bl 80014ec 800137a: 1e03 subs r3, r0, #0 800137c: d001 beq.n 8001382 { return HAL_ERROR; 800137e: 2301 movs r3, #1 8001380: e02d b.n 80013de } /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8001382: f7ff fa47 bl 8000814 8001386: 0002 movs r2, r0 8001388: 687b ldr r3, [r7, #4] 800138a: 1ad3 subs r3, r2, r3 800138c: 68ba ldr r2, [r7, #8] 800138e: 429a cmp r2, r3 8001390: d302 bcc.n 8001398 8001392: 68bb ldr r3, [r7, #8] 8001394: 2b00 cmp r3, #0 8001396: d11a bne.n 80013ce { if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) 8001398: 68fb ldr r3, [r7, #12] 800139a: 681b ldr r3, [r3, #0] 800139c: 699b ldr r3, [r3, #24] 800139e: 2220 movs r2, #32 80013a0: 4013 ands r3, r2 80013a2: 2b20 cmp r3, #32 80013a4: d013 beq.n 80013ce { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 80013a6: 68fb ldr r3, [r7, #12] 80013a8: 6c5b ldr r3, [r3, #68] ; 0x44 80013aa: 2220 movs r2, #32 80013ac: 431a orrs r2, r3 80013ae: 68fb ldr r3, [r7, #12] 80013b0: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; 80013b2: 68fb ldr r3, [r7, #12] 80013b4: 2241 movs r2, #65 ; 0x41 80013b6: 2120 movs r1, #32 80013b8: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_NONE; 80013ba: 68fb ldr r3, [r7, #12] 80013bc: 2242 movs r2, #66 ; 0x42 80013be: 2100 movs r1, #0 80013c0: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80013c2: 68fb ldr r3, [r7, #12] 80013c4: 2240 movs r2, #64 ; 0x40 80013c6: 2100 movs r1, #0 80013c8: 5499 strb r1, [r3, r2] return HAL_ERROR; 80013ca: 2301 movs r3, #1 80013cc: e007 b.n 80013de while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) 80013ce: 68fb ldr r3, [r7, #12] 80013d0: 681b ldr r3, [r3, #0] 80013d2: 699b ldr r3, [r3, #24] 80013d4: 2220 movs r2, #32 80013d6: 4013 ands r3, r2 80013d8: 2b20 cmp r3, #32 80013da: d1c8 bne.n 800136e } } } return HAL_OK; 80013dc: 2300 movs r3, #0 } 80013de: 0018 movs r0, r3 80013e0: 46bd mov sp, r7 80013e2: b004 add sp, #16 80013e4: bd80 pop {r7, pc} ... 080013e8 : * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { 80013e8: b580 push {r7, lr} 80013ea: b084 sub sp, #16 80013ec: af00 add r7, sp, #0 80013ee: 60f8 str r0, [r7, #12] 80013f0: 60b9 str r1, [r7, #8] 80013f2: 607a str r2, [r7, #4] while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) 80013f4: e06b b.n 80014ce { /* Check if an error is detected */ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) 80013f6: 687a ldr r2, [r7, #4] 80013f8: 68b9 ldr r1, [r7, #8] 80013fa: 68fb ldr r3, [r7, #12] 80013fc: 0018 movs r0, r3 80013fe: f000 f875 bl 80014ec 8001402: 1e03 subs r3, r0, #0 8001404: d001 beq.n 800140a { return HAL_ERROR; 8001406: 2301 movs r3, #1 8001408: e069 b.n 80014de } /* Check if a STOPF is detected */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) 800140a: 68fb ldr r3, [r7, #12] 800140c: 681b ldr r3, [r3, #0] 800140e: 699b ldr r3, [r3, #24] 8001410: 2220 movs r2, #32 8001412: 4013 ands r3, r2 8001414: 2b20 cmp r3, #32 8001416: d138 bne.n 800148a { /* Check if an RXNE is pending */ /* Store Last receive data if any */ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) 8001418: 68fb ldr r3, [r7, #12] 800141a: 681b ldr r3, [r3, #0] 800141c: 699b ldr r3, [r3, #24] 800141e: 2204 movs r2, #4 8001420: 4013 ands r3, r2 8001422: 2b04 cmp r3, #4 8001424: d105 bne.n 8001432 8001426: 68fb ldr r3, [r7, #12] 8001428: 8d1b ldrh r3, [r3, #40] ; 0x28 800142a: 2b00 cmp r3, #0 800142c: d001 beq.n 8001432 { /* Return HAL_OK */ /* The Reading of data from RXDR will be done in caller function */ return HAL_OK; 800142e: 2300 movs r3, #0 8001430: e055 b.n 80014de } else { if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) 8001432: 68fb ldr r3, [r7, #12] 8001434: 681b ldr r3, [r3, #0] 8001436: 699b ldr r3, [r3, #24] 8001438: 2210 movs r2, #16 800143a: 4013 ands r3, r2 800143c: 2b10 cmp r3, #16 800143e: d107 bne.n 8001450 { __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8001440: 68fb ldr r3, [r7, #12] 8001442: 681b ldr r3, [r3, #0] 8001444: 2210 movs r2, #16 8001446: 61da str r2, [r3, #28] hi2c->ErrorCode = HAL_I2C_ERROR_AF; 8001448: 68fb ldr r3, [r7, #12] 800144a: 2204 movs r2, #4 800144c: 645a str r2, [r3, #68] ; 0x44 800144e: e002 b.n 8001456 } else { hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8001450: 68fb ldr r3, [r7, #12] 8001452: 2200 movs r2, #0 8001454: 645a str r2, [r3, #68] ; 0x44 } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 8001456: 68fb ldr r3, [r7, #12] 8001458: 681b ldr r3, [r3, #0] 800145a: 2220 movs r2, #32 800145c: 61da str r2, [r3, #28] /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 800145e: 68fb ldr r3, [r7, #12] 8001460: 681b ldr r3, [r3, #0] 8001462: 685a ldr r2, [r3, #4] 8001464: 68fb ldr r3, [r7, #12] 8001466: 681b ldr r3, [r3, #0] 8001468: 491f ldr r1, [pc, #124] ; (80014e8 ) 800146a: 400a ands r2, r1 800146c: 605a str r2, [r3, #4] hi2c->State = HAL_I2C_STATE_READY; 800146e: 68fb ldr r3, [r7, #12] 8001470: 2241 movs r2, #65 ; 0x41 8001472: 2120 movs r1, #32 8001474: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_NONE; 8001476: 68fb ldr r3, [r7, #12] 8001478: 2242 movs r2, #66 ; 0x42 800147a: 2100 movs r1, #0 800147c: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800147e: 68fb ldr r3, [r7, #12] 8001480: 2240 movs r2, #64 ; 0x40 8001482: 2100 movs r1, #0 8001484: 5499 strb r1, [r3, r2] return HAL_ERROR; 8001486: 2301 movs r3, #1 8001488: e029 b.n 80014de } } /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 800148a: f7ff f9c3 bl 8000814 800148e: 0002 movs r2, r0 8001490: 687b ldr r3, [r7, #4] 8001492: 1ad3 subs r3, r2, r3 8001494: 68ba ldr r2, [r7, #8] 8001496: 429a cmp r2, r3 8001498: d302 bcc.n 80014a0 800149a: 68bb ldr r3, [r7, #8] 800149c: 2b00 cmp r3, #0 800149e: d116 bne.n 80014ce { if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) 80014a0: 68fb ldr r3, [r7, #12] 80014a2: 681b ldr r3, [r3, #0] 80014a4: 699b ldr r3, [r3, #24] 80014a6: 2204 movs r2, #4 80014a8: 4013 ands r3, r2 80014aa: 2b04 cmp r3, #4 80014ac: d00f beq.n 80014ce { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 80014ae: 68fb ldr r3, [r7, #12] 80014b0: 6c5b ldr r3, [r3, #68] ; 0x44 80014b2: 2220 movs r2, #32 80014b4: 431a orrs r2, r3 80014b6: 68fb ldr r3, [r7, #12] 80014b8: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; 80014ba: 68fb ldr r3, [r7, #12] 80014bc: 2241 movs r2, #65 ; 0x41 80014be: 2120 movs r1, #32 80014c0: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80014c2: 68fb ldr r3, [r7, #12] 80014c4: 2240 movs r2, #64 ; 0x40 80014c6: 2100 movs r1, #0 80014c8: 5499 strb r1, [r3, r2] return HAL_ERROR; 80014ca: 2301 movs r3, #1 80014cc: e007 b.n 80014de while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) 80014ce: 68fb ldr r3, [r7, #12] 80014d0: 681b ldr r3, [r3, #0] 80014d2: 699b ldr r3, [r3, #24] 80014d4: 2204 movs r2, #4 80014d6: 4013 ands r3, r2 80014d8: 2b04 cmp r3, #4 80014da: d18c bne.n 80013f6 } } } return HAL_OK; 80014dc: 2300 movs r3, #0 } 80014de: 0018 movs r0, r3 80014e0: 46bd mov sp, r7 80014e2: b004 add sp, #16 80014e4: bd80 pop {r7, pc} 80014e6: 46c0 nop ; (mov r8, r8) 80014e8: fe00e800 .word 0xfe00e800 080014ec : * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { 80014ec: b590 push {r4, r7, lr} 80014ee: b08b sub sp, #44 ; 0x2c 80014f0: af00 add r7, sp, #0 80014f2: 60f8 str r0, [r7, #12] 80014f4: 60b9 str r1, [r7, #8] 80014f6: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80014f8: 2327 movs r3, #39 ; 0x27 80014fa: 18fb adds r3, r7, r3 80014fc: 2200 movs r2, #0 80014fe: 701a strb r2, [r3, #0] uint32_t itflag = hi2c->Instance->ISR; 8001500: 68fb ldr r3, [r7, #12] 8001502: 681b ldr r3, [r3, #0] 8001504: 699b ldr r3, [r3, #24] 8001506: 61bb str r3, [r7, #24] uint32_t error_code = 0; 8001508: 2300 movs r3, #0 800150a: 623b str r3, [r7, #32] uint32_t tickstart = Tickstart; 800150c: 687b ldr r3, [r7, #4] 800150e: 61fb str r3, [r7, #28] uint32_t tmp1; HAL_I2C_ModeTypeDef tmp2; if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) 8001510: 69bb ldr r3, [r7, #24] 8001512: 2210 movs r2, #16 8001514: 4013 ands r3, r2 8001516: d100 bne.n 800151a 8001518: e082 b.n 8001620 { /* Clear NACKF Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 800151a: 68fb ldr r3, [r7, #12] 800151c: 681b ldr r3, [r3, #0] 800151e: 2210 movs r2, #16 8001520: 61da str r2, [r3, #28] /* Wait until STOP Flag is set or timeout occurred */ /* AutoEnd should be initiate after AF */ while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) 8001522: e060 b.n 80015e6 8001524: 2427 movs r4, #39 ; 0x27 8001526: 193b adds r3, r7, r4 8001528: 193a adds r2, r7, r4 800152a: 7812 ldrb r2, [r2, #0] 800152c: 701a strb r2, [r3, #0] { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 800152e: 68bb ldr r3, [r7, #8] 8001530: 3301 adds r3, #1 8001532: d058 beq.n 80015e6 { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) 8001534: f7ff f96e bl 8000814 8001538: 0002 movs r2, r0 800153a: 69fb ldr r3, [r7, #28] 800153c: 1ad3 subs r3, r2, r3 800153e: 68ba ldr r2, [r7, #8] 8001540: 429a cmp r2, r3 8001542: d306 bcc.n 8001552 8001544: 193b adds r3, r7, r4 8001546: 193a adds r2, r7, r4 8001548: 7812 ldrb r2, [r2, #0] 800154a: 701a strb r2, [r3, #0] 800154c: 68bb ldr r3, [r7, #8] 800154e: 2b00 cmp r3, #0 8001550: d149 bne.n 80015e6 { tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); 8001552: 68fb ldr r3, [r7, #12] 8001554: 681b ldr r3, [r3, #0] 8001556: 685a ldr r2, [r3, #4] 8001558: 2380 movs r3, #128 ; 0x80 800155a: 01db lsls r3, r3, #7 800155c: 4013 ands r3, r2 800155e: 617b str r3, [r7, #20] tmp2 = hi2c->Mode; 8001560: 2013 movs r0, #19 8001562: 183b adds r3, r7, r0 8001564: 68fa ldr r2, [r7, #12] 8001566: 2142 movs r1, #66 ; 0x42 8001568: 5c52 ldrb r2, [r2, r1] 800156a: 701a strb r2, [r3, #0] /* In case of I2C still busy, try to regenerate a STOP manually */ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ 800156c: 68fb ldr r3, [r7, #12] 800156e: 681b ldr r3, [r3, #0] 8001570: 699a ldr r2, [r3, #24] 8001572: 2380 movs r3, #128 ; 0x80 8001574: 021b lsls r3, r3, #8 8001576: 401a ands r2, r3 8001578: 2380 movs r3, #128 ; 0x80 800157a: 021b lsls r3, r3, #8 800157c: 429a cmp r2, r3 800157e: d126 bne.n 80015ce 8001580: 697a ldr r2, [r7, #20] 8001582: 2380 movs r3, #128 ; 0x80 8001584: 01db lsls r3, r3, #7 8001586: 429a cmp r2, r3 8001588: d021 beq.n 80015ce (tmp1 != I2C_CR2_STOP) && \ 800158a: 183b adds r3, r7, r0 800158c: 781b ldrb r3, [r3, #0] 800158e: 2b20 cmp r3, #32 8001590: d01d beq.n 80015ce (tmp2 != HAL_I2C_MODE_SLAVE)) { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; 8001592: 68fb ldr r3, [r7, #12] 8001594: 681b ldr r3, [r3, #0] 8001596: 685a ldr r2, [r3, #4] 8001598: 68fb ldr r3, [r7, #12] 800159a: 681b ldr r3, [r3, #0] 800159c: 2180 movs r1, #128 ; 0x80 800159e: 01c9 lsls r1, r1, #7 80015a0: 430a orrs r2, r1 80015a2: 605a str r2, [r3, #4] /* Update Tick with new reference */ tickstart = HAL_GetTick(); 80015a4: f7ff f936 bl 8000814 80015a8: 0003 movs r3, r0 80015aa: 61fb str r3, [r7, #28] } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) 80015ac: e00f b.n 80015ce { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) 80015ae: f7ff f931 bl 8000814 80015b2: 0002 movs r2, r0 80015b4: 69fb ldr r3, [r7, #28] 80015b6: 1ad3 subs r3, r2, r3 80015b8: 2b19 cmp r3, #25 80015ba: d908 bls.n 80015ce { error_code |= HAL_I2C_ERROR_TIMEOUT; 80015bc: 6a3b ldr r3, [r7, #32] 80015be: 2220 movs r2, #32 80015c0: 4313 orrs r3, r2 80015c2: 623b str r3, [r7, #32] status = HAL_ERROR; 80015c4: 2327 movs r3, #39 ; 0x27 80015c6: 18fb adds r3, r7, r3 80015c8: 2201 movs r2, #1 80015ca: 701a strb r2, [r3, #0] break; 80015cc: e00b b.n 80015e6 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) 80015ce: 68fb ldr r3, [r7, #12] 80015d0: 681b ldr r3, [r3, #0] 80015d2: 699b ldr r3, [r3, #24] 80015d4: 2220 movs r2, #32 80015d6: 4013 ands r3, r2 80015d8: 2127 movs r1, #39 ; 0x27 80015da: 187a adds r2, r7, r1 80015dc: 1879 adds r1, r7, r1 80015de: 7809 ldrb r1, [r1, #0] 80015e0: 7011 strb r1, [r2, #0] 80015e2: 2b20 cmp r3, #32 80015e4: d1e3 bne.n 80015ae while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) 80015e6: 68fb ldr r3, [r7, #12] 80015e8: 681b ldr r3, [r3, #0] 80015ea: 699b ldr r3, [r3, #24] 80015ec: 2220 movs r2, #32 80015ee: 4013 ands r3, r2 80015f0: 2b20 cmp r3, #32 80015f2: d004 beq.n 80015fe 80015f4: 2327 movs r3, #39 ; 0x27 80015f6: 18fb adds r3, r7, r3 80015f8: 781b ldrb r3, [r3, #0] 80015fa: 2b00 cmp r3, #0 80015fc: d092 beq.n 8001524 } } } /* In case STOP Flag is detected, clear it */ if (status == HAL_OK) 80015fe: 2327 movs r3, #39 ; 0x27 8001600: 18fb adds r3, r7, r3 8001602: 781b ldrb r3, [r3, #0] 8001604: 2b00 cmp r3, #0 8001606: d103 bne.n 8001610 { /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 8001608: 68fb ldr r3, [r7, #12] 800160a: 681b ldr r3, [r3, #0] 800160c: 2220 movs r2, #32 800160e: 61da str r2, [r3, #28] } error_code |= HAL_I2C_ERROR_AF; 8001610: 6a3b ldr r3, [r7, #32] 8001612: 2204 movs r2, #4 8001614: 4313 orrs r3, r2 8001616: 623b str r3, [r7, #32] status = HAL_ERROR; 8001618: 2327 movs r3, #39 ; 0x27 800161a: 18fb adds r3, r7, r3 800161c: 2201 movs r2, #1 800161e: 701a strb r2, [r3, #0] } /* Refresh Content of Status register */ itflag = hi2c->Instance->ISR; 8001620: 68fb ldr r3, [r7, #12] 8001622: 681b ldr r3, [r3, #0] 8001624: 699b ldr r3, [r3, #24] 8001626: 61bb str r3, [r7, #24] /* Then verify if an additional errors occurs */ /* Check if a Bus error occurred */ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) 8001628: 69ba ldr r2, [r7, #24] 800162a: 2380 movs r3, #128 ; 0x80 800162c: 005b lsls r3, r3, #1 800162e: 4013 ands r3, r2 8001630: d00c beq.n 800164c { error_code |= HAL_I2C_ERROR_BERR; 8001632: 6a3b ldr r3, [r7, #32] 8001634: 2201 movs r2, #1 8001636: 4313 orrs r3, r2 8001638: 623b str r3, [r7, #32] /* Clear BERR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); 800163a: 68fb ldr r3, [r7, #12] 800163c: 681b ldr r3, [r3, #0] 800163e: 2280 movs r2, #128 ; 0x80 8001640: 0052 lsls r2, r2, #1 8001642: 61da str r2, [r3, #28] status = HAL_ERROR; 8001644: 2327 movs r3, #39 ; 0x27 8001646: 18fb adds r3, r7, r3 8001648: 2201 movs r2, #1 800164a: 701a strb r2, [r3, #0] } /* Check if an Over-Run/Under-Run error occurred */ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) 800164c: 69ba ldr r2, [r7, #24] 800164e: 2380 movs r3, #128 ; 0x80 8001650: 00db lsls r3, r3, #3 8001652: 4013 ands r3, r2 8001654: d00c beq.n 8001670 { error_code |= HAL_I2C_ERROR_OVR; 8001656: 6a3b ldr r3, [r7, #32] 8001658: 2208 movs r2, #8 800165a: 4313 orrs r3, r2 800165c: 623b str r3, [r7, #32] /* Clear OVR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); 800165e: 68fb ldr r3, [r7, #12] 8001660: 681b ldr r3, [r3, #0] 8001662: 2280 movs r2, #128 ; 0x80 8001664: 00d2 lsls r2, r2, #3 8001666: 61da str r2, [r3, #28] status = HAL_ERROR; 8001668: 2327 movs r3, #39 ; 0x27 800166a: 18fb adds r3, r7, r3 800166c: 2201 movs r2, #1 800166e: 701a strb r2, [r3, #0] } /* Check if an Arbitration Loss error occurred */ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) 8001670: 69ba ldr r2, [r7, #24] 8001672: 2380 movs r3, #128 ; 0x80 8001674: 009b lsls r3, r3, #2 8001676: 4013 ands r3, r2 8001678: d00c beq.n 8001694 { error_code |= HAL_I2C_ERROR_ARLO; 800167a: 6a3b ldr r3, [r7, #32] 800167c: 2202 movs r2, #2 800167e: 4313 orrs r3, r2 8001680: 623b str r3, [r7, #32] /* Clear ARLO flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); 8001682: 68fb ldr r3, [r7, #12] 8001684: 681b ldr r3, [r3, #0] 8001686: 2280 movs r2, #128 ; 0x80 8001688: 0092 lsls r2, r2, #2 800168a: 61da str r2, [r3, #28] status = HAL_ERROR; 800168c: 2327 movs r3, #39 ; 0x27 800168e: 18fb adds r3, r7, r3 8001690: 2201 movs r2, #1 8001692: 701a strb r2, [r3, #0] } if (status != HAL_OK) 8001694: 2327 movs r3, #39 ; 0x27 8001696: 18fb adds r3, r7, r3 8001698: 781b ldrb r3, [r3, #0] 800169a: 2b00 cmp r3, #0 800169c: d01d beq.n 80016da { /* Flush TX register */ I2C_Flush_TXDR(hi2c); 800169e: 68fb ldr r3, [r7, #12] 80016a0: 0018 movs r0, r3 80016a2: f7ff fda7 bl 80011f4 /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 80016a6: 68fb ldr r3, [r7, #12] 80016a8: 681b ldr r3, [r3, #0] 80016aa: 685a ldr r2, [r3, #4] 80016ac: 68fb ldr r3, [r7, #12] 80016ae: 681b ldr r3, [r3, #0] 80016b0: 490d ldr r1, [pc, #52] ; (80016e8 ) 80016b2: 400a ands r2, r1 80016b4: 605a str r2, [r3, #4] hi2c->ErrorCode |= error_code; 80016b6: 68fb ldr r3, [r7, #12] 80016b8: 6c5a ldr r2, [r3, #68] ; 0x44 80016ba: 6a3b ldr r3, [r7, #32] 80016bc: 431a orrs r2, r3 80016be: 68fb ldr r3, [r7, #12] 80016c0: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; 80016c2: 68fb ldr r3, [r7, #12] 80016c4: 2241 movs r2, #65 ; 0x41 80016c6: 2120 movs r1, #32 80016c8: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_NONE; 80016ca: 68fb ldr r3, [r7, #12] 80016cc: 2242 movs r2, #66 ; 0x42 80016ce: 2100 movs r1, #0 80016d0: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80016d2: 68fb ldr r3, [r7, #12] 80016d4: 2240 movs r2, #64 ; 0x40 80016d6: 2100 movs r1, #0 80016d8: 5499 strb r1, [r3, r2] } return status; 80016da: 2327 movs r3, #39 ; 0x27 80016dc: 18fb adds r3, r7, r3 80016de: 781b ldrb r3, [r3, #0] } 80016e0: 0018 movs r0, r3 80016e2: 46bd mov sp, r7 80016e4: b00b add sp, #44 ; 0x2c 80016e6: bd90 pop {r4, r7, pc} 80016e8: fe00e800 .word 0xfe00e800 080016ec : * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { 80016ec: b590 push {r4, r7, lr} 80016ee: b087 sub sp, #28 80016f0: af00 add r7, sp, #0 80016f2: 60f8 str r0, [r7, #12] 80016f4: 0008 movs r0, r1 80016f6: 0011 movs r1, r2 80016f8: 607b str r3, [r7, #4] 80016fa: 240a movs r4, #10 80016fc: 193b adds r3, r7, r4 80016fe: 1c02 adds r2, r0, #0 8001700: 801a strh r2, [r3, #0] 8001702: 2009 movs r0, #9 8001704: 183b adds r3, r7, r0 8001706: 1c0a adds r2, r1, #0 8001708: 701a strb r2, [r3, #0] assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ 800170a: 193b adds r3, r7, r4 800170c: 881b ldrh r3, [r3, #0] 800170e: 059b lsls r3, r3, #22 8001710: 0d9a lsrs r2, r3, #22 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ 8001712: 183b adds r3, r7, r0 8001714: 781b ldrb r3, [r3, #0] 8001716: 0419 lsls r1, r3, #16 8001718: 23ff movs r3, #255 ; 0xff 800171a: 041b lsls r3, r3, #16 800171c: 400b ands r3, r1 uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ 800171e: 431a orrs r2, r3 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ 8001720: 687b ldr r3, [r7, #4] 8001722: 431a orrs r2, r3 uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ 8001724: 6abb ldr r3, [r7, #40] ; 0x28 8001726: 4313 orrs r3, r2 8001728: 005b lsls r3, r3, #1 800172a: 085b lsrs r3, r3, #1 800172c: 617b str r3, [r7, #20] (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ 800172e: 68fb ldr r3, [r7, #12] 8001730: 681b ldr r3, [r3, #0] 8001732: 685b ldr r3, [r3, #4] 8001734: 6aba ldr r2, [r7, #40] ; 0x28 8001736: 0d51 lsrs r1, r2, #21 8001738: 2280 movs r2, #128 ; 0x80 800173a: 00d2 lsls r2, r2, #3 800173c: 400a ands r2, r1 800173e: 4907 ldr r1, [pc, #28] ; (800175c ) 8001740: 430a orrs r2, r1 8001742: 43d2 mvns r2, r2 8001744: 401a ands r2, r3 8001746: 0011 movs r1, r2 8001748: 68fb ldr r3, [r7, #12] 800174a: 681b ldr r3, [r3, #0] 800174c: 697a ldr r2, [r7, #20] 800174e: 430a orrs r2, r1 8001750: 605a str r2, [r3, #4] ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ I2C_CR2_START | I2C_CR2_STOP)), tmp); } 8001752: 46c0 nop ; (mov r8, r8) 8001754: 46bd mov sp, r7 8001756: b007 add sp, #28 8001758: bd90 pop {r4, r7, pc} 800175a: 46c0 nop ; (mov r8, r8) 800175c: 03ff63ff .word 0x03ff63ff 08001760 : * the configuration information for the specified I2Cx peripheral. * @param AnalogFilter New state of the Analog filter. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) { 8001760: b580 push {r7, lr} 8001762: b082 sub sp, #8 8001764: af00 add r7, sp, #0 8001766: 6078 str r0, [r7, #4] 8001768: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 800176a: 687b ldr r3, [r7, #4] 800176c: 2241 movs r2, #65 ; 0x41 800176e: 5c9b ldrb r3, [r3, r2] 8001770: b2db uxtb r3, r3 8001772: 2b20 cmp r3, #32 8001774: d138 bne.n 80017e8 { /* Process Locked */ __HAL_LOCK(hi2c); 8001776: 687b ldr r3, [r7, #4] 8001778: 2240 movs r2, #64 ; 0x40 800177a: 5c9b ldrb r3, [r3, r2] 800177c: 2b01 cmp r3, #1 800177e: d101 bne.n 8001784 8001780: 2302 movs r3, #2 8001782: e032 b.n 80017ea 8001784: 687b ldr r3, [r7, #4] 8001786: 2240 movs r2, #64 ; 0x40 8001788: 2101 movs r1, #1 800178a: 5499 strb r1, [r3, r2] hi2c->State = HAL_I2C_STATE_BUSY; 800178c: 687b ldr r3, [r7, #4] 800178e: 2241 movs r2, #65 ; 0x41 8001790: 2124 movs r1, #36 ; 0x24 8001792: 5499 strb r1, [r3, r2] /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8001794: 687b ldr r3, [r7, #4] 8001796: 681b ldr r3, [r3, #0] 8001798: 681a ldr r2, [r3, #0] 800179a: 687b ldr r3, [r7, #4] 800179c: 681b ldr r3, [r3, #0] 800179e: 2101 movs r1, #1 80017a0: 438a bics r2, r1 80017a2: 601a str r2, [r3, #0] /* Reset I2Cx ANOFF bit */ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); 80017a4: 687b ldr r3, [r7, #4] 80017a6: 681b ldr r3, [r3, #0] 80017a8: 681a ldr r2, [r3, #0] 80017aa: 687b ldr r3, [r7, #4] 80017ac: 681b ldr r3, [r3, #0] 80017ae: 4911 ldr r1, [pc, #68] ; (80017f4 ) 80017b0: 400a ands r2, r1 80017b2: 601a str r2, [r3, #0] /* Set analog filter bit*/ hi2c->Instance->CR1 |= AnalogFilter; 80017b4: 687b ldr r3, [r7, #4] 80017b6: 681b ldr r3, [r3, #0] 80017b8: 6819 ldr r1, [r3, #0] 80017ba: 687b ldr r3, [r7, #4] 80017bc: 681b ldr r3, [r3, #0] 80017be: 683a ldr r2, [r7, #0] 80017c0: 430a orrs r2, r1 80017c2: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); 80017c4: 687b ldr r3, [r7, #4] 80017c6: 681b ldr r3, [r3, #0] 80017c8: 681a ldr r2, [r3, #0] 80017ca: 687b ldr r3, [r7, #4] 80017cc: 681b ldr r3, [r3, #0] 80017ce: 2101 movs r1, #1 80017d0: 430a orrs r2, r1 80017d2: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 80017d4: 687b ldr r3, [r7, #4] 80017d6: 2241 movs r2, #65 ; 0x41 80017d8: 2120 movs r1, #32 80017da: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80017dc: 687b ldr r3, [r7, #4] 80017de: 2240 movs r2, #64 ; 0x40 80017e0: 2100 movs r1, #0 80017e2: 5499 strb r1, [r3, r2] return HAL_OK; 80017e4: 2300 movs r3, #0 80017e6: e000 b.n 80017ea } else { return HAL_BUSY; 80017e8: 2302 movs r3, #2 } } 80017ea: 0018 movs r0, r3 80017ec: 46bd mov sp, r7 80017ee: b002 add sp, #8 80017f0: bd80 pop {r7, pc} 80017f2: 46c0 nop ; (mov r8, r8) 80017f4: ffffefff .word 0xffffefff 080017f8 : * the configuration information for the specified I2Cx peripheral. * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { 80017f8: b580 push {r7, lr} 80017fa: b084 sub sp, #16 80017fc: af00 add r7, sp, #0 80017fe: 6078 str r0, [r7, #4] 8001800: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 8001802: 687b ldr r3, [r7, #4] 8001804: 2241 movs r2, #65 ; 0x41 8001806: 5c9b ldrb r3, [r3, r2] 8001808: b2db uxtb r3, r3 800180a: 2b20 cmp r3, #32 800180c: d139 bne.n 8001882 { /* Process Locked */ __HAL_LOCK(hi2c); 800180e: 687b ldr r3, [r7, #4] 8001810: 2240 movs r2, #64 ; 0x40 8001812: 5c9b ldrb r3, [r3, r2] 8001814: 2b01 cmp r3, #1 8001816: d101 bne.n 800181c 8001818: 2302 movs r3, #2 800181a: e033 b.n 8001884 800181c: 687b ldr r3, [r7, #4] 800181e: 2240 movs r2, #64 ; 0x40 8001820: 2101 movs r1, #1 8001822: 5499 strb r1, [r3, r2] hi2c->State = HAL_I2C_STATE_BUSY; 8001824: 687b ldr r3, [r7, #4] 8001826: 2241 movs r2, #65 ; 0x41 8001828: 2124 movs r1, #36 ; 0x24 800182a: 5499 strb r1, [r3, r2] /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 800182c: 687b ldr r3, [r7, #4] 800182e: 681b ldr r3, [r3, #0] 8001830: 681a ldr r2, [r3, #0] 8001832: 687b ldr r3, [r7, #4] 8001834: 681b ldr r3, [r3, #0] 8001836: 2101 movs r1, #1 8001838: 438a bics r2, r1 800183a: 601a str r2, [r3, #0] /* Get the old register value */ tmpreg = hi2c->Instance->CR1; 800183c: 687b ldr r3, [r7, #4] 800183e: 681b ldr r3, [r3, #0] 8001840: 681b ldr r3, [r3, #0] 8001842: 60fb str r3, [r7, #12] /* Reset I2Cx DNF bits [11:8] */ tmpreg &= ~(I2C_CR1_DNF); 8001844: 68fb ldr r3, [r7, #12] 8001846: 4a11 ldr r2, [pc, #68] ; (800188c ) 8001848: 4013 ands r3, r2 800184a: 60fb str r3, [r7, #12] /* Set I2Cx DNF coefficient */ tmpreg |= DigitalFilter << 8U; 800184c: 683b ldr r3, [r7, #0] 800184e: 021b lsls r3, r3, #8 8001850: 68fa ldr r2, [r7, #12] 8001852: 4313 orrs r3, r2 8001854: 60fb str r3, [r7, #12] /* Store the new register value */ hi2c->Instance->CR1 = tmpreg; 8001856: 687b ldr r3, [r7, #4] 8001858: 681b ldr r3, [r3, #0] 800185a: 68fa ldr r2, [r7, #12] 800185c: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); 800185e: 687b ldr r3, [r7, #4] 8001860: 681b ldr r3, [r3, #0] 8001862: 681a ldr r2, [r3, #0] 8001864: 687b ldr r3, [r7, #4] 8001866: 681b ldr r3, [r3, #0] 8001868: 2101 movs r1, #1 800186a: 430a orrs r2, r1 800186c: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 800186e: 687b ldr r3, [r7, #4] 8001870: 2241 movs r2, #65 ; 0x41 8001872: 2120 movs r1, #32 8001874: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8001876: 687b ldr r3, [r7, #4] 8001878: 2240 movs r2, #64 ; 0x40 800187a: 2100 movs r1, #0 800187c: 5499 strb r1, [r3, r2] return HAL_OK; 800187e: 2300 movs r3, #0 8001880: e000 b.n 8001884 } else { return HAL_BUSY; 8001882: 2302 movs r3, #2 } } 8001884: 0018 movs r0, r3 8001886: 46bd mov sp, r7 8001888: b004 add sp, #16 800188a: bd80 pop {r7, pc} 800188c: fffff0ff .word 0xfffff0ff 08001890 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8001890: b580 push {r7, lr} 8001892: b088 sub sp, #32 8001894: af00 add r7, sp, #0 8001896: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; uint32_t pll_config2; /* Check Null pointer */ if(RCC_OscInitStruct == NULL) 8001898: 687b ldr r3, [r7, #4] 800189a: 2b00 cmp r3, #0 800189c: d102 bne.n 80018a4 { return HAL_ERROR; 800189e: 2301 movs r3, #1 80018a0: f000 fb76 bl 8001f90 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 80018a4: 687b ldr r3, [r7, #4] 80018a6: 681b ldr r3, [r3, #0] 80018a8: 2201 movs r2, #1 80018aa: 4013 ands r3, r2 80018ac: d100 bne.n 80018b0 80018ae: e08e b.n 80019ce { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 80018b0: 4bc5 ldr r3, [pc, #788] ; (8001bc8 ) 80018b2: 685b ldr r3, [r3, #4] 80018b4: 220c movs r2, #12 80018b6: 4013 ands r3, r2 80018b8: 2b04 cmp r3, #4 80018ba: d00e beq.n 80018da || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 80018bc: 4bc2 ldr r3, [pc, #776] ; (8001bc8 ) 80018be: 685b ldr r3, [r3, #4] 80018c0: 220c movs r2, #12 80018c2: 4013 ands r3, r2 80018c4: 2b08 cmp r3, #8 80018c6: d117 bne.n 80018f8 80018c8: 4bbf ldr r3, [pc, #764] ; (8001bc8 ) 80018ca: 685a ldr r2, [r3, #4] 80018cc: 23c0 movs r3, #192 ; 0xc0 80018ce: 025b lsls r3, r3, #9 80018d0: 401a ands r2, r3 80018d2: 2380 movs r3, #128 ; 0x80 80018d4: 025b lsls r3, r3, #9 80018d6: 429a cmp r2, r3 80018d8: d10e bne.n 80018f8 { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80018da: 4bbb ldr r3, [pc, #748] ; (8001bc8 ) 80018dc: 681a ldr r2, [r3, #0] 80018de: 2380 movs r3, #128 ; 0x80 80018e0: 029b lsls r3, r3, #10 80018e2: 4013 ands r3, r2 80018e4: d100 bne.n 80018e8 80018e6: e071 b.n 80019cc 80018e8: 687b ldr r3, [r7, #4] 80018ea: 685b ldr r3, [r3, #4] 80018ec: 2b00 cmp r3, #0 80018ee: d000 beq.n 80018f2 80018f0: e06c b.n 80019cc { return HAL_ERROR; 80018f2: 2301 movs r3, #1 80018f4: f000 fb4c bl 8001f90 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80018f8: 687b ldr r3, [r7, #4] 80018fa: 685b ldr r3, [r3, #4] 80018fc: 2b01 cmp r3, #1 80018fe: d107 bne.n 8001910 8001900: 4bb1 ldr r3, [pc, #708] ; (8001bc8 ) 8001902: 681a ldr r2, [r3, #0] 8001904: 4bb0 ldr r3, [pc, #704] ; (8001bc8 ) 8001906: 2180 movs r1, #128 ; 0x80 8001908: 0249 lsls r1, r1, #9 800190a: 430a orrs r2, r1 800190c: 601a str r2, [r3, #0] 800190e: e02f b.n 8001970 8001910: 687b ldr r3, [r7, #4] 8001912: 685b ldr r3, [r3, #4] 8001914: 2b00 cmp r3, #0 8001916: d10c bne.n 8001932 8001918: 4bab ldr r3, [pc, #684] ; (8001bc8 ) 800191a: 681a ldr r2, [r3, #0] 800191c: 4baa ldr r3, [pc, #680] ; (8001bc8 ) 800191e: 49ab ldr r1, [pc, #684] ; (8001bcc ) 8001920: 400a ands r2, r1 8001922: 601a str r2, [r3, #0] 8001924: 4ba8 ldr r3, [pc, #672] ; (8001bc8 ) 8001926: 681a ldr r2, [r3, #0] 8001928: 4ba7 ldr r3, [pc, #668] ; (8001bc8 ) 800192a: 49a9 ldr r1, [pc, #676] ; (8001bd0 ) 800192c: 400a ands r2, r1 800192e: 601a str r2, [r3, #0] 8001930: e01e b.n 8001970 8001932: 687b ldr r3, [r7, #4] 8001934: 685b ldr r3, [r3, #4] 8001936: 2b05 cmp r3, #5 8001938: d10e bne.n 8001958 800193a: 4ba3 ldr r3, [pc, #652] ; (8001bc8 ) 800193c: 681a ldr r2, [r3, #0] 800193e: 4ba2 ldr r3, [pc, #648] ; (8001bc8 ) 8001940: 2180 movs r1, #128 ; 0x80 8001942: 02c9 lsls r1, r1, #11 8001944: 430a orrs r2, r1 8001946: 601a str r2, [r3, #0] 8001948: 4b9f ldr r3, [pc, #636] ; (8001bc8 ) 800194a: 681a ldr r2, [r3, #0] 800194c: 4b9e ldr r3, [pc, #632] ; (8001bc8 ) 800194e: 2180 movs r1, #128 ; 0x80 8001950: 0249 lsls r1, r1, #9 8001952: 430a orrs r2, r1 8001954: 601a str r2, [r3, #0] 8001956: e00b b.n 8001970 8001958: 4b9b ldr r3, [pc, #620] ; (8001bc8 ) 800195a: 681a ldr r2, [r3, #0] 800195c: 4b9a ldr r3, [pc, #616] ; (8001bc8 ) 800195e: 499b ldr r1, [pc, #620] ; (8001bcc ) 8001960: 400a ands r2, r1 8001962: 601a str r2, [r3, #0] 8001964: 4b98 ldr r3, [pc, #608] ; (8001bc8 ) 8001966: 681a ldr r2, [r3, #0] 8001968: 4b97 ldr r3, [pc, #604] ; (8001bc8 ) 800196a: 4999 ldr r1, [pc, #612] ; (8001bd0 ) 800196c: 400a ands r2, r1 800196e: 601a str r2, [r3, #0] /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8001970: 687b ldr r3, [r7, #4] 8001972: 685b ldr r3, [r3, #4] 8001974: 2b00 cmp r3, #0 8001976: d014 beq.n 80019a2 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001978: f7fe ff4c bl 8000814 800197c: 0003 movs r3, r0 800197e: 61bb str r3, [r7, #24] /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001980: e008 b.n 8001994 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8001982: f7fe ff47 bl 8000814 8001986: 0002 movs r2, r0 8001988: 69bb ldr r3, [r7, #24] 800198a: 1ad3 subs r3, r2, r3 800198c: 2b64 cmp r3, #100 ; 0x64 800198e: d901 bls.n 8001994 { return HAL_TIMEOUT; 8001990: 2303 movs r3, #3 8001992: e2fd b.n 8001f90 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001994: 4b8c ldr r3, [pc, #560] ; (8001bc8 ) 8001996: 681a ldr r2, [r3, #0] 8001998: 2380 movs r3, #128 ; 0x80 800199a: 029b lsls r3, r3, #10 800199c: 4013 ands r3, r2 800199e: d0f0 beq.n 8001982 80019a0: e015 b.n 80019ce } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 80019a2: f7fe ff37 bl 8000814 80019a6: 0003 movs r3, r0 80019a8: 61bb str r3, [r7, #24] /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 80019aa: e008 b.n 80019be { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 80019ac: f7fe ff32 bl 8000814 80019b0: 0002 movs r2, r0 80019b2: 69bb ldr r3, [r7, #24] 80019b4: 1ad3 subs r3, r2, r3 80019b6: 2b64 cmp r3, #100 ; 0x64 80019b8: d901 bls.n 80019be { return HAL_TIMEOUT; 80019ba: 2303 movs r3, #3 80019bc: e2e8 b.n 8001f90 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 80019be: 4b82 ldr r3, [pc, #520] ; (8001bc8 ) 80019c0: 681a ldr r2, [r3, #0] 80019c2: 2380 movs r3, #128 ; 0x80 80019c4: 029b lsls r3, r3, #10 80019c6: 4013 ands r3, r2 80019c8: d1f0 bne.n 80019ac 80019ca: e000 b.n 80019ce if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80019cc: 46c0 nop ; (mov r8, r8) } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 80019ce: 687b ldr r3, [r7, #4] 80019d0: 681b ldr r3, [r3, #0] 80019d2: 2202 movs r2, #2 80019d4: 4013 ands r3, r2 80019d6: d100 bne.n 80019da 80019d8: e06c b.n 8001ab4 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 80019da: 4b7b ldr r3, [pc, #492] ; (8001bc8 ) 80019dc: 685b ldr r3, [r3, #4] 80019de: 220c movs r2, #12 80019e0: 4013 ands r3, r2 80019e2: d00e beq.n 8001a02 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) 80019e4: 4b78 ldr r3, [pc, #480] ; (8001bc8 ) 80019e6: 685b ldr r3, [r3, #4] 80019e8: 220c movs r2, #12 80019ea: 4013 ands r3, r2 80019ec: 2b08 cmp r3, #8 80019ee: d11f bne.n 8001a30 80019f0: 4b75 ldr r3, [pc, #468] ; (8001bc8 ) 80019f2: 685a ldr r2, [r3, #4] 80019f4: 23c0 movs r3, #192 ; 0xc0 80019f6: 025b lsls r3, r3, #9 80019f8: 401a ands r2, r3 80019fa: 2380 movs r3, #128 ; 0x80 80019fc: 021b lsls r3, r3, #8 80019fe: 429a cmp r2, r3 8001a00: d116 bne.n 8001a30 { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8001a02: 4b71 ldr r3, [pc, #452] ; (8001bc8 ) 8001a04: 681b ldr r3, [r3, #0] 8001a06: 2202 movs r2, #2 8001a08: 4013 ands r3, r2 8001a0a: d005 beq.n 8001a18 8001a0c: 687b ldr r3, [r7, #4] 8001a0e: 68db ldr r3, [r3, #12] 8001a10: 2b01 cmp r3, #1 8001a12: d001 beq.n 8001a18 { return HAL_ERROR; 8001a14: 2301 movs r3, #1 8001a16: e2bb b.n 8001f90 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8001a18: 4b6b ldr r3, [pc, #428] ; (8001bc8 ) 8001a1a: 681b ldr r3, [r3, #0] 8001a1c: 22f8 movs r2, #248 ; 0xf8 8001a1e: 4393 bics r3, r2 8001a20: 0019 movs r1, r3 8001a22: 687b ldr r3, [r7, #4] 8001a24: 691b ldr r3, [r3, #16] 8001a26: 00da lsls r2, r3, #3 8001a28: 4b67 ldr r3, [pc, #412] ; (8001bc8 ) 8001a2a: 430a orrs r2, r1 8001a2c: 601a str r2, [r3, #0] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8001a2e: e041 b.n 8001ab4 } } else { /* Check the HSI State */ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8001a30: 687b ldr r3, [r7, #4] 8001a32: 68db ldr r3, [r3, #12] 8001a34: 2b00 cmp r3, #0 8001a36: d024 beq.n 8001a82 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8001a38: 4b63 ldr r3, [pc, #396] ; (8001bc8 ) 8001a3a: 681a ldr r2, [r3, #0] 8001a3c: 4b62 ldr r3, [pc, #392] ; (8001bc8 ) 8001a3e: 2101 movs r1, #1 8001a40: 430a orrs r2, r1 8001a42: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001a44: f7fe fee6 bl 8000814 8001a48: 0003 movs r3, r0 8001a4a: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001a4c: e008 b.n 8001a60 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8001a4e: f7fe fee1 bl 8000814 8001a52: 0002 movs r2, r0 8001a54: 69bb ldr r3, [r7, #24] 8001a56: 1ad3 subs r3, r2, r3 8001a58: 2b02 cmp r3, #2 8001a5a: d901 bls.n 8001a60 { return HAL_TIMEOUT; 8001a5c: 2303 movs r3, #3 8001a5e: e297 b.n 8001f90 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001a60: 4b59 ldr r3, [pc, #356] ; (8001bc8 ) 8001a62: 681b ldr r3, [r3, #0] 8001a64: 2202 movs r2, #2 8001a66: 4013 ands r3, r2 8001a68: d0f1 beq.n 8001a4e } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8001a6a: 4b57 ldr r3, [pc, #348] ; (8001bc8 ) 8001a6c: 681b ldr r3, [r3, #0] 8001a6e: 22f8 movs r2, #248 ; 0xf8 8001a70: 4393 bics r3, r2 8001a72: 0019 movs r1, r3 8001a74: 687b ldr r3, [r7, #4] 8001a76: 691b ldr r3, [r3, #16] 8001a78: 00da lsls r2, r3, #3 8001a7a: 4b53 ldr r3, [pc, #332] ; (8001bc8 ) 8001a7c: 430a orrs r2, r1 8001a7e: 601a str r2, [r3, #0] 8001a80: e018 b.n 8001ab4 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8001a82: 4b51 ldr r3, [pc, #324] ; (8001bc8 ) 8001a84: 681a ldr r2, [r3, #0] 8001a86: 4b50 ldr r3, [pc, #320] ; (8001bc8 ) 8001a88: 2101 movs r1, #1 8001a8a: 438a bics r2, r1 8001a8c: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001a8e: f7fe fec1 bl 8000814 8001a92: 0003 movs r3, r0 8001a94: 61bb str r3, [r7, #24] /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8001a96: e008 b.n 8001aaa { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8001a98: f7fe febc bl 8000814 8001a9c: 0002 movs r2, r0 8001a9e: 69bb ldr r3, [r7, #24] 8001aa0: 1ad3 subs r3, r2, r3 8001aa2: 2b02 cmp r3, #2 8001aa4: d901 bls.n 8001aaa { return HAL_TIMEOUT; 8001aa6: 2303 movs r3, #3 8001aa8: e272 b.n 8001f90 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8001aaa: 4b47 ldr r3, [pc, #284] ; (8001bc8 ) 8001aac: 681b ldr r3, [r3, #0] 8001aae: 2202 movs r2, #2 8001ab0: 4013 ands r3, r2 8001ab2: d1f1 bne.n 8001a98 } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8001ab4: 687b ldr r3, [r7, #4] 8001ab6: 681b ldr r3, [r3, #0] 8001ab8: 2208 movs r2, #8 8001aba: 4013 ands r3, r2 8001abc: d036 beq.n 8001b2c { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8001abe: 687b ldr r3, [r7, #4] 8001ac0: 69db ldr r3, [r3, #28] 8001ac2: 2b00 cmp r3, #0 8001ac4: d019 beq.n 8001afa { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8001ac6: 4b40 ldr r3, [pc, #256] ; (8001bc8 ) 8001ac8: 6a5a ldr r2, [r3, #36] ; 0x24 8001aca: 4b3f ldr r3, [pc, #252] ; (8001bc8 ) 8001acc: 2101 movs r1, #1 8001ace: 430a orrs r2, r1 8001ad0: 625a str r2, [r3, #36] ; 0x24 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001ad2: f7fe fe9f bl 8000814 8001ad6: 0003 movs r3, r0 8001ad8: 61bb str r3, [r7, #24] /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8001ada: e008 b.n 8001aee { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8001adc: f7fe fe9a bl 8000814 8001ae0: 0002 movs r2, r0 8001ae2: 69bb ldr r3, [r7, #24] 8001ae4: 1ad3 subs r3, r2, r3 8001ae6: 2b02 cmp r3, #2 8001ae8: d901 bls.n 8001aee { return HAL_TIMEOUT; 8001aea: 2303 movs r3, #3 8001aec: e250 b.n 8001f90 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8001aee: 4b36 ldr r3, [pc, #216] ; (8001bc8 ) 8001af0: 6a5b ldr r3, [r3, #36] ; 0x24 8001af2: 2202 movs r2, #2 8001af4: 4013 ands r3, r2 8001af6: d0f1 beq.n 8001adc 8001af8: e018 b.n 8001b2c } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8001afa: 4b33 ldr r3, [pc, #204] ; (8001bc8 ) 8001afc: 6a5a ldr r2, [r3, #36] ; 0x24 8001afe: 4b32 ldr r3, [pc, #200] ; (8001bc8 ) 8001b00: 2101 movs r1, #1 8001b02: 438a bics r2, r1 8001b04: 625a str r2, [r3, #36] ; 0x24 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001b06: f7fe fe85 bl 8000814 8001b0a: 0003 movs r3, r0 8001b0c: 61bb str r3, [r7, #24] /* Wait till LSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8001b0e: e008 b.n 8001b22 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8001b10: f7fe fe80 bl 8000814 8001b14: 0002 movs r2, r0 8001b16: 69bb ldr r3, [r7, #24] 8001b18: 1ad3 subs r3, r2, r3 8001b1a: 2b02 cmp r3, #2 8001b1c: d901 bls.n 8001b22 { return HAL_TIMEOUT; 8001b1e: 2303 movs r3, #3 8001b20: e236 b.n 8001f90 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8001b22: 4b29 ldr r3, [pc, #164] ; (8001bc8 ) 8001b24: 6a5b ldr r3, [r3, #36] ; 0x24 8001b26: 2202 movs r2, #2 8001b28: 4013 ands r3, r2 8001b2a: d1f1 bne.n 8001b10 } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8001b2c: 687b ldr r3, [r7, #4] 8001b2e: 681b ldr r3, [r3, #0] 8001b30: 2204 movs r2, #4 8001b32: 4013 ands r3, r2 8001b34: d100 bne.n 8001b38 8001b36: e0b5 b.n 8001ca4 { FlagStatus pwrclkchanged = RESET; 8001b38: 201f movs r0, #31 8001b3a: 183b adds r3, r7, r0 8001b3c: 2200 movs r2, #0 8001b3e: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 8001b40: 4b21 ldr r3, [pc, #132] ; (8001bc8 ) 8001b42: 69da ldr r2, [r3, #28] 8001b44: 2380 movs r3, #128 ; 0x80 8001b46: 055b lsls r3, r3, #21 8001b48: 4013 ands r3, r2 8001b4a: d110 bne.n 8001b6e { __HAL_RCC_PWR_CLK_ENABLE(); 8001b4c: 4b1e ldr r3, [pc, #120] ; (8001bc8 ) 8001b4e: 69da ldr r2, [r3, #28] 8001b50: 4b1d ldr r3, [pc, #116] ; (8001bc8 ) 8001b52: 2180 movs r1, #128 ; 0x80 8001b54: 0549 lsls r1, r1, #21 8001b56: 430a orrs r2, r1 8001b58: 61da str r2, [r3, #28] 8001b5a: 4b1b ldr r3, [pc, #108] ; (8001bc8 ) 8001b5c: 69da ldr r2, [r3, #28] 8001b5e: 2380 movs r3, #128 ; 0x80 8001b60: 055b lsls r3, r3, #21 8001b62: 4013 ands r3, r2 8001b64: 60fb str r3, [r7, #12] 8001b66: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 8001b68: 183b adds r3, r7, r0 8001b6a: 2201 movs r2, #1 8001b6c: 701a strb r2, [r3, #0] } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001b6e: 4b19 ldr r3, [pc, #100] ; (8001bd4 ) 8001b70: 681a ldr r2, [r3, #0] 8001b72: 2380 movs r3, #128 ; 0x80 8001b74: 005b lsls r3, r3, #1 8001b76: 4013 ands r3, r2 8001b78: d11a bne.n 8001bb0 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8001b7a: 4b16 ldr r3, [pc, #88] ; (8001bd4 ) 8001b7c: 681a ldr r2, [r3, #0] 8001b7e: 4b15 ldr r3, [pc, #84] ; (8001bd4 ) 8001b80: 2180 movs r1, #128 ; 0x80 8001b82: 0049 lsls r1, r1, #1 8001b84: 430a orrs r2, r1 8001b86: 601a str r2, [r3, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8001b88: f7fe fe44 bl 8000814 8001b8c: 0003 movs r3, r0 8001b8e: 61bb str r3, [r7, #24] while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001b90: e008 b.n 8001ba4 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8001b92: f7fe fe3f bl 8000814 8001b96: 0002 movs r2, r0 8001b98: 69bb ldr r3, [r7, #24] 8001b9a: 1ad3 subs r3, r2, r3 8001b9c: 2b64 cmp r3, #100 ; 0x64 8001b9e: d901 bls.n 8001ba4 { return HAL_TIMEOUT; 8001ba0: 2303 movs r3, #3 8001ba2: e1f5 b.n 8001f90 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001ba4: 4b0b ldr r3, [pc, #44] ; (8001bd4 ) 8001ba6: 681a ldr r2, [r3, #0] 8001ba8: 2380 movs r3, #128 ; 0x80 8001baa: 005b lsls r3, r3, #1 8001bac: 4013 ands r3, r2 8001bae: d0f0 beq.n 8001b92 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8001bb0: 687b ldr r3, [r7, #4] 8001bb2: 689b ldr r3, [r3, #8] 8001bb4: 2b01 cmp r3, #1 8001bb6: d10f bne.n 8001bd8 8001bb8: 4b03 ldr r3, [pc, #12] ; (8001bc8 ) 8001bba: 6a1a ldr r2, [r3, #32] 8001bbc: 4b02 ldr r3, [pc, #8] ; (8001bc8 ) 8001bbe: 2101 movs r1, #1 8001bc0: 430a orrs r2, r1 8001bc2: 621a str r2, [r3, #32] 8001bc4: e036 b.n 8001c34 8001bc6: 46c0 nop ; (mov r8, r8) 8001bc8: 40021000 .word 0x40021000 8001bcc: fffeffff .word 0xfffeffff 8001bd0: fffbffff .word 0xfffbffff 8001bd4: 40007000 .word 0x40007000 8001bd8: 687b ldr r3, [r7, #4] 8001bda: 689b ldr r3, [r3, #8] 8001bdc: 2b00 cmp r3, #0 8001bde: d10c bne.n 8001bfa 8001be0: 4bca ldr r3, [pc, #808] ; (8001f0c ) 8001be2: 6a1a ldr r2, [r3, #32] 8001be4: 4bc9 ldr r3, [pc, #804] ; (8001f0c ) 8001be6: 2101 movs r1, #1 8001be8: 438a bics r2, r1 8001bea: 621a str r2, [r3, #32] 8001bec: 4bc7 ldr r3, [pc, #796] ; (8001f0c ) 8001bee: 6a1a ldr r2, [r3, #32] 8001bf0: 4bc6 ldr r3, [pc, #792] ; (8001f0c ) 8001bf2: 2104 movs r1, #4 8001bf4: 438a bics r2, r1 8001bf6: 621a str r2, [r3, #32] 8001bf8: e01c b.n 8001c34 8001bfa: 687b ldr r3, [r7, #4] 8001bfc: 689b ldr r3, [r3, #8] 8001bfe: 2b05 cmp r3, #5 8001c00: d10c bne.n 8001c1c 8001c02: 4bc2 ldr r3, [pc, #776] ; (8001f0c ) 8001c04: 6a1a ldr r2, [r3, #32] 8001c06: 4bc1 ldr r3, [pc, #772] ; (8001f0c ) 8001c08: 2104 movs r1, #4 8001c0a: 430a orrs r2, r1 8001c0c: 621a str r2, [r3, #32] 8001c0e: 4bbf ldr r3, [pc, #764] ; (8001f0c ) 8001c10: 6a1a ldr r2, [r3, #32] 8001c12: 4bbe ldr r3, [pc, #760] ; (8001f0c ) 8001c14: 2101 movs r1, #1 8001c16: 430a orrs r2, r1 8001c18: 621a str r2, [r3, #32] 8001c1a: e00b b.n 8001c34 8001c1c: 4bbb ldr r3, [pc, #748] ; (8001f0c ) 8001c1e: 6a1a ldr r2, [r3, #32] 8001c20: 4bba ldr r3, [pc, #744] ; (8001f0c ) 8001c22: 2101 movs r1, #1 8001c24: 438a bics r2, r1 8001c26: 621a str r2, [r3, #32] 8001c28: 4bb8 ldr r3, [pc, #736] ; (8001f0c ) 8001c2a: 6a1a ldr r2, [r3, #32] 8001c2c: 4bb7 ldr r3, [pc, #732] ; (8001f0c ) 8001c2e: 2104 movs r1, #4 8001c30: 438a bics r2, r1 8001c32: 621a str r2, [r3, #32] /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8001c34: 687b ldr r3, [r7, #4] 8001c36: 689b ldr r3, [r3, #8] 8001c38: 2b00 cmp r3, #0 8001c3a: d014 beq.n 8001c66 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001c3c: f7fe fdea bl 8000814 8001c40: 0003 movs r3, r0 8001c42: 61bb str r3, [r7, #24] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8001c44: e009 b.n 8001c5a { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8001c46: f7fe fde5 bl 8000814 8001c4a: 0002 movs r2, r0 8001c4c: 69bb ldr r3, [r7, #24] 8001c4e: 1ad3 subs r3, r2, r3 8001c50: 4aaf ldr r2, [pc, #700] ; (8001f10 ) 8001c52: 4293 cmp r3, r2 8001c54: d901 bls.n 8001c5a { return HAL_TIMEOUT; 8001c56: 2303 movs r3, #3 8001c58: e19a b.n 8001f90 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8001c5a: 4bac ldr r3, [pc, #688] ; (8001f0c ) 8001c5c: 6a1b ldr r3, [r3, #32] 8001c5e: 2202 movs r2, #2 8001c60: 4013 ands r3, r2 8001c62: d0f0 beq.n 8001c46 8001c64: e013 b.n 8001c8e } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001c66: f7fe fdd5 bl 8000814 8001c6a: 0003 movs r3, r0 8001c6c: 61bb str r3, [r7, #24] /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8001c6e: e009 b.n 8001c84 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8001c70: f7fe fdd0 bl 8000814 8001c74: 0002 movs r2, r0 8001c76: 69bb ldr r3, [r7, #24] 8001c78: 1ad3 subs r3, r2, r3 8001c7a: 4aa5 ldr r2, [pc, #660] ; (8001f10 ) 8001c7c: 4293 cmp r3, r2 8001c7e: d901 bls.n 8001c84 { return HAL_TIMEOUT; 8001c80: 2303 movs r3, #3 8001c82: e185 b.n 8001f90 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8001c84: 4ba1 ldr r3, [pc, #644] ; (8001f0c ) 8001c86: 6a1b ldr r3, [r3, #32] 8001c88: 2202 movs r2, #2 8001c8a: 4013 ands r3, r2 8001c8c: d1f0 bne.n 8001c70 } } } /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) 8001c8e: 231f movs r3, #31 8001c90: 18fb adds r3, r7, r3 8001c92: 781b ldrb r3, [r3, #0] 8001c94: 2b01 cmp r3, #1 8001c96: d105 bne.n 8001ca4 { __HAL_RCC_PWR_CLK_DISABLE(); 8001c98: 4b9c ldr r3, [pc, #624] ; (8001f0c ) 8001c9a: 69da ldr r2, [r3, #28] 8001c9c: 4b9b ldr r3, [pc, #620] ; (8001f0c ) 8001c9e: 499d ldr r1, [pc, #628] ; (8001f14 ) 8001ca0: 400a ands r2, r1 8001ca2: 61da str r2, [r3, #28] } } /*----------------------------- HSI14 Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) 8001ca4: 687b ldr r3, [r7, #4] 8001ca6: 681b ldr r3, [r3, #0] 8001ca8: 2210 movs r2, #16 8001caa: 4013 ands r3, r2 8001cac: d063 beq.n 8001d76 /* Check the parameters */ assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue)); /* Check the HSI14 State */ if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON) 8001cae: 687b ldr r3, [r7, #4] 8001cb0: 695b ldr r3, [r3, #20] 8001cb2: 2b01 cmp r3, #1 8001cb4: d12a bne.n 8001d0c { /* Disable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_DISABLE(); 8001cb6: 4b95 ldr r3, [pc, #596] ; (8001f0c ) 8001cb8: 6b5a ldr r2, [r3, #52] ; 0x34 8001cba: 4b94 ldr r3, [pc, #592] ; (8001f0c ) 8001cbc: 2104 movs r1, #4 8001cbe: 430a orrs r2, r1 8001cc0: 635a str r2, [r3, #52] ; 0x34 /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI14_ENABLE(); 8001cc2: 4b92 ldr r3, [pc, #584] ; (8001f0c ) 8001cc4: 6b5a ldr r2, [r3, #52] ; 0x34 8001cc6: 4b91 ldr r3, [pc, #580] ; (8001f0c ) 8001cc8: 2101 movs r1, #1 8001cca: 430a orrs r2, r1 8001ccc: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001cce: f7fe fda1 bl 8000814 8001cd2: 0003 movs r3, r0 8001cd4: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) 8001cd6: e008 b.n 8001cea { if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) 8001cd8: f7fe fd9c bl 8000814 8001cdc: 0002 movs r2, r0 8001cde: 69bb ldr r3, [r7, #24] 8001ce0: 1ad3 subs r3, r2, r3 8001ce2: 2b02 cmp r3, #2 8001ce4: d901 bls.n 8001cea { return HAL_TIMEOUT; 8001ce6: 2303 movs r3, #3 8001ce8: e152 b.n 8001f90 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) 8001cea: 4b88 ldr r3, [pc, #544] ; (8001f0c ) 8001cec: 6b5b ldr r3, [r3, #52] ; 0x34 8001cee: 2202 movs r2, #2 8001cf0: 4013 ands r3, r2 8001cf2: d0f1 beq.n 8001cd8 } } /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); 8001cf4: 4b85 ldr r3, [pc, #532] ; (8001f0c ) 8001cf6: 6b5b ldr r3, [r3, #52] ; 0x34 8001cf8: 22f8 movs r2, #248 ; 0xf8 8001cfa: 4393 bics r3, r2 8001cfc: 0019 movs r1, r3 8001cfe: 687b ldr r3, [r7, #4] 8001d00: 699b ldr r3, [r3, #24] 8001d02: 00da lsls r2, r3, #3 8001d04: 4b81 ldr r3, [pc, #516] ; (8001f0c ) 8001d06: 430a orrs r2, r1 8001d08: 635a str r2, [r3, #52] ; 0x34 8001d0a: e034 b.n 8001d76 } else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL) 8001d0c: 687b ldr r3, [r7, #4] 8001d0e: 695b ldr r3, [r3, #20] 8001d10: 3305 adds r3, #5 8001d12: d111 bne.n 8001d38 { /* Enable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_ENABLE(); 8001d14: 4b7d ldr r3, [pc, #500] ; (8001f0c ) 8001d16: 6b5a ldr r2, [r3, #52] ; 0x34 8001d18: 4b7c ldr r3, [pc, #496] ; (8001f0c ) 8001d1a: 2104 movs r1, #4 8001d1c: 438a bics r2, r1 8001d1e: 635a str r2, [r3, #52] ; 0x34 /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); 8001d20: 4b7a ldr r3, [pc, #488] ; (8001f0c ) 8001d22: 6b5b ldr r3, [r3, #52] ; 0x34 8001d24: 22f8 movs r2, #248 ; 0xf8 8001d26: 4393 bics r3, r2 8001d28: 0019 movs r1, r3 8001d2a: 687b ldr r3, [r7, #4] 8001d2c: 699b ldr r3, [r3, #24] 8001d2e: 00da lsls r2, r3, #3 8001d30: 4b76 ldr r3, [pc, #472] ; (8001f0c ) 8001d32: 430a orrs r2, r1 8001d34: 635a str r2, [r3, #52] ; 0x34 8001d36: e01e b.n 8001d76 } else { /* Disable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_DISABLE(); 8001d38: 4b74 ldr r3, [pc, #464] ; (8001f0c ) 8001d3a: 6b5a ldr r2, [r3, #52] ; 0x34 8001d3c: 4b73 ldr r3, [pc, #460] ; (8001f0c ) 8001d3e: 2104 movs r1, #4 8001d40: 430a orrs r2, r1 8001d42: 635a str r2, [r3, #52] ; 0x34 /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI14_DISABLE(); 8001d44: 4b71 ldr r3, [pc, #452] ; (8001f0c ) 8001d46: 6b5a ldr r2, [r3, #52] ; 0x34 8001d48: 4b70 ldr r3, [pc, #448] ; (8001f0c ) 8001d4a: 2101 movs r1, #1 8001d4c: 438a bics r2, r1 8001d4e: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001d50: f7fe fd60 bl 8000814 8001d54: 0003 movs r3, r0 8001d56: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) 8001d58: e008 b.n 8001d6c { if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) 8001d5a: f7fe fd5b bl 8000814 8001d5e: 0002 movs r2, r0 8001d60: 69bb ldr r3, [r7, #24] 8001d62: 1ad3 subs r3, r2, r3 8001d64: 2b02 cmp r3, #2 8001d66: d901 bls.n 8001d6c { return HAL_TIMEOUT; 8001d68: 2303 movs r3, #3 8001d6a: e111 b.n 8001f90 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) 8001d6c: 4b67 ldr r3, [pc, #412] ; (8001f0c ) 8001d6e: 6b5b ldr r3, [r3, #52] ; 0x34 8001d70: 2202 movs r2, #2 8001d72: 4013 ands r3, r2 8001d74: d1f1 bne.n 8001d5a } } #if defined(RCC_HSI48_SUPPORT) /*----------------------------- HSI48 Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 8001d76: 687b ldr r3, [r7, #4] 8001d78: 681b ldr r3, [r3, #0] 8001d7a: 2220 movs r2, #32 8001d7c: 4013 ands r3, r2 8001d7e: d05c beq.n 8001e3a { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* When the HSI48 is used as system clock it is not allowed to be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) || 8001d80: 4b62 ldr r3, [pc, #392] ; (8001f0c ) 8001d82: 685b ldr r3, [r3, #4] 8001d84: 220c movs r2, #12 8001d86: 4013 ands r3, r2 8001d88: 2b0c cmp r3, #12 8001d8a: d00e beq.n 8001daa ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48))) 8001d8c: 4b5f ldr r3, [pc, #380] ; (8001f0c ) 8001d8e: 685b ldr r3, [r3, #4] 8001d90: 220c movs r2, #12 8001d92: 4013 ands r3, r2 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) || 8001d94: 2b08 cmp r3, #8 8001d96: d114 bne.n 8001dc2 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48))) 8001d98: 4b5c ldr r3, [pc, #368] ; (8001f0c ) 8001d9a: 685a ldr r2, [r3, #4] 8001d9c: 23c0 movs r3, #192 ; 0xc0 8001d9e: 025b lsls r3, r3, #9 8001da0: 401a ands r2, r3 8001da2: 23c0 movs r3, #192 ; 0xc0 8001da4: 025b lsls r3, r3, #9 8001da6: 429a cmp r2, r3 8001da8: d10b bne.n 8001dc2 { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON)) 8001daa: 4b58 ldr r3, [pc, #352] ; (8001f0c ) 8001dac: 6b5a ldr r2, [r3, #52] ; 0x34 8001dae: 2380 movs r3, #128 ; 0x80 8001db0: 029b lsls r3, r3, #10 8001db2: 4013 ands r3, r2 8001db4: d040 beq.n 8001e38 8001db6: 687b ldr r3, [r7, #4] 8001db8: 6a1b ldr r3, [r3, #32] 8001dba: 2b01 cmp r3, #1 8001dbc: d03c beq.n 8001e38 { return HAL_ERROR; 8001dbe: 2301 movs r3, #1 8001dc0: e0e6 b.n 8001f90 } } else { /* Check the HSI48 State */ if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) 8001dc2: 687b ldr r3, [r7, #4] 8001dc4: 6a1b ldr r3, [r3, #32] 8001dc6: 2b00 cmp r3, #0 8001dc8: d01b beq.n 8001e02 { /* Enable the Internal High Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 8001dca: 4b50 ldr r3, [pc, #320] ; (8001f0c ) 8001dcc: 6b5a ldr r2, [r3, #52] ; 0x34 8001dce: 4b4f ldr r3, [pc, #316] ; (8001f0c ) 8001dd0: 2180 movs r1, #128 ; 0x80 8001dd2: 0249 lsls r1, r1, #9 8001dd4: 430a orrs r2, r1 8001dd6: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001dd8: f7fe fd1c bl 8000814 8001ddc: 0003 movs r3, r0 8001dde: 61bb str r3, [r7, #24] /* Wait till HSI48 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) 8001de0: e008 b.n 8001df4 { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 8001de2: f7fe fd17 bl 8000814 8001de6: 0002 movs r2, r0 8001de8: 69bb ldr r3, [r7, #24] 8001dea: 1ad3 subs r3, r2, r3 8001dec: 2b02 cmp r3, #2 8001dee: d901 bls.n 8001df4 { return HAL_TIMEOUT; 8001df0: 2303 movs r3, #3 8001df2: e0cd b.n 8001f90 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) 8001df4: 4b45 ldr r3, [pc, #276] ; (8001f0c ) 8001df6: 6b5a ldr r2, [r3, #52] ; 0x34 8001df8: 2380 movs r3, #128 ; 0x80 8001dfa: 029b lsls r3, r3, #10 8001dfc: 4013 ands r3, r2 8001dfe: d0f0 beq.n 8001de2 8001e00: e01b b.n 8001e3a } } else { /* Disable the Internal High Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 8001e02: 4b42 ldr r3, [pc, #264] ; (8001f0c ) 8001e04: 6b5a ldr r2, [r3, #52] ; 0x34 8001e06: 4b41 ldr r3, [pc, #260] ; (8001f0c ) 8001e08: 4943 ldr r1, [pc, #268] ; (8001f18 ) 8001e0a: 400a ands r2, r1 8001e0c: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001e0e: f7fe fd01 bl 8000814 8001e12: 0003 movs r3, r0 8001e14: 61bb str r3, [r7, #24] /* Wait till HSI48 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) 8001e16: e008 b.n 8001e2a { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 8001e18: f7fe fcfc bl 8000814 8001e1c: 0002 movs r2, r0 8001e1e: 69bb ldr r3, [r7, #24] 8001e20: 1ad3 subs r3, r2, r3 8001e22: 2b02 cmp r3, #2 8001e24: d901 bls.n 8001e2a { return HAL_TIMEOUT; 8001e26: 2303 movs r3, #3 8001e28: e0b2 b.n 8001f90 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) 8001e2a: 4b38 ldr r3, [pc, #224] ; (8001f0c ) 8001e2c: 6b5a ldr r2, [r3, #52] ; 0x34 8001e2e: 2380 movs r3, #128 ; 0x80 8001e30: 029b lsls r3, r3, #10 8001e32: 4013 ands r3, r2 8001e34: d1f0 bne.n 8001e18 8001e36: e000 b.n 8001e3a if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON)) 8001e38: 46c0 nop ; (mov r8, r8) #endif /* RCC_HSI48_SUPPORT */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8001e3a: 687b ldr r3, [r7, #4] 8001e3c: 6a5b ldr r3, [r3, #36] ; 0x24 8001e3e: 2b00 cmp r3, #0 8001e40: d100 bne.n 8001e44 8001e42: e0a4 b.n 8001f8e { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8001e44: 4b31 ldr r3, [pc, #196] ; (8001f0c ) 8001e46: 685b ldr r3, [r3, #4] 8001e48: 220c movs r2, #12 8001e4a: 4013 ands r3, r2 8001e4c: 2b08 cmp r3, #8 8001e4e: d100 bne.n 8001e52 8001e50: e078 b.n 8001f44 { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8001e52: 687b ldr r3, [r7, #4] 8001e54: 6a5b ldr r3, [r3, #36] ; 0x24 8001e56: 2b02 cmp r3, #2 8001e58: d14c bne.n 8001ef4 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8001e5a: 4b2c ldr r3, [pc, #176] ; (8001f0c ) 8001e5c: 681a ldr r2, [r3, #0] 8001e5e: 4b2b ldr r3, [pc, #172] ; (8001f0c ) 8001e60: 492e ldr r1, [pc, #184] ; (8001f1c ) 8001e62: 400a ands r2, r1 8001e64: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001e66: f7fe fcd5 bl 8000814 8001e6a: 0003 movs r3, r0 8001e6c: 61bb str r3, [r7, #24] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001e6e: e008 b.n 8001e82 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001e70: f7fe fcd0 bl 8000814 8001e74: 0002 movs r2, r0 8001e76: 69bb ldr r3, [r7, #24] 8001e78: 1ad3 subs r3, r2, r3 8001e7a: 2b02 cmp r3, #2 8001e7c: d901 bls.n 8001e82 { return HAL_TIMEOUT; 8001e7e: 2303 movs r3, #3 8001e80: e086 b.n 8001f90 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001e82: 4b22 ldr r3, [pc, #136] ; (8001f0c ) 8001e84: 681a ldr r2, [r3, #0] 8001e86: 2380 movs r3, #128 ; 0x80 8001e88: 049b lsls r3, r3, #18 8001e8a: 4013 ands r3, r2 8001e8c: d1f0 bne.n 8001e70 } } /* Configure the main PLL clock source, predivider and multiplication factor. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8001e8e: 4b1f ldr r3, [pc, #124] ; (8001f0c ) 8001e90: 6adb ldr r3, [r3, #44] ; 0x2c 8001e92: 220f movs r2, #15 8001e94: 4393 bics r3, r2 8001e96: 0019 movs r1, r3 8001e98: 687b ldr r3, [r7, #4] 8001e9a: 6b1a ldr r2, [r3, #48] ; 0x30 8001e9c: 4b1b ldr r3, [pc, #108] ; (8001f0c ) 8001e9e: 430a orrs r2, r1 8001ea0: 62da str r2, [r3, #44] ; 0x2c 8001ea2: 4b1a ldr r3, [pc, #104] ; (8001f0c ) 8001ea4: 685b ldr r3, [r3, #4] 8001ea6: 4a1e ldr r2, [pc, #120] ; (8001f20 ) 8001ea8: 4013 ands r3, r2 8001eaa: 0019 movs r1, r3 8001eac: 687b ldr r3, [r7, #4] 8001eae: 6ada ldr r2, [r3, #44] ; 0x2c 8001eb0: 687b ldr r3, [r7, #4] 8001eb2: 6a9b ldr r3, [r3, #40] ; 0x28 8001eb4: 431a orrs r2, r3 8001eb6: 4b15 ldr r3, [pc, #84] ; (8001f0c ) 8001eb8: 430a orrs r2, r1 8001eba: 605a str r2, [r3, #4] RCC_OscInitStruct->PLL.PREDIV, RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8001ebc: 4b13 ldr r3, [pc, #76] ; (8001f0c ) 8001ebe: 681a ldr r2, [r3, #0] 8001ec0: 4b12 ldr r3, [pc, #72] ; (8001f0c ) 8001ec2: 2180 movs r1, #128 ; 0x80 8001ec4: 0449 lsls r1, r1, #17 8001ec6: 430a orrs r2, r1 8001ec8: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001eca: f7fe fca3 bl 8000814 8001ece: 0003 movs r3, r0 8001ed0: 61bb str r3, [r7, #24] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001ed2: e008 b.n 8001ee6 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001ed4: f7fe fc9e bl 8000814 8001ed8: 0002 movs r2, r0 8001eda: 69bb ldr r3, [r7, #24] 8001edc: 1ad3 subs r3, r2, r3 8001ede: 2b02 cmp r3, #2 8001ee0: d901 bls.n 8001ee6 { return HAL_TIMEOUT; 8001ee2: 2303 movs r3, #3 8001ee4: e054 b.n 8001f90 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001ee6: 4b09 ldr r3, [pc, #36] ; (8001f0c ) 8001ee8: 681a ldr r2, [r3, #0] 8001eea: 2380 movs r3, #128 ; 0x80 8001eec: 049b lsls r3, r3, #18 8001eee: 4013 ands r3, r2 8001ef0: d0f0 beq.n 8001ed4 8001ef2: e04c b.n 8001f8e } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8001ef4: 4b05 ldr r3, [pc, #20] ; (8001f0c ) 8001ef6: 681a ldr r2, [r3, #0] 8001ef8: 4b04 ldr r3, [pc, #16] ; (8001f0c ) 8001efa: 4908 ldr r1, [pc, #32] ; (8001f1c ) 8001efc: 400a ands r2, r1 8001efe: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001f00: f7fe fc88 bl 8000814 8001f04: 0003 movs r3, r0 8001f06: 61bb str r3, [r7, #24] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001f08: e015 b.n 8001f36 8001f0a: 46c0 nop ; (mov r8, r8) 8001f0c: 40021000 .word 0x40021000 8001f10: 00001388 .word 0x00001388 8001f14: efffffff .word 0xefffffff 8001f18: fffeffff .word 0xfffeffff 8001f1c: feffffff .word 0xfeffffff 8001f20: ffc27fff .word 0xffc27fff { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001f24: f7fe fc76 bl 8000814 8001f28: 0002 movs r2, r0 8001f2a: 69bb ldr r3, [r7, #24] 8001f2c: 1ad3 subs r3, r2, r3 8001f2e: 2b02 cmp r3, #2 8001f30: d901 bls.n 8001f36 { return HAL_TIMEOUT; 8001f32: 2303 movs r3, #3 8001f34: e02c b.n 8001f90 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001f36: 4b18 ldr r3, [pc, #96] ; (8001f98 ) 8001f38: 681a ldr r2, [r3, #0] 8001f3a: 2380 movs r3, #128 ; 0x80 8001f3c: 049b lsls r3, r3, #18 8001f3e: 4013 ands r3, r2 8001f40: d1f0 bne.n 8001f24 8001f42: e024 b.n 8001f8e } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8001f44: 687b ldr r3, [r7, #4] 8001f46: 6a5b ldr r3, [r3, #36] ; 0x24 8001f48: 2b01 cmp r3, #1 8001f4a: d101 bne.n 8001f50 { return HAL_ERROR; 8001f4c: 2301 movs r3, #1 8001f4e: e01f b.n 8001f90 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8001f50: 4b11 ldr r3, [pc, #68] ; (8001f98 ) 8001f52: 685b ldr r3, [r3, #4] 8001f54: 617b str r3, [r7, #20] pll_config2 = RCC->CFGR2; 8001f56: 4b10 ldr r3, [pc, #64] ; (8001f98 ) 8001f58: 6adb ldr r3, [r3, #44] ; 0x2c 8001f5a: 613b str r3, [r7, #16] if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8001f5c: 697a ldr r2, [r7, #20] 8001f5e: 23c0 movs r3, #192 ; 0xc0 8001f60: 025b lsls r3, r3, #9 8001f62: 401a ands r2, r3 8001f64: 687b ldr r3, [r7, #4] 8001f66: 6a9b ldr r3, [r3, #40] ; 0x28 8001f68: 429a cmp r2, r3 8001f6a: d10e bne.n 8001f8a (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || 8001f6c: 693b ldr r3, [r7, #16] 8001f6e: 220f movs r2, #15 8001f70: 401a ands r2, r3 8001f72: 687b ldr r3, [r7, #4] 8001f74: 6b1b ldr r3, [r3, #48] ; 0x30 if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8001f76: 429a cmp r2, r3 8001f78: d107 bne.n 8001f8a (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) 8001f7a: 697a ldr r2, [r7, #20] 8001f7c: 23f0 movs r3, #240 ; 0xf0 8001f7e: 039b lsls r3, r3, #14 8001f80: 401a ands r2, r3 8001f82: 687b ldr r3, [r7, #4] 8001f84: 6adb ldr r3, [r3, #44] ; 0x2c (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || 8001f86: 429a cmp r2, r3 8001f88: d001 beq.n 8001f8e { return HAL_ERROR; 8001f8a: 2301 movs r3, #1 8001f8c: e000 b.n 8001f90 } } } } return HAL_OK; 8001f8e: 2300 movs r3, #0 } 8001f90: 0018 movs r0, r3 8001f92: 46bd mov sp, r7 8001f94: b008 add sp, #32 8001f96: bd80 pop {r7, pc} 8001f98: 40021000 .word 0x40021000 08001f9c : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8001f9c: b580 push {r7, lr} 8001f9e: b084 sub sp, #16 8001fa0: af00 add r7, sp, #0 8001fa2: 6078 str r0, [r7, #4] 8001fa4: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) 8001fa6: 687b ldr r3, [r7, #4] 8001fa8: 2b00 cmp r3, #0 8001faa: d101 bne.n 8001fb0 { return HAL_ERROR; 8001fac: 2301 movs r3, #1 8001fae: e0bf b.n 8002130 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 8001fb0: 4b61 ldr r3, [pc, #388] ; (8002138 ) 8001fb2: 681b ldr r3, [r3, #0] 8001fb4: 2201 movs r2, #1 8001fb6: 4013 ands r3, r2 8001fb8: 683a ldr r2, [r7, #0] 8001fba: 429a cmp r2, r3 8001fbc: d911 bls.n 8001fe2 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8001fbe: 4b5e ldr r3, [pc, #376] ; (8002138 ) 8001fc0: 681b ldr r3, [r3, #0] 8001fc2: 2201 movs r2, #1 8001fc4: 4393 bics r3, r2 8001fc6: 0019 movs r1, r3 8001fc8: 4b5b ldr r3, [pc, #364] ; (8002138 ) 8001fca: 683a ldr r2, [r7, #0] 8001fcc: 430a orrs r2, r1 8001fce: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8001fd0: 4b59 ldr r3, [pc, #356] ; (8002138 ) 8001fd2: 681b ldr r3, [r3, #0] 8001fd4: 2201 movs r2, #1 8001fd6: 4013 ands r3, r2 8001fd8: 683a ldr r2, [r7, #0] 8001fda: 429a cmp r2, r3 8001fdc: d001 beq.n 8001fe2 { return HAL_ERROR; 8001fde: 2301 movs r3, #1 8001fe0: e0a6 b.n 8002130 } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8001fe2: 687b ldr r3, [r7, #4] 8001fe4: 681b ldr r3, [r3, #0] 8001fe6: 2202 movs r2, #2 8001fe8: 4013 ands r3, r2 8001fea: d015 beq.n 8002018 { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8001fec: 687b ldr r3, [r7, #4] 8001fee: 681b ldr r3, [r3, #0] 8001ff0: 2204 movs r2, #4 8001ff2: 4013 ands r3, r2 8001ff4: d006 beq.n 8002004 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); 8001ff6: 4b51 ldr r3, [pc, #324] ; (800213c ) 8001ff8: 685a ldr r2, [r3, #4] 8001ffa: 4b50 ldr r3, [pc, #320] ; (800213c ) 8001ffc: 21e0 movs r1, #224 ; 0xe0 8001ffe: 00c9 lsls r1, r1, #3 8002000: 430a orrs r2, r1 8002002: 605a str r2, [r3, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8002004: 4b4d ldr r3, [pc, #308] ; (800213c ) 8002006: 685b ldr r3, [r3, #4] 8002008: 22f0 movs r2, #240 ; 0xf0 800200a: 4393 bics r3, r2 800200c: 0019 movs r1, r3 800200e: 687b ldr r3, [r7, #4] 8002010: 689a ldr r2, [r3, #8] 8002012: 4b4a ldr r3, [pc, #296] ; (800213c ) 8002014: 430a orrs r2, r1 8002016: 605a str r2, [r3, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8002018: 687b ldr r3, [r7, #4] 800201a: 681b ldr r3, [r3, #0] 800201c: 2201 movs r2, #1 800201e: 4013 ands r3, r2 8002020: d04c beq.n 80020bc { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8002022: 687b ldr r3, [r7, #4] 8002024: 685b ldr r3, [r3, #4] 8002026: 2b01 cmp r3, #1 8002028: d107 bne.n 800203a { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800202a: 4b44 ldr r3, [pc, #272] ; (800213c ) 800202c: 681a ldr r2, [r3, #0] 800202e: 2380 movs r3, #128 ; 0x80 8002030: 029b lsls r3, r3, #10 8002032: 4013 ands r3, r2 8002034: d120 bne.n 8002078 { return HAL_ERROR; 8002036: 2301 movs r3, #1 8002038: e07a b.n 8002130 } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 800203a: 687b ldr r3, [r7, #4] 800203c: 685b ldr r3, [r3, #4] 800203e: 2b02 cmp r3, #2 8002040: d107 bne.n 8002052 { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8002042: 4b3e ldr r3, [pc, #248] ; (800213c ) 8002044: 681a ldr r2, [r3, #0] 8002046: 2380 movs r3, #128 ; 0x80 8002048: 049b lsls r3, r3, #18 800204a: 4013 ands r3, r2 800204c: d114 bne.n 8002078 { return HAL_ERROR; 800204e: 2301 movs r3, #1 8002050: e06e b.n 8002130 } } #if defined(RCC_CFGR_SWS_HSI48) /* HSI48 is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) 8002052: 687b ldr r3, [r7, #4] 8002054: 685b ldr r3, [r3, #4] 8002056: 2b03 cmp r3, #3 8002058: d107 bne.n 800206a { /* Check the HSI48 ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) 800205a: 4b38 ldr r3, [pc, #224] ; (800213c ) 800205c: 6b5a ldr r2, [r3, #52] ; 0x34 800205e: 2380 movs r3, #128 ; 0x80 8002060: 029b lsls r3, r3, #10 8002062: 4013 ands r3, r2 8002064: d108 bne.n 8002078 { return HAL_ERROR; 8002066: 2301 movs r3, #1 8002068: e062 b.n 8002130 #endif /* RCC_CFGR_SWS_HSI48 */ /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800206a: 4b34 ldr r3, [pc, #208] ; (800213c ) 800206c: 681b ldr r3, [r3, #0] 800206e: 2202 movs r2, #2 8002070: 4013 ands r3, r2 8002072: d101 bne.n 8002078 { return HAL_ERROR; 8002074: 2301 movs r3, #1 8002076: e05b b.n 8002130 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8002078: 4b30 ldr r3, [pc, #192] ; (800213c ) 800207a: 685b ldr r3, [r3, #4] 800207c: 2203 movs r2, #3 800207e: 4393 bics r3, r2 8002080: 0019 movs r1, r3 8002082: 687b ldr r3, [r7, #4] 8002084: 685a ldr r2, [r3, #4] 8002086: 4b2d ldr r3, [pc, #180] ; (800213c ) 8002088: 430a orrs r2, r1 800208a: 605a str r2, [r3, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 800208c: f7fe fbc2 bl 8000814 8002090: 0003 movs r3, r0 8002092: 60fb str r3, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8002094: e009 b.n 80020aa { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 8002096: f7fe fbbd bl 8000814 800209a: 0002 movs r2, r0 800209c: 68fb ldr r3, [r7, #12] 800209e: 1ad3 subs r3, r2, r3 80020a0: 4a27 ldr r2, [pc, #156] ; (8002140 ) 80020a2: 4293 cmp r3, r2 80020a4: d901 bls.n 80020aa { return HAL_TIMEOUT; 80020a6: 2303 movs r3, #3 80020a8: e042 b.n 8002130 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80020aa: 4b24 ldr r3, [pc, #144] ; (800213c ) 80020ac: 685b ldr r3, [r3, #4] 80020ae: 220c movs r2, #12 80020b0: 401a ands r2, r3 80020b2: 687b ldr r3, [r7, #4] 80020b4: 685b ldr r3, [r3, #4] 80020b6: 009b lsls r3, r3, #2 80020b8: 429a cmp r2, r3 80020ba: d1ec bne.n 8002096 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 80020bc: 4b1e ldr r3, [pc, #120] ; (8002138 ) 80020be: 681b ldr r3, [r3, #0] 80020c0: 2201 movs r2, #1 80020c2: 4013 ands r3, r2 80020c4: 683a ldr r2, [r7, #0] 80020c6: 429a cmp r2, r3 80020c8: d211 bcs.n 80020ee { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80020ca: 4b1b ldr r3, [pc, #108] ; (8002138 ) 80020cc: 681b ldr r3, [r3, #0] 80020ce: 2201 movs r2, #1 80020d0: 4393 bics r3, r2 80020d2: 0019 movs r1, r3 80020d4: 4b18 ldr r3, [pc, #96] ; (8002138 ) 80020d6: 683a ldr r2, [r7, #0] 80020d8: 430a orrs r2, r1 80020da: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 80020dc: 4b16 ldr r3, [pc, #88] ; (8002138 ) 80020de: 681b ldr r3, [r3, #0] 80020e0: 2201 movs r2, #1 80020e2: 4013 ands r3, r2 80020e4: 683a ldr r2, [r7, #0] 80020e6: 429a cmp r2, r3 80020e8: d001 beq.n 80020ee { return HAL_ERROR; 80020ea: 2301 movs r3, #1 80020ec: e020 b.n 8002130 } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80020ee: 687b ldr r3, [r7, #4] 80020f0: 681b ldr r3, [r3, #0] 80020f2: 2204 movs r2, #4 80020f4: 4013 ands r3, r2 80020f6: d009 beq.n 800210c { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); 80020f8: 4b10 ldr r3, [pc, #64] ; (800213c ) 80020fa: 685b ldr r3, [r3, #4] 80020fc: 4a11 ldr r2, [pc, #68] ; (8002144 ) 80020fe: 4013 ands r3, r2 8002100: 0019 movs r1, r3 8002102: 687b ldr r3, [r7, #4] 8002104: 68da ldr r2, [r3, #12] 8002106: 4b0d ldr r3, [pc, #52] ; (800213c ) 8002108: 430a orrs r2, r1 800210a: 605a str r2, [r3, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; 800210c: f000 f820 bl 8002150 8002110: 0001 movs r1, r0 8002112: 4b0a ldr r3, [pc, #40] ; (800213c ) 8002114: 685b ldr r3, [r3, #4] 8002116: 091b lsrs r3, r3, #4 8002118: 220f movs r2, #15 800211a: 4013 ands r3, r2 800211c: 4a0a ldr r2, [pc, #40] ; (8002148 ) 800211e: 5cd3 ldrb r3, [r2, r3] 8002120: 000a movs r2, r1 8002122: 40da lsrs r2, r3 8002124: 4b09 ldr r3, [pc, #36] ; (800214c ) 8002126: 601a str r2, [r3, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); 8002128: 2003 movs r0, #3 800212a: f7fe fb2d bl 8000788 return HAL_OK; 800212e: 2300 movs r3, #0 } 8002130: 0018 movs r0, r3 8002132: 46bd mov sp, r7 8002134: b004 add sp, #16 8002136: bd80 pop {r7, pc} 8002138: 40022000 .word 0x40022000 800213c: 40021000 .word 0x40021000 8002140: 00001388 .word 0x00001388 8002144: fffff8ff .word 0xfffff8ff 8002148: 08002494 .word 0x08002494 800214c: 20000000 .word 0x20000000 08002150 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8002150: b580 push {r7, lr} 8002152: b086 sub sp, #24 8002154: af00 add r7, sp, #0 static const uint8_t aPLLMULFactorTable[16U] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; static const uint8_t aPredivFactorTable[16U] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8002156: 2300 movs r3, #0 8002158: 60fb str r3, [r7, #12] 800215a: 2300 movs r3, #0 800215c: 60bb str r3, [r7, #8] 800215e: 2300 movs r3, #0 8002160: 617b str r3, [r7, #20] 8002162: 2300 movs r3, #0 8002164: 607b str r3, [r7, #4] uint32_t sysclockfreq = 0U; 8002166: 2300 movs r3, #0 8002168: 613b str r3, [r7, #16] tmpreg = RCC->CFGR; 800216a: 4b2d ldr r3, [pc, #180] ; (8002220 ) 800216c: 685b ldr r3, [r3, #4] 800216e: 60fb str r3, [r7, #12] /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8002170: 68fb ldr r3, [r7, #12] 8002172: 220c movs r2, #12 8002174: 4013 ands r3, r2 8002176: 2b0c cmp r3, #12 8002178: d046 beq.n 8002208 800217a: d848 bhi.n 800220e 800217c: 2b04 cmp r3, #4 800217e: d002 beq.n 8002186 8002180: 2b08 cmp r3, #8 8002182: d003 beq.n 800218c 8002184: e043 b.n 800220e { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8002186: 4b27 ldr r3, [pc, #156] ; (8002224 ) 8002188: 613b str r3, [r7, #16] break; 800218a: e043 b.n 8002214 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER]; 800218c: 68fb ldr r3, [r7, #12] 800218e: 0c9b lsrs r3, r3, #18 8002190: 220f movs r2, #15 8002192: 4013 ands r3, r2 8002194: 4a24 ldr r2, [pc, #144] ; (8002228 ) 8002196: 5cd3 ldrb r3, [r2, r3] 8002198: 607b str r3, [r7, #4] prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER]; 800219a: 4b21 ldr r3, [pc, #132] ; (8002220 ) 800219c: 6adb ldr r3, [r3, #44] ; 0x2c 800219e: 220f movs r2, #15 80021a0: 4013 ands r3, r2 80021a2: 4a22 ldr r2, [pc, #136] ; (800222c ) 80021a4: 5cd3 ldrb r3, [r2, r3] 80021a6: 60bb str r3, [r7, #8] if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE) 80021a8: 68fa ldr r2, [r7, #12] 80021aa: 23c0 movs r3, #192 ; 0xc0 80021ac: 025b lsls r3, r3, #9 80021ae: 401a ands r2, r3 80021b0: 2380 movs r3, #128 ; 0x80 80021b2: 025b lsls r3, r3, #9 80021b4: 429a cmp r2, r3 80021b6: d109 bne.n 80021cc { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); 80021b8: 68b9 ldr r1, [r7, #8] 80021ba: 481a ldr r0, [pc, #104] ; (8002224 ) 80021bc: f7fd ffa4 bl 8000108 <__udivsi3> 80021c0: 0003 movs r3, r0 80021c2: 001a movs r2, r3 80021c4: 687b ldr r3, [r7, #4] 80021c6: 4353 muls r3, r2 80021c8: 617b str r3, [r7, #20] 80021ca: e01a b.n 8002202 } #if defined(RCC_CFGR_PLLSRC_HSI48_PREDIV) else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48) 80021cc: 68fa ldr r2, [r7, #12] 80021ce: 23c0 movs r3, #192 ; 0xc0 80021d0: 025b lsls r3, r3, #9 80021d2: 401a ands r2, r3 80021d4: 23c0 movs r3, #192 ; 0xc0 80021d6: 025b lsls r3, r3, #9 80021d8: 429a cmp r2, r3 80021da: d109 bne.n 80021f0 { /* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSI48_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); 80021dc: 68b9 ldr r1, [r7, #8] 80021de: 4814 ldr r0, [pc, #80] ; (8002230 ) 80021e0: f7fd ff92 bl 8000108 <__udivsi3> 80021e4: 0003 movs r3, r0 80021e6: 001a movs r2, r3 80021e8: 687b ldr r3, [r7, #4] 80021ea: 4353 muls r3, r2 80021ec: 617b str r3, [r7, #20] 80021ee: e008 b.n 8002202 #endif /* RCC_CFGR_PLLSRC_HSI48_PREDIV */ else { #if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)) /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); 80021f0: 68b9 ldr r1, [r7, #8] 80021f2: 480c ldr r0, [pc, #48] ; (8002224 ) 80021f4: f7fd ff88 bl 8000108 <__udivsi3> 80021f8: 0003 movs r3, r0 80021fa: 001a movs r2, r3 80021fc: 687b ldr r3, [r7, #4] 80021fe: 4353 muls r3, r2 8002200: 617b str r3, [r7, #20] #else /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); #endif } sysclockfreq = pllclk; 8002202: 697b ldr r3, [r7, #20] 8002204: 613b str r3, [r7, #16] break; 8002206: e005 b.n 8002214 } #if defined(RCC_CFGR_SWS_HSI48) case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */ { sysclockfreq = HSI48_VALUE; 8002208: 4b09 ldr r3, [pc, #36] ; (8002230 ) 800220a: 613b str r3, [r7, #16] break; 800220c: e002 b.n 8002214 } #endif /* RCC_CFGR_SWS_HSI48 */ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 800220e: 4b05 ldr r3, [pc, #20] ; (8002224 ) 8002210: 613b str r3, [r7, #16] break; 8002212: 46c0 nop ; (mov r8, r8) } } return sysclockfreq; 8002214: 693b ldr r3, [r7, #16] } 8002216: 0018 movs r0, r3 8002218: 46bd mov sp, r7 800221a: b006 add sp, #24 800221c: bd80 pop {r7, pc} 800221e: 46c0 nop ; (mov r8, r8) 8002220: 40021000 .word 0x40021000 8002224: 007a1200 .word 0x007a1200 8002228: 080024a4 .word 0x080024a4 800222c: 080024b4 .word 0x080024b4 8002230: 02dc6c00 .word 0x02dc6c00 08002234 : * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8002234: b580 push {r7, lr} 8002236: b086 sub sp, #24 8002238: af00 add r7, sp, #0 800223a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800223c: 2300 movs r3, #0 800223e: 613b str r3, [r7, #16] uint32_t temp_reg = 0U; 8002240: 2300 movs r3, #0 8002242: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*---------------------------- RTC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) 8002244: 687b ldr r3, [r7, #4] 8002246: 681a ldr r2, [r3, #0] 8002248: 2380 movs r3, #128 ; 0x80 800224a: 025b lsls r3, r3, #9 800224c: 4013 ands r3, r2 800224e: d100 bne.n 8002252 8002250: e08e b.n 8002370 { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); FlagStatus pwrclkchanged = RESET; 8002252: 2017 movs r0, #23 8002254: 183b adds r3, r7, r0 8002256: 2200 movs r2, #0 8002258: 701a strb r2, [r3, #0] /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 800225a: 4b67 ldr r3, [pc, #412] ; (80023f8 ) 800225c: 69da ldr r2, [r3, #28] 800225e: 2380 movs r3, #128 ; 0x80 8002260: 055b lsls r3, r3, #21 8002262: 4013 ands r3, r2 8002264: d110 bne.n 8002288 { __HAL_RCC_PWR_CLK_ENABLE(); 8002266: 4b64 ldr r3, [pc, #400] ; (80023f8 ) 8002268: 69da ldr r2, [r3, #28] 800226a: 4b63 ldr r3, [pc, #396] ; (80023f8 ) 800226c: 2180 movs r1, #128 ; 0x80 800226e: 0549 lsls r1, r1, #21 8002270: 430a orrs r2, r1 8002272: 61da str r2, [r3, #28] 8002274: 4b60 ldr r3, [pc, #384] ; (80023f8 ) 8002276: 69da ldr r2, [r3, #28] 8002278: 2380 movs r3, #128 ; 0x80 800227a: 055b lsls r3, r3, #21 800227c: 4013 ands r3, r2 800227e: 60bb str r3, [r7, #8] 8002280: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8002282: 183b adds r3, r7, r0 8002284: 2201 movs r2, #1 8002286: 701a strb r2, [r3, #0] } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8002288: 4b5c ldr r3, [pc, #368] ; (80023fc ) 800228a: 681a ldr r2, [r3, #0] 800228c: 2380 movs r3, #128 ; 0x80 800228e: 005b lsls r3, r3, #1 8002290: 4013 ands r3, r2 8002292: d11a bne.n 80022ca { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8002294: 4b59 ldr r3, [pc, #356] ; (80023fc ) 8002296: 681a ldr r2, [r3, #0] 8002298: 4b58 ldr r3, [pc, #352] ; (80023fc ) 800229a: 2180 movs r1, #128 ; 0x80 800229c: 0049 lsls r1, r1, #1 800229e: 430a orrs r2, r1 80022a0: 601a str r2, [r3, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80022a2: f7fe fab7 bl 8000814 80022a6: 0003 movs r3, r0 80022a8: 613b str r3, [r7, #16] while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80022aa: e008 b.n 80022be { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80022ac: f7fe fab2 bl 8000814 80022b0: 0002 movs r2, r0 80022b2: 693b ldr r3, [r7, #16] 80022b4: 1ad3 subs r3, r2, r3 80022b6: 2b64 cmp r3, #100 ; 0x64 80022b8: d901 bls.n 80022be { return HAL_TIMEOUT; 80022ba: 2303 movs r3, #3 80022bc: e097 b.n 80023ee while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80022be: 4b4f ldr r3, [pc, #316] ; (80023fc ) 80022c0: 681a ldr r2, [r3, #0] 80022c2: 2380 movs r3, #128 ; 0x80 80022c4: 005b lsls r3, r3, #1 80022c6: 4013 ands r3, r2 80022c8: d0f0 beq.n 80022ac } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 80022ca: 4b4b ldr r3, [pc, #300] ; (80023f8 ) 80022cc: 6a1a ldr r2, [r3, #32] 80022ce: 23c0 movs r3, #192 ; 0xc0 80022d0: 009b lsls r3, r3, #2 80022d2: 4013 ands r3, r2 80022d4: 60fb str r3, [r7, #12] if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 80022d6: 68fb ldr r3, [r7, #12] 80022d8: 2b00 cmp r3, #0 80022da: d034 beq.n 8002346 80022dc: 687b ldr r3, [r7, #4] 80022de: 685a ldr r2, [r3, #4] 80022e0: 23c0 movs r3, #192 ; 0xc0 80022e2: 009b lsls r3, r3, #2 80022e4: 4013 ands r3, r2 80022e6: 68fa ldr r2, [r7, #12] 80022e8: 429a cmp r2, r3 80022ea: d02c beq.n 8002346 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 80022ec: 4b42 ldr r3, [pc, #264] ; (80023f8 ) 80022ee: 6a1b ldr r3, [r3, #32] 80022f0: 4a43 ldr r2, [pc, #268] ; (8002400 ) 80022f2: 4013 ands r3, r2 80022f4: 60fb str r3, [r7, #12] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 80022f6: 4b40 ldr r3, [pc, #256] ; (80023f8 ) 80022f8: 6a1a ldr r2, [r3, #32] 80022fa: 4b3f ldr r3, [pc, #252] ; (80023f8 ) 80022fc: 2180 movs r1, #128 ; 0x80 80022fe: 0249 lsls r1, r1, #9 8002300: 430a orrs r2, r1 8002302: 621a str r2, [r3, #32] __HAL_RCC_BACKUPRESET_RELEASE(); 8002304: 4b3c ldr r3, [pc, #240] ; (80023f8 ) 8002306: 6a1a ldr r2, [r3, #32] 8002308: 4b3b ldr r3, [pc, #236] ; (80023f8 ) 800230a: 493e ldr r1, [pc, #248] ; (8002404 ) 800230c: 400a ands r2, r1 800230e: 621a str r2, [r3, #32] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 8002310: 4b39 ldr r3, [pc, #228] ; (80023f8 ) 8002312: 68fa ldr r2, [r7, #12] 8002314: 621a str r2, [r3, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8002316: 68fb ldr r3, [r7, #12] 8002318: 2201 movs r2, #1 800231a: 4013 ands r3, r2 800231c: d013 beq.n 8002346 { /* Get Start Tick */ tickstart = HAL_GetTick(); 800231e: f7fe fa79 bl 8000814 8002322: 0003 movs r3, r0 8002324: 613b str r3, [r7, #16] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8002326: e009 b.n 800233c { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8002328: f7fe fa74 bl 8000814 800232c: 0002 movs r2, r0 800232e: 693b ldr r3, [r7, #16] 8002330: 1ad3 subs r3, r2, r3 8002332: 4a35 ldr r2, [pc, #212] ; (8002408 ) 8002334: 4293 cmp r3, r2 8002336: d901 bls.n 800233c { return HAL_TIMEOUT; 8002338: 2303 movs r3, #3 800233a: e058 b.n 80023ee while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800233c: 4b2e ldr r3, [pc, #184] ; (80023f8 ) 800233e: 6a1b ldr r3, [r3, #32] 8002340: 2202 movs r2, #2 8002342: 4013 ands r3, r2 8002344: d0f0 beq.n 8002328 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8002346: 4b2c ldr r3, [pc, #176] ; (80023f8 ) 8002348: 6a1b ldr r3, [r3, #32] 800234a: 4a2d ldr r2, [pc, #180] ; (8002400 ) 800234c: 4013 ands r3, r2 800234e: 0019 movs r1, r3 8002350: 687b ldr r3, [r7, #4] 8002352: 685a ldr r2, [r3, #4] 8002354: 4b28 ldr r3, [pc, #160] ; (80023f8 ) 8002356: 430a orrs r2, r1 8002358: 621a str r2, [r3, #32] /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) 800235a: 2317 movs r3, #23 800235c: 18fb adds r3, r7, r3 800235e: 781b ldrb r3, [r3, #0] 8002360: 2b01 cmp r3, #1 8002362: d105 bne.n 8002370 { __HAL_RCC_PWR_CLK_DISABLE(); 8002364: 4b24 ldr r3, [pc, #144] ; (80023f8 ) 8002366: 69da ldr r2, [r3, #28] 8002368: 4b23 ldr r3, [pc, #140] ; (80023f8 ) 800236a: 4928 ldr r1, [pc, #160] ; (800240c ) 800236c: 400a ands r2, r1 800236e: 61da str r2, [r3, #28] } } /*------------------------------- USART1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 8002370: 687b ldr r3, [r7, #4] 8002372: 681b ldr r3, [r3, #0] 8002374: 2201 movs r2, #1 8002376: 4013 ands r3, r2 8002378: d009 beq.n 800238e { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 800237a: 4b1f ldr r3, [pc, #124] ; (80023f8 ) 800237c: 6b1b ldr r3, [r3, #48] ; 0x30 800237e: 2203 movs r2, #3 8002380: 4393 bics r3, r2 8002382: 0019 movs r1, r3 8002384: 687b ldr r3, [r7, #4] 8002386: 689a ldr r2, [r3, #8] 8002388: 4b1b ldr r3, [pc, #108] ; (80023f8 ) 800238a: 430a orrs r2, r1 800238c: 631a str r2, [r3, #48] ; 0x30 __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); } #endif /* STM32F091xC || STM32F098xx */ /*------------------------------ I2C1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 800238e: 687b ldr r3, [r7, #4] 8002390: 681b ldr r3, [r3, #0] 8002392: 2220 movs r2, #32 8002394: 4013 ands r3, r2 8002396: d009 beq.n 80023ac { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 8002398: 4b17 ldr r3, [pc, #92] ; (80023f8 ) 800239a: 6b1b ldr r3, [r3, #48] ; 0x30 800239c: 2210 movs r2, #16 800239e: 4393 bics r3, r2 80023a0: 0019 movs r1, r3 80023a2: 687b ldr r3, [r7, #4] 80023a4: 68da ldr r2, [r3, #12] 80023a6: 4b14 ldr r3, [pc, #80] ; (80023f8 ) 80023a8: 430a orrs r2, r1 80023aa: 631a str r2, [r3, #48] ; 0x30 } #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6) /*------------------------------ USB Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 80023ac: 687b ldr r3, [r7, #4] 80023ae: 681a ldr r2, [r3, #0] 80023b0: 2380 movs r3, #128 ; 0x80 80023b2: 029b lsls r3, r3, #10 80023b4: 4013 ands r3, r2 80023b6: d009 beq.n 80023cc { /* Check the parameters */ assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 80023b8: 4b0f ldr r3, [pc, #60] ; (80023f8 ) 80023ba: 6b1b ldr r3, [r3, #48] ; 0x30 80023bc: 2280 movs r2, #128 ; 0x80 80023be: 4393 bics r3, r2 80023c0: 0019 movs r1, r3 80023c2: 687b ldr r3, [r7, #4] 80023c4: 695a ldr r2, [r3, #20] 80023c6: 4b0c ldr r3, [pc, #48] ; (80023f8 ) 80023c8: 430a orrs r2, r1 80023ca: 631a str r2, [r3, #48] ; 0x30 #if defined(STM32F042x6) || defined(STM32F048xx)\ || defined(STM32F051x8) || defined(STM32F058xx)\ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ || defined(STM32F091xC) || defined(STM32F098xx) /*------------------------------ CEC clock Configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 80023cc: 687b ldr r3, [r7, #4] 80023ce: 681a ldr r2, [r3, #0] 80023d0: 2380 movs r3, #128 ; 0x80 80023d2: 00db lsls r3, r3, #3 80023d4: 4013 ands r3, r2 80023d6: d009 beq.n 80023ec { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 80023d8: 4b07 ldr r3, [pc, #28] ; (80023f8 ) 80023da: 6b1b ldr r3, [r3, #48] ; 0x30 80023dc: 2240 movs r2, #64 ; 0x40 80023de: 4393 bics r3, r2 80023e0: 0019 movs r1, r3 80023e2: 687b ldr r3, [r7, #4] 80023e4: 691a ldr r2, [r3, #16] 80023e6: 4b04 ldr r3, [pc, #16] ; (80023f8 ) 80023e8: 430a orrs r2, r1 80023ea: 631a str r2, [r3, #48] ; 0x30 #endif /* STM32F042x6 || STM32F048xx || */ /* STM32F051x8 || STM32F058xx || */ /* STM32F071xB || STM32F072xB || STM32F078xx || */ /* STM32F091xC || STM32F098xx */ return HAL_OK; 80023ec: 2300 movs r3, #0 } 80023ee: 0018 movs r0, r3 80023f0: 46bd mov sp, r7 80023f2: b006 add sp, #24 80023f4: bd80 pop {r7, pc} 80023f6: 46c0 nop ; (mov r8, r8) 80023f8: 40021000 .word 0x40021000 80023fc: 40007000 .word 0x40007000 8002400: fffffcff .word 0xfffffcff 8002404: fffeffff .word 0xfffeffff 8002408: 00001388 .word 0x00001388 800240c: efffffff .word 0xefffffff 08002410 <__libc_init_array>: 8002410: b570 push {r4, r5, r6, lr} 8002412: 2600 movs r6, #0 8002414: 4d0c ldr r5, [pc, #48] ; (8002448 <__libc_init_array+0x38>) 8002416: 4c0d ldr r4, [pc, #52] ; (800244c <__libc_init_array+0x3c>) 8002418: 1b64 subs r4, r4, r5 800241a: 10a4 asrs r4, r4, #2 800241c: 42a6 cmp r6, r4 800241e: d109 bne.n 8002434 <__libc_init_array+0x24> 8002420: 2600 movs r6, #0 8002422: f000 f82b bl 800247c <_init> 8002426: 4d0a ldr r5, [pc, #40] ; (8002450 <__libc_init_array+0x40>) 8002428: 4c0a ldr r4, [pc, #40] ; (8002454 <__libc_init_array+0x44>) 800242a: 1b64 subs r4, r4, r5 800242c: 10a4 asrs r4, r4, #2 800242e: 42a6 cmp r6, r4 8002430: d105 bne.n 800243e <__libc_init_array+0x2e> 8002432: bd70 pop {r4, r5, r6, pc} 8002434: 00b3 lsls r3, r6, #2 8002436: 58eb ldr r3, [r5, r3] 8002438: 4798 blx r3 800243a: 3601 adds r6, #1 800243c: e7ee b.n 800241c <__libc_init_array+0xc> 800243e: 00b3 lsls r3, r6, #2 8002440: 58eb ldr r3, [r5, r3] 8002442: 4798 blx r3 8002444: 3601 adds r6, #1 8002446: e7f2 b.n 800242e <__libc_init_array+0x1e> 8002448: 080024c4 .word 0x080024c4 800244c: 080024c4 .word 0x080024c4 8002450: 080024c4 .word 0x080024c4 8002454: 080024c8 .word 0x080024c8 08002458 : 8002458: 2300 movs r3, #0 800245a: b510 push {r4, lr} 800245c: 429a cmp r2, r3 800245e: d100 bne.n 8002462 8002460: bd10 pop {r4, pc} 8002462: 5ccc ldrb r4, [r1, r3] 8002464: 54c4 strb r4, [r0, r3] 8002466: 3301 adds r3, #1 8002468: e7f8 b.n 800245c 0800246a : 800246a: 0003 movs r3, r0 800246c: 1882 adds r2, r0, r2 800246e: 4293 cmp r3, r2 8002470: d100 bne.n 8002474 8002472: 4770 bx lr 8002474: 7019 strb r1, [r3, #0] 8002476: 3301 adds r3, #1 8002478: e7f9 b.n 800246e ... 0800247c <_init>: 800247c: b5f8 push {r3, r4, r5, r6, r7, lr} 800247e: 46c0 nop ; (mov r8, r8) 8002480: bcf8 pop {r3, r4, r5, r6, r7} 8002482: bc08 pop {r3} 8002484: 469e mov lr, r3 8002486: 4770 bx lr 08002488 <_fini>: 8002488: b5f8 push {r3, r4, r5, r6, r7, lr} 800248a: 46c0 nop ; (mov r8, r8) 800248c: bcf8 pop {r3, r4, r5, r6, r7} 800248e: bc08 pop {r3} 8002490: 469e mov lr, r3 8002492: 4770 bx lr