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base: FaSTTUBe:260f57f3ae0109ff0814d04a09536ca728a2e024
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FaSTTUBe:main
FaSTTUBe:FT25_TS-DCDC-V1
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FaSTTUBe:main
FaSTTUBe:FT25_TS-DCDC-V1

2 Commits
260f57f3ae ... 8f87e24109

Author SHA1 Message Date
Frederico Boavida
8f87e24109 Merge branch 'main' of https://git.fasttube.de/FaSTTUBe/TS-DCDC 
new nmos + sim
 2025-04-09 13:35:53 +02:00
Frederico Boavida
0639b9857e new nmos 2025-04-09 13:26:08 +02:00
14 changed files with 1283 additions and 95 deletions
Show Stats Expand all files Collapse all files

33
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58
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34
Hardware/sim/IPW60R045CP.lib Normal file
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.SUBCKT IPW60R045CP_L0 drain gate source
Lg gate g1 8n
Ld drain d1 3n
Ls source s1 8n
Rs s1 s2 1.5m
Rg g1 g2 1.3
M1 d2 g2 s2 s2 DMOS L=1u W=1u
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Dbd s2 d2 Dbt
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6
Hardware/sim/IPD60R.asy → Hardware/sim/IPW60R045CP_L0.asy
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SymbolType BLOCK
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SYMATTR Prefix X
SYMATTR Value IPD60R210PFD7S_L0
SYMATTR ModelFile C:\Users\frede\Downloads\Infineon-Power_CoolMOS_PFD7_MOSFET_600V_Spice-SimulationModels-v03_00-EN\IPD60R.lib
WINDOW 3 8 40 Top 2
SYMATTR Prefix X
SYMATTR Value IPW60R045CP_L0
SYMATTR ModelFile C:\Users\frede\OneDrive\Dokumente\Fasttube\FT25\TS-DCDC\Hardware\sim\IPW60R045CP.lib
PIN -96 0 LEFT 8
PINATTR PinName drain
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0
Hardware/sim/IPW60R045CP_LO.txt Normal file
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74
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Version 4
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WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 420 1 1ľ 1ľ 2 3 1)
SYMATTR Value PULSE(0 300 1m 100u 100u 1 1)
SYMATTR InstName V1
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SYMBOL cap 448 208 R0
SYMATTR InstName C1
SYMATTR Value 44ľ
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SYMATTR Value 20ľ
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SYMATTR InstName R1
SYMATTR Value 6.6Mega
SYMBOL res -48 240 R0
SYMBOL res -144 256 R0
SYMATTR InstName R2
SYMATTR Value 150k
SYMBOL cap -112 272 R0
SYMATTR Value 80k
SYMBOL cap -240 272 R0
SYMATTR InstName C2
SYMATTR Value 3.3ľ
SYMBOL IPD60R 160 384 M0
SYMATTR InstName U1
SYMATTR Value 20ľ
SYMATTR SpiceLine Rser=0.01
SYMBOL zener 96 352 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value CDZV18B
SYMBOL IPW60R045CP_L0 320 384 M0
SYMATTR InstName U2
SYMBOL res -384 272 R0
SYMATTR InstName R3
SYMATTR Value 0.1
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11
Hardware/sim/precharge_sim.log
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LTspice 24.0.12 for Windows
Circuit: * C:\Users\frede\OneDrive\Dokumente\Fasttube\FT25\TS-DCDC\Hardware\sim\precharge_sim.asc
Start Time: Sun Mar 2 17:00:25 2025
Start Time: Wed Apr 9 13:34:20 2025
solver = Normal
Maximum thread count: 8
tnom = 27
temp = 27
method = modified trap
Instance "m:u1:1:r": Length shorter than recommended for a level 1 MOSFET.
Instance "m:u1:1:r": Width narrower than recommended for a level 1 MOSFET.
Instance "m:u1:1:1": Width narrower than recommended for a level 3 MOSFET.
WARNING: Specified period is not longer than the sum of Trise, Tfall, and Ton for v1. Increasing period to 1.0002
Instance "m:u2:r": Length shorter than recommended for a level 1 MOSFET.
Instance "m:u2:r": Width narrower than recommended for a level 1 MOSFET.
Instance "m:u2:1": Width narrower than recommended for a level 3 MOSFET.
.OP point found by inspection.
Total elapsed time: 0.097 seconds.
Total elapsed time: 0.132 seconds.

BIN
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BIN
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BIN
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142
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