FaSTTUBe/TS-DCDC
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Merge branch 'main' of https://git.fasttube.de/FaSTTUBe/TS-DCDC

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new nmos + sim
This commit is contained in:
Frederico Boavida
2025-04-09 13:35:53 +02:00
parent 0639b9857e 260f57f3ae
commit 8f87e24109
18 changed files with 17365 additions and 14653 deletions
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17
Hardware/sim/IPD60R.asy
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@ -1,17 +0,0 @@
Version 4
SymbolType BLOCK
RECTANGLE Normal -96 -40 112 40
WINDOW 0 8 -40 Bottom 2
SYMATTR Prefix X
SYMATTR Value IPD60R210PFD7S_L0
SYMATTR ModelFile C:\Users\frede\Downloads\Infineon-Power_CoolMOS_PFD7_MOSFET_600V_Spice-SimulationModels-v03_00-EN\IPD60R.lib
WINDOW 3 8 40 Top 2
PIN -96 0 LEFT 8
PINATTR PinName drain
PINATTR SpiceOrder 1
PIN 112 -16 RIGHT 8
PINATTR PinName gate
PINATTR SpiceOrder 2
PIN 112 16 RIGHT 8
PINATTR PinName source
PINATTR SpiceOrder 3

8
Hardware/sim/precharge_sim.asc
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@ -11,12 +11,13 @@ WIRE 80 240 -128 240
WIRE 176 240 80 240
WIRE -224 272 -224 240
WIRE -128 272 -128 240
WIRE -368 288 -368 272
WIRE 80 288 80 240
WIRE 176 368 176 240
WIRE 208 368 176 368
WIRE 464 384 464 272
WIRE 464 384 416 384
WIRE -368 400 -368 272
WIRE -368 400 -368 368
WIRE -336 400 -368 400
WIRE -224 400 -224 336
WIRE -224 400 -336 400
@ -31,7 +32,7 @@ SYMBOL voltage -368 176 R0
WINDOW 3 -65 -79 VRight 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 400 1m 100u 100u 1 1)
SYMATTR Value PULSE(0 300 1m 100u 100u 1 1)
SYMATTR InstName V1
SYMBOL cap 448 208 R0
SYMATTR InstName C1
@ -53,4 +54,7 @@ SYMATTR InstName D1
SYMATTR Value CDZV18B
SYMBOL IPW60R045CP_L0 320 384 M0
SYMATTR InstName U2
SYMBOL res -384 272 R0
SYMATTR InstName R3
SYMATTR Value 0.1
TEXT -232 504 Left 2 !.tran 0 2 0.7 1m

4
Hardware/sim/precharge_sim.log
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@ -1,6 +1,6 @@
LTspice 24.0.12 for Windows
Circuit: * C:\Users\frede\OneDrive\Dokumente\Fasttube\FT25\TS-DCDC\Hardware\sim\precharge_sim.asc
Start Time: Tue Apr 8 22:26:57 2025
Start Time: Wed Apr 9 13:34:20 2025
solver = Normal
Maximum thread count: 8
tnom = 27
@ -11,5 +11,5 @@ Instance "m:u2:r": Length shorter than recommended for a level 1 MOSFET.
Instance "m:u2:r": Width narrower than recommended for a level 1 MOSFET.
Instance "m:u2:1": Width narrower than recommended for a level 3 MOSFET.
.OP point found by inspection.
Total elapsed time: 0.129 seconds.
Total elapsed time: 0.132 seconds.

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Hardware/sim/precharge_sim.op.raw
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Hardware/sim/precharge_sim.raw
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57
Hardware/sim/sim_gpt.asc
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@ -1,57 +0,0 @@
Version 4
SHEET 1 880 680
WIRE 96 80 48 80
WIRE 224 80 176 80
WIRE 224 144 224 80
WIRE 96 160 96 80
WIRE 224 160 96 160
WIRE 96 208 96 160
WIRE 224 208 224 160
WIRE 224 256 224 208
WIRE 224 256 96 256
WIRE 96 256 96 208
WIRE 96 304 96 256
WIRE 96 304 48 304
WIRE 224 304 224 256
WIRE 224 304 272 304
WIRE 272 304 272 160
WIRE 272 160 304 160
WIRE 96 160 48 160
WIRE 48 160 48 80
WIRE 304 160 304 80
WIRE 304 80 224 80
WIRE 96 304 96 352
WIRE 96 352 224 352
WIRE 224 352 224 304
WIRE 224 160 272 160
WIRE 272 160 272 96
WIRE 272 96 352 96
WIRE 352 96 352 304
WIRE 352 304 304 304
WIRE 304 304 304 160
FLAG 48 304 0
FLAG 352 304 0
SYMBOL voltage 48 64 R0
WINDOW 3 24 120 Left 2
SYMATTR InstName V1
SYMATTR Value 403
SYMBOL cap 208 208 R0
SYMATTR InstName C1
SYMATTR Value 20u
SYMBOL nmos 96 208 R270
WINDOW 0 32 80 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName M1
SYMATTR Value IPW60R045CPA
SYMATTR Value2 IPW60R045CPA
SYMATTR SpiceLine Rg=0
SYMBOL res 272 80 R0
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL res 304 144 R270
SYMATTR InstName R2
SYMATTR Value 3.3k
SYMBOL cap 96 64 R270
SYMATTR InstName C2
SYMATTR Value 220n
.END