1032 lines
66 KiB
Plaintext
1032 lines
66 KiB
Plaintext
ARM GAS /tmp/cc4CvqUD.s page 1
|
||
|
||
|
||
1 .cpu cortex-m0
|
||
2 .arch armv6s-m
|
||
3 .fpu softvfp
|
||
4 .eabi_attribute 20, 1
|
||
5 .eabi_attribute 21, 1
|
||
6 .eabi_attribute 23, 3
|
||
7 .eabi_attribute 24, 1
|
||
8 .eabi_attribute 25, 1
|
||
9 .eabi_attribute 26, 1
|
||
10 .eabi_attribute 30, 1
|
||
11 .eabi_attribute 34, 0
|
||
12 .eabi_attribute 18, 4
|
||
13 .file "stm32f0xx_hal_pwr.c"
|
||
14 .text
|
||
15 .Ltext0:
|
||
16 .cfi_sections .debug_frame
|
||
17 .file 1 "Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c"
|
||
18 .section .text.HAL_PWR_DeInit,"ax",%progbits
|
||
19 .align 1
|
||
20 .global HAL_PWR_DeInit
|
||
21 .syntax unified
|
||
22 .code 16
|
||
23 .thumb_func
|
||
25 HAL_PWR_DeInit:
|
||
26 .LFB40:
|
||
1:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /**
|
||
2:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** ******************************************************************************
|
||
3:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @file stm32f0xx_hal_pwr.c
|
||
4:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @author MCD Application Team
|
||
5:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @brief PWR HAL module driver.
|
||
6:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * This file provides firmware functions to manage the following
|
||
7:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * functionalities of the Power Controller (PWR) peripheral:
|
||
8:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * + Initialization/de-initialization function
|
||
9:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * + Peripheral Control function
|
||
10:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** *
|
||
11:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** ******************************************************************************
|
||
12:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @attention
|
||
13:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** *
|
||
14:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * Copyright (c) 2016 STMicroelectronics.
|
||
15:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * All rights reserved.
|
||
16:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** *
|
||
17:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * This software is licensed under terms that can be found in the LICENSE file
|
||
18:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * in the root directory of this software component.
|
||
19:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
|
||
20:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** *
|
||
21:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** ******************************************************************************
|
||
22:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** */
|
||
23:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
24:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/
|
||
25:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** #include "stm32f0xx_hal.h"
|
||
26:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
27:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /** @addtogroup STM32F0xx_HAL_Driver
|
||
28:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @{
|
||
29:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** */
|
||
30:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
31:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /** @defgroup PWR PWR
|
||
32:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @brief PWR HAL module driver
|
||
ARM GAS /tmp/cc4CvqUD.s page 2
|
||
|
||
|
||
33:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @{
|
||
34:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** */
|
||
35:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
36:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED
|
||
37:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
38:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/
|
||
39:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/
|
||
40:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/
|
||
41:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/
|
||
42:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/
|
||
43:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Private functions ---------------------------------------------------------*/
|
||
44:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
45:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions
|
||
46:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @{
|
||
47:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** */
|
||
48:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
49:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||
50:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @brief Initialization and de-initialization functions
|
||
51:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** *
|
||
52:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** @verbatim
|
||
53:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** ===============================================================================
|
||
54:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** ##### Initialization and de-initialization functions #####
|
||
55:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** ===============================================================================
|
||
56:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** [..]
|
||
57:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** After reset, the backup domain (RTC registers, RTC backup data
|
||
58:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** registers) is protected against possible unwanted
|
||
59:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** write accesses.
|
||
60:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** To enable access to the RTC Domain and RTC registers, proceed as follows:
|
||
61:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (+) Enable the Power Controller (PWR) APB1 interface clock using the
|
||
62:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** __HAL_RCC_PWR_CLK_ENABLE() macro.
|
||
63:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
|
||
64:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
65:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** @endverbatim
|
||
66:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @{
|
||
67:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** */
|
||
68:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
69:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /**
|
||
70:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @brief Deinitializes the PWR peripheral registers to their default reset values.
|
||
71:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @retval None
|
||
72:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** */
|
||
73:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** void HAL_PWR_DeInit(void)
|
||
74:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** {
|
||
27 .loc 1 74 1 view -0
|
||
28 .cfi_startproc
|
||
29 @ args = 0, pretend = 0, frame = 0
|
||
30 @ frame_needed = 0, uses_anonymous_args = 0
|
||
31 @ link register save eliminated.
|
||
75:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** __HAL_RCC_PWR_FORCE_RESET();
|
||
32 .loc 1 75 3 view .LVU1
|
||
33 0000 054B ldr r3, .L2
|
||
34 0002 1969 ldr r1, [r3, #16]
|
||
35 0004 8022 movs r2, #128
|
||
36 0006 5205 lsls r2, r2, #21
|
||
37 0008 0A43 orrs r2, r1
|
||
38 000a 1A61 str r2, [r3, #16]
|
||
76:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET();
|
||
39 .loc 1 76 3 view .LVU2
|
||
ARM GAS /tmp/cc4CvqUD.s page 3
|
||
|
||
|
||
40 000c 1A69 ldr r2, [r3, #16]
|
||
41 000e 0349 ldr r1, .L2+4
|
||
42 0010 0A40 ands r2, r1
|
||
43 0012 1A61 str r2, [r3, #16]
|
||
77:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** }
|
||
44 .loc 1 77 1 is_stmt 0 view .LVU3
|
||
45 @ sp needed
|
||
46 0014 7047 bx lr
|
||
47 .L3:
|
||
48 0016 C046 .align 2
|
||
49 .L2:
|
||
50 0018 00100240 .word 1073876992
|
||
51 001c FFFFFFEF .word -268435457
|
||
52 .cfi_endproc
|
||
53 .LFE40:
|
||
55 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits
|
||
56 .align 1
|
||
57 .global HAL_PWR_EnableBkUpAccess
|
||
58 .syntax unified
|
||
59 .code 16
|
||
60 .thumb_func
|
||
62 HAL_PWR_EnableBkUpAccess:
|
||
63 .LFB41:
|
||
78:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
79:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /**
|
||
80:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @brief Enables access to the backup domain (RTC registers, RTC
|
||
81:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * backup data registers when present).
|
||
82:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @note If the HSE divided by 32 is used as the RTC clock, the
|
||
83:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * Backup Domain Access should be kept enabled.
|
||
84:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @retval None
|
||
85:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** */
|
||
86:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void)
|
||
87:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** {
|
||
64 .loc 1 87 1 is_stmt 1 view -0
|
||
65 .cfi_startproc
|
||
66 @ args = 0, pretend = 0, frame = 0
|
||
67 @ frame_needed = 0, uses_anonymous_args = 0
|
||
68 @ link register save eliminated.
|
||
88:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** PWR->CR |= (uint32_t)PWR_CR_DBP;
|
||
69 .loc 1 88 3 view .LVU5
|
||
70 .loc 1 88 6 is_stmt 0 view .LVU6
|
||
71 0000 034A ldr r2, .L5
|
||
72 0002 1168 ldr r1, [r2]
|
||
73 .loc 1 88 11 view .LVU7
|
||
74 0004 8023 movs r3, #128
|
||
75 0006 5B00 lsls r3, r3, #1
|
||
76 0008 0B43 orrs r3, r1
|
||
77 000a 1360 str r3, [r2]
|
||
89:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** }
|
||
78 .loc 1 89 1 view .LVU8
|
||
79 @ sp needed
|
||
80 000c 7047 bx lr
|
||
81 .L6:
|
||
82 000e C046 .align 2
|
||
83 .L5:
|
||
84 0010 00700040 .word 1073770496
|
||
85 .cfi_endproc
|
||
ARM GAS /tmp/cc4CvqUD.s page 4
|
||
|
||
|
||
86 .LFE41:
|
||
88 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits
|
||
89 .align 1
|
||
90 .global HAL_PWR_DisableBkUpAccess
|
||
91 .syntax unified
|
||
92 .code 16
|
||
93 .thumb_func
|
||
95 HAL_PWR_DisableBkUpAccess:
|
||
96 .LFB42:
|
||
90:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
91:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /**
|
||
92:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @brief Disables access to the backup domain (RTC registers, RTC
|
||
93:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * backup data registers when present).
|
||
94:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @note If the HSE divided by 32 is used as the RTC clock, the
|
||
95:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * Backup Domain Access should be kept enabled.
|
||
96:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @retval None
|
||
97:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** */
|
||
98:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void)
|
||
99:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** {
|
||
97 .loc 1 99 1 is_stmt 1 view -0
|
||
98 .cfi_startproc
|
||
99 @ args = 0, pretend = 0, frame = 0
|
||
100 @ frame_needed = 0, uses_anonymous_args = 0
|
||
101 @ link register save eliminated.
|
||
100:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** PWR->CR &= ~((uint32_t)PWR_CR_DBP);
|
||
102 .loc 1 100 3 view .LVU10
|
||
103 .loc 1 100 6 is_stmt 0 view .LVU11
|
||
104 0000 024A ldr r2, .L8
|
||
105 0002 1368 ldr r3, [r2]
|
||
106 .loc 1 100 11 view .LVU12
|
||
107 0004 0249 ldr r1, .L8+4
|
||
108 0006 0B40 ands r3, r1
|
||
109 0008 1360 str r3, [r2]
|
||
101:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** }
|
||
110 .loc 1 101 1 view .LVU13
|
||
111 @ sp needed
|
||
112 000a 7047 bx lr
|
||
113 .L9:
|
||
114 .align 2
|
||
115 .L8:
|
||
116 000c 00700040 .word 1073770496
|
||
117 0010 FFFEFFFF .word -257
|
||
118 .cfi_endproc
|
||
119 .LFE42:
|
||
121 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits
|
||
122 .align 1
|
||
123 .global HAL_PWR_EnableWakeUpPin
|
||
124 .syntax unified
|
||
125 .code 16
|
||
126 .thumb_func
|
||
128 HAL_PWR_EnableWakeUpPin:
|
||
129 .LVL0:
|
||
130 .LFB43:
|
||
102:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
103:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /**
|
||
104:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @}
|
||
105:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** */
|
||
ARM GAS /tmp/cc4CvqUD.s page 5
|
||
|
||
|
||
106:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
107:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||
108:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @brief Low Power modes configuration functions
|
||
109:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** *
|
||
110:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** @verbatim
|
||
111:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
112:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** ===============================================================================
|
||
113:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** ##### Peripheral Control functions #####
|
||
114:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** ===============================================================================
|
||
115:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
116:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** *** WakeUp pin configuration ***
|
||
117:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** ================================
|
||
118:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** [..]
|
||
119:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
|
||
120:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** forced in input pull down configuration and is active on rising edges.
|
||
121:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (+) There are two WakeUp pins, and up to eight Wakeup pins on STM32F07x & STM32F09x devices.
|
||
122:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++)WakeUp Pin 1 on PA.00.
|
||
123:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++)WakeUp Pin 2 on PC.13.
|
||
124:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++)WakeUp Pin 3 on PE.06.(STM32F07x/STM32F09x)
|
||
125:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++)WakeUp Pin 4 on PA.02.(STM32F07x/STM32F09x)
|
||
126:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++)WakeUp Pin 5 on PC.05.(STM32F07x/STM32F09x)
|
||
127:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++)WakeUp Pin 6 on PB.05.(STM32F07x/STM32F09x)
|
||
128:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++)WakeUp Pin 7 on PB.15.(STM32F07x/STM32F09x)
|
||
129:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++)WakeUp Pin 8 on PF.02.(STM32F07x/STM32F09x)
|
||
130:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
131:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** *** Low Power modes configuration ***
|
||
132:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** =====================================
|
||
133:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** [..]
|
||
134:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** The devices feature 3 low-power modes:
|
||
135:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running.
|
||
136:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (+) Stop mode: all clocks are stopped, regulator running, regulator
|
||
137:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** in low power mode
|
||
138:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (+) Standby mode: 1.2V domain powered off (mode not available on STM32F0x8 devices).
|
||
139:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
140:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** *** Sleep mode ***
|
||
141:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** ==================
|
||
142:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** [..]
|
||
143:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (+) Entry:
|
||
144:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_S
|
||
145:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** functions with
|
||
146:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||
147:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||
148:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
149:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (+) Exit:
|
||
150:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
|
||
151:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** controller (NVIC) can wake up the device from Sleep mode.
|
||
152:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
153:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** *** Stop mode ***
|
||
154:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** =================
|
||
155:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** [..]
|
||
156:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
|
||
157:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** and the HSE RC oscillators are disabled. Internal SRAM and register contents
|
||
158:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** are preserved.
|
||
159:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** The voltage regulator can be configured either in normal or low-power mode.
|
||
160:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** To minimize the consumption.
|
||
161:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
162:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (+) Entry:
|
||
ARM GAS /tmp/cc4CvqUD.s page 6
|
||
|
||
|
||
163:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPEN
|
||
164:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** function with:
|
||
165:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++) Main regulator ON.
|
||
166:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++) Low Power regulator ON.
|
||
167:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction
|
||
168:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
|
||
169:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (+) Exit:
|
||
170:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
|
||
171:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
|
||
172:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** when programmed in wakeup mode (the peripheral must be
|
||
173:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** programmed in wakeup mode and the corresponding interrupt vector
|
||
174:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** must be enabled in the NVIC)
|
||
175:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
176:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** *** Standby mode ***
|
||
177:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** ====================
|
||
178:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** [..]
|
||
179:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** The Standby mode allows to achieve the lowest power consumption. It is based
|
||
180:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** on the Cortex-M0 deep sleep mode, with the voltage regulator disabled.
|
||
181:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
|
||
182:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** the HSE oscillator are also switched off. SRAM and register contents are lost
|
||
183:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** except for the RTC registers, RTC backup registers and Standby circuitry.
|
||
184:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** The voltage regulator is OFF.
|
||
185:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
186:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (+) Entry:
|
||
187:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
|
||
188:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (+) Exit:
|
||
189:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++) WKUP pin rising edge, RTC alarm (Alarm A), RTC wakeup,
|
||
190:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
|
||
191:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
192:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** *** Auto-wakeup (AWU) from low-power mode ***
|
||
193:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** =============================================
|
||
194:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** [..]
|
||
195:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
|
||
196:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** Wakeup event, a tamper event, a time-stamp event, or a comparator event,
|
||
197:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** without depending on an external interrupt (Auto-wakeup mode).
|
||
198:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
199:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
|
||
200:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
201:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
|
||
202:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
|
||
203:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
204:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
|
||
205:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** is necessary to configure the RTC to detect the tamper or time stamp event using the
|
||
206:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
|
||
207:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
208:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
|
||
209:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT()
|
||
210:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
211:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (+) Comparator auto-wakeup (AWU) from the Stop mode
|
||
212:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
213:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
|
||
214:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for c
|
||
215:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** to be sensitive to to the selected edges (falling, rising or falling
|
||
216:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** and rising) (Interrupt or Event modes) using the EXTI_Init() function.
|
||
217:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** (+++) Configure the comparator to generate the event.
|
||
218:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** @endverbatim
|
||
219:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @{
|
||
ARM GAS /tmp/cc4CvqUD.s page 7
|
||
|
||
|
||
220:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** */
|
||
221:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
222:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /**
|
||
223:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @brief Enables the WakeUp PINx functionality.
|
||
224:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
|
||
225:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * This parameter can be value of :
|
||
226:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @ref PWREx_WakeUp_Pins
|
||
227:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @retval None
|
||
228:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** */
|
||
229:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
|
||
230:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** {
|
||
131 .loc 1 230 1 is_stmt 1 view -0
|
||
132 .cfi_startproc
|
||
133 @ args = 0, pretend = 0, frame = 0
|
||
134 @ frame_needed = 0, uses_anonymous_args = 0
|
||
135 @ link register save eliminated.
|
||
231:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Check the parameters */
|
||
232:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||
136 .loc 1 232 3 view .LVU15
|
||
233:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Enable the EWUPx pin */
|
||
234:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** SET_BIT(PWR->CSR, WakeUpPinx);
|
||
137 .loc 1 234 3 view .LVU16
|
||
138 0000 024A ldr r2, .L11
|
||
139 0002 5368 ldr r3, [r2, #4]
|
||
140 0004 0343 orrs r3, r0
|
||
141 0006 5360 str r3, [r2, #4]
|
||
235:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** }
|
||
142 .loc 1 235 1 is_stmt 0 view .LVU17
|
||
143 @ sp needed
|
||
144 0008 7047 bx lr
|
||
145 .L12:
|
||
146 000a C046 .align 2
|
||
147 .L11:
|
||
148 000c 00700040 .word 1073770496
|
||
149 .cfi_endproc
|
||
150 .LFE43:
|
||
152 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits
|
||
153 .align 1
|
||
154 .global HAL_PWR_DisableWakeUpPin
|
||
155 .syntax unified
|
||
156 .code 16
|
||
157 .thumb_func
|
||
159 HAL_PWR_DisableWakeUpPin:
|
||
160 .LVL1:
|
||
161 .LFB44:
|
||
236:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
237:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /**
|
||
238:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @brief Disables the WakeUp PINx functionality.
|
||
239:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
|
||
240:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * This parameter can be values of :
|
||
241:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @ref PWREx_WakeUp_Pins
|
||
242:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @retval None
|
||
243:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** */
|
||
244:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
|
||
245:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** {
|
||
162 .loc 1 245 1 is_stmt 1 view -0
|
||
163 .cfi_startproc
|
||
ARM GAS /tmp/cc4CvqUD.s page 8
|
||
|
||
|
||
164 @ args = 0, pretend = 0, frame = 0
|
||
165 @ frame_needed = 0, uses_anonymous_args = 0
|
||
166 @ link register save eliminated.
|
||
246:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Check the parameters */
|
||
247:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||
167 .loc 1 247 3 view .LVU19
|
||
248:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Disable the EWUPx pin */
|
||
249:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** CLEAR_BIT(PWR->CSR, WakeUpPinx);
|
||
168 .loc 1 249 3 view .LVU20
|
||
169 0000 024A ldr r2, .L14
|
||
170 0002 5368 ldr r3, [r2, #4]
|
||
171 0004 8343 bics r3, r0
|
||
172 0006 5360 str r3, [r2, #4]
|
||
250:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** }
|
||
173 .loc 1 250 1 is_stmt 0 view .LVU21
|
||
174 @ sp needed
|
||
175 0008 7047 bx lr
|
||
176 .L15:
|
||
177 000a C046 .align 2
|
||
178 .L14:
|
||
179 000c 00700040 .word 1073770496
|
||
180 .cfi_endproc
|
||
181 .LFE44:
|
||
183 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits
|
||
184 .align 1
|
||
185 .global HAL_PWR_EnterSLEEPMode
|
||
186 .syntax unified
|
||
187 .code 16
|
||
188 .thumb_func
|
||
190 HAL_PWR_EnterSLEEPMode:
|
||
191 .LVL2:
|
||
192 .LFB45:
|
||
251:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
252:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /**
|
||
253:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @brief Enters Sleep mode.
|
||
254:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
|
||
255:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in SLEEP mode.
|
||
256:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * On STM32F0 devices, this parameter is a dummy value and it is ignored
|
||
257:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * as regulator can't be modified in this mode. Parameter is kept for platform
|
||
258:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * compatibility.
|
||
259:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
|
||
260:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * When WFI entry is used, tick interrupt have to be disabled if not desired as
|
||
261:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * the interrupt wake up source.
|
||
262:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * This parameter can be one of the following values:
|
||
263:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||
264:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||
265:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @retval None
|
||
266:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** */
|
||
267:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
|
||
268:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** {
|
||
193 .loc 1 268 1 is_stmt 1 view -0
|
||
194 .cfi_startproc
|
||
195 @ args = 0, pretend = 0, frame = 0
|
||
196 @ frame_needed = 0, uses_anonymous_args = 0
|
||
197 @ link register save eliminated.
|
||
269:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Check the parameters */
|
||
270:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator));
|
||
ARM GAS /tmp/cc4CvqUD.s page 9
|
||
|
||
|
||
198 .loc 1 270 3 view .LVU23
|
||
271:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
|
||
199 .loc 1 271 3 view .LVU24
|
||
272:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
273:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||
274:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||
200 .loc 1 274 3 view .LVU25
|
||
201 .loc 1 274 6 is_stmt 0 view .LVU26
|
||
202 0000 064A ldr r2, .L20
|
||
203 0002 1369 ldr r3, [r2, #16]
|
||
204 .loc 1 274 12 view .LVU27
|
||
205 0004 0420 movs r0, #4
|
||
206 .LVL3:
|
||
207 .loc 1 274 12 view .LVU28
|
||
208 0006 8343 bics r3, r0
|
||
209 0008 1361 str r3, [r2, #16]
|
||
275:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
276:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Select SLEEP mode entry -------------------------------------------------*/
|
||
277:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
||
210 .loc 1 277 3 is_stmt 1 view .LVU29
|
||
211 .loc 1 277 5 is_stmt 0 view .LVU30
|
||
212 000a 0129 cmp r1, #1
|
||
213 000c 03D0 beq .L19
|
||
278:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** {
|
||
279:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Request Wait For Interrupt */
|
||
280:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** __WFI();
|
||
281:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** }
|
||
282:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** else
|
||
283:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** {
|
||
284:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Request Wait For Event */
|
||
285:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** __SEV();
|
||
214 .loc 1 285 5 is_stmt 1 view .LVU31
|
||
215 .syntax divided
|
||
216 @ 285 "Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c" 1
|
||
217 000e 40BF sev
|
||
218 @ 0 "" 2
|
||
286:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** __WFE();
|
||
219 .loc 1 286 5 view .LVU32
|
||
220 @ 286 "Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c" 1
|
||
221 0010 20BF wfe
|
||
222 @ 0 "" 2
|
||
287:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** __WFE();
|
||
223 .loc 1 287 5 view .LVU33
|
||
224 @ 287 "Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c" 1
|
||
225 0012 20BF wfe
|
||
226 @ 0 "" 2
|
||
227 .thumb
|
||
228 .syntax unified
|
||
229 .L16:
|
||
288:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** }
|
||
289:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** }
|
||
230 .loc 1 289 1 is_stmt 0 view .LVU34
|
||
231 @ sp needed
|
||
232 0014 7047 bx lr
|
||
233 .L19:
|
||
280:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** }
|
||
234 .loc 1 280 5 is_stmt 1 view .LVU35
|
||
ARM GAS /tmp/cc4CvqUD.s page 10
|
||
|
||
|
||
235 .syntax divided
|
||
236 @ 280 "Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c" 1
|
||
237 0016 30BF wfi
|
||
238 @ 0 "" 2
|
||
239 .thumb
|
||
240 .syntax unified
|
||
241 0018 FCE7 b .L16
|
||
242 .L21:
|
||
243 001a C046 .align 2
|
||
244 .L20:
|
||
245 001c 00ED00E0 .word -536810240
|
||
246 .cfi_endproc
|
||
247 .LFE45:
|
||
249 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits
|
||
250 .align 1
|
||
251 .global HAL_PWR_EnterSTOPMode
|
||
252 .syntax unified
|
||
253 .code 16
|
||
254 .thumb_func
|
||
256 HAL_PWR_EnterSTOPMode:
|
||
257 .LVL4:
|
||
258 .LFB46:
|
||
290:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
291:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /**
|
||
292:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @brief Enters STOP mode.
|
||
293:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
||
294:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
|
||
295:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * the HSI RC oscillator is selected as system clock.
|
||
296:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @note When the voltage regulator operates in low power mode, an additional
|
||
297:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * startup delay is incurred when waking up from Stop mode.
|
||
298:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * By keeping the internal regulator ON during Stop mode, the consumption
|
||
299:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * is higher although the startup time is reduced.
|
||
300:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in STOP mode.
|
||
301:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * This parameter can be one of the following values:
|
||
302:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
|
||
303:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
|
||
304:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
|
||
305:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * This parameter can be one of the following values:
|
||
306:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
|
||
307:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
|
||
308:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @retval None
|
||
309:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** */
|
||
310:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
||
311:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** {
|
||
259 .loc 1 311 1 view -0
|
||
260 .cfi_startproc
|
||
261 @ args = 0, pretend = 0, frame = 0
|
||
262 @ frame_needed = 0, uses_anonymous_args = 0
|
||
263 .loc 1 311 1 is_stmt 0 view .LVU37
|
||
264 0000 10B5 push {r4, lr}
|
||
265 .cfi_def_cfa_offset 8
|
||
266 .cfi_offset 4, -8
|
||
267 .cfi_offset 14, -4
|
||
312:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** uint32_t tmpreg = 0;
|
||
268 .loc 1 312 3 is_stmt 1 view .LVU38
|
||
269 .LVL5:
|
||
313:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
ARM GAS /tmp/cc4CvqUD.s page 11
|
||
|
||
|
||
314:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Check the parameters */
|
||
315:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator));
|
||
270 .loc 1 315 3 view .LVU39
|
||
316:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
||
271 .loc 1 316 3 view .LVU40
|
||
317:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
318:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Select the regulator state in STOP mode ---------------------------------*/
|
||
319:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** tmpreg = PWR->CR;
|
||
272 .loc 1 319 3 view .LVU41
|
||
273 .loc 1 319 10 is_stmt 0 view .LVU42
|
||
274 0002 0C4A ldr r2, .L26
|
||
275 0004 1368 ldr r3, [r2]
|
||
276 .LVL6:
|
||
320:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
321:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Clear PDDS and LPDS bits */
|
||
322:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
|
||
277 .loc 1 322 3 is_stmt 1 view .LVU43
|
||
278 .loc 1 322 10 is_stmt 0 view .LVU44
|
||
279 0006 0324 movs r4, #3
|
||
280 0008 A343 bics r3, r4
|
||
281 .LVL7:
|
||
323:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
324:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Set LPDS bit according to Regulator value */
|
||
325:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** tmpreg |= Regulator;
|
||
282 .loc 1 325 3 is_stmt 1 view .LVU45
|
||
283 .loc 1 325 10 is_stmt 0 view .LVU46
|
||
284 000a 0343 orrs r3, r0
|
||
285 .LVL8:
|
||
326:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
327:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Store the new value */
|
||
328:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** PWR->CR = tmpreg;
|
||
286 .loc 1 328 3 is_stmt 1 view .LVU47
|
||
287 .loc 1 328 11 is_stmt 0 view .LVU48
|
||
288 000c 1360 str r3, [r2]
|
||
329:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
330:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
331:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||
289 .loc 1 331 3 is_stmt 1 view .LVU49
|
||
290 .loc 1 331 6 is_stmt 0 view .LVU50
|
||
291 000e 0A4A ldr r2, .L26+4
|
||
292 0010 1369 ldr r3, [r2, #16]
|
||
293 .LVL9:
|
||
294 .loc 1 331 12 view .LVU51
|
||
295 0012 0420 movs r0, #4
|
||
296 .LVL10:
|
||
297 .loc 1 331 12 view .LVU52
|
||
298 0014 0343 orrs r3, r0
|
||
299 0016 1361 str r3, [r2, #16]
|
||
300 .LVL11:
|
||
332:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
333:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Select STOP mode entry --------------------------------------------------*/
|
||
334:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** if(STOPEntry == PWR_STOPENTRY_WFI)
|
||
301 .loc 1 334 3 is_stmt 1 view .LVU53
|
||
302 .loc 1 334 5 is_stmt 0 view .LVU54
|
||
303 0018 0129 cmp r1, #1
|
||
304 001a 08D0 beq .L25
|
||
335:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** {
|
||
ARM GAS /tmp/cc4CvqUD.s page 12
|
||
|
||
|
||
336:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Request Wait For Interrupt */
|
||
337:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** __WFI();
|
||
338:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** }
|
||
339:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** else
|
||
340:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** {
|
||
341:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Request Wait For Event */
|
||
342:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** __SEV();
|
||
305 .loc 1 342 5 is_stmt 1 view .LVU55
|
||
306 .syntax divided
|
||
307 @ 342 "Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c" 1
|
||
308 001c 40BF sev
|
||
309 @ 0 "" 2
|
||
343:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** __WFE();
|
||
310 .loc 1 343 5 view .LVU56
|
||
311 @ 343 "Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c" 1
|
||
312 001e 20BF wfe
|
||
313 @ 0 "" 2
|
||
344:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** __WFE();
|
||
314 .loc 1 344 5 view .LVU57
|
||
315 @ 344 "Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c" 1
|
||
316 0020 20BF wfe
|
||
317 @ 0 "" 2
|
||
318 .thumb
|
||
319 .syntax unified
|
||
320 .L24:
|
||
345:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** }
|
||
346:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
347:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||
348:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||
321 .loc 1 348 3 view .LVU58
|
||
322 .loc 1 348 6 is_stmt 0 view .LVU59
|
||
323 0022 054A ldr r2, .L26+4
|
||
324 0024 1369 ldr r3, [r2, #16]
|
||
325 .loc 1 348 12 view .LVU60
|
||
326 0026 0421 movs r1, #4
|
||
327 .LVL12:
|
||
328 .loc 1 348 12 view .LVU61
|
||
329 0028 8B43 bics r3, r1
|
||
330 002a 1361 str r3, [r2, #16]
|
||
349:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** }
|
||
331 .loc 1 349 1 view .LVU62
|
||
332 @ sp needed
|
||
333 .loc 1 349 1 view .LVU63
|
||
334 002c 10BD pop {r4, pc}
|
||
335 .LVL13:
|
||
336 .L25:
|
||
337:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** }
|
||
337 .loc 1 337 5 is_stmt 1 view .LVU64
|
||
338 .syntax divided
|
||
339 @ 337 "Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c" 1
|
||
340 002e 30BF wfi
|
||
341 @ 0 "" 2
|
||
342 .thumb
|
||
343 .syntax unified
|
||
344 0030 F7E7 b .L24
|
||
345 .L27:
|
||
346 0032 C046 .align 2
|
||
ARM GAS /tmp/cc4CvqUD.s page 13
|
||
|
||
|
||
347 .L26:
|
||
348 0034 00700040 .word 1073770496
|
||
349 0038 00ED00E0 .word -536810240
|
||
350 .cfi_endproc
|
||
351 .LFE46:
|
||
353 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits
|
||
354 .align 1
|
||
355 .global HAL_PWR_EnterSTANDBYMode
|
||
356 .syntax unified
|
||
357 .code 16
|
||
358 .thumb_func
|
||
360 HAL_PWR_EnterSTANDBYMode:
|
||
361 .LFB47:
|
||
350:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
351:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /**
|
||
352:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @brief Enters STANDBY mode.
|
||
353:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @note In Standby mode, all I/O pins are high impedance except for:
|
||
354:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * - Reset pad (still available)
|
||
355:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * - RTC alternate function pins if configured for tamper, time-stamp, RTC
|
||
356:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * Alarm out, or RTC clock calibration out.
|
||
357:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * - WKUP pins if enabled.
|
||
358:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * STM32F0x8 devices, the Stop mode is available, but it is
|
||
359:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * aningless to distinguish between voltage regulator in Low power
|
||
360:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * mode and voltage regulator in Run mode because the regulator
|
||
361:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * not used and the core is supplied directly from an external source.
|
||
362:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * Consequently, the Standby mode is not available on those devices.
|
||
363:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @retval None
|
||
364:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** */
|
||
365:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void)
|
||
366:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** {
|
||
362 .loc 1 366 1 view -0
|
||
363 .cfi_startproc
|
||
364 @ args = 0, pretend = 0, frame = 0
|
||
365 @ frame_needed = 0, uses_anonymous_args = 0
|
||
366 @ link register save eliminated.
|
||
367:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Select STANDBY mode */
|
||
368:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** PWR->CR |= (uint32_t)PWR_CR_PDDS;
|
||
367 .loc 1 368 3 view .LVU66
|
||
368 .loc 1 368 6 is_stmt 0 view .LVU67
|
||
369 0000 054A ldr r2, .L29
|
||
370 0002 1368 ldr r3, [r2]
|
||
371 .loc 1 368 11 view .LVU68
|
||
372 0004 0221 movs r1, #2
|
||
373 0006 0B43 orrs r3, r1
|
||
374 0008 1360 str r3, [r2]
|
||
369:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
370:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
371:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||
375 .loc 1 371 3 is_stmt 1 view .LVU69
|
||
376 .loc 1 371 6 is_stmt 0 view .LVU70
|
||
377 000a 044A ldr r2, .L29+4
|
||
378 000c 1369 ldr r3, [r2, #16]
|
||
379 .loc 1 371 12 view .LVU71
|
||
380 000e 0231 adds r1, r1, #2
|
||
381 0010 0B43 orrs r3, r1
|
||
382 0012 1361 str r3, [r2, #16]
|
||
372:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
ARM GAS /tmp/cc4CvqUD.s page 14
|
||
|
||
|
||
373:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */
|
||
374:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** #if defined ( __CC_ARM)
|
||
375:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** __force_stores();
|
||
376:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** #endif
|
||
377:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Request Wait For Interrupt */
|
||
378:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** __WFI();
|
||
383 .loc 1 378 3 is_stmt 1 view .LVU72
|
||
384 .syntax divided
|
||
385 @ 378 "Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c" 1
|
||
386 0014 30BF wfi
|
||
387 @ 0 "" 2
|
||
379:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** }
|
||
388 .loc 1 379 1 is_stmt 0 view .LVU73
|
||
389 .thumb
|
||
390 .syntax unified
|
||
391 @ sp needed
|
||
392 0016 7047 bx lr
|
||
393 .L30:
|
||
394 .align 2
|
||
395 .L29:
|
||
396 0018 00700040 .word 1073770496
|
||
397 001c 00ED00E0 .word -536810240
|
||
398 .cfi_endproc
|
||
399 .LFE47:
|
||
401 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits
|
||
402 .align 1
|
||
403 .global HAL_PWR_EnableSleepOnExit
|
||
404 .syntax unified
|
||
405 .code 16
|
||
406 .thumb_func
|
||
408 HAL_PWR_EnableSleepOnExit:
|
||
409 .LFB48:
|
||
380:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
381:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /**
|
||
382:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
|
||
383:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||
384:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over.
|
||
385:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * Setting this bit is useful when the processor is expected to run only on
|
||
386:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * interruptions handling.
|
||
387:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @retval None
|
||
388:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** */
|
||
389:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void)
|
||
390:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** {
|
||
410 .loc 1 390 1 is_stmt 1 view -0
|
||
411 .cfi_startproc
|
||
412 @ args = 0, pretend = 0, frame = 0
|
||
413 @ frame_needed = 0, uses_anonymous_args = 0
|
||
414 @ link register save eliminated.
|
||
391:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||
392:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||
415 .loc 1 392 3 view .LVU75
|
||
416 0000 024A ldr r2, .L32
|
||
417 0002 1369 ldr r3, [r2, #16]
|
||
418 0004 0221 movs r1, #2
|
||
419 0006 0B43 orrs r3, r1
|
||
420 0008 1361 str r3, [r2, #16]
|
||
393:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** }
|
||
ARM GAS /tmp/cc4CvqUD.s page 15
|
||
|
||
|
||
421 .loc 1 393 1 is_stmt 0 view .LVU76
|
||
422 @ sp needed
|
||
423 000a 7047 bx lr
|
||
424 .L33:
|
||
425 .align 2
|
||
426 .L32:
|
||
427 000c 00ED00E0 .word -536810240
|
||
428 .cfi_endproc
|
||
429 .LFE48:
|
||
431 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits
|
||
432 .align 1
|
||
433 .global HAL_PWR_DisableSleepOnExit
|
||
434 .syntax unified
|
||
435 .code 16
|
||
436 .thumb_func
|
||
438 HAL_PWR_DisableSleepOnExit:
|
||
439 .LFB49:
|
||
394:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
395:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
396:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /**
|
||
397:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
|
||
398:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||
399:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over.
|
||
400:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @retval None
|
||
401:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** */
|
||
402:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void)
|
||
403:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** {
|
||
440 .loc 1 403 1 is_stmt 1 view -0
|
||
441 .cfi_startproc
|
||
442 @ args = 0, pretend = 0, frame = 0
|
||
443 @ frame_needed = 0, uses_anonymous_args = 0
|
||
444 @ link register save eliminated.
|
||
404:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||
405:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||
445 .loc 1 405 3 view .LVU78
|
||
446 0000 024A ldr r2, .L35
|
||
447 0002 1369 ldr r3, [r2, #16]
|
||
448 0004 0221 movs r1, #2
|
||
449 0006 8B43 bics r3, r1
|
||
450 0008 1361 str r3, [r2, #16]
|
||
406:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** }
|
||
451 .loc 1 406 1 is_stmt 0 view .LVU79
|
||
452 @ sp needed
|
||
453 000a 7047 bx lr
|
||
454 .L36:
|
||
455 .align 2
|
||
456 .L35:
|
||
457 000c 00ED00E0 .word -536810240
|
||
458 .cfi_endproc
|
||
459 .LFE49:
|
||
461 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits
|
||
462 .align 1
|
||
463 .global HAL_PWR_EnableSEVOnPend
|
||
464 .syntax unified
|
||
465 .code 16
|
||
466 .thumb_func
|
||
468 HAL_PWR_EnableSEVOnPend:
|
||
ARM GAS /tmp/cc4CvqUD.s page 16
|
||
|
||
|
||
469 .LFB50:
|
||
407:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
408:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
409:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
410:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /**
|
||
411:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @brief Enables CORTEX M4 SEVONPEND bit.
|
||
412:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
|
||
413:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended.
|
||
414:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @retval None
|
||
415:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** */
|
||
416:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void)
|
||
417:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** {
|
||
470 .loc 1 417 1 is_stmt 1 view -0
|
||
471 .cfi_startproc
|
||
472 @ args = 0, pretend = 0, frame = 0
|
||
473 @ frame_needed = 0, uses_anonymous_args = 0
|
||
474 @ link register save eliminated.
|
||
418:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex System Control Register */
|
||
419:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||
475 .loc 1 419 3 view .LVU81
|
||
476 0000 024A ldr r2, .L38
|
||
477 0002 1369 ldr r3, [r2, #16]
|
||
478 0004 1021 movs r1, #16
|
||
479 0006 0B43 orrs r3, r1
|
||
480 0008 1361 str r3, [r2, #16]
|
||
420:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** }
|
||
481 .loc 1 420 1 is_stmt 0 view .LVU82
|
||
482 @ sp needed
|
||
483 000a 7047 bx lr
|
||
484 .L39:
|
||
485 .align 2
|
||
486 .L38:
|
||
487 000c 00ED00E0 .word -536810240
|
||
488 .cfi_endproc
|
||
489 .LFE50:
|
||
491 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits
|
||
492 .align 1
|
||
493 .global HAL_PWR_DisableSEVOnPend
|
||
494 .syntax unified
|
||
495 .code 16
|
||
496 .thumb_func
|
||
498 HAL_PWR_DisableSEVOnPend:
|
||
499 .LFB51:
|
||
421:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
422:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c ****
|
||
423:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /**
|
||
424:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @brief Disables CORTEX M4 SEVONPEND bit.
|
||
425:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
|
||
426:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended.
|
||
427:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** * @retval None
|
||
428:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** */
|
||
429:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void)
|
||
430:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** {
|
||
500 .loc 1 430 1 is_stmt 1 view -0
|
||
501 .cfi_startproc
|
||
502 @ args = 0, pretend = 0, frame = 0
|
||
503 @ frame_needed = 0, uses_anonymous_args = 0
|
||
ARM GAS /tmp/cc4CvqUD.s page 17
|
||
|
||
|
||
504 @ link register save eliminated.
|
||
431:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */
|
||
432:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||
505 .loc 1 432 3 view .LVU84
|
||
506 0000 024A ldr r2, .L41
|
||
507 0002 1369 ldr r3, [r2, #16]
|
||
508 0004 1021 movs r1, #16
|
||
509 0006 8B43 bics r3, r1
|
||
510 0008 1361 str r3, [r2, #16]
|
||
433:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c **** }
|
||
511 .loc 1 433 1 is_stmt 0 view .LVU85
|
||
512 @ sp needed
|
||
513 000a 7047 bx lr
|
||
514 .L42:
|
||
515 .align 2
|
||
516 .L41:
|
||
517 000c 00ED00E0 .word -536810240
|
||
518 .cfi_endproc
|
||
519 .LFE51:
|
||
521 .text
|
||
522 .Letext0:
|
||
523 .file 2 "/home/chiangni/.config/VSCodium/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/
|
||
524 .file 3 "/home/chiangni/.config/VSCodium/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/
|
||
525 .file 4 "Drivers/CMSIS/Include/core_cm0.h"
|
||
526 .file 5 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h"
|
||
ARM GAS /tmp/cc4CvqUD.s page 18
|
||
|
||
|
||
DEFINED SYMBOLS
|
||
*ABS*:00000000 stm32f0xx_hal_pwr.c
|
||
/tmp/cc4CvqUD.s:19 .text.HAL_PWR_DeInit:00000000 $t
|
||
/tmp/cc4CvqUD.s:25 .text.HAL_PWR_DeInit:00000000 HAL_PWR_DeInit
|
||
/tmp/cc4CvqUD.s:50 .text.HAL_PWR_DeInit:00000018 $d
|
||
/tmp/cc4CvqUD.s:56 .text.HAL_PWR_EnableBkUpAccess:00000000 $t
|
||
/tmp/cc4CvqUD.s:62 .text.HAL_PWR_EnableBkUpAccess:00000000 HAL_PWR_EnableBkUpAccess
|
||
/tmp/cc4CvqUD.s:84 .text.HAL_PWR_EnableBkUpAccess:00000010 $d
|
||
/tmp/cc4CvqUD.s:89 .text.HAL_PWR_DisableBkUpAccess:00000000 $t
|
||
/tmp/cc4CvqUD.s:95 .text.HAL_PWR_DisableBkUpAccess:00000000 HAL_PWR_DisableBkUpAccess
|
||
/tmp/cc4CvqUD.s:116 .text.HAL_PWR_DisableBkUpAccess:0000000c $d
|
||
/tmp/cc4CvqUD.s:122 .text.HAL_PWR_EnableWakeUpPin:00000000 $t
|
||
/tmp/cc4CvqUD.s:128 .text.HAL_PWR_EnableWakeUpPin:00000000 HAL_PWR_EnableWakeUpPin
|
||
/tmp/cc4CvqUD.s:148 .text.HAL_PWR_EnableWakeUpPin:0000000c $d
|
||
/tmp/cc4CvqUD.s:153 .text.HAL_PWR_DisableWakeUpPin:00000000 $t
|
||
/tmp/cc4CvqUD.s:159 .text.HAL_PWR_DisableWakeUpPin:00000000 HAL_PWR_DisableWakeUpPin
|
||
/tmp/cc4CvqUD.s:179 .text.HAL_PWR_DisableWakeUpPin:0000000c $d
|
||
/tmp/cc4CvqUD.s:184 .text.HAL_PWR_EnterSLEEPMode:00000000 $t
|
||
/tmp/cc4CvqUD.s:190 .text.HAL_PWR_EnterSLEEPMode:00000000 HAL_PWR_EnterSLEEPMode
|
||
/tmp/cc4CvqUD.s:245 .text.HAL_PWR_EnterSLEEPMode:0000001c $d
|
||
/tmp/cc4CvqUD.s:250 .text.HAL_PWR_EnterSTOPMode:00000000 $t
|
||
/tmp/cc4CvqUD.s:256 .text.HAL_PWR_EnterSTOPMode:00000000 HAL_PWR_EnterSTOPMode
|
||
/tmp/cc4CvqUD.s:348 .text.HAL_PWR_EnterSTOPMode:00000034 $d
|
||
/tmp/cc4CvqUD.s:354 .text.HAL_PWR_EnterSTANDBYMode:00000000 $t
|
||
/tmp/cc4CvqUD.s:360 .text.HAL_PWR_EnterSTANDBYMode:00000000 HAL_PWR_EnterSTANDBYMode
|
||
/tmp/cc4CvqUD.s:396 .text.HAL_PWR_EnterSTANDBYMode:00000018 $d
|
||
/tmp/cc4CvqUD.s:402 .text.HAL_PWR_EnableSleepOnExit:00000000 $t
|
||
/tmp/cc4CvqUD.s:408 .text.HAL_PWR_EnableSleepOnExit:00000000 HAL_PWR_EnableSleepOnExit
|
||
/tmp/cc4CvqUD.s:427 .text.HAL_PWR_EnableSleepOnExit:0000000c $d
|
||
/tmp/cc4CvqUD.s:432 .text.HAL_PWR_DisableSleepOnExit:00000000 $t
|
||
/tmp/cc4CvqUD.s:438 .text.HAL_PWR_DisableSleepOnExit:00000000 HAL_PWR_DisableSleepOnExit
|
||
/tmp/cc4CvqUD.s:457 .text.HAL_PWR_DisableSleepOnExit:0000000c $d
|
||
/tmp/cc4CvqUD.s:462 .text.HAL_PWR_EnableSEVOnPend:00000000 $t
|
||
/tmp/cc4CvqUD.s:468 .text.HAL_PWR_EnableSEVOnPend:00000000 HAL_PWR_EnableSEVOnPend
|
||
/tmp/cc4CvqUD.s:487 .text.HAL_PWR_EnableSEVOnPend:0000000c $d
|
||
/tmp/cc4CvqUD.s:492 .text.HAL_PWR_DisableSEVOnPend:00000000 $t
|
||
/tmp/cc4CvqUD.s:498 .text.HAL_PWR_DisableSEVOnPend:00000000 HAL_PWR_DisableSEVOnPend
|
||
/tmp/cc4CvqUD.s:517 .text.HAL_PWR_DisableSEVOnPend:0000000c $d
|
||
|
||
NO UNDEFINED SYMBOLS
|