ARM GAS /tmp/ccOqAezw.s page 1 1 .cpu cortex-m0 2 .arch armv6s-m 3 .fpu softvfp 4 .eabi_attribute 20, 1 5 .eabi_attribute 21, 1 6 .eabi_attribute 23, 3 7 .eabi_attribute 24, 1 8 .eabi_attribute 25, 1 9 .eabi_attribute 26, 1 10 .eabi_attribute 30, 1 11 .eabi_attribute 34, 0 12 .eabi_attribute 18, 4 13 .file "main.c" 14 .text 15 .Ltext0: 16 .cfi_sections .debug_frame 17 .file 1 "Core/Src/main.c" 18 .section .text.MX_GPIO_Init,"ax",%progbits 19 .align 1 20 .syntax unified 21 .code 16 22 .thumb_func 24 MX_GPIO_Init: 25 .LFB45: 1:Core/Src/main.c **** /* USER CODE BEGIN Header */ 2:Core/Src/main.c **** /** 3:Core/Src/main.c **** ****************************************************************************** 4:Core/Src/main.c **** * @file : main.c 5:Core/Src/main.c **** * @brief : Main program body 6:Core/Src/main.c **** ****************************************************************************** 7:Core/Src/main.c **** * @attention 8:Core/Src/main.c **** * 9:Core/Src/main.c **** * Copyright (c) 2024 STMicroelectronics. 10:Core/Src/main.c **** * All rights reserved. 11:Core/Src/main.c **** * 12:Core/Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file 13:Core/Src/main.c **** * in the root directory of this software component. 14:Core/Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Core/Src/main.c **** * 16:Core/Src/main.c **** ****************************************************************************** 17:Core/Src/main.c **** */ 18:Core/Src/main.c **** /* USER CODE END Header */ 19:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/ 20:Core/Src/main.c **** #include "main.h" 21:Core/Src/main.c **** 22:Core/Src/main.c **** /* Private includes ----------------------------------------------------------*/ 23:Core/Src/main.c **** /* USER CODE BEGIN Includes */ 24:Core/Src/main.c **** 25:Core/Src/main.c **** /* USER CODE END Includes */ 26:Core/Src/main.c **** 27:Core/Src/main.c **** /* Private typedef -----------------------------------------------------------*/ 28:Core/Src/main.c **** /* USER CODE BEGIN PTD */ 29:Core/Src/main.c **** 30:Core/Src/main.c **** /* USER CODE END PTD */ 31:Core/Src/main.c **** 32:Core/Src/main.c **** /* Private define ------------------------------------------------------------*/ 33:Core/Src/main.c **** /* USER CODE BEGIN PD */ ARM GAS /tmp/ccOqAezw.s page 2 34:Core/Src/main.c **** 35:Core/Src/main.c **** /* USER CODE END PD */ 36:Core/Src/main.c **** 37:Core/Src/main.c **** /* Private macro -------------------------------------------------------------*/ 38:Core/Src/main.c **** /* USER CODE BEGIN PM */ 39:Core/Src/main.c **** 40:Core/Src/main.c **** /* USER CODE END PM */ 41:Core/Src/main.c **** 42:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/ 43:Core/Src/main.c **** ADC_HandleTypeDef hadc; 44:Core/Src/main.c **** 45:Core/Src/main.c **** CAN_HandleTypeDef hcan; 46:Core/Src/main.c **** 47:Core/Src/main.c **** TIM_HandleTypeDef htim2; 48:Core/Src/main.c **** 49:Core/Src/main.c **** /* USER CODE BEGIN PV */ 50:Core/Src/main.c **** 51:Core/Src/main.c **** /* USER CODE END PV */ 52:Core/Src/main.c **** 53:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/ 54:Core/Src/main.c **** void SystemClock_Config(void); 55:Core/Src/main.c **** static void MX_GPIO_Init(void); 56:Core/Src/main.c **** static void MX_ADC_Init(void); 57:Core/Src/main.c **** static void MX_CAN_Init(void); 58:Core/Src/main.c **** static void MX_TIM2_Init(void); 59:Core/Src/main.c **** /* USER CODE BEGIN PFP */ 60:Core/Src/main.c **** 61:Core/Src/main.c **** /* USER CODE END PFP */ 62:Core/Src/main.c **** 63:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/ 64:Core/Src/main.c **** /* USER CODE BEGIN 0 */ 65:Core/Src/main.c **** 66:Core/Src/main.c **** /* USER CODE END 0 */ 67:Core/Src/main.c **** 68:Core/Src/main.c **** /** 69:Core/Src/main.c **** * @brief The application entry point. 70:Core/Src/main.c **** * @retval int 71:Core/Src/main.c **** */ 72:Core/Src/main.c **** int main(void) 73:Core/Src/main.c **** { 74:Core/Src/main.c **** /* USER CODE BEGIN 1 */ 75:Core/Src/main.c **** 76:Core/Src/main.c **** /* USER CODE END 1 */ 77:Core/Src/main.c **** 78:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ 79:Core/Src/main.c **** 80:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 81:Core/Src/main.c **** HAL_Init(); 82:Core/Src/main.c **** 83:Core/Src/main.c **** /* USER CODE BEGIN Init */ 84:Core/Src/main.c **** 85:Core/Src/main.c **** /* USER CODE END Init */ 86:Core/Src/main.c **** 87:Core/Src/main.c **** /* Configure the system clock */ 88:Core/Src/main.c **** SystemClock_Config(); 89:Core/Src/main.c **** 90:Core/Src/main.c **** /* USER CODE BEGIN SysInit */ ARM GAS /tmp/ccOqAezw.s page 3 91:Core/Src/main.c **** 92:Core/Src/main.c **** /* USER CODE END SysInit */ 93:Core/Src/main.c **** 94:Core/Src/main.c **** /* Initialize all configured peripherals */ 95:Core/Src/main.c **** MX_GPIO_Init(); 96:Core/Src/main.c **** MX_ADC_Init(); 97:Core/Src/main.c **** MX_CAN_Init(); 98:Core/Src/main.c **** MX_TIM2_Init(); 99:Core/Src/main.c **** /* USER CODE BEGIN 2 */ 100:Core/Src/main.c **** 101:Core/Src/main.c **** /* USER CODE END 2 */ 102:Core/Src/main.c **** 103:Core/Src/main.c **** /* Infinite loop */ 104:Core/Src/main.c **** /* USER CODE BEGIN WHILE */ 105:Core/Src/main.c **** while (1) 106:Core/Src/main.c **** { 107:Core/Src/main.c **** /* USER CODE END WHILE */ 108:Core/Src/main.c **** 109:Core/Src/main.c **** /* USER CODE BEGIN 3 */ 110:Core/Src/main.c **** } 111:Core/Src/main.c **** /* USER CODE END 3 */ 112:Core/Src/main.c **** } 113:Core/Src/main.c **** 114:Core/Src/main.c **** /** 115:Core/Src/main.c **** * @brief System Clock Configuration 116:Core/Src/main.c **** * @retval None 117:Core/Src/main.c **** */ 118:Core/Src/main.c **** void SystemClock_Config(void) 119:Core/Src/main.c **** { 120:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 121:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 122:Core/Src/main.c **** 123:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters 124:Core/Src/main.c **** * in the RCC_OscInitTypeDef structure. 125:Core/Src/main.c **** */ 126:Core/Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI14; 127:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; 128:Core/Src/main.c **** RCC_OscInitStruct.HSI14State = RCC_HSI14_ON; 129:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 130:Core/Src/main.c **** RCC_OscInitStruct.HSI14CalibrationValue = 16; 131:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 132:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 133:Core/Src/main.c **** { 134:Core/Src/main.c **** Error_Handler(); 135:Core/Src/main.c **** } 136:Core/Src/main.c **** 137:Core/Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks 138:Core/Src/main.c **** */ 139:Core/Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 140:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1; 141:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; 142:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 143:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 144:Core/Src/main.c **** 145:Core/Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 146:Core/Src/main.c **** { 147:Core/Src/main.c **** Error_Handler(); ARM GAS /tmp/ccOqAezw.s page 4 148:Core/Src/main.c **** } 149:Core/Src/main.c **** } 150:Core/Src/main.c **** 151:Core/Src/main.c **** /** 152:Core/Src/main.c **** * @brief ADC Initialization Function 153:Core/Src/main.c **** * @param None 154:Core/Src/main.c **** * @retval None 155:Core/Src/main.c **** */ 156:Core/Src/main.c **** static void MX_ADC_Init(void) 157:Core/Src/main.c **** { 158:Core/Src/main.c **** 159:Core/Src/main.c **** /* USER CODE BEGIN ADC_Init 0 */ 160:Core/Src/main.c **** 161:Core/Src/main.c **** /* USER CODE END ADC_Init 0 */ 162:Core/Src/main.c **** 163:Core/Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0}; 164:Core/Src/main.c **** 165:Core/Src/main.c **** /* USER CODE BEGIN ADC_Init 1 */ 166:Core/Src/main.c **** 167:Core/Src/main.c **** /* USER CODE END ADC_Init 1 */ 168:Core/Src/main.c **** 169:Core/Src/main.c **** /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of con 170:Core/Src/main.c **** */ 171:Core/Src/main.c **** hadc.Instance = ADC1; 172:Core/Src/main.c **** hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 173:Core/Src/main.c **** hadc.Init.Resolution = ADC_RESOLUTION_12B; 174:Core/Src/main.c **** hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT; 175:Core/Src/main.c **** hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; 176:Core/Src/main.c **** hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 177:Core/Src/main.c **** hadc.Init.LowPowerAutoWait = DISABLE; 178:Core/Src/main.c **** hadc.Init.LowPowerAutoPowerOff = DISABLE; 179:Core/Src/main.c **** hadc.Init.ContinuousConvMode = DISABLE; 180:Core/Src/main.c **** hadc.Init.DiscontinuousConvMode = DISABLE; 181:Core/Src/main.c **** hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START; 182:Core/Src/main.c **** hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 183:Core/Src/main.c **** hadc.Init.DMAContinuousRequests = DISABLE; 184:Core/Src/main.c **** hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED; 185:Core/Src/main.c **** if (HAL_ADC_Init(&hadc) != HAL_OK) 186:Core/Src/main.c **** { 187:Core/Src/main.c **** Error_Handler(); 188:Core/Src/main.c **** } 189:Core/Src/main.c **** 190:Core/Src/main.c **** /** Configure for the selected ADC regular channel to be converted. 191:Core/Src/main.c **** */ 192:Core/Src/main.c **** sConfig.Channel = ADC_CHANNEL_0; 193:Core/Src/main.c **** sConfig.Rank = ADC_RANK_CHANNEL_NUMBER; 194:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 195:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) 196:Core/Src/main.c **** { 197:Core/Src/main.c **** Error_Handler(); 198:Core/Src/main.c **** } 199:Core/Src/main.c **** 200:Core/Src/main.c **** /** Configure for the selected ADC regular channel to be converted. 201:Core/Src/main.c **** */ 202:Core/Src/main.c **** sConfig.Channel = ADC_CHANNEL_1; 203:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) 204:Core/Src/main.c **** { ARM GAS /tmp/ccOqAezw.s page 5 205:Core/Src/main.c **** Error_Handler(); 206:Core/Src/main.c **** } 207:Core/Src/main.c **** /* USER CODE BEGIN ADC_Init 2 */ 208:Core/Src/main.c **** 209:Core/Src/main.c **** /* USER CODE END ADC_Init 2 */ 210:Core/Src/main.c **** 211:Core/Src/main.c **** } 212:Core/Src/main.c **** 213:Core/Src/main.c **** /** 214:Core/Src/main.c **** * @brief CAN Initialization Function 215:Core/Src/main.c **** * @param None 216:Core/Src/main.c **** * @retval None 217:Core/Src/main.c **** */ 218:Core/Src/main.c **** static void MX_CAN_Init(void) 219:Core/Src/main.c **** { 220:Core/Src/main.c **** 221:Core/Src/main.c **** /* USER CODE BEGIN CAN_Init 0 */ 222:Core/Src/main.c **** 223:Core/Src/main.c **** /* USER CODE END CAN_Init 0 */ 224:Core/Src/main.c **** 225:Core/Src/main.c **** /* USER CODE BEGIN CAN_Init 1 */ 226:Core/Src/main.c **** 227:Core/Src/main.c **** /* USER CODE END CAN_Init 1 */ 228:Core/Src/main.c **** hcan.Instance = CAN; 229:Core/Src/main.c **** hcan.Init.Prescaler = 16; 230:Core/Src/main.c **** hcan.Init.Mode = CAN_MODE_NORMAL; 231:Core/Src/main.c **** hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; 232:Core/Src/main.c **** hcan.Init.TimeSeg1 = CAN_BS1_1TQ; 233:Core/Src/main.c **** hcan.Init.TimeSeg2 = CAN_BS2_1TQ; 234:Core/Src/main.c **** hcan.Init.TimeTriggeredMode = DISABLE; 235:Core/Src/main.c **** hcan.Init.AutoBusOff = DISABLE; 236:Core/Src/main.c **** hcan.Init.AutoWakeUp = DISABLE; 237:Core/Src/main.c **** hcan.Init.AutoRetransmission = DISABLE; 238:Core/Src/main.c **** hcan.Init.ReceiveFifoLocked = DISABLE; 239:Core/Src/main.c **** hcan.Init.TransmitFifoPriority = DISABLE; 240:Core/Src/main.c **** if (HAL_CAN_Init(&hcan) != HAL_OK) 241:Core/Src/main.c **** { 242:Core/Src/main.c **** Error_Handler(); 243:Core/Src/main.c **** } 244:Core/Src/main.c **** /* USER CODE BEGIN CAN_Init 2 */ 245:Core/Src/main.c **** 246:Core/Src/main.c **** /* USER CODE END CAN_Init 2 */ 247:Core/Src/main.c **** 248:Core/Src/main.c **** } 249:Core/Src/main.c **** 250:Core/Src/main.c **** /** 251:Core/Src/main.c **** * @brief TIM2 Initialization Function 252:Core/Src/main.c **** * @param None 253:Core/Src/main.c **** * @retval None 254:Core/Src/main.c **** */ 255:Core/Src/main.c **** static void MX_TIM2_Init(void) 256:Core/Src/main.c **** { 257:Core/Src/main.c **** 258:Core/Src/main.c **** /* USER CODE BEGIN TIM2_Init 0 */ 259:Core/Src/main.c **** 260:Core/Src/main.c **** /* USER CODE END TIM2_Init 0 */ 261:Core/Src/main.c **** ARM GAS /tmp/ccOqAezw.s page 6 262:Core/Src/main.c **** TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 263:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 264:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 265:Core/Src/main.c **** 266:Core/Src/main.c **** /* USER CODE BEGIN TIM2_Init 1 */ 267:Core/Src/main.c **** 268:Core/Src/main.c **** /* USER CODE END TIM2_Init 1 */ 269:Core/Src/main.c **** htim2.Instance = TIM2; 270:Core/Src/main.c **** htim2.Init.Prescaler = 0; 271:Core/Src/main.c **** htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 272:Core/Src/main.c **** htim2.Init.Period = 4294967295; 273:Core/Src/main.c **** htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 274:Core/Src/main.c **** htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 275:Core/Src/main.c **** if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 276:Core/Src/main.c **** { 277:Core/Src/main.c **** Error_Handler(); 278:Core/Src/main.c **** } 279:Core/Src/main.c **** sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 280:Core/Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 281:Core/Src/main.c **** { 282:Core/Src/main.c **** Error_Handler(); 283:Core/Src/main.c **** } 284:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) 285:Core/Src/main.c **** { 286:Core/Src/main.c **** Error_Handler(); 287:Core/Src/main.c **** } 288:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 289:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 290:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 291:Core/Src/main.c **** { 292:Core/Src/main.c **** Error_Handler(); 293:Core/Src/main.c **** } 294:Core/Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1; 295:Core/Src/main.c **** sConfigOC.Pulse = 0; 296:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 297:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 298:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 299:Core/Src/main.c **** { 300:Core/Src/main.c **** Error_Handler(); 301:Core/Src/main.c **** } 302:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 303:Core/Src/main.c **** { 304:Core/Src/main.c **** Error_Handler(); 305:Core/Src/main.c **** } 306:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 307:Core/Src/main.c **** { 308:Core/Src/main.c **** Error_Handler(); 309:Core/Src/main.c **** } 310:Core/Src/main.c **** /* USER CODE BEGIN TIM2_Init 2 */ 311:Core/Src/main.c **** 312:Core/Src/main.c **** /* USER CODE END TIM2_Init 2 */ 313:Core/Src/main.c **** HAL_TIM_MspPostInit(&htim2); 314:Core/Src/main.c **** 315:Core/Src/main.c **** } 316:Core/Src/main.c **** 317:Core/Src/main.c **** /** 318:Core/Src/main.c **** * @brief GPIO Initialization Function ARM GAS /tmp/ccOqAezw.s page 7 319:Core/Src/main.c **** * @param None 320:Core/Src/main.c **** * @retval None 321:Core/Src/main.c **** */ 322:Core/Src/main.c **** static void MX_GPIO_Init(void) 323:Core/Src/main.c **** { 26 .loc 1 323 1 view -0 27 .cfi_startproc 28 @ args = 0, pretend = 0, frame = 16 29 @ frame_needed = 0, uses_anonymous_args = 0 30 @ link register save eliminated. 31 0000 84B0 sub sp, sp, #16 32 .cfi_def_cfa_offset 16 324:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */ 325:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_1 */ 326:Core/Src/main.c **** 327:Core/Src/main.c **** /* GPIO Ports Clock Enable */ 328:Core/Src/main.c **** __HAL_RCC_GPIOF_CLK_ENABLE(); 33 .loc 1 328 3 view .LVU1 34 .LBB4: 35 .loc 1 328 3 view .LVU2 36 .loc 1 328 3 view .LVU3 37 0002 0F4B ldr r3, .L2 38 0004 5A69 ldr r2, [r3, #20] 39 0006 8021 movs r1, #128 40 0008 C903 lsls r1, r1, #15 41 000a 0A43 orrs r2, r1 42 000c 5A61 str r2, [r3, #20] 43 .loc 1 328 3 view .LVU4 44 000e 5A69 ldr r2, [r3, #20] 45 0010 0A40 ands r2, r1 46 0012 0192 str r2, [sp, #4] 47 .loc 1 328 3 view .LVU5 48 0014 019A ldr r2, [sp, #4] 49 .LBE4: 50 .loc 1 328 3 view .LVU6 329:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); 51 .loc 1 329 3 view .LVU7 52 .LBB5: 53 .loc 1 329 3 view .LVU8 54 .loc 1 329 3 view .LVU9 55 0016 5A69 ldr r2, [r3, #20] 56 0018 8021 movs r1, #128 57 001a 8902 lsls r1, r1, #10 58 001c 0A43 orrs r2, r1 59 001e 5A61 str r2, [r3, #20] 60 .loc 1 329 3 view .LVU10 61 0020 5A69 ldr r2, [r3, #20] 62 0022 0A40 ands r2, r1 63 0024 0292 str r2, [sp, #8] 64 .loc 1 329 3 view .LVU11 65 0026 029A ldr r2, [sp, #8] 66 .LBE5: 67 .loc 1 329 3 view .LVU12 330:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); 68 .loc 1 330 3 view .LVU13 69 .LBB6: 70 .loc 1 330 3 view .LVU14 ARM GAS /tmp/ccOqAezw.s page 8 71 .loc 1 330 3 view .LVU15 72 0028 5A69 ldr r2, [r3, #20] 73 002a 8021 movs r1, #128 74 002c C902 lsls r1, r1, #11 75 002e 0A43 orrs r2, r1 76 0030 5A61 str r2, [r3, #20] 77 .loc 1 330 3 view .LVU16 78 0032 5B69 ldr r3, [r3, #20] 79 0034 0B40 ands r3, r1 80 0036 0393 str r3, [sp, #12] 81 .loc 1 330 3 view .LVU17 82 0038 039B ldr r3, [sp, #12] 83 .LBE6: 84 .loc 1 330 3 view .LVU18 331:Core/Src/main.c **** 332:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_2 */ 333:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_2 */ 334:Core/Src/main.c **** } 85 .loc 1 334 1 is_stmt 0 view .LVU19 86 003a 04B0 add sp, sp, #16 87 @ sp needed 88 003c 7047 bx lr 89 .L3: 90 003e C046 .align 2 91 .L2: 92 0040 00100240 .word 1073876992 93 .cfi_endproc 94 .LFE45: 96 .section .text.Error_Handler,"ax",%progbits 97 .align 1 98 .global Error_Handler 99 .syntax unified 100 .code 16 101 .thumb_func 103 Error_Handler: 104 .LFB46: 335:Core/Src/main.c **** 336:Core/Src/main.c **** /* USER CODE BEGIN 4 */ 337:Core/Src/main.c **** 338:Core/Src/main.c **** /* USER CODE END 4 */ 339:Core/Src/main.c **** 340:Core/Src/main.c **** /** 341:Core/Src/main.c **** * @brief This function is executed in case of error occurrence. 342:Core/Src/main.c **** * @retval None 343:Core/Src/main.c **** */ 344:Core/Src/main.c **** void Error_Handler(void) 345:Core/Src/main.c **** { 105 .loc 1 345 1 is_stmt 1 view -0 106 .cfi_startproc 107 @ Volatile: function does not return. 108 @ args = 0, pretend = 0, frame = 0 109 @ frame_needed = 0, uses_anonymous_args = 0 110 @ link register save eliminated. 346:Core/Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */ 347:Core/Src/main.c **** /* User can add his own implementation to report the HAL error return state */ 348:Core/Src/main.c **** __disable_irq(); 111 .loc 1 348 3 view .LVU21 ARM GAS /tmp/ccOqAezw.s page 9 112 .LBB7: 113 .LBI7: 114 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 24:Drivers/CMSIS/Include/cmsis_gcc.h **** 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H 27:Drivers/CMSIS/Include/cmsis_gcc.h **** 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" 33:Drivers/CMSIS/Include/cmsis_gcc.h **** 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 38:Drivers/CMSIS/Include/cmsis_gcc.h **** 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif ARM GAS /tmp/ccOqAezw.s page 10 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) ARM GAS /tmp/ccOqAezw.s page 11 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 116:Drivers/CMSIS/Include/cmsis_gcc.h **** 117:Drivers/CMSIS/Include/cmsis_gcc.h **** 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } 133:Drivers/CMSIS/Include/cmsis_gcc.h **** 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) 115 .loc 2 140 27 view .LVU22 116 .LBB8: 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); 117 .loc 2 142 3 view .LVU23 118 .syntax divided 119 @ 142 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 120 0000 72B6 cpsid i 121 @ 0 "" 2 122 .thumb 123 .syntax unified 124 .L5: 125 .LBE8: 126 .LBE7: 349:Core/Src/main.c **** while (1) 127 .loc 1 349 3 view .LVU24 350:Core/Src/main.c **** { 351:Core/Src/main.c **** } 128 .loc 1 351 3 view .LVU25 349:Core/Src/main.c **** while (1) 129 .loc 1 349 9 view .LVU26 130 0002 FEE7 b .L5 131 .cfi_endproc 132 .LFE46: 134 .section .text.MX_ADC_Init,"ax",%progbits 135 .align 1 136 .syntax unified 137 .code 16 ARM GAS /tmp/ccOqAezw.s page 12 138 .thumb_func 140 MX_ADC_Init: 141 .LFB42: 157:Core/Src/main.c **** 142 .loc 1 157 1 view -0 143 .cfi_startproc 144 @ args = 0, pretend = 0, frame = 16 145 @ frame_needed = 0, uses_anonymous_args = 0 146 0000 00B5 push {lr} 147 .cfi_def_cfa_offset 4 148 .cfi_offset 14, -4 149 0002 85B0 sub sp, sp, #20 150 .cfi_def_cfa_offset 24 163:Core/Src/main.c **** 151 .loc 1 163 3 view .LVU28 163:Core/Src/main.c **** 152 .loc 1 163 26 is_stmt 0 view .LVU29 153 0004 0C22 movs r2, #12 154 0006 0021 movs r1, #0 155 0008 01A8 add r0, sp, #4 156 000a FFF7FEFF bl memset 157 .LVL0: 171:Core/Src/main.c **** hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 158 .loc 1 171 3 is_stmt 1 view .LVU30 171:Core/Src/main.c **** hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 159 .loc 1 171 17 is_stmt 0 view .LVU31 160 000e 1C48 ldr r0, .L13 161 0010 1C4B ldr r3, .L13+4 162 0012 0360 str r3, [r0] 172:Core/Src/main.c **** hadc.Init.Resolution = ADC_RESOLUTION_12B; 163 .loc 1 172 3 is_stmt 1 view .LVU32 172:Core/Src/main.c **** hadc.Init.Resolution = ADC_RESOLUTION_12B; 164 .loc 1 172 28 is_stmt 0 view .LVU33 165 0014 0023 movs r3, #0 166 0016 4360 str r3, [r0, #4] 173:Core/Src/main.c **** hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT; 167 .loc 1 173 3 is_stmt 1 view .LVU34 173:Core/Src/main.c **** hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT; 168 .loc 1 173 24 is_stmt 0 view .LVU35 169 0018 8360 str r3, [r0, #8] 174:Core/Src/main.c **** hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; 170 .loc 1 174 3 is_stmt 1 view .LVU36 174:Core/Src/main.c **** hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; 171 .loc 1 174 23 is_stmt 0 view .LVU37 172 001a C360 str r3, [r0, #12] 175:Core/Src/main.c **** hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 173 .loc 1 175 3 is_stmt 1 view .LVU38 175:Core/Src/main.c **** hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 174 .loc 1 175 26 is_stmt 0 view .LVU39 175 001c 0122 movs r2, #1 176 001e 0261 str r2, [r0, #16] 176:Core/Src/main.c **** hadc.Init.LowPowerAutoWait = DISABLE; 177 .loc 1 176 3 is_stmt 1 view .LVU40 176:Core/Src/main.c **** hadc.Init.LowPowerAutoWait = DISABLE; 178 .loc 1 176 26 is_stmt 0 view .LVU41 179 0020 0421 movs r1, #4 180 0022 4161 str r1, [r0, #20] ARM GAS /tmp/ccOqAezw.s page 13 177:Core/Src/main.c **** hadc.Init.LowPowerAutoPowerOff = DISABLE; 181 .loc 1 177 3 is_stmt 1 view .LVU42 177:Core/Src/main.c **** hadc.Init.LowPowerAutoPowerOff = DISABLE; 182 .loc 1 177 30 is_stmt 0 view .LVU43 183 0024 0376 strb r3, [r0, #24] 178:Core/Src/main.c **** hadc.Init.ContinuousConvMode = DISABLE; 184 .loc 1 178 3 is_stmt 1 view .LVU44 178:Core/Src/main.c **** hadc.Init.ContinuousConvMode = DISABLE; 185 .loc 1 178 34 is_stmt 0 view .LVU45 186 0026 4376 strb r3, [r0, #25] 179:Core/Src/main.c **** hadc.Init.DiscontinuousConvMode = DISABLE; 187 .loc 1 179 3 is_stmt 1 view .LVU46 179:Core/Src/main.c **** hadc.Init.DiscontinuousConvMode = DISABLE; 188 .loc 1 179 32 is_stmt 0 view .LVU47 189 0028 8376 strb r3, [r0, #26] 180:Core/Src/main.c **** hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START; 190 .loc 1 180 3 is_stmt 1 view .LVU48 180:Core/Src/main.c **** hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START; 191 .loc 1 180 35 is_stmt 0 view .LVU49 192 002a C376 strb r3, [r0, #27] 181:Core/Src/main.c **** hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 193 .loc 1 181 3 is_stmt 1 view .LVU50 181:Core/Src/main.c **** hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 194 .loc 1 181 30 is_stmt 0 view .LVU51 195 002c C221 movs r1, #194 196 002e FF31 adds r1, r1, #255 197 0030 C161 str r1, [r0, #28] 182:Core/Src/main.c **** hadc.Init.DMAContinuousRequests = DISABLE; 198 .loc 1 182 3 is_stmt 1 view .LVU52 182:Core/Src/main.c **** hadc.Init.DMAContinuousRequests = DISABLE; 199 .loc 1 182 34 is_stmt 0 view .LVU53 200 0032 0362 str r3, [r0, #32] 183:Core/Src/main.c **** hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED; 201 .loc 1 183 3 is_stmt 1 view .LVU54 183:Core/Src/main.c **** hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED; 202 .loc 1 183 35 is_stmt 0 view .LVU55 203 0034 9E39 subs r1, r1, #158 204 0036 FF39 subs r1, r1, #255 205 0038 4354 strb r3, [r0, r1] 184:Core/Src/main.c **** if (HAL_ADC_Init(&hadc) != HAL_OK) 206 .loc 1 184 3 is_stmt 1 view .LVU56 184:Core/Src/main.c **** if (HAL_ADC_Init(&hadc) != HAL_OK) 207 .loc 1 184 21 is_stmt 0 view .LVU57 208 003a 8262 str r2, [r0, #40] 185:Core/Src/main.c **** { 209 .loc 1 185 3 is_stmt 1 view .LVU58 185:Core/Src/main.c **** { 210 .loc 1 185 7 is_stmt 0 view .LVU59 211 003c FFF7FEFF bl HAL_ADC_Init 212 .LVL1: 185:Core/Src/main.c **** { 213 .loc 1 185 6 discriminator 1 view .LVU60 214 0040 0028 cmp r0, #0 215 0042 17D1 bne .L10 192:Core/Src/main.c **** sConfig.Rank = ADC_RANK_CHANNEL_NUMBER; 216 .loc 1 192 3 is_stmt 1 view .LVU61 192:Core/Src/main.c **** sConfig.Rank = ADC_RANK_CHANNEL_NUMBER; ARM GAS /tmp/ccOqAezw.s page 14 217 .loc 1 192 19 is_stmt 0 view .LVU62 218 0044 0023 movs r3, #0 219 0046 0193 str r3, [sp, #4] 193:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 220 .loc 1 193 3 is_stmt 1 view .LVU63 193:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 221 .loc 1 193 16 is_stmt 0 view .LVU64 222 0048 8023 movs r3, #128 223 004a 5B01 lsls r3, r3, #5 224 004c 0293 str r3, [sp, #8] 194:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) 225 .loc 1 194 3 is_stmt 1 view .LVU65 194:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) 226 .loc 1 194 24 is_stmt 0 view .LVU66 227 004e 8023 movs r3, #128 228 0050 5B05 lsls r3, r3, #21 229 0052 0393 str r3, [sp, #12] 195:Core/Src/main.c **** { 230 .loc 1 195 3 is_stmt 1 view .LVU67 195:Core/Src/main.c **** { 231 .loc 1 195 7 is_stmt 0 view .LVU68 232 0054 0A48 ldr r0, .L13 233 0056 01A9 add r1, sp, #4 234 0058 FFF7FEFF bl HAL_ADC_ConfigChannel 235 .LVL2: 195:Core/Src/main.c **** { 236 .loc 1 195 6 discriminator 1 view .LVU69 237 005c 0028 cmp r0, #0 238 005e 0BD1 bne .L11 202:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) 239 .loc 1 202 3 is_stmt 1 view .LVU70 202:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) 240 .loc 1 202 19 is_stmt 0 view .LVU71 241 0060 0123 movs r3, #1 242 0062 0193 str r3, [sp, #4] 203:Core/Src/main.c **** { 243 .loc 1 203 3 is_stmt 1 view .LVU72 203:Core/Src/main.c **** { 244 .loc 1 203 7 is_stmt 0 view .LVU73 245 0064 0648 ldr r0, .L13 246 0066 01A9 add r1, sp, #4 247 0068 FFF7FEFF bl HAL_ADC_ConfigChannel 248 .LVL3: 203:Core/Src/main.c **** { 249 .loc 1 203 6 discriminator 1 view .LVU74 250 006c 0028 cmp r0, #0 251 006e 05D1 bne .L12 211:Core/Src/main.c **** 252 .loc 1 211 1 view .LVU75 253 0070 05B0 add sp, sp, #20 254 @ sp needed 255 0072 00BD pop {pc} 256 .L10: 187:Core/Src/main.c **** } 257 .loc 1 187 5 is_stmt 1 view .LVU76 258 0074 FFF7FEFF bl Error_Handler 259 .LVL4: ARM GAS /tmp/ccOqAezw.s page 15 260 .L11: 197:Core/Src/main.c **** } 261 .loc 1 197 5 view .LVU77 262 0078 FFF7FEFF bl Error_Handler 263 .LVL5: 264 .L12: 205:Core/Src/main.c **** } 265 .loc 1 205 5 view .LVU78 266 007c FFF7FEFF bl Error_Handler 267 .LVL6: 268 .L14: 269 .align 2 270 .L13: 271 0080 00000000 .word hadc 272 0084 00240140 .word 1073816576 273 .cfi_endproc 274 .LFE42: 276 .section .text.MX_CAN_Init,"ax",%progbits 277 .align 1 278 .syntax unified 279 .code 16 280 .thumb_func 282 MX_CAN_Init: 283 .LFB43: 219:Core/Src/main.c **** 284 .loc 1 219 1 view -0 285 .cfi_startproc 286 @ args = 0, pretend = 0, frame = 0 287 @ frame_needed = 0, uses_anonymous_args = 0 288 0000 10B5 push {r4, lr} 289 .cfi_def_cfa_offset 8 290 .cfi_offset 4, -8 291 .cfi_offset 14, -4 228:Core/Src/main.c **** hcan.Init.Prescaler = 16; 292 .loc 1 228 3 view .LVU80 228:Core/Src/main.c **** hcan.Init.Prescaler = 16; 293 .loc 1 228 17 is_stmt 0 view .LVU81 294 0002 0B48 ldr r0, .L18 295 0004 0B4B ldr r3, .L18+4 296 0006 0360 str r3, [r0] 229:Core/Src/main.c **** hcan.Init.Mode = CAN_MODE_NORMAL; 297 .loc 1 229 3 is_stmt 1 view .LVU82 229:Core/Src/main.c **** hcan.Init.Mode = CAN_MODE_NORMAL; 298 .loc 1 229 23 is_stmt 0 view .LVU83 299 0008 1023 movs r3, #16 300 000a 4360 str r3, [r0, #4] 230:Core/Src/main.c **** hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; 301 .loc 1 230 3 is_stmt 1 view .LVU84 230:Core/Src/main.c **** hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; 302 .loc 1 230 18 is_stmt 0 view .LVU85 303 000c 0023 movs r3, #0 304 000e 8360 str r3, [r0, #8] 231:Core/Src/main.c **** hcan.Init.TimeSeg1 = CAN_BS1_1TQ; 305 .loc 1 231 3 is_stmt 1 view .LVU86 231:Core/Src/main.c **** hcan.Init.TimeSeg1 = CAN_BS1_1TQ; 306 .loc 1 231 27 is_stmt 0 view .LVU87 307 0010 C360 str r3, [r0, #12] ARM GAS /tmp/ccOqAezw.s page 16 232:Core/Src/main.c **** hcan.Init.TimeSeg2 = CAN_BS2_1TQ; 308 .loc 1 232 3 is_stmt 1 view .LVU88 232:Core/Src/main.c **** hcan.Init.TimeSeg2 = CAN_BS2_1TQ; 309 .loc 1 232 22 is_stmt 0 view .LVU89 310 0012 0361 str r3, [r0, #16] 233:Core/Src/main.c **** hcan.Init.TimeTriggeredMode = DISABLE; 311 .loc 1 233 3 is_stmt 1 view .LVU90 233:Core/Src/main.c **** hcan.Init.TimeTriggeredMode = DISABLE; 312 .loc 1 233 22 is_stmt 0 view .LVU91 313 0014 4361 str r3, [r0, #20] 234:Core/Src/main.c **** hcan.Init.AutoBusOff = DISABLE; 314 .loc 1 234 3 is_stmt 1 view .LVU92 234:Core/Src/main.c **** hcan.Init.AutoBusOff = DISABLE; 315 .loc 1 234 31 is_stmt 0 view .LVU93 316 0016 0376 strb r3, [r0, #24] 235:Core/Src/main.c **** hcan.Init.AutoWakeUp = DISABLE; 317 .loc 1 235 3 is_stmt 1 view .LVU94 235:Core/Src/main.c **** hcan.Init.AutoWakeUp = DISABLE; 318 .loc 1 235 24 is_stmt 0 view .LVU95 319 0018 4376 strb r3, [r0, #25] 236:Core/Src/main.c **** hcan.Init.AutoRetransmission = DISABLE; 320 .loc 1 236 3 is_stmt 1 view .LVU96 236:Core/Src/main.c **** hcan.Init.AutoRetransmission = DISABLE; 321 .loc 1 236 24 is_stmt 0 view .LVU97 322 001a 8376 strb r3, [r0, #26] 237:Core/Src/main.c **** hcan.Init.ReceiveFifoLocked = DISABLE; 323 .loc 1 237 3 is_stmt 1 view .LVU98 237:Core/Src/main.c **** hcan.Init.ReceiveFifoLocked = DISABLE; 324 .loc 1 237 32 is_stmt 0 view .LVU99 325 001c C376 strb r3, [r0, #27] 238:Core/Src/main.c **** hcan.Init.TransmitFifoPriority = DISABLE; 326 .loc 1 238 3 is_stmt 1 view .LVU100 238:Core/Src/main.c **** hcan.Init.TransmitFifoPriority = DISABLE; 327 .loc 1 238 31 is_stmt 0 view .LVU101 328 001e 0377 strb r3, [r0, #28] 239:Core/Src/main.c **** if (HAL_CAN_Init(&hcan) != HAL_OK) 329 .loc 1 239 3 is_stmt 1 view .LVU102 239:Core/Src/main.c **** if (HAL_CAN_Init(&hcan) != HAL_OK) 330 .loc 1 239 34 is_stmt 0 view .LVU103 331 0020 4377 strb r3, [r0, #29] 240:Core/Src/main.c **** { 332 .loc 1 240 3 is_stmt 1 view .LVU104 240:Core/Src/main.c **** { 333 .loc 1 240 7 is_stmt 0 view .LVU105 334 0022 FFF7FEFF bl HAL_CAN_Init 335 .LVL7: 240:Core/Src/main.c **** { 336 .loc 1 240 6 discriminator 1 view .LVU106 337 0026 0028 cmp r0, #0 338 0028 00D1 bne .L17 248:Core/Src/main.c **** 339 .loc 1 248 1 view .LVU107 340 @ sp needed 341 002a 10BD pop {r4, pc} 342 .L17: 242:Core/Src/main.c **** } 343 .loc 1 242 5 is_stmt 1 view .LVU108 ARM GAS /tmp/ccOqAezw.s page 17 344 002c FFF7FEFF bl Error_Handler 345 .LVL8: 346 .L19: 347 .align 2 348 .L18: 349 0030 00000000 .word hcan 350 0034 00640040 .word 1073767424 351 .cfi_endproc 352 .LFE43: 354 .section .text.MX_TIM2_Init,"ax",%progbits 355 .align 1 356 .syntax unified 357 .code 16 358 .thumb_func 360 MX_TIM2_Init: 361 .LFB44: 256:Core/Src/main.c **** 362 .loc 1 256 1 view -0 363 .cfi_startproc 364 @ args = 0, pretend = 0, frame = 56 365 @ frame_needed = 0, uses_anonymous_args = 0 366 0000 00B5 push {lr} 367 .cfi_def_cfa_offset 4 368 .cfi_offset 14, -4 369 0002 8FB0 sub sp, sp, #60 370 .cfi_def_cfa_offset 64 262:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 371 .loc 1 262 3 view .LVU110 262:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 372 .loc 1 262 26 is_stmt 0 view .LVU111 373 0004 1022 movs r2, #16 374 0006 0021 movs r1, #0 375 0008 0AA8 add r0, sp, #40 376 000a FFF7FEFF bl memset 377 .LVL9: 263:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 378 .loc 1 263 3 is_stmt 1 view .LVU112 263:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 379 .loc 1 263 27 is_stmt 0 view .LVU113 380 000e 0822 movs r2, #8 381 0010 0021 movs r1, #0 382 0012 08A8 add r0, sp, #32 383 0014 FFF7FEFF bl memset 384 .LVL10: 264:Core/Src/main.c **** 385 .loc 1 264 3 is_stmt 1 view .LVU114 264:Core/Src/main.c **** 386 .loc 1 264 22 is_stmt 0 view .LVU115 387 0018 1C22 movs r2, #28 388 001a 0021 movs r1, #0 389 001c 01A8 add r0, sp, #4 390 001e FFF7FEFF bl memset 391 .LVL11: 269:Core/Src/main.c **** htim2.Init.Prescaler = 0; 392 .loc 1 269 3 is_stmt 1 view .LVU116 269:Core/Src/main.c **** htim2.Init.Prescaler = 0; 393 .loc 1 269 18 is_stmt 0 view .LVU117 ARM GAS /tmp/ccOqAezw.s page 18 394 0022 2A48 ldr r0, .L35 395 0024 8023 movs r3, #128 396 0026 DB05 lsls r3, r3, #23 397 0028 0360 str r3, [r0] 270:Core/Src/main.c **** htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 398 .loc 1 270 3 is_stmt 1 view .LVU118 270:Core/Src/main.c **** htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 399 .loc 1 270 24 is_stmt 0 view .LVU119 400 002a 0023 movs r3, #0 401 002c 4360 str r3, [r0, #4] 271:Core/Src/main.c **** htim2.Init.Period = 4294967295; 402 .loc 1 271 3 is_stmt 1 view .LVU120 271:Core/Src/main.c **** htim2.Init.Period = 4294967295; 403 .loc 1 271 26 is_stmt 0 view .LVU121 404 002e 8360 str r3, [r0, #8] 272:Core/Src/main.c **** htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 405 .loc 1 272 3 is_stmt 1 view .LVU122 272:Core/Src/main.c **** htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 406 .loc 1 272 21 is_stmt 0 view .LVU123 407 0030 0122 movs r2, #1 408 0032 5242 rsbs r2, r2, #0 409 0034 C260 str r2, [r0, #12] 273:Core/Src/main.c **** htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 410 .loc 1 273 3 is_stmt 1 view .LVU124 273:Core/Src/main.c **** htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 411 .loc 1 273 28 is_stmt 0 view .LVU125 412 0036 0361 str r3, [r0, #16] 274:Core/Src/main.c **** if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 413 .loc 1 274 3 is_stmt 1 view .LVU126 274:Core/Src/main.c **** if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 414 .loc 1 274 32 is_stmt 0 view .LVU127 415 0038 8361 str r3, [r0, #24] 275:Core/Src/main.c **** { 416 .loc 1 275 3 is_stmt 1 view .LVU128 275:Core/Src/main.c **** { 417 .loc 1 275 7 is_stmt 0 view .LVU129 418 003a FFF7FEFF bl HAL_TIM_Base_Init 419 .LVL12: 275:Core/Src/main.c **** { 420 .loc 1 275 6 discriminator 1 view .LVU130 421 003e 0028 cmp r0, #0 422 0040 36D1 bne .L28 279:Core/Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 423 .loc 1 279 3 is_stmt 1 view .LVU131 279:Core/Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 424 .loc 1 279 34 is_stmt 0 view .LVU132 425 0042 8023 movs r3, #128 426 0044 5B01 lsls r3, r3, #5 427 0046 0A93 str r3, [sp, #40] 280:Core/Src/main.c **** { 428 .loc 1 280 3 is_stmt 1 view .LVU133 280:Core/Src/main.c **** { 429 .loc 1 280 7 is_stmt 0 view .LVU134 430 0048 2048 ldr r0, .L35 431 004a 0AA9 add r1, sp, #40 432 004c FFF7FEFF bl HAL_TIM_ConfigClockSource 433 .LVL13: ARM GAS /tmp/ccOqAezw.s page 19 280:Core/Src/main.c **** { 434 .loc 1 280 6 discriminator 1 view .LVU135 435 0050 0028 cmp r0, #0 436 0052 2FD1 bne .L29 284:Core/Src/main.c **** { 437 .loc 1 284 3 is_stmt 1 view .LVU136 284:Core/Src/main.c **** { 438 .loc 1 284 7 is_stmt 0 view .LVU137 439 0054 1D48 ldr r0, .L35 440 0056 FFF7FEFF bl HAL_TIM_PWM_Init 441 .LVL14: 284:Core/Src/main.c **** { 442 .loc 1 284 6 discriminator 1 view .LVU138 443 005a 0028 cmp r0, #0 444 005c 2CD1 bne .L30 288:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 445 .loc 1 288 3 is_stmt 1 view .LVU139 288:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 446 .loc 1 288 37 is_stmt 0 view .LVU140 447 005e 0023 movs r3, #0 448 0060 0893 str r3, [sp, #32] 289:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 449 .loc 1 289 3 is_stmt 1 view .LVU141 289:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 450 .loc 1 289 33 is_stmt 0 view .LVU142 451 0062 0993 str r3, [sp, #36] 290:Core/Src/main.c **** { 452 .loc 1 290 3 is_stmt 1 view .LVU143 290:Core/Src/main.c **** { 453 .loc 1 290 7 is_stmt 0 view .LVU144 454 0064 1948 ldr r0, .L35 455 0066 08A9 add r1, sp, #32 456 0068 FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization 457 .LVL15: 290:Core/Src/main.c **** { 458 .loc 1 290 6 discriminator 1 view .LVU145 459 006c 0028 cmp r0, #0 460 006e 25D1 bne .L31 294:Core/Src/main.c **** sConfigOC.Pulse = 0; 461 .loc 1 294 3 is_stmt 1 view .LVU146 294:Core/Src/main.c **** sConfigOC.Pulse = 0; 462 .loc 1 294 20 is_stmt 0 view .LVU147 463 0070 6023 movs r3, #96 464 0072 0193 str r3, [sp, #4] 295:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 465 .loc 1 295 3 is_stmt 1 view .LVU148 295:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 466 .loc 1 295 19 is_stmt 0 view .LVU149 467 0074 0023 movs r3, #0 468 0076 0293 str r3, [sp, #8] 296:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 469 .loc 1 296 3 is_stmt 1 view .LVU150 296:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 470 .loc 1 296 24 is_stmt 0 view .LVU151 471 0078 0393 str r3, [sp, #12] 297:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 472 .loc 1 297 3 is_stmt 1 view .LVU152 ARM GAS /tmp/ccOqAezw.s page 20 297:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 473 .loc 1 297 24 is_stmt 0 view .LVU153 474 007a 0593 str r3, [sp, #20] 298:Core/Src/main.c **** { 475 .loc 1 298 3 is_stmt 1 view .LVU154 298:Core/Src/main.c **** { 476 .loc 1 298 7 is_stmt 0 view .LVU155 477 007c 1348 ldr r0, .L35 478 007e 0022 movs r2, #0 479 0080 01A9 add r1, sp, #4 480 0082 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 481 .LVL16: 298:Core/Src/main.c **** { 482 .loc 1 298 6 discriminator 1 view .LVU156 483 0086 0028 cmp r0, #0 484 0088 1AD1 bne .L32 302:Core/Src/main.c **** { 485 .loc 1 302 3 is_stmt 1 view .LVU157 302:Core/Src/main.c **** { 486 .loc 1 302 7 is_stmt 0 view .LVU158 487 008a 1048 ldr r0, .L35 488 008c 0422 movs r2, #4 489 008e 01A9 add r1, sp, #4 490 0090 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 491 .LVL17: 302:Core/Src/main.c **** { 492 .loc 1 302 6 discriminator 1 view .LVU159 493 0094 0028 cmp r0, #0 494 0096 15D1 bne .L33 306:Core/Src/main.c **** { 495 .loc 1 306 3 is_stmt 1 view .LVU160 306:Core/Src/main.c **** { 496 .loc 1 306 7 is_stmt 0 view .LVU161 497 0098 0C48 ldr r0, .L35 498 009a 0822 movs r2, #8 499 009c 01A9 add r1, sp, #4 500 009e FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 501 .LVL18: 306:Core/Src/main.c **** { 502 .loc 1 306 6 discriminator 1 view .LVU162 503 00a2 0028 cmp r0, #0 504 00a4 10D1 bne .L34 313:Core/Src/main.c **** 505 .loc 1 313 3 is_stmt 1 view .LVU163 506 00a6 0948 ldr r0, .L35 507 00a8 FFF7FEFF bl HAL_TIM_MspPostInit 508 .LVL19: 315:Core/Src/main.c **** 509 .loc 1 315 1 is_stmt 0 view .LVU164 510 00ac 0FB0 add sp, sp, #60 511 @ sp needed 512 00ae 00BD pop {pc} 513 .L28: 277:Core/Src/main.c **** } 514 .loc 1 277 5 is_stmt 1 view .LVU165 515 00b0 FFF7FEFF bl Error_Handler 516 .LVL20: ARM GAS /tmp/ccOqAezw.s page 21 517 .L29: 282:Core/Src/main.c **** } 518 .loc 1 282 5 view .LVU166 519 00b4 FFF7FEFF bl Error_Handler 520 .LVL21: 521 .L30: 286:Core/Src/main.c **** } 522 .loc 1 286 5 view .LVU167 523 00b8 FFF7FEFF bl Error_Handler 524 .LVL22: 525 .L31: 292:Core/Src/main.c **** } 526 .loc 1 292 5 view .LVU168 527 00bc FFF7FEFF bl Error_Handler 528 .LVL23: 529 .L32: 300:Core/Src/main.c **** } 530 .loc 1 300 5 view .LVU169 531 00c0 FFF7FEFF bl Error_Handler 532 .LVL24: 533 .L33: 304:Core/Src/main.c **** } 534 .loc 1 304 5 view .LVU170 535 00c4 FFF7FEFF bl Error_Handler 536 .LVL25: 537 .L34: 308:Core/Src/main.c **** } 538 .loc 1 308 5 view .LVU171 539 00c8 FFF7FEFF bl Error_Handler 540 .LVL26: 541 .L36: 542 .align 2 543 .L35: 544 00cc 00000000 .word htim2 545 .cfi_endproc 546 .LFE44: 548 .section .text.SystemClock_Config,"ax",%progbits 549 .align 1 550 .global SystemClock_Config 551 .syntax unified 552 .code 16 553 .thumb_func 555 SystemClock_Config: 556 .LFB41: 119:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 557 .loc 1 119 1 view -0 558 .cfi_startproc 559 @ args = 0, pretend = 0, frame = 72 560 @ frame_needed = 0, uses_anonymous_args = 0 561 0000 10B5 push {r4, lr} 562 .cfi_def_cfa_offset 8 563 .cfi_offset 4, -8 564 .cfi_offset 14, -4 565 0002 92B0 sub sp, sp, #72 566 .cfi_def_cfa_offset 80 120:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 567 .loc 1 120 3 view .LVU173 ARM GAS /tmp/ccOqAezw.s page 22 120:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 568 .loc 1 120 22 is_stmt 0 view .LVU174 569 0004 3422 movs r2, #52 570 0006 0021 movs r1, #0 571 0008 05A8 add r0, sp, #20 572 000a FFF7FEFF bl memset 573 .LVL27: 121:Core/Src/main.c **** 574 .loc 1 121 3 is_stmt 1 view .LVU175 121:Core/Src/main.c **** 575 .loc 1 121 22 is_stmt 0 view .LVU176 576 000e 1024 movs r4, #16 577 0010 1022 movs r2, #16 578 0012 0021 movs r1, #0 579 0014 01A8 add r0, sp, #4 580 0016 FFF7FEFF bl memset 581 .LVL28: 126:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; 582 .loc 1 126 3 is_stmt 1 view .LVU177 126:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; 583 .loc 1 126 36 is_stmt 0 view .LVU178 584 001a 1223 movs r3, #18 585 001c 0593 str r3, [sp, #20] 127:Core/Src/main.c **** RCC_OscInitStruct.HSI14State = RCC_HSI14_ON; 586 .loc 1 127 3 is_stmt 1 view .LVU179 127:Core/Src/main.c **** RCC_OscInitStruct.HSI14State = RCC_HSI14_ON; 587 .loc 1 127 30 is_stmt 0 view .LVU180 588 001e 113B subs r3, r3, #17 589 0020 0893 str r3, [sp, #32] 128:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 590 .loc 1 128 3 is_stmt 1 view .LVU181 128:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 591 .loc 1 128 32 is_stmt 0 view .LVU182 592 0022 0A93 str r3, [sp, #40] 129:Core/Src/main.c **** RCC_OscInitStruct.HSI14CalibrationValue = 16; 593 .loc 1 129 3 is_stmt 1 view .LVU183 129:Core/Src/main.c **** RCC_OscInitStruct.HSI14CalibrationValue = 16; 594 .loc 1 129 41 is_stmt 0 view .LVU184 595 0024 0994 str r4, [sp, #36] 130:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 596 .loc 1 130 3 is_stmt 1 view .LVU185 130:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 597 .loc 1 130 43 is_stmt 0 view .LVU186 598 0026 0B94 str r4, [sp, #44] 131:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 599 .loc 1 131 3 is_stmt 1 view .LVU187 132:Core/Src/main.c **** { 600 .loc 1 132 3 view .LVU188 132:Core/Src/main.c **** { 601 .loc 1 132 7 is_stmt 0 view .LVU189 602 0028 05A8 add r0, sp, #20 603 002a FFF7FEFF bl HAL_RCC_OscConfig 604 .LVL29: 132:Core/Src/main.c **** { 605 .loc 1 132 6 discriminator 1 view .LVU190 606 002e 0028 cmp r0, #0 607 0030 0DD1 bne .L40 ARM GAS /tmp/ccOqAezw.s page 23 139:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1; 608 .loc 1 139 3 is_stmt 1 view .LVU191 139:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1; 609 .loc 1 139 31 is_stmt 0 view .LVU192 610 0032 0723 movs r3, #7 611 0034 0193 str r3, [sp, #4] 141:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 612 .loc 1 141 3 is_stmt 1 view .LVU193 141:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 613 .loc 1 141 34 is_stmt 0 view .LVU194 614 0036 0023 movs r3, #0 615 0038 0293 str r3, [sp, #8] 142:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 616 .loc 1 142 3 is_stmt 1 view .LVU195 142:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 617 .loc 1 142 35 is_stmt 0 view .LVU196 618 003a 0393 str r3, [sp, #12] 143:Core/Src/main.c **** 619 .loc 1 143 3 is_stmt 1 view .LVU197 143:Core/Src/main.c **** 620 .loc 1 143 36 is_stmt 0 view .LVU198 621 003c 0493 str r3, [sp, #16] 145:Core/Src/main.c **** { 622 .loc 1 145 3 is_stmt 1 view .LVU199 145:Core/Src/main.c **** { 623 .loc 1 145 7 is_stmt 0 view .LVU200 624 003e 0021 movs r1, #0 625 0040 01A8 add r0, sp, #4 626 0042 FFF7FEFF bl HAL_RCC_ClockConfig 627 .LVL30: 145:Core/Src/main.c **** { 628 .loc 1 145 6 discriminator 1 view .LVU201 629 0046 0028 cmp r0, #0 630 0048 03D1 bne .L41 149:Core/Src/main.c **** 631 .loc 1 149 1 view .LVU202 632 004a 12B0 add sp, sp, #72 633 @ sp needed 634 004c 10BD pop {r4, pc} 635 .L40: 134:Core/Src/main.c **** } 636 .loc 1 134 5 is_stmt 1 view .LVU203 637 004e FFF7FEFF bl Error_Handler 638 .LVL31: 639 .L41: 147:Core/Src/main.c **** } 640 .loc 1 147 5 view .LVU204 641 0052 FFF7FEFF bl Error_Handler 642 .LVL32: 643 .cfi_endproc 644 .LFE41: 646 .section .text.main,"ax",%progbits 647 .align 1 648 .global main 649 .syntax unified 650 .code 16 651 .thumb_func ARM GAS /tmp/ccOqAezw.s page 24 653 main: 654 .LFB40: 73:Core/Src/main.c **** /* USER CODE BEGIN 1 */ 655 .loc 1 73 1 view -0 656 .cfi_startproc 657 @ Volatile: function does not return. 658 @ args = 0, pretend = 0, frame = 0 659 @ frame_needed = 0, uses_anonymous_args = 0 660 0000 10B5 push {r4, lr} 661 .cfi_def_cfa_offset 8 662 .cfi_offset 4, -8 663 .cfi_offset 14, -4 81:Core/Src/main.c **** 664 .loc 1 81 3 view .LVU206 665 0002 FFF7FEFF bl HAL_Init 666 .LVL33: 88:Core/Src/main.c **** 667 .loc 1 88 3 view .LVU207 668 0006 FFF7FEFF bl SystemClock_Config 669 .LVL34: 95:Core/Src/main.c **** MX_ADC_Init(); 670 .loc 1 95 3 view .LVU208 671 000a FFF7FEFF bl MX_GPIO_Init 672 .LVL35: 96:Core/Src/main.c **** MX_CAN_Init(); 673 .loc 1 96 3 view .LVU209 674 000e FFF7FEFF bl MX_ADC_Init 675 .LVL36: 97:Core/Src/main.c **** MX_TIM2_Init(); 676 .loc 1 97 3 view .LVU210 677 0012 FFF7FEFF bl MX_CAN_Init 678 .LVL37: 98:Core/Src/main.c **** /* USER CODE BEGIN 2 */ 679 .loc 1 98 3 view .LVU211 680 0016 FFF7FEFF bl MX_TIM2_Init 681 .LVL38: 682 .L43: 105:Core/Src/main.c **** { 683 .loc 1 105 3 view .LVU212 110:Core/Src/main.c **** /* USER CODE END 3 */ 684 .loc 1 110 3 view .LVU213 105:Core/Src/main.c **** { 685 .loc 1 105 9 view .LVU214 686 001a FEE7 b .L43 687 .cfi_endproc 688 .LFE40: 690 .global htim2 691 .section .bss.htim2,"aw",%nobits 692 .align 2 695 htim2: 696 0000 00000000 .space 72 696 00000000 696 00000000 696 00000000 696 00000000 697 .global hcan 698 .section .bss.hcan,"aw",%nobits ARM GAS /tmp/ccOqAezw.s page 25 699 .align 2 702 hcan: 703 0000 00000000 .space 40 703 00000000 703 00000000 703 00000000 703 00000000 704 .global hadc 705 .section .bss.hadc,"aw",%nobits 706 .align 2 709 hadc: 710 0000 00000000 .space 64 710 00000000 710 00000000 710 00000000 710 00000000 711 .text 712 .Letext0: 713 .file 3 "/home/chiangni/.config/VSCodium/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/ 714 .file 4 "/home/chiangni/.config/VSCodium/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/ 715 .file 5 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h" 716 .file 6 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h" 717 .file 7 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h" 718 .file 8 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h" 719 .file 9 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h" 720 .file 10 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h" 721 .file 11 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h" 722 .file 12 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h" 723 .file 13 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h" 724 .file 14 "Core/Inc/main.h" 725 .file 15 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h" 726 .file 16 "" ARM GAS /tmp/ccOqAezw.s page 26 DEFINED SYMBOLS *ABS*:00000000 main.c /tmp/ccOqAezw.s:19 .text.MX_GPIO_Init:00000000 $t /tmp/ccOqAezw.s:24 .text.MX_GPIO_Init:00000000 MX_GPIO_Init /tmp/ccOqAezw.s:92 .text.MX_GPIO_Init:00000040 $d /tmp/ccOqAezw.s:97 .text.Error_Handler:00000000 $t /tmp/ccOqAezw.s:103 .text.Error_Handler:00000000 Error_Handler /tmp/ccOqAezw.s:135 .text.MX_ADC_Init:00000000 $t /tmp/ccOqAezw.s:140 .text.MX_ADC_Init:00000000 MX_ADC_Init /tmp/ccOqAezw.s:271 .text.MX_ADC_Init:00000080 $d /tmp/ccOqAezw.s:709 .bss.hadc:00000000 hadc /tmp/ccOqAezw.s:277 .text.MX_CAN_Init:00000000 $t /tmp/ccOqAezw.s:282 .text.MX_CAN_Init:00000000 MX_CAN_Init /tmp/ccOqAezw.s:349 .text.MX_CAN_Init:00000030 $d /tmp/ccOqAezw.s:702 .bss.hcan:00000000 hcan /tmp/ccOqAezw.s:355 .text.MX_TIM2_Init:00000000 $t /tmp/ccOqAezw.s:360 .text.MX_TIM2_Init:00000000 MX_TIM2_Init /tmp/ccOqAezw.s:544 .text.MX_TIM2_Init:000000cc $d /tmp/ccOqAezw.s:695 .bss.htim2:00000000 htim2 /tmp/ccOqAezw.s:549 .text.SystemClock_Config:00000000 $t /tmp/ccOqAezw.s:555 .text.SystemClock_Config:00000000 SystemClock_Config /tmp/ccOqAezw.s:647 .text.main:00000000 $t /tmp/ccOqAezw.s:653 .text.main:00000000 main /tmp/ccOqAezw.s:692 .bss.htim2:00000000 $d /tmp/ccOqAezw.s:699 .bss.hcan:00000000 $d /tmp/ccOqAezw.s:706 .bss.hadc:00000000 $d UNDEFINED SYMBOLS memset HAL_ADC_Init HAL_ADC_ConfigChannel HAL_CAN_Init HAL_TIM_Base_Init HAL_TIM_ConfigClockSource HAL_TIM_PWM_Init HAL_TIMEx_MasterConfigSynchronization HAL_TIM_PWM_ConfigChannel HAL_TIM_MspPostInit HAL_RCC_OscConfig HAL_RCC_ClockConfig HAL_Init