292 lines
14 KiB
Plaintext
292 lines
14 KiB
Plaintext
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ARM GAS /tmp/ccDtjY0E.s page 1
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1 .cpu cortex-m0
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2 .arch armv6s-m
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3 .fpu softvfp
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4 .eabi_attribute 20, 1
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5 .eabi_attribute 21, 1
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6 .eabi_attribute 23, 3
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7 .eabi_attribute 24, 1
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8 .eabi_attribute 25, 1
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9 .eabi_attribute 26, 1
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10 .eabi_attribute 30, 1
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11 .eabi_attribute 34, 0
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12 .eabi_attribute 18, 4
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13 .file "stm32f0xx_it.c"
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14 .text
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15 .Ltext0:
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16 .cfi_sections .debug_frame
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17 .file 1 "Core/Src/stm32f0xx_it.c"
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18 .section .text.NMI_Handler,"ax",%progbits
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19 .align 1
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20 .global NMI_Handler
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21 .syntax unified
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22 .code 16
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23 .thumb_func
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25 NMI_Handler:
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26 .LFB40:
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1:Core/Src/stm32f0xx_it.c **** /* USER CODE BEGIN Header */
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2:Core/Src/stm32f0xx_it.c **** /**
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3:Core/Src/stm32f0xx_it.c **** ******************************************************************************
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4:Core/Src/stm32f0xx_it.c **** * @file stm32f0xx_it.c
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5:Core/Src/stm32f0xx_it.c **** * @brief Interrupt Service Routines.
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6:Core/Src/stm32f0xx_it.c **** ******************************************************************************
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7:Core/Src/stm32f0xx_it.c **** * @attention
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8:Core/Src/stm32f0xx_it.c **** *
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9:Core/Src/stm32f0xx_it.c **** * Copyright (c) 2024 STMicroelectronics.
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10:Core/Src/stm32f0xx_it.c **** * All rights reserved.
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11:Core/Src/stm32f0xx_it.c **** *
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12:Core/Src/stm32f0xx_it.c **** * This software is licensed under terms that can be found in the LICENSE file
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13:Core/Src/stm32f0xx_it.c **** * in the root directory of this software component.
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14:Core/Src/stm32f0xx_it.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
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15:Core/Src/stm32f0xx_it.c **** *
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16:Core/Src/stm32f0xx_it.c **** ******************************************************************************
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17:Core/Src/stm32f0xx_it.c **** */
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18:Core/Src/stm32f0xx_it.c **** /* USER CODE END Header */
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19:Core/Src/stm32f0xx_it.c ****
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20:Core/Src/stm32f0xx_it.c **** /* Includes ------------------------------------------------------------------*/
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21:Core/Src/stm32f0xx_it.c **** #include "main.h"
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22:Core/Src/stm32f0xx_it.c **** #include "stm32f0xx_it.h"
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23:Core/Src/stm32f0xx_it.c **** /* Private includes ----------------------------------------------------------*/
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24:Core/Src/stm32f0xx_it.c **** /* USER CODE BEGIN Includes */
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25:Core/Src/stm32f0xx_it.c **** /* USER CODE END Includes */
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26:Core/Src/stm32f0xx_it.c ****
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27:Core/Src/stm32f0xx_it.c **** /* Private typedef -----------------------------------------------------------*/
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28:Core/Src/stm32f0xx_it.c **** /* USER CODE BEGIN TD */
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29:Core/Src/stm32f0xx_it.c ****
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30:Core/Src/stm32f0xx_it.c **** /* USER CODE END TD */
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31:Core/Src/stm32f0xx_it.c ****
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32:Core/Src/stm32f0xx_it.c **** /* Private define ------------------------------------------------------------*/
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ARM GAS /tmp/ccDtjY0E.s page 2
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33:Core/Src/stm32f0xx_it.c **** /* USER CODE BEGIN PD */
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34:Core/Src/stm32f0xx_it.c ****
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35:Core/Src/stm32f0xx_it.c **** /* USER CODE END PD */
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36:Core/Src/stm32f0xx_it.c ****
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37:Core/Src/stm32f0xx_it.c **** /* Private macro -------------------------------------------------------------*/
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38:Core/Src/stm32f0xx_it.c **** /* USER CODE BEGIN PM */
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39:Core/Src/stm32f0xx_it.c ****
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40:Core/Src/stm32f0xx_it.c **** /* USER CODE END PM */
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41:Core/Src/stm32f0xx_it.c ****
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42:Core/Src/stm32f0xx_it.c **** /* Private variables ---------------------------------------------------------*/
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43:Core/Src/stm32f0xx_it.c **** /* USER CODE BEGIN PV */
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44:Core/Src/stm32f0xx_it.c ****
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45:Core/Src/stm32f0xx_it.c **** /* USER CODE END PV */
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46:Core/Src/stm32f0xx_it.c ****
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47:Core/Src/stm32f0xx_it.c **** /* Private function prototypes -----------------------------------------------*/
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48:Core/Src/stm32f0xx_it.c **** /* USER CODE BEGIN PFP */
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49:Core/Src/stm32f0xx_it.c ****
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50:Core/Src/stm32f0xx_it.c **** /* USER CODE END PFP */
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51:Core/Src/stm32f0xx_it.c ****
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52:Core/Src/stm32f0xx_it.c **** /* Private user code ---------------------------------------------------------*/
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53:Core/Src/stm32f0xx_it.c **** /* USER CODE BEGIN 0 */
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54:Core/Src/stm32f0xx_it.c ****
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55:Core/Src/stm32f0xx_it.c **** /* USER CODE END 0 */
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56:Core/Src/stm32f0xx_it.c ****
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57:Core/Src/stm32f0xx_it.c **** /* External variables --------------------------------------------------------*/
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58:Core/Src/stm32f0xx_it.c ****
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59:Core/Src/stm32f0xx_it.c **** /* USER CODE BEGIN EV */
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60:Core/Src/stm32f0xx_it.c ****
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61:Core/Src/stm32f0xx_it.c **** /* USER CODE END EV */
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62:Core/Src/stm32f0xx_it.c ****
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63:Core/Src/stm32f0xx_it.c **** /******************************************************************************/
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64:Core/Src/stm32f0xx_it.c **** /* Cortex-M0 Processor Interruption and Exception Handlers */
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65:Core/Src/stm32f0xx_it.c **** /******************************************************************************/
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66:Core/Src/stm32f0xx_it.c **** /**
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67:Core/Src/stm32f0xx_it.c **** * @brief This function handles Non maskable interrupt.
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68:Core/Src/stm32f0xx_it.c **** */
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69:Core/Src/stm32f0xx_it.c **** void NMI_Handler(void)
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70:Core/Src/stm32f0xx_it.c **** {
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27 .loc 1 70 1 view -0
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28 .cfi_startproc
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29 @ Volatile: function does not return.
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30 @ args = 0, pretend = 0, frame = 0
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31 @ frame_needed = 0, uses_anonymous_args = 0
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32 @ link register save eliminated.
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33 .L2:
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71:Core/Src/stm32f0xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
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72:Core/Src/stm32f0xx_it.c ****
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73:Core/Src/stm32f0xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 0 */
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74:Core/Src/stm32f0xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
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75:Core/Src/stm32f0xx_it.c **** while (1)
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34 .loc 1 75 3 view .LVU1
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76:Core/Src/stm32f0xx_it.c **** {
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77:Core/Src/stm32f0xx_it.c **** }
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35 .loc 1 77 3 view .LVU2
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75:Core/Src/stm32f0xx_it.c **** {
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36 .loc 1 75 9 view .LVU3
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37 0000 FEE7 b .L2
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ARM GAS /tmp/ccDtjY0E.s page 3
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38 .cfi_endproc
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39 .LFE40:
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41 .section .text.HardFault_Handler,"ax",%progbits
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42 .align 1
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43 .global HardFault_Handler
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44 .syntax unified
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45 .code 16
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46 .thumb_func
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48 HardFault_Handler:
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49 .LFB41:
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78:Core/Src/stm32f0xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 1 */
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79:Core/Src/stm32f0xx_it.c **** }
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80:Core/Src/stm32f0xx_it.c ****
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81:Core/Src/stm32f0xx_it.c **** /**
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82:Core/Src/stm32f0xx_it.c **** * @brief This function handles Hard fault interrupt.
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83:Core/Src/stm32f0xx_it.c **** */
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84:Core/Src/stm32f0xx_it.c **** void HardFault_Handler(void)
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85:Core/Src/stm32f0xx_it.c **** {
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50 .loc 1 85 1 view -0
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51 .cfi_startproc
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52 @ Volatile: function does not return.
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53 @ args = 0, pretend = 0, frame = 0
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54 @ frame_needed = 0, uses_anonymous_args = 0
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55 @ link register save eliminated.
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56 .L4:
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86:Core/Src/stm32f0xx_it.c **** /* USER CODE BEGIN HardFault_IRQn 0 */
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87:Core/Src/stm32f0xx_it.c ****
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88:Core/Src/stm32f0xx_it.c **** /* USER CODE END HardFault_IRQn 0 */
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89:Core/Src/stm32f0xx_it.c **** while (1)
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57 .loc 1 89 3 view .LVU5
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90:Core/Src/stm32f0xx_it.c **** {
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91:Core/Src/stm32f0xx_it.c **** /* USER CODE BEGIN W1_HardFault_IRQn 0 */
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92:Core/Src/stm32f0xx_it.c **** /* USER CODE END W1_HardFault_IRQn 0 */
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93:Core/Src/stm32f0xx_it.c **** }
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58 .loc 1 93 3 view .LVU6
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89:Core/Src/stm32f0xx_it.c **** {
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59 .loc 1 89 9 view .LVU7
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60 0000 FEE7 b .L4
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61 .cfi_endproc
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62 .LFE41:
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64 .section .text.SVC_Handler,"ax",%progbits
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65 .align 1
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66 .global SVC_Handler
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67 .syntax unified
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68 .code 16
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69 .thumb_func
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71 SVC_Handler:
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72 .LFB42:
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94:Core/Src/stm32f0xx_it.c **** }
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95:Core/Src/stm32f0xx_it.c ****
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96:Core/Src/stm32f0xx_it.c **** /**
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97:Core/Src/stm32f0xx_it.c **** * @brief This function handles System service call via SWI instruction.
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98:Core/Src/stm32f0xx_it.c **** */
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99:Core/Src/stm32f0xx_it.c **** void SVC_Handler(void)
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100:Core/Src/stm32f0xx_it.c **** {
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73 .loc 1 100 1 view -0
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74 .cfi_startproc
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ARM GAS /tmp/ccDtjY0E.s page 4
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75 @ args = 0, pretend = 0, frame = 0
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76 @ frame_needed = 0, uses_anonymous_args = 0
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77 @ link register save eliminated.
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101:Core/Src/stm32f0xx_it.c **** /* USER CODE BEGIN SVC_IRQn 0 */
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102:Core/Src/stm32f0xx_it.c ****
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103:Core/Src/stm32f0xx_it.c **** /* USER CODE END SVC_IRQn 0 */
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104:Core/Src/stm32f0xx_it.c **** /* USER CODE BEGIN SVC_IRQn 1 */
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105:Core/Src/stm32f0xx_it.c ****
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106:Core/Src/stm32f0xx_it.c **** /* USER CODE END SVC_IRQn 1 */
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107:Core/Src/stm32f0xx_it.c **** }
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78 .loc 1 107 1 view .LVU9
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79 @ sp needed
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80 0000 7047 bx lr
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81 .cfi_endproc
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82 .LFE42:
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84 .section .text.PendSV_Handler,"ax",%progbits
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85 .align 1
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86 .global PendSV_Handler
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87 .syntax unified
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88 .code 16
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89 .thumb_func
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91 PendSV_Handler:
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92 .LFB43:
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108:Core/Src/stm32f0xx_it.c ****
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109:Core/Src/stm32f0xx_it.c **** /**
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110:Core/Src/stm32f0xx_it.c **** * @brief This function handles Pendable request for system service.
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111:Core/Src/stm32f0xx_it.c **** */
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112:Core/Src/stm32f0xx_it.c **** void PendSV_Handler(void)
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113:Core/Src/stm32f0xx_it.c **** {
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93 .loc 1 113 1 view -0
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94 .cfi_startproc
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95 @ args = 0, pretend = 0, frame = 0
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96 @ frame_needed = 0, uses_anonymous_args = 0
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97 @ link register save eliminated.
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114:Core/Src/stm32f0xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 0 */
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115:Core/Src/stm32f0xx_it.c ****
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116:Core/Src/stm32f0xx_it.c **** /* USER CODE END PendSV_IRQn 0 */
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117:Core/Src/stm32f0xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 1 */
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118:Core/Src/stm32f0xx_it.c ****
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119:Core/Src/stm32f0xx_it.c **** /* USER CODE END PendSV_IRQn 1 */
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120:Core/Src/stm32f0xx_it.c **** }
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98 .loc 1 120 1 view .LVU11
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99 @ sp needed
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100 0000 7047 bx lr
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101 .cfi_endproc
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102 .LFE43:
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104 .section .text.SysTick_Handler,"ax",%progbits
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105 .align 1
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106 .global SysTick_Handler
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107 .syntax unified
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108 .code 16
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109 .thumb_func
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111 SysTick_Handler:
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112 .LFB44:
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121:Core/Src/stm32f0xx_it.c ****
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122:Core/Src/stm32f0xx_it.c **** /**
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123:Core/Src/stm32f0xx_it.c **** * @brief This function handles System tick timer.
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ARM GAS /tmp/ccDtjY0E.s page 5
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124:Core/Src/stm32f0xx_it.c **** */
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125:Core/Src/stm32f0xx_it.c **** void SysTick_Handler(void)
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126:Core/Src/stm32f0xx_it.c **** {
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113 .loc 1 126 1 view -0
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114 .cfi_startproc
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115 @ args = 0, pretend = 0, frame = 0
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116 @ frame_needed = 0, uses_anonymous_args = 0
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117 0000 10B5 push {r4, lr}
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118 .cfi_def_cfa_offset 8
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119 .cfi_offset 4, -8
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120 .cfi_offset 14, -4
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127:Core/Src/stm32f0xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 0 */
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128:Core/Src/stm32f0xx_it.c ****
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129:Core/Src/stm32f0xx_it.c **** /* USER CODE END SysTick_IRQn 0 */
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130:Core/Src/stm32f0xx_it.c **** HAL_IncTick();
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121 .loc 1 130 3 view .LVU13
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122 0002 FFF7FEFF bl HAL_IncTick
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123 .LVL0:
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131:Core/Src/stm32f0xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 1 */
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132:Core/Src/stm32f0xx_it.c ****
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133:Core/Src/stm32f0xx_it.c **** /* USER CODE END SysTick_IRQn 1 */
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134:Core/Src/stm32f0xx_it.c **** }
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124 .loc 1 134 1 is_stmt 0 view .LVU14
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125 @ sp needed
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126 0006 10BD pop {r4, pc}
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127 .cfi_endproc
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128 .LFE44:
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130 .text
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131 .Letext0:
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132 .file 2 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h"
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ARM GAS /tmp/ccDtjY0E.s page 6
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DEFINED SYMBOLS
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*ABS*:00000000 stm32f0xx_it.c
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/tmp/ccDtjY0E.s:19 .text.NMI_Handler:00000000 $t
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/tmp/ccDtjY0E.s:25 .text.NMI_Handler:00000000 NMI_Handler
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/tmp/ccDtjY0E.s:42 .text.HardFault_Handler:00000000 $t
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/tmp/ccDtjY0E.s:48 .text.HardFault_Handler:00000000 HardFault_Handler
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/tmp/ccDtjY0E.s:65 .text.SVC_Handler:00000000 $t
|
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/tmp/ccDtjY0E.s:71 .text.SVC_Handler:00000000 SVC_Handler
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/tmp/ccDtjY0E.s:85 .text.PendSV_Handler:00000000 $t
|
|||
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/tmp/ccDtjY0E.s:91 .text.PendSV_Handler:00000000 PendSV_Handler
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/tmp/ccDtjY0E.s:105 .text.SysTick_Handler:00000000 $t
|
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/tmp/ccDtjY0E.s:111 .text.SysTick_Handler:00000000 SysTick_Handler
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UNDEFINED SYMBOLS
|
|||
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HAL_IncTick
|