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SLS/Software/build/stm32f0xx_hal_msp.lst

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test commit, update gitignore
2024-11-03 13:02:53 +01:00
ARM GAS /tmp/ccP9ub9v.s page 1
1 .cpu cortex-m0
2 .arch armv6s-m
3 .fpu softvfp
4 .eabi_attribute 20, 1
5 .eabi_attribute 21, 1
6 .eabi_attribute 23, 3
7 .eabi_attribute 24, 1
8 .eabi_attribute 25, 1
9 .eabi_attribute 26, 1
10 .eabi_attribute 30, 1
11 .eabi_attribute 34, 0
12 .eabi_attribute 18, 4
13 .file "stm32f0xx_hal_msp.c"
14 .text
15 .Ltext0:
16 .cfi_sections .debug_frame
17 .file 1 "Core/Src/stm32f0xx_hal_msp.c"
18 .section .text.HAL_MspInit,"ax",%progbits
19 .align 1
20 .global HAL_MspInit
21 .syntax unified
22 .code 16
23 .thumb_func
25 HAL_MspInit:
26 .LFB40:
1:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN Header */
2:Core/Src/stm32f0xx_hal_msp.c **** /**
3:Core/Src/stm32f0xx_hal_msp.c **** ******************************************************************************
4:Core/Src/stm32f0xx_hal_msp.c **** * @file stm32f0xx_hal_msp.c
5:Core/Src/stm32f0xx_hal_msp.c **** * @brief This file provides code for the MSP Initialization
6:Core/Src/stm32f0xx_hal_msp.c **** * and de-Initialization codes.
7:Core/Src/stm32f0xx_hal_msp.c **** ******************************************************************************
8:Core/Src/stm32f0xx_hal_msp.c **** * @attention
9:Core/Src/stm32f0xx_hal_msp.c **** *
10:Core/Src/stm32f0xx_hal_msp.c **** * Copyright (c) 2024 STMicroelectronics.
11:Core/Src/stm32f0xx_hal_msp.c **** * All rights reserved.
12:Core/Src/stm32f0xx_hal_msp.c **** *
13:Core/Src/stm32f0xx_hal_msp.c **** * This software is licensed under terms that can be found in the LICENSE file
14:Core/Src/stm32f0xx_hal_msp.c **** * in the root directory of this software component.
15:Core/Src/stm32f0xx_hal_msp.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
16:Core/Src/stm32f0xx_hal_msp.c **** *
17:Core/Src/stm32f0xx_hal_msp.c **** ******************************************************************************
18:Core/Src/stm32f0xx_hal_msp.c **** */
19:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END Header */
20:Core/Src/stm32f0xx_hal_msp.c ****
21:Core/Src/stm32f0xx_hal_msp.c **** /* Includes ------------------------------------------------------------------*/
22:Core/Src/stm32f0xx_hal_msp.c **** #include "main.h"
23:Core/Src/stm32f0xx_hal_msp.c ****
24:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN Includes */
25:Core/Src/stm32f0xx_hal_msp.c ****
26:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END Includes */
27:Core/Src/stm32f0xx_hal_msp.c ****
28:Core/Src/stm32f0xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/
29:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN TD */
30:Core/Src/stm32f0xx_hal_msp.c ****
31:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END TD */
32:Core/Src/stm32f0xx_hal_msp.c ****
ARM GAS /tmp/ccP9ub9v.s page 2
33:Core/Src/stm32f0xx_hal_msp.c **** /* Private define ------------------------------------------------------------*/
34:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN Define */
35:Core/Src/stm32f0xx_hal_msp.c ****
36:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END Define */
37:Core/Src/stm32f0xx_hal_msp.c ****
38:Core/Src/stm32f0xx_hal_msp.c **** /* Private macro -------------------------------------------------------------*/
39:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN Macro */
40:Core/Src/stm32f0xx_hal_msp.c ****
41:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END Macro */
42:Core/Src/stm32f0xx_hal_msp.c ****
43:Core/Src/stm32f0xx_hal_msp.c **** /* Private variables ---------------------------------------------------------*/
44:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN PV */
45:Core/Src/stm32f0xx_hal_msp.c ****
46:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END PV */
47:Core/Src/stm32f0xx_hal_msp.c ****
48:Core/Src/stm32f0xx_hal_msp.c **** /* Private function prototypes -----------------------------------------------*/
49:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN PFP */
50:Core/Src/stm32f0xx_hal_msp.c ****
51:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END PFP */
52:Core/Src/stm32f0xx_hal_msp.c ****
53:Core/Src/stm32f0xx_hal_msp.c **** /* External functions --------------------------------------------------------*/
54:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN ExternalFunctions */
55:Core/Src/stm32f0xx_hal_msp.c ****
56:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END ExternalFunctions */
57:Core/Src/stm32f0xx_hal_msp.c ****
58:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN 0 */
59:Core/Src/stm32f0xx_hal_msp.c ****
60:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END 0 */
61:Core/Src/stm32f0xx_hal_msp.c ****
62:Core/Src/stm32f0xx_hal_msp.c **** void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
63:Core/Src/stm32f0xx_hal_msp.c **** /**
64:Core/Src/stm32f0xx_hal_msp.c **** * Initializes the Global MSP.
65:Core/Src/stm32f0xx_hal_msp.c **** */
66:Core/Src/stm32f0xx_hal_msp.c **** void HAL_MspInit(void)
67:Core/Src/stm32f0xx_hal_msp.c **** {
27 .loc 1 67 1 view -0
28 .cfi_startproc
29 @ args = 0, pretend = 0, frame = 8
30 @ frame_needed = 0, uses_anonymous_args = 0
31 @ link register save eliminated.
32 0000 82B0 sub sp, sp, #8
33 .cfi_def_cfa_offset 8
68:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN MspInit 0 */
69:Core/Src/stm32f0xx_hal_msp.c ****
70:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END MspInit 0 */
71:Core/Src/stm32f0xx_hal_msp.c ****
72:Core/Src/stm32f0xx_hal_msp.c **** __HAL_RCC_SYSCFG_CLK_ENABLE();
34 .loc 1 72 3 view .LVU1
35 .LBB2:
36 .loc 1 72 3 view .LVU2
37 .loc 1 72 3 view .LVU3
38 0002 0A4B ldr r3, .L2
39 0004 9969 ldr r1, [r3, #24]
40 0006 0122 movs r2, #1
41 0008 1143 orrs r1, r2
42 000a 9961 str r1, [r3, #24]
43 .loc 1 72 3 view .LVU4
ARM GAS /tmp/ccP9ub9v.s page 3
44 000c 9969 ldr r1, [r3, #24]
45 000e 0A40 ands r2, r1
46 0010 0092 str r2, [sp]
47 .loc 1 72 3 view .LVU5
48 0012 009A ldr r2, [sp]
49 .LBE2:
50 .loc 1 72 3 view .LVU6
73:Core/Src/stm32f0xx_hal_msp.c **** __HAL_RCC_PWR_CLK_ENABLE();
51 .loc 1 73 3 view .LVU7
52 .LBB3:
53 .loc 1 73 3 view .LVU8
54 .loc 1 73 3 view .LVU9
55 0014 DA69 ldr r2, [r3, #28]
56 0016 8021 movs r1, #128
57 0018 4905 lsls r1, r1, #21
58 001a 0A43 orrs r2, r1
59 001c DA61 str r2, [r3, #28]
60 .loc 1 73 3 view .LVU10
61 001e DB69 ldr r3, [r3, #28]
62 0020 0B40 ands r3, r1
63 0022 0193 str r3, [sp, #4]
64 .loc 1 73 3 view .LVU11
65 0024 019B ldr r3, [sp, #4]
66 .LBE3:
67 .loc 1 73 3 view .LVU12
74:Core/Src/stm32f0xx_hal_msp.c ****
75:Core/Src/stm32f0xx_hal_msp.c **** /* System interrupt init*/
76:Core/Src/stm32f0xx_hal_msp.c ****
77:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN MspInit 1 */
78:Core/Src/stm32f0xx_hal_msp.c ****
79:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END MspInit 1 */
80:Core/Src/stm32f0xx_hal_msp.c **** }
68 .loc 1 80 1 is_stmt 0 view .LVU13
69 0026 02B0 add sp, sp, #8
70 @ sp needed
71 0028 7047 bx lr
72 .L3:
73 002a C046 .align 2
74 .L2:
75 002c 00100240 .word 1073876992
76 .cfi_endproc
77 .LFE40:
79 .section .text.HAL_ADC_MspInit,"ax",%progbits
80 .align 1
81 .global HAL_ADC_MspInit
82 .syntax unified
83 .code 16
84 .thumb_func
86 HAL_ADC_MspInit:
87 .LVL0:
88 .LFB41:
81:Core/Src/stm32f0xx_hal_msp.c ****
82:Core/Src/stm32f0xx_hal_msp.c **** /**
83:Core/Src/stm32f0xx_hal_msp.c **** * @brief ADC MSP Initialization
84:Core/Src/stm32f0xx_hal_msp.c **** * This function configures the hardware resources used in this example
85:Core/Src/stm32f0xx_hal_msp.c **** * @param hadc: ADC handle pointer
86:Core/Src/stm32f0xx_hal_msp.c **** * @retval None
ARM GAS /tmp/ccP9ub9v.s page 4
87:Core/Src/stm32f0xx_hal_msp.c **** */
88:Core/Src/stm32f0xx_hal_msp.c **** void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
89:Core/Src/stm32f0xx_hal_msp.c **** {
89 .loc 1 89 1 is_stmt 1 view -0
90 .cfi_startproc
91 @ args = 0, pretend = 0, frame = 32
92 @ frame_needed = 0, uses_anonymous_args = 0
93 .loc 1 89 1 is_stmt 0 view .LVU15
94 0000 10B5 push {r4, lr}
95 .cfi_def_cfa_offset 8
96 .cfi_offset 4, -8
97 .cfi_offset 14, -4
98 0002 88B0 sub sp, sp, #32
99 .cfi_def_cfa_offset 40
100 0004 0400 movs r4, r0
90:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
101 .loc 1 90 3 is_stmt 1 view .LVU16
102 .loc 1 90 20 is_stmt 0 view .LVU17
103 0006 1422 movs r2, #20
104 0008 0021 movs r1, #0
105 000a 03A8 add r0, sp, #12
106 .LVL1:
107 .loc 1 90 20 view .LVU18
108 000c FFF7FEFF bl memset
109 .LVL2:
91:Core/Src/stm32f0xx_hal_msp.c **** if(hadc->Instance==ADC1)
110 .loc 1 91 3 is_stmt 1 view .LVU19
111 .loc 1 91 10 is_stmt 0 view .LVU20
112 0010 2268 ldr r2, [r4]
113 .loc 1 91 5 view .LVU21
114 0012 104B ldr r3, .L7
115 0014 9A42 cmp r2, r3
116 0016 01D0 beq .L6
117 .L4:
92:Core/Src/stm32f0xx_hal_msp.c **** {
93:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspInit 0 */
94:Core/Src/stm32f0xx_hal_msp.c ****
95:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END ADC1_MspInit 0 */
96:Core/Src/stm32f0xx_hal_msp.c **** /* Peripheral clock enable */
97:Core/Src/stm32f0xx_hal_msp.c **** __HAL_RCC_ADC1_CLK_ENABLE();
98:Core/Src/stm32f0xx_hal_msp.c ****
99:Core/Src/stm32f0xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
100:Core/Src/stm32f0xx_hal_msp.c **** /**ADC GPIO Configuration
101:Core/Src/stm32f0xx_hal_msp.c **** PA0 ------> ADC_IN0
102:Core/Src/stm32f0xx_hal_msp.c **** PA1 ------> ADC_IN1
103:Core/Src/stm32f0xx_hal_msp.c **** */
104:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
105:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
106:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
107:Core/Src/stm32f0xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
108:Core/Src/stm32f0xx_hal_msp.c ****
109:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspInit 1 */
110:Core/Src/stm32f0xx_hal_msp.c ****
111:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END ADC1_MspInit 1 */
112:Core/Src/stm32f0xx_hal_msp.c **** }
113:Core/Src/stm32f0xx_hal_msp.c ****
114:Core/Src/stm32f0xx_hal_msp.c **** }
ARM GAS /tmp/ccP9ub9v.s page 5
118 .loc 1 114 1 view .LVU22
119 0018 08B0 add sp, sp, #32
120 @ sp needed
121 .LVL3:
122 .loc 1 114 1 view .LVU23
123 001a 10BD pop {r4, pc}
124 .LVL4:
125 .L6:
97:Core/Src/stm32f0xx_hal_msp.c ****
126 .loc 1 97 5 is_stmt 1 view .LVU24
127 .LBB4:
97:Core/Src/stm32f0xx_hal_msp.c ****
128 .loc 1 97 5 view .LVU25
97:Core/Src/stm32f0xx_hal_msp.c ****
129 .loc 1 97 5 view .LVU26
130 001c 0E4B ldr r3, .L7+4
131 001e 9A69 ldr r2, [r3, #24]
132 0020 8021 movs r1, #128
133 0022 8900 lsls r1, r1, #2
134 0024 0A43 orrs r2, r1
135 0026 9A61 str r2, [r3, #24]
97:Core/Src/stm32f0xx_hal_msp.c ****
136 .loc 1 97 5 view .LVU27
137 0028 9A69 ldr r2, [r3, #24]
138 002a 0A40 ands r2, r1
139 002c 0192 str r2, [sp, #4]
97:Core/Src/stm32f0xx_hal_msp.c ****
140 .loc 1 97 5 view .LVU28
141 002e 019A ldr r2, [sp, #4]
142 .LBE4:
97:Core/Src/stm32f0xx_hal_msp.c ****
143 .loc 1 97 5 view .LVU29
99:Core/Src/stm32f0xx_hal_msp.c **** /**ADC GPIO Configuration
144 .loc 1 99 5 view .LVU30
145 .LBB5:
99:Core/Src/stm32f0xx_hal_msp.c **** /**ADC GPIO Configuration
146 .loc 1 99 5 view .LVU31
99:Core/Src/stm32f0xx_hal_msp.c **** /**ADC GPIO Configuration
147 .loc 1 99 5 view .LVU32
148 0030 5A69 ldr r2, [r3, #20]
149 0032 8021 movs r1, #128
150 0034 8902 lsls r1, r1, #10
151 0036 0A43 orrs r2, r1
152 0038 5A61 str r2, [r3, #20]
99:Core/Src/stm32f0xx_hal_msp.c **** /**ADC GPIO Configuration
153 .loc 1 99 5 view .LVU33
154 003a 5B69 ldr r3, [r3, #20]
155 003c 0B40 ands r3, r1
156 003e 0293 str r3, [sp, #8]
99:Core/Src/stm32f0xx_hal_msp.c **** /**ADC GPIO Configuration
157 .loc 1 99 5 view .LVU34
158 0040 029B ldr r3, [sp, #8]
159 .LBE5:
99:Core/Src/stm32f0xx_hal_msp.c **** /**ADC GPIO Configuration
160 .loc 1 99 5 view .LVU35
104:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
161 .loc 1 104 5 view .LVU36
ARM GAS /tmp/ccP9ub9v.s page 6
104:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
162 .loc 1 104 25 is_stmt 0 view .LVU37
163 0042 0323 movs r3, #3
164 0044 0393 str r3, [sp, #12]
105:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
165 .loc 1 105 5 is_stmt 1 view .LVU38
105:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
166 .loc 1 105 26 is_stmt 0 view .LVU39
167 0046 0493 str r3, [sp, #16]
106:Core/Src/stm32f0xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
168 .loc 1 106 5 is_stmt 1 view .LVU40
107:Core/Src/stm32f0xx_hal_msp.c ****
169 .loc 1 107 5 view .LVU41
170 0048 9020 movs r0, #144
171 004a 03A9 add r1, sp, #12
172 004c C005 lsls r0, r0, #23
173 004e FFF7FEFF bl HAL_GPIO_Init
174 .LVL5:
175 .loc 1 114 1 is_stmt 0 view .LVU42
176 0052 E1E7 b .L4
177 .L8:
178 .align 2
179 .L7:
180 0054 00240140 .word 1073816576
181 0058 00100240 .word 1073876992
182 .cfi_endproc
183 .LFE41:
185 .section .text.HAL_ADC_MspDeInit,"ax",%progbits
186 .align 1
187 .global HAL_ADC_MspDeInit
188 .syntax unified
189 .code 16
190 .thumb_func
192 HAL_ADC_MspDeInit:
193 .LVL6:
194 .LFB42:
115:Core/Src/stm32f0xx_hal_msp.c ****
116:Core/Src/stm32f0xx_hal_msp.c **** /**
117:Core/Src/stm32f0xx_hal_msp.c **** * @brief ADC MSP De-Initialization
118:Core/Src/stm32f0xx_hal_msp.c **** * This function freeze the hardware resources used in this example
119:Core/Src/stm32f0xx_hal_msp.c **** * @param hadc: ADC handle pointer
120:Core/Src/stm32f0xx_hal_msp.c **** * @retval None
121:Core/Src/stm32f0xx_hal_msp.c **** */
122:Core/Src/stm32f0xx_hal_msp.c **** void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
123:Core/Src/stm32f0xx_hal_msp.c **** {
195 .loc 1 123 1 is_stmt 1 view -0
196 .cfi_startproc
197 @ args = 0, pretend = 0, frame = 0
198 @ frame_needed = 0, uses_anonymous_args = 0
199 .loc 1 123 1 is_stmt 0 view .LVU44
200 0000 10B5 push {r4, lr}
201 .cfi_def_cfa_offset 8
202 .cfi_offset 4, -8
203 .cfi_offset 14, -4
124:Core/Src/stm32f0xx_hal_msp.c **** if(hadc->Instance==ADC1)
204 .loc 1 124 3 is_stmt 1 view .LVU45
205 .loc 1 124 10 is_stmt 0 view .LVU46
ARM GAS /tmp/ccP9ub9v.s page 7
206 0002 0268 ldr r2, [r0]
207 .loc 1 124 5 view .LVU47
208 0004 074B ldr r3, .L12
209 0006 9A42 cmp r2, r3
210 0008 00D0 beq .L11
211 .LVL7:
212 .L9:
125:Core/Src/stm32f0xx_hal_msp.c **** {
126:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspDeInit 0 */
127:Core/Src/stm32f0xx_hal_msp.c ****
128:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END ADC1_MspDeInit 0 */
129:Core/Src/stm32f0xx_hal_msp.c **** /* Peripheral clock disable */
130:Core/Src/stm32f0xx_hal_msp.c **** __HAL_RCC_ADC1_CLK_DISABLE();
131:Core/Src/stm32f0xx_hal_msp.c ****
132:Core/Src/stm32f0xx_hal_msp.c **** /**ADC GPIO Configuration
133:Core/Src/stm32f0xx_hal_msp.c **** PA0 ------> ADC_IN0
134:Core/Src/stm32f0xx_hal_msp.c **** PA1 ------> ADC_IN1
135:Core/Src/stm32f0xx_hal_msp.c **** */
136:Core/Src/stm32f0xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0|GPIO_PIN_1);
137:Core/Src/stm32f0xx_hal_msp.c ****
138:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspDeInit 1 */
139:Core/Src/stm32f0xx_hal_msp.c ****
140:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END ADC1_MspDeInit 1 */
141:Core/Src/stm32f0xx_hal_msp.c **** }
142:Core/Src/stm32f0xx_hal_msp.c ****
143:Core/Src/stm32f0xx_hal_msp.c **** }
213 .loc 1 143 1 view .LVU48
214 @ sp needed
215 000a 10BD pop {r4, pc}
216 .LVL8:
217 .L11:
130:Core/Src/stm32f0xx_hal_msp.c ****
218 .loc 1 130 5 is_stmt 1 view .LVU49
219 000c 064A ldr r2, .L12+4
220 000e 9369 ldr r3, [r2, #24]
221 0010 0649 ldr r1, .L12+8
222 0012 0B40 ands r3, r1
223 0014 9361 str r3, [r2, #24]
136:Core/Src/stm32f0xx_hal_msp.c ****
224 .loc 1 136 5 view .LVU50
225 0016 9020 movs r0, #144
226 .LVL9:
136:Core/Src/stm32f0xx_hal_msp.c ****
227 .loc 1 136 5 is_stmt 0 view .LVU51
228 0018 0321 movs r1, #3
229 001a C005 lsls r0, r0, #23
230 001c FFF7FEFF bl HAL_GPIO_DeInit
231 .LVL10:
232 .loc 1 143 1 view .LVU52
233 0020 F3E7 b .L9
234 .L13:
235 0022 C046 .align 2
236 .L12:
237 0024 00240140 .word 1073816576
238 0028 00100240 .word 1073876992
239 002c FFFDFFFF .word -513
240 .cfi_endproc
ARM GAS /tmp/ccP9ub9v.s page 8
241 .LFE42:
243 .section .text.HAL_CAN_MspInit,"ax",%progbits
244 .align 1
245 .global HAL_CAN_MspInit
246 .syntax unified
247 .code 16
248 .thumb_func
250 HAL_CAN_MspInit:
251 .LVL11:
252 .LFB43:
144:Core/Src/stm32f0xx_hal_msp.c ****
145:Core/Src/stm32f0xx_hal_msp.c **** /**
146:Core/Src/stm32f0xx_hal_msp.c **** * @brief CAN MSP Initialization
147:Core/Src/stm32f0xx_hal_msp.c **** * This function configures the hardware resources used in this example
148:Core/Src/stm32f0xx_hal_msp.c **** * @param hcan: CAN handle pointer
149:Core/Src/stm32f0xx_hal_msp.c **** * @retval None
150:Core/Src/stm32f0xx_hal_msp.c **** */
151:Core/Src/stm32f0xx_hal_msp.c **** void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
152:Core/Src/stm32f0xx_hal_msp.c **** {
253 .loc 1 152 1 is_stmt 1 view -0
254 .cfi_startproc
255 @ args = 0, pretend = 0, frame = 32
256 @ frame_needed = 0, uses_anonymous_args = 0
257 .loc 1 152 1 is_stmt 0 view .LVU54
258 0000 10B5 push {r4, lr}
259 .cfi_def_cfa_offset 8
260 .cfi_offset 4, -8
261 .cfi_offset 14, -4
262 0002 88B0 sub sp, sp, #32
263 .cfi_def_cfa_offset 40
264 0004 0400 movs r4, r0
153:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
265 .loc 1 153 3 is_stmt 1 view .LVU55
266 .loc 1 153 20 is_stmt 0 view .LVU56
267 0006 1422 movs r2, #20
268 0008 0021 movs r1, #0
269 000a 03A8 add r0, sp, #12
270 .LVL12:
271 .loc 1 153 20 view .LVU57
272 000c FFF7FEFF bl memset
273 .LVL13:
154:Core/Src/stm32f0xx_hal_msp.c **** if(hcan->Instance==CAN)
274 .loc 1 154 3 is_stmt 1 view .LVU58
275 .loc 1 154 10 is_stmt 0 view .LVU59
276 0010 2268 ldr r2, [r4]
277 .loc 1 154 5 view .LVU60
278 0012 134B ldr r3, .L17
279 0014 9A42 cmp r2, r3
280 0016 01D0 beq .L16
281 .L14:
155:Core/Src/stm32f0xx_hal_msp.c **** {
156:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN CAN_MspInit 0 */
157:Core/Src/stm32f0xx_hal_msp.c ****
158:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END CAN_MspInit 0 */
159:Core/Src/stm32f0xx_hal_msp.c **** /* Peripheral clock enable */
160:Core/Src/stm32f0xx_hal_msp.c **** __HAL_RCC_CAN1_CLK_ENABLE();
161:Core/Src/stm32f0xx_hal_msp.c ****
ARM GAS /tmp/ccP9ub9v.s page 9
162:Core/Src/stm32f0xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
163:Core/Src/stm32f0xx_hal_msp.c **** /**CAN GPIO Configuration
164:Core/Src/stm32f0xx_hal_msp.c **** PA11 ------> CAN_RX
165:Core/Src/stm32f0xx_hal_msp.c **** PA12 ------> CAN_TX
166:Core/Src/stm32f0xx_hal_msp.c **** */
167:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
168:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
169:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
170:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
171:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF4_CAN;
172:Core/Src/stm32f0xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
173:Core/Src/stm32f0xx_hal_msp.c ****
174:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN CAN_MspInit 1 */
175:Core/Src/stm32f0xx_hal_msp.c ****
176:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END CAN_MspInit 1 */
177:Core/Src/stm32f0xx_hal_msp.c **** }
178:Core/Src/stm32f0xx_hal_msp.c ****
179:Core/Src/stm32f0xx_hal_msp.c **** }
282 .loc 1 179 1 view .LVU61
283 0018 08B0 add sp, sp, #32
284 @ sp needed
285 .LVL14:
286 .loc 1 179 1 view .LVU62
287 001a 10BD pop {r4, pc}
288 .LVL15:
289 .L16:
160:Core/Src/stm32f0xx_hal_msp.c ****
290 .loc 1 160 5 is_stmt 1 view .LVU63
291 .LBB6:
160:Core/Src/stm32f0xx_hal_msp.c ****
292 .loc 1 160 5 view .LVU64
160:Core/Src/stm32f0xx_hal_msp.c ****
293 .loc 1 160 5 view .LVU65
294 001c 114B ldr r3, .L17+4
295 001e DA69 ldr r2, [r3, #28]
296 0020 8021 movs r1, #128
297 0022 8904 lsls r1, r1, #18
298 0024 0A43 orrs r2, r1
299 0026 DA61 str r2, [r3, #28]
160:Core/Src/stm32f0xx_hal_msp.c ****
300 .loc 1 160 5 view .LVU66
301 0028 DA69 ldr r2, [r3, #28]
302 002a 0A40 ands r2, r1
303 002c 0192 str r2, [sp, #4]
160:Core/Src/stm32f0xx_hal_msp.c ****
304 .loc 1 160 5 view .LVU67
305 002e 019A ldr r2, [sp, #4]
306 .LBE6:
160:Core/Src/stm32f0xx_hal_msp.c ****
307 .loc 1 160 5 view .LVU68
162:Core/Src/stm32f0xx_hal_msp.c **** /**CAN GPIO Configuration
308 .loc 1 162 5 view .LVU69
309 .LBB7:
162:Core/Src/stm32f0xx_hal_msp.c **** /**CAN GPIO Configuration
310 .loc 1 162 5 view .LVU70
162:Core/Src/stm32f0xx_hal_msp.c **** /**CAN GPIO Configuration
311 .loc 1 162 5 view .LVU71
ARM GAS /tmp/ccP9ub9v.s page 10
312 0030 5A69 ldr r2, [r3, #20]
313 0032 8021 movs r1, #128
314 0034 8902 lsls r1, r1, #10
315 0036 0A43 orrs r2, r1
316 0038 5A61 str r2, [r3, #20]
162:Core/Src/stm32f0xx_hal_msp.c **** /**CAN GPIO Configuration
317 .loc 1 162 5 view .LVU72
318 003a 5B69 ldr r3, [r3, #20]
319 003c 0B40 ands r3, r1
320 003e 0293 str r3, [sp, #8]
162:Core/Src/stm32f0xx_hal_msp.c **** /**CAN GPIO Configuration
321 .loc 1 162 5 view .LVU73
322 0040 029B ldr r3, [sp, #8]
323 .LBE7:
162:Core/Src/stm32f0xx_hal_msp.c **** /**CAN GPIO Configuration
324 .loc 1 162 5 view .LVU74
167:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
325 .loc 1 167 5 view .LVU75
167:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
326 .loc 1 167 25 is_stmt 0 view .LVU76
327 0042 C023 movs r3, #192
328 0044 5B01 lsls r3, r3, #5
329 0046 0393 str r3, [sp, #12]
168:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
330 .loc 1 168 5 is_stmt 1 view .LVU77
168:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
331 .loc 1 168 26 is_stmt 0 view .LVU78
332 0048 0223 movs r3, #2
333 004a 0493 str r3, [sp, #16]
169:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
334 .loc 1 169 5 is_stmt 1 view .LVU79
170:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF4_CAN;
335 .loc 1 170 5 view .LVU80
170:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF4_CAN;
336 .loc 1 170 27 is_stmt 0 view .LVU81
337 004c 0133 adds r3, r3, #1
338 004e 0693 str r3, [sp, #24]
171:Core/Src/stm32f0xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
339 .loc 1 171 5 is_stmt 1 view .LVU82
171:Core/Src/stm32f0xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
340 .loc 1 171 31 is_stmt 0 view .LVU83
341 0050 0133 adds r3, r3, #1
342 0052 0793 str r3, [sp, #28]
172:Core/Src/stm32f0xx_hal_msp.c ****
343 .loc 1 172 5 is_stmt 1 view .LVU84
344 0054 9020 movs r0, #144
345 0056 03A9 add r1, sp, #12
346 0058 C005 lsls r0, r0, #23
347 005a FFF7FEFF bl HAL_GPIO_Init
348 .LVL16:
349 .loc 1 179 1 is_stmt 0 view .LVU85
350 005e DBE7 b .L14
351 .L18:
352 .align 2
353 .L17:
354 0060 00640040 .word 1073767424
355 0064 00100240 .word 1073876992
ARM GAS /tmp/ccP9ub9v.s page 11
356 .cfi_endproc
357 .LFE43:
359 .section .text.HAL_CAN_MspDeInit,"ax",%progbits
360 .align 1
361 .global HAL_CAN_MspDeInit
362 .syntax unified
363 .code 16
364 .thumb_func
366 HAL_CAN_MspDeInit:
367 .LVL17:
368 .LFB44:
180:Core/Src/stm32f0xx_hal_msp.c ****
181:Core/Src/stm32f0xx_hal_msp.c **** /**
182:Core/Src/stm32f0xx_hal_msp.c **** * @brief CAN MSP De-Initialization
183:Core/Src/stm32f0xx_hal_msp.c **** * This function freeze the hardware resources used in this example
184:Core/Src/stm32f0xx_hal_msp.c **** * @param hcan: CAN handle pointer
185:Core/Src/stm32f0xx_hal_msp.c **** * @retval None
186:Core/Src/stm32f0xx_hal_msp.c **** */
187:Core/Src/stm32f0xx_hal_msp.c **** void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
188:Core/Src/stm32f0xx_hal_msp.c **** {
369 .loc 1 188 1 is_stmt 1 view -0
370 .cfi_startproc
371 @ args = 0, pretend = 0, frame = 0
372 @ frame_needed = 0, uses_anonymous_args = 0
373 .loc 1 188 1 is_stmt 0 view .LVU87
374 0000 10B5 push {r4, lr}
375 .cfi_def_cfa_offset 8
376 .cfi_offset 4, -8
377 .cfi_offset 14, -4
189:Core/Src/stm32f0xx_hal_msp.c **** if(hcan->Instance==CAN)
378 .loc 1 189 3 is_stmt 1 view .LVU88
379 .loc 1 189 10 is_stmt 0 view .LVU89
380 0002 0268 ldr r2, [r0]
381 .loc 1 189 5 view .LVU90
382 0004 074B ldr r3, .L22
383 0006 9A42 cmp r2, r3
384 0008 00D0 beq .L21
385 .LVL18:
386 .L19:
190:Core/Src/stm32f0xx_hal_msp.c **** {
191:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN CAN_MspDeInit 0 */
192:Core/Src/stm32f0xx_hal_msp.c ****
193:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END CAN_MspDeInit 0 */
194:Core/Src/stm32f0xx_hal_msp.c **** /* Peripheral clock disable */
195:Core/Src/stm32f0xx_hal_msp.c **** __HAL_RCC_CAN1_CLK_DISABLE();
196:Core/Src/stm32f0xx_hal_msp.c ****
197:Core/Src/stm32f0xx_hal_msp.c **** /**CAN GPIO Configuration
198:Core/Src/stm32f0xx_hal_msp.c **** PA11 ------> CAN_RX
199:Core/Src/stm32f0xx_hal_msp.c **** PA12 ------> CAN_TX
200:Core/Src/stm32f0xx_hal_msp.c **** */
201:Core/Src/stm32f0xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12);
202:Core/Src/stm32f0xx_hal_msp.c ****
203:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN CAN_MspDeInit 1 */
204:Core/Src/stm32f0xx_hal_msp.c ****
205:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END CAN_MspDeInit 1 */
206:Core/Src/stm32f0xx_hal_msp.c **** }
207:Core/Src/stm32f0xx_hal_msp.c ****
ARM GAS /tmp/ccP9ub9v.s page 12
208:Core/Src/stm32f0xx_hal_msp.c **** }
387 .loc 1 208 1 view .LVU91
388 @ sp needed
389 000a 10BD pop {r4, pc}
390 .LVL19:
391 .L21:
195:Core/Src/stm32f0xx_hal_msp.c ****
392 .loc 1 195 5 is_stmt 1 view .LVU92
393 000c 064A ldr r2, .L22+4
394 000e D369 ldr r3, [r2, #28]
395 0010 0649 ldr r1, .L22+8
396 0012 0B40 ands r3, r1
397 0014 D361 str r3, [r2, #28]
201:Core/Src/stm32f0xx_hal_msp.c ****
398 .loc 1 201 5 view .LVU93
399 0016 C021 movs r1, #192
400 0018 9020 movs r0, #144
401 .LVL20:
201:Core/Src/stm32f0xx_hal_msp.c ****
402 .loc 1 201 5 is_stmt 0 view .LVU94
403 001a 4901 lsls r1, r1, #5
404 001c C005 lsls r0, r0, #23
405 001e FFF7FEFF bl HAL_GPIO_DeInit
406 .LVL21:
407 .loc 1 208 1 view .LVU95
408 0022 F2E7 b .L19
409 .L23:
410 .align 2
411 .L22:
412 0024 00640040 .word 1073767424
413 0028 00100240 .word 1073876992
414 002c FFFFFFFD .word -33554433
415 .cfi_endproc
416 .LFE44:
418 .section .text.HAL_TIM_Base_MspInit,"ax",%progbits
419 .align 1
420 .global HAL_TIM_Base_MspInit
421 .syntax unified
422 .code 16
423 .thumb_func
425 HAL_TIM_Base_MspInit:
426 .LVL22:
427 .LFB45:
209:Core/Src/stm32f0xx_hal_msp.c ****
210:Core/Src/stm32f0xx_hal_msp.c **** /**
211:Core/Src/stm32f0xx_hal_msp.c **** * @brief TIM_Base MSP Initialization
212:Core/Src/stm32f0xx_hal_msp.c **** * This function configures the hardware resources used in this example
213:Core/Src/stm32f0xx_hal_msp.c **** * @param htim_base: TIM_Base handle pointer
214:Core/Src/stm32f0xx_hal_msp.c **** * @retval None
215:Core/Src/stm32f0xx_hal_msp.c **** */
216:Core/Src/stm32f0xx_hal_msp.c **** void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
217:Core/Src/stm32f0xx_hal_msp.c **** {
428 .loc 1 217 1 is_stmt 1 view -0
429 .cfi_startproc
430 @ args = 0, pretend = 0, frame = 8
431 @ frame_needed = 0, uses_anonymous_args = 0
432 @ link register save eliminated.
ARM GAS /tmp/ccP9ub9v.s page 13
433 .loc 1 217 1 is_stmt 0 view .LVU97
434 0000 82B0 sub sp, sp, #8
435 .cfi_def_cfa_offset 8
218:Core/Src/stm32f0xx_hal_msp.c **** if(htim_base->Instance==TIM2)
436 .loc 1 218 3 is_stmt 1 view .LVU98
437 .loc 1 218 15 is_stmt 0 view .LVU99
438 0002 0268 ldr r2, [r0]
439 .loc 1 218 5 view .LVU100
440 0004 8023 movs r3, #128
441 0006 DB05 lsls r3, r3, #23
442 0008 9A42 cmp r2, r3
443 000a 01D0 beq .L26
444 .L24:
219:Core/Src/stm32f0xx_hal_msp.c **** {
220:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspInit 0 */
221:Core/Src/stm32f0xx_hal_msp.c ****
222:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END TIM2_MspInit 0 */
223:Core/Src/stm32f0xx_hal_msp.c **** /* Peripheral clock enable */
224:Core/Src/stm32f0xx_hal_msp.c **** __HAL_RCC_TIM2_CLK_ENABLE();
225:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspInit 1 */
226:Core/Src/stm32f0xx_hal_msp.c ****
227:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END TIM2_MspInit 1 */
228:Core/Src/stm32f0xx_hal_msp.c **** }
229:Core/Src/stm32f0xx_hal_msp.c ****
230:Core/Src/stm32f0xx_hal_msp.c **** }
445 .loc 1 230 1 view .LVU101
446 000c 02B0 add sp, sp, #8
447 @ sp needed
448 000e 7047 bx lr
449 .L26:
224:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspInit 1 */
450 .loc 1 224 5 is_stmt 1 view .LVU102
451 .LBB8:
224:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspInit 1 */
452 .loc 1 224 5 view .LVU103
224:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspInit 1 */
453 .loc 1 224 5 view .LVU104
454 0010 044A ldr r2, .L27
455 0012 D169 ldr r1, [r2, #28]
456 0014 0123 movs r3, #1
457 0016 1943 orrs r1, r3
458 0018 D161 str r1, [r2, #28]
224:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspInit 1 */
459 .loc 1 224 5 view .LVU105
460 001a D269 ldr r2, [r2, #28]
461 001c 1340 ands r3, r2
462 001e 0193 str r3, [sp, #4]
224:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspInit 1 */
463 .loc 1 224 5 view .LVU106
464 0020 019B ldr r3, [sp, #4]
465 .LBE8:
224:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspInit 1 */
466 .loc 1 224 5 discriminator 1 view .LVU107
467 .loc 1 230 1 is_stmt 0 view .LVU108
468 0022 F3E7 b .L24
469 .L28:
470 .align 2
ARM GAS /tmp/ccP9ub9v.s page 14
471 .L27:
472 0024 00100240 .word 1073876992
473 .cfi_endproc
474 .LFE45:
476 .section .text.HAL_TIM_MspPostInit,"ax",%progbits
477 .align 1
478 .global HAL_TIM_MspPostInit
479 .syntax unified
480 .code 16
481 .thumb_func
483 HAL_TIM_MspPostInit:
484 .LVL23:
485 .LFB46:
231:Core/Src/stm32f0xx_hal_msp.c ****
232:Core/Src/stm32f0xx_hal_msp.c **** void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
233:Core/Src/stm32f0xx_hal_msp.c **** {
486 .loc 1 233 1 is_stmt 1 view -0
487 .cfi_startproc
488 @ args = 0, pretend = 0, frame = 32
489 @ frame_needed = 0, uses_anonymous_args = 0
490 .loc 1 233 1 is_stmt 0 view .LVU110
491 0000 10B5 push {r4, lr}
492 .cfi_def_cfa_offset 8
493 .cfi_offset 4, -8
494 .cfi_offset 14, -4
495 0002 88B0 sub sp, sp, #32
496 .cfi_def_cfa_offset 40
497 0004 0400 movs r4, r0
234:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
498 .loc 1 234 3 is_stmt 1 view .LVU111
499 .loc 1 234 20 is_stmt 0 view .LVU112
500 0006 1422 movs r2, #20
501 0008 0021 movs r1, #0
502 000a 03A8 add r0, sp, #12
503 .LVL24:
504 .loc 1 234 20 view .LVU113
505 000c FFF7FEFF bl memset
506 .LVL25:
235:Core/Src/stm32f0xx_hal_msp.c **** if(htim->Instance==TIM2)
507 .loc 1 235 3 is_stmt 1 view .LVU114
508 .loc 1 235 10 is_stmt 0 view .LVU115
509 0010 2268 ldr r2, [r4]
510 .loc 1 235 5 view .LVU116
511 0012 8023 movs r3, #128
512 0014 DB05 lsls r3, r3, #23
513 0016 9A42 cmp r2, r3
514 0018 01D0 beq .L31
515 .LVL26:
516 .L29:
236:Core/Src/stm32f0xx_hal_msp.c **** {
237:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspPostInit 0 */
238:Core/Src/stm32f0xx_hal_msp.c ****
239:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END TIM2_MspPostInit 0 */
240:Core/Src/stm32f0xx_hal_msp.c ****
241:Core/Src/stm32f0xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
242:Core/Src/stm32f0xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
243:Core/Src/stm32f0xx_hal_msp.c **** /**TIM2 GPIO Configuration
ARM GAS /tmp/ccP9ub9v.s page 15
244:Core/Src/stm32f0xx_hal_msp.c **** PA2 ------> TIM2_CH3
245:Core/Src/stm32f0xx_hal_msp.c **** PA5 ------> TIM2_CH1
246:Core/Src/stm32f0xx_hal_msp.c **** PB3 ------> TIM2_CH2
247:Core/Src/stm32f0xx_hal_msp.c **** */
248:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_5;
249:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
250:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
251:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
252:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM2;
253:Core/Src/stm32f0xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
254:Core/Src/stm32f0xx_hal_msp.c ****
255:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_3;
256:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
257:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
258:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
259:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM2;
260:Core/Src/stm32f0xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
261:Core/Src/stm32f0xx_hal_msp.c ****
262:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspPostInit 1 */
263:Core/Src/stm32f0xx_hal_msp.c ****
264:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END TIM2_MspPostInit 1 */
265:Core/Src/stm32f0xx_hal_msp.c **** }
266:Core/Src/stm32f0xx_hal_msp.c ****
267:Core/Src/stm32f0xx_hal_msp.c **** }
517 .loc 1 267 1 view .LVU117
518 001a 08B0 add sp, sp, #32
519 @ sp needed
520 001c 10BD pop {r4, pc}
521 .LVL27:
522 .L31:
241:Core/Src/stm32f0xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
523 .loc 1 241 5 is_stmt 1 view .LVU118
524 .LBB9:
241:Core/Src/stm32f0xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
525 .loc 1 241 5 view .LVU119
241:Core/Src/stm32f0xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
526 .loc 1 241 5 view .LVU120
527 001e 144B ldr r3, .L32
528 0020 5A69 ldr r2, [r3, #20]
529 0022 8021 movs r1, #128
530 0024 8902 lsls r1, r1, #10
531 0026 0A43 orrs r2, r1
532 0028 5A61 str r2, [r3, #20]
241:Core/Src/stm32f0xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
533 .loc 1 241 5 view .LVU121
534 002a 5A69 ldr r2, [r3, #20]
535 002c 0A40 ands r2, r1
536 002e 0192 str r2, [sp, #4]
241:Core/Src/stm32f0xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
537 .loc 1 241 5 view .LVU122
538 0030 019A ldr r2, [sp, #4]
539 .LBE9:
241:Core/Src/stm32f0xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
540 .loc 1 241 5 view .LVU123
242:Core/Src/stm32f0xx_hal_msp.c **** /**TIM2 GPIO Configuration
541 .loc 1 242 5 view .LVU124
542 .LBB10:
ARM GAS /tmp/ccP9ub9v.s page 16
242:Core/Src/stm32f0xx_hal_msp.c **** /**TIM2 GPIO Configuration
543 .loc 1 242 5 view .LVU125
242:Core/Src/stm32f0xx_hal_msp.c **** /**TIM2 GPIO Configuration
544 .loc 1 242 5 view .LVU126
545 0032 5A69 ldr r2, [r3, #20]
546 0034 8021 movs r1, #128
547 0036 C902 lsls r1, r1, #11
548 0038 0A43 orrs r2, r1
549 003a 5A61 str r2, [r3, #20]
242:Core/Src/stm32f0xx_hal_msp.c **** /**TIM2 GPIO Configuration
550 .loc 1 242 5 view .LVU127
551 003c 5B69 ldr r3, [r3, #20]
552 003e 0B40 ands r3, r1
553 0040 0293 str r3, [sp, #8]
242:Core/Src/stm32f0xx_hal_msp.c **** /**TIM2 GPIO Configuration
554 .loc 1 242 5 view .LVU128
555 0042 029B ldr r3, [sp, #8]
556 .LBE10:
242:Core/Src/stm32f0xx_hal_msp.c **** /**TIM2 GPIO Configuration
557 .loc 1 242 5 view .LVU129
248:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
558 .loc 1 248 5 view .LVU130
248:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
559 .loc 1 248 25 is_stmt 0 view .LVU131
560 0044 2423 movs r3, #36
561 0046 0393 str r3, [sp, #12]
249:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
562 .loc 1 249 5 is_stmt 1 view .LVU132
249:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
563 .loc 1 249 26 is_stmt 0 view .LVU133
564 0048 0224 movs r4, #2
565 .LVL28:
249:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
566 .loc 1 249 26 view .LVU134
567 004a 0494 str r4, [sp, #16]
250:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
568 .loc 1 250 5 is_stmt 1 view .LVU135
251:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM2;
569 .loc 1 251 5 view .LVU136
252:Core/Src/stm32f0xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
570 .loc 1 252 5 view .LVU137
252:Core/Src/stm32f0xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
571 .loc 1 252 31 is_stmt 0 view .LVU138
572 004c 0794 str r4, [sp, #28]
253:Core/Src/stm32f0xx_hal_msp.c ****
573 .loc 1 253 5 is_stmt 1 view .LVU139
574 004e 9020 movs r0, #144
575 0050 03A9 add r1, sp, #12
576 0052 C005 lsls r0, r0, #23
577 0054 FFF7FEFF bl HAL_GPIO_Init
578 .LVL29:
255:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
579 .loc 1 255 5 view .LVU140
255:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
580 .loc 1 255 25 is_stmt 0 view .LVU141
581 0058 0823 movs r3, #8
582 005a 0393 str r3, [sp, #12]
ARM GAS /tmp/ccP9ub9v.s page 17
256:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
583 .loc 1 256 5 is_stmt 1 view .LVU142
256:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
584 .loc 1 256 26 is_stmt 0 view .LVU143
585 005c 0494 str r4, [sp, #16]
257:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
586 .loc 1 257 5 is_stmt 1 view .LVU144
257:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
587 .loc 1 257 26 is_stmt 0 view .LVU145
588 005e 0023 movs r3, #0
589 0060 0593 str r3, [sp, #20]
258:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM2;
590 .loc 1 258 5 is_stmt 1 view .LVU146
258:Core/Src/stm32f0xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM2;
591 .loc 1 258 27 is_stmt 0 view .LVU147
592 0062 0693 str r3, [sp, #24]
259:Core/Src/stm32f0xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
593 .loc 1 259 5 is_stmt 1 view .LVU148
259:Core/Src/stm32f0xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
594 .loc 1 259 31 is_stmt 0 view .LVU149
595 0064 0794 str r4, [sp, #28]
260:Core/Src/stm32f0xx_hal_msp.c ****
596 .loc 1 260 5 is_stmt 1 view .LVU150
597 0066 03A9 add r1, sp, #12
598 0068 0248 ldr r0, .L32+4
599 006a FFF7FEFF bl HAL_GPIO_Init
600 .LVL30:
601 .loc 1 267 1 is_stmt 0 view .LVU151
602 006e D4E7 b .L29
603 .L33:
604 .align 2
605 .L32:
606 0070 00100240 .word 1073876992
607 0074 00040048 .word 1207960576
608 .cfi_endproc
609 .LFE46:
611 .section .text.HAL_TIM_Base_MspDeInit,"ax",%progbits
612 .align 1
613 .global HAL_TIM_Base_MspDeInit
614 .syntax unified
615 .code 16
616 .thumb_func
618 HAL_TIM_Base_MspDeInit:
619 .LVL31:
620 .LFB47:
268:Core/Src/stm32f0xx_hal_msp.c **** /**
269:Core/Src/stm32f0xx_hal_msp.c **** * @brief TIM_Base MSP De-Initialization
270:Core/Src/stm32f0xx_hal_msp.c **** * This function freeze the hardware resources used in this example
271:Core/Src/stm32f0xx_hal_msp.c **** * @param htim_base: TIM_Base handle pointer
272:Core/Src/stm32f0xx_hal_msp.c **** * @retval None
273:Core/Src/stm32f0xx_hal_msp.c **** */
274:Core/Src/stm32f0xx_hal_msp.c **** void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
275:Core/Src/stm32f0xx_hal_msp.c **** {
621 .loc 1 275 1 is_stmt 1 view -0
622 .cfi_startproc
623 @ args = 0, pretend = 0, frame = 0
624 @ frame_needed = 0, uses_anonymous_args = 0
ARM GAS /tmp/ccP9ub9v.s page 18
625 @ link register save eliminated.
276:Core/Src/stm32f0xx_hal_msp.c **** if(htim_base->Instance==TIM2)
626 .loc 1 276 3 view .LVU153
627 .loc 1 276 15 is_stmt 0 view .LVU154
628 0000 0268 ldr r2, [r0]
629 .loc 1 276 5 view .LVU155
630 0002 8023 movs r3, #128
631 0004 DB05 lsls r3, r3, #23
632 0006 9A42 cmp r2, r3
633 0008 00D0 beq .L36
634 .L34:
277:Core/Src/stm32f0xx_hal_msp.c **** {
278:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspDeInit 0 */
279:Core/Src/stm32f0xx_hal_msp.c ****
280:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END TIM2_MspDeInit 0 */
281:Core/Src/stm32f0xx_hal_msp.c **** /* Peripheral clock disable */
282:Core/Src/stm32f0xx_hal_msp.c **** __HAL_RCC_TIM2_CLK_DISABLE();
283:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspDeInit 1 */
284:Core/Src/stm32f0xx_hal_msp.c ****
285:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE END TIM2_MspDeInit 1 */
286:Core/Src/stm32f0xx_hal_msp.c **** }
287:Core/Src/stm32f0xx_hal_msp.c ****
288:Core/Src/stm32f0xx_hal_msp.c **** }
635 .loc 1 288 1 view .LVU156
636 @ sp needed
637 000a 7047 bx lr
638 .L36:
282:Core/Src/stm32f0xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspDeInit 1 */
639 .loc 1 282 5 is_stmt 1 view .LVU157
640 000c 024A ldr r2, .L37
641 000e D369 ldr r3, [r2, #28]
642 0010 0121 movs r1, #1
643 0012 8B43 bics r3, r1
644 0014 D361 str r3, [r2, #28]
645 .loc 1 288 1 is_stmt 0 view .LVU158
646 0016 F8E7 b .L34
647 .L38:
648 .align 2
649 .L37:
650 0018 00100240 .word 1073876992
651 .cfi_endproc
652 .LFE47:
654 .text
655 .Letext0:
656 .file 2 "/home/chiangni/.config/VSCodium/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/
657 .file 3 "/home/chiangni/.config/VSCodium/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/
658 .file 4 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h"
659 .file 5 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h"
660 .file 6 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h"
661 .file 7 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h"
662 .file 8 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h"
663 .file 9 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h"
664 .file 10 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h"
665 .file 11 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h"
666 .file 12 "<built-in>"
ARM GAS /tmp/ccP9ub9v.s page 19
DEFINED SYMBOLS
*ABS*:00000000 stm32f0xx_hal_msp.c
/tmp/ccP9ub9v.s:19 .text.HAL_MspInit:00000000 $t
/tmp/ccP9ub9v.s:25 .text.HAL_MspInit:00000000 HAL_MspInit
/tmp/ccP9ub9v.s:75 .text.HAL_MspInit:0000002c $d
/tmp/ccP9ub9v.s:80 .text.HAL_ADC_MspInit:00000000 $t
/tmp/ccP9ub9v.s:86 .text.HAL_ADC_MspInit:00000000 HAL_ADC_MspInit
/tmp/ccP9ub9v.s:180 .text.HAL_ADC_MspInit:00000054 $d
/tmp/ccP9ub9v.s:186 .text.HAL_ADC_MspDeInit:00000000 $t
/tmp/ccP9ub9v.s:192 .text.HAL_ADC_MspDeInit:00000000 HAL_ADC_MspDeInit
/tmp/ccP9ub9v.s:237 .text.HAL_ADC_MspDeInit:00000024 $d
/tmp/ccP9ub9v.s:244 .text.HAL_CAN_MspInit:00000000 $t
/tmp/ccP9ub9v.s:250 .text.HAL_CAN_MspInit:00000000 HAL_CAN_MspInit
/tmp/ccP9ub9v.s:354 .text.HAL_CAN_MspInit:00000060 $d
/tmp/ccP9ub9v.s:360 .text.HAL_CAN_MspDeInit:00000000 $t
/tmp/ccP9ub9v.s:366 .text.HAL_CAN_MspDeInit:00000000 HAL_CAN_MspDeInit
/tmp/ccP9ub9v.s:412 .text.HAL_CAN_MspDeInit:00000024 $d
/tmp/ccP9ub9v.s:419 .text.HAL_TIM_Base_MspInit:00000000 $t
/tmp/ccP9ub9v.s:425 .text.HAL_TIM_Base_MspInit:00000000 HAL_TIM_Base_MspInit
/tmp/ccP9ub9v.s:472 .text.HAL_TIM_Base_MspInit:00000024 $d
/tmp/ccP9ub9v.s:477 .text.HAL_TIM_MspPostInit:00000000 $t
/tmp/ccP9ub9v.s:483 .text.HAL_TIM_MspPostInit:00000000 HAL_TIM_MspPostInit
/tmp/ccP9ub9v.s:606 .text.HAL_TIM_MspPostInit:00000070 $d
/tmp/ccP9ub9v.s:612 .text.HAL_TIM_Base_MspDeInit:00000000 $t
/tmp/ccP9ub9v.s:618 .text.HAL_TIM_Base_MspDeInit:00000000 HAL_TIM_Base_MspDeInit
/tmp/ccP9ub9v.s:650 .text.HAL_TIM_Base_MspDeInit:00000018 $d
UNDEFINED SYMBOLS
memset
HAL_GPIO_Init
HAL_GPIO_DeInit