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PDU_Code/Debug/PDU_FT23.list

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PDU_FT23.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001d8 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00007ad0 080001d8 080001d8 000101d8 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000028 08007ca8 08007ca8 00017ca8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08007cd0 08007cd0 00020010 2**0
CONTENTS
4 .ARM 00000000 08007cd0 08007cd0 00020010 2**0
CONTENTS
5 .preinit_array 00000000 08007cd0 08007cd0 00020010 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08007cd0 08007cd0 00017cd0 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08007cd4 08007cd4 00017cd4 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 00000010 20000000 08007cd8 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000428 20000010 08007ce8 00020010 2**2
ALLOC
10 ._user_heap_stack 00000600 20000438 08007ce8 00020438 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 00020010 2**0
CONTENTS, READONLY
12 .debug_info 0001be2d 00000000 00000000 00020040 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 0000338d 00000000 00000000 0003be6d 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 000017d0 00000000 00000000 0003f200 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 00001658 00000000 00000000 000409d0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 000252c8 00000000 00000000 00042028 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00019f7a 00000000 00000000 000672f0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000e13a9 00000000 00000000 0008126a 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000050 00000000 00000000 00162613 2**0
CONTENTS, READONLY
20 .debug_frame 0000666c 00000000 00000000 00162664 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001d8 <__do_global_dtors_aux>:
80001d8: b510 push {r4, lr}
80001da: 4c05 ldr r4, [pc, #20] ; (80001f0 <__do_global_dtors_aux+0x18>)
80001dc: 7823 ldrb r3, [r4, #0]
80001de: b933 cbnz r3, 80001ee <__do_global_dtors_aux+0x16>
80001e0: 4b04 ldr r3, [pc, #16] ; (80001f4 <__do_global_dtors_aux+0x1c>)
80001e2: b113 cbz r3, 80001ea <__do_global_dtors_aux+0x12>
80001e4: 4804 ldr r0, [pc, #16] ; (80001f8 <__do_global_dtors_aux+0x20>)
80001e6: f3af 8000 nop.w
80001ea: 2301 movs r3, #1
80001ec: 7023 strb r3, [r4, #0]
80001ee: bd10 pop {r4, pc}
80001f0: 20000010 .word 0x20000010
80001f4: 00000000 .word 0x00000000
80001f8: 08007c90 .word 0x08007c90
080001fc <frame_dummy>:
80001fc: b508 push {r3, lr}
80001fe: 4b03 ldr r3, [pc, #12] ; (800020c <frame_dummy+0x10>)
8000200: b11b cbz r3, 800020a <frame_dummy+0xe>
8000202: 4903 ldr r1, [pc, #12] ; (8000210 <frame_dummy+0x14>)
8000204: 4803 ldr r0, [pc, #12] ; (8000214 <frame_dummy+0x18>)
8000206: f3af 8000 nop.w
800020a: bd08 pop {r3, pc}
800020c: 00000000 .word 0x00000000
8000210: 20000014 .word 0x20000014
8000214: 08007c90 .word 0x08007c90
08000218 <can_init>:
volatile uint8_t canmsg_received = 0;
extern PortExtenderGPIO EN_Ports;
extern CurrentMeasurements current_measurements_adc_val;
void can_init(FDCAN_HandleTypeDef* hcan)
{
8000218: b580 push {r7, lr}
800021a: b082 sub sp, #8
800021c: af00 add r7, sp, #0
800021e: 6078 str r0, [r7, #4]
ftcan_init(hcan);
8000220: 6878 ldr r0, [r7, #4]
8000222: f000 fb8d bl 8000940 <ftcan_init>
ftcan_add_filter(0x00, 0x00); //No Filter
8000226: 2100 movs r1, #0
8000228: 2000 movs r0, #0
800022a: f000 fc2b bl 8000a84 <ftcan_add_filter>
}
800022e: bf00 nop
8000230: 3708 adds r7, #8
8000232: 46bd mov sp, r7
8000234: bd80 pop {r7, pc}
...
08000238 <can_sendloop>:
void can_sendloop()
{
8000238: b580 push {r7, lr}
800023a: b084 sub sp, #16
800023c: af00 add r7, sp, #0
static uint8_t additionaltxcouter = 0;
uint8_t status_data[6];
status_data[0] = EN_Ports.porta.porta;
800023e: 4b7e ldr r3, [pc, #504] ; (8000438 <can_sendloop+0x200>)
8000240: 781b ldrb r3, [r3, #0]
8000242: 723b strb r3, [r7, #8]
status_data[1] = EN_Ports.portb.portb;
8000244: 4b7c ldr r3, [pc, #496] ; (8000438 <can_sendloop+0x200>)
8000246: 785b ldrb r3, [r3, #1]
8000248: 727b strb r3, [r7, #9]
status_data[2] = rxstate.pwmfans;
800024a: 4b7c ldr r3, [pc, #496] ; (800043c <can_sendloop+0x204>)
800024c: 789b ldrb r3, [r3, #2]
800024e: 72bb strb r3, [r7, #10]
status_data[3] = rxstate.pwmaggregat;
8000250: 4b7a ldr r3, [pc, #488] ; (800043c <can_sendloop+0x204>)
8000252: 78db ldrb r3, [r3, #3]
8000254: 72fb strb r3, [r7, #11]
status_data[4] = rxstate.pwmpumps;
8000256: 4b79 ldr r3, [pc, #484] ; (800043c <can_sendloop+0x204>)
8000258: 791b ldrb r3, [r3, #4]
800025a: 733b strb r3, [r7, #12]
status_data[5] = 0xFF ^ rxstate.checksum;
800025c: 4b77 ldr r3, [pc, #476] ; (800043c <can_sendloop+0x204>)
800025e: 795b ldrb r3, [r3, #5]
8000260: 43db mvns r3, r3
8000262: b2db uxtb r3, r3
8000264: 737b strb r3, [r7, #13]
ftcan_transmit(TX_STATUS_MSG_ID, status_data, 6);
8000266: f107 0308 add.w r3, r7, #8
800026a: 2206 movs r2, #6
800026c: 4619 mov r1, r3
800026e: 20c9 movs r0, #201 ; 0xc9
8000270: f000 fb98 bl 80009a4 <ftcan_transmit>
uint8_t data[8];
if(additionaltxcouter < 4)
8000274: 4b72 ldr r3, [pc, #456] ; (8000440 <can_sendloop+0x208>)
8000276: 781b ldrb r3, [r3, #0]
8000278: 2b03 cmp r3, #3
800027a: f200 80d5 bhi.w 8000428 <can_sendloop+0x1f0>
{
switch(additionaltxcouter)
800027e: 4b70 ldr r3, [pc, #448] ; (8000440 <can_sendloop+0x208>)
8000280: 781b ldrb r3, [r3, #0]
8000282: 2b03 cmp r3, #3
8000284: f200 80c8 bhi.w 8000418 <can_sendloop+0x1e0>
8000288: a201 add r2, pc, #4 ; (adr r2, 8000290 <can_sendloop+0x58>)
800028a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800028e: bf00 nop
8000290: 080002a1 .word 0x080002a1
8000294: 080002ff .word 0x080002ff
8000298: 0800035d .word 0x0800035d
800029c: 080003bb .word 0x080003bb
{
case 0:
data[0] = (uint8_t)current_measurements_adc_val.always_on >> 8;
80002a0: 4b68 ldr r3, [pc, #416] ; (8000444 <can_sendloop+0x20c>)
80002a2: 8a5b ldrh r3, [r3, #18]
80002a4: b2db uxtb r3, r3
80002a6: 121b asrs r3, r3, #8
80002a8: b2db uxtb r3, r3
80002aa: 703b strb r3, [r7, #0]
data[1] = (uint8_t)current_measurements_adc_val.always_on & 0xFF;
80002ac: 4b65 ldr r3, [pc, #404] ; (8000444 <can_sendloop+0x20c>)
80002ae: 8a5b ldrh r3, [r3, #18]
80002b0: b2db uxtb r3, r3
80002b2: 707b strb r3, [r7, #1]
data[2] = (uint8_t)current_measurements_adc_val.misc >> 8;
80002b4: 4b63 ldr r3, [pc, #396] ; (8000444 <can_sendloop+0x20c>)
80002b6: 8a1b ldrh r3, [r3, #16]
80002b8: b2db uxtb r3, r3
80002ba: 121b asrs r3, r3, #8
80002bc: b2db uxtb r3, r3
80002be: 70bb strb r3, [r7, #2]
data[3] = (uint8_t)current_measurements_adc_val.misc & 0xFF;
80002c0: 4b60 ldr r3, [pc, #384] ; (8000444 <can_sendloop+0x20c>)
80002c2: 8a1b ldrh r3, [r3, #16]
80002c4: b2db uxtb r3, r3
80002c6: 70fb strb r3, [r7, #3]
data[4] = (uint8_t)current_measurements_adc_val.inverter >> 8;
80002c8: 4b5e ldr r3, [pc, #376] ; (8000444 <can_sendloop+0x20c>)
80002ca: 891b ldrh r3, [r3, #8]
80002cc: b2db uxtb r3, r3
80002ce: 121b asrs r3, r3, #8
80002d0: b2db uxtb r3, r3
80002d2: 713b strb r3, [r7, #4]
data[5] = (uint8_t)current_measurements_adc_val.inverter & 0xFF;
80002d4: 4b5b ldr r3, [pc, #364] ; (8000444 <can_sendloop+0x20c>)
80002d6: 891b ldrh r3, [r3, #8]
80002d8: b2db uxtb r3, r3
80002da: 717b strb r3, [r7, #5]
data[6] = (uint8_t)current_measurements_adc_val.shutdown_circuit >> 8;
80002dc: 4b59 ldr r3, [pc, #356] ; (8000444 <can_sendloop+0x20c>)
80002de: 8a9b ldrh r3, [r3, #20]
80002e0: b2db uxtb r3, r3
80002e2: 121b asrs r3, r3, #8
80002e4: b2db uxtb r3, r3
80002e6: 71bb strb r3, [r7, #6]
data[7] = (uint8_t)current_measurements_adc_val.shutdown_circuit & 0xFF;
80002e8: 4b56 ldr r3, [pc, #344] ; (8000444 <can_sendloop+0x20c>)
80002ea: 8a9b ldrh r3, [r3, #20]
80002ec: b2db uxtb r3, r3
80002ee: 71fb strb r3, [r7, #7]
ftcan_transmit(CUR_CHANNELS_1_ID, data, 8);
80002f0: 463b mov r3, r7
80002f2: 2208 movs r2, #8
80002f4: 4619 mov r1, r3
80002f6: 20ca movs r0, #202 ; 0xca
80002f8: f000 fb54 bl 80009a4 <ftcan_transmit>
break;
80002fc: e08d b.n 800041a <can_sendloop+0x1e2>
case 1:
data[0] = (uint8_t)current_measurements_adc_val.fans >> 8;
80002fe: 4b51 ldr r3, [pc, #324] ; (8000444 <can_sendloop+0x20c>)
8000300: 889b ldrh r3, [r3, #4]
8000302: b2db uxtb r3, r3
8000304: 121b asrs r3, r3, #8
8000306: b2db uxtb r3, r3
8000308: 703b strb r3, [r7, #0]
data[1] = (uint8_t)current_measurements_adc_val.fans & 0xFF;
800030a: 4b4e ldr r3, [pc, #312] ; (8000444 <can_sendloop+0x20c>)
800030c: 889b ldrh r3, [r3, #4]
800030e: b2db uxtb r3, r3
8000310: 707b strb r3, [r7, #1]
data[2] = (uint8_t)current_measurements_adc_val.pumps >> 8;
8000312: 4b4c ldr r3, [pc, #304] ; (8000444 <can_sendloop+0x20c>)
8000314: 895b ldrh r3, [r3, #10]
8000316: b2db uxtb r3, r3
8000318: 121b asrs r3, r3, #8
800031a: b2db uxtb r3, r3
800031c: 70bb strb r3, [r7, #2]
data[3] = (uint8_t)current_measurements_adc_val.pumps & 0xFF;
800031e: 4b49 ldr r3, [pc, #292] ; (8000444 <can_sendloop+0x20c>)
8000320: 895b ldrh r3, [r3, #10]
8000322: b2db uxtb r3, r3
8000324: 70fb strb r3, [r7, #3]
data[4] = (uint8_t)current_measurements_adc_val.aggregat >> 8;
8000326: 4b47 ldr r3, [pc, #284] ; (8000444 <can_sendloop+0x20c>)
8000328: 88db ldrh r3, [r3, #6]
800032a: b2db uxtb r3, r3
800032c: 121b asrs r3, r3, #8
800032e: b2db uxtb r3, r3
8000330: 713b strb r3, [r7, #4]
data[5] = (uint8_t)current_measurements_adc_val.aggregat & 0xFF;
8000332: 4b44 ldr r3, [pc, #272] ; (8000444 <can_sendloop+0x20c>)
8000334: 88db ldrh r3, [r3, #6]
8000336: b2db uxtb r3, r3
8000338: 717b strb r3, [r7, #5]
data[6] = (uint8_t)current_measurements_adc_val.steering >> 8;
800033a: 4b42 ldr r3, [pc, #264] ; (8000444 <can_sendloop+0x20c>)
800033c: 899b ldrh r3, [r3, #12]
800033e: b2db uxtb r3, r3
8000340: 121b asrs r3, r3, #8
8000342: b2db uxtb r3, r3
8000344: 71bb strb r3, [r7, #6]
data[7] = (uint8_t)current_measurements_adc_val.steering & 0xFF;
8000346: 4b3f ldr r3, [pc, #252] ; (8000444 <can_sendloop+0x20c>)
8000348: 899b ldrh r3, [r3, #12]
800034a: b2db uxtb r3, r3
800034c: 71fb strb r3, [r7, #7]
ftcan_transmit(CUR_CHANNELS_2_ID, data, 8);
800034e: 463b mov r3, r7
8000350: 2208 movs r2, #8
8000352: 4619 mov r1, r3
8000354: 20cb movs r0, #203 ; 0xcb
8000356: f000 fb25 bl 80009a4 <ftcan_transmit>
break;
800035a: e05e b.n 800041a <can_sendloop+0x1e2>
case 2:
data[0] = (uint8_t)current_measurements_adc_val.ebsvalve_1 >> 8;
800035c: 4b39 ldr r3, [pc, #228] ; (8000444 <can_sendloop+0x20c>)
800035e: 8b5b ldrh r3, [r3, #26]
8000360: b2db uxtb r3, r3
8000362: 121b asrs r3, r3, #8
8000364: b2db uxtb r3, r3
8000366: 703b strb r3, [r7, #0]
data[1] = (uint8_t)current_measurements_adc_val.ebsvalve_1 & 0xFF;
8000368: 4b36 ldr r3, [pc, #216] ; (8000444 <can_sendloop+0x20c>)
800036a: 8b5b ldrh r3, [r3, #26]
800036c: b2db uxtb r3, r3
800036e: 707b strb r3, [r7, #1]
data[2] = (uint8_t)current_measurements_adc_val.ebsvalve_2 >> 8;
8000370: 4b34 ldr r3, [pc, #208] ; (8000444 <can_sendloop+0x20c>)
8000372: 8b9b ldrh r3, [r3, #28]
8000374: b2db uxtb r3, r3
8000376: 121b asrs r3, r3, #8
8000378: b2db uxtb r3, r3
800037a: 70bb strb r3, [r7, #2]
data[3] = (uint8_t)current_measurements_adc_val.ebsvalve_2 & 0xFF;
800037c: 4b31 ldr r3, [pc, #196] ; (8000444 <can_sendloop+0x20c>)
800037e: 8b9b ldrh r3, [r3, #28]
8000380: b2db uxtb r3, r3
8000382: 70fb strb r3, [r7, #3]
data[4] = (uint8_t)current_measurements_adc_val.modevalve_1 >> 8;
8000384: 4b2f ldr r3, [pc, #188] ; (8000444 <can_sendloop+0x20c>)
8000386: 8adb ldrh r3, [r3, #22]
8000388: b2db uxtb r3, r3
800038a: 121b asrs r3, r3, #8
800038c: b2db uxtb r3, r3
800038e: 713b strb r3, [r7, #4]
data[5] = (uint8_t)current_measurements_adc_val.modevalve_1 & 0xFF;
8000390: 4b2c ldr r3, [pc, #176] ; (8000444 <can_sendloop+0x20c>)
8000392: 8adb ldrh r3, [r3, #22]
8000394: b2db uxtb r3, r3
8000396: 717b strb r3, [r7, #5]
data[6] = (uint8_t)current_measurements_adc_val.modevalve_2 >> 8;
8000398: 4b2a ldr r3, [pc, #168] ; (8000444 <can_sendloop+0x20c>)
800039a: 8b1b ldrh r3, [r3, #24]
800039c: b2db uxtb r3, r3
800039e: 121b asrs r3, r3, #8
80003a0: b2db uxtb r3, r3
80003a2: 71bb strb r3, [r7, #6]
data[7] = (uint8_t)current_measurements_adc_val.modevalve_2 & 0xFF;
80003a4: 4b27 ldr r3, [pc, #156] ; (8000444 <can_sendloop+0x20c>)
80003a6: 8b1b ldrh r3, [r3, #24]
80003a8: b2db uxtb r3, r3
80003aa: 71fb strb r3, [r7, #7]
ftcan_transmit(CUR_CHANNELS_3_ID, data, 8);
80003ac: 463b mov r3, r7
80003ae: 2208 movs r2, #8
80003b0: 4619 mov r1, r3
80003b2: 20cc movs r0, #204 ; 0xcc
80003b4: f000 faf6 bl 80009a4 <ftcan_transmit>
break;
80003b8: e02f b.n 800041a <can_sendloop+0x1e2>
case 3:
data[0] = (uint8_t)current_measurements_adc_val.sensorbox >> 8;
80003ba: 4b22 ldr r3, [pc, #136] ; (8000444 <can_sendloop+0x20c>)
80003bc: 885b ldrh r3, [r3, #2]
80003be: b2db uxtb r3, r3
80003c0: 121b asrs r3, r3, #8
80003c2: b2db uxtb r3, r3
80003c4: 703b strb r3, [r7, #0]
data[1] = (uint8_t)current_measurements_adc_val.sensorbox & 0xFF;
80003c6: 4b1f ldr r3, [pc, #124] ; (8000444 <can_sendloop+0x20c>)
80003c8: 885b ldrh r3, [r3, #2]
80003ca: b2db uxtb r3, r3
80003cc: 707b strb r3, [r7, #1]
data[2] = (uint8_t)current_measurements_adc_val.servicebrake >> 8;
80003ce: 4b1d ldr r3, [pc, #116] ; (8000444 <can_sendloop+0x20c>)
80003d0: 881b ldrh r3, [r3, #0]
80003d2: b2db uxtb r3, r3
80003d4: 121b asrs r3, r3, #8
80003d6: b2db uxtb r3, r3
80003d8: 70bb strb r3, [r7, #2]
data[3] = (uint8_t)current_measurements_adc_val.servicebrake & 0xFF;
80003da: 4b1a ldr r3, [pc, #104] ; (8000444 <can_sendloop+0x20c>)
80003dc: 881b ldrh r3, [r3, #0]
80003de: b2db uxtb r3, r3
80003e0: 70fb strb r3, [r7, #3]
data[4] = (uint8_t)current_measurements_adc_val.servos >> 8;
80003e2: 4b18 ldr r3, [pc, #96] ; (8000444 <can_sendloop+0x20c>)
80003e4: 89db ldrh r3, [r3, #14]
80003e6: b2db uxtb r3, r3
80003e8: 121b asrs r3, r3, #8
80003ea: b2db uxtb r3, r3
80003ec: 713b strb r3, [r7, #4]
data[5] = (uint8_t)current_measurements_adc_val.servos & 0xFF;
80003ee: 4b15 ldr r3, [pc, #84] ; (8000444 <can_sendloop+0x20c>)
80003f0: 89db ldrh r3, [r3, #14]
80003f2: b2db uxtb r3, r3
80003f4: 717b strb r3, [r7, #5]
data[6] = (uint8_t)current_measurements_adc_val.shutdown_circuit >> 8;
80003f6: 4b13 ldr r3, [pc, #76] ; (8000444 <can_sendloop+0x20c>)
80003f8: 8a9b ldrh r3, [r3, #20]
80003fa: b2db uxtb r3, r3
80003fc: 121b asrs r3, r3, #8
80003fe: b2db uxtb r3, r3
8000400: 71bb strb r3, [r7, #6]
data[7] = (uint8_t)current_measurements_adc_val.shutdown_circuit & 0xFF;
8000402: 4b10 ldr r3, [pc, #64] ; (8000444 <can_sendloop+0x20c>)
8000404: 8a9b ldrh r3, [r3, #20]
8000406: b2db uxtb r3, r3
8000408: 71fb strb r3, [r7, #7]
ftcan_transmit(CUR_CHANNELS_4_ID, data, 8);
800040a: 463b mov r3, r7
800040c: 2208 movs r2, #8
800040e: 4619 mov r1, r3
8000410: 20cd movs r0, #205 ; 0xcd
8000412: f000 fac7 bl 80009a4 <ftcan_transmit>
break;
8000416: e000 b.n 800041a <can_sendloop+0x1e2>
default:
break;
8000418: bf00 nop
}
additionaltxcouter++;
800041a: 4b09 ldr r3, [pc, #36] ; (8000440 <can_sendloop+0x208>)
800041c: 781b ldrb r3, [r3, #0]
800041e: 3301 adds r3, #1
8000420: b2da uxtb r2, r3
8000422: 4b07 ldr r3, [pc, #28] ; (8000440 <can_sendloop+0x208>)
8000424: 701a strb r2, [r3, #0]
additionaltxcouter = 0;
}
}
8000426: e002 b.n 800042e <can_sendloop+0x1f6>
additionaltxcouter = 0;
8000428: 4b05 ldr r3, [pc, #20] ; (8000440 <can_sendloop+0x208>)
800042a: 2200 movs r2, #0
800042c: 701a strb r2, [r3, #0]
}
800042e: bf00 nop
8000430: 3710 adds r7, #16
8000432: 46bd mov sp, r7
8000434: bd80 pop {r7, pc}
8000436: bf00 nop
8000438: 20000034 .word 0x20000034
800043c: 2000002c .word 0x2000002c
8000440: 20000033 .word 0x20000033
8000444: 20000060 .word 0x20000060
08000448 <ftcan_msg_received_cb>:
void ftcan_msg_received_cb(uint16_t id, size_t datalen, const uint8_t *data)
{
8000448: b480 push {r7}
800044a: b085 sub sp, #20
800044c: af00 add r7, sp, #0
800044e: 4603 mov r3, r0
8000450: 60b9 str r1, [r7, #8]
8000452: 607a str r2, [r7, #4]
8000454: 81fb strh r3, [r7, #14]
canmsg_received = 1;
8000456: 4b13 ldr r3, [pc, #76] ; (80004a4 <ftcan_msg_received_cb+0x5c>)
8000458: 2201 movs r2, #1
800045a: 701a strb r2, [r3, #0]
if((id == RX_STATUS_MSG_ID) && (datalen == 6))
800045c: 89fb ldrh r3, [r7, #14]
800045e: 2bc8 cmp r3, #200 ; 0xc8
8000460: d11a bne.n 8000498 <ftcan_msg_received_cb+0x50>
8000462: 68bb ldr r3, [r7, #8]
8000464: 2b06 cmp r3, #6
8000466: d117 bne.n 8000498 <ftcan_msg_received_cb+0x50>
{
rxstate.iostatus.porta.porta = data[0];
8000468: 687b ldr r3, [r7, #4]
800046a: 781a ldrb r2, [r3, #0]
800046c: 4b0e ldr r3, [pc, #56] ; (80004a8 <ftcan_msg_received_cb+0x60>)
800046e: 701a strb r2, [r3, #0]
rxstate.iostatus.portb.portb = data[1];
8000470: 687b ldr r3, [r7, #4]
8000472: 785a ldrb r2, [r3, #1]
8000474: 4b0c ldr r3, [pc, #48] ; (80004a8 <ftcan_msg_received_cb+0x60>)
8000476: 705a strb r2, [r3, #1]
rxstate.pwmfans = data[2];
8000478: 687b ldr r3, [r7, #4]
800047a: 789a ldrb r2, [r3, #2]
800047c: 4b0a ldr r3, [pc, #40] ; (80004a8 <ftcan_msg_received_cb+0x60>)
800047e: 709a strb r2, [r3, #2]
rxstate.pwmaggregat = data[3];
8000480: 687b ldr r3, [r7, #4]
8000482: 78da ldrb r2, [r3, #3]
8000484: 4b08 ldr r3, [pc, #32] ; (80004a8 <ftcan_msg_received_cb+0x60>)
8000486: 70da strb r2, [r3, #3]
rxstate.pwmpumps = data[4];
8000488: 687b ldr r3, [r7, #4]
800048a: 791a ldrb r2, [r3, #4]
800048c: 4b06 ldr r3, [pc, #24] ; (80004a8 <ftcan_msg_received_cb+0x60>)
800048e: 711a strb r2, [r3, #4]
rxstate.checksum = data[5];
8000490: 687b ldr r3, [r7, #4]
8000492: 795a ldrb r2, [r3, #5]
8000494: 4b04 ldr r3, [pc, #16] ; (80004a8 <ftcan_msg_received_cb+0x60>)
8000496: 715a strb r2, [r3, #5]
}
}
8000498: bf00 nop
800049a: 3714 adds r7, #20
800049c: 46bd mov sp, r7
800049e: f85d 7b04 ldr.w r7, [sp], #4
80004a2: 4770 bx lr
80004a4: 20000032 .word 0x20000032
80004a8: 2000002c .word 0x2000002c
080004ac <ChannelControl_init>:
uint8_t timer2_running = 0;
TIM_HandleTypeDef* pwmtimer1;
TIM_HandleTypeDef* pwmtimer2;
void ChannelControl_init(I2C_HandleTypeDef* hi2c, TIM_HandleTypeDef* timer3, TIM_HandleTypeDef* timer2)
{
80004ac: b580 push {r7, lr}
80004ae: b084 sub sp, #16
80004b0: af00 add r7, sp, #0
80004b2: 60f8 str r0, [r7, #12]
80004b4: 60b9 str r1, [r7, #8]
80004b6: 607a str r2, [r7, #4]
pwmtimer1 = timer3;
80004b8: 4a18 ldr r2, [pc, #96] ; (800051c <ChannelControl_init+0x70>)
80004ba: 68bb ldr r3, [r7, #8]
80004bc: 6013 str r3, [r2, #0]
pwmtimer2 = timer2;
80004be: 4a18 ldr r2, [pc, #96] ; (8000520 <ChannelControl_init+0x74>)
80004c0: 687b ldr r3, [r7, #4]
80004c2: 6013 str r3, [r2, #0]
PCA9535_init(hi2c, 0);
80004c4: 2100 movs r1, #0
80004c6: 68f8 ldr r0, [r7, #12]
80004c8: f000 f99a bl 8000800 <PCA9535_init>
PCA9535_setGPIOPortOutput(PC9535_PORTA, 0x00);
80004cc: 2100 movs r1, #0
80004ce: 2000 movs r0, #0
80004d0: f000 fa00 bl 80008d4 <PCA9535_setGPIOPortOutput>
PCA9535_setGPIOPortOutput(PC9535_PORTB, 0x00);
80004d4: 2100 movs r1, #0
80004d6: 2001 movs r0, #1
80004d8: f000 f9fc bl 80008d4 <PCA9535_setGPIOPortOutput>
PCA9535_setGPIOPortDirection(PC9535_PORTA, 0x00);
80004dc: 2100 movs r1, #0
80004de: 2000 movs r0, #0
80004e0: f000 f9c2 bl 8000868 <PCA9535_setGPIOPortDirection>
PCA9535_setGPIOPortDirection(PC9535_PORTB, 0x00);
80004e4: 2100 movs r1, #0
80004e6: 2001 movs r0, #1
80004e8: f000 f9be bl 8000868 <PCA9535_setGPIOPortDirection>
EN_Ports.porta.porta = 0;
80004ec: 4b0d ldr r3, [pc, #52] ; (8000524 <ChannelControl_init+0x78>)
80004ee: 2200 movs r2, #0
80004f0: 701a strb r2, [r3, #0]
EN_Ports.portb.portb = 0;
80004f2: 4b0c ldr r3, [pc, #48] ; (8000524 <ChannelControl_init+0x78>)
80004f4: 2200 movs r2, #0
80004f6: 705a strb r2, [r3, #1]
EN_Ports.porta.alwayson = 1;
80004f8: 4a0a ldr r2, [pc, #40] ; (8000524 <ChannelControl_init+0x78>)
80004fa: 7813 ldrb r3, [r2, #0]
80004fc: f043 0308 orr.w r3, r3, #8
8000500: 7013 strb r3, [r2, #0]
ChannelControl_UpdateGPIOs(EN_Ports);
8000502: 4b08 ldr r3, [pc, #32] ; (8000524 <ChannelControl_init+0x78>)
8000504: 8818 ldrh r0, [r3, #0]
8000506: f000 f80f bl 8000528 <ChannelControl_UpdateGPIOs>
ChannelControl_UpdatePWMs(0,0,0);
800050a: 2200 movs r2, #0
800050c: 2100 movs r1, #0
800050e: 2000 movs r0, #0
8000510: f000 f826 bl 8000560 <ChannelControl_UpdatePWMs>
}
8000514: bf00 nop
8000516: 3710 adds r7, #16
8000518: 46bd mov sp, r7
800051a: bd80 pop {r7, pc}
800051c: 20000038 .word 0x20000038
8000520: 2000003c .word 0x2000003c
8000524: 20000034 .word 0x20000034
08000528 <ChannelControl_UpdateGPIOs>:
void ChannelControl_UpdateGPIOs(PortExtenderGPIO UpdatePorts)
{
8000528: b580 push {r7, lr}
800052a: b082 sub sp, #8
800052c: af00 add r7, sp, #0
800052e: 80b8 strh r0, [r7, #4]
EN_Ports = UpdatePorts;
8000530: 4a0a ldr r2, [pc, #40] ; (800055c <ChannelControl_UpdateGPIOs+0x34>)
8000532: 88bb ldrh r3, [r7, #4]
8000534: 8013 strh r3, [r2, #0]
UpdatePorts.porta.alwayson = 1; //Always on stays always on
8000536: 793b ldrb r3, [r7, #4]
8000538: f043 0308 orr.w r3, r3, #8
800053c: 713b strb r3, [r7, #4]
PCA9535_setGPIOPortOutput(PC9535_PORTA, UpdatePorts.porta.porta);
800053e: 793b ldrb r3, [r7, #4]
8000540: 4619 mov r1, r3
8000542: 2000 movs r0, #0
8000544: f000 f9c6 bl 80008d4 <PCA9535_setGPIOPortOutput>
PCA9535_setGPIOPortOutput(PC9535_PORTB, UpdatePorts.portb.portb);
8000548: 797b ldrb r3, [r7, #5]
800054a: 4619 mov r1, r3
800054c: 2001 movs r0, #1
800054e: f000 f9c1 bl 80008d4 <PCA9535_setGPIOPortOutput>
}
8000552: bf00 nop
8000554: 3708 adds r7, #8
8000556: 46bd mov sp, r7
8000558: bd80 pop {r7, pc}
800055a: bf00 nop
800055c: 20000034 .word 0x20000034
08000560 <ChannelControl_UpdatePWMs>:
void ChannelControl_UpdatePWMs(uint8_t pwmfans, uint8_t pwmaggregat, uint8_t pwmpumps)
{
8000560: b580 push {r7, lr}
8000562: b082 sub sp, #8
8000564: af00 add r7, sp, #0
8000566: 4603 mov r3, r0
8000568: 71fb strb r3, [r7, #7]
800056a: 460b mov r3, r1
800056c: 71bb strb r3, [r7, #6]
800056e: 4613 mov r3, r2
8000570: 717b strb r3, [r7, #5]
pwmtimer1->Instance->CCR1 = pwmaggregat<<7;
8000572: 79bb ldrb r3, [r7, #6]
8000574: 01da lsls r2, r3, #7
8000576: 4b30 ldr r3, [pc, #192] ; (8000638 <ChannelControl_UpdatePWMs+0xd8>)
8000578: 681b ldr r3, [r3, #0]
800057a: 681b ldr r3, [r3, #0]
800057c: 635a str r2, [r3, #52] ; 0x34
pwmtimer1->Instance->CCR2 = pwmpumps<<8;
800057e: 797b ldrb r3, [r7, #5]
8000580: 021a lsls r2, r3, #8
8000582: 4b2d ldr r3, [pc, #180] ; (8000638 <ChannelControl_UpdatePWMs+0xd8>)
8000584: 681b ldr r3, [r3, #0]
8000586: 681b ldr r3, [r3, #0]
8000588: 639a str r2, [r3, #56] ; 0x38
pwmtimer2->Instance->CCR2 = pwmfans<<8;
800058a: 79fb ldrb r3, [r7, #7]
800058c: 021a lsls r2, r3, #8
800058e: 4b2b ldr r3, [pc, #172] ; (800063c <ChannelControl_UpdatePWMs+0xdc>)
8000590: 681b ldr r3, [r3, #0]
8000592: 681b ldr r3, [r3, #0]
8000594: 639a str r2, [r3, #56] ; 0x38
if(timer1_running)
8000596: 4b2a ldr r3, [pc, #168] ; (8000640 <ChannelControl_UpdatePWMs+0xe0>)
8000598: 781b ldrb r3, [r3, #0]
800059a: 2b00 cmp r3, #0
800059c: d015 beq.n 80005ca <ChannelControl_UpdatePWMs+0x6a>
{
if((pwmaggregat == 0) && (pwmpumps == 0))
800059e: 79bb ldrb r3, [r7, #6]
80005a0: 2b00 cmp r3, #0
80005a2: d127 bne.n 80005f4 <ChannelControl_UpdatePWMs+0x94>
80005a4: 797b ldrb r3, [r7, #5]
80005a6: 2b00 cmp r3, #0
80005a8: d124 bne.n 80005f4 <ChannelControl_UpdatePWMs+0x94>
{
timer1_running = 0;
80005aa: 4b25 ldr r3, [pc, #148] ; (8000640 <ChannelControl_UpdatePWMs+0xe0>)
80005ac: 2200 movs r2, #0
80005ae: 701a strb r2, [r3, #0]
HAL_TIM_PWM_Stop(pwmtimer1, TIM_CHANNEL_1);
80005b0: 4b21 ldr r3, [pc, #132] ; (8000638 <ChannelControl_UpdatePWMs+0xd8>)
80005b2: 681b ldr r3, [r3, #0]
80005b4: 2100 movs r1, #0
80005b6: 4618 mov r0, r3
80005b8: f006 f9d8 bl 800696c <HAL_TIM_PWM_Stop>
HAL_TIM_PWM_Stop(pwmtimer1, TIM_CHANNEL_2);
80005bc: 4b1e ldr r3, [pc, #120] ; (8000638 <ChannelControl_UpdatePWMs+0xd8>)
80005be: 681b ldr r3, [r3, #0]
80005c0: 2104 movs r1, #4
80005c2: 4618 mov r0, r3
80005c4: f006 f9d2 bl 800696c <HAL_TIM_PWM_Stop>
80005c8: e014 b.n 80005f4 <ChannelControl_UpdatePWMs+0x94>
}
}
else
{
if((pwmaggregat != 0) || (pwmpumps != 0))
80005ca: 79bb ldrb r3, [r7, #6]
80005cc: 2b00 cmp r3, #0
80005ce: d102 bne.n 80005d6 <ChannelControl_UpdatePWMs+0x76>
80005d0: 797b ldrb r3, [r7, #5]
80005d2: 2b00 cmp r3, #0
80005d4: d00e beq.n 80005f4 <ChannelControl_UpdatePWMs+0x94>
{
timer1_running = 1;
80005d6: 4b1a ldr r3, [pc, #104] ; (8000640 <ChannelControl_UpdatePWMs+0xe0>)
80005d8: 2201 movs r2, #1
80005da: 701a strb r2, [r3, #0]
HAL_TIM_PWM_Start(pwmtimer1, TIM_CHANNEL_1);
80005dc: 4b16 ldr r3, [pc, #88] ; (8000638 <ChannelControl_UpdatePWMs+0xd8>)
80005de: 681b ldr r3, [r3, #0]
80005e0: 2100 movs r1, #0
80005e2: 4618 mov r0, r3
80005e4: f006 f8c2 bl 800676c <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(pwmtimer1, TIM_CHANNEL_2);
80005e8: 4b13 ldr r3, [pc, #76] ; (8000638 <ChannelControl_UpdatePWMs+0xd8>)
80005ea: 681b ldr r3, [r3, #0]
80005ec: 2104 movs r1, #4
80005ee: 4618 mov r0, r3
80005f0: f006 f8bc bl 800676c <HAL_TIM_PWM_Start>
}
}
if(timer2_running)
80005f4: 4b13 ldr r3, [pc, #76] ; (8000644 <ChannelControl_UpdatePWMs+0xe4>)
80005f6: 781b ldrb r3, [r3, #0]
80005f8: 2b00 cmp r3, #0
80005fa: d00c beq.n 8000616 <ChannelControl_UpdatePWMs+0xb6>
{
if(pwmfans == 0)
80005fc: 79fb ldrb r3, [r7, #7]
80005fe: 2b00 cmp r3, #0
8000600: d115 bne.n 800062e <ChannelControl_UpdatePWMs+0xce>
{
timer2_running = 0;
8000602: 4b10 ldr r3, [pc, #64] ; (8000644 <ChannelControl_UpdatePWMs+0xe4>)
8000604: 2200 movs r2, #0
8000606: 701a strb r2, [r3, #0]
HAL_TIM_PWM_Stop(pwmtimer2, TIM_CHANNEL_2);
8000608: 4b0c ldr r3, [pc, #48] ; (800063c <ChannelControl_UpdatePWMs+0xdc>)
800060a: 681b ldr r3, [r3, #0]
800060c: 2104 movs r1, #4
800060e: 4618 mov r0, r3
8000610: f006 f9ac bl 800696c <HAL_TIM_PWM_Stop>
{
timer2_running = 1;
HAL_TIM_PWM_Start(pwmtimer2, TIM_CHANNEL_2);
}
}
}
8000614: e00b b.n 800062e <ChannelControl_UpdatePWMs+0xce>
if(pwmfans != 0)
8000616: 79fb ldrb r3, [r7, #7]
8000618: 2b00 cmp r3, #0
800061a: d008 beq.n 800062e <ChannelControl_UpdatePWMs+0xce>
timer2_running = 1;
800061c: 4b09 ldr r3, [pc, #36] ; (8000644 <ChannelControl_UpdatePWMs+0xe4>)
800061e: 2201 movs r2, #1
8000620: 701a strb r2, [r3, #0]
HAL_TIM_PWM_Start(pwmtimer2, TIM_CHANNEL_2);
8000622: 4b06 ldr r3, [pc, #24] ; (800063c <ChannelControl_UpdatePWMs+0xdc>)
8000624: 681b ldr r3, [r3, #0]
8000626: 2104 movs r1, #4
8000628: 4618 mov r0, r3
800062a: f006 f89f bl 800676c <HAL_TIM_PWM_Start>
}
800062e: bf00 nop
8000630: 3708 adds r7, #8
8000632: 46bd mov sp, r7
8000634: bd80 pop {r7, pc}
8000636: bf00 nop
8000638: 20000038 .word 0x20000038
800063c: 2000003c .word 0x2000003c
8000640: 20000036 .word 0x20000036
8000644: 20000037 .word 0x20000037
08000648 <currentMonitor_init>:
ADC_HandleTypeDef* adc1;
ADC_HandleTypeDef* adc2;
void currentMonitor_init(ADC_HandleTypeDef *hadc1, ADC_HandleTypeDef *hadc2, TIM_HandleTypeDef* trigtim)
{
8000648: b580 push {r7, lr}
800064a: b084 sub sp, #16
800064c: af00 add r7, sp, #0
800064e: 60f8 str r0, [r7, #12]
8000650: 60b9 str r1, [r7, #8]
8000652: 607a str r2, [r7, #4]
adc1 = hadc1;
8000654: 4a0b ldr r2, [pc, #44] ; (8000684 <currentMonitor_init+0x3c>)
8000656: 68fb ldr r3, [r7, #12]
8000658: 6013 str r3, [r2, #0]
adc2 = hadc2;
800065a: 4a0b ldr r2, [pc, #44] ; (8000688 <currentMonitor_init+0x40>)
800065c: 68bb ldr r3, [r7, #8]
800065e: 6013 str r3, [r2, #0]
HAL_TIM_Base_Start(trigtim);
8000660: 6878 ldr r0, [r7, #4]
8000662: f005 ffbf bl 80065e4 <HAL_TIM_Base_Start>
HAL_ADC_Start_DMA(hadc1,(uint32_t*) adc_channels1.adcbuffer, 7);
8000666: 2207 movs r2, #7
8000668: 4908 ldr r1, [pc, #32] ; (800068c <currentMonitor_init+0x44>)
800066a: 68f8 ldr r0, [r7, #12]
800066c: f001 ff4c bl 8002508 <HAL_ADC_Start_DMA>
HAL_ADC_Start_DMA(hadc2,(uint32_t*) adc_channels2.adcbuffer, 7);
8000670: 2207 movs r2, #7
8000672: 4907 ldr r1, [pc, #28] ; (8000690 <currentMonitor_init+0x48>)
8000674: 68b8 ldr r0, [r7, #8]
8000676: f001 ff47 bl 8002508 <HAL_ADC_Start_DMA>
}
800067a: bf00 nop
800067c: 3710 adds r7, #16
800067e: 46bd mov sp, r7
8000680: bd80 pop {r7, pc}
8000682: bf00 nop
8000684: 20000080 .word 0x20000080
8000688: 20000084 .word 0x20000084
800068c: 20000040 .word 0x20000040
8000690: 20000050 .word 0x20000050
08000694 <currentMonitor_checklimits>:
uint8_t currentMonitor_checklimits()
{
8000694: b480 push {r7}
8000696: af00 add r7, sp, #0
return 0;
8000698: 2300 movs r3, #0
}
800069a: 4618 mov r0, r3
800069c: 46bd mov sp, r7
800069e: f85d 7b04 ldr.w r7, [sp], #4
80006a2: 4770 bx lr
080006a4 <HAL_ADC_ConvCpltCallback>:
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
{
80006a4: b580 push {r7, lr}
80006a6: b082 sub sp, #8
80006a8: af00 add r7, sp, #0
80006aa: 6078 str r0, [r7, #4]
if(hadc == adc2)
80006ac: 4b4c ldr r3, [pc, #304] ; (80007e0 <HAL_ADC_ConvCpltCallback+0x13c>)
80006ae: 681b ldr r3, [r3, #0]
80006b0: 687a ldr r2, [r7, #4]
80006b2: 429a cmp r2, r3
80006b4: d14b bne.n 800074e <HAL_ADC_ConvCpltCallback+0xaa>
{
if(adcbank2)
80006b6: 4b4b ldr r3, [pc, #300] ; (80007e4 <HAL_ADC_ConvCpltCallback+0x140>)
80006b8: 781b ldrb r3, [r3, #0]
80006ba: 2b00 cmp r3, #0
80006bc: d015 beq.n 80006ea <HAL_ADC_ConvCpltCallback+0x46>
{
adcbank2 = 0;
80006be: 4b49 ldr r3, [pc, #292] ; (80007e4 <HAL_ADC_ConvCpltCallback+0x140>)
80006c0: 2200 movs r2, #0
80006c2: 701a strb r2, [r3, #0]
HAL_GPIO_WritePin(Diagnose_Select2_GPIO_Port, Diagnose_Select2_Pin, GPIO_PIN_SET);
80006c4: 2201 movs r2, #1
80006c6: f44f 6100 mov.w r1, #2048 ; 0x800
80006ca: 4847 ldr r0, [pc, #284] ; (80007e8 <HAL_ADC_ConvCpltCallback+0x144>)
80006cc: f004 fb74 bl 8004db8 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(Diagnose_Select3_GPIO_Port, Diagnose_Select3_Pin, GPIO_PIN_SET);
80006d0: 2201 movs r2, #1
80006d2: f44f 4180 mov.w r1, #16384 ; 0x4000
80006d6: 4844 ldr r0, [pc, #272] ; (80007e8 <HAL_ADC_ConvCpltCallback+0x144>)
80006d8: f004 fb6e bl 8004db8 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(Diagnose_Select4_GPIO_Port, Diagnose_Select4_Pin, GPIO_PIN_SET);
80006dc: 2201 movs r2, #1
80006de: f44f 5100 mov.w r1, #8192 ; 0x2000
80006e2: 4841 ldr r0, [pc, #260] ; (80007e8 <HAL_ADC_ConvCpltCallback+0x144>)
80006e4: f004 fb68 bl 8004db8 <HAL_GPIO_WritePin>
80006e8: e014 b.n 8000714 <HAL_ADC_ConvCpltCallback+0x70>
}
else
{
adcbank2 = 1;
80006ea: 4b3e ldr r3, [pc, #248] ; (80007e4 <HAL_ADC_ConvCpltCallback+0x140>)
80006ec: 2201 movs r2, #1
80006ee: 701a strb r2, [r3, #0]
HAL_GPIO_WritePin(Diagnose_Select2_GPIO_Port, Diagnose_Select2_Pin, GPIO_PIN_RESET);
80006f0: 2200 movs r2, #0
80006f2: f44f 6100 mov.w r1, #2048 ; 0x800
80006f6: 483c ldr r0, [pc, #240] ; (80007e8 <HAL_ADC_ConvCpltCallback+0x144>)
80006f8: f004 fb5e bl 8004db8 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(Diagnose_Select3_GPIO_Port, Diagnose_Select3_Pin, GPIO_PIN_RESET);
80006fc: 2200 movs r2, #0
80006fe: f44f 4180 mov.w r1, #16384 ; 0x4000
8000702: 4839 ldr r0, [pc, #228] ; (80007e8 <HAL_ADC_ConvCpltCallback+0x144>)
8000704: f004 fb58 bl 8004db8 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(Diagnose_Select4_GPIO_Port, Diagnose_Select4_Pin, GPIO_PIN_RESET);
8000708: 2200 movs r2, #0
800070a: f44f 5100 mov.w r1, #8192 ; 0x2000
800070e: 4836 ldr r0, [pc, #216] ; (80007e8 <HAL_ADC_ConvCpltCallback+0x144>)
8000710: f004 fb52 bl 8004db8 <HAL_GPIO_WritePin>
}
if(adcbank2 == 1)
8000714: 4b33 ldr r3, [pc, #204] ; (80007e4 <HAL_ADC_ConvCpltCallback+0x140>)
8000716: 781b ldrb r3, [r3, #0]
8000718: 2b01 cmp r3, #1
800071a: d10c bne.n 8000736 <HAL_ADC_ConvCpltCallback+0x92>
{
current_measurements_adc_val.always_on = adc_channels2.adcbank1.isense10;
800071c: 4b33 ldr r3, [pc, #204] ; (80007ec <HAL_ADC_ConvCpltCallback+0x148>)
800071e: 885a ldrh r2, [r3, #2]
8000720: 4b33 ldr r3, [pc, #204] ; (80007f0 <HAL_ADC_ConvCpltCallback+0x14c>)
8000722: 825a strh r2, [r3, #18]
current_measurements_adc_val.modevalve_1 = adc_channels2.adcbank1.isense5;
8000724: 4b31 ldr r3, [pc, #196] ; (80007ec <HAL_ADC_ConvCpltCallback+0x148>)
8000726: 889a ldrh r2, [r3, #4]
8000728: 4b31 ldr r3, [pc, #196] ; (80007f0 <HAL_ADC_ConvCpltCallback+0x14c>)
800072a: 82da strh r2, [r3, #22]
current_measurements_adc_val.ebsvalve_1 = adc_channels2.adcbank1.isense4;
800072c: 4b2f ldr r3, [pc, #188] ; (80007ec <HAL_ADC_ConvCpltCallback+0x148>)
800072e: 88da ldrh r2, [r3, #6]
8000730: 4b2f ldr r3, [pc, #188] ; (80007f0 <HAL_ADC_ConvCpltCallback+0x14c>)
8000732: 835a strh r2, [r3, #26]
8000734: e00b b.n 800074e <HAL_ADC_ConvCpltCallback+0xaa>
}
else
{
current_measurements_adc_val.shutdown_circuit = adc_channels2.adcbank1.isense10;
8000736: 4b2d ldr r3, [pc, #180] ; (80007ec <HAL_ADC_ConvCpltCallback+0x148>)
8000738: 885a ldrh r2, [r3, #2]
800073a: 4b2d ldr r3, [pc, #180] ; (80007f0 <HAL_ADC_ConvCpltCallback+0x14c>)
800073c: 829a strh r2, [r3, #20]
current_measurements_adc_val.modevalve_2 = adc_channels2.adcbank1.isense5;
800073e: 4b2b ldr r3, [pc, #172] ; (80007ec <HAL_ADC_ConvCpltCallback+0x148>)
8000740: 889a ldrh r2, [r3, #4]
8000742: 4b2b ldr r3, [pc, #172] ; (80007f0 <HAL_ADC_ConvCpltCallback+0x14c>)
8000744: 831a strh r2, [r3, #24]
current_measurements_adc_val.ebsvalve_2 = adc_channels2.adcbank1.isense4;
8000746: 4b29 ldr r3, [pc, #164] ; (80007ec <HAL_ADC_ConvCpltCallback+0x148>)
8000748: 88da ldrh r2, [r3, #6]
800074a: 4b29 ldr r3, [pc, #164] ; (80007f0 <HAL_ADC_ConvCpltCallback+0x14c>)
800074c: 839a strh r2, [r3, #28]
}
}
if(hadc == adc1)
800074e: 4b29 ldr r3, [pc, #164] ; (80007f4 <HAL_ADC_ConvCpltCallback+0x150>)
8000750: 681b ldr r3, [r3, #0]
8000752: 687a ldr r2, [r7, #4]
8000754: 429a cmp r2, r3
8000756: d13f bne.n 80007d8 <HAL_ADC_ConvCpltCallback+0x134>
{
if(adcbank1)
8000758: 4b27 ldr r3, [pc, #156] ; (80007f8 <HAL_ADC_ConvCpltCallback+0x154>)
800075a: 781b ldrb r3, [r3, #0]
800075c: 2b00 cmp r3, #0
800075e: d009 beq.n 8000774 <HAL_ADC_ConvCpltCallback+0xd0>
{
adcbank1 = 0;
8000760: 4b25 ldr r3, [pc, #148] ; (80007f8 <HAL_ADC_ConvCpltCallback+0x154>)
8000762: 2200 movs r2, #0
8000764: 701a strb r2, [r3, #0]
HAL_GPIO_WritePin(Diagnose_Select1_GPIO_Port, Diagnose_Select1_Pin, GPIO_PIN_SET);
8000766: 2201 movs r2, #1
8000768: f44f 5180 mov.w r1, #4096 ; 0x1000
800076c: 481e ldr r0, [pc, #120] ; (80007e8 <HAL_ADC_ConvCpltCallback+0x144>)
800076e: f004 fb23 bl 8004db8 <HAL_GPIO_WritePin>
8000772: e008 b.n 8000786 <HAL_ADC_ConvCpltCallback+0xe2>
}
else
{
adcbank1 = 1;
8000774: 4b20 ldr r3, [pc, #128] ; (80007f8 <HAL_ADC_ConvCpltCallback+0x154>)
8000776: 2201 movs r2, #1
8000778: 701a strb r2, [r3, #0]
HAL_GPIO_WritePin(Diagnose_Select1_GPIO_Port, Diagnose_Select1_Pin, GPIO_PIN_RESET);
800077a: 2200 movs r2, #0
800077c: f44f 5180 mov.w r1, #4096 ; 0x1000
8000780: 4819 ldr r0, [pc, #100] ; (80007e8 <HAL_ADC_ConvCpltCallback+0x144>)
8000782: f004 fb19 bl 8004db8 <HAL_GPIO_WritePin>
}
current_measurements_adc_val.servicebrake = adc_channels1.adcbank1.isense3;
8000786: 4b1d ldr r3, [pc, #116] ; (80007fc <HAL_ADC_ConvCpltCallback+0x158>)
8000788: 88da ldrh r2, [r3, #6]
800078a: 4b19 ldr r3, [pc, #100] ; (80007f0 <HAL_ADC_ConvCpltCallback+0x14c>)
800078c: 801a strh r2, [r3, #0]
current_measurements_adc_val.sensorbox = adc_channels1.adcbank1.isense2;
800078e: 4b1b ldr r3, [pc, #108] ; (80007fc <HAL_ADC_ConvCpltCallback+0x158>)
8000790: 889a ldrh r2, [r3, #4]
8000792: 4b17 ldr r3, [pc, #92] ; (80007f0 <HAL_ADC_ConvCpltCallback+0x14c>)
8000794: 805a strh r2, [r3, #2]
current_measurements_adc_val.fans = adc_channels2.adcbank1.isense6;
8000796: 4b15 ldr r3, [pc, #84] ; (80007ec <HAL_ADC_ConvCpltCallback+0x148>)
8000798: 899a ldrh r2, [r3, #12]
800079a: 4b15 ldr r3, [pc, #84] ; (80007f0 <HAL_ADC_ConvCpltCallback+0x14c>)
800079c: 809a strh r2, [r3, #4]
current_measurements_adc_val.aggregat = adc_channels2.adcbank1.isense1;
800079e: 4b13 ldr r3, [pc, #76] ; (80007ec <HAL_ADC_ConvCpltCallback+0x148>)
80007a0: 891a ldrh r2, [r3, #8]
80007a2: 4b13 ldr r3, [pc, #76] ; (80007f0 <HAL_ADC_ConvCpltCallback+0x14c>)
80007a4: 80da strh r2, [r3, #6]
current_measurements_adc_val.inverter = adc_channels2.adcbank1.isense11;
80007a6: 4b11 ldr r3, [pc, #68] ; (80007ec <HAL_ADC_ConvCpltCallback+0x148>)
80007a8: 881a ldrh r2, [r3, #0]
80007aa: 4b11 ldr r3, [pc, #68] ; (80007f0 <HAL_ADC_ConvCpltCallback+0x14c>)
80007ac: 811a strh r2, [r3, #8]
current_measurements_adc_val.pumps = adc_channels1.adcbank1.isense9;
80007ae: 4b13 ldr r3, [pc, #76] ; (80007fc <HAL_ADC_ConvCpltCallback+0x158>)
80007b0: 881a ldrh r2, [r3, #0]
80007b2: 4b0f ldr r3, [pc, #60] ; (80007f0 <HAL_ADC_ConvCpltCallback+0x14c>)
80007b4: 815a strh r2, [r3, #10]
current_measurements_adc_val.steering = adc_channels2.adcbank1.isense7;
80007b6: 4b0d ldr r3, [pc, #52] ; (80007ec <HAL_ADC_ConvCpltCallback+0x148>)
80007b8: 895a ldrh r2, [r3, #10]
80007ba: 4b0d ldr r3, [pc, #52] ; (80007f0 <HAL_ADC_ConvCpltCallback+0x14c>)
80007bc: 819a strh r2, [r3, #12]
if(adcbank1 == 1)
80007be: 4b0e ldr r3, [pc, #56] ; (80007f8 <HAL_ADC_ConvCpltCallback+0x154>)
80007c0: 781b ldrb r3, [r3, #0]
80007c2: 2b01 cmp r3, #1
80007c4: d104 bne.n 80007d0 <HAL_ADC_ConvCpltCallback+0x12c>
{
current_measurements_adc_val.misc = adc_channels1.adcbank1.isense8;
80007c6: 4b0d ldr r3, [pc, #52] ; (80007fc <HAL_ADC_ConvCpltCallback+0x158>)
80007c8: 885a ldrh r2, [r3, #2]
80007ca: 4b09 ldr r3, [pc, #36] ; (80007f0 <HAL_ADC_ConvCpltCallback+0x14c>)
80007cc: 821a strh r2, [r3, #16]
current_measurements_adc_val.servos = adc_channels1.adcbank1.isense8;
}
}
}
80007ce: e003 b.n 80007d8 <HAL_ADC_ConvCpltCallback+0x134>
current_measurements_adc_val.servos = adc_channels1.adcbank1.isense8;
80007d0: 4b0a ldr r3, [pc, #40] ; (80007fc <HAL_ADC_ConvCpltCallback+0x158>)
80007d2: 885a ldrh r2, [r3, #2]
80007d4: 4b06 ldr r3, [pc, #24] ; (80007f0 <HAL_ADC_ConvCpltCallback+0x14c>)
80007d6: 81da strh r2, [r3, #14]
}
80007d8: bf00 nop
80007da: 3708 adds r7, #8
80007dc: 46bd mov sp, r7
80007de: bd80 pop {r7, pc}
80007e0: 20000084 .word 0x20000084
80007e4: 2000007f .word 0x2000007f
80007e8: 48000400 .word 0x48000400
80007ec: 20000050 .word 0x20000050
80007f0: 20000060 .word 0x20000060
80007f4: 20000080 .word 0x20000080
80007f8: 2000007e .word 0x2000007e
80007fc: 20000040 .word 0x20000040
08000800 <PCA9535_init>:
* @param subaddress of the port expander
* @retval none
*/
void PCA9535_init(I2C_HandleTypeDef* hi2c, uint8_t subadr)
{
8000800: b580 push {r7, lr}
8000802: b086 sub sp, #24
8000804: af02 add r7, sp, #8
8000806: 6078 str r0, [r7, #4]
8000808: 460b mov r3, r1
800080a: 70fb strb r3, [r7, #3]
pcai2c = hi2c;
800080c: 4a13 ldr r2, [pc, #76] ; (800085c <PCA9535_init+0x5c>)
800080e: 687b ldr r3, [r7, #4]
8000810: 6013 str r3, [r2, #0]
deviceadr = PCA_I2C_BASE_ADDRESS | (subadr << 1);
8000812: 78fb ldrb r3, [r7, #3]
8000814: 005b lsls r3, r3, #1
8000816: b25b sxtb r3, r3
8000818: f043 0340 orr.w r3, r3, #64 ; 0x40
800081c: b25b sxtb r3, r3
800081e: b2da uxtb r2, r3
8000820: 4b0f ldr r3, [pc, #60] ; (8000860 <PCA9535_init+0x60>)
8000822: 701a strb r2, [r3, #0]
uint8_t initalizationconfig[7] = {0x02, 0x00,0x00,0x00,0x00,0xFF,0xFF};
8000824: 4a0f ldr r2, [pc, #60] ; (8000864 <PCA9535_init+0x64>)
8000826: f107 0308 add.w r3, r7, #8
800082a: e892 0003 ldmia.w r2, {r0, r1}
800082e: 6018 str r0, [r3, #0]
8000830: 3304 adds r3, #4
8000832: 8019 strh r1, [r3, #0]
8000834: 3302 adds r3, #2
8000836: 0c0a lsrs r2, r1, #16
8000838: 701a strb r2, [r3, #0]
HAL_I2C_Master_Transmit(pcai2c, deviceadr, initalizationconfig, 7, 1000);
800083a: 4b08 ldr r3, [pc, #32] ; (800085c <PCA9535_init+0x5c>)
800083c: 6818 ldr r0, [r3, #0]
800083e: 4b08 ldr r3, [pc, #32] ; (8000860 <PCA9535_init+0x60>)
8000840: 781b ldrb r3, [r3, #0]
8000842: b299 uxth r1, r3
8000844: f107 0208 add.w r2, r7, #8
8000848: f44f 737a mov.w r3, #1000 ; 0x3e8
800084c: 9300 str r3, [sp, #0]
800084e: 2307 movs r3, #7
8000850: f004 fb5a bl 8004f08 <HAL_I2C_Master_Transmit>
}
8000854: bf00 nop
8000856: 3710 adds r7, #16
8000858: 46bd mov sp, r7
800085a: bd80 pop {r7, pc}
800085c: 20000088 .word 0x20000088
8000860: 2000008c .word 0x2000008c
8000864: 08007ca8 .word 0x08007ca8
08000868 <PCA9535_setGPIOPortDirection>:
reval = reval >> (pin);
return reval;
}
void PCA9535_setGPIOPortDirection(uint8_t Port, uint8_t bitmask)
{
8000868: b580 push {r7, lr}
800086a: b086 sub sp, #24
800086c: af02 add r7, sp, #8
800086e: 4603 mov r3, r0
8000870: 460a mov r2, r1
8000872: 71fb strb r3, [r7, #7]
8000874: 4613 mov r3, r2
8000876: 71bb strb r3, [r7, #6]
uint8_t command[2] = {0x00, bitmask};
8000878: 2300 movs r3, #0
800087a: 733b strb r3, [r7, #12]
800087c: 79bb ldrb r3, [r7, #6]
800087e: 737b strb r3, [r7, #13]
if(Port == PC9535_PORTA)
8000880: 79fb ldrb r3, [r7, #7]
8000882: 2b00 cmp r3, #0
8000884: d105 bne.n 8000892 <PCA9535_setGPIOPortDirection+0x2a>
{
gpioa_shadow_reg_dir = bitmask;
8000886: 4a0f ldr r2, [pc, #60] ; (80008c4 <PCA9535_setGPIOPortDirection+0x5c>)
8000888: 79bb ldrb r3, [r7, #6]
800088a: 7013 strb r3, [r2, #0]
command[0] = CONFIGURATION_REG_BASE_ADDRESS;
800088c: 2306 movs r3, #6
800088e: 733b strb r3, [r7, #12]
8000890: e007 b.n 80008a2 <PCA9535_setGPIOPortDirection+0x3a>
}
else if(Port == PC9535_PORTB)
8000892: 79fb ldrb r3, [r7, #7]
8000894: 2b01 cmp r3, #1
8000896: d104 bne.n 80008a2 <PCA9535_setGPIOPortDirection+0x3a>
{
gpiob_shadow_reg_dir = bitmask;
8000898: 4a0b ldr r2, [pc, #44] ; (80008c8 <PCA9535_setGPIOPortDirection+0x60>)
800089a: 79bb ldrb r3, [r7, #6]
800089c: 7013 strb r3, [r2, #0]
command[0] = CONFIGURATION_REG_BASE_ADDRESS | 1;
800089e: 2307 movs r3, #7
80008a0: 733b strb r3, [r7, #12]
}
HAL_I2C_Master_Transmit(pcai2c, deviceadr, command, 2, 1000);
80008a2: 4b0a ldr r3, [pc, #40] ; (80008cc <PCA9535_setGPIOPortDirection+0x64>)
80008a4: 6818 ldr r0, [r3, #0]
80008a6: 4b0a ldr r3, [pc, #40] ; (80008d0 <PCA9535_setGPIOPortDirection+0x68>)
80008a8: 781b ldrb r3, [r3, #0]
80008aa: b299 uxth r1, r3
80008ac: f107 020c add.w r2, r7, #12
80008b0: f44f 737a mov.w r3, #1000 ; 0x3e8
80008b4: 9300 str r3, [sp, #0]
80008b6: 2302 movs r3, #2
80008b8: f004 fb26 bl 8004f08 <HAL_I2C_Master_Transmit>
}
80008bc: bf00 nop
80008be: 3710 adds r7, #16
80008c0: 46bd mov sp, r7
80008c2: bd80 pop {r7, pc}
80008c4: 20000000 .word 0x20000000
80008c8: 20000001 .word 0x20000001
80008cc: 20000088 .word 0x20000088
80008d0: 2000008c .word 0x2000008c
080008d4 <PCA9535_setGPIOPortOutput>:
void PCA9535_setGPIOPortOutput(uint8_t Port, uint8_t bitmask)
{
80008d4: b580 push {r7, lr}
80008d6: b086 sub sp, #24
80008d8: af02 add r7, sp, #8
80008da: 4603 mov r3, r0
80008dc: 460a mov r2, r1
80008de: 71fb strb r3, [r7, #7]
80008e0: 4613 mov r3, r2
80008e2: 71bb strb r3, [r7, #6]
uint8_t command[2] = {0x00, bitmask};
80008e4: 2300 movs r3, #0
80008e6: 733b strb r3, [r7, #12]
80008e8: 79bb ldrb r3, [r7, #6]
80008ea: 737b strb r3, [r7, #13]
if(Port == PC9535_PORTA)
80008ec: 79fb ldrb r3, [r7, #7]
80008ee: 2b00 cmp r3, #0
80008f0: d105 bne.n 80008fe <PCA9535_setGPIOPortOutput+0x2a>
{
gpioa_shadow_reg_out = bitmask;
80008f2: 4a0f ldr r2, [pc, #60] ; (8000930 <PCA9535_setGPIOPortOutput+0x5c>)
80008f4: 79bb ldrb r3, [r7, #6]
80008f6: 7013 strb r3, [r2, #0]
command[0] = OUTPUT_REG_BASE_ADDRESS;
80008f8: 2302 movs r3, #2
80008fa: 733b strb r3, [r7, #12]
80008fc: e007 b.n 800090e <PCA9535_setGPIOPortOutput+0x3a>
}
else if(Port == PC9535_PORTB)
80008fe: 79fb ldrb r3, [r7, #7]
8000900: 2b01 cmp r3, #1
8000902: d104 bne.n 800090e <PCA9535_setGPIOPortOutput+0x3a>
{
gpiob_shadow_reg_out = bitmask;
8000904: 4a0b ldr r2, [pc, #44] ; (8000934 <PCA9535_setGPIOPortOutput+0x60>)
8000906: 79bb ldrb r3, [r7, #6]
8000908: 7013 strb r3, [r2, #0]
command[0] = OUTPUT_REG_BASE_ADDRESS | 1;
800090a: 2303 movs r3, #3
800090c: 733b strb r3, [r7, #12]
}
HAL_I2C_Master_Transmit(pcai2c, deviceadr, command, 2, 1000);
800090e: 4b0a ldr r3, [pc, #40] ; (8000938 <PCA9535_setGPIOPortOutput+0x64>)
8000910: 6818 ldr r0, [r3, #0]
8000912: 4b0a ldr r3, [pc, #40] ; (800093c <PCA9535_setGPIOPortOutput+0x68>)
8000914: 781b ldrb r3, [r3, #0]
8000916: b299 uxth r1, r3
8000918: f107 020c add.w r2, r7, #12
800091c: f44f 737a mov.w r3, #1000 ; 0x3e8
8000920: 9300 str r3, [sp, #0]
8000922: 2302 movs r3, #2
8000924: f004 faf0 bl 8004f08 <HAL_I2C_Master_Transmit>
}
8000928: bf00 nop
800092a: 3710 adds r7, #16
800092c: 46bd mov sp, r7
800092e: bd80 pop {r7, pc}
8000930: 2000008d .word 0x2000008d
8000934: 2000008e .word 0x2000008e
8000938: 20000088 .word 0x20000088
800093c: 2000008c .word 0x2000008c
08000940 <ftcan_init>:
ftcan_msg_received_cb(header.StdId, header.DLC, data);
}
#elif defined(FTCAN_IS_FDCAN)
static FDCAN_HandleTypeDef *hcan;
HAL_StatusTypeDef ftcan_init(FDCAN_HandleTypeDef *handle) {
8000940: b580 push {r7, lr}
8000942: b086 sub sp, #24
8000944: af02 add r7, sp, #8
8000946: 6078 str r0, [r7, #4]
hcan = handle;
8000948: 4a15 ldr r2, [pc, #84] ; (80009a0 <ftcan_init+0x60>)
800094a: 687b ldr r3, [r7, #4]
800094c: 6013 str r3, [r2, #0]
HAL_StatusTypeDef status =
HAL_FDCAN_ActivateNotification(hcan, FDCAN_IT_RX_FIFO0_NEW_MESSAGE, 0);
800094e: 4b14 ldr r3, [pc, #80] ; (80009a0 <ftcan_init+0x60>)
8000950: 681b ldr r3, [r3, #0]
8000952: 2200 movs r2, #0
8000954: 2101 movs r1, #1
8000956: 4618 mov r0, r3
8000958: f003 fd52 bl 8004400 <HAL_FDCAN_ActivateNotification>
800095c: 4603 mov r3, r0
800095e: 73fb strb r3, [r7, #15]
if (status != HAL_OK) {
8000960: 7bfb ldrb r3, [r7, #15]
8000962: 2b00 cmp r3, #0
8000964: d001 beq.n 800096a <ftcan_init+0x2a>
return status;
8000966: 7bfb ldrb r3, [r7, #15]
8000968: e015 b.n 8000996 <ftcan_init+0x56>
}
// Reject non-matching messages
status =
HAL_FDCAN_ConfigGlobalFilter(hcan, FDCAN_REJECT, FDCAN_REJECT,
800096a: 4b0d ldr r3, [pc, #52] ; (80009a0 <ftcan_init+0x60>)
800096c: 6818 ldr r0, [r3, #0]
800096e: 2301 movs r3, #1
8000970: 9300 str r3, [sp, #0]
8000972: 2301 movs r3, #1
8000974: 2202 movs r2, #2
8000976: 2102 movs r1, #2
8000978: f003 fbca bl 8004110 <HAL_FDCAN_ConfigGlobalFilter>
800097c: 4603 mov r3, r0
800097e: 73fb strb r3, [r7, #15]
FDCAN_REJECT_REMOTE, FDCAN_REJECT_REMOTE);
if (status != HAL_OK) {
8000980: 7bfb ldrb r3, [r7, #15]
8000982: 2b00 cmp r3, #0
8000984: d001 beq.n 800098a <ftcan_init+0x4a>
return status;
8000986: 7bfb ldrb r3, [r7, #15]
8000988: e005 b.n 8000996 <ftcan_init+0x56>
}
return HAL_FDCAN_Start(hcan);
800098a: 4b05 ldr r3, [pc, #20] ; (80009a0 <ftcan_init+0x60>)
800098c: 681b ldr r3, [r3, #0]
800098e: 4618 mov r0, r3
8000990: f003 fbef bl 8004172 <HAL_FDCAN_Start>
8000994: 4603 mov r3, r0
}
8000996: 4618 mov r0, r3
8000998: 3710 adds r7, #16
800099a: 46bd mov sp, r7
800099c: bd80 pop {r7, pc}
800099e: bf00 nop
80009a0: 20000090 .word 0x20000090
080009a4 <ftcan_transmit>:
HAL_StatusTypeDef ftcan_transmit(uint16_t id, uint8_t *data,
size_t datalen) {
80009a4: b580 push {r7, lr}
80009a6: b084 sub sp, #16
80009a8: af00 add r7, sp, #0
80009aa: 4603 mov r3, r0
80009ac: 60b9 str r1, [r7, #8]
80009ae: 607a str r2, [r7, #4]
80009b0: 81fb strh r3, [r7, #14]
static FDCAN_TxHeaderTypeDef header;
header.Identifier = id;
80009b2: 89fb ldrh r3, [r7, #14]
80009b4: 4a31 ldr r2, [pc, #196] ; (8000a7c <ftcan_transmit+0xd8>)
80009b6: 6013 str r3, [r2, #0]
header.IdType = FDCAN_STANDARD_ID;
80009b8: 4b30 ldr r3, [pc, #192] ; (8000a7c <ftcan_transmit+0xd8>)
80009ba: 2200 movs r2, #0
80009bc: 605a str r2, [r3, #4]
header.TxFrameType = FDCAN_DATA_FRAME;
80009be: 4b2f ldr r3, [pc, #188] ; (8000a7c <ftcan_transmit+0xd8>)
80009c0: 2200 movs r2, #0
80009c2: 609a str r2, [r3, #8]
switch (datalen) {
80009c4: 687b ldr r3, [r7, #4]
80009c6: 2b07 cmp r3, #7
80009c8: d839 bhi.n 8000a3e <ftcan_transmit+0x9a>
80009ca: a201 add r2, pc, #4 ; (adr r2, 80009d0 <ftcan_transmit+0x2c>)
80009cc: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80009d0: 080009f1 .word 0x080009f1
80009d4: 080009f9 .word 0x080009f9
80009d8: 08000a03 .word 0x08000a03
80009dc: 08000a0d .word 0x08000a0d
80009e0: 08000a17 .word 0x08000a17
80009e4: 08000a21 .word 0x08000a21
80009e8: 08000a2b .word 0x08000a2b
80009ec: 08000a35 .word 0x08000a35
case 0:
header.DataLength = FDCAN_DLC_BYTES_0;
80009f0: 4b22 ldr r3, [pc, #136] ; (8000a7c <ftcan_transmit+0xd8>)
80009f2: 2200 movs r2, #0
80009f4: 60da str r2, [r3, #12]
break;
80009f6: e027 b.n 8000a48 <ftcan_transmit+0xa4>
case 1:
header.DataLength = FDCAN_DLC_BYTES_1;
80009f8: 4b20 ldr r3, [pc, #128] ; (8000a7c <ftcan_transmit+0xd8>)
80009fa: f44f 3280 mov.w r2, #65536 ; 0x10000
80009fe: 60da str r2, [r3, #12]
break;
8000a00: e022 b.n 8000a48 <ftcan_transmit+0xa4>
case 2:
header.DataLength = FDCAN_DLC_BYTES_2;
8000a02: 4b1e ldr r3, [pc, #120] ; (8000a7c <ftcan_transmit+0xd8>)
8000a04: f44f 3200 mov.w r2, #131072 ; 0x20000
8000a08: 60da str r2, [r3, #12]
break;
8000a0a: e01d b.n 8000a48 <ftcan_transmit+0xa4>
case 3:
header.DataLength = FDCAN_DLC_BYTES_3;
8000a0c: 4b1b ldr r3, [pc, #108] ; (8000a7c <ftcan_transmit+0xd8>)
8000a0e: f44f 3240 mov.w r2, #196608 ; 0x30000
8000a12: 60da str r2, [r3, #12]
break;
8000a14: e018 b.n 8000a48 <ftcan_transmit+0xa4>
case 4:
header.DataLength = FDCAN_DLC_BYTES_4;
8000a16: 4b19 ldr r3, [pc, #100] ; (8000a7c <ftcan_transmit+0xd8>)
8000a18: f44f 2280 mov.w r2, #262144 ; 0x40000
8000a1c: 60da str r2, [r3, #12]
break;
8000a1e: e013 b.n 8000a48 <ftcan_transmit+0xa4>
case 5:
header.DataLength = FDCAN_DLC_BYTES_5;
8000a20: 4b16 ldr r3, [pc, #88] ; (8000a7c <ftcan_transmit+0xd8>)
8000a22: f44f 22a0 mov.w r2, #327680 ; 0x50000
8000a26: 60da str r2, [r3, #12]
break;
8000a28: e00e b.n 8000a48 <ftcan_transmit+0xa4>
case 6:
header.DataLength = FDCAN_DLC_BYTES_6;
8000a2a: 4b14 ldr r3, [pc, #80] ; (8000a7c <ftcan_transmit+0xd8>)
8000a2c: f44f 22c0 mov.w r2, #393216 ; 0x60000
8000a30: 60da str r2, [r3, #12]
break;
8000a32: e009 b.n 8000a48 <ftcan_transmit+0xa4>
case 7:
header.DataLength = FDCAN_DLC_BYTES_7;
8000a34: 4b11 ldr r3, [pc, #68] ; (8000a7c <ftcan_transmit+0xd8>)
8000a36: f44f 22e0 mov.w r2, #458752 ; 0x70000
8000a3a: 60da str r2, [r3, #12]
break;
8000a3c: e004 b.n 8000a48 <ftcan_transmit+0xa4>
case 8:
default:
header.DataLength = FDCAN_DLC_BYTES_8;
8000a3e: 4b0f ldr r3, [pc, #60] ; (8000a7c <ftcan_transmit+0xd8>)
8000a40: f44f 2200 mov.w r2, #524288 ; 0x80000
8000a44: 60da str r2, [r3, #12]
break;
8000a46: bf00 nop
}
header.ErrorStateIndicator = FDCAN_ESI_PASSIVE;
8000a48: 4b0c ldr r3, [pc, #48] ; (8000a7c <ftcan_transmit+0xd8>)
8000a4a: f04f 4200 mov.w r2, #2147483648 ; 0x80000000
8000a4e: 611a str r2, [r3, #16]
header.BitRateSwitch = FDCAN_BRS_OFF;
8000a50: 4b0a ldr r3, [pc, #40] ; (8000a7c <ftcan_transmit+0xd8>)
8000a52: 2200 movs r2, #0
8000a54: 615a str r2, [r3, #20]
header.FDFormat = FDCAN_CLASSIC_CAN;
8000a56: 4b09 ldr r3, [pc, #36] ; (8000a7c <ftcan_transmit+0xd8>)
8000a58: 2200 movs r2, #0
8000a5a: 619a str r2, [r3, #24]
header.TxEventFifoControl = FDCAN_NO_TX_EVENTS;
8000a5c: 4b07 ldr r3, [pc, #28] ; (8000a7c <ftcan_transmit+0xd8>)
8000a5e: 2200 movs r2, #0
8000a60: 61da str r2, [r3, #28]
return HAL_FDCAN_AddMessageToTxFifoQ(hcan, &header, data);
8000a62: 4b07 ldr r3, [pc, #28] ; (8000a80 <ftcan_transmit+0xdc>)
8000a64: 681b ldr r3, [r3, #0]
8000a66: 68ba ldr r2, [r7, #8]
8000a68: 4904 ldr r1, [pc, #16] ; (8000a7c <ftcan_transmit+0xd8>)
8000a6a: 4618 mov r0, r3
8000a6c: f003 fba9 bl 80041c2 <HAL_FDCAN_AddMessageToTxFifoQ>
8000a70: 4603 mov r3, r0
}
8000a72: 4618 mov r0, r3
8000a74: 3710 adds r7, #16
8000a76: 46bd mov sp, r7
8000a78: bd80 pop {r7, pc}
8000a7a: bf00 nop
8000a7c: 20000094 .word 0x20000094
8000a80: 20000090 .word 0x20000090
08000a84 <ftcan_add_filter>:
HAL_StatusTypeDef ftcan_add_filter(uint16_t id, uint16_t mask) {
8000a84: b580 push {r7, lr}
8000a86: b084 sub sp, #16
8000a88: af00 add r7, sp, #0
8000a8a: 4603 mov r3, r0
8000a8c: 460a mov r2, r1
8000a8e: 80fb strh r3, [r7, #6]
8000a90: 4613 mov r3, r2
8000a92: 80bb strh r3, [r7, #4]
static uint32_t next_filter_no = 0;
static FDCAN_FilterTypeDef filter;
filter.IdType = FDCAN_STANDARD_ID;
8000a94: 4b16 ldr r3, [pc, #88] ; (8000af0 <ftcan_add_filter+0x6c>)
8000a96: 2200 movs r2, #0
8000a98: 601a str r2, [r3, #0]
filter.FilterIndex = next_filter_no;
8000a9a: 4b16 ldr r3, [pc, #88] ; (8000af4 <ftcan_add_filter+0x70>)
8000a9c: 681b ldr r3, [r3, #0]
8000a9e: 4a14 ldr r2, [pc, #80] ; (8000af0 <ftcan_add_filter+0x6c>)
8000aa0: 6053 str r3, [r2, #4]
if (filter.FilterIndex > FTCAN_NUM_FILTERS + 1) {
8000aa2: 4b13 ldr r3, [pc, #76] ; (8000af0 <ftcan_add_filter+0x6c>)
8000aa4: 685b ldr r3, [r3, #4]
8000aa6: 2b0e cmp r3, #14
8000aa8: d901 bls.n 8000aae <ftcan_add_filter+0x2a>
return HAL_ERROR;
8000aaa: 2301 movs r3, #1
8000aac: e01c b.n 8000ae8 <ftcan_add_filter+0x64>
}
filter.FilterType = FDCAN_FILTER_MASK;
8000aae: 4b10 ldr r3, [pc, #64] ; (8000af0 <ftcan_add_filter+0x6c>)
8000ab0: 2202 movs r2, #2
8000ab2: 609a str r2, [r3, #8]
filter.FilterConfig = FDCAN_FILTER_TO_RXFIFO0;
8000ab4: 4b0e ldr r3, [pc, #56] ; (8000af0 <ftcan_add_filter+0x6c>)
8000ab6: 2201 movs r2, #1
8000ab8: 60da str r2, [r3, #12]
filter.FilterID1 = id;
8000aba: 88fb ldrh r3, [r7, #6]
8000abc: 4a0c ldr r2, [pc, #48] ; (8000af0 <ftcan_add_filter+0x6c>)
8000abe: 6113 str r3, [r2, #16]
filter.FilterID2 = mask;
8000ac0: 88bb ldrh r3, [r7, #4]
8000ac2: 4a0b ldr r2, [pc, #44] ; (8000af0 <ftcan_add_filter+0x6c>)
8000ac4: 6153 str r3, [r2, #20]
HAL_StatusTypeDef status = HAL_FDCAN_ConfigFilter(hcan, &filter);
8000ac6: 4b0c ldr r3, [pc, #48] ; (8000af8 <ftcan_add_filter+0x74>)
8000ac8: 681b ldr r3, [r3, #0]
8000aca: 4909 ldr r1, [pc, #36] ; (8000af0 <ftcan_add_filter+0x6c>)
8000acc: 4618 mov r0, r3
8000ace: f003 fac5 bl 800405c <HAL_FDCAN_ConfigFilter>
8000ad2: 4603 mov r3, r0
8000ad4: 73fb strb r3, [r7, #15]
if (status == HAL_OK) {
8000ad6: 7bfb ldrb r3, [r7, #15]
8000ad8: 2b00 cmp r3, #0
8000ada: d104 bne.n 8000ae6 <ftcan_add_filter+0x62>
next_filter_no++;
8000adc: 4b05 ldr r3, [pc, #20] ; (8000af4 <ftcan_add_filter+0x70>)
8000ade: 681b ldr r3, [r3, #0]
8000ae0: 3301 adds r3, #1
8000ae2: 4a04 ldr r2, [pc, #16] ; (8000af4 <ftcan_add_filter+0x70>)
8000ae4: 6013 str r3, [r2, #0]
}
return status;
8000ae6: 7bfb ldrb r3, [r7, #15]
}
8000ae8: 4618 mov r0, r3
8000aea: 3710 adds r7, #16
8000aec: 46bd mov sp, r7
8000aee: bd80 pop {r7, pc}
8000af0: 200000b8 .word 0x200000b8
8000af4: 200000d0 .word 0x200000d0
8000af8: 20000090 .word 0x20000090
08000afc <HAL_FDCAN_RxFifo0Callback>:
void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *handle,
uint32_t RxFifo0ITs) {
8000afc: b580 push {r7, lr}
8000afe: b084 sub sp, #16
8000b00: af00 add r7, sp, #0
8000b02: 6078 str r0, [r7, #4]
8000b04: 6039 str r1, [r7, #0]
if (handle != hcan || (RxFifo0ITs & FDCAN_IT_RX_FIFO0_NEW_MESSAGE) == RESET) {
8000b06: 4b40 ldr r3, [pc, #256] ; (8000c08 <HAL_FDCAN_RxFifo0Callback+0x10c>)
8000b08: 681b ldr r3, [r3, #0]
8000b0a: 687a ldr r2, [r7, #4]
8000b0c: 429a cmp r2, r3
8000b0e: d170 bne.n 8000bf2 <HAL_FDCAN_RxFifo0Callback+0xf6>
8000b10: 683b ldr r3, [r7, #0]
8000b12: f003 0301 and.w r3, r3, #1
8000b16: 2b00 cmp r3, #0
8000b18: d06b beq.n 8000bf2 <HAL_FDCAN_RxFifo0Callback+0xf6>
return;
}
static FDCAN_RxHeaderTypeDef header;
static uint8_t data[8];
if (HAL_FDCAN_GetRxMessage(hcan, FDCAN_RX_FIFO0, &header, data) != HAL_OK) {
8000b1a: 4b3b ldr r3, [pc, #236] ; (8000c08 <HAL_FDCAN_RxFifo0Callback+0x10c>)
8000b1c: 6818 ldr r0, [r3, #0]
8000b1e: 4b3b ldr r3, [pc, #236] ; (8000c0c <HAL_FDCAN_RxFifo0Callback+0x110>)
8000b20: 4a3b ldr r2, [pc, #236] ; (8000c10 <HAL_FDCAN_RxFifo0Callback+0x114>)
8000b22: 2140 movs r1, #64 ; 0x40
8000b24: f003 fb92 bl 800424c <HAL_FDCAN_GetRxMessage>
8000b28: 4603 mov r3, r0
8000b2a: 2b00 cmp r3, #0
8000b2c: d163 bne.n 8000bf6 <HAL_FDCAN_RxFifo0Callback+0xfa>
return;
}
if (header.FDFormat != FDCAN_CLASSIC_CAN ||
8000b2e: 4b38 ldr r3, [pc, #224] ; (8000c10 <HAL_FDCAN_RxFifo0Callback+0x114>)
8000b30: 699b ldr r3, [r3, #24]
8000b32: 2b00 cmp r3, #0
8000b34: d161 bne.n 8000bfa <HAL_FDCAN_RxFifo0Callback+0xfe>
header.RxFrameType != FDCAN_DATA_FRAME ||
8000b36: 4b36 ldr r3, [pc, #216] ; (8000c10 <HAL_FDCAN_RxFifo0Callback+0x114>)
8000b38: 689b ldr r3, [r3, #8]
if (header.FDFormat != FDCAN_CLASSIC_CAN ||
8000b3a: 2b00 cmp r3, #0
8000b3c: d15d bne.n 8000bfa <HAL_FDCAN_RxFifo0Callback+0xfe>
header.IdType != FDCAN_STANDARD_ID) {
8000b3e: 4b34 ldr r3, [pc, #208] ; (8000c10 <HAL_FDCAN_RxFifo0Callback+0x114>)
8000b40: 685b ldr r3, [r3, #4]
header.RxFrameType != FDCAN_DATA_FRAME ||
8000b42: 2b00 cmp r3, #0
8000b44: d159 bne.n 8000bfa <HAL_FDCAN_RxFifo0Callback+0xfe>
return;
}
size_t datalen;
switch (header.DataLength) {
8000b46: 4b32 ldr r3, [pc, #200] ; (8000c10 <HAL_FDCAN_RxFifo0Callback+0x114>)
8000b48: 68db ldr r3, [r3, #12]
8000b4a: f5b3 2f00 cmp.w r3, #524288 ; 0x80000
8000b4e: d044 beq.n 8000bda <HAL_FDCAN_RxFifo0Callback+0xde>
8000b50: f5b3 2f00 cmp.w r3, #524288 ; 0x80000
8000b54: d853 bhi.n 8000bfe <HAL_FDCAN_RxFifo0Callback+0x102>
8000b56: f5b3 2fe0 cmp.w r3, #458752 ; 0x70000
8000b5a: d03b beq.n 8000bd4 <HAL_FDCAN_RxFifo0Callback+0xd8>
8000b5c: f5b3 2fe0 cmp.w r3, #458752 ; 0x70000
8000b60: d84d bhi.n 8000bfe <HAL_FDCAN_RxFifo0Callback+0x102>
8000b62: f5b3 2fc0 cmp.w r3, #393216 ; 0x60000
8000b66: d032 beq.n 8000bce <HAL_FDCAN_RxFifo0Callback+0xd2>
8000b68: f5b3 2fc0 cmp.w r3, #393216 ; 0x60000
8000b6c: d847 bhi.n 8000bfe <HAL_FDCAN_RxFifo0Callback+0x102>
8000b6e: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8000b72: d029 beq.n 8000bc8 <HAL_FDCAN_RxFifo0Callback+0xcc>
8000b74: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8000b78: d841 bhi.n 8000bfe <HAL_FDCAN_RxFifo0Callback+0x102>
8000b7a: f5b3 2f80 cmp.w r3, #262144 ; 0x40000
8000b7e: d020 beq.n 8000bc2 <HAL_FDCAN_RxFifo0Callback+0xc6>
8000b80: f5b3 2f80 cmp.w r3, #262144 ; 0x40000
8000b84: d83b bhi.n 8000bfe <HAL_FDCAN_RxFifo0Callback+0x102>
8000b86: f5b3 3f40 cmp.w r3, #196608 ; 0x30000
8000b8a: d017 beq.n 8000bbc <HAL_FDCAN_RxFifo0Callback+0xc0>
8000b8c: f5b3 3f40 cmp.w r3, #196608 ; 0x30000
8000b90: d835 bhi.n 8000bfe <HAL_FDCAN_RxFifo0Callback+0x102>
8000b92: f5b3 3f00 cmp.w r3, #131072 ; 0x20000
8000b96: d00e beq.n 8000bb6 <HAL_FDCAN_RxFifo0Callback+0xba>
8000b98: f5b3 3f00 cmp.w r3, #131072 ; 0x20000
8000b9c: d82f bhi.n 8000bfe <HAL_FDCAN_RxFifo0Callback+0x102>
8000b9e: 2b00 cmp r3, #0
8000ba0: d003 beq.n 8000baa <HAL_FDCAN_RxFifo0Callback+0xae>
8000ba2: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8000ba6: d003 beq.n 8000bb0 <HAL_FDCAN_RxFifo0Callback+0xb4>
break;
case FDCAN_DLC_BYTES_8:
datalen = 8;
break;
default:
return;
8000ba8: e029 b.n 8000bfe <HAL_FDCAN_RxFifo0Callback+0x102>
datalen = 0;
8000baa: 2300 movs r3, #0
8000bac: 60fb str r3, [r7, #12]
break;
8000bae: e017 b.n 8000be0 <HAL_FDCAN_RxFifo0Callback+0xe4>
datalen = 1;
8000bb0: 2301 movs r3, #1
8000bb2: 60fb str r3, [r7, #12]
break;
8000bb4: e014 b.n 8000be0 <HAL_FDCAN_RxFifo0Callback+0xe4>
datalen = 2;
8000bb6: 2302 movs r3, #2
8000bb8: 60fb str r3, [r7, #12]
break;
8000bba: e011 b.n 8000be0 <HAL_FDCAN_RxFifo0Callback+0xe4>
datalen = 3;
8000bbc: 2303 movs r3, #3
8000bbe: 60fb str r3, [r7, #12]
break;
8000bc0: e00e b.n 8000be0 <HAL_FDCAN_RxFifo0Callback+0xe4>
datalen = 4;
8000bc2: 2304 movs r3, #4
8000bc4: 60fb str r3, [r7, #12]
break;
8000bc6: e00b b.n 8000be0 <HAL_FDCAN_RxFifo0Callback+0xe4>
datalen = 5;
8000bc8: 2305 movs r3, #5
8000bca: 60fb str r3, [r7, #12]
break;
8000bcc: e008 b.n 8000be0 <HAL_FDCAN_RxFifo0Callback+0xe4>
datalen = 6;
8000bce: 2306 movs r3, #6
8000bd0: 60fb str r3, [r7, #12]
break;
8000bd2: e005 b.n 8000be0 <HAL_FDCAN_RxFifo0Callback+0xe4>
datalen = 7;
8000bd4: 2307 movs r3, #7
8000bd6: 60fb str r3, [r7, #12]
break;
8000bd8: e002 b.n 8000be0 <HAL_FDCAN_RxFifo0Callback+0xe4>
datalen = 8;
8000bda: 2308 movs r3, #8
8000bdc: 60fb str r3, [r7, #12]
break;
8000bde: bf00 nop
}
ftcan_msg_received_cb(header.Identifier, datalen, data);
8000be0: 4b0b ldr r3, [pc, #44] ; (8000c10 <HAL_FDCAN_RxFifo0Callback+0x114>)
8000be2: 681b ldr r3, [r3, #0]
8000be4: b29b uxth r3, r3
8000be6: 4a09 ldr r2, [pc, #36] ; (8000c0c <HAL_FDCAN_RxFifo0Callback+0x110>)
8000be8: 68f9 ldr r1, [r7, #12]
8000bea: 4618 mov r0, r3
8000bec: f7ff fc2c bl 8000448 <ftcan_msg_received_cb>
8000bf0: e006 b.n 8000c00 <HAL_FDCAN_RxFifo0Callback+0x104>
return;
8000bf2: bf00 nop
8000bf4: e004 b.n 8000c00 <HAL_FDCAN_RxFifo0Callback+0x104>
return;
8000bf6: bf00 nop
8000bf8: e002 b.n 8000c00 <HAL_FDCAN_RxFifo0Callback+0x104>
return;
8000bfa: bf00 nop
8000bfc: e000 b.n 8000c00 <HAL_FDCAN_RxFifo0Callback+0x104>
return;
8000bfe: bf00 nop
}
8000c00: 3710 adds r7, #16
8000c02: 46bd mov sp, r7
8000c04: bd80 pop {r7, pc}
8000c06: bf00 nop
8000c08: 20000090 .word 0x20000090
8000c0c: 200000fc .word 0x200000fc
8000c10: 200000d4 .word 0x200000d4
08000c14 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000c14: b580 push {r7, lr}
8000c16: b082 sub sp, #8
8000c18: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000c1a: f001 f836 bl 8001c8a <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000c1e: f000 f865 bl 8000cec <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000c22: f000 fc33 bl 800148c <MX_GPIO_Init>
MX_DMA_Init();
8000c26: f000 fbff bl 8001428 <MX_DMA_Init>
MX_ADC1_Init();
8000c2a: f000 f89d bl 8000d68 <MX_ADC1_Init>
MX_ADC2_Init();
8000c2e: f000 f979 bl 8000f24 <MX_ADC2_Init>
MX_TIM7_Init();
8000c32: f000 fbc1 bl 80013b8 <MX_TIM7_Init>
MX_I2C1_Init();
8000c36: f000 fa87 bl 8001148 <MX_I2C1_Init>
MX_TIM2_Init();
8000c3a: f000 fac5 bl 80011c8 <MX_TIM2_Init>
MX_TIM3_Init();
8000c3e: f000 fb39 bl 80012b4 <MX_TIM3_Init>
MX_FDCAN1_Init();
8000c42: f000 fa3b bl 80010bc <MX_FDCAN1_Init>
/* USER CODE BEGIN 2 */
HAL_GPIO_WritePin(Status_LED_GPIO_Port, Status_LED_Pin, GPIO_PIN_SET);
8000c46: 2201 movs r2, #1
8000c48: f44f 7180 mov.w r1, #256 ; 0x100
8000c4c: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
8000c50: f004 f8b2 bl 8004db8 <HAL_GPIO_WritePin>
currentMonitor_init(&hadc1, &hadc2, &htim7);
8000c54: 4a1c ldr r2, [pc, #112] ; (8000cc8 <main+0xb4>)
8000c56: 491d ldr r1, [pc, #116] ; (8000ccc <main+0xb8>)
8000c58: 481d ldr r0, [pc, #116] ; (8000cd0 <main+0xbc>)
8000c5a: f7ff fcf5 bl 8000648 <currentMonitor_init>
ChannelControl_init(&hi2c1, &htim3, &htim2);
8000c5e: 4a1d ldr r2, [pc, #116] ; (8000cd4 <main+0xc0>)
8000c60: 491d ldr r1, [pc, #116] ; (8000cd8 <main+0xc4>)
8000c62: 481e ldr r0, [pc, #120] ; (8000cdc <main+0xc8>)
8000c64: f7ff fc22 bl 80004ac <ChannelControl_init>
can_init(&hfdcan1);
8000c68: 481d ldr r0, [pc, #116] ; (8000ce0 <main+0xcc>)
8000c6a: f7ff fad5 bl 8000218 <can_init>
uint32_t lasttick = HAL_GetTick();
8000c6e: f001 f871 bl 8001d54 <HAL_GetTick>
8000c72: 6078 str r0, [r7, #4]
HAL_TIM_Base_Start(&htim2);
8000c74: 4817 ldr r0, [pc, #92] ; (8000cd4 <main+0xc0>)
8000c76: f005 fcb5 bl 80065e4 <HAL_TIM_Base_Start>
HAL_TIM_Base_Start(&htim3);
8000c7a: 4817 ldr r0, [pc, #92] ; (8000cd8 <main+0xc4>)
8000c7c: f005 fcb2 bl 80065e4 <HAL_TIM_Base_Start>
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
if(canmsg_received)
8000c80: 4b18 ldr r3, [pc, #96] ; (8000ce4 <main+0xd0>)
8000c82: 781b ldrb r3, [r3, #0]
8000c84: b2db uxtb r3, r3
8000c86: 2b00 cmp r3, #0
8000c88: d00f beq.n 8000caa <main+0x96>
{
canmsg_received = 0;
8000c8a: 4b16 ldr r3, [pc, #88] ; (8000ce4 <main+0xd0>)
8000c8c: 2200 movs r2, #0
8000c8e: 701a strb r2, [r3, #0]
ChannelControl_UpdateGPIOs(rxstate.iostatus);
8000c90: 4b15 ldr r3, [pc, #84] ; (8000ce8 <main+0xd4>)
8000c92: 8818 ldrh r0, [r3, #0]
8000c94: f7ff fc48 bl 8000528 <ChannelControl_UpdateGPIOs>
ChannelControl_UpdatePWMs(rxstate.pwmfans, rxstate.pwmaggregat, rxstate.pwmpumps);
8000c98: 4b13 ldr r3, [pc, #76] ; (8000ce8 <main+0xd4>)
8000c9a: 789b ldrb r3, [r3, #2]
8000c9c: 4a12 ldr r2, [pc, #72] ; (8000ce8 <main+0xd4>)
8000c9e: 78d1 ldrb r1, [r2, #3]
8000ca0: 4a11 ldr r2, [pc, #68] ; (8000ce8 <main+0xd4>)
8000ca2: 7912 ldrb r2, [r2, #4]
8000ca4: 4618 mov r0, r3
8000ca6: f7ff fc5b bl 8000560 <ChannelControl_UpdatePWMs>
}
if((HAL_GetTick()-lasttick)>100U)
8000caa: f001 f853 bl 8001d54 <HAL_GetTick>
8000cae: 4602 mov r2, r0
8000cb0: 687b ldr r3, [r7, #4]
8000cb2: 1ad3 subs r3, r2, r3
8000cb4: 2b64 cmp r3, #100 ; 0x64
8000cb6: d904 bls.n 8000cc2 <main+0xae>
{
lasttick = HAL_GetTick();
8000cb8: f001 f84c bl 8001d54 <HAL_GetTick>
8000cbc: 6078 str r0, [r7, #4]
can_sendloop();
8000cbe: f7ff fabb bl 8000238 <can_sendloop>
}
currentMonitor_checklimits();
8000cc2: f7ff fce7 bl 8000694 <currentMonitor_checklimits>
if(canmsg_received)
8000cc6: e7db b.n 8000c80 <main+0x6c>
8000cc8: 200003e4 .word 0x200003e4
8000ccc: 20000170 .word 0x20000170
8000cd0: 20000104 .word 0x20000104
8000cd4: 2000034c .word 0x2000034c
8000cd8: 20000398 .word 0x20000398
8000cdc: 20000300 .word 0x20000300
8000ce0: 2000029c .word 0x2000029c
8000ce4: 20000032 .word 0x20000032
8000ce8: 2000002c .word 0x2000002c
08000cec <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000cec: b580 push {r7, lr}
8000cee: b094 sub sp, #80 ; 0x50
8000cf0: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000cf2: f107 0318 add.w r3, r7, #24
8000cf6: 2238 movs r2, #56 ; 0x38
8000cf8: 2100 movs r1, #0
8000cfa: 4618 mov r0, r3
8000cfc: f006 ffc0 bl 8007c80 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000d00: 1d3b adds r3, r7, #4
8000d02: 2200 movs r2, #0
8000d04: 601a str r2, [r3, #0]
8000d06: 605a str r2, [r3, #4]
8000d08: 609a str r2, [r3, #8]
8000d0a: 60da str r2, [r3, #12]
8000d0c: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
8000d0e: f44f 7000 mov.w r0, #512 ; 0x200
8000d12: f004 fc83 bl 800561c <HAL_PWREx_ControlVoltageScaling>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
8000d16: 2301 movs r3, #1
8000d18: 61bb str r3, [r7, #24]
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
8000d1a: f44f 3380 mov.w r3, #65536 ; 0x10000
8000d1e: 61fb str r3, [r7, #28]
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
8000d20: 2300 movs r3, #0
8000d22: 637b str r3, [r7, #52] ; 0x34
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000d24: f107 0318 add.w r3, r7, #24
8000d28: 4618 mov r0, r3
8000d2a: f004 fd1b bl 8005764 <HAL_RCC_OscConfig>
8000d2e: 4603 mov r3, r0
8000d30: 2b00 cmp r3, #0
8000d32: d001 beq.n 8000d38 <SystemClock_Config+0x4c>
{
Error_Handler();
8000d34: f000 fc0e bl 8001554 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000d38: 230f movs r3, #15
8000d3a: 607b str r3, [r7, #4]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
8000d3c: 2302 movs r3, #2
8000d3e: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000d40: 2300 movs r3, #0
8000d42: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
8000d44: 2300 movs r3, #0
8000d46: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000d48: 2300 movs r3, #0
8000d4a: 617b str r3, [r7, #20]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
8000d4c: 1d3b adds r3, r7, #4
8000d4e: 2100 movs r1, #0
8000d50: 4618 mov r0, r3
8000d52: f005 f81f bl 8005d94 <HAL_RCC_ClockConfig>
8000d56: 4603 mov r3, r0
8000d58: 2b00 cmp r3, #0
8000d5a: d001 beq.n 8000d60 <SystemClock_Config+0x74>
{
Error_Handler();
8000d5c: f000 fbfa bl 8001554 <Error_Handler>
}
}
8000d60: bf00 nop
8000d62: 3750 adds r7, #80 ; 0x50
8000d64: 46bd mov sp, r7
8000d66: bd80 pop {r7, pc}
08000d68 <MX_ADC1_Init>:
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC1_Init(void)
{
8000d68: b580 push {r7, lr}
8000d6a: b08c sub sp, #48 ; 0x30
8000d6c: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_MultiModeTypeDef multimode = {0};
8000d6e: f107 0324 add.w r3, r7, #36 ; 0x24
8000d72: 2200 movs r2, #0
8000d74: 601a str r2, [r3, #0]
8000d76: 605a str r2, [r3, #4]
8000d78: 609a str r2, [r3, #8]
ADC_ChannelConfTypeDef sConfig = {0};
8000d7a: 1d3b adds r3, r7, #4
8000d7c: 2220 movs r2, #32
8000d7e: 2100 movs r1, #0
8000d80: 4618 mov r0, r3
8000d82: f006 ff7d bl 8007c80 <memset>
/* USER CODE END ADC1_Init 1 */
/** Common config
*/
hadc1.Instance = ADC1;
8000d86: 4b5f ldr r3, [pc, #380] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000d88: f04f 42a0 mov.w r2, #1342177280 ; 0x50000000
8000d8c: 601a str r2, [r3, #0]
hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV16;
8000d8e: 4b5d ldr r3, [pc, #372] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000d90: f44f 12e0 mov.w r2, #1835008 ; 0x1c0000
8000d94: 605a str r2, [r3, #4]
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
8000d96: 4b5b ldr r3, [pc, #364] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000d98: 2200 movs r2, #0
8000d9a: 609a str r2, [r3, #8]
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8000d9c: 4b59 ldr r3, [pc, #356] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000d9e: 2200 movs r2, #0
8000da0: 60da str r2, [r3, #12]
hadc1.Init.GainCompensation = 0;
8000da2: 4b58 ldr r3, [pc, #352] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000da4: 2200 movs r2, #0
8000da6: 611a str r2, [r3, #16]
hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
8000da8: 4b56 ldr r3, [pc, #344] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000daa: 2201 movs r2, #1
8000dac: 615a str r2, [r3, #20]
hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV;
8000dae: 4b55 ldr r3, [pc, #340] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000db0: 2208 movs r2, #8
8000db2: 619a str r2, [r3, #24]
hadc1.Init.LowPowerAutoWait = DISABLE;
8000db4: 4b53 ldr r3, [pc, #332] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000db6: 2200 movs r2, #0
8000db8: 771a strb r2, [r3, #28]
hadc1.Init.ContinuousConvMode = DISABLE;
8000dba: 4b52 ldr r3, [pc, #328] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000dbc: 2200 movs r2, #0
8000dbe: 775a strb r2, [r3, #29]
hadc1.Init.NbrOfConversion = 7;
8000dc0: 4b50 ldr r3, [pc, #320] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000dc2: 2207 movs r2, #7
8000dc4: 621a str r2, [r3, #32]
hadc1.Init.DiscontinuousConvMode = DISABLE;
8000dc6: 4b4f ldr r3, [pc, #316] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000dc8: 2200 movs r2, #0
8000dca: f883 2024 strb.w r2, [r3, #36] ; 0x24
hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T7_TRGO;
8000dce: 4b4d ldr r3, [pc, #308] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000dd0: f44f 62f8 mov.w r2, #1984 ; 0x7c0
8000dd4: 62da str r2, [r3, #44] ; 0x2c
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
8000dd6: 4b4b ldr r3, [pc, #300] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000dd8: f44f 6280 mov.w r2, #1024 ; 0x400
8000ddc: 631a str r2, [r3, #48] ; 0x30
hadc1.Init.DMAContinuousRequests = ENABLE;
8000dde: 4b49 ldr r3, [pc, #292] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000de0: 2201 movs r2, #1
8000de2: f883 2038 strb.w r2, [r3, #56] ; 0x38
hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
8000de6: 4b47 ldr r3, [pc, #284] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000de8: f44f 5280 mov.w r2, #4096 ; 0x1000
8000dec: 63da str r2, [r3, #60] ; 0x3c
hadc1.Init.OversamplingMode = DISABLE;
8000dee: 4b45 ldr r3, [pc, #276] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000df0: 2200 movs r2, #0
8000df2: f883 2040 strb.w r2, [r3, #64] ; 0x40
if (HAL_ADC_Init(&hadc1) != HAL_OK)
8000df6: 4843 ldr r0, [pc, #268] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000df8: f001 f9fc bl 80021f4 <HAL_ADC_Init>
8000dfc: 4603 mov r3, r0
8000dfe: 2b00 cmp r3, #0
8000e00: d001 beq.n 8000e06 <MX_ADC1_Init+0x9e>
{
Error_Handler();
8000e02: f000 fba7 bl 8001554 <Error_Handler>
}
/** Configure the ADC multi-mode
*/
multimode.Mode = ADC_MODE_INDEPENDENT;
8000e06: 2300 movs r3, #0
8000e08: 627b str r3, [r7, #36] ; 0x24
if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
8000e0a: f107 0324 add.w r3, r7, #36 ; 0x24
8000e0e: 4619 mov r1, r3
8000e10: 483c ldr r0, [pc, #240] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000e12: f002 fba3 bl 800355c <HAL_ADCEx_MultiModeConfigChannel>
8000e16: 4603 mov r3, r0
8000e18: 2b00 cmp r3, #0
8000e1a: d001 beq.n 8000e20 <MX_ADC1_Init+0xb8>
{
Error_Handler();
8000e1c: f000 fb9a bl 8001554 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_3;
8000e20: 4b39 ldr r3, [pc, #228] ; (8000f08 <MX_ADC1_Init+0x1a0>)
8000e22: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
8000e24: 2306 movs r3, #6
8000e26: 60bb str r3, [r7, #8]
sConfig.SamplingTime = ADC_SAMPLETIME_92CYCLES_5;
8000e28: 2305 movs r3, #5
8000e2a: 60fb str r3, [r7, #12]
sConfig.SingleDiff = ADC_SINGLE_ENDED;
8000e2c: 237f movs r3, #127 ; 0x7f
8000e2e: 613b str r3, [r7, #16]
sConfig.OffsetNumber = ADC_OFFSET_NONE;
8000e30: 2304 movs r3, #4
8000e32: 617b str r3, [r7, #20]
sConfig.Offset = 0;
8000e34: 2300 movs r3, #0
8000e36: 61bb str r3, [r7, #24]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8000e38: 1d3b adds r3, r7, #4
8000e3a: 4619 mov r1, r3
8000e3c: 4831 ldr r0, [pc, #196] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000e3e: f001 fe4f bl 8002ae0 <HAL_ADC_ConfigChannel>
8000e42: 4603 mov r3, r0
8000e44: 2b00 cmp r3, #0
8000e46: d001 beq.n 8000e4c <MX_ADC1_Init+0xe4>
{
Error_Handler();
8000e48: f000 fb84 bl 8001554 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_4;
8000e4c: 4b2f ldr r3, [pc, #188] ; (8000f0c <MX_ADC1_Init+0x1a4>)
8000e4e: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_2;
8000e50: 230c movs r3, #12
8000e52: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8000e54: 1d3b adds r3, r7, #4
8000e56: 4619 mov r1, r3
8000e58: 482a ldr r0, [pc, #168] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000e5a: f001 fe41 bl 8002ae0 <HAL_ADC_ConfigChannel>
8000e5e: 4603 mov r3, r0
8000e60: 2b00 cmp r3, #0
8000e62: d001 beq.n 8000e68 <MX_ADC1_Init+0x100>
{
Error_Handler();
8000e64: f000 fb76 bl 8001554 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_12;
8000e68: 4b29 ldr r3, [pc, #164] ; (8000f10 <MX_ADC1_Init+0x1a8>)
8000e6a: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_3;
8000e6c: 2312 movs r3, #18
8000e6e: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8000e70: 1d3b adds r3, r7, #4
8000e72: 4619 mov r1, r3
8000e74: 4823 ldr r0, [pc, #140] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000e76: f001 fe33 bl 8002ae0 <HAL_ADC_ConfigChannel>
8000e7a: 4603 mov r3, r0
8000e7c: 2b00 cmp r3, #0
8000e7e: d001 beq.n 8000e84 <MX_ADC1_Init+0x11c>
{
Error_Handler();
8000e80: f000 fb68 bl 8001554 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_15;
8000e84: 4b23 ldr r3, [pc, #140] ; (8000f14 <MX_ADC1_Init+0x1ac>)
8000e86: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_4;
8000e88: 2318 movs r3, #24
8000e8a: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8000e8c: 1d3b adds r3, r7, #4
8000e8e: 4619 mov r1, r3
8000e90: 481c ldr r0, [pc, #112] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000e92: f001 fe25 bl 8002ae0 <HAL_ADC_ConfigChannel>
8000e96: 4603 mov r3, r0
8000e98: 2b00 cmp r3, #0
8000e9a: d001 beq.n 8000ea0 <MX_ADC1_Init+0x138>
{
Error_Handler();
8000e9c: f000 fb5a bl 8001554 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_TEMPSENSOR_ADC1;
8000ea0: 4b1d ldr r3, [pc, #116] ; (8000f18 <MX_ADC1_Init+0x1b0>)
8000ea2: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_5;
8000ea4: f44f 7380 mov.w r3, #256 ; 0x100
8000ea8: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8000eaa: 1d3b adds r3, r7, #4
8000eac: 4619 mov r1, r3
8000eae: 4815 ldr r0, [pc, #84] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000eb0: f001 fe16 bl 8002ae0 <HAL_ADC_ConfigChannel>
8000eb4: 4603 mov r3, r0
8000eb6: 2b00 cmp r3, #0
8000eb8: d001 beq.n 8000ebe <MX_ADC1_Init+0x156>
{
Error_Handler();
8000eba: f000 fb4b bl 8001554 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_VBAT;
8000ebe: 4b17 ldr r3, [pc, #92] ; (8000f1c <MX_ADC1_Init+0x1b4>)
8000ec0: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_6;
8000ec2: f44f 7383 mov.w r3, #262 ; 0x106
8000ec6: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8000ec8: 1d3b adds r3, r7, #4
8000eca: 4619 mov r1, r3
8000ecc: 480d ldr r0, [pc, #52] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000ece: f001 fe07 bl 8002ae0 <HAL_ADC_ConfigChannel>
8000ed2: 4603 mov r3, r0
8000ed4: 2b00 cmp r3, #0
8000ed6: d001 beq.n 8000edc <MX_ADC1_Init+0x174>
{
Error_Handler();
8000ed8: f000 fb3c bl 8001554 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_VREFINT;
8000edc: 4b10 ldr r3, [pc, #64] ; (8000f20 <MX_ADC1_Init+0x1b8>)
8000ede: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_7;
8000ee0: f44f 7386 mov.w r3, #268 ; 0x10c
8000ee4: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8000ee6: 1d3b adds r3, r7, #4
8000ee8: 4619 mov r1, r3
8000eea: 4806 ldr r0, [pc, #24] ; (8000f04 <MX_ADC1_Init+0x19c>)
8000eec: f001 fdf8 bl 8002ae0 <HAL_ADC_ConfigChannel>
8000ef0: 4603 mov r3, r0
8000ef2: 2b00 cmp r3, #0
8000ef4: d001 beq.n 8000efa <MX_ADC1_Init+0x192>
{
Error_Handler();
8000ef6: f000 fb2d bl 8001554 <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
8000efa: bf00 nop
8000efc: 3730 adds r7, #48 ; 0x30
8000efe: 46bd mov sp, r7
8000f00: bd80 pop {r7, pc}
8000f02: bf00 nop
8000f04: 20000104 .word 0x20000104
8000f08: 0c900008 .word 0x0c900008
8000f0c: 10c00010 .word 0x10c00010
8000f10: 32601000 .word 0x32601000
8000f14: 3ef08000 .word 0x3ef08000
8000f18: c3210000 .word 0xc3210000
8000f1c: c7520000 .word 0xc7520000
8000f20: cb840000 .word 0xcb840000
08000f24 <MX_ADC2_Init>:
* @brief ADC2 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC2_Init(void)
{
8000f24: b580 push {r7, lr}
8000f26: b088 sub sp, #32
8000f28: af00 add r7, sp, #0
/* USER CODE BEGIN ADC2_Init 0 */
/* USER CODE END ADC2_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
8000f2a: 463b mov r3, r7
8000f2c: 2220 movs r2, #32
8000f2e: 2100 movs r1, #0
8000f30: 4618 mov r0, r3
8000f32: f006 fea5 bl 8007c80 <memset>
/* USER CODE END ADC2_Init 1 */
/** Common config
*/
hadc2.Instance = ADC2;
8000f36: 4b58 ldr r3, [pc, #352] ; (8001098 <MX_ADC2_Init+0x174>)
8000f38: 4a58 ldr r2, [pc, #352] ; (800109c <MX_ADC2_Init+0x178>)
8000f3a: 601a str r2, [r3, #0]
hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV16;
8000f3c: 4b56 ldr r3, [pc, #344] ; (8001098 <MX_ADC2_Init+0x174>)
8000f3e: f44f 12e0 mov.w r2, #1835008 ; 0x1c0000
8000f42: 605a str r2, [r3, #4]
hadc2.Init.Resolution = ADC_RESOLUTION_12B;
8000f44: 4b54 ldr r3, [pc, #336] ; (8001098 <MX_ADC2_Init+0x174>)
8000f46: 2200 movs r2, #0
8000f48: 609a str r2, [r3, #8]
hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8000f4a: 4b53 ldr r3, [pc, #332] ; (8001098 <MX_ADC2_Init+0x174>)
8000f4c: 2200 movs r2, #0
8000f4e: 60da str r2, [r3, #12]
hadc2.Init.GainCompensation = 0;
8000f50: 4b51 ldr r3, [pc, #324] ; (8001098 <MX_ADC2_Init+0x174>)
8000f52: 2200 movs r2, #0
8000f54: 611a str r2, [r3, #16]
hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE;
8000f56: 4b50 ldr r3, [pc, #320] ; (8001098 <MX_ADC2_Init+0x174>)
8000f58: 2201 movs r2, #1
8000f5a: 615a str r2, [r3, #20]
hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV;
8000f5c: 4b4e ldr r3, [pc, #312] ; (8001098 <MX_ADC2_Init+0x174>)
8000f5e: 2208 movs r2, #8
8000f60: 619a str r2, [r3, #24]
hadc2.Init.LowPowerAutoWait = DISABLE;
8000f62: 4b4d ldr r3, [pc, #308] ; (8001098 <MX_ADC2_Init+0x174>)
8000f64: 2200 movs r2, #0
8000f66: 771a strb r2, [r3, #28]
hadc2.Init.ContinuousConvMode = DISABLE;
8000f68: 4b4b ldr r3, [pc, #300] ; (8001098 <MX_ADC2_Init+0x174>)
8000f6a: 2200 movs r2, #0
8000f6c: 775a strb r2, [r3, #29]
hadc2.Init.NbrOfConversion = 7;
8000f6e: 4b4a ldr r3, [pc, #296] ; (8001098 <MX_ADC2_Init+0x174>)
8000f70: 2207 movs r2, #7
8000f72: 621a str r2, [r3, #32]
hadc2.Init.DiscontinuousConvMode = DISABLE;
8000f74: 4b48 ldr r3, [pc, #288] ; (8001098 <MX_ADC2_Init+0x174>)
8000f76: 2200 movs r2, #0
8000f78: f883 2024 strb.w r2, [r3, #36] ; 0x24
hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T7_TRGO;
8000f7c: 4b46 ldr r3, [pc, #280] ; (8001098 <MX_ADC2_Init+0x174>)
8000f7e: f44f 62f8 mov.w r2, #1984 ; 0x7c0
8000f82: 62da str r2, [r3, #44] ; 0x2c
hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
8000f84: 4b44 ldr r3, [pc, #272] ; (8001098 <MX_ADC2_Init+0x174>)
8000f86: f44f 6280 mov.w r2, #1024 ; 0x400
8000f8a: 631a str r2, [r3, #48] ; 0x30
hadc2.Init.DMAContinuousRequests = ENABLE;
8000f8c: 4b42 ldr r3, [pc, #264] ; (8001098 <MX_ADC2_Init+0x174>)
8000f8e: 2201 movs r2, #1
8000f90: f883 2038 strb.w r2, [r3, #56] ; 0x38
hadc2.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
8000f94: 4b40 ldr r3, [pc, #256] ; (8001098 <MX_ADC2_Init+0x174>)
8000f96: f44f 5280 mov.w r2, #4096 ; 0x1000
8000f9a: 63da str r2, [r3, #60] ; 0x3c
hadc2.Init.OversamplingMode = DISABLE;
8000f9c: 4b3e ldr r3, [pc, #248] ; (8001098 <MX_ADC2_Init+0x174>)
8000f9e: 2200 movs r2, #0
8000fa0: f883 2040 strb.w r2, [r3, #64] ; 0x40
if (HAL_ADC_Init(&hadc2) != HAL_OK)
8000fa4: 483c ldr r0, [pc, #240] ; (8001098 <MX_ADC2_Init+0x174>)
8000fa6: f001 f925 bl 80021f4 <HAL_ADC_Init>
8000faa: 4603 mov r3, r0
8000fac: 2b00 cmp r3, #0
8000fae: d001 beq.n 8000fb4 <MX_ADC2_Init+0x90>
{
Error_Handler();
8000fb0: f000 fad0 bl 8001554 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_1;
8000fb4: 4b3a ldr r3, [pc, #232] ; (80010a0 <MX_ADC2_Init+0x17c>)
8000fb6: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_1;
8000fb8: 2306 movs r3, #6
8000fba: 607b str r3, [r7, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_92CYCLES_5;
8000fbc: 2305 movs r3, #5
8000fbe: 60bb str r3, [r7, #8]
sConfig.SingleDiff = ADC_SINGLE_ENDED;
8000fc0: 237f movs r3, #127 ; 0x7f
8000fc2: 60fb str r3, [r7, #12]
sConfig.OffsetNumber = ADC_OFFSET_NONE;
8000fc4: 2304 movs r3, #4
8000fc6: 613b str r3, [r7, #16]
sConfig.Offset = 0;
8000fc8: 2300 movs r3, #0
8000fca: 617b str r3, [r7, #20]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
8000fcc: 463b mov r3, r7
8000fce: 4619 mov r1, r3
8000fd0: 4831 ldr r0, [pc, #196] ; (8001098 <MX_ADC2_Init+0x174>)
8000fd2: f001 fd85 bl 8002ae0 <HAL_ADC_ConfigChannel>
8000fd6: 4603 mov r3, r0
8000fd8: 2b00 cmp r3, #0
8000fda: d001 beq.n 8000fe0 <MX_ADC2_Init+0xbc>
{
Error_Handler();
8000fdc: f000 faba bl 8001554 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_2;
8000fe0: 4b30 ldr r3, [pc, #192] ; (80010a4 <MX_ADC2_Init+0x180>)
8000fe2: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_2;
8000fe4: 230c movs r3, #12
8000fe6: 607b str r3, [r7, #4]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
8000fe8: 463b mov r3, r7
8000fea: 4619 mov r1, r3
8000fec: 482a ldr r0, [pc, #168] ; (8001098 <MX_ADC2_Init+0x174>)
8000fee: f001 fd77 bl 8002ae0 <HAL_ADC_ConfigChannel>
8000ff2: 4603 mov r3, r0
8000ff4: 2b00 cmp r3, #0
8000ff6: d001 beq.n 8000ffc <MX_ADC2_Init+0xd8>
{
Error_Handler();
8000ff8: f000 faac bl 8001554 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_3;
8000ffc: 4b2a ldr r3, [pc, #168] ; (80010a8 <MX_ADC2_Init+0x184>)
8000ffe: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_3;
8001000: 2312 movs r3, #18
8001002: 607b str r3, [r7, #4]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
8001004: 463b mov r3, r7
8001006: 4619 mov r1, r3
8001008: 4823 ldr r0, [pc, #140] ; (8001098 <MX_ADC2_Init+0x174>)
800100a: f001 fd69 bl 8002ae0 <HAL_ADC_ConfigChannel>
800100e: 4603 mov r3, r0
8001010: 2b00 cmp r3, #0
8001012: d001 beq.n 8001018 <MX_ADC2_Init+0xf4>
{
Error_Handler();
8001014: f000 fa9e bl 8001554 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_4;
8001018: 4b24 ldr r3, [pc, #144] ; (80010ac <MX_ADC2_Init+0x188>)
800101a: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_4;
800101c: 2318 movs r3, #24
800101e: 607b str r3, [r7, #4]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
8001020: 463b mov r3, r7
8001022: 4619 mov r1, r3
8001024: 481c ldr r0, [pc, #112] ; (8001098 <MX_ADC2_Init+0x174>)
8001026: f001 fd5b bl 8002ae0 <HAL_ADC_ConfigChannel>
800102a: 4603 mov r3, r0
800102c: 2b00 cmp r3, #0
800102e: d001 beq.n 8001034 <MX_ADC2_Init+0x110>
{
Error_Handler();
8001030: f000 fa90 bl 8001554 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_12;
8001034: 4b1e ldr r3, [pc, #120] ; (80010b0 <MX_ADC2_Init+0x18c>)
8001036: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_5;
8001038: f44f 7380 mov.w r3, #256 ; 0x100
800103c: 607b str r3, [r7, #4]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
800103e: 463b mov r3, r7
8001040: 4619 mov r1, r3
8001042: 4815 ldr r0, [pc, #84] ; (8001098 <MX_ADC2_Init+0x174>)
8001044: f001 fd4c bl 8002ae0 <HAL_ADC_ConfigChannel>
8001048: 4603 mov r3, r0
800104a: 2b00 cmp r3, #0
800104c: d001 beq.n 8001052 <MX_ADC2_Init+0x12e>
{
Error_Handler();
800104e: f000 fa81 bl 8001554 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_13;
8001052: 4b18 ldr r3, [pc, #96] ; (80010b4 <MX_ADC2_Init+0x190>)
8001054: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_6;
8001056: f44f 7383 mov.w r3, #262 ; 0x106
800105a: 607b str r3, [r7, #4]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
800105c: 463b mov r3, r7
800105e: 4619 mov r1, r3
8001060: 480d ldr r0, [pc, #52] ; (8001098 <MX_ADC2_Init+0x174>)
8001062: f001 fd3d bl 8002ae0 <HAL_ADC_ConfigChannel>
8001066: 4603 mov r3, r0
8001068: 2b00 cmp r3, #0
800106a: d001 beq.n 8001070 <MX_ADC2_Init+0x14c>
{
Error_Handler();
800106c: f000 fa72 bl 8001554 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_17;
8001070: 4b11 ldr r3, [pc, #68] ; (80010b8 <MX_ADC2_Init+0x194>)
8001072: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_7;
8001074: f44f 7386 mov.w r3, #268 ; 0x10c
8001078: 607b str r3, [r7, #4]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
800107a: 463b mov r3, r7
800107c: 4619 mov r1, r3
800107e: 4806 ldr r0, [pc, #24] ; (8001098 <MX_ADC2_Init+0x174>)
8001080: f001 fd2e bl 8002ae0 <HAL_ADC_ConfigChannel>
8001084: 4603 mov r3, r0
8001086: 2b00 cmp r3, #0
8001088: d001 beq.n 800108e <MX_ADC2_Init+0x16a>
{
Error_Handler();
800108a: f000 fa63 bl 8001554 <Error_Handler>
}
/* USER CODE BEGIN ADC2_Init 2 */
/* USER CODE END ADC2_Init 2 */
}
800108e: bf00 nop
8001090: 3720 adds r7, #32
8001092: 46bd mov sp, r7
8001094: bd80 pop {r7, pc}
8001096: bf00 nop
8001098: 20000170 .word 0x20000170
800109c: 50000100 .word 0x50000100
80010a0: 04300002 .word 0x04300002
80010a4: 08600004 .word 0x08600004
80010a8: 0c900008 .word 0x0c900008
80010ac: 10c00010 .word 0x10c00010
80010b0: 32601000 .word 0x32601000
80010b4: 36902000 .word 0x36902000
80010b8: 47520000 .word 0x47520000
080010bc <MX_FDCAN1_Init>:
* @brief FDCAN1 Initialization Function
* @param None
* @retval None
*/
static void MX_FDCAN1_Init(void)
{
80010bc: b580 push {r7, lr}
80010be: af00 add r7, sp, #0
/* USER CODE END FDCAN1_Init 0 */
/* USER CODE BEGIN FDCAN1_Init 1 */
/* USER CODE END FDCAN1_Init 1 */
hfdcan1.Instance = FDCAN1;
80010c0: 4b1f ldr r3, [pc, #124] ; (8001140 <MX_FDCAN1_Init+0x84>)
80010c2: 4a20 ldr r2, [pc, #128] ; (8001144 <MX_FDCAN1_Init+0x88>)
80010c4: 601a str r2, [r3, #0]
hfdcan1.Init.ClockDivider = FDCAN_CLOCK_DIV1;
80010c6: 4b1e ldr r3, [pc, #120] ; (8001140 <MX_FDCAN1_Init+0x84>)
80010c8: 2200 movs r2, #0
80010ca: 605a str r2, [r3, #4]
hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
80010cc: 4b1c ldr r3, [pc, #112] ; (8001140 <MX_FDCAN1_Init+0x84>)
80010ce: 2200 movs r2, #0
80010d0: 609a str r2, [r3, #8]
hfdcan1.Init.Mode = FDCAN_MODE_NORMAL;
80010d2: 4b1b ldr r3, [pc, #108] ; (8001140 <MX_FDCAN1_Init+0x84>)
80010d4: 2200 movs r2, #0
80010d6: 60da str r2, [r3, #12]
hfdcan1.Init.AutoRetransmission = DISABLE;
80010d8: 4b19 ldr r3, [pc, #100] ; (8001140 <MX_FDCAN1_Init+0x84>)
80010da: 2200 movs r2, #0
80010dc: 741a strb r2, [r3, #16]
hfdcan1.Init.TransmitPause = DISABLE;
80010de: 4b18 ldr r3, [pc, #96] ; (8001140 <MX_FDCAN1_Init+0x84>)
80010e0: 2200 movs r2, #0
80010e2: 745a strb r2, [r3, #17]
hfdcan1.Init.ProtocolException = DISABLE;
80010e4: 4b16 ldr r3, [pc, #88] ; (8001140 <MX_FDCAN1_Init+0x84>)
80010e6: 2200 movs r2, #0
80010e8: 749a strb r2, [r3, #18]
hfdcan1.Init.NominalPrescaler = 1;
80010ea: 4b15 ldr r3, [pc, #84] ; (8001140 <MX_FDCAN1_Init+0x84>)
80010ec: 2201 movs r2, #1
80010ee: 615a str r2, [r3, #20]
hfdcan1.Init.NominalSyncJumpWidth = 13;
80010f0: 4b13 ldr r3, [pc, #76] ; (8001140 <MX_FDCAN1_Init+0x84>)
80010f2: 220d movs r2, #13
80010f4: 619a str r2, [r3, #24]
hfdcan1.Init.NominalTimeSeg1 = 18;
80010f6: 4b12 ldr r3, [pc, #72] ; (8001140 <MX_FDCAN1_Init+0x84>)
80010f8: 2212 movs r2, #18
80010fa: 61da str r2, [r3, #28]
hfdcan1.Init.NominalTimeSeg2 = 13;
80010fc: 4b10 ldr r3, [pc, #64] ; (8001140 <MX_FDCAN1_Init+0x84>)
80010fe: 220d movs r2, #13
8001100: 621a str r2, [r3, #32]
hfdcan1.Init.DataPrescaler = 2;
8001102: 4b0f ldr r3, [pc, #60] ; (8001140 <MX_FDCAN1_Init+0x84>)
8001104: 2202 movs r2, #2
8001106: 625a str r2, [r3, #36] ; 0x24
hfdcan1.Init.DataSyncJumpWidth = 6;
8001108: 4b0d ldr r3, [pc, #52] ; (8001140 <MX_FDCAN1_Init+0x84>)
800110a: 2206 movs r2, #6
800110c: 629a str r2, [r3, #40] ; 0x28
hfdcan1.Init.DataTimeSeg1 = 9;
800110e: 4b0c ldr r3, [pc, #48] ; (8001140 <MX_FDCAN1_Init+0x84>)
8001110: 2209 movs r2, #9
8001112: 62da str r2, [r3, #44] ; 0x2c
hfdcan1.Init.DataTimeSeg2 = 6;
8001114: 4b0a ldr r3, [pc, #40] ; (8001140 <MX_FDCAN1_Init+0x84>)
8001116: 2206 movs r2, #6
8001118: 631a str r2, [r3, #48] ; 0x30
hfdcan1.Init.StdFiltersNbr = 10;
800111a: 4b09 ldr r3, [pc, #36] ; (8001140 <MX_FDCAN1_Init+0x84>)
800111c: 220a movs r2, #10
800111e: 635a str r2, [r3, #52] ; 0x34
hfdcan1.Init.ExtFiltersNbr = 0;
8001120: 4b07 ldr r3, [pc, #28] ; (8001140 <MX_FDCAN1_Init+0x84>)
8001122: 2200 movs r2, #0
8001124: 639a str r2, [r3, #56] ; 0x38
hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
8001126: 4b06 ldr r3, [pc, #24] ; (8001140 <MX_FDCAN1_Init+0x84>)
8001128: 2200 movs r2, #0
800112a: 63da str r2, [r3, #60] ; 0x3c
if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK)
800112c: 4804 ldr r0, [pc, #16] ; (8001140 <MX_FDCAN1_Init+0x84>)
800112e: f002 fe3b bl 8003da8 <HAL_FDCAN_Init>
8001132: 4603 mov r3, r0
8001134: 2b00 cmp r3, #0
8001136: d001 beq.n 800113c <MX_FDCAN1_Init+0x80>
{
Error_Handler();
8001138: f000 fa0c bl 8001554 <Error_Handler>
}
/* USER CODE BEGIN FDCAN1_Init 2 */
/* USER CODE END FDCAN1_Init 2 */
}
800113c: bf00 nop
800113e: bd80 pop {r7, pc}
8001140: 2000029c .word 0x2000029c
8001144: 40006400 .word 0x40006400
08001148 <MX_I2C1_Init>:
* @brief I2C1 Initialization Function
* @param None
* @retval None
*/
static void MX_I2C1_Init(void)
{
8001148: b580 push {r7, lr}
800114a: af00 add r7, sp, #0
/* USER CODE END I2C1_Init 0 */
/* USER CODE BEGIN I2C1_Init 1 */
/* USER CODE END I2C1_Init 1 */
hi2c1.Instance = I2C1;
800114c: 4b1b ldr r3, [pc, #108] ; (80011bc <MX_I2C1_Init+0x74>)
800114e: 4a1c ldr r2, [pc, #112] ; (80011c0 <MX_I2C1_Init+0x78>)
8001150: 601a str r2, [r3, #0]
hi2c1.Init.Timing = 0x00303D5B;
8001152: 4b1a ldr r3, [pc, #104] ; (80011bc <MX_I2C1_Init+0x74>)
8001154: 4a1b ldr r2, [pc, #108] ; (80011c4 <MX_I2C1_Init+0x7c>)
8001156: 605a str r2, [r3, #4]
hi2c1.Init.OwnAddress1 = 0;
8001158: 4b18 ldr r3, [pc, #96] ; (80011bc <MX_I2C1_Init+0x74>)
800115a: 2200 movs r2, #0
800115c: 609a str r2, [r3, #8]
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
800115e: 4b17 ldr r3, [pc, #92] ; (80011bc <MX_I2C1_Init+0x74>)
8001160: 2201 movs r2, #1
8001162: 60da str r2, [r3, #12]
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
8001164: 4b15 ldr r3, [pc, #84] ; (80011bc <MX_I2C1_Init+0x74>)
8001166: 2200 movs r2, #0
8001168: 611a str r2, [r3, #16]
hi2c1.Init.OwnAddress2 = 0;
800116a: 4b14 ldr r3, [pc, #80] ; (80011bc <MX_I2C1_Init+0x74>)
800116c: 2200 movs r2, #0
800116e: 615a str r2, [r3, #20]
hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
8001170: 4b12 ldr r3, [pc, #72] ; (80011bc <MX_I2C1_Init+0x74>)
8001172: 2200 movs r2, #0
8001174: 619a str r2, [r3, #24]
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
8001176: 4b11 ldr r3, [pc, #68] ; (80011bc <MX_I2C1_Init+0x74>)
8001178: 2200 movs r2, #0
800117a: 61da str r2, [r3, #28]
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
800117c: 4b0f ldr r3, [pc, #60] ; (80011bc <MX_I2C1_Init+0x74>)
800117e: 2200 movs r2, #0
8001180: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
8001182: 480e ldr r0, [pc, #56] ; (80011bc <MX_I2C1_Init+0x74>)
8001184: f003 fe30 bl 8004de8 <HAL_I2C_Init>
8001188: 4603 mov r3, r0
800118a: 2b00 cmp r3, #0
800118c: d001 beq.n 8001192 <MX_I2C1_Init+0x4a>
{
Error_Handler();
800118e: f000 f9e1 bl 8001554 <Error_Handler>
}
/** Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
8001192: 2100 movs r1, #0
8001194: 4809 ldr r0, [pc, #36] ; (80011bc <MX_I2C1_Init+0x74>)
8001196: f004 f9a9 bl 80054ec <HAL_I2CEx_ConfigAnalogFilter>
800119a: 4603 mov r3, r0
800119c: 2b00 cmp r3, #0
800119e: d001 beq.n 80011a4 <MX_I2C1_Init+0x5c>
{
Error_Handler();
80011a0: f000 f9d8 bl 8001554 <Error_Handler>
}
/** Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
80011a4: 2100 movs r1, #0
80011a6: 4805 ldr r0, [pc, #20] ; (80011bc <MX_I2C1_Init+0x74>)
80011a8: f004 f9eb bl 8005582 <HAL_I2CEx_ConfigDigitalFilter>
80011ac: 4603 mov r3, r0
80011ae: 2b00 cmp r3, #0
80011b0: d001 beq.n 80011b6 <MX_I2C1_Init+0x6e>
{
Error_Handler();
80011b2: f000 f9cf bl 8001554 <Error_Handler>
}
/* USER CODE BEGIN I2C1_Init 2 */
/* USER CODE END I2C1_Init 2 */
}
80011b6: bf00 nop
80011b8: bd80 pop {r7, pc}
80011ba: bf00 nop
80011bc: 20000300 .word 0x20000300
80011c0: 40005400 .word 0x40005400
80011c4: 00303d5b .word 0x00303d5b
080011c8 <MX_TIM2_Init>:
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
80011c8: b580 push {r7, lr}
80011ca: b08e sub sp, #56 ; 0x38
80011cc: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80011ce: f107 0328 add.w r3, r7, #40 ; 0x28
80011d2: 2200 movs r2, #0
80011d4: 601a str r2, [r3, #0]
80011d6: 605a str r2, [r3, #4]
80011d8: 609a str r2, [r3, #8]
80011da: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
80011dc: f107 031c add.w r3, r7, #28
80011e0: 2200 movs r2, #0
80011e2: 601a str r2, [r3, #0]
80011e4: 605a str r2, [r3, #4]
80011e6: 609a str r2, [r3, #8]
TIM_OC_InitTypeDef sConfigOC = {0};
80011e8: 463b mov r3, r7
80011ea: 2200 movs r2, #0
80011ec: 601a str r2, [r3, #0]
80011ee: 605a str r2, [r3, #4]
80011f0: 609a str r2, [r3, #8]
80011f2: 60da str r2, [r3, #12]
80011f4: 611a str r2, [r3, #16]
80011f6: 615a str r2, [r3, #20]
80011f8: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
80011fa: 4b2d ldr r3, [pc, #180] ; (80012b0 <MX_TIM2_Init+0xe8>)
80011fc: f04f 4280 mov.w r2, #1073741824 ; 0x40000000
8001200: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 4;
8001202: 4b2b ldr r3, [pc, #172] ; (80012b0 <MX_TIM2_Init+0xe8>)
8001204: 2204 movs r2, #4
8001206: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
8001208: 4b29 ldr r3, [pc, #164] ; (80012b0 <MX_TIM2_Init+0xe8>)
800120a: 2200 movs r2, #0
800120c: 609a str r2, [r3, #8]
htim2.Init.Period = 65535;
800120e: 4b28 ldr r3, [pc, #160] ; (80012b0 <MX_TIM2_Init+0xe8>)
8001210: f64f 72ff movw r2, #65535 ; 0xffff
8001214: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001216: 4b26 ldr r3, [pc, #152] ; (80012b0 <MX_TIM2_Init+0xe8>)
8001218: 2200 movs r2, #0
800121a: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800121c: 4b24 ldr r3, [pc, #144] ; (80012b0 <MX_TIM2_Init+0xe8>)
800121e: 2200 movs r2, #0
8001220: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
8001222: 4823 ldr r0, [pc, #140] ; (80012b0 <MX_TIM2_Init+0xe8>)
8001224: f005 f986 bl 8006534 <HAL_TIM_Base_Init>
8001228: 4603 mov r3, r0
800122a: 2b00 cmp r3, #0
800122c: d001 beq.n 8001232 <MX_TIM2_Init+0x6a>
{
Error_Handler();
800122e: f000 f991 bl 8001554 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8001232: f44f 5380 mov.w r3, #4096 ; 0x1000
8001236: 62bb str r3, [r7, #40] ; 0x28
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
8001238: f107 0328 add.w r3, r7, #40 ; 0x28
800123c: 4619 mov r1, r3
800123e: 481c ldr r0, [pc, #112] ; (80012b0 <MX_TIM2_Init+0xe8>)
8001240: f005 febe bl 8006fc0 <HAL_TIM_ConfigClockSource>
8001244: 4603 mov r3, r0
8001246: 2b00 cmp r3, #0
8001248: d001 beq.n 800124e <MX_TIM2_Init+0x86>
{
Error_Handler();
800124a: f000 f983 bl 8001554 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
800124e: 4818 ldr r0, [pc, #96] ; (80012b0 <MX_TIM2_Init+0xe8>)
8001250: f005 fa2a bl 80066a8 <HAL_TIM_PWM_Init>
8001254: 4603 mov r3, r0
8001256: 2b00 cmp r3, #0
8001258: d001 beq.n 800125e <MX_TIM2_Init+0x96>
{
Error_Handler();
800125a: f000 f97b bl 8001554 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
800125e: 2300 movs r3, #0
8001260: 61fb str r3, [r7, #28]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8001262: 2300 movs r3, #0
8001264: 627b str r3, [r7, #36] ; 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
8001266: f107 031c add.w r3, r7, #28
800126a: 4619 mov r1, r3
800126c: 4810 ldr r0, [pc, #64] ; (80012b0 <MX_TIM2_Init+0xe8>)
800126e: f006 fc1b bl 8007aa8 <HAL_TIMEx_MasterConfigSynchronization>
8001272: 4603 mov r3, r0
8001274: 2b00 cmp r3, #0
8001276: d001 beq.n 800127c <MX_TIM2_Init+0xb4>
{
Error_Handler();
8001278: f000 f96c bl 8001554 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
800127c: 2360 movs r3, #96 ; 0x60
800127e: 603b str r3, [r7, #0]
sConfigOC.Pulse = 0;
8001280: 2300 movs r3, #0
8001282: 607b str r3, [r7, #4]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8001284: 2300 movs r3, #0
8001286: 60bb str r3, [r7, #8]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8001288: 2300 movs r3, #0
800128a: 613b str r3, [r7, #16]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
800128c: 463b mov r3, r7
800128e: 2204 movs r2, #4
8001290: 4619 mov r1, r3
8001292: 4807 ldr r0, [pc, #28] ; (80012b0 <MX_TIM2_Init+0xe8>)
8001294: f005 fd80 bl 8006d98 <HAL_TIM_PWM_ConfigChannel>
8001298: 4603 mov r3, r0
800129a: 2b00 cmp r3, #0
800129c: d001 beq.n 80012a2 <MX_TIM2_Init+0xda>
{
Error_Handler();
800129e: f000 f959 bl 8001554 <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
HAL_TIM_MspPostInit(&htim2);
80012a2: 4803 ldr r0, [pc, #12] ; (80012b0 <MX_TIM2_Init+0xe8>)
80012a4: f000 fbf2 bl 8001a8c <HAL_TIM_MspPostInit>
}
80012a8: bf00 nop
80012aa: 3738 adds r7, #56 ; 0x38
80012ac: 46bd mov sp, r7
80012ae: bd80 pop {r7, pc}
80012b0: 2000034c .word 0x2000034c
080012b4 <MX_TIM3_Init>:
* @brief TIM3 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM3_Init(void)
{
80012b4: b580 push {r7, lr}
80012b6: b08e sub sp, #56 ; 0x38
80012b8: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80012ba: f107 0328 add.w r3, r7, #40 ; 0x28
80012be: 2200 movs r2, #0
80012c0: 601a str r2, [r3, #0]
80012c2: 605a str r2, [r3, #4]
80012c4: 609a str r2, [r3, #8]
80012c6: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
80012c8: f107 031c add.w r3, r7, #28
80012cc: 2200 movs r2, #0
80012ce: 601a str r2, [r3, #0]
80012d0: 605a str r2, [r3, #4]
80012d2: 609a str r2, [r3, #8]
TIM_OC_InitTypeDef sConfigOC = {0};
80012d4: 463b mov r3, r7
80012d6: 2200 movs r2, #0
80012d8: 601a str r2, [r3, #0]
80012da: 605a str r2, [r3, #4]
80012dc: 609a str r2, [r3, #8]
80012de: 60da str r2, [r3, #12]
80012e0: 611a str r2, [r3, #16]
80012e2: 615a str r2, [r3, #20]
80012e4: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
80012e6: 4b32 ldr r3, [pc, #200] ; (80013b0 <MX_TIM3_Init+0xfc>)
80012e8: 4a32 ldr r2, [pc, #200] ; (80013b4 <MX_TIM3_Init+0x100>)
80012ea: 601a str r2, [r3, #0]
htim3.Init.Prescaler = 4;
80012ec: 4b30 ldr r3, [pc, #192] ; (80013b0 <MX_TIM3_Init+0xfc>)
80012ee: 2204 movs r2, #4
80012f0: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
80012f2: 4b2f ldr r3, [pc, #188] ; (80013b0 <MX_TIM3_Init+0xfc>)
80012f4: 2200 movs r2, #0
80012f6: 609a str r2, [r3, #8]
htim3.Init.Period = 65535;
80012f8: 4b2d ldr r3, [pc, #180] ; (80013b0 <MX_TIM3_Init+0xfc>)
80012fa: f64f 72ff movw r2, #65535 ; 0xffff
80012fe: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001300: 4b2b ldr r3, [pc, #172] ; (80013b0 <MX_TIM3_Init+0xfc>)
8001302: 2200 movs r2, #0
8001304: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8001306: 4b2a ldr r3, [pc, #168] ; (80013b0 <MX_TIM3_Init+0xfc>)
8001308: 2200 movs r2, #0
800130a: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
800130c: 4828 ldr r0, [pc, #160] ; (80013b0 <MX_TIM3_Init+0xfc>)
800130e: f005 f911 bl 8006534 <HAL_TIM_Base_Init>
8001312: 4603 mov r3, r0
8001314: 2b00 cmp r3, #0
8001316: d001 beq.n 800131c <MX_TIM3_Init+0x68>
{
Error_Handler();
8001318: f000 f91c bl 8001554 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
800131c: f44f 5380 mov.w r3, #4096 ; 0x1000
8001320: 62bb str r3, [r7, #40] ; 0x28
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
8001322: f107 0328 add.w r3, r7, #40 ; 0x28
8001326: 4619 mov r1, r3
8001328: 4821 ldr r0, [pc, #132] ; (80013b0 <MX_TIM3_Init+0xfc>)
800132a: f005 fe49 bl 8006fc0 <HAL_TIM_ConfigClockSource>
800132e: 4603 mov r3, r0
8001330: 2b00 cmp r3, #0
8001332: d001 beq.n 8001338 <MX_TIM3_Init+0x84>
{
Error_Handler();
8001334: f000 f90e bl 8001554 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
8001338: 481d ldr r0, [pc, #116] ; (80013b0 <MX_TIM3_Init+0xfc>)
800133a: f005 f9b5 bl 80066a8 <HAL_TIM_PWM_Init>
800133e: 4603 mov r3, r0
8001340: 2b00 cmp r3, #0
8001342: d001 beq.n 8001348 <MX_TIM3_Init+0x94>
{
Error_Handler();
8001344: f000 f906 bl 8001554 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8001348: 2300 movs r3, #0
800134a: 61fb str r3, [r7, #28]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
800134c: 2300 movs r3, #0
800134e: 627b str r3, [r7, #36] ; 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
8001350: f107 031c add.w r3, r7, #28
8001354: 4619 mov r1, r3
8001356: 4816 ldr r0, [pc, #88] ; (80013b0 <MX_TIM3_Init+0xfc>)
8001358: f006 fba6 bl 8007aa8 <HAL_TIMEx_MasterConfigSynchronization>
800135c: 4603 mov r3, r0
800135e: 2b00 cmp r3, #0
8001360: d001 beq.n 8001366 <MX_TIM3_Init+0xb2>
{
Error_Handler();
8001362: f000 f8f7 bl 8001554 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8001366: 2360 movs r3, #96 ; 0x60
8001368: 603b str r3, [r7, #0]
sConfigOC.Pulse = 0;
800136a: 2300 movs r3, #0
800136c: 607b str r3, [r7, #4]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
800136e: 2300 movs r3, #0
8001370: 60bb str r3, [r7, #8]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8001372: 2300 movs r3, #0
8001374: 613b str r3, [r7, #16]
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8001376: 463b mov r3, r7
8001378: 2200 movs r2, #0
800137a: 4619 mov r1, r3
800137c: 480c ldr r0, [pc, #48] ; (80013b0 <MX_TIM3_Init+0xfc>)
800137e: f005 fd0b bl 8006d98 <HAL_TIM_PWM_ConfigChannel>
8001382: 4603 mov r3, r0
8001384: 2b00 cmp r3, #0
8001386: d001 beq.n 800138c <MX_TIM3_Init+0xd8>
{
Error_Handler();
8001388: f000 f8e4 bl 8001554 <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
800138c: 463b mov r3, r7
800138e: 2204 movs r2, #4
8001390: 4619 mov r1, r3
8001392: 4807 ldr r0, [pc, #28] ; (80013b0 <MX_TIM3_Init+0xfc>)
8001394: f005 fd00 bl 8006d98 <HAL_TIM_PWM_ConfigChannel>
8001398: 4603 mov r3, r0
800139a: 2b00 cmp r3, #0
800139c: d001 beq.n 80013a2 <MX_TIM3_Init+0xee>
{
Error_Handler();
800139e: f000 f8d9 bl 8001554 <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
HAL_TIM_MspPostInit(&htim3);
80013a2: 4803 ldr r0, [pc, #12] ; (80013b0 <MX_TIM3_Init+0xfc>)
80013a4: f000 fb72 bl 8001a8c <HAL_TIM_MspPostInit>
}
80013a8: bf00 nop
80013aa: 3738 adds r7, #56 ; 0x38
80013ac: 46bd mov sp, r7
80013ae: bd80 pop {r7, pc}
80013b0: 20000398 .word 0x20000398
80013b4: 40000400 .word 0x40000400
080013b8 <MX_TIM7_Init>:
* @brief TIM7 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM7_Init(void)
{
80013b8: b580 push {r7, lr}
80013ba: b084 sub sp, #16
80013bc: af00 add r7, sp, #0
/* USER CODE BEGIN TIM7_Init 0 */
/* USER CODE END TIM7_Init 0 */
TIM_MasterConfigTypeDef sMasterConfig = {0};
80013be: 1d3b adds r3, r7, #4
80013c0: 2200 movs r2, #0
80013c2: 601a str r2, [r3, #0]
80013c4: 605a str r2, [r3, #4]
80013c6: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM7_Init 1 */
/* USER CODE END TIM7_Init 1 */
htim7.Instance = TIM7;
80013c8: 4b15 ldr r3, [pc, #84] ; (8001420 <MX_TIM7_Init+0x68>)
80013ca: 4a16 ldr r2, [pc, #88] ; (8001424 <MX_TIM7_Init+0x6c>)
80013cc: 601a str r2, [r3, #0]
htim7.Init.Prescaler = 400;
80013ce: 4b14 ldr r3, [pc, #80] ; (8001420 <MX_TIM7_Init+0x68>)
80013d0: f44f 72c8 mov.w r2, #400 ; 0x190
80013d4: 605a str r2, [r3, #4]
htim7.Init.CounterMode = TIM_COUNTERMODE_UP;
80013d6: 4b12 ldr r3, [pc, #72] ; (8001420 <MX_TIM7_Init+0x68>)
80013d8: 2200 movs r2, #0
80013da: 609a str r2, [r3, #8]
htim7.Init.Period = 65535;
80013dc: 4b10 ldr r3, [pc, #64] ; (8001420 <MX_TIM7_Init+0x68>)
80013de: f64f 72ff movw r2, #65535 ; 0xffff
80013e2: 60da str r2, [r3, #12]
htim7.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80013e4: 4b0e ldr r3, [pc, #56] ; (8001420 <MX_TIM7_Init+0x68>)
80013e6: 2200 movs r2, #0
80013e8: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim7) != HAL_OK)
80013ea: 480d ldr r0, [pc, #52] ; (8001420 <MX_TIM7_Init+0x68>)
80013ec: f005 f8a2 bl 8006534 <HAL_TIM_Base_Init>
80013f0: 4603 mov r3, r0
80013f2: 2b00 cmp r3, #0
80013f4: d001 beq.n 80013fa <MX_TIM7_Init+0x42>
{
Error_Handler();
80013f6: f000 f8ad bl 8001554 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
80013fa: 2320 movs r3, #32
80013fc: 607b str r3, [r7, #4]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80013fe: 2300 movs r3, #0
8001400: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim7, &sMasterConfig) != HAL_OK)
8001402: 1d3b adds r3, r7, #4
8001404: 4619 mov r1, r3
8001406: 4806 ldr r0, [pc, #24] ; (8001420 <MX_TIM7_Init+0x68>)
8001408: f006 fb4e bl 8007aa8 <HAL_TIMEx_MasterConfigSynchronization>
800140c: 4603 mov r3, r0
800140e: 2b00 cmp r3, #0
8001410: d001 beq.n 8001416 <MX_TIM7_Init+0x5e>
{
Error_Handler();
8001412: f000 f89f bl 8001554 <Error_Handler>
}
/* USER CODE BEGIN TIM7_Init 2 */
/* USER CODE END TIM7_Init 2 */
}
8001416: bf00 nop
8001418: 3710 adds r7, #16
800141a: 46bd mov sp, r7
800141c: bd80 pop {r7, pc}
800141e: bf00 nop
8001420: 200003e4 .word 0x200003e4
8001424: 40001400 .word 0x40001400
08001428 <MX_DMA_Init>:
/**
* Enable DMA controller clock
*/
static void MX_DMA_Init(void)
{
8001428: b580 push {r7, lr}
800142a: b082 sub sp, #8
800142c: af00 add r7, sp, #0
/* DMA controller clock enable */
__HAL_RCC_DMAMUX1_CLK_ENABLE();
800142e: 4b16 ldr r3, [pc, #88] ; (8001488 <MX_DMA_Init+0x60>)
8001430: 6c9b ldr r3, [r3, #72] ; 0x48
8001432: 4a15 ldr r2, [pc, #84] ; (8001488 <MX_DMA_Init+0x60>)
8001434: f043 0304 orr.w r3, r3, #4
8001438: 6493 str r3, [r2, #72] ; 0x48
800143a: 4b13 ldr r3, [pc, #76] ; (8001488 <MX_DMA_Init+0x60>)
800143c: 6c9b ldr r3, [r3, #72] ; 0x48
800143e: f003 0304 and.w r3, r3, #4
8001442: 607b str r3, [r7, #4]
8001444: 687b ldr r3, [r7, #4]
__HAL_RCC_DMA1_CLK_ENABLE();
8001446: 4b10 ldr r3, [pc, #64] ; (8001488 <MX_DMA_Init+0x60>)
8001448: 6c9b ldr r3, [r3, #72] ; 0x48
800144a: 4a0f ldr r2, [pc, #60] ; (8001488 <MX_DMA_Init+0x60>)
800144c: f043 0301 orr.w r3, r3, #1
8001450: 6493 str r3, [r2, #72] ; 0x48
8001452: 4b0d ldr r3, [pc, #52] ; (8001488 <MX_DMA_Init+0x60>)
8001454: 6c9b ldr r3, [r3, #72] ; 0x48
8001456: f003 0301 and.w r3, r3, #1
800145a: 603b str r3, [r7, #0]
800145c: 683b ldr r3, [r7, #0]
/* DMA interrupt init */
/* DMA1_Channel1_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
800145e: 2200 movs r2, #0
8001460: 2100 movs r1, #0
8001462: 200b movs r0, #11
8001464: f002 f9f9 bl 800385a <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
8001468: 200b movs r0, #11
800146a: f002 fa10 bl 800388e <HAL_NVIC_EnableIRQ>
/* DMA1_Channel2_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0);
800146e: 2200 movs r2, #0
8001470: 2100 movs r1, #0
8001472: 200c movs r0, #12
8001474: f002 f9f1 bl 800385a <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn);
8001478: 200c movs r0, #12
800147a: f002 fa08 bl 800388e <HAL_NVIC_EnableIRQ>
}
800147e: bf00 nop
8001480: 3708 adds r7, #8
8001482: 46bd mov sp, r7
8001484: bd80 pop {r7, pc}
8001486: bf00 nop
8001488: 40021000 .word 0x40021000
0800148c <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
800148c: b580 push {r7, lr}
800148e: b088 sub sp, #32
8001490: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001492: f107 030c add.w r3, r7, #12
8001496: 2200 movs r2, #0
8001498: 601a str r2, [r3, #0]
800149a: 605a str r2, [r3, #4]
800149c: 609a str r2, [r3, #8]
800149e: 60da str r2, [r3, #12]
80014a0: 611a str r2, [r3, #16]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOF_CLK_ENABLE();
80014a2: 4b2a ldr r3, [pc, #168] ; (800154c <MX_GPIO_Init+0xc0>)
80014a4: 6cdb ldr r3, [r3, #76] ; 0x4c
80014a6: 4a29 ldr r2, [pc, #164] ; (800154c <MX_GPIO_Init+0xc0>)
80014a8: f043 0320 orr.w r3, r3, #32
80014ac: 64d3 str r3, [r2, #76] ; 0x4c
80014ae: 4b27 ldr r3, [pc, #156] ; (800154c <MX_GPIO_Init+0xc0>)
80014b0: 6cdb ldr r3, [r3, #76] ; 0x4c
80014b2: f003 0320 and.w r3, r3, #32
80014b6: 60bb str r3, [r7, #8]
80014b8: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
80014ba: 4b24 ldr r3, [pc, #144] ; (800154c <MX_GPIO_Init+0xc0>)
80014bc: 6cdb ldr r3, [r3, #76] ; 0x4c
80014be: 4a23 ldr r2, [pc, #140] ; (800154c <MX_GPIO_Init+0xc0>)
80014c0: f043 0301 orr.w r3, r3, #1
80014c4: 64d3 str r3, [r2, #76] ; 0x4c
80014c6: 4b21 ldr r3, [pc, #132] ; (800154c <MX_GPIO_Init+0xc0>)
80014c8: 6cdb ldr r3, [r3, #76] ; 0x4c
80014ca: f003 0301 and.w r3, r3, #1
80014ce: 607b str r3, [r7, #4]
80014d0: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
80014d2: 4b1e ldr r3, [pc, #120] ; (800154c <MX_GPIO_Init+0xc0>)
80014d4: 6cdb ldr r3, [r3, #76] ; 0x4c
80014d6: 4a1d ldr r2, [pc, #116] ; (800154c <MX_GPIO_Init+0xc0>)
80014d8: f043 0302 orr.w r3, r3, #2
80014dc: 64d3 str r3, [r2, #76] ; 0x4c
80014de: 4b1b ldr r3, [pc, #108] ; (800154c <MX_GPIO_Init+0xc0>)
80014e0: 6cdb ldr r3, [r3, #76] ; 0x4c
80014e2: f003 0302 and.w r3, r3, #2
80014e6: 603b str r3, [r7, #0]
80014e8: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, Diagnose_Select2_Pin|Diagnose_Select1_Pin|Diagnose_Select4_Pin|Diagnose_Select3_Pin, GPIO_PIN_RESET);
80014ea: 2200 movs r2, #0
80014ec: f44f 41f0 mov.w r1, #30720 ; 0x7800
80014f0: 4817 ldr r0, [pc, #92] ; (8001550 <MX_GPIO_Init+0xc4>)
80014f2: f003 fc61 bl 8004db8 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(Status_LED_GPIO_Port, Status_LED_Pin, GPIO_PIN_RESET);
80014f6: 2200 movs r2, #0
80014f8: f44f 7180 mov.w r1, #256 ; 0x100
80014fc: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
8001500: f003 fc5a bl 8004db8 <HAL_GPIO_WritePin>
/*Configure GPIO pins : Diagnose_Select2_Pin Diagnose_Select1_Pin Diagnose_Select4_Pin Diagnose_Select3_Pin */
GPIO_InitStruct.Pin = Diagnose_Select2_Pin|Diagnose_Select1_Pin|Diagnose_Select4_Pin|Diagnose_Select3_Pin;
8001504: f44f 43f0 mov.w r3, #30720 ; 0x7800
8001508: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800150a: 2301 movs r3, #1
800150c: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800150e: 2300 movs r3, #0
8001510: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001512: 2300 movs r3, #0
8001514: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001516: f107 030c add.w r3, r7, #12
800151a: 4619 mov r1, r3
800151c: 480c ldr r0, [pc, #48] ; (8001550 <MX_GPIO_Init+0xc4>)
800151e: f003 fac9 bl 8004ab4 <HAL_GPIO_Init>
/*Configure GPIO pin : Status_LED_Pin */
GPIO_InitStruct.Pin = Status_LED_Pin;
8001522: f44f 7380 mov.w r3, #256 ; 0x100
8001526: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001528: 2301 movs r3, #1
800152a: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800152c: 2300 movs r3, #0
800152e: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001530: 2300 movs r3, #0
8001532: 61bb str r3, [r7, #24]
HAL_GPIO_Init(Status_LED_GPIO_Port, &GPIO_InitStruct);
8001534: f107 030c add.w r3, r7, #12
8001538: 4619 mov r1, r3
800153a: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
800153e: f003 fab9 bl 8004ab4 <HAL_GPIO_Init>
}
8001542: bf00 nop
8001544: 3720 adds r7, #32
8001546: 46bd mov sp, r7
8001548: bd80 pop {r7, pc}
800154a: bf00 nop
800154c: 40021000 .word 0x40021000
8001550: 48000400 .word 0x48000400
08001554 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8001554: b480 push {r7}
8001556: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8001558: b672 cpsid i
}
800155a: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
800155c: e7fe b.n 800155c <Error_Handler+0x8>
...
08001560 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8001560: b480 push {r7}
8001562: b083 sub sp, #12
8001564: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001566: 4b0f ldr r3, [pc, #60] ; (80015a4 <HAL_MspInit+0x44>)
8001568: 6e1b ldr r3, [r3, #96] ; 0x60
800156a: 4a0e ldr r2, [pc, #56] ; (80015a4 <HAL_MspInit+0x44>)
800156c: f043 0301 orr.w r3, r3, #1
8001570: 6613 str r3, [r2, #96] ; 0x60
8001572: 4b0c ldr r3, [pc, #48] ; (80015a4 <HAL_MspInit+0x44>)
8001574: 6e1b ldr r3, [r3, #96] ; 0x60
8001576: f003 0301 and.w r3, r3, #1
800157a: 607b str r3, [r7, #4]
800157c: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
800157e: 4b09 ldr r3, [pc, #36] ; (80015a4 <HAL_MspInit+0x44>)
8001580: 6d9b ldr r3, [r3, #88] ; 0x58
8001582: 4a08 ldr r2, [pc, #32] ; (80015a4 <HAL_MspInit+0x44>)
8001584: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8001588: 6593 str r3, [r2, #88] ; 0x58
800158a: 4b06 ldr r3, [pc, #24] ; (80015a4 <HAL_MspInit+0x44>)
800158c: 6d9b ldr r3, [r3, #88] ; 0x58
800158e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8001592: 603b str r3, [r7, #0]
8001594: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8001596: bf00 nop
8001598: 370c adds r7, #12
800159a: 46bd mov sp, r7
800159c: f85d 7b04 ldr.w r7, [sp], #4
80015a0: 4770 bx lr
80015a2: bf00 nop
80015a4: 40021000 .word 0x40021000
080015a8 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
80015a8: b580 push {r7, lr}
80015aa: b09e sub sp, #120 ; 0x78
80015ac: af00 add r7, sp, #0
80015ae: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80015b0: f107 0364 add.w r3, r7, #100 ; 0x64
80015b4: 2200 movs r2, #0
80015b6: 601a str r2, [r3, #0]
80015b8: 605a str r2, [r3, #4]
80015ba: 609a str r2, [r3, #8]
80015bc: 60da str r2, [r3, #12]
80015be: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
80015c0: f107 0320 add.w r3, r7, #32
80015c4: 2244 movs r2, #68 ; 0x44
80015c6: 2100 movs r1, #0
80015c8: 4618 mov r0, r3
80015ca: f006 fb59 bl 8007c80 <memset>
if(hadc->Instance==ADC1)
80015ce: 687b ldr r3, [r7, #4]
80015d0: 681b ldr r3, [r3, #0]
80015d2: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000
80015d6: f040 808a bne.w 80016ee <HAL_ADC_MspInit+0x146>
/* USER CODE END ADC1_MspInit 0 */
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12;
80015da: f44f 4300 mov.w r3, #32768 ; 0x8000
80015de: 623b str r3, [r7, #32]
PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
80015e0: f04f 5300 mov.w r3, #536870912 ; 0x20000000
80015e4: 65fb str r3, [r7, #92] ; 0x5c
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
80015e6: f107 0320 add.w r3, r7, #32
80015ea: 4618 mov r0, r3
80015ec: f004 fdb2 bl 8006154 <HAL_RCCEx_PeriphCLKConfig>
80015f0: 4603 mov r3, r0
80015f2: 2b00 cmp r3, #0
80015f4: d001 beq.n 80015fa <HAL_ADC_MspInit+0x52>
{
Error_Handler();
80015f6: f7ff ffad bl 8001554 <Error_Handler>
}
/* Peripheral clock enable */
HAL_RCC_ADC12_CLK_ENABLED++;
80015fa: 4b86 ldr r3, [pc, #536] ; (8001814 <HAL_ADC_MspInit+0x26c>)
80015fc: 681b ldr r3, [r3, #0]
80015fe: 3301 adds r3, #1
8001600: 4a84 ldr r2, [pc, #528] ; (8001814 <HAL_ADC_MspInit+0x26c>)
8001602: 6013 str r3, [r2, #0]
if(HAL_RCC_ADC12_CLK_ENABLED==1){
8001604: 4b83 ldr r3, [pc, #524] ; (8001814 <HAL_ADC_MspInit+0x26c>)
8001606: 681b ldr r3, [r3, #0]
8001608: 2b01 cmp r3, #1
800160a: d10b bne.n 8001624 <HAL_ADC_MspInit+0x7c>
__HAL_RCC_ADC12_CLK_ENABLE();
800160c: 4b82 ldr r3, [pc, #520] ; (8001818 <HAL_ADC_MspInit+0x270>)
800160e: 6cdb ldr r3, [r3, #76] ; 0x4c
8001610: 4a81 ldr r2, [pc, #516] ; (8001818 <HAL_ADC_MspInit+0x270>)
8001612: f443 5300 orr.w r3, r3, #8192 ; 0x2000
8001616: 64d3 str r3, [r2, #76] ; 0x4c
8001618: 4b7f ldr r3, [pc, #508] ; (8001818 <HAL_ADC_MspInit+0x270>)
800161a: 6cdb ldr r3, [r3, #76] ; 0x4c
800161c: f403 5300 and.w r3, r3, #8192 ; 0x2000
8001620: 61fb str r3, [r7, #28]
8001622: 69fb ldr r3, [r7, #28]
}
__HAL_RCC_GPIOA_CLK_ENABLE();
8001624: 4b7c ldr r3, [pc, #496] ; (8001818 <HAL_ADC_MspInit+0x270>)
8001626: 6cdb ldr r3, [r3, #76] ; 0x4c
8001628: 4a7b ldr r2, [pc, #492] ; (8001818 <HAL_ADC_MspInit+0x270>)
800162a: f043 0301 orr.w r3, r3, #1
800162e: 64d3 str r3, [r2, #76] ; 0x4c
8001630: 4b79 ldr r3, [pc, #484] ; (8001818 <HAL_ADC_MspInit+0x270>)
8001632: 6cdb ldr r3, [r3, #76] ; 0x4c
8001634: f003 0301 and.w r3, r3, #1
8001638: 61bb str r3, [r7, #24]
800163a: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOB_CLK_ENABLE();
800163c: 4b76 ldr r3, [pc, #472] ; (8001818 <HAL_ADC_MspInit+0x270>)
800163e: 6cdb ldr r3, [r3, #76] ; 0x4c
8001640: 4a75 ldr r2, [pc, #468] ; (8001818 <HAL_ADC_MspInit+0x270>)
8001642: f043 0302 orr.w r3, r3, #2
8001646: 64d3 str r3, [r2, #76] ; 0x4c
8001648: 4b73 ldr r3, [pc, #460] ; (8001818 <HAL_ADC_MspInit+0x270>)
800164a: 6cdb ldr r3, [r3, #76] ; 0x4c
800164c: f003 0302 and.w r3, r3, #2
8001650: 617b str r3, [r7, #20]
8001652: 697b ldr r3, [r7, #20]
PA2 ------> ADC1_IN3
PA3 ------> ADC1_IN4
PB0 ------> ADC1_IN15
PB1 ------> ADC1_IN12
*/
GPIO_InitStruct.Pin = ISense9_Pin|ISense8_Pin;
8001654: 230c movs r3, #12
8001656: 667b str r3, [r7, #100] ; 0x64
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001658: 2303 movs r3, #3
800165a: 66bb str r3, [r7, #104] ; 0x68
GPIO_InitStruct.Pull = GPIO_NOPULL;
800165c: 2300 movs r3, #0
800165e: 66fb str r3, [r7, #108] ; 0x6c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001660: f107 0364 add.w r3, r7, #100 ; 0x64
8001664: 4619 mov r1, r3
8001666: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
800166a: f003 fa23 bl 8004ab4 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = ISense3_Pin|ISense2_Pin;
800166e: 2303 movs r3, #3
8001670: 667b str r3, [r7, #100] ; 0x64
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001672: 2303 movs r3, #3
8001674: 66bb str r3, [r7, #104] ; 0x68
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001676: 2300 movs r3, #0
8001678: 66fb str r3, [r7, #108] ; 0x6c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800167a: f107 0364 add.w r3, r7, #100 ; 0x64
800167e: 4619 mov r1, r3
8001680: 4866 ldr r0, [pc, #408] ; (800181c <HAL_ADC_MspInit+0x274>)
8001682: f003 fa17 bl 8004ab4 <HAL_GPIO_Init>
/* ADC1 DMA Init */
/* ADC1 Init */
hdma_adc1.Instance = DMA1_Channel2;
8001686: 4b66 ldr r3, [pc, #408] ; (8001820 <HAL_ADC_MspInit+0x278>)
8001688: 4a66 ldr r2, [pc, #408] ; (8001824 <HAL_ADC_MspInit+0x27c>)
800168a: 601a str r2, [r3, #0]
hdma_adc1.Init.Request = DMA_REQUEST_ADC1;
800168c: 4b64 ldr r3, [pc, #400] ; (8001820 <HAL_ADC_MspInit+0x278>)
800168e: 2205 movs r2, #5
8001690: 605a str r2, [r3, #4]
hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
8001692: 4b63 ldr r3, [pc, #396] ; (8001820 <HAL_ADC_MspInit+0x278>)
8001694: 2200 movs r2, #0
8001696: 609a str r2, [r3, #8]
hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
8001698: 4b61 ldr r3, [pc, #388] ; (8001820 <HAL_ADC_MspInit+0x278>)
800169a: 2200 movs r2, #0
800169c: 60da str r2, [r3, #12]
hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
800169e: 4b60 ldr r3, [pc, #384] ; (8001820 <HAL_ADC_MspInit+0x278>)
80016a0: 2280 movs r2, #128 ; 0x80
80016a2: 611a str r2, [r3, #16]
hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
80016a4: 4b5e ldr r3, [pc, #376] ; (8001820 <HAL_ADC_MspInit+0x278>)
80016a6: f44f 7280 mov.w r2, #256 ; 0x100
80016aa: 615a str r2, [r3, #20]
hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
80016ac: 4b5c ldr r3, [pc, #368] ; (8001820 <HAL_ADC_MspInit+0x278>)
80016ae: f44f 6280 mov.w r2, #1024 ; 0x400
80016b2: 619a str r2, [r3, #24]
hdma_adc1.Init.Mode = DMA_CIRCULAR;
80016b4: 4b5a ldr r3, [pc, #360] ; (8001820 <HAL_ADC_MspInit+0x278>)
80016b6: 2220 movs r2, #32
80016b8: 61da str r2, [r3, #28]
hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
80016ba: 4b59 ldr r3, [pc, #356] ; (8001820 <HAL_ADC_MspInit+0x278>)
80016bc: 2200 movs r2, #0
80016be: 621a str r2, [r3, #32]
if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
80016c0: 4857 ldr r0, [pc, #348] ; (8001820 <HAL_ADC_MspInit+0x278>)
80016c2: f002 f8ff bl 80038c4 <HAL_DMA_Init>
80016c6: 4603 mov r3, r0
80016c8: 2b00 cmp r3, #0
80016ca: d001 beq.n 80016d0 <HAL_ADC_MspInit+0x128>
{
Error_Handler();
80016cc: f7ff ff42 bl 8001554 <Error_Handler>
}
__HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
80016d0: 687b ldr r3, [r7, #4]
80016d2: 4a53 ldr r2, [pc, #332] ; (8001820 <HAL_ADC_MspInit+0x278>)
80016d4: 655a str r2, [r3, #84] ; 0x54
80016d6: 4a52 ldr r2, [pc, #328] ; (8001820 <HAL_ADC_MspInit+0x278>)
80016d8: 687b ldr r3, [r7, #4]
80016da: 6293 str r3, [r2, #40] ; 0x28
/* ADC1 interrupt Init */
HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0);
80016dc: 2200 movs r2, #0
80016de: 2100 movs r1, #0
80016e0: 2012 movs r0, #18
80016e2: f002 f8ba bl 800385a <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
80016e6: 2012 movs r0, #18
80016e8: f002 f8d1 bl 800388e <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN ADC2_MspInit 1 */
/* USER CODE END ADC2_MspInit 1 */
}
}
80016ec: e08e b.n 800180c <HAL_ADC_MspInit+0x264>
else if(hadc->Instance==ADC2)
80016ee: 687b ldr r3, [r7, #4]
80016f0: 681b ldr r3, [r3, #0]
80016f2: 4a4d ldr r2, [pc, #308] ; (8001828 <HAL_ADC_MspInit+0x280>)
80016f4: 4293 cmp r3, r2
80016f6: f040 8089 bne.w 800180c <HAL_ADC_MspInit+0x264>
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12;
80016fa: f44f 4300 mov.w r3, #32768 ; 0x8000
80016fe: 623b str r3, [r7, #32]
PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
8001700: f04f 5300 mov.w r3, #536870912 ; 0x20000000
8001704: 65fb str r3, [r7, #92] ; 0x5c
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8001706: f107 0320 add.w r3, r7, #32
800170a: 4618 mov r0, r3
800170c: f004 fd22 bl 8006154 <HAL_RCCEx_PeriphCLKConfig>
8001710: 4603 mov r3, r0
8001712: 2b00 cmp r3, #0
8001714: d001 beq.n 800171a <HAL_ADC_MspInit+0x172>
Error_Handler();
8001716: f7ff ff1d bl 8001554 <Error_Handler>
HAL_RCC_ADC12_CLK_ENABLED++;
800171a: 4b3e ldr r3, [pc, #248] ; (8001814 <HAL_ADC_MspInit+0x26c>)
800171c: 681b ldr r3, [r3, #0]
800171e: 3301 adds r3, #1
8001720: 4a3c ldr r2, [pc, #240] ; (8001814 <HAL_ADC_MspInit+0x26c>)
8001722: 6013 str r3, [r2, #0]
if(HAL_RCC_ADC12_CLK_ENABLED==1){
8001724: 4b3b ldr r3, [pc, #236] ; (8001814 <HAL_ADC_MspInit+0x26c>)
8001726: 681b ldr r3, [r3, #0]
8001728: 2b01 cmp r3, #1
800172a: d10b bne.n 8001744 <HAL_ADC_MspInit+0x19c>
__HAL_RCC_ADC12_CLK_ENABLE();
800172c: 4b3a ldr r3, [pc, #232] ; (8001818 <HAL_ADC_MspInit+0x270>)
800172e: 6cdb ldr r3, [r3, #76] ; 0x4c
8001730: 4a39 ldr r2, [pc, #228] ; (8001818 <HAL_ADC_MspInit+0x270>)
8001732: f443 5300 orr.w r3, r3, #8192 ; 0x2000
8001736: 64d3 str r3, [r2, #76] ; 0x4c
8001738: 4b37 ldr r3, [pc, #220] ; (8001818 <HAL_ADC_MspInit+0x270>)
800173a: 6cdb ldr r3, [r3, #76] ; 0x4c
800173c: f403 5300 and.w r3, r3, #8192 ; 0x2000
8001740: 613b str r3, [r7, #16]
8001742: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001744: 4b34 ldr r3, [pc, #208] ; (8001818 <HAL_ADC_MspInit+0x270>)
8001746: 6cdb ldr r3, [r3, #76] ; 0x4c
8001748: 4a33 ldr r2, [pc, #204] ; (8001818 <HAL_ADC_MspInit+0x270>)
800174a: f043 0301 orr.w r3, r3, #1
800174e: 64d3 str r3, [r2, #76] ; 0x4c
8001750: 4b31 ldr r3, [pc, #196] ; (8001818 <HAL_ADC_MspInit+0x270>)
8001752: 6cdb ldr r3, [r3, #76] ; 0x4c
8001754: f003 0301 and.w r3, r3, #1
8001758: 60fb str r3, [r7, #12]
800175a: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
800175c: 4b2e ldr r3, [pc, #184] ; (8001818 <HAL_ADC_MspInit+0x270>)
800175e: 6cdb ldr r3, [r3, #76] ; 0x4c
8001760: 4a2d ldr r2, [pc, #180] ; (8001818 <HAL_ADC_MspInit+0x270>)
8001762: f043 0302 orr.w r3, r3, #2
8001766: 64d3 str r3, [r2, #76] ; 0x4c
8001768: 4b2b ldr r3, [pc, #172] ; (8001818 <HAL_ADC_MspInit+0x270>)
800176a: 6cdb ldr r3, [r3, #76] ; 0x4c
800176c: f003 0302 and.w r3, r3, #2
8001770: 60bb str r3, [r7, #8]
8001772: 68bb ldr r3, [r7, #8]
GPIO_InitStruct.Pin = ISense11_Pin|ISense10_Pin|ISense6_Pin|ISense7_Pin
8001774: 23f3 movs r3, #243 ; 0xf3
8001776: 667b str r3, [r7, #100] ; 0x64
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001778: 2303 movs r3, #3
800177a: 66bb str r3, [r7, #104] ; 0x68
GPIO_InitStruct.Pull = GPIO_NOPULL;
800177c: 2300 movs r3, #0
800177e: 66fb str r3, [r7, #108] ; 0x6c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001780: f107 0364 add.w r3, r7, #100 ; 0x64
8001784: 4619 mov r1, r3
8001786: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
800178a: f003 f993 bl 8004ab4 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = ISense1_Pin;
800178e: 2304 movs r3, #4
8001790: 667b str r3, [r7, #100] ; 0x64
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001792: 2303 movs r3, #3
8001794: 66bb str r3, [r7, #104] ; 0x68
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001796: 2300 movs r3, #0
8001798: 66fb str r3, [r7, #108] ; 0x6c
HAL_GPIO_Init(ISense1_GPIO_Port, &GPIO_InitStruct);
800179a: f107 0364 add.w r3, r7, #100 ; 0x64
800179e: 4619 mov r1, r3
80017a0: 481e ldr r0, [pc, #120] ; (800181c <HAL_ADC_MspInit+0x274>)
80017a2: f003 f987 bl 8004ab4 <HAL_GPIO_Init>
hdma_adc2.Instance = DMA1_Channel1;
80017a6: 4b21 ldr r3, [pc, #132] ; (800182c <HAL_ADC_MspInit+0x284>)
80017a8: 4a21 ldr r2, [pc, #132] ; (8001830 <HAL_ADC_MspInit+0x288>)
80017aa: 601a str r2, [r3, #0]
hdma_adc2.Init.Request = DMA_REQUEST_ADC2;
80017ac: 4b1f ldr r3, [pc, #124] ; (800182c <HAL_ADC_MspInit+0x284>)
80017ae: 2224 movs r2, #36 ; 0x24
80017b0: 605a str r2, [r3, #4]
hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY;
80017b2: 4b1e ldr r3, [pc, #120] ; (800182c <HAL_ADC_MspInit+0x284>)
80017b4: 2200 movs r2, #0
80017b6: 609a str r2, [r3, #8]
hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE;
80017b8: 4b1c ldr r3, [pc, #112] ; (800182c <HAL_ADC_MspInit+0x284>)
80017ba: 2200 movs r2, #0
80017bc: 60da str r2, [r3, #12]
hdma_adc2.Init.MemInc = DMA_MINC_ENABLE;
80017be: 4b1b ldr r3, [pc, #108] ; (800182c <HAL_ADC_MspInit+0x284>)
80017c0: 2280 movs r2, #128 ; 0x80
80017c2: 611a str r2, [r3, #16]
hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
80017c4: 4b19 ldr r3, [pc, #100] ; (800182c <HAL_ADC_MspInit+0x284>)
80017c6: f44f 7280 mov.w r2, #256 ; 0x100
80017ca: 615a str r2, [r3, #20]
hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
80017cc: 4b17 ldr r3, [pc, #92] ; (800182c <HAL_ADC_MspInit+0x284>)
80017ce: f44f 6280 mov.w r2, #1024 ; 0x400
80017d2: 619a str r2, [r3, #24]
hdma_adc2.Init.Mode = DMA_CIRCULAR;
80017d4: 4b15 ldr r3, [pc, #84] ; (800182c <HAL_ADC_MspInit+0x284>)
80017d6: 2220 movs r2, #32
80017d8: 61da str r2, [r3, #28]
hdma_adc2.Init.Priority = DMA_PRIORITY_LOW;
80017da: 4b14 ldr r3, [pc, #80] ; (800182c <HAL_ADC_MspInit+0x284>)
80017dc: 2200 movs r2, #0
80017de: 621a str r2, [r3, #32]
if (HAL_DMA_Init(&hdma_adc2) != HAL_OK)
80017e0: 4812 ldr r0, [pc, #72] ; (800182c <HAL_ADC_MspInit+0x284>)
80017e2: f002 f86f bl 80038c4 <HAL_DMA_Init>
80017e6: 4603 mov r3, r0
80017e8: 2b00 cmp r3, #0
80017ea: d001 beq.n 80017f0 <HAL_ADC_MspInit+0x248>
Error_Handler();
80017ec: f7ff feb2 bl 8001554 <Error_Handler>
__HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2);
80017f0: 687b ldr r3, [r7, #4]
80017f2: 4a0e ldr r2, [pc, #56] ; (800182c <HAL_ADC_MspInit+0x284>)
80017f4: 655a str r2, [r3, #84] ; 0x54
80017f6: 4a0d ldr r2, [pc, #52] ; (800182c <HAL_ADC_MspInit+0x284>)
80017f8: 687b ldr r3, [r7, #4]
80017fa: 6293 str r3, [r2, #40] ; 0x28
HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0);
80017fc: 2200 movs r2, #0
80017fe: 2100 movs r1, #0
8001800: 2012 movs r0, #18
8001802: f002 f82a bl 800385a <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
8001806: 2012 movs r0, #18
8001808: f002 f841 bl 800388e <HAL_NVIC_EnableIRQ>
}
800180c: bf00 nop
800180e: 3778 adds r7, #120 ; 0x78
8001810: 46bd mov sp, r7
8001812: bd80 pop {r7, pc}
8001814: 20000430 .word 0x20000430
8001818: 40021000 .word 0x40021000
800181c: 48000400 .word 0x48000400
8001820: 200001dc .word 0x200001dc
8001824: 4002001c .word 0x4002001c
8001828: 50000100 .word 0x50000100
800182c: 2000023c .word 0x2000023c
8001830: 40020008 .word 0x40020008
08001834 <HAL_FDCAN_MspInit>:
* This function configures the hardware resources used in this example
* @param hfdcan: FDCAN handle pointer
* @retval None
*/
void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan)
{
8001834: b580 push {r7, lr}
8001836: b09a sub sp, #104 ; 0x68
8001838: af00 add r7, sp, #0
800183a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800183c: f107 0354 add.w r3, r7, #84 ; 0x54
8001840: 2200 movs r2, #0
8001842: 601a str r2, [r3, #0]
8001844: 605a str r2, [r3, #4]
8001846: 609a str r2, [r3, #8]
8001848: 60da str r2, [r3, #12]
800184a: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
800184c: f107 0310 add.w r3, r7, #16
8001850: 2244 movs r2, #68 ; 0x44
8001852: 2100 movs r1, #0
8001854: 4618 mov r0, r3
8001856: f006 fa13 bl 8007c80 <memset>
if(hfdcan->Instance==FDCAN1)
800185a: 687b ldr r3, [r7, #4]
800185c: 681b ldr r3, [r3, #0]
800185e: 4a28 ldr r2, [pc, #160] ; (8001900 <HAL_FDCAN_MspInit+0xcc>)
8001860: 4293 cmp r3, r2
8001862: d149 bne.n 80018f8 <HAL_FDCAN_MspInit+0xc4>
/* USER CODE END FDCAN1_MspInit 0 */
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
8001864: f44f 5380 mov.w r3, #4096 ; 0x1000
8001868: 613b str r3, [r7, #16]
PeriphClkInit.FdcanClockSelection = RCC_FDCANCLKSOURCE_PCLK1;
800186a: f04f 7300 mov.w r3, #33554432 ; 0x2000000
800186e: 643b str r3, [r7, #64] ; 0x40
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8001870: f107 0310 add.w r3, r7, #16
8001874: 4618 mov r0, r3
8001876: f004 fc6d bl 8006154 <HAL_RCCEx_PeriphCLKConfig>
800187a: 4603 mov r3, r0
800187c: 2b00 cmp r3, #0
800187e: d001 beq.n 8001884 <HAL_FDCAN_MspInit+0x50>
{
Error_Handler();
8001880: f7ff fe68 bl 8001554 <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_FDCAN_CLK_ENABLE();
8001884: 4b1f ldr r3, [pc, #124] ; (8001904 <HAL_FDCAN_MspInit+0xd0>)
8001886: 6d9b ldr r3, [r3, #88] ; 0x58
8001888: 4a1e ldr r2, [pc, #120] ; (8001904 <HAL_FDCAN_MspInit+0xd0>)
800188a: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
800188e: 6593 str r3, [r2, #88] ; 0x58
8001890: 4b1c ldr r3, [pc, #112] ; (8001904 <HAL_FDCAN_MspInit+0xd0>)
8001892: 6d9b ldr r3, [r3, #88] ; 0x58
8001894: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001898: 60fb str r3, [r7, #12]
800189a: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
800189c: 4b19 ldr r3, [pc, #100] ; (8001904 <HAL_FDCAN_MspInit+0xd0>)
800189e: 6cdb ldr r3, [r3, #76] ; 0x4c
80018a0: 4a18 ldr r2, [pc, #96] ; (8001904 <HAL_FDCAN_MspInit+0xd0>)
80018a2: f043 0301 orr.w r3, r3, #1
80018a6: 64d3 str r3, [r2, #76] ; 0x4c
80018a8: 4b16 ldr r3, [pc, #88] ; (8001904 <HAL_FDCAN_MspInit+0xd0>)
80018aa: 6cdb ldr r3, [r3, #76] ; 0x4c
80018ac: f003 0301 and.w r3, r3, #1
80018b0: 60bb str r3, [r7, #8]
80018b2: 68bb ldr r3, [r7, #8]
/**FDCAN1 GPIO Configuration
PA11 ------> FDCAN1_RX
PA12 ------> FDCAN1_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
80018b4: f44f 53c0 mov.w r3, #6144 ; 0x1800
80018b8: 657b str r3, [r7, #84] ; 0x54
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80018ba: 2302 movs r3, #2
80018bc: 65bb str r3, [r7, #88] ; 0x58
GPIO_InitStruct.Pull = GPIO_NOPULL;
80018be: 2300 movs r3, #0
80018c0: 65fb str r3, [r7, #92] ; 0x5c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80018c2: 2300 movs r3, #0
80018c4: 663b str r3, [r7, #96] ; 0x60
GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
80018c6: 2309 movs r3, #9
80018c8: 667b str r3, [r7, #100] ; 0x64
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80018ca: f107 0354 add.w r3, r7, #84 ; 0x54
80018ce: 4619 mov r1, r3
80018d0: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
80018d4: f003 f8ee bl 8004ab4 <HAL_GPIO_Init>
/* FDCAN1 interrupt Init */
HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 0, 0);
80018d8: 2200 movs r2, #0
80018da: 2100 movs r1, #0
80018dc: 2015 movs r0, #21
80018de: f001 ffbc bl 800385a <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
80018e2: 2015 movs r0, #21
80018e4: f001 ffd3 bl 800388e <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(FDCAN1_IT1_IRQn, 0, 0);
80018e8: 2200 movs r2, #0
80018ea: 2100 movs r1, #0
80018ec: 2016 movs r0, #22
80018ee: f001 ffb4 bl 800385a <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(FDCAN1_IT1_IRQn);
80018f2: 2016 movs r0, #22
80018f4: f001 ffcb bl 800388e <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN FDCAN1_MspInit 1 */
/* USER CODE END FDCAN1_MspInit 1 */
}
}
80018f8: bf00 nop
80018fa: 3768 adds r7, #104 ; 0x68
80018fc: 46bd mov sp, r7
80018fe: bd80 pop {r7, pc}
8001900: 40006400 .word 0x40006400
8001904: 40021000 .word 0x40021000
08001908 <HAL_I2C_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
8001908: b580 push {r7, lr}
800190a: b09c sub sp, #112 ; 0x70
800190c: af00 add r7, sp, #0
800190e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001910: f107 035c add.w r3, r7, #92 ; 0x5c
8001914: 2200 movs r2, #0
8001916: 601a str r2, [r3, #0]
8001918: 605a str r2, [r3, #4]
800191a: 609a str r2, [r3, #8]
800191c: 60da str r2, [r3, #12]
800191e: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8001920: f107 0318 add.w r3, r7, #24
8001924: 2244 movs r2, #68 ; 0x44
8001926: 2100 movs r1, #0
8001928: 4618 mov r0, r3
800192a: f006 f9a9 bl 8007c80 <memset>
if(hi2c->Instance==I2C1)
800192e: 687b ldr r3, [r7, #4]
8001930: 681b ldr r3, [r3, #0]
8001932: 4a2d ldr r2, [pc, #180] ; (80019e8 <HAL_I2C_MspInit+0xe0>)
8001934: 4293 cmp r3, r2
8001936: d153 bne.n 80019e0 <HAL_I2C_MspInit+0xd8>
/* USER CODE END I2C1_MspInit 0 */
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
8001938: 2340 movs r3, #64 ; 0x40
800193a: 61bb str r3, [r7, #24]
PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
800193c: 2300 movs r3, #0
800193e: 633b str r3, [r7, #48] ; 0x30
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8001940: f107 0318 add.w r3, r7, #24
8001944: 4618 mov r0, r3
8001946: f004 fc05 bl 8006154 <HAL_RCCEx_PeriphCLKConfig>
800194a: 4603 mov r3, r0
800194c: 2b00 cmp r3, #0
800194e: d001 beq.n 8001954 <HAL_I2C_MspInit+0x4c>
{
Error_Handler();
8001950: f7ff fe00 bl 8001554 <Error_Handler>
}
__HAL_RCC_GPIOA_CLK_ENABLE();
8001954: 4b25 ldr r3, [pc, #148] ; (80019ec <HAL_I2C_MspInit+0xe4>)
8001956: 6cdb ldr r3, [r3, #76] ; 0x4c
8001958: 4a24 ldr r2, [pc, #144] ; (80019ec <HAL_I2C_MspInit+0xe4>)
800195a: f043 0301 orr.w r3, r3, #1
800195e: 64d3 str r3, [r2, #76] ; 0x4c
8001960: 4b22 ldr r3, [pc, #136] ; (80019ec <HAL_I2C_MspInit+0xe4>)
8001962: 6cdb ldr r3, [r3, #76] ; 0x4c
8001964: f003 0301 and.w r3, r3, #1
8001968: 617b str r3, [r7, #20]
800196a: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOB_CLK_ENABLE();
800196c: 4b1f ldr r3, [pc, #124] ; (80019ec <HAL_I2C_MspInit+0xe4>)
800196e: 6cdb ldr r3, [r3, #76] ; 0x4c
8001970: 4a1e ldr r2, [pc, #120] ; (80019ec <HAL_I2C_MspInit+0xe4>)
8001972: f043 0302 orr.w r3, r3, #2
8001976: 64d3 str r3, [r2, #76] ; 0x4c
8001978: 4b1c ldr r3, [pc, #112] ; (80019ec <HAL_I2C_MspInit+0xe4>)
800197a: 6cdb ldr r3, [r3, #76] ; 0x4c
800197c: f003 0302 and.w r3, r3, #2
8001980: 613b str r3, [r7, #16]
8001982: 693b ldr r3, [r7, #16]
/**I2C1 GPIO Configuration
PA15 ------> I2C1_SCL
PB7 ------> I2C1_SDA
*/
GPIO_InitStruct.Pin = GPIO_PIN_15;
8001984: f44f 4300 mov.w r3, #32768 ; 0x8000
8001988: 65fb str r3, [r7, #92] ; 0x5c
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
800198a: 2312 movs r3, #18
800198c: 663b str r3, [r7, #96] ; 0x60
GPIO_InitStruct.Pull = GPIO_NOPULL;
800198e: 2300 movs r3, #0
8001990: 667b str r3, [r7, #100] ; 0x64
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001992: 2300 movs r3, #0
8001994: 66bb str r3, [r7, #104] ; 0x68
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
8001996: 2304 movs r3, #4
8001998: 66fb str r3, [r7, #108] ; 0x6c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800199a: f107 035c add.w r3, r7, #92 ; 0x5c
800199e: 4619 mov r1, r3
80019a0: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
80019a4: f003 f886 bl 8004ab4 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_7;
80019a8: 2380 movs r3, #128 ; 0x80
80019aa: 65fb str r3, [r7, #92] ; 0x5c
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
80019ac: 2312 movs r3, #18
80019ae: 663b str r3, [r7, #96] ; 0x60
GPIO_InitStruct.Pull = GPIO_NOPULL;
80019b0: 2300 movs r3, #0
80019b2: 667b str r3, [r7, #100] ; 0x64
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80019b4: 2300 movs r3, #0
80019b6: 66bb str r3, [r7, #104] ; 0x68
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
80019b8: 2304 movs r3, #4
80019ba: 66fb str r3, [r7, #108] ; 0x6c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80019bc: f107 035c add.w r3, r7, #92 ; 0x5c
80019c0: 4619 mov r1, r3
80019c2: 480b ldr r0, [pc, #44] ; (80019f0 <HAL_I2C_MspInit+0xe8>)
80019c4: f003 f876 bl 8004ab4 <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_I2C1_CLK_ENABLE();
80019c8: 4b08 ldr r3, [pc, #32] ; (80019ec <HAL_I2C_MspInit+0xe4>)
80019ca: 6d9b ldr r3, [r3, #88] ; 0x58
80019cc: 4a07 ldr r2, [pc, #28] ; (80019ec <HAL_I2C_MspInit+0xe4>)
80019ce: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
80019d2: 6593 str r3, [r2, #88] ; 0x58
80019d4: 4b05 ldr r3, [pc, #20] ; (80019ec <HAL_I2C_MspInit+0xe4>)
80019d6: 6d9b ldr r3, [r3, #88] ; 0x58
80019d8: f403 1300 and.w r3, r3, #2097152 ; 0x200000
80019dc: 60fb str r3, [r7, #12]
80019de: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN I2C1_MspInit 1 */
/* USER CODE END I2C1_MspInit 1 */
}
}
80019e0: bf00 nop
80019e2: 3770 adds r7, #112 ; 0x70
80019e4: 46bd mov sp, r7
80019e6: bd80 pop {r7, pc}
80019e8: 40005400 .word 0x40005400
80019ec: 40021000 .word 0x40021000
80019f0: 48000400 .word 0x48000400
080019f4 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
80019f4: b580 push {r7, lr}
80019f6: b086 sub sp, #24
80019f8: af00 add r7, sp, #0
80019fa: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM2)
80019fc: 687b ldr r3, [r7, #4]
80019fe: 681b ldr r3, [r3, #0]
8001a00: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8001a04: d10c bne.n 8001a20 <HAL_TIM_Base_MspInit+0x2c>
{
/* USER CODE BEGIN TIM2_MspInit 0 */
/* USER CODE END TIM2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM2_CLK_ENABLE();
8001a06: 4b1e ldr r3, [pc, #120] ; (8001a80 <HAL_TIM_Base_MspInit+0x8c>)
8001a08: 6d9b ldr r3, [r3, #88] ; 0x58
8001a0a: 4a1d ldr r2, [pc, #116] ; (8001a80 <HAL_TIM_Base_MspInit+0x8c>)
8001a0c: f043 0301 orr.w r3, r3, #1
8001a10: 6593 str r3, [r2, #88] ; 0x58
8001a12: 4b1b ldr r3, [pc, #108] ; (8001a80 <HAL_TIM_Base_MspInit+0x8c>)
8001a14: 6d9b ldr r3, [r3, #88] ; 0x58
8001a16: f003 0301 and.w r3, r3, #1
8001a1a: 617b str r3, [r7, #20]
8001a1c: 697b ldr r3, [r7, #20]
/* USER CODE BEGIN TIM7_MspInit 1 */
/* USER CODE END TIM7_MspInit 1 */
}
}
8001a1e: e02a b.n 8001a76 <HAL_TIM_Base_MspInit+0x82>
else if(htim_base->Instance==TIM3)
8001a20: 687b ldr r3, [r7, #4]
8001a22: 681b ldr r3, [r3, #0]
8001a24: 4a17 ldr r2, [pc, #92] ; (8001a84 <HAL_TIM_Base_MspInit+0x90>)
8001a26: 4293 cmp r3, r2
8001a28: d10c bne.n 8001a44 <HAL_TIM_Base_MspInit+0x50>
__HAL_RCC_TIM3_CLK_ENABLE();
8001a2a: 4b15 ldr r3, [pc, #84] ; (8001a80 <HAL_TIM_Base_MspInit+0x8c>)
8001a2c: 6d9b ldr r3, [r3, #88] ; 0x58
8001a2e: 4a14 ldr r2, [pc, #80] ; (8001a80 <HAL_TIM_Base_MspInit+0x8c>)
8001a30: f043 0302 orr.w r3, r3, #2
8001a34: 6593 str r3, [r2, #88] ; 0x58
8001a36: 4b12 ldr r3, [pc, #72] ; (8001a80 <HAL_TIM_Base_MspInit+0x8c>)
8001a38: 6d9b ldr r3, [r3, #88] ; 0x58
8001a3a: f003 0302 and.w r3, r3, #2
8001a3e: 613b str r3, [r7, #16]
8001a40: 693b ldr r3, [r7, #16]
}
8001a42: e018 b.n 8001a76 <HAL_TIM_Base_MspInit+0x82>
else if(htim_base->Instance==TIM7)
8001a44: 687b ldr r3, [r7, #4]
8001a46: 681b ldr r3, [r3, #0]
8001a48: 4a0f ldr r2, [pc, #60] ; (8001a88 <HAL_TIM_Base_MspInit+0x94>)
8001a4a: 4293 cmp r3, r2
8001a4c: d113 bne.n 8001a76 <HAL_TIM_Base_MspInit+0x82>
__HAL_RCC_TIM7_CLK_ENABLE();
8001a4e: 4b0c ldr r3, [pc, #48] ; (8001a80 <HAL_TIM_Base_MspInit+0x8c>)
8001a50: 6d9b ldr r3, [r3, #88] ; 0x58
8001a52: 4a0b ldr r2, [pc, #44] ; (8001a80 <HAL_TIM_Base_MspInit+0x8c>)
8001a54: f043 0320 orr.w r3, r3, #32
8001a58: 6593 str r3, [r2, #88] ; 0x58
8001a5a: 4b09 ldr r3, [pc, #36] ; (8001a80 <HAL_TIM_Base_MspInit+0x8c>)
8001a5c: 6d9b ldr r3, [r3, #88] ; 0x58
8001a5e: f003 0320 and.w r3, r3, #32
8001a62: 60fb str r3, [r7, #12]
8001a64: 68fb ldr r3, [r7, #12]
HAL_NVIC_SetPriority(TIM7_IRQn, 0, 0);
8001a66: 2200 movs r2, #0
8001a68: 2100 movs r1, #0
8001a6a: 2037 movs r0, #55 ; 0x37
8001a6c: f001 fef5 bl 800385a <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM7_IRQn);
8001a70: 2037 movs r0, #55 ; 0x37
8001a72: f001 ff0c bl 800388e <HAL_NVIC_EnableIRQ>
}
8001a76: bf00 nop
8001a78: 3718 adds r7, #24
8001a7a: 46bd mov sp, r7
8001a7c: bd80 pop {r7, pc}
8001a7e: bf00 nop
8001a80: 40021000 .word 0x40021000
8001a84: 40000400 .word 0x40000400
8001a88: 40001400 .word 0x40001400
08001a8c <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8001a8c: b580 push {r7, lr}
8001a8e: b08a sub sp, #40 ; 0x28
8001a90: af00 add r7, sp, #0
8001a92: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001a94: f107 0314 add.w r3, r7, #20
8001a98: 2200 movs r2, #0
8001a9a: 601a str r2, [r3, #0]
8001a9c: 605a str r2, [r3, #4]
8001a9e: 609a str r2, [r3, #8]
8001aa0: 60da str r2, [r3, #12]
8001aa2: 611a str r2, [r3, #16]
if(htim->Instance==TIM2)
8001aa4: 687b ldr r3, [r7, #4]
8001aa6: 681b ldr r3, [r3, #0]
8001aa8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8001aac: d11c bne.n 8001ae8 <HAL_TIM_MspPostInit+0x5c>
{
/* USER CODE BEGIN TIM2_MspPostInit 0 */
/* USER CODE END TIM2_MspPostInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
8001aae: 4b21 ldr r3, [pc, #132] ; (8001b34 <HAL_TIM_MspPostInit+0xa8>)
8001ab0: 6cdb ldr r3, [r3, #76] ; 0x4c
8001ab2: 4a20 ldr r2, [pc, #128] ; (8001b34 <HAL_TIM_MspPostInit+0xa8>)
8001ab4: f043 0302 orr.w r3, r3, #2
8001ab8: 64d3 str r3, [r2, #76] ; 0x4c
8001aba: 4b1e ldr r3, [pc, #120] ; (8001b34 <HAL_TIM_MspPostInit+0xa8>)
8001abc: 6cdb ldr r3, [r3, #76] ; 0x4c
8001abe: f003 0302 and.w r3, r3, #2
8001ac2: 613b str r3, [r7, #16]
8001ac4: 693b ldr r3, [r7, #16]
/**TIM2 GPIO Configuration
PB3 ------> TIM2_CH2
*/
GPIO_InitStruct.Pin = Fans_PWM_Pin;
8001ac6: 2308 movs r3, #8
8001ac8: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001aca: 2302 movs r3, #2
8001acc: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001ace: 2300 movs r3, #0
8001ad0: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001ad2: 2300 movs r3, #0
8001ad4: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
8001ad6: 2301 movs r3, #1
8001ad8: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(Fans_PWM_GPIO_Port, &GPIO_InitStruct);
8001ada: f107 0314 add.w r3, r7, #20
8001ade: 4619 mov r1, r3
8001ae0: 4815 ldr r0, [pc, #84] ; (8001b38 <HAL_TIM_MspPostInit+0xac>)
8001ae2: f002 ffe7 bl 8004ab4 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM3_MspPostInit 1 */
/* USER CODE END TIM3_MspPostInit 1 */
}
}
8001ae6: e020 b.n 8001b2a <HAL_TIM_MspPostInit+0x9e>
else if(htim->Instance==TIM3)
8001ae8: 687b ldr r3, [r7, #4]
8001aea: 681b ldr r3, [r3, #0]
8001aec: 4a13 ldr r2, [pc, #76] ; (8001b3c <HAL_TIM_MspPostInit+0xb0>)
8001aee: 4293 cmp r3, r2
8001af0: d11b bne.n 8001b2a <HAL_TIM_MspPostInit+0x9e>
__HAL_RCC_GPIOB_CLK_ENABLE();
8001af2: 4b10 ldr r3, [pc, #64] ; (8001b34 <HAL_TIM_MspPostInit+0xa8>)
8001af4: 6cdb ldr r3, [r3, #76] ; 0x4c
8001af6: 4a0f ldr r2, [pc, #60] ; (8001b34 <HAL_TIM_MspPostInit+0xa8>)
8001af8: f043 0302 orr.w r3, r3, #2
8001afc: 64d3 str r3, [r2, #76] ; 0x4c
8001afe: 4b0d ldr r3, [pc, #52] ; (8001b34 <HAL_TIM_MspPostInit+0xa8>)
8001b00: 6cdb ldr r3, [r3, #76] ; 0x4c
8001b02: f003 0302 and.w r3, r3, #2
8001b06: 60fb str r3, [r7, #12]
8001b08: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = Aggregat_PWM_Pin|Pumpe_PWM_Pin;
8001b0a: 2330 movs r3, #48 ; 0x30
8001b0c: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001b0e: 2302 movs r3, #2
8001b10: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b12: 2300 movs r3, #0
8001b14: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001b16: 2300 movs r3, #0
8001b18: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
8001b1a: 2302 movs r3, #2
8001b1c: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001b1e: f107 0314 add.w r3, r7, #20
8001b22: 4619 mov r1, r3
8001b24: 4804 ldr r0, [pc, #16] ; (8001b38 <HAL_TIM_MspPostInit+0xac>)
8001b26: f002 ffc5 bl 8004ab4 <HAL_GPIO_Init>
}
8001b2a: bf00 nop
8001b2c: 3728 adds r7, #40 ; 0x28
8001b2e: 46bd mov sp, r7
8001b30: bd80 pop {r7, pc}
8001b32: bf00 nop
8001b34: 40021000 .word 0x40021000
8001b38: 48000400 .word 0x48000400
8001b3c: 40000400 .word 0x40000400
08001b40 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001b40: b480 push {r7}
8001b42: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8001b44: e7fe b.n 8001b44 <NMI_Handler+0x4>
08001b46 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8001b46: b480 push {r7}
8001b48: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8001b4a: e7fe b.n 8001b4a <HardFault_Handler+0x4>
08001b4c <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8001b4c: b480 push {r7}
8001b4e: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8001b50: e7fe b.n 8001b50 <MemManage_Handler+0x4>
08001b52 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8001b52: b480 push {r7}
8001b54: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8001b56: e7fe b.n 8001b56 <BusFault_Handler+0x4>
08001b58 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8001b58: b480 push {r7}
8001b5a: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8001b5c: e7fe b.n 8001b5c <UsageFault_Handler+0x4>
08001b5e <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8001b5e: b480 push {r7}
8001b60: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8001b62: bf00 nop
8001b64: 46bd mov sp, r7
8001b66: f85d 7b04 ldr.w r7, [sp], #4
8001b6a: 4770 bx lr
08001b6c <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8001b6c: b480 push {r7}
8001b6e: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8001b70: bf00 nop
8001b72: 46bd mov sp, r7
8001b74: f85d 7b04 ldr.w r7, [sp], #4
8001b78: 4770 bx lr
08001b7a <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8001b7a: b480 push {r7}
8001b7c: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8001b7e: bf00 nop
8001b80: 46bd mov sp, r7
8001b82: f85d 7b04 ldr.w r7, [sp], #4
8001b86: 4770 bx lr
08001b88 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8001b88: b580 push {r7, lr}
8001b8a: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8001b8c: f000 f8d0 bl 8001d30 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8001b90: bf00 nop
8001b92: bd80 pop {r7, pc}
08001b94 <DMA1_Channel1_IRQHandler>:
/**
* @brief This function handles DMA1 channel1 global interrupt.
*/
void DMA1_Channel1_IRQHandler(void)
{
8001b94: b580 push {r7, lr}
8001b96: af00 add r7, sp, #0
/* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
/* USER CODE END DMA1_Channel1_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_adc2);
8001b98: 4802 ldr r0, [pc, #8] ; (8001ba4 <DMA1_Channel1_IRQHandler+0x10>)
8001b9a: f001 ffb6 bl 8003b0a <HAL_DMA_IRQHandler>
/* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
/* USER CODE END DMA1_Channel1_IRQn 1 */
}
8001b9e: bf00 nop
8001ba0: bd80 pop {r7, pc}
8001ba2: bf00 nop
8001ba4: 2000023c .word 0x2000023c
08001ba8 <DMA1_Channel2_IRQHandler>:
/**
* @brief This function handles DMA1 channel2 global interrupt.
*/
void DMA1_Channel2_IRQHandler(void)
{
8001ba8: b580 push {r7, lr}
8001baa: af00 add r7, sp, #0
/* USER CODE BEGIN DMA1_Channel2_IRQn 0 */
/* USER CODE END DMA1_Channel2_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_adc1);
8001bac: 4802 ldr r0, [pc, #8] ; (8001bb8 <DMA1_Channel2_IRQHandler+0x10>)
8001bae: f001 ffac bl 8003b0a <HAL_DMA_IRQHandler>
/* USER CODE BEGIN DMA1_Channel2_IRQn 1 */
/* USER CODE END DMA1_Channel2_IRQn 1 */
}
8001bb2: bf00 nop
8001bb4: bd80 pop {r7, pc}
8001bb6: bf00 nop
8001bb8: 200001dc .word 0x200001dc
08001bbc <ADC1_2_IRQHandler>:
/**
* @brief This function handles ADC1 and ADC2 global interrupt.
*/
void ADC1_2_IRQHandler(void)
{
8001bbc: b580 push {r7, lr}
8001bbe: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_2_IRQn 0 */
/* USER CODE END ADC1_2_IRQn 0 */
HAL_ADC_IRQHandler(&hadc1);
8001bc0: 4803 ldr r0, [pc, #12] ; (8001bd0 <ADC1_2_IRQHandler+0x14>)
8001bc2: f000 fd55 bl 8002670 <HAL_ADC_IRQHandler>
HAL_ADC_IRQHandler(&hadc2);
8001bc6: 4803 ldr r0, [pc, #12] ; (8001bd4 <ADC1_2_IRQHandler+0x18>)
8001bc8: f000 fd52 bl 8002670 <HAL_ADC_IRQHandler>
/* USER CODE BEGIN ADC1_2_IRQn 1 */
/* USER CODE END ADC1_2_IRQn 1 */
}
8001bcc: bf00 nop
8001bce: bd80 pop {r7, pc}
8001bd0: 20000104 .word 0x20000104
8001bd4: 20000170 .word 0x20000170
08001bd8 <FDCAN1_IT0_IRQHandler>:
/**
* @brief This function handles FDCAN1 interrupt 0.
*/
void FDCAN1_IT0_IRQHandler(void)
{
8001bd8: b580 push {r7, lr}
8001bda: af00 add r7, sp, #0
/* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */
/* USER CODE END FDCAN1_IT0_IRQn 0 */
HAL_FDCAN_IRQHandler(&hfdcan1);
8001bdc: 4802 ldr r0, [pc, #8] ; (8001be8 <FDCAN1_IT0_IRQHandler+0x10>)
8001bde: f002 fcf5 bl 80045cc <HAL_FDCAN_IRQHandler>
/* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */
/* USER CODE END FDCAN1_IT0_IRQn 1 */
}
8001be2: bf00 nop
8001be4: bd80 pop {r7, pc}
8001be6: bf00 nop
8001be8: 2000029c .word 0x2000029c
08001bec <FDCAN1_IT1_IRQHandler>:
/**
* @brief This function handles FDCAN1 interrupt 1.
*/
void FDCAN1_IT1_IRQHandler(void)
{
8001bec: b580 push {r7, lr}
8001bee: af00 add r7, sp, #0
/* USER CODE BEGIN FDCAN1_IT1_IRQn 0 */
/* USER CODE END FDCAN1_IT1_IRQn 0 */
HAL_FDCAN_IRQHandler(&hfdcan1);
8001bf0: 4802 ldr r0, [pc, #8] ; (8001bfc <FDCAN1_IT1_IRQHandler+0x10>)
8001bf2: f002 fceb bl 80045cc <HAL_FDCAN_IRQHandler>
/* USER CODE BEGIN FDCAN1_IT1_IRQn 1 */
/* USER CODE END FDCAN1_IT1_IRQn 1 */
}
8001bf6: bf00 nop
8001bf8: bd80 pop {r7, pc}
8001bfa: bf00 nop
8001bfc: 2000029c .word 0x2000029c
08001c00 <TIM7_IRQHandler>:
/**
* @brief This function handles TIM7 global interrupt.
*/
void TIM7_IRQHandler(void)
{
8001c00: b580 push {r7, lr}
8001c02: af00 add r7, sp, #0
/* USER CODE BEGIN TIM7_IRQn 0 */
/* USER CODE END TIM7_IRQn 0 */
HAL_TIM_IRQHandler(&htim7);
8001c04: 4802 ldr r0, [pc, #8] ; (8001c10 <TIM7_IRQHandler+0x10>)
8001c06: f004 ff47 bl 8006a98 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM7_IRQn 1 */
/* USER CODE END TIM7_IRQn 1 */
}
8001c0a: bf00 nop
8001c0c: bd80 pop {r7, pc}
8001c0e: bf00 nop
8001c10: 200003e4 .word 0x200003e4
08001c14 <SystemInit>:
* @param None
* @retval None
*/
void SystemInit(void)
{
8001c14: b480 push {r7}
8001c16: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
8001c18: 4b06 ldr r3, [pc, #24] ; (8001c34 <SystemInit+0x20>)
8001c1a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8001c1e: 4a05 ldr r2, [pc, #20] ; (8001c34 <SystemInit+0x20>)
8001c20: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
8001c24: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location add offset address ------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
8001c28: bf00 nop
8001c2a: 46bd mov sp, r7
8001c2c: f85d 7b04 ldr.w r7, [sp], #4
8001c30: 4770 bx lr
8001c32: bf00 nop
8001c34: e000ed00 .word 0xe000ed00
08001c38 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
8001c38: 480d ldr r0, [pc, #52] ; (8001c70 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
8001c3a: 4685 mov sp, r0
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8001c3c: 480d ldr r0, [pc, #52] ; (8001c74 <LoopForever+0x6>)
ldr r1, =_edata
8001c3e: 490e ldr r1, [pc, #56] ; (8001c78 <LoopForever+0xa>)
ldr r2, =_sidata
8001c40: 4a0e ldr r2, [pc, #56] ; (8001c7c <LoopForever+0xe>)
movs r3, #0
8001c42: 2300 movs r3, #0
b LoopCopyDataInit
8001c44: e002 b.n 8001c4c <LoopCopyDataInit>
08001c46 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8001c46: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8001c48: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8001c4a: 3304 adds r3, #4
08001c4c <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8001c4c: 18c4 adds r4, r0, r3
cmp r4, r1
8001c4e: 428c cmp r4, r1
bcc CopyDataInit
8001c50: d3f9 bcc.n 8001c46 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8001c52: 4a0b ldr r2, [pc, #44] ; (8001c80 <LoopForever+0x12>)
ldr r4, =_ebss
8001c54: 4c0b ldr r4, [pc, #44] ; (8001c84 <LoopForever+0x16>)
movs r3, #0
8001c56: 2300 movs r3, #0
b LoopFillZerobss
8001c58: e001 b.n 8001c5e <LoopFillZerobss>
08001c5a <FillZerobss>:
FillZerobss:
str r3, [r2]
8001c5a: 6013 str r3, [r2, #0]
adds r2, r2, #4
8001c5c: 3204 adds r2, #4
08001c5e <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8001c5e: 42a2 cmp r2, r4
bcc FillZerobss
8001c60: d3fb bcc.n 8001c5a <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
8001c62: f7ff ffd7 bl 8001c14 <SystemInit>
/* Call static constructors */
bl __libc_init_array
8001c66: f005 ffe7 bl 8007c38 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8001c6a: f7fe ffd3 bl 8000c14 <main>
08001c6e <LoopForever>:
LoopForever:
b LoopForever
8001c6e: e7fe b.n 8001c6e <LoopForever>
ldr r0, =_estack
8001c70: 20008000 .word 0x20008000
ldr r0, =_sdata
8001c74: 20000000 .word 0x20000000
ldr r1, =_edata
8001c78: 20000010 .word 0x20000010
ldr r2, =_sidata
8001c7c: 08007cd8 .word 0x08007cd8
ldr r2, =_sbss
8001c80: 20000010 .word 0x20000010
ldr r4, =_ebss
8001c84: 20000438 .word 0x20000438
08001c88 <COMP1_2_3_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8001c88: e7fe b.n 8001c88 <COMP1_2_3_IRQHandler>
08001c8a <HAL_Init>:
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8001c8a: b580 push {r7, lr}
8001c8c: b082 sub sp, #8
8001c8e: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8001c90: 2300 movs r3, #0
8001c92: 71fb strb r3, [r7, #7]
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8001c94: 2003 movs r0, #3
8001c96: f001 fdd5 bl 8003844 <HAL_NVIC_SetPriorityGrouping>
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
8001c9a: 200f movs r0, #15
8001c9c: f000 f80e bl 8001cbc <HAL_InitTick>
8001ca0: 4603 mov r3, r0
8001ca2: 2b00 cmp r3, #0
8001ca4: d002 beq.n 8001cac <HAL_Init+0x22>
{
status = HAL_ERROR;
8001ca6: 2301 movs r3, #1
8001ca8: 71fb strb r3, [r7, #7]
8001caa: e001 b.n 8001cb0 <HAL_Init+0x26>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
8001cac: f7ff fc58 bl 8001560 <HAL_MspInit>
}
/* Return function status */
return status;
8001cb0: 79fb ldrb r3, [r7, #7]
}
8001cb2: 4618 mov r0, r3
8001cb4: 3708 adds r7, #8
8001cb6: 46bd mov sp, r7
8001cb8: bd80 pop {r7, pc}
...
08001cbc <HAL_InitTick>:
* implementation in user file.
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8001cbc: b580 push {r7, lr}
8001cbe: b084 sub sp, #16
8001cc0: af00 add r7, sp, #0
8001cc2: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8001cc4: 2300 movs r3, #0
8001cc6: 73fb strb r3, [r7, #15]
if (uwTickFreq != 0U)
8001cc8: 4b16 ldr r3, [pc, #88] ; (8001d24 <HAL_InitTick+0x68>)
8001cca: 681b ldr r3, [r3, #0]
8001ccc: 2b00 cmp r3, #0
8001cce: d022 beq.n 8001d16 <HAL_InitTick+0x5a>
{
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
8001cd0: 4b15 ldr r3, [pc, #84] ; (8001d28 <HAL_InitTick+0x6c>)
8001cd2: 681a ldr r2, [r3, #0]
8001cd4: 4b13 ldr r3, [pc, #76] ; (8001d24 <HAL_InitTick+0x68>)
8001cd6: 681b ldr r3, [r3, #0]
8001cd8: f44f 717a mov.w r1, #1000 ; 0x3e8
8001cdc: fbb1 f3f3 udiv r3, r1, r3
8001ce0: fbb2 f3f3 udiv r3, r2, r3
8001ce4: 4618 mov r0, r3
8001ce6: f001 fde0 bl 80038aa <HAL_SYSTICK_Config>
8001cea: 4603 mov r3, r0
8001cec: 2b00 cmp r3, #0
8001cee: d10f bne.n 8001d10 <HAL_InitTick+0x54>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8001cf0: 687b ldr r3, [r7, #4]
8001cf2: 2b0f cmp r3, #15
8001cf4: d809 bhi.n 8001d0a <HAL_InitTick+0x4e>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8001cf6: 2200 movs r2, #0
8001cf8: 6879 ldr r1, [r7, #4]
8001cfa: f04f 30ff mov.w r0, #4294967295
8001cfe: f001 fdac bl 800385a <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8001d02: 4a0a ldr r2, [pc, #40] ; (8001d2c <HAL_InitTick+0x70>)
8001d04: 687b ldr r3, [r7, #4]
8001d06: 6013 str r3, [r2, #0]
8001d08: e007 b.n 8001d1a <HAL_InitTick+0x5e>
}
else
{
status = HAL_ERROR;
8001d0a: 2301 movs r3, #1
8001d0c: 73fb strb r3, [r7, #15]
8001d0e: e004 b.n 8001d1a <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
8001d10: 2301 movs r3, #1
8001d12: 73fb strb r3, [r7, #15]
8001d14: e001 b.n 8001d1a <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
8001d16: 2301 movs r3, #1
8001d18: 73fb strb r3, [r7, #15]
}
/* Return function status */
return status;
8001d1a: 7bfb ldrb r3, [r7, #15]
}
8001d1c: 4618 mov r0, r3
8001d1e: 3710 adds r7, #16
8001d20: 46bd mov sp, r7
8001d22: bd80 pop {r7, pc}
8001d24: 2000000c .word 0x2000000c
8001d28: 20000004 .word 0x20000004
8001d2c: 20000008 .word 0x20000008
08001d30 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8001d30: b480 push {r7}
8001d32: af00 add r7, sp, #0
uwTick += uwTickFreq;
8001d34: 4b05 ldr r3, [pc, #20] ; (8001d4c <HAL_IncTick+0x1c>)
8001d36: 681a ldr r2, [r3, #0]
8001d38: 4b05 ldr r3, [pc, #20] ; (8001d50 <HAL_IncTick+0x20>)
8001d3a: 681b ldr r3, [r3, #0]
8001d3c: 4413 add r3, r2
8001d3e: 4a03 ldr r2, [pc, #12] ; (8001d4c <HAL_IncTick+0x1c>)
8001d40: 6013 str r3, [r2, #0]
}
8001d42: bf00 nop
8001d44: 46bd mov sp, r7
8001d46: f85d 7b04 ldr.w r7, [sp], #4
8001d4a: 4770 bx lr
8001d4c: 20000434 .word 0x20000434
8001d50: 2000000c .word 0x2000000c
08001d54 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8001d54: b480 push {r7}
8001d56: af00 add r7, sp, #0
return uwTick;
8001d58: 4b03 ldr r3, [pc, #12] ; (8001d68 <HAL_GetTick+0x14>)
8001d5a: 681b ldr r3, [r3, #0]
}
8001d5c: 4618 mov r0, r3
8001d5e: 46bd mov sp, r7
8001d60: f85d 7b04 ldr.w r7, [sp], #4
8001d64: 4770 bx lr
8001d66: bf00 nop
8001d68: 20000434 .word 0x20000434
08001d6c <LL_ADC_SetCommonClock>:
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
{
8001d6c: b480 push {r7}
8001d6e: b083 sub sp, #12
8001d70: af00 add r7, sp, #0
8001d72: 6078 str r0, [r7, #4]
8001d74: 6039 str r1, [r7, #0]
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
8001d76: 687b ldr r3, [r7, #4]
8001d78: 689b ldr r3, [r3, #8]
8001d7a: f423 127c bic.w r2, r3, #4128768 ; 0x3f0000
8001d7e: 683b ldr r3, [r7, #0]
8001d80: 431a orrs r2, r3
8001d82: 687b ldr r3, [r7, #4]
8001d84: 609a str r2, [r3, #8]
}
8001d86: bf00 nop
8001d88: 370c adds r7, #12
8001d8a: 46bd mov sp, r7
8001d8c: f85d 7b04 ldr.w r7, [sp], #4
8001d90: 4770 bx lr
08001d92 <LL_ADC_SetCommonPathInternalCh>:
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
{
8001d92: b480 push {r7}
8001d94: b083 sub sp, #12
8001d96: af00 add r7, sp, #0
8001d98: 6078 str r0, [r7, #4]
8001d9a: 6039 str r1, [r7, #0]
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal);
8001d9c: 687b ldr r3, [r7, #4]
8001d9e: 689b ldr r3, [r3, #8]
8001da0: f023 72e0 bic.w r2, r3, #29360128 ; 0x1c00000
8001da4: 683b ldr r3, [r7, #0]
8001da6: 431a orrs r2, r3
8001da8: 687b ldr r3, [r7, #4]
8001daa: 609a str r2, [r3, #8]
}
8001dac: bf00 nop
8001dae: 370c adds r7, #12
8001db0: 46bd mov sp, r7
8001db2: f85d 7b04 ldr.w r7, [sp], #4
8001db6: 4770 bx lr
08001db8 <LL_ADC_GetCommonPathInternalCh>:
* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
*/
__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
{
8001db8: b480 push {r7}
8001dba: b083 sub sp, #12
8001dbc: af00 add r7, sp, #0
8001dbe: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL));
8001dc0: 687b ldr r3, [r7, #4]
8001dc2: 689b ldr r3, [r3, #8]
8001dc4: f003 73e0 and.w r3, r3, #29360128 ; 0x1c00000
}
8001dc8: 4618 mov r0, r3
8001dca: 370c adds r7, #12
8001dcc: 46bd mov sp, r7
8001dce: f85d 7b04 ldr.w r7, [sp], #4
8001dd2: 4770 bx lr
08001dd4 <LL_ADC_SetOffset>:
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
{
8001dd4: b480 push {r7}
8001dd6: b087 sub sp, #28
8001dd8: af00 add r7, sp, #0
8001dda: 60f8 str r0, [r7, #12]
8001ddc: 60b9 str r1, [r7, #8]
8001dde: 607a str r2, [r7, #4]
8001de0: 603b str r3, [r7, #0]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001de2: 68fb ldr r3, [r7, #12]
8001de4: 3360 adds r3, #96 ; 0x60
8001de6: 461a mov r2, r3
8001de8: 68bb ldr r3, [r7, #8]
8001dea: 009b lsls r3, r3, #2
8001dec: 4413 add r3, r2
8001dee: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001df0: 697b ldr r3, [r7, #20]
8001df2: 681a ldr r2, [r3, #0]
8001df4: 4b08 ldr r3, [pc, #32] ; (8001e18 <LL_ADC_SetOffset+0x44>)
8001df6: 4013 ands r3, r2
8001df8: 687a ldr r2, [r7, #4]
8001dfa: f002 41f8 and.w r1, r2, #2080374784 ; 0x7c000000
8001dfe: 683a ldr r2, [r7, #0]
8001e00: 430a orrs r2, r1
8001e02: 4313 orrs r3, r2
8001e04: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000
8001e08: 697b ldr r3, [r7, #20]
8001e0a: 601a str r2, [r3, #0]
ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
}
8001e0c: bf00 nop
8001e0e: 371c adds r7, #28
8001e10: 46bd mov sp, r7
8001e12: f85d 7b04 ldr.w r7, [sp], #4
8001e16: 4770 bx lr
8001e18: 03fff000 .word 0x03fff000
08001e1c <LL_ADC_GetOffsetChannel>:
* (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
{
8001e1c: b480 push {r7}
8001e1e: b085 sub sp, #20
8001e20: af00 add r7, sp, #0
8001e22: 6078 str r0, [r7, #4]
8001e24: 6039 str r1, [r7, #0]
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001e26: 687b ldr r3, [r7, #4]
8001e28: 3360 adds r3, #96 ; 0x60
8001e2a: 461a mov r2, r3
8001e2c: 683b ldr r3, [r7, #0]
8001e2e: 009b lsls r3, r3, #2
8001e30: 4413 add r3, r2
8001e32: 60fb str r3, [r7, #12]
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
8001e34: 68fb ldr r3, [r7, #12]
8001e36: 681b ldr r3, [r3, #0]
8001e38: f003 43f8 and.w r3, r3, #2080374784 ; 0x7c000000
}
8001e3c: 4618 mov r0, r3
8001e3e: 3714 adds r7, #20
8001e40: 46bd mov sp, r7
8001e42: f85d 7b04 ldr.w r7, [sp], #4
8001e46: 4770 bx lr
08001e48 <LL_ADC_SetOffsetState>:
* @arg @ref LL_ADC_OFFSET_DISABLE
* @arg @ref LL_ADC_OFFSET_ENABLE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
{
8001e48: b480 push {r7}
8001e4a: b087 sub sp, #28
8001e4c: af00 add r7, sp, #0
8001e4e: 60f8 str r0, [r7, #12]
8001e50: 60b9 str r1, [r7, #8]
8001e52: 607a str r2, [r7, #4]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001e54: 68fb ldr r3, [r7, #12]
8001e56: 3360 adds r3, #96 ; 0x60
8001e58: 461a mov r2, r3
8001e5a: 68bb ldr r3, [r7, #8]
8001e5c: 009b lsls r3, r3, #2
8001e5e: 4413 add r3, r2
8001e60: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001e62: 697b ldr r3, [r7, #20]
8001e64: 681b ldr r3, [r3, #0]
8001e66: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000
8001e6a: 687b ldr r3, [r7, #4]
8001e6c: 431a orrs r2, r3
8001e6e: 697b ldr r3, [r7, #20]
8001e70: 601a str r2, [r3, #0]
ADC_OFR1_OFFSET1_EN,
OffsetState);
}
8001e72: bf00 nop
8001e74: 371c adds r7, #28
8001e76: 46bd mov sp, r7
8001e78: f85d 7b04 ldr.w r7, [sp], #4
8001e7c: 4770 bx lr
08001e7e <LL_ADC_SetOffsetSign>:
* @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
* @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
{
8001e7e: b480 push {r7}
8001e80: b087 sub sp, #28
8001e82: af00 add r7, sp, #0
8001e84: 60f8 str r0, [r7, #12]
8001e86: 60b9 str r1, [r7, #8]
8001e88: 607a str r2, [r7, #4]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001e8a: 68fb ldr r3, [r7, #12]
8001e8c: 3360 adds r3, #96 ; 0x60
8001e8e: 461a mov r2, r3
8001e90: 68bb ldr r3, [r7, #8]
8001e92: 009b lsls r3, r3, #2
8001e94: 4413 add r3, r2
8001e96: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001e98: 697b ldr r3, [r7, #20]
8001e9a: 681b ldr r3, [r3, #0]
8001e9c: f023 7280 bic.w r2, r3, #16777216 ; 0x1000000
8001ea0: 687b ldr r3, [r7, #4]
8001ea2: 431a orrs r2, r3
8001ea4: 697b ldr r3, [r7, #20]
8001ea6: 601a str r2, [r3, #0]
ADC_OFR1_OFFSETPOS,
OffsetSign);
}
8001ea8: bf00 nop
8001eaa: 371c adds r7, #28
8001eac: 46bd mov sp, r7
8001eae: f85d 7b04 ldr.w r7, [sp], #4
8001eb2: 4770 bx lr
08001eb4 <LL_ADC_SetOffsetSaturation>:
* @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
* @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
{
8001eb4: b480 push {r7}
8001eb6: b087 sub sp, #28
8001eb8: af00 add r7, sp, #0
8001eba: 60f8 str r0, [r7, #12]
8001ebc: 60b9 str r1, [r7, #8]
8001ebe: 607a str r2, [r7, #4]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001ec0: 68fb ldr r3, [r7, #12]
8001ec2: 3360 adds r3, #96 ; 0x60
8001ec4: 461a mov r2, r3
8001ec6: 68bb ldr r3, [r7, #8]
8001ec8: 009b lsls r3, r3, #2
8001eca: 4413 add r3, r2
8001ecc: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001ece: 697b ldr r3, [r7, #20]
8001ed0: 681b ldr r3, [r3, #0]
8001ed2: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000
8001ed6: 687b ldr r3, [r7, #4]
8001ed8: 431a orrs r2, r3
8001eda: 697b ldr r3, [r7, #20]
8001edc: 601a str r2, [r3, #0]
ADC_OFR1_SATEN,
OffsetSaturation);
}
8001ede: bf00 nop
8001ee0: 371c adds r7, #28
8001ee2: 46bd mov sp, r7
8001ee4: f85d 7b04 ldr.w r7, [sp], #4
8001ee8: 4770 bx lr
08001eea <LL_ADC_SetSamplingTimeCommonConfig>:
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
{
8001eea: b480 push {r7}
8001eec: b083 sub sp, #12
8001eee: af00 add r7, sp, #0
8001ef0: 6078 str r0, [r7, #4]
8001ef2: 6039 str r1, [r7, #0]
MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
8001ef4: 687b ldr r3, [r7, #4]
8001ef6: 695b ldr r3, [r3, #20]
8001ef8: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000
8001efc: 683b ldr r3, [r7, #0]
8001efe: 431a orrs r2, r3
8001f00: 687b ldr r3, [r7, #4]
8001f02: 615a str r2, [r3, #20]
}
8001f04: bf00 nop
8001f06: 370c adds r7, #12
8001f08: 46bd mov sp, r7
8001f0a: f85d 7b04 ldr.w r7, [sp], #4
8001f0e: 4770 bx lr
08001f10 <LL_ADC_REG_IsTriggerSourceSWStart>:
* @param ADCx ADC instance
* @retval Value "0" if trigger source external trigger
* Value "1" if trigger source SW start.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
{
8001f10: b480 push {r7}
8001f12: b083 sub sp, #12
8001f14: af00 add r7, sp, #0
8001f16: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
8001f18: 687b ldr r3, [r7, #4]
8001f1a: 68db ldr r3, [r3, #12]
8001f1c: f403 6340 and.w r3, r3, #3072 ; 0xc00
8001f20: 2b00 cmp r3, #0
8001f22: d101 bne.n 8001f28 <LL_ADC_REG_IsTriggerSourceSWStart+0x18>
8001f24: 2301 movs r3, #1
8001f26: e000 b.n 8001f2a <LL_ADC_REG_IsTriggerSourceSWStart+0x1a>
8001f28: 2300 movs r3, #0
}
8001f2a: 4618 mov r0, r3
8001f2c: 370c adds r7, #12
8001f2e: 46bd mov sp, r7
8001f30: f85d 7b04 ldr.w r7, [sp], #4
8001f34: 4770 bx lr
08001f36 <LL_ADC_REG_SetSequencerRanks>:
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
8001f36: b480 push {r7}
8001f38: b087 sub sp, #28
8001f3a: af00 add r7, sp, #0
8001f3c: 60f8 str r0, [r7, #12]
8001f3e: 60b9 str r1, [r7, #8]
8001f40: 607a str r2, [r7, #4]
/* Set bits with content of parameter "Channel" with bits position */
/* in register and register position depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
8001f42: 68fb ldr r3, [r7, #12]
8001f44: 3330 adds r3, #48 ; 0x30
8001f46: 461a mov r2, r3
8001f48: 68bb ldr r3, [r7, #8]
8001f4a: 0a1b lsrs r3, r3, #8
8001f4c: 009b lsls r3, r3, #2
8001f4e: f003 030c and.w r3, r3, #12
8001f52: 4413 add r3, r2
8001f54: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001f56: 697b ldr r3, [r7, #20]
8001f58: 681a ldr r2, [r3, #0]
8001f5a: 68bb ldr r3, [r7, #8]
8001f5c: f003 031f and.w r3, r3, #31
8001f60: 211f movs r1, #31
8001f62: fa01 f303 lsl.w r3, r1, r3
8001f66: 43db mvns r3, r3
8001f68: 401a ands r2, r3
8001f6a: 687b ldr r3, [r7, #4]
8001f6c: 0e9b lsrs r3, r3, #26
8001f6e: f003 011f and.w r1, r3, #31
8001f72: 68bb ldr r3, [r7, #8]
8001f74: f003 031f and.w r3, r3, #31
8001f78: fa01 f303 lsl.w r3, r1, r3
8001f7c: 431a orrs r2, r3
8001f7e: 697b ldr r3, [r7, #20]
8001f80: 601a str r2, [r3, #0]
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
}
8001f82: bf00 nop
8001f84: 371c adds r7, #28
8001f86: 46bd mov sp, r7
8001f88: f85d 7b04 ldr.w r7, [sp], #4
8001f8c: 4770 bx lr
08001f8e <LL_ADC_INJ_IsTriggerSourceSWStart>:
* @param ADCx ADC instance
* @retval Value "0" if trigger source external trigger
* Value "1" if trigger source SW start.
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
{
8001f8e: b480 push {r7}
8001f90: b083 sub sp, #12
8001f92: af00 add r7, sp, #0
8001f94: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
8001f96: 687b ldr r3, [r7, #4]
8001f98: 6cdb ldr r3, [r3, #76] ; 0x4c
8001f9a: f403 73c0 and.w r3, r3, #384 ; 0x180
8001f9e: 2b00 cmp r3, #0
8001fa0: d101 bne.n 8001fa6 <LL_ADC_INJ_IsTriggerSourceSWStart+0x18>
8001fa2: 2301 movs r3, #1
8001fa4: e000 b.n 8001fa8 <LL_ADC_INJ_IsTriggerSourceSWStart+0x1a>
8001fa6: 2300 movs r3, #0
}
8001fa8: 4618 mov r0, r3
8001faa: 370c adds r7, #12
8001fac: 46bd mov sp, r7
8001fae: f85d 7b04 ldr.w r7, [sp], #4
8001fb2: 4770 bx lr
08001fb4 <LL_ADC_SetChannelSamplingTime>:
* can be replaced by 3.5 ADC clock cycles.
* Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
{
8001fb4: b480 push {r7}
8001fb6: b087 sub sp, #28
8001fb8: af00 add r7, sp, #0
8001fba: 60f8 str r0, [r7, #12]
8001fbc: 60b9 str r1, [r7, #8]
8001fbe: 607a str r2, [r7, #4]
/* Set bits with content of parameter "SamplingTime" with bits position */
/* in register and register position depending on parameter "Channel". */
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
8001fc0: 68fb ldr r3, [r7, #12]
8001fc2: 3314 adds r3, #20
8001fc4: 461a mov r2, r3
8001fc6: 68bb ldr r3, [r7, #8]
8001fc8: 0e5b lsrs r3, r3, #25
8001fca: 009b lsls r3, r3, #2
8001fcc: f003 0304 and.w r3, r3, #4
8001fd0: 4413 add r3, r2
8001fd2: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001fd4: 697b ldr r3, [r7, #20]
8001fd6: 681a ldr r2, [r3, #0]
8001fd8: 68bb ldr r3, [r7, #8]
8001fda: 0d1b lsrs r3, r3, #20
8001fdc: f003 031f and.w r3, r3, #31
8001fe0: 2107 movs r1, #7
8001fe2: fa01 f303 lsl.w r3, r1, r3
8001fe6: 43db mvns r3, r3
8001fe8: 401a ands r2, r3
8001fea: 68bb ldr r3, [r7, #8]
8001fec: 0d1b lsrs r3, r3, #20
8001fee: f003 031f and.w r3, r3, #31
8001ff2: 6879 ldr r1, [r7, #4]
8001ff4: fa01 f303 lsl.w r3, r1, r3
8001ff8: 431a orrs r2, r3
8001ffa: 697b ldr r3, [r7, #20]
8001ffc: 601a str r2, [r3, #0]
ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
}
8001ffe: bf00 nop
8002000: 371c adds r7, #28
8002002: 46bd mov sp, r7
8002004: f85d 7b04 ldr.w r7, [sp], #4
8002008: 4770 bx lr
...
0800200c <LL_ADC_SetChannelSingleDiff>:
* @arg @ref LL_ADC_SINGLE_ENDED
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
{
800200c: b480 push {r7}
800200e: b085 sub sp, #20
8002010: af00 add r7, sp, #0
8002012: 60f8 str r0, [r7, #12]
8002014: 60b9 str r1, [r7, #8]
8002016: 607a str r2, [r7, #4]
/* Bits for single or differential mode selection for each channel are set */
/* to 1 only when the differential mode is selected, and to 0 when the */
/* single mode is selected. */
if (SingleDiff == LL_ADC_DIFFERENTIAL_ENDED)
8002018: 687b ldr r3, [r7, #4]
800201a: 4a0f ldr r2, [pc, #60] ; (8002058 <LL_ADC_SetChannelSingleDiff+0x4c>)
800201c: 4293 cmp r3, r2
800201e: d10a bne.n 8002036 <LL_ADC_SetChannelSingleDiff+0x2a>
{
SET_BIT(ADCx->DIFSEL,
8002020: 68fb ldr r3, [r7, #12]
8002022: f8d3 20b0 ldr.w r2, [r3, #176] ; 0xb0
8002026: 68bb ldr r3, [r7, #8]
8002028: f3c3 0312 ubfx r3, r3, #0, #19
800202c: 431a orrs r2, r3
800202e: 68fb ldr r3, [r7, #12]
8002030: f8c3 20b0 str.w r2, [r3, #176] ; 0xb0
else
{
CLEAR_BIT(ADCx->DIFSEL,
Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
}
}
8002034: e00a b.n 800204c <LL_ADC_SetChannelSingleDiff+0x40>
CLEAR_BIT(ADCx->DIFSEL,
8002036: 68fb ldr r3, [r7, #12]
8002038: f8d3 20b0 ldr.w r2, [r3, #176] ; 0xb0
800203c: 68bb ldr r3, [r7, #8]
800203e: f3c3 0312 ubfx r3, r3, #0, #19
8002042: 43db mvns r3, r3
8002044: 401a ands r2, r3
8002046: 68fb ldr r3, [r7, #12]
8002048: f8c3 20b0 str.w r2, [r3, #176] ; 0xb0
}
800204c: bf00 nop
800204e: 3714 adds r7, #20
8002050: 46bd mov sp, r7
8002052: f85d 7b04 ldr.w r7, [sp], #4
8002056: 4770 bx lr
8002058: 407f0000 .word 0x407f0000
0800205c <LL_ADC_GetMultimode>:
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
* @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
*/
__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
{
800205c: b480 push {r7}
800205e: b083 sub sp, #12
8002060: af00 add r7, sp, #0
8002062: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
8002064: 687b ldr r3, [r7, #4]
8002066: 689b ldr r3, [r3, #8]
8002068: f003 031f and.w r3, r3, #31
}
800206c: 4618 mov r0, r3
800206e: 370c adds r7, #12
8002070: 46bd mov sp, r7
8002072: f85d 7b04 ldr.w r7, [sp], #4
8002076: 4770 bx lr
08002078 <LL_ADC_GetMultiDMATransfer>:
* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
*/
__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
{
8002078: b480 push {r7}
800207a: b083 sub sp, #12
800207c: af00 add r7, sp, #0
800207e: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
8002080: 687b ldr r3, [r7, #4]
8002082: 689b ldr r3, [r3, #8]
8002084: f403 4360 and.w r3, r3, #57344 ; 0xe000
}
8002088: 4618 mov r0, r3
800208a: 370c adds r7, #12
800208c: 46bd mov sp, r7
800208e: f85d 7b04 ldr.w r7, [sp], #4
8002092: 4770 bx lr
08002094 <LL_ADC_DisableDeepPowerDown>:
* @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
{
8002094: b480 push {r7}
8002096: b083 sub sp, #12
8002098: af00 add r7, sp, #0
800209a: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
800209c: 687b ldr r3, [r7, #4]
800209e: 689b ldr r3, [r3, #8]
80020a0: f023 4320 bic.w r3, r3, #2684354560 ; 0xa0000000
80020a4: f023 033f bic.w r3, r3, #63 ; 0x3f
80020a8: 687a ldr r2, [r7, #4]
80020aa: 6093 str r3, [r2, #8]
}
80020ac: bf00 nop
80020ae: 370c adds r7, #12
80020b0: 46bd mov sp, r7
80020b2: f85d 7b04 ldr.w r7, [sp], #4
80020b6: 4770 bx lr
080020b8 <LL_ADC_IsDeepPowerDownEnabled>:
* @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
* @param ADCx ADC instance
* @retval 0: deep power down is disabled, 1: deep power down is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
{
80020b8: b480 push {r7}
80020ba: b083 sub sp, #12
80020bc: af00 add r7, sp, #0
80020be: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
80020c0: 687b ldr r3, [r7, #4]
80020c2: 689b ldr r3, [r3, #8]
80020c4: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
80020c8: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
80020cc: d101 bne.n 80020d2 <LL_ADC_IsDeepPowerDownEnabled+0x1a>
80020ce: 2301 movs r3, #1
80020d0: e000 b.n 80020d4 <LL_ADC_IsDeepPowerDownEnabled+0x1c>
80020d2: 2300 movs r3, #0
}
80020d4: 4618 mov r0, r3
80020d6: 370c adds r7, #12
80020d8: 46bd mov sp, r7
80020da: f85d 7b04 ldr.w r7, [sp], #4
80020de: 4770 bx lr
080020e0 <LL_ADC_EnableInternalRegulator>:
* @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
{
80020e0: b480 push {r7}
80020e2: b083 sub sp, #12
80020e4: af00 add r7, sp, #0
80020e6: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
80020e8: 687b ldr r3, [r7, #4]
80020ea: 689b ldr r3, [r3, #8]
80020ec: f023 4310 bic.w r3, r3, #2415919104 ; 0x90000000
80020f0: f023 033f bic.w r3, r3, #63 ; 0x3f
80020f4: f043 5280 orr.w r2, r3, #268435456 ; 0x10000000
80020f8: 687b ldr r3, [r7, #4]
80020fa: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADVREGEN);
}
80020fc: bf00 nop
80020fe: 370c adds r7, #12
8002100: 46bd mov sp, r7
8002102: f85d 7b04 ldr.w r7, [sp], #4
8002106: 4770 bx lr
08002108 <LL_ADC_IsInternalRegulatorEnabled>:
* @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
* @param ADCx ADC instance
* @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
{
8002108: b480 push {r7}
800210a: b083 sub sp, #12
800210c: af00 add r7, sp, #0
800210e: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
8002110: 687b ldr r3, [r7, #4]
8002112: 689b ldr r3, [r3, #8]
8002114: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8002118: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
800211c: d101 bne.n 8002122 <LL_ADC_IsInternalRegulatorEnabled+0x1a>
800211e: 2301 movs r3, #1
8002120: e000 b.n 8002124 <LL_ADC_IsInternalRegulatorEnabled+0x1c>
8002122: 2300 movs r3, #0
}
8002124: 4618 mov r0, r3
8002126: 370c adds r7, #12
8002128: 46bd mov sp, r7
800212a: f85d 7b04 ldr.w r7, [sp], #4
800212e: 4770 bx lr
08002130 <LL_ADC_Enable>:
* @rmtoll CR ADEN LL_ADC_Enable
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
{
8002130: b480 push {r7}
8002132: b083 sub sp, #12
8002134: af00 add r7, sp, #0
8002136: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8002138: 687b ldr r3, [r7, #4]
800213a: 689b ldr r3, [r3, #8]
800213c: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000
8002140: f023 033f bic.w r3, r3, #63 ; 0x3f
8002144: f043 0201 orr.w r2, r3, #1
8002148: 687b ldr r3, [r7, #4]
800214a: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADEN);
}
800214c: bf00 nop
800214e: 370c adds r7, #12
8002150: 46bd mov sp, r7
8002152: f85d 7b04 ldr.w r7, [sp], #4
8002156: 4770 bx lr
08002158 <LL_ADC_IsEnabled>:
* @rmtoll CR ADEN LL_ADC_IsEnabled
* @param ADCx ADC instance
* @retval 0: ADC is disabled, 1: ADC is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
{
8002158: b480 push {r7}
800215a: b083 sub sp, #12
800215c: af00 add r7, sp, #0
800215e: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
8002160: 687b ldr r3, [r7, #4]
8002162: 689b ldr r3, [r3, #8]
8002164: f003 0301 and.w r3, r3, #1
8002168: 2b01 cmp r3, #1
800216a: d101 bne.n 8002170 <LL_ADC_IsEnabled+0x18>
800216c: 2301 movs r3, #1
800216e: e000 b.n 8002172 <LL_ADC_IsEnabled+0x1a>
8002170: 2300 movs r3, #0
}
8002172: 4618 mov r0, r3
8002174: 370c adds r7, #12
8002176: 46bd mov sp, r7
8002178: f85d 7b04 ldr.w r7, [sp], #4
800217c: 4770 bx lr
0800217e <LL_ADC_REG_StartConversion>:
* @rmtoll CR ADSTART LL_ADC_REG_StartConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
{
800217e: b480 push {r7}
8002180: b083 sub sp, #12
8002182: af00 add r7, sp, #0
8002184: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8002186: 687b ldr r3, [r7, #4]
8002188: 689b ldr r3, [r3, #8]
800218a: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000
800218e: f023 033f bic.w r3, r3, #63 ; 0x3f
8002192: f043 0204 orr.w r2, r3, #4
8002196: 687b ldr r3, [r7, #4]
8002198: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADSTART);
}
800219a: bf00 nop
800219c: 370c adds r7, #12
800219e: 46bd mov sp, r7
80021a0: f85d 7b04 ldr.w r7, [sp], #4
80021a4: 4770 bx lr
080021a6 <LL_ADC_REG_IsConversionOngoing>:
* @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group regular.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
{
80021a6: b480 push {r7}
80021a8: b083 sub sp, #12
80021aa: af00 add r7, sp, #0
80021ac: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
80021ae: 687b ldr r3, [r7, #4]
80021b0: 689b ldr r3, [r3, #8]
80021b2: f003 0304 and.w r3, r3, #4
80021b6: 2b04 cmp r3, #4
80021b8: d101 bne.n 80021be <LL_ADC_REG_IsConversionOngoing+0x18>
80021ba: 2301 movs r3, #1
80021bc: e000 b.n 80021c0 <LL_ADC_REG_IsConversionOngoing+0x1a>
80021be: 2300 movs r3, #0
}
80021c0: 4618 mov r0, r3
80021c2: 370c adds r7, #12
80021c4: 46bd mov sp, r7
80021c6: f85d 7b04 ldr.w r7, [sp], #4
80021ca: 4770 bx lr
080021cc <LL_ADC_INJ_IsConversionOngoing>:
* @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group injected.
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
{
80021cc: b480 push {r7}
80021ce: b083 sub sp, #12
80021d0: af00 add r7, sp, #0
80021d2: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
80021d4: 687b ldr r3, [r7, #4]
80021d6: 689b ldr r3, [r3, #8]
80021d8: f003 0308 and.w r3, r3, #8
80021dc: 2b08 cmp r3, #8
80021de: d101 bne.n 80021e4 <LL_ADC_INJ_IsConversionOngoing+0x18>
80021e0: 2301 movs r3, #1
80021e2: e000 b.n 80021e6 <LL_ADC_INJ_IsConversionOngoing+0x1a>
80021e4: 2300 movs r3, #0
}
80021e6: 4618 mov r0, r3
80021e8: 370c adds r7, #12
80021ea: 46bd mov sp, r7
80021ec: f85d 7b04 ldr.w r7, [sp], #4
80021f0: 4770 bx lr
...
080021f4 <HAL_ADC_Init>:
* without disabling the other ADCs.
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
{
80021f4: b590 push {r4, r7, lr}
80021f6: b089 sub sp, #36 ; 0x24
80021f8: af00 add r7, sp, #0
80021fa: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
80021fc: 2300 movs r3, #0
80021fe: 77fb strb r3, [r7, #31]
uint32_t tmpCFGR;
uint32_t tmp_adc_reg_is_conversion_on_going;
__IO uint32_t wait_loop_index = 0UL;
8002200: 2300 movs r3, #0
8002202: 60bb str r3, [r7, #8]
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
/* Check ADC handle */
if (hadc == NULL)
8002204: 687b ldr r3, [r7, #4]
8002206: 2b00 cmp r3, #0
8002208: d101 bne.n 800220e <HAL_ADC_Init+0x1a>
{
return HAL_ERROR;
800220a: 2301 movs r3, #1
800220c: e177 b.n 80024fe <HAL_ADC_Init+0x30a>
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
800220e: 687b ldr r3, [r7, #4]
8002210: 695b ldr r3, [r3, #20]
8002212: 2b00 cmp r3, #0
/* DISCEN and CONT bits cannot be set at the same time */
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
if (hadc->State == HAL_ADC_STATE_RESET)
8002214: 687b ldr r3, [r7, #4]
8002216: 6ddb ldr r3, [r3, #92] ; 0x5c
8002218: 2b00 cmp r3, #0
800221a: d109 bne.n 8002230 <HAL_ADC_Init+0x3c>
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
800221c: 6878 ldr r0, [r7, #4]
800221e: f7ff f9c3 bl 80015a8 <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8002222: 687b ldr r3, [r7, #4]
8002224: 2200 movs r2, #0
8002226: 661a str r2, [r3, #96] ; 0x60
/* Initialize Lock */
hadc->Lock = HAL_UNLOCKED;
8002228: 687b ldr r3, [r7, #4]
800222a: 2200 movs r2, #0
800222c: f883 2058 strb.w r2, [r3, #88] ; 0x58
}
/* - Exit from deep-power-down mode and ADC voltage regulator enable */
if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
8002230: 687b ldr r3, [r7, #4]
8002232: 681b ldr r3, [r3, #0]
8002234: 4618 mov r0, r3
8002236: f7ff ff3f bl 80020b8 <LL_ADC_IsDeepPowerDownEnabled>
800223a: 4603 mov r3, r0
800223c: 2b00 cmp r3, #0
800223e: d004 beq.n 800224a <HAL_ADC_Init+0x56>
{
/* Disable ADC deep power down mode */
LL_ADC_DisableDeepPowerDown(hadc->Instance);
8002240: 687b ldr r3, [r7, #4]
8002242: 681b ldr r3, [r3, #0]
8002244: 4618 mov r0, r3
8002246: f7ff ff25 bl 8002094 <LL_ADC_DisableDeepPowerDown>
/* System was in deep power down mode, calibration must
be relaunched or a previously saved calibration factor
re-applied once the ADC voltage regulator is enabled */
}
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
800224a: 687b ldr r3, [r7, #4]
800224c: 681b ldr r3, [r3, #0]
800224e: 4618 mov r0, r3
8002250: f7ff ff5a bl 8002108 <LL_ADC_IsInternalRegulatorEnabled>
8002254: 4603 mov r3, r0
8002256: 2b00 cmp r3, #0
8002258: d115 bne.n 8002286 <HAL_ADC_Init+0x92>
{
/* Enable ADC internal voltage regulator */
LL_ADC_EnableInternalRegulator(hadc->Instance);
800225a: 687b ldr r3, [r7, #4]
800225c: 681b ldr r3, [r3, #0]
800225e: 4618 mov r0, r3
8002260: f7ff ff3e bl 80020e0 <LL_ADC_EnableInternalRegulator>
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
8002264: 4b9c ldr r3, [pc, #624] ; (80024d8 <HAL_ADC_Init+0x2e4>)
8002266: 681b ldr r3, [r3, #0]
8002268: 099b lsrs r3, r3, #6
800226a: 4a9c ldr r2, [pc, #624] ; (80024dc <HAL_ADC_Init+0x2e8>)
800226c: fba2 2303 umull r2, r3, r2, r3
8002270: 099b lsrs r3, r3, #6
8002272: 3301 adds r3, #1
8002274: 005b lsls r3, r3, #1
8002276: 60bb str r3, [r7, #8]
while (wait_loop_index != 0UL)
8002278: e002 b.n 8002280 <HAL_ADC_Init+0x8c>
{
wait_loop_index--;
800227a: 68bb ldr r3, [r7, #8]
800227c: 3b01 subs r3, #1
800227e: 60bb str r3, [r7, #8]
while (wait_loop_index != 0UL)
8002280: 68bb ldr r3, [r7, #8]
8002282: 2b00 cmp r3, #0
8002284: d1f9 bne.n 800227a <HAL_ADC_Init+0x86>
}
/* Verification that ADC voltage regulator is correctly enabled, whether */
/* or not ADC is coming from state reset (if any potential problem of */
/* clocking, voltage regulator would not be enabled). */
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
8002286: 687b ldr r3, [r7, #4]
8002288: 681b ldr r3, [r3, #0]
800228a: 4618 mov r0, r3
800228c: f7ff ff3c bl 8002108 <LL_ADC_IsInternalRegulatorEnabled>
8002290: 4603 mov r3, r0
8002292: 2b00 cmp r3, #0
8002294: d10d bne.n 80022b2 <HAL_ADC_Init+0xbe>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002296: 687b ldr r3, [r7, #4]
8002298: 6ddb ldr r3, [r3, #92] ; 0x5c
800229a: f043 0210 orr.w r2, r3, #16
800229e: 687b ldr r3, [r7, #4]
80022a0: 65da str r2, [r3, #92] ; 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80022a2: 687b ldr r3, [r7, #4]
80022a4: 6e1b ldr r3, [r3, #96] ; 0x60
80022a6: f043 0201 orr.w r2, r3, #1
80022aa: 687b ldr r3, [r7, #4]
80022ac: 661a str r2, [r3, #96] ; 0x60
tmp_hal_status = HAL_ERROR;
80022ae: 2301 movs r3, #1
80022b0: 77fb strb r3, [r7, #31]
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed and if there is no conversion on going on regular */
/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
/* called to update a parameter on the fly). */
tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
80022b2: 687b ldr r3, [r7, #4]
80022b4: 681b ldr r3, [r3, #0]
80022b6: 4618 mov r0, r3
80022b8: f7ff ff75 bl 80021a6 <LL_ADC_REG_IsConversionOngoing>
80022bc: 6178 str r0, [r7, #20]
if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
80022be: 687b ldr r3, [r7, #4]
80022c0: 6ddb ldr r3, [r3, #92] ; 0x5c
80022c2: f003 0310 and.w r3, r3, #16
80022c6: 2b00 cmp r3, #0
80022c8: f040 8110 bne.w 80024ec <HAL_ADC_Init+0x2f8>
&& (tmp_adc_reg_is_conversion_on_going == 0UL)
80022cc: 697b ldr r3, [r7, #20]
80022ce: 2b00 cmp r3, #0
80022d0: f040 810c bne.w 80024ec <HAL_ADC_Init+0x2f8>
)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
80022d4: 687b ldr r3, [r7, #4]
80022d6: 6ddb ldr r3, [r3, #92] ; 0x5c
80022d8: f423 7381 bic.w r3, r3, #258 ; 0x102
80022dc: f043 0202 orr.w r2, r3, #2
80022e0: 687b ldr r3, [r7, #4]
80022e2: 65da str r2, [r3, #92] ; 0x5c
/* Configuration of common ADC parameters */
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - clock configuration */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
80022e4: 687b ldr r3, [r7, #4]
80022e6: 681b ldr r3, [r3, #0]
80022e8: 4618 mov r0, r3
80022ea: f7ff ff35 bl 8002158 <LL_ADC_IsEnabled>
80022ee: 4603 mov r3, r0
80022f0: 2b00 cmp r3, #0
80022f2: d111 bne.n 8002318 <HAL_ADC_Init+0x124>
{
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
80022f4: f04f 40a0 mov.w r0, #1342177280 ; 0x50000000
80022f8: f7ff ff2e bl 8002158 <LL_ADC_IsEnabled>
80022fc: 4604 mov r4, r0
80022fe: 4878 ldr r0, [pc, #480] ; (80024e0 <HAL_ADC_Init+0x2ec>)
8002300: f7ff ff2a bl 8002158 <LL_ADC_IsEnabled>
8002304: 4603 mov r3, r0
8002306: 4323 orrs r3, r4
8002308: 2b00 cmp r3, #0
800230a: d105 bne.n 8002318 <HAL_ADC_Init+0x124>
/* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
/* HAL_ADCEx_MultiModeConfigChannel() ) */
/* - internal measurement paths: Vbat, temperature sensor, Vref */
/* (set into HAL_ADC_ConfigChannel() or */
/* HAL_ADCEx_InjectedConfigChannel() ) */
LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
800230c: 687b ldr r3, [r7, #4]
800230e: 685b ldr r3, [r3, #4]
8002310: 4619 mov r1, r3
8002312: 4874 ldr r0, [pc, #464] ; (80024e4 <HAL_ADC_Init+0x2f0>)
8002314: f7ff fd2a bl 8001d6c <LL_ADC_SetCommonClock>
/* - external trigger polarity Init.ExternalTrigConvEdge */
/* - continuous conversion mode Init.ContinuousConvMode */
/* - overrun Init.Overrun */
/* - discontinuous mode Init.DiscontinuousConvMode */
/* - discontinuous mode channel count Init.NbrOfDiscConversion */
tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8002318: 687b ldr r3, [r7, #4]
800231a: 7f5b ldrb r3, [r3, #29]
800231c: 035a lsls r2, r3, #13
hadc->Init.Overrun |
800231e: 687b ldr r3, [r7, #4]
8002320: 6bdb ldr r3, [r3, #60] ; 0x3c
tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8002322: 431a orrs r2, r3
hadc->Init.DataAlign |
8002324: 687b ldr r3, [r7, #4]
8002326: 68db ldr r3, [r3, #12]
hadc->Init.Overrun |
8002328: 431a orrs r2, r3
hadc->Init.Resolution |
800232a: 687b ldr r3, [r7, #4]
800232c: 689b ldr r3, [r3, #8]
hadc->Init.DataAlign |
800232e: 431a orrs r2, r3
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
8002330: 687b ldr r3, [r7, #4]
8002332: f893 3024 ldrb.w r3, [r3, #36] ; 0x24
8002336: 041b lsls r3, r3, #16
tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8002338: 4313 orrs r3, r2
800233a: 61bb str r3, [r7, #24]
if (hadc->Init.DiscontinuousConvMode == ENABLE)
800233c: 687b ldr r3, [r7, #4]
800233e: f893 3024 ldrb.w r3, [r3, #36] ; 0x24
8002342: 2b01 cmp r3, #1
8002344: d106 bne.n 8002354 <HAL_ADC_Init+0x160>
{
tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
8002346: 687b ldr r3, [r7, #4]
8002348: 6a9b ldr r3, [r3, #40] ; 0x28
800234a: 3b01 subs r3, #1
800234c: 045b lsls r3, r3, #17
800234e: 69ba ldr r2, [r7, #24]
8002350: 4313 orrs r3, r2
8002352: 61bb str r3, [r7, #24]
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
8002354: 687b ldr r3, [r7, #4]
8002356: 6adb ldr r3, [r3, #44] ; 0x2c
8002358: 2b00 cmp r3, #0
800235a: d009 beq.n 8002370 <HAL_ADC_Init+0x17c>
{
tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
800235c: 687b ldr r3, [r7, #4]
800235e: 6adb ldr r3, [r3, #44] ; 0x2c
8002360: f403 7278 and.w r2, r3, #992 ; 0x3e0
| hadc->Init.ExternalTrigConvEdge
8002364: 687b ldr r3, [r7, #4]
8002366: 6b1b ldr r3, [r3, #48] ; 0x30
8002368: 4313 orrs r3, r2
tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
800236a: 69ba ldr r2, [r7, #24]
800236c: 4313 orrs r3, r2
800236e: 61bb str r3, [r7, #24]
);
}
/* Update Configuration Register CFGR */
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
8002370: 687b ldr r3, [r7, #4]
8002372: 681b ldr r3, [r3, #0]
8002374: 68da ldr r2, [r3, #12]
8002376: 4b5c ldr r3, [pc, #368] ; (80024e8 <HAL_ADC_Init+0x2f4>)
8002378: 4013 ands r3, r2
800237a: 687a ldr r2, [r7, #4]
800237c: 6812 ldr r2, [r2, #0]
800237e: 69b9 ldr r1, [r7, #24]
8002380: 430b orrs r3, r1
8002382: 60d3 str r3, [r2, #12]
/* Configuration of sampling mode */
MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode);
8002384: 687b ldr r3, [r7, #4]
8002386: 681b ldr r3, [r3, #0]
8002388: 691b ldr r3, [r3, #16]
800238a: f023 6140 bic.w r1, r3, #201326592 ; 0xc000000
800238e: 687b ldr r3, [r7, #4]
8002390: 6b5a ldr r2, [r3, #52] ; 0x34
8002392: 687b ldr r3, [r7, #4]
8002394: 681b ldr r3, [r3, #0]
8002396: 430a orrs r2, r1
8002398: 611a str r2, [r3, #16]
/* conversion on going on regular and injected groups: */
/* - Gain Compensation Init.GainCompensation */
/* - DMA continuous request Init.DMAContinuousRequests */
/* - LowPowerAutoWait feature Init.LowPowerAutoWait */
/* - Oversampling parameters Init.Oversampling */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
800239a: 687b ldr r3, [r7, #4]
800239c: 681b ldr r3, [r3, #0]
800239e: 4618 mov r0, r3
80023a0: f7ff ff01 bl 80021a6 <LL_ADC_REG_IsConversionOngoing>
80023a4: 6138 str r0, [r7, #16]
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
80023a6: 687b ldr r3, [r7, #4]
80023a8: 681b ldr r3, [r3, #0]
80023aa: 4618 mov r0, r3
80023ac: f7ff ff0e bl 80021cc <LL_ADC_INJ_IsConversionOngoing>
80023b0: 60f8 str r0, [r7, #12]
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
80023b2: 693b ldr r3, [r7, #16]
80023b4: 2b00 cmp r3, #0
80023b6: d16d bne.n 8002494 <HAL_ADC_Init+0x2a0>
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
80023b8: 68fb ldr r3, [r7, #12]
80023ba: 2b00 cmp r3, #0
80023bc: d16a bne.n 8002494 <HAL_ADC_Init+0x2a0>
)
{
tmpCFGR = (ADC_CFGR_DFSDM(hadc) |
ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
80023be: 687b ldr r3, [r7, #4]
80023c0: 7f1b ldrb r3, [r3, #28]
tmpCFGR = (ADC_CFGR_DFSDM(hadc) |
80023c2: 039a lsls r2, r3, #14
ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
80023c4: 687b ldr r3, [r7, #4]
80023c6: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
80023ca: 005b lsls r3, r3, #1
tmpCFGR = (ADC_CFGR_DFSDM(hadc) |
80023cc: 4313 orrs r3, r2
80023ce: 61bb str r3, [r7, #24]
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
80023d0: 687b ldr r3, [r7, #4]
80023d2: 681b ldr r3, [r3, #0]
80023d4: 68db ldr r3, [r3, #12]
80023d6: f423 4380 bic.w r3, r3, #16384 ; 0x4000
80023da: f023 0302 bic.w r3, r3, #2
80023de: 687a ldr r2, [r7, #4]
80023e0: 6812 ldr r2, [r2, #0]
80023e2: 69b9 ldr r1, [r7, #24]
80023e4: 430b orrs r3, r1
80023e6: 60d3 str r3, [r2, #12]
if (hadc->Init.GainCompensation != 0UL)
80023e8: 687b ldr r3, [r7, #4]
80023ea: 691b ldr r3, [r3, #16]
80023ec: 2b00 cmp r3, #0
80023ee: d017 beq.n 8002420 <HAL_ADC_Init+0x22c>
{
SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
80023f0: 687b ldr r3, [r7, #4]
80023f2: 681b ldr r3, [r3, #0]
80023f4: 691a ldr r2, [r3, #16]
80023f6: 687b ldr r3, [r7, #4]
80023f8: 681b ldr r3, [r3, #0]
80023fa: f442 3280 orr.w r2, r2, #65536 ; 0x10000
80023fe: 611a str r2, [r3, #16]
MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation);
8002400: 687b ldr r3, [r7, #4]
8002402: 681b ldr r3, [r3, #0]
8002404: f8d3 30c0 ldr.w r3, [r3, #192] ; 0xc0
8002408: f423 537f bic.w r3, r3, #16320 ; 0x3fc0
800240c: f023 033f bic.w r3, r3, #63 ; 0x3f
8002410: 687a ldr r2, [r7, #4]
8002412: 6911 ldr r1, [r2, #16]
8002414: 687a ldr r2, [r7, #4]
8002416: 6812 ldr r2, [r2, #0]
8002418: 430b orrs r3, r1
800241a: f8c2 30c0 str.w r3, [r2, #192] ; 0xc0
800241e: e013 b.n 8002448 <HAL_ADC_Init+0x254>
}
else
{
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
8002420: 687b ldr r3, [r7, #4]
8002422: 681b ldr r3, [r3, #0]
8002424: 691a ldr r2, [r3, #16]
8002426: 687b ldr r3, [r7, #4]
8002428: 681b ldr r3, [r3, #0]
800242a: f422 3280 bic.w r2, r2, #65536 ; 0x10000
800242e: 611a str r2, [r3, #16]
MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL);
8002430: 687b ldr r3, [r7, #4]
8002432: 681b ldr r3, [r3, #0]
8002434: f8d3 30c0 ldr.w r3, [r3, #192] ; 0xc0
8002438: 687a ldr r2, [r7, #4]
800243a: 6812 ldr r2, [r2, #0]
800243c: f423 537f bic.w r3, r3, #16320 ; 0x3fc0
8002440: f023 033f bic.w r3, r3, #63 ; 0x3f
8002444: f8c2 30c0 str.w r3, [r2, #192] ; 0xc0
}
if (hadc->Init.OversamplingMode == ENABLE)
8002448: 687b ldr r3, [r7, #4]
800244a: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
800244e: 2b01 cmp r3, #1
8002450: d118 bne.n 8002484 <HAL_ADC_Init+0x290>
/* Configuration of Oversampler: */
/* - Oversampling Ratio */
/* - Right bit shift */
/* - Triggered mode */
/* - Oversampling mode (continued/resumed) */
MODIFY_REG(hadc->Instance->CFGR2,
8002452: 687b ldr r3, [r7, #4]
8002454: 681b ldr r3, [r3, #0]
8002456: 691b ldr r3, [r3, #16]
8002458: f423 63ff bic.w r3, r3, #2040 ; 0x7f8
800245c: f023 0304 bic.w r3, r3, #4
8002460: 687a ldr r2, [r7, #4]
8002462: 6c51 ldr r1, [r2, #68] ; 0x44
8002464: 687a ldr r2, [r7, #4]
8002466: 6c92 ldr r2, [r2, #72] ; 0x48
8002468: 4311 orrs r1, r2
800246a: 687a ldr r2, [r7, #4]
800246c: 6cd2 ldr r2, [r2, #76] ; 0x4c
800246e: 4311 orrs r1, r2
8002470: 687a ldr r2, [r7, #4]
8002472: 6d12 ldr r2, [r2, #80] ; 0x50
8002474: 430a orrs r2, r1
8002476: 431a orrs r2, r3
8002478: 687b ldr r3, [r7, #4]
800247a: 681b ldr r3, [r3, #0]
800247c: f042 0201 orr.w r2, r2, #1
8002480: 611a str r2, [r3, #16]
8002482: e007 b.n 8002494 <HAL_ADC_Init+0x2a0>
);
}
else
{
/* Disable ADC oversampling scope on ADC group regular */
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
8002484: 687b ldr r3, [r7, #4]
8002486: 681b ldr r3, [r3, #0]
8002488: 691a ldr r2, [r3, #16]
800248a: 687b ldr r3, [r7, #4]
800248c: 681b ldr r3, [r3, #0]
800248e: f022 0201 bic.w r2, r2, #1
8002492: 611a str r2, [r3, #16]
/* Note: Scan mode is not present by hardware on this device, but */
/* emulated by software for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion". */
if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
8002494: 687b ldr r3, [r7, #4]
8002496: 695b ldr r3, [r3, #20]
8002498: 2b01 cmp r3, #1
800249a: d10c bne.n 80024b6 <HAL_ADC_Init+0x2c2>
{
/* Set number of ranks in regular group sequencer */
MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
800249c: 687b ldr r3, [r7, #4]
800249e: 681b ldr r3, [r3, #0]
80024a0: 6b1b ldr r3, [r3, #48] ; 0x30
80024a2: f023 010f bic.w r1, r3, #15
80024a6: 687b ldr r3, [r7, #4]
80024a8: 6a1b ldr r3, [r3, #32]
80024aa: 1e5a subs r2, r3, #1
80024ac: 687b ldr r3, [r7, #4]
80024ae: 681b ldr r3, [r3, #0]
80024b0: 430a orrs r2, r1
80024b2: 631a str r2, [r3, #48] ; 0x30
80024b4: e007 b.n 80024c6 <HAL_ADC_Init+0x2d2>
}
else
{
CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
80024b6: 687b ldr r3, [r7, #4]
80024b8: 681b ldr r3, [r3, #0]
80024ba: 6b1a ldr r2, [r3, #48] ; 0x30
80024bc: 687b ldr r3, [r7, #4]
80024be: 681b ldr r3, [r3, #0]
80024c0: f022 020f bic.w r2, r2, #15
80024c4: 631a str r2, [r3, #48] ; 0x30
}
/* Initialize the ADC state */
/* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
80024c6: 687b ldr r3, [r7, #4]
80024c8: 6ddb ldr r3, [r3, #92] ; 0x5c
80024ca: f023 0303 bic.w r3, r3, #3
80024ce: f043 0201 orr.w r2, r3, #1
80024d2: 687b ldr r3, [r7, #4]
80024d4: 65da str r2, [r3, #92] ; 0x5c
80024d6: e011 b.n 80024fc <HAL_ADC_Init+0x308>
80024d8: 20000004 .word 0x20000004
80024dc: 053e2d63 .word 0x053e2d63
80024e0: 50000100 .word 0x50000100
80024e4: 50000300 .word 0x50000300
80024e8: fff04007 .word 0xfff04007
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80024ec: 687b ldr r3, [r7, #4]
80024ee: 6ddb ldr r3, [r3, #92] ; 0x5c
80024f0: f043 0210 orr.w r2, r3, #16
80024f4: 687b ldr r3, [r7, #4]
80024f6: 65da str r2, [r3, #92] ; 0x5c
tmp_hal_status = HAL_ERROR;
80024f8: 2301 movs r3, #1
80024fa: 77fb strb r3, [r7, #31]
}
/* Return function status */
return tmp_hal_status;
80024fc: 7ffb ldrb r3, [r7, #31]
}
80024fe: 4618 mov r0, r3
8002500: 3724 adds r7, #36 ; 0x24
8002502: 46bd mov sp, r7
8002504: bd90 pop {r4, r7, pc}
8002506: bf00 nop
08002508 <HAL_ADC_Start_DMA>:
* @param pData Destination Buffer address.
* @param Length Number of data to be transferred from ADC peripheral to memory
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
{
8002508: b580 push {r7, lr}
800250a: b086 sub sp, #24
800250c: af00 add r7, sp, #0
800250e: 60f8 str r0, [r7, #12]
8002510: 60b9 str r1, [r7, #8]
8002512: 607a str r2, [r7, #4]
HAL_StatusTypeDef tmp_hal_status;
#if defined(ADC_MULTIMODE_SUPPORT)
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
8002514: 4851 ldr r0, [pc, #324] ; (800265c <HAL_ADC_Start_DMA+0x154>)
8002516: f7ff fda1 bl 800205c <LL_ADC_GetMultimode>
800251a: 6138 str r0, [r7, #16]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Perform ADC enable and conversion start if no conversion is on going */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
800251c: 68fb ldr r3, [r7, #12]
800251e: 681b ldr r3, [r3, #0]
8002520: 4618 mov r0, r3
8002522: f7ff fe40 bl 80021a6 <LL_ADC_REG_IsConversionOngoing>
8002526: 4603 mov r3, r0
8002528: 2b00 cmp r3, #0
800252a: f040 808f bne.w 800264c <HAL_ADC_Start_DMA+0x144>
{
/* Process locked */
__HAL_LOCK(hadc);
800252e: 68fb ldr r3, [r7, #12]
8002530: f893 3058 ldrb.w r3, [r3, #88] ; 0x58
8002534: 2b01 cmp r3, #1
8002536: d101 bne.n 800253c <HAL_ADC_Start_DMA+0x34>
8002538: 2302 movs r3, #2
800253a: e08a b.n 8002652 <HAL_ADC_Start_DMA+0x14a>
800253c: 68fb ldr r3, [r7, #12]
800253e: 2201 movs r2, #1
8002540: f883 2058 strb.w r2, [r3, #88] ; 0x58
#if defined(ADC_MULTIMODE_SUPPORT)
/* Ensure that multimode regular conversions are not enabled. */
/* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */
if ((ADC_IS_INDEPENDENT(hadc) != RESET)
8002544: 693b ldr r3, [r7, #16]
8002546: 2b00 cmp r3, #0
8002548: d005 beq.n 8002556 <HAL_ADC_Start_DMA+0x4e>
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
800254a: 693b ldr r3, [r7, #16]
800254c: 2b05 cmp r3, #5
800254e: d002 beq.n 8002556 <HAL_ADC_Start_DMA+0x4e>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
8002550: 693b ldr r3, [r7, #16]
8002552: 2b09 cmp r3, #9
8002554: d173 bne.n 800263e <HAL_ADC_Start_DMA+0x136>
)
#endif /* ADC_MULTIMODE_SUPPORT */
{
/* Enable the ADC peripheral */
tmp_hal_status = ADC_Enable(hadc);
8002556: 68f8 ldr r0, [r7, #12]
8002558: f000 feb2 bl 80032c0 <ADC_Enable>
800255c: 4603 mov r3, r0
800255e: 75fb strb r3, [r7, #23]
/* Start conversion if ADC is effectively enabled */
if (tmp_hal_status == HAL_OK)
8002560: 7dfb ldrb r3, [r7, #23]
8002562: 2b00 cmp r3, #0
8002564: d166 bne.n 8002634 <HAL_ADC_Start_DMA+0x12c>
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular operation */
ADC_STATE_CLR_SET(hadc->State,
8002566: 68fb ldr r3, [r7, #12]
8002568: 6ddb ldr r3, [r3, #92] ; 0x5c
800256a: f423 6370 bic.w r3, r3, #3840 ; 0xf00
800256e: f023 0301 bic.w r3, r3, #1
8002572: f443 7280 orr.w r2, r3, #256 ; 0x100
8002576: 68fb ldr r3, [r7, #12]
8002578: 65da str r2, [r3, #92] ; 0x5c
#if defined(ADC_MULTIMODE_SUPPORT)
/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
- if ADC instance is master or if multimode feature is not available
- if multimode setting is disabled (ADC instance slave in independent mode) */
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
800257a: 68fb ldr r3, [r7, #12]
800257c: 681b ldr r3, [r3, #0]
800257e: 4a38 ldr r2, [pc, #224] ; (8002660 <HAL_ADC_Start_DMA+0x158>)
8002580: 4293 cmp r3, r2
8002582: d002 beq.n 800258a <HAL_ADC_Start_DMA+0x82>
8002584: 68fb ldr r3, [r7, #12]
8002586: 681b ldr r3, [r3, #0]
8002588: e001 b.n 800258e <HAL_ADC_Start_DMA+0x86>
800258a: f04f 43a0 mov.w r3, #1342177280 ; 0x50000000
800258e: 68fa ldr r2, [r7, #12]
8002590: 6812 ldr r2, [r2, #0]
8002592: 4293 cmp r3, r2
8002594: d002 beq.n 800259c <HAL_ADC_Start_DMA+0x94>
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
8002596: 693b ldr r3, [r7, #16]
8002598: 2b00 cmp r3, #0
800259a: d105 bne.n 80025a8 <HAL_ADC_Start_DMA+0xa0>
)
{
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
800259c: 68fb ldr r3, [r7, #12]
800259e: 6ddb ldr r3, [r3, #92] ; 0x5c
80025a0: f423 1280 bic.w r2, r3, #1048576 ; 0x100000
80025a4: 68fb ldr r3, [r7, #12]
80025a6: 65da str r2, [r3, #92] ; 0x5c
}
#endif
/* Check if a conversion is on going on ADC group injected */
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
80025a8: 68fb ldr r3, [r7, #12]
80025aa: 6ddb ldr r3, [r3, #92] ; 0x5c
80025ac: f403 5380 and.w r3, r3, #4096 ; 0x1000
80025b0: 2b00 cmp r3, #0
80025b2: d006 beq.n 80025c2 <HAL_ADC_Start_DMA+0xba>
{
/* Reset ADC error code fields related to regular conversions only */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
80025b4: 68fb ldr r3, [r7, #12]
80025b6: 6e1b ldr r3, [r3, #96] ; 0x60
80025b8: f023 0206 bic.w r2, r3, #6
80025bc: 68fb ldr r3, [r7, #12]
80025be: 661a str r2, [r3, #96] ; 0x60
80025c0: e002 b.n 80025c8 <HAL_ADC_Start_DMA+0xc0>
}
else
{
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
80025c2: 68fb ldr r3, [r7, #12]
80025c4: 2200 movs r2, #0
80025c6: 661a str r2, [r3, #96] ; 0x60
}
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
80025c8: 68fb ldr r3, [r7, #12]
80025ca: 6d5b ldr r3, [r3, #84] ; 0x54
80025cc: 4a25 ldr r2, [pc, #148] ; (8002664 <HAL_ADC_Start_DMA+0x15c>)
80025ce: 62da str r2, [r3, #44] ; 0x2c
/* Set the DMA half transfer complete callback */
hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
80025d0: 68fb ldr r3, [r7, #12]
80025d2: 6d5b ldr r3, [r3, #84] ; 0x54
80025d4: 4a24 ldr r2, [pc, #144] ; (8002668 <HAL_ADC_Start_DMA+0x160>)
80025d6: 631a str r2, [r3, #48] ; 0x30
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
80025d8: 68fb ldr r3, [r7, #12]
80025da: 6d5b ldr r3, [r3, #84] ; 0x54
80025dc: 4a23 ldr r2, [pc, #140] ; (800266c <HAL_ADC_Start_DMA+0x164>)
80025de: 635a str r2, [r3, #52] ; 0x34
/* ADC start (in case of SW start): */
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC */
/* operations) */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
80025e0: 68fb ldr r3, [r7, #12]
80025e2: 681b ldr r3, [r3, #0]
80025e4: 221c movs r2, #28
80025e6: 601a str r2, [r3, #0]
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
80025e8: 68fb ldr r3, [r7, #12]
80025ea: 2200 movs r2, #0
80025ec: f883 2058 strb.w r2, [r3, #88] ; 0x58
/* With DMA, overrun event is always considered as an error even if
hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
ADC_IT_OVR is enabled. */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
80025f0: 68fb ldr r3, [r7, #12]
80025f2: 681b ldr r3, [r3, #0]
80025f4: 685a ldr r2, [r3, #4]
80025f6: 68fb ldr r3, [r7, #12]
80025f8: 681b ldr r3, [r3, #0]
80025fa: f042 0210 orr.w r2, r2, #16
80025fe: 605a str r2, [r3, #4]
/* Enable ADC DMA mode */
SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
8002600: 68fb ldr r3, [r7, #12]
8002602: 681b ldr r3, [r3, #0]
8002604: 68da ldr r2, [r3, #12]
8002606: 68fb ldr r3, [r7, #12]
8002608: 681b ldr r3, [r3, #0]
800260a: f042 0201 orr.w r2, r2, #1
800260e: 60da str r2, [r3, #12]
/* Start the DMA channel */
tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
8002610: 68fb ldr r3, [r7, #12]
8002612: 6d58 ldr r0, [r3, #84] ; 0x54
8002614: 68fb ldr r3, [r7, #12]
8002616: 681b ldr r3, [r3, #0]
8002618: 3340 adds r3, #64 ; 0x40
800261a: 4619 mov r1, r3
800261c: 68ba ldr r2, [r7, #8]
800261e: 687b ldr r3, [r7, #4]
8002620: f001 f9f8 bl 8003a14 <HAL_DMA_Start_IT>
8002624: 4603 mov r3, r0
8002626: 75fb strb r3, [r7, #23]
/* Enable conversion of regular group. */
/* If software start has been selected, conversion starts immediately. */
/* If external trigger has been selected, conversion will start at next */
/* trigger event. */
/* Start ADC group regular conversion */
LL_ADC_REG_StartConversion(hadc->Instance);
8002628: 68fb ldr r3, [r7, #12]
800262a: 681b ldr r3, [r3, #0]
800262c: 4618 mov r0, r3
800262e: f7ff fda6 bl 800217e <LL_ADC_REG_StartConversion>
if (tmp_hal_status == HAL_OK)
8002632: e00d b.n 8002650 <HAL_ADC_Start_DMA+0x148>
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hadc);
8002634: 68fb ldr r3, [r7, #12]
8002636: 2200 movs r2, #0
8002638: f883 2058 strb.w r2, [r3, #88] ; 0x58
if (tmp_hal_status == HAL_OK)
800263c: e008 b.n 8002650 <HAL_ADC_Start_DMA+0x148>
}
#if defined(ADC_MULTIMODE_SUPPORT)
else
{
tmp_hal_status = HAL_ERROR;
800263e: 2301 movs r3, #1
8002640: 75fb strb r3, [r7, #23]
/* Process unlocked */
__HAL_UNLOCK(hadc);
8002642: 68fb ldr r3, [r7, #12]
8002644: 2200 movs r2, #0
8002646: f883 2058 strb.w r2, [r3, #88] ; 0x58
800264a: e001 b.n 8002650 <HAL_ADC_Start_DMA+0x148>
}
#endif
}
else
{
tmp_hal_status = HAL_BUSY;
800264c: 2302 movs r3, #2
800264e: 75fb strb r3, [r7, #23]
}
/* Return function status */
return tmp_hal_status;
8002650: 7dfb ldrb r3, [r7, #23]
}
8002652: 4618 mov r0, r3
8002654: 3718 adds r7, #24
8002656: 46bd mov sp, r7
8002658: bd80 pop {r7, pc}
800265a: bf00 nop
800265c: 50000300 .word 0x50000300
8002660: 50000100 .word 0x50000100
8002664: 08003385 .word 0x08003385
8002668: 0800345d .word 0x0800345d
800266c: 08003479 .word 0x08003479
08002670 <HAL_ADC_IRQHandler>:
* @brief Handle ADC interrupt request.
* @param hadc ADC handle
* @retval None
*/
void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
{
8002670: b580 push {r7, lr}
8002672: b08a sub sp, #40 ; 0x28
8002674: af00 add r7, sp, #0
8002676: 6078 str r0, [r7, #4]
uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
8002678: 2300 movs r3, #0
800267a: 627b str r3, [r7, #36] ; 0x24
uint32_t tmp_isr = hadc->Instance->ISR;
800267c: 687b ldr r3, [r7, #4]
800267e: 681b ldr r3, [r3, #0]
8002680: 681b ldr r3, [r3, #0]
8002682: 61fb str r3, [r7, #28]
uint32_t tmp_ier = hadc->Instance->IER;
8002684: 687b ldr r3, [r7, #4]
8002686: 681b ldr r3, [r3, #0]
8002688: 685b ldr r3, [r3, #4]
800268a: 61bb str r3, [r7, #24]
uint32_t tmp_adc_inj_is_trigger_source_sw_start;
uint32_t tmp_adc_reg_is_trigger_source_sw_start;
uint32_t tmp_cfgr;
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmpADC_Master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
800268c: 4883 ldr r0, [pc, #524] ; (800289c <HAL_ADC_IRQHandler+0x22c>)
800268e: f7ff fce5 bl 800205c <LL_ADC_GetMultimode>
8002692: 6178 str r0, [r7, #20]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
/* ========== Check End of Sampling flag for ADC group regular ========== */
if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
8002694: 69fb ldr r3, [r7, #28]
8002696: f003 0302 and.w r3, r3, #2
800269a: 2b00 cmp r3, #0
800269c: d017 beq.n 80026ce <HAL_ADC_IRQHandler+0x5e>
800269e: 69bb ldr r3, [r7, #24]
80026a0: f003 0302 and.w r3, r3, #2
80026a4: 2b00 cmp r3, #0
80026a6: d012 beq.n 80026ce <HAL_ADC_IRQHandler+0x5e>
{
/* Update state machine on end of sampling status if not in error state */
if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
80026a8: 687b ldr r3, [r7, #4]
80026aa: 6ddb ldr r3, [r3, #92] ; 0x5c
80026ac: f003 0310 and.w r3, r3, #16
80026b0: 2b00 cmp r3, #0
80026b2: d105 bne.n 80026c0 <HAL_ADC_IRQHandler+0x50>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
80026b4: 687b ldr r3, [r7, #4]
80026b6: 6ddb ldr r3, [r3, #92] ; 0x5c
80026b8: f443 6200 orr.w r2, r3, #2048 ; 0x800
80026bc: 687b ldr r3, [r7, #4]
80026be: 65da str r2, [r3, #92] ; 0x5c
/* End Of Sampling callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->EndOfSamplingCallback(hadc);
#else
HAL_ADCEx_EndOfSamplingCallback(hadc);
80026c0: 6878 ldr r0, [r7, #4]
80026c2: f000 ff41 bl 8003548 <HAL_ADCEx_EndOfSamplingCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear regular group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
80026c6: 687b ldr r3, [r7, #4]
80026c8: 681b ldr r3, [r3, #0]
80026ca: 2202 movs r2, #2
80026cc: 601a str r2, [r3, #0]
}
/* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
80026ce: 69fb ldr r3, [r7, #28]
80026d0: f003 0304 and.w r3, r3, #4
80026d4: 2b00 cmp r3, #0
80026d6: d004 beq.n 80026e2 <HAL_ADC_IRQHandler+0x72>
80026d8: 69bb ldr r3, [r7, #24]
80026da: f003 0304 and.w r3, r3, #4
80026de: 2b00 cmp r3, #0
80026e0: d10a bne.n 80026f8 <HAL_ADC_IRQHandler+0x88>
(((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
80026e2: 69fb ldr r3, [r7, #28]
80026e4: f003 0308 and.w r3, r3, #8
if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
80026e8: 2b00 cmp r3, #0
80026ea: f000 8085 beq.w 80027f8 <HAL_ADC_IRQHandler+0x188>
(((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
80026ee: 69bb ldr r3, [r7, #24]
80026f0: f003 0308 and.w r3, r3, #8
80026f4: 2b00 cmp r3, #0
80026f6: d07f beq.n 80027f8 <HAL_ADC_IRQHandler+0x188>
{
/* Update state machine on conversion status if not in error state */
if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
80026f8: 687b ldr r3, [r7, #4]
80026fa: 6ddb ldr r3, [r3, #92] ; 0x5c
80026fc: f003 0310 and.w r3, r3, #16
8002700: 2b00 cmp r3, #0
8002702: d105 bne.n 8002710 <HAL_ADC_IRQHandler+0xa0>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
8002704: 687b ldr r3, [r7, #4]
8002706: 6ddb ldr r3, [r3, #92] ; 0x5c
8002708: f443 7200 orr.w r2, r3, #512 ; 0x200
800270c: 687b ldr r3, [r7, #4]
800270e: 65da str r2, [r3, #92] ; 0x5c
}
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going */
/* to disable interruption. */
if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
8002710: 687b ldr r3, [r7, #4]
8002712: 681b ldr r3, [r3, #0]
8002714: 4618 mov r0, r3
8002716: f7ff fbfb bl 8001f10 <LL_ADC_REG_IsTriggerSourceSWStart>
800271a: 4603 mov r3, r0
800271c: 2b00 cmp r3, #0
800271e: d064 beq.n 80027ea <HAL_ADC_IRQHandler+0x17a>
{
/* Get relevant register CFGR in ADC instance of ADC master or slave */
/* in function of multimode state (for devices with multimode */
/* available). */
#if defined(ADC_MULTIMODE_SUPPORT)
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
8002720: 687b ldr r3, [r7, #4]
8002722: 681b ldr r3, [r3, #0]
8002724: 4a5e ldr r2, [pc, #376] ; (80028a0 <HAL_ADC_IRQHandler+0x230>)
8002726: 4293 cmp r3, r2
8002728: d002 beq.n 8002730 <HAL_ADC_IRQHandler+0xc0>
800272a: 687b ldr r3, [r7, #4]
800272c: 681b ldr r3, [r3, #0]
800272e: e001 b.n 8002734 <HAL_ADC_IRQHandler+0xc4>
8002730: f04f 43a0 mov.w r3, #1342177280 ; 0x50000000
8002734: 687a ldr r2, [r7, #4]
8002736: 6812 ldr r2, [r2, #0]
8002738: 4293 cmp r3, r2
800273a: d008 beq.n 800274e <HAL_ADC_IRQHandler+0xde>
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
800273c: 697b ldr r3, [r7, #20]
800273e: 2b00 cmp r3, #0
8002740: d005 beq.n 800274e <HAL_ADC_IRQHandler+0xde>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
8002742: 697b ldr r3, [r7, #20]
8002744: 2b05 cmp r3, #5
8002746: d002 beq.n 800274e <HAL_ADC_IRQHandler+0xde>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
8002748: 697b ldr r3, [r7, #20]
800274a: 2b09 cmp r3, #9
800274c: d104 bne.n 8002758 <HAL_ADC_IRQHandler+0xe8>
)
{
/* check CONT bit directly in handle ADC CFGR register */
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
800274e: 687b ldr r3, [r7, #4]
8002750: 681b ldr r3, [r3, #0]
8002752: 68db ldr r3, [r3, #12]
8002754: 623b str r3, [r7, #32]
8002756: e00d b.n 8002774 <HAL_ADC_IRQHandler+0x104>
}
else
{
/* else need to check Master ADC CONT bit */
tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
8002758: 687b ldr r3, [r7, #4]
800275a: 681b ldr r3, [r3, #0]
800275c: 4a50 ldr r2, [pc, #320] ; (80028a0 <HAL_ADC_IRQHandler+0x230>)
800275e: 4293 cmp r3, r2
8002760: d002 beq.n 8002768 <HAL_ADC_IRQHandler+0xf8>
8002762: 687b ldr r3, [r7, #4]
8002764: 681b ldr r3, [r3, #0]
8002766: e001 b.n 800276c <HAL_ADC_IRQHandler+0xfc>
8002768: f04f 43a0 mov.w r3, #1342177280 ; 0x50000000
800276c: 613b str r3, [r7, #16]
tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
800276e: 693b ldr r3, [r7, #16]
8002770: 68db ldr r3, [r3, #12]
8002772: 623b str r3, [r7, #32]
#else
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
#endif
/* Carry on if continuous mode is disabled */
if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
8002774: 6a3b ldr r3, [r7, #32]
8002776: f403 5300 and.w r3, r3, #8192 ; 0x2000
800277a: 2b00 cmp r3, #0
800277c: d135 bne.n 80027ea <HAL_ADC_IRQHandler+0x17a>
{
/* If End of Sequence is reached, disable interrupts */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
800277e: 687b ldr r3, [r7, #4]
8002780: 681b ldr r3, [r3, #0]
8002782: 681b ldr r3, [r3, #0]
8002784: f003 0308 and.w r3, r3, #8
8002788: 2b08 cmp r3, #8
800278a: d12e bne.n 80027ea <HAL_ADC_IRQHandler+0x17a>
{
/* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
/* ADSTART==0 (no conversion on going) */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
800278c: 687b ldr r3, [r7, #4]
800278e: 681b ldr r3, [r3, #0]
8002790: 4618 mov r0, r3
8002792: f7ff fd08 bl 80021a6 <LL_ADC_REG_IsConversionOngoing>
8002796: 4603 mov r3, r0
8002798: 2b00 cmp r3, #0
800279a: d11a bne.n 80027d2 <HAL_ADC_IRQHandler+0x162>
{
/* Disable ADC end of sequence conversion interrupt */
/* Note: Overrun interrupt was enabled with EOC interrupt in */
/* HAL_Start_IT(), but is not disabled here because can be used */
/* by overrun IRQ process below. */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
800279c: 687b ldr r3, [r7, #4]
800279e: 681b ldr r3, [r3, #0]
80027a0: 685a ldr r2, [r3, #4]
80027a2: 687b ldr r3, [r7, #4]
80027a4: 681b ldr r3, [r3, #0]
80027a6: f022 020c bic.w r2, r2, #12
80027aa: 605a str r2, [r3, #4]
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
80027ac: 687b ldr r3, [r7, #4]
80027ae: 6ddb ldr r3, [r3, #92] ; 0x5c
80027b0: f423 7280 bic.w r2, r3, #256 ; 0x100
80027b4: 687b ldr r3, [r7, #4]
80027b6: 65da str r2, [r3, #92] ; 0x5c
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
80027b8: 687b ldr r3, [r7, #4]
80027ba: 6ddb ldr r3, [r3, #92] ; 0x5c
80027bc: f403 5380 and.w r3, r3, #4096 ; 0x1000
80027c0: 2b00 cmp r3, #0
80027c2: d112 bne.n 80027ea <HAL_ADC_IRQHandler+0x17a>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
80027c4: 687b ldr r3, [r7, #4]
80027c6: 6ddb ldr r3, [r3, #92] ; 0x5c
80027c8: f043 0201 orr.w r2, r3, #1
80027cc: 687b ldr r3, [r7, #4]
80027ce: 65da str r2, [r3, #92] ; 0x5c
80027d0: e00b b.n 80027ea <HAL_ADC_IRQHandler+0x17a>
}
}
else
{
/* Change ADC state to error state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80027d2: 687b ldr r3, [r7, #4]
80027d4: 6ddb ldr r3, [r3, #92] ; 0x5c
80027d6: f043 0210 orr.w r2, r3, #16
80027da: 687b ldr r3, [r7, #4]
80027dc: 65da str r2, [r3, #92] ; 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80027de: 687b ldr r3, [r7, #4]
80027e0: 6e1b ldr r3, [r3, #96] ; 0x60
80027e2: f043 0201 orr.w r2, r3, #1
80027e6: 687b ldr r3, [r7, #4]
80027e8: 661a str r2, [r3, #96] ; 0x60
/* possibility to use: */
/* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvCpltCallback(hadc);
#else
HAL_ADC_ConvCpltCallback(hadc);
80027ea: 6878 ldr r0, [r7, #4]
80027ec: f7fd ff5a bl 80006a4 <HAL_ADC_ConvCpltCallback>
/* Clear regular group conversion flag */
/* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
/* conversion flags clear induces the release of the preserved data.*/
/* Therefore, if the preserved data value is needed, it must be */
/* read preliminarily into HAL_ADC_ConvCpltCallback(). */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
80027f0: 687b ldr r3, [r7, #4]
80027f2: 681b ldr r3, [r3, #0]
80027f4: 220c movs r2, #12
80027f6: 601a str r2, [r3, #0]
}
/* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
80027f8: 69fb ldr r3, [r7, #28]
80027fa: f003 0320 and.w r3, r3, #32
80027fe: 2b00 cmp r3, #0
8002800: d004 beq.n 800280c <HAL_ADC_IRQHandler+0x19c>
8002802: 69bb ldr r3, [r7, #24]
8002804: f003 0320 and.w r3, r3, #32
8002808: 2b00 cmp r3, #0
800280a: d10b bne.n 8002824 <HAL_ADC_IRQHandler+0x1b4>
(((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
800280c: 69fb ldr r3, [r7, #28]
800280e: f003 0340 and.w r3, r3, #64 ; 0x40
if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
8002812: 2b00 cmp r3, #0
8002814: f000 809e beq.w 8002954 <HAL_ADC_IRQHandler+0x2e4>
(((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
8002818: 69bb ldr r3, [r7, #24]
800281a: f003 0340 and.w r3, r3, #64 ; 0x40
800281e: 2b00 cmp r3, #0
8002820: f000 8098 beq.w 8002954 <HAL_ADC_IRQHandler+0x2e4>
{
/* Update state machine on conversion status if not in error state */
if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
8002824: 687b ldr r3, [r7, #4]
8002826: 6ddb ldr r3, [r3, #92] ; 0x5c
8002828: f003 0310 and.w r3, r3, #16
800282c: 2b00 cmp r3, #0
800282e: d105 bne.n 800283c <HAL_ADC_IRQHandler+0x1cc>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
8002830: 687b ldr r3, [r7, #4]
8002832: 6ddb ldr r3, [r3, #92] ; 0x5c
8002834: f443 5200 orr.w r2, r3, #8192 ; 0x2000
8002838: 687b ldr r3, [r7, #4]
800283a: 65da str r2, [r3, #92] ; 0x5c
}
/* Retrieve ADC configuration */
tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
800283c: 687b ldr r3, [r7, #4]
800283e: 681b ldr r3, [r3, #0]
8002840: 4618 mov r0, r3
8002842: f7ff fba4 bl 8001f8e <LL_ADC_INJ_IsTriggerSourceSWStart>
8002846: 60f8 str r0, [r7, #12]
tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
8002848: 687b ldr r3, [r7, #4]
800284a: 681b ldr r3, [r3, #0]
800284c: 4618 mov r0, r3
800284e: f7ff fb5f bl 8001f10 <LL_ADC_REG_IsTriggerSourceSWStart>
8002852: 60b8 str r0, [r7, #8]
/* Get relevant register CFGR in ADC instance of ADC master or slave */
/* in function of multimode state (for devices with multimode */
/* available). */
#if defined(ADC_MULTIMODE_SUPPORT)
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
8002854: 687b ldr r3, [r7, #4]
8002856: 681b ldr r3, [r3, #0]
8002858: 4a11 ldr r2, [pc, #68] ; (80028a0 <HAL_ADC_IRQHandler+0x230>)
800285a: 4293 cmp r3, r2
800285c: d002 beq.n 8002864 <HAL_ADC_IRQHandler+0x1f4>
800285e: 687b ldr r3, [r7, #4]
8002860: 681b ldr r3, [r3, #0]
8002862: e001 b.n 8002868 <HAL_ADC_IRQHandler+0x1f8>
8002864: f04f 43a0 mov.w r3, #1342177280 ; 0x50000000
8002868: 687a ldr r2, [r7, #4]
800286a: 6812 ldr r2, [r2, #0]
800286c: 4293 cmp r3, r2
800286e: d008 beq.n 8002882 <HAL_ADC_IRQHandler+0x212>
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
8002870: 697b ldr r3, [r7, #20]
8002872: 2b00 cmp r3, #0
8002874: d005 beq.n 8002882 <HAL_ADC_IRQHandler+0x212>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
8002876: 697b ldr r3, [r7, #20]
8002878: 2b06 cmp r3, #6
800287a: d002 beq.n 8002882 <HAL_ADC_IRQHandler+0x212>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
800287c: 697b ldr r3, [r7, #20]
800287e: 2b07 cmp r3, #7
8002880: d104 bne.n 800288c <HAL_ADC_IRQHandler+0x21c>
)
{
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
8002882: 687b ldr r3, [r7, #4]
8002884: 681b ldr r3, [r3, #0]
8002886: 68db ldr r3, [r3, #12]
8002888: 623b str r3, [r7, #32]
800288a: e011 b.n 80028b0 <HAL_ADC_IRQHandler+0x240>
}
else
{
tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
800288c: 687b ldr r3, [r7, #4]
800288e: 681b ldr r3, [r3, #0]
8002890: 4a03 ldr r2, [pc, #12] ; (80028a0 <HAL_ADC_IRQHandler+0x230>)
8002892: 4293 cmp r3, r2
8002894: d006 beq.n 80028a4 <HAL_ADC_IRQHandler+0x234>
8002896: 687b ldr r3, [r7, #4]
8002898: 681b ldr r3, [r3, #0]
800289a: e005 b.n 80028a8 <HAL_ADC_IRQHandler+0x238>
800289c: 50000300 .word 0x50000300
80028a0: 50000100 .word 0x50000100
80028a4: f04f 43a0 mov.w r3, #1342177280 ; 0x50000000
80028a8: 613b str r3, [r7, #16]
tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
80028aa: 693b ldr r3, [r7, #16]
80028ac: 68db ldr r3, [r3, #12]
80028ae: 623b str r3, [r7, #32]
/* Disable interruption if no further conversion upcoming by injected */
/* external trigger or by automatic injected conversion with regular */
/* group having no further conversion upcoming (same conditions as */
/* regular group interruption disabling above), */
/* and if injected scan sequence is completed. */
if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
80028b0: 68fb ldr r3, [r7, #12]
80028b2: 2b00 cmp r3, #0
80028b4: d047 beq.n 8002946 <HAL_ADC_IRQHandler+0x2d6>
{
if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) ||
80028b6: 6a3b ldr r3, [r7, #32]
80028b8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80028bc: 2b00 cmp r3, #0
80028be: d007 beq.n 80028d0 <HAL_ADC_IRQHandler+0x260>
80028c0: 68bb ldr r3, [r7, #8]
80028c2: 2b00 cmp r3, #0
80028c4: d03f beq.n 8002946 <HAL_ADC_IRQHandler+0x2d6>
((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
(READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))
80028c6: 6a3b ldr r3, [r7, #32]
80028c8: f403 5300 and.w r3, r3, #8192 ; 0x2000
((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
80028cc: 2b00 cmp r3, #0
80028ce: d13a bne.n 8002946 <HAL_ADC_IRQHandler+0x2d6>
{
/* If End of Sequence is reached, disable interrupts */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
80028d0: 687b ldr r3, [r7, #4]
80028d2: 681b ldr r3, [r3, #0]
80028d4: 681b ldr r3, [r3, #0]
80028d6: f003 0340 and.w r3, r3, #64 ; 0x40
80028da: 2b40 cmp r3, #64 ; 0x40
80028dc: d133 bne.n 8002946 <HAL_ADC_IRQHandler+0x2d6>
/* when the last context has been fully processed, JSQR is reset */
/* by the hardware. Even if no injected conversion is planned to come */
/* (queue empty, triggers are ignored), it can start again */
/* immediately after setting a new context (JADSTART is still set). */
/* Therefore, state of HAL ADC injected group is kept to busy. */
if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
80028de: 6a3b ldr r3, [r7, #32]
80028e0: f403 1300 and.w r3, r3, #2097152 ; 0x200000
80028e4: 2b00 cmp r3, #0
80028e6: d12e bne.n 8002946 <HAL_ADC_IRQHandler+0x2d6>
{
/* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
/* JADSTART==0 (no conversion on going) */
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
80028e8: 687b ldr r3, [r7, #4]
80028ea: 681b ldr r3, [r3, #0]
80028ec: 4618 mov r0, r3
80028ee: f7ff fc6d bl 80021cc <LL_ADC_INJ_IsConversionOngoing>
80028f2: 4603 mov r3, r0
80028f4: 2b00 cmp r3, #0
80028f6: d11a bne.n 800292e <HAL_ADC_IRQHandler+0x2be>
{
/* Disable ADC end of sequence conversion interrupt */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
80028f8: 687b ldr r3, [r7, #4]
80028fa: 681b ldr r3, [r3, #0]
80028fc: 685a ldr r2, [r3, #4]
80028fe: 687b ldr r3, [r7, #4]
8002900: 681b ldr r3, [r3, #0]
8002902: f022 0260 bic.w r2, r2, #96 ; 0x60
8002906: 605a str r2, [r3, #4]
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
8002908: 687b ldr r3, [r7, #4]
800290a: 6ddb ldr r3, [r3, #92] ; 0x5c
800290c: f423 5280 bic.w r2, r3, #4096 ; 0x1000
8002910: 687b ldr r3, [r7, #4]
8002912: 65da str r2, [r3, #92] ; 0x5c
if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
8002914: 687b ldr r3, [r7, #4]
8002916: 6ddb ldr r3, [r3, #92] ; 0x5c
8002918: f403 7380 and.w r3, r3, #256 ; 0x100
800291c: 2b00 cmp r3, #0
800291e: d112 bne.n 8002946 <HAL_ADC_IRQHandler+0x2d6>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
8002920: 687b ldr r3, [r7, #4]
8002922: 6ddb ldr r3, [r3, #92] ; 0x5c
8002924: f043 0201 orr.w r2, r3, #1
8002928: 687b ldr r3, [r7, #4]
800292a: 65da str r2, [r3, #92] ; 0x5c
800292c: e00b b.n 8002946 <HAL_ADC_IRQHandler+0x2d6>
}
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800292e: 687b ldr r3, [r7, #4]
8002930: 6ddb ldr r3, [r3, #92] ; 0x5c
8002932: f043 0210 orr.w r2, r3, #16
8002936: 687b ldr r3, [r7, #4]
8002938: 65da str r2, [r3, #92] ; 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
800293a: 687b ldr r3, [r7, #4]
800293c: 6e1b ldr r3, [r3, #96] ; 0x60
800293e: f043 0201 orr.w r2, r3, #1
8002942: 687b ldr r3, [r7, #4]
8002944: 661a str r2, [r3, #96] ; 0x60
interruption has been triggered by end of conversion or end of
sequence. */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->InjectedConvCpltCallback(hadc);
#else
HAL_ADCEx_InjectedConvCpltCallback(hadc);
8002946: 6878 ldr r0, [r7, #4]
8002948: f000 fdd6 bl 80034f8 <HAL_ADCEx_InjectedConvCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear injected group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
800294c: 687b ldr r3, [r7, #4]
800294e: 681b ldr r3, [r3, #0]
8002950: 2260 movs r2, #96 ; 0x60
8002952: 601a str r2, [r3, #0]
}
/* ========== Check Analog watchdog 1 flag ========== */
if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
8002954: 69fb ldr r3, [r7, #28]
8002956: f003 0380 and.w r3, r3, #128 ; 0x80
800295a: 2b00 cmp r3, #0
800295c: d011 beq.n 8002982 <HAL_ADC_IRQHandler+0x312>
800295e: 69bb ldr r3, [r7, #24]
8002960: f003 0380 and.w r3, r3, #128 ; 0x80
8002964: 2b00 cmp r3, #0
8002966: d00c beq.n 8002982 <HAL_ADC_IRQHandler+0x312>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
8002968: 687b ldr r3, [r7, #4]
800296a: 6ddb ldr r3, [r3, #92] ; 0x5c
800296c: f443 3280 orr.w r2, r3, #65536 ; 0x10000
8002970: 687b ldr r3, [r7, #4]
8002972: 65da str r2, [r3, #92] ; 0x5c
/* Level out of window 1 callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->LevelOutOfWindowCallback(hadc);
#else
HAL_ADC_LevelOutOfWindowCallback(hadc);
8002974: 6878 ldr r0, [r7, #4]
8002976: f000 f89f bl 8002ab8 <HAL_ADC_LevelOutOfWindowCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
800297a: 687b ldr r3, [r7, #4]
800297c: 681b ldr r3, [r3, #0]
800297e: 2280 movs r2, #128 ; 0x80
8002980: 601a str r2, [r3, #0]
}
/* ========== Check analog watchdog 2 flag ========== */
if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
8002982: 69fb ldr r3, [r7, #28]
8002984: f403 7380 and.w r3, r3, #256 ; 0x100
8002988: 2b00 cmp r3, #0
800298a: d012 beq.n 80029b2 <HAL_ADC_IRQHandler+0x342>
800298c: 69bb ldr r3, [r7, #24]
800298e: f403 7380 and.w r3, r3, #256 ; 0x100
8002992: 2b00 cmp r3, #0
8002994: d00d beq.n 80029b2 <HAL_ADC_IRQHandler+0x342>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
8002996: 687b ldr r3, [r7, #4]
8002998: 6ddb ldr r3, [r3, #92] ; 0x5c
800299a: f443 3200 orr.w r2, r3, #131072 ; 0x20000
800299e: 687b ldr r3, [r7, #4]
80029a0: 65da str r2, [r3, #92] ; 0x5c
/* Level out of window 2 callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->LevelOutOfWindow2Callback(hadc);
#else
HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
80029a2: 6878 ldr r0, [r7, #4]
80029a4: f000 fdbc bl 8003520 <HAL_ADCEx_LevelOutOfWindow2Callback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
80029a8: 687b ldr r3, [r7, #4]
80029aa: 681b ldr r3, [r3, #0]
80029ac: f44f 7280 mov.w r2, #256 ; 0x100
80029b0: 601a str r2, [r3, #0]
}
/* ========== Check analog watchdog 3 flag ========== */
if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
80029b2: 69fb ldr r3, [r7, #28]
80029b4: f403 7300 and.w r3, r3, #512 ; 0x200
80029b8: 2b00 cmp r3, #0
80029ba: d012 beq.n 80029e2 <HAL_ADC_IRQHandler+0x372>
80029bc: 69bb ldr r3, [r7, #24]
80029be: f403 7300 and.w r3, r3, #512 ; 0x200
80029c2: 2b00 cmp r3, #0
80029c4: d00d beq.n 80029e2 <HAL_ADC_IRQHandler+0x372>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
80029c6: 687b ldr r3, [r7, #4]
80029c8: 6ddb ldr r3, [r3, #92] ; 0x5c
80029ca: f443 2280 orr.w r2, r3, #262144 ; 0x40000
80029ce: 687b ldr r3, [r7, #4]
80029d0: 65da str r2, [r3, #92] ; 0x5c
/* Level out of window 3 callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->LevelOutOfWindow3Callback(hadc);
#else
HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
80029d2: 6878 ldr r0, [r7, #4]
80029d4: f000 fdae bl 8003534 <HAL_ADCEx_LevelOutOfWindow3Callback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
80029d8: 687b ldr r3, [r7, #4]
80029da: 681b ldr r3, [r3, #0]
80029dc: f44f 7200 mov.w r2, #512 ; 0x200
80029e0: 601a str r2, [r3, #0]
}
/* ========== Check Overrun flag ========== */
if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
80029e2: 69fb ldr r3, [r7, #28]
80029e4: f003 0310 and.w r3, r3, #16
80029e8: 2b00 cmp r3, #0
80029ea: d036 beq.n 8002a5a <HAL_ADC_IRQHandler+0x3ea>
80029ec: 69bb ldr r3, [r7, #24]
80029ee: f003 0310 and.w r3, r3, #16
80029f2: 2b00 cmp r3, #0
80029f4: d031 beq.n 8002a5a <HAL_ADC_IRQHandler+0x3ea>
/* overrun event is not considered as an error. */
/* (cf ref manual "Managing conversions without using the DMA and without */
/* overrun ") */
/* Exception for usage with DMA overrun event always considered as an */
/* error. */
if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
80029f6: 687b ldr r3, [r7, #4]
80029f8: 6bdb ldr r3, [r3, #60] ; 0x3c
80029fa: 2b00 cmp r3, #0
80029fc: d102 bne.n 8002a04 <HAL_ADC_IRQHandler+0x394>
{
overrun_error = 1UL;
80029fe: 2301 movs r3, #1
8002a00: 627b str r3, [r7, #36] ; 0x24
8002a02: e014 b.n 8002a2e <HAL_ADC_IRQHandler+0x3be>
}
else
{
/* Check DMA configuration */
#if defined(ADC_MULTIMODE_SUPPORT)
if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT)
8002a04: 697b ldr r3, [r7, #20]
8002a06: 2b00 cmp r3, #0
8002a08: d008 beq.n 8002a1c <HAL_ADC_IRQHandler+0x3ac>
{
/* Multimode (when feature is available) is enabled,
Common Control Register MDMA bits must be checked. */
if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
8002a0a: 4825 ldr r0, [pc, #148] ; (8002aa0 <HAL_ADC_IRQHandler+0x430>)
8002a0c: f7ff fb34 bl 8002078 <LL_ADC_GetMultiDMATransfer>
8002a10: 4603 mov r3, r0
8002a12: 2b00 cmp r3, #0
8002a14: d00b beq.n 8002a2e <HAL_ADC_IRQHandler+0x3be>
{
overrun_error = 1UL;
8002a16: 2301 movs r3, #1
8002a18: 627b str r3, [r7, #36] ; 0x24
8002a1a: e008 b.n 8002a2e <HAL_ADC_IRQHandler+0x3be>
}
else
#endif
{
/* Multimode not set or feature not available or ADC independent */
if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL)
8002a1c: 687b ldr r3, [r7, #4]
8002a1e: 681b ldr r3, [r3, #0]
8002a20: 68db ldr r3, [r3, #12]
8002a22: f003 0301 and.w r3, r3, #1
8002a26: 2b00 cmp r3, #0
8002a28: d001 beq.n 8002a2e <HAL_ADC_IRQHandler+0x3be>
{
overrun_error = 1UL;
8002a2a: 2301 movs r3, #1
8002a2c: 627b str r3, [r7, #36] ; 0x24
}
}
}
if (overrun_error == 1UL)
8002a2e: 6a7b ldr r3, [r7, #36] ; 0x24
8002a30: 2b01 cmp r3, #1
8002a32: d10e bne.n 8002a52 <HAL_ADC_IRQHandler+0x3e2>
{
/* Change ADC state to error state */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
8002a34: 687b ldr r3, [r7, #4]
8002a36: 6ddb ldr r3, [r3, #92] ; 0x5c
8002a38: f443 6280 orr.w r2, r3, #1024 ; 0x400
8002a3c: 687b ldr r3, [r7, #4]
8002a3e: 65da str r2, [r3, #92] ; 0x5c
/* Set ADC error code to overrun */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
8002a40: 687b ldr r3, [r7, #4]
8002a42: 6e1b ldr r3, [r3, #96] ; 0x60
8002a44: f043 0202 orr.w r2, r3, #2
8002a48: 687b ldr r3, [r7, #4]
8002a4a: 661a str r2, [r3, #96] ; 0x60
/* Therefore, old ADC conversion data can be retrieved in */
/* function "HAL_ADC_ErrorCallback()". */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ErrorCallback(hadc);
#else
HAL_ADC_ErrorCallback(hadc);
8002a4c: 6878 ldr r0, [r7, #4]
8002a4e: f000 f83d bl 8002acc <HAL_ADC_ErrorCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
/* Clear ADC overrun flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
8002a52: 687b ldr r3, [r7, #4]
8002a54: 681b ldr r3, [r3, #0]
8002a56: 2210 movs r2, #16
8002a58: 601a str r2, [r3, #0]
}
/* ========== Check Injected context queue overflow flag ========== */
if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
8002a5a: 69fb ldr r3, [r7, #28]
8002a5c: f403 6380 and.w r3, r3, #1024 ; 0x400
8002a60: 2b00 cmp r3, #0
8002a62: d018 beq.n 8002a96 <HAL_ADC_IRQHandler+0x426>
8002a64: 69bb ldr r3, [r7, #24]
8002a66: f403 6380 and.w r3, r3, #1024 ; 0x400
8002a6a: 2b00 cmp r3, #0
8002a6c: d013 beq.n 8002a96 <HAL_ADC_IRQHandler+0x426>
{
/* Change ADC state to overrun state */
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
8002a6e: 687b ldr r3, [r7, #4]
8002a70: 6ddb ldr r3, [r3, #92] ; 0x5c
8002a72: f443 4280 orr.w r2, r3, #16384 ; 0x4000
8002a76: 687b ldr r3, [r7, #4]
8002a78: 65da str r2, [r3, #92] ; 0x5c
/* Set ADC error code to Injected context queue overflow */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
8002a7a: 687b ldr r3, [r7, #4]
8002a7c: 6e1b ldr r3, [r3, #96] ; 0x60
8002a7e: f043 0208 orr.w r2, r3, #8
8002a82: 687b ldr r3, [r7, #4]
8002a84: 661a str r2, [r3, #96] ; 0x60
/* Clear the Injected context queue overflow flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
8002a86: 687b ldr r3, [r7, #4]
8002a88: 681b ldr r3, [r3, #0]
8002a8a: f44f 6280 mov.w r2, #1024 ; 0x400
8002a8e: 601a str r2, [r3, #0]
/* Injected context queue overflow callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->InjectedQueueOverflowCallback(hadc);
#else
HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
8002a90: 6878 ldr r0, [r7, #4]
8002a92: f000 fd3b bl 800350c <HAL_ADCEx_InjectedQueueOverflowCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
}
8002a96: bf00 nop
8002a98: 3728 adds r7, #40 ; 0x28
8002a9a: 46bd mov sp, r7
8002a9c: bd80 pop {r7, pc}
8002a9e: bf00 nop
8002aa0: 50000300 .word 0x50000300
08002aa4 <HAL_ADC_ConvHalfCpltCallback>:
* @brief Conversion DMA half-transfer callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
{
8002aa4: b480 push {r7}
8002aa6: b083 sub sp, #12
8002aa8: af00 add r7, sp, #0
8002aaa: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
*/
}
8002aac: bf00 nop
8002aae: 370c adds r7, #12
8002ab0: 46bd mov sp, r7
8002ab2: f85d 7b04 ldr.w r7, [sp], #4
8002ab6: 4770 bx lr
08002ab8 <HAL_ADC_LevelOutOfWindowCallback>:
* @brief Analog watchdog 1 callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
{
8002ab8: b480 push {r7}
8002aba: b083 sub sp, #12
8002abc: af00 add r7, sp, #0
8002abe: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
*/
}
8002ac0: bf00 nop
8002ac2: 370c adds r7, #12
8002ac4: 46bd mov sp, r7
8002ac6: f85d 7b04 ldr.w r7, [sp], #4
8002aca: 4770 bx lr
08002acc <HAL_ADC_ErrorCallback>:
* (this function is also clearing overrun flag)
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
{
8002acc: b480 push {r7}
8002ace: b083 sub sp, #12
8002ad0: af00 add r7, sp, #0
8002ad2: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ErrorCallback must be implemented in the user file.
*/
}
8002ad4: bf00 nop
8002ad6: 370c adds r7, #12
8002ad8: 46bd mov sp, r7
8002ada: f85d 7b04 ldr.w r7, [sp], #4
8002ade: 4770 bx lr
08002ae0 <HAL_ADC_ConfigChannel>:
* @param hadc ADC handle
* @param sConfig Structure of ADC channel assigned to ADC group regular.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
{
8002ae0: b580 push {r7, lr}
8002ae2: b0b6 sub sp, #216 ; 0xd8
8002ae4: af00 add r7, sp, #0
8002ae6: 6078 str r0, [r7, #4]
8002ae8: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8002aea: 2300 movs r3, #0
8002aec: f887 30d7 strb.w r3, [r7, #215] ; 0xd7
uint32_t tmpOffsetShifted;
uint32_t tmp_config_internal_channel;
__IO uint32_t wait_loop_index = 0UL;
8002af0: 2300 movs r3, #0
8002af2: 60fb str r3, [r7, #12]
{
assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel));
}
/* Process locked */
__HAL_LOCK(hadc);
8002af4: 687b ldr r3, [r7, #4]
8002af6: f893 3058 ldrb.w r3, [r3, #88] ; 0x58
8002afa: 2b01 cmp r3, #1
8002afc: d101 bne.n 8002b02 <HAL_ADC_ConfigChannel+0x22>
8002afe: 2302 movs r3, #2
8002b00: e3c8 b.n 8003294 <HAL_ADC_ConfigChannel+0x7b4>
8002b02: 687b ldr r3, [r7, #4]
8002b04: 2201 movs r2, #1
8002b06: f883 2058 strb.w r2, [r3, #88] ; 0x58
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel number */
/* - Channel rank */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
8002b0a: 687b ldr r3, [r7, #4]
8002b0c: 681b ldr r3, [r3, #0]
8002b0e: 4618 mov r0, r3
8002b10: f7ff fb49 bl 80021a6 <LL_ADC_REG_IsConversionOngoing>
8002b14: 4603 mov r3, r0
8002b16: 2b00 cmp r3, #0
8002b18: f040 83ad bne.w 8003276 <HAL_ADC_ConfigChannel+0x796>
{
/* Set ADC group regular sequence: channel on the selected scan sequence rank */
LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
8002b1c: 687b ldr r3, [r7, #4]
8002b1e: 6818 ldr r0, [r3, #0]
8002b20: 683b ldr r3, [r7, #0]
8002b22: 6859 ldr r1, [r3, #4]
8002b24: 683b ldr r3, [r7, #0]
8002b26: 681b ldr r3, [r3, #0]
8002b28: 461a mov r2, r3
8002b2a: f7ff fa04 bl 8001f36 <LL_ADC_REG_SetSequencerRanks>
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel sampling time */
/* - Channel offset */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
8002b2e: 687b ldr r3, [r7, #4]
8002b30: 681b ldr r3, [r3, #0]
8002b32: 4618 mov r0, r3
8002b34: f7ff fb37 bl 80021a6 <LL_ADC_REG_IsConversionOngoing>
8002b38: f8c7 00d0 str.w r0, [r7, #208] ; 0xd0
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
8002b3c: 687b ldr r3, [r7, #4]
8002b3e: 681b ldr r3, [r3, #0]
8002b40: 4618 mov r0, r3
8002b42: f7ff fb43 bl 80021cc <LL_ADC_INJ_IsConversionOngoing>
8002b46: f8c7 00cc str.w r0, [r7, #204] ; 0xcc
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
8002b4a: f8d7 30d0 ldr.w r3, [r7, #208] ; 0xd0
8002b4e: 2b00 cmp r3, #0
8002b50: f040 81d9 bne.w 8002f06 <HAL_ADC_ConfigChannel+0x426>
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
8002b54: f8d7 30cc ldr.w r3, [r7, #204] ; 0xcc
8002b58: 2b00 cmp r3, #0
8002b5a: f040 81d4 bne.w 8002f06 <HAL_ADC_ConfigChannel+0x426>
)
{
/* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
if (sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5)
8002b5e: 683b ldr r3, [r7, #0]
8002b60: 689b ldr r3, [r3, #8]
8002b62: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
8002b66: d10f bne.n 8002b88 <HAL_ADC_ConfigChannel+0xa8>
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
8002b68: 687b ldr r3, [r7, #4]
8002b6a: 6818 ldr r0, [r3, #0]
8002b6c: 683b ldr r3, [r7, #0]
8002b6e: 681b ldr r3, [r3, #0]
8002b70: 2200 movs r2, #0
8002b72: 4619 mov r1, r3
8002b74: f7ff fa1e bl 8001fb4 <LL_ADC_SetChannelSamplingTime>
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
8002b78: 687b ldr r3, [r7, #4]
8002b7a: 681b ldr r3, [r3, #0]
8002b7c: f04f 4100 mov.w r1, #2147483648 ; 0x80000000
8002b80: 4618 mov r0, r3
8002b82: f7ff f9b2 bl 8001eea <LL_ADC_SetSamplingTimeCommonConfig>
8002b86: e00e b.n 8002ba6 <HAL_ADC_ConfigChannel+0xc6>
}
else
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
8002b88: 687b ldr r3, [r7, #4]
8002b8a: 6818 ldr r0, [r3, #0]
8002b8c: 683b ldr r3, [r7, #0]
8002b8e: 6819 ldr r1, [r3, #0]
8002b90: 683b ldr r3, [r7, #0]
8002b92: 689b ldr r3, [r3, #8]
8002b94: 461a mov r2, r3
8002b96: f7ff fa0d bl 8001fb4 <LL_ADC_SetChannelSamplingTime>
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
8002b9a: 687b ldr r3, [r7, #4]
8002b9c: 681b ldr r3, [r3, #0]
8002b9e: 2100 movs r1, #0
8002ba0: 4618 mov r0, r3
8002ba2: f7ff f9a2 bl 8001eea <LL_ADC_SetSamplingTimeCommonConfig>
/* Configure the offset: offset enable/disable, channel, offset value */
/* Shift the offset with respect to the selected ADC resolution. */
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
8002ba6: 683b ldr r3, [r7, #0]
8002ba8: 695a ldr r2, [r3, #20]
8002baa: 687b ldr r3, [r7, #4]
8002bac: 681b ldr r3, [r3, #0]
8002bae: 68db ldr r3, [r3, #12]
8002bb0: 08db lsrs r3, r3, #3
8002bb2: f003 0303 and.w r3, r3, #3
8002bb6: 005b lsls r3, r3, #1
8002bb8: fa02 f303 lsl.w r3, r2, r3
8002bbc: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
8002bc0: 683b ldr r3, [r7, #0]
8002bc2: 691b ldr r3, [r3, #16]
8002bc4: 2b04 cmp r3, #4
8002bc6: d022 beq.n 8002c0e <HAL_ADC_ConfigChannel+0x12e>
{
/* Set ADC selected offset number */
LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
8002bc8: 687b ldr r3, [r7, #4]
8002bca: 6818 ldr r0, [r3, #0]
8002bcc: 683b ldr r3, [r7, #0]
8002bce: 6919 ldr r1, [r3, #16]
8002bd0: 683b ldr r3, [r7, #0]
8002bd2: 681a ldr r2, [r3, #0]
8002bd4: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8
8002bd8: f7ff f8fc bl 8001dd4 <LL_ADC_SetOffset>
assert_param(IS_ADC_OFFSET_SIGN(sConfig->OffsetSign));
assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSaturation));
/* Set ADC selected offset sign & saturation */
LL_ADC_SetOffsetSign(hadc->Instance, sConfig->OffsetNumber, sConfig->OffsetSign);
8002bdc: 687b ldr r3, [r7, #4]
8002bde: 6818 ldr r0, [r3, #0]
8002be0: 683b ldr r3, [r7, #0]
8002be2: 6919 ldr r1, [r3, #16]
8002be4: 683b ldr r3, [r7, #0]
8002be6: 699b ldr r3, [r3, #24]
8002be8: 461a mov r2, r3
8002bea: f7ff f948 bl 8001e7e <LL_ADC_SetOffsetSign>
LL_ADC_SetOffsetSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSaturation == ENABLE) ? LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE);
8002bee: 687b ldr r3, [r7, #4]
8002bf0: 6818 ldr r0, [r3, #0]
8002bf2: 683b ldr r3, [r7, #0]
8002bf4: 6919 ldr r1, [r3, #16]
8002bf6: 683b ldr r3, [r7, #0]
8002bf8: 7f1b ldrb r3, [r3, #28]
8002bfa: 2b01 cmp r3, #1
8002bfc: d102 bne.n 8002c04 <HAL_ADC_ConfigChannel+0x124>
8002bfe: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8002c02: e000 b.n 8002c06 <HAL_ADC_ConfigChannel+0x126>
8002c04: 2300 movs r3, #0
8002c06: 461a mov r2, r3
8002c08: f7ff f954 bl 8001eb4 <LL_ADC_SetOffsetSaturation>
8002c0c: e17b b.n 8002f06 <HAL_ADC_ConfigChannel+0x426>
}
else
{
/* Scan each offset register to check if the selected channel is targeted. */
/* If this is the case, the corresponding offset number is disabled. */
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
8002c0e: 687b ldr r3, [r7, #4]
8002c10: 681b ldr r3, [r3, #0]
8002c12: 2100 movs r1, #0
8002c14: 4618 mov r0, r3
8002c16: f7ff f901 bl 8001e1c <LL_ADC_GetOffsetChannel>
8002c1a: 4603 mov r3, r0
8002c1c: f3c3 0312 ubfx r3, r3, #0, #19
8002c20: 2b00 cmp r3, #0
8002c22: d10a bne.n 8002c3a <HAL_ADC_ConfigChannel+0x15a>
8002c24: 687b ldr r3, [r7, #4]
8002c26: 681b ldr r3, [r3, #0]
8002c28: 2100 movs r1, #0
8002c2a: 4618 mov r0, r3
8002c2c: f7ff f8f6 bl 8001e1c <LL_ADC_GetOffsetChannel>
8002c30: 4603 mov r3, r0
8002c32: 0e9b lsrs r3, r3, #26
8002c34: f003 021f and.w r2, r3, #31
8002c38: e01e b.n 8002c78 <HAL_ADC_ConfigChannel+0x198>
8002c3a: 687b ldr r3, [r7, #4]
8002c3c: 681b ldr r3, [r3, #0]
8002c3e: 2100 movs r1, #0
8002c40: 4618 mov r0, r3
8002c42: f7ff f8eb bl 8001e1c <LL_ADC_GetOffsetChannel>
8002c46: 4603 mov r3, r0
8002c48: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002c4c: f8d7 30bc ldr.w r3, [r7, #188] ; 0xbc
8002c50: fa93 f3a3 rbit r3, r3
8002c54: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return result;
8002c58: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8
8002c5c: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0
optimisations using the logic "value was passed to __builtin_clz, so it
is non-zero".
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
single CLZ instruction.
*/
if (value == 0U)
8002c60: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0
8002c64: 2b00 cmp r3, #0
8002c66: d101 bne.n 8002c6c <HAL_ADC_ConfigChannel+0x18c>
{
return 32U;
8002c68: 2320 movs r3, #32
8002c6a: e004 b.n 8002c76 <HAL_ADC_ConfigChannel+0x196>
}
return __builtin_clz(value);
8002c6c: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0
8002c70: fab3 f383 clz r3, r3
8002c74: b2db uxtb r3, r3
8002c76: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
8002c78: 683b ldr r3, [r7, #0]
8002c7a: 681b ldr r3, [r3, #0]
8002c7c: f3c3 0312 ubfx r3, r3, #0, #19
8002c80: 2b00 cmp r3, #0
8002c82: d105 bne.n 8002c90 <HAL_ADC_ConfigChannel+0x1b0>
8002c84: 683b ldr r3, [r7, #0]
8002c86: 681b ldr r3, [r3, #0]
8002c88: 0e9b lsrs r3, r3, #26
8002c8a: f003 031f and.w r3, r3, #31
8002c8e: e018 b.n 8002cc2 <HAL_ADC_ConfigChannel+0x1e2>
8002c90: 683b ldr r3, [r7, #0]
8002c92: 681b ldr r3, [r3, #0]
8002c94: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002c98: f8d7 30b0 ldr.w r3, [r7, #176] ; 0xb0
8002c9c: fa93 f3a3 rbit r3, r3
8002ca0: f8c7 30ac str.w r3, [r7, #172] ; 0xac
return result;
8002ca4: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac
8002ca8: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
if (value == 0U)
8002cac: f8d7 30b4 ldr.w r3, [r7, #180] ; 0xb4
8002cb0: 2b00 cmp r3, #0
8002cb2: d101 bne.n 8002cb8 <HAL_ADC_ConfigChannel+0x1d8>
return 32U;
8002cb4: 2320 movs r3, #32
8002cb6: e004 b.n 8002cc2 <HAL_ADC_ConfigChannel+0x1e2>
return __builtin_clz(value);
8002cb8: f8d7 30b4 ldr.w r3, [r7, #180] ; 0xb4
8002cbc: fab3 f383 clz r3, r3
8002cc0: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
8002cc2: 429a cmp r2, r3
8002cc4: d106 bne.n 8002cd4 <HAL_ADC_ConfigChannel+0x1f4>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
8002cc6: 687b ldr r3, [r7, #4]
8002cc8: 681b ldr r3, [r3, #0]
8002cca: 2200 movs r2, #0
8002ccc: 2100 movs r1, #0
8002cce: 4618 mov r0, r3
8002cd0: f7ff f8ba bl 8001e48 <LL_ADC_SetOffsetState>
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
8002cd4: 687b ldr r3, [r7, #4]
8002cd6: 681b ldr r3, [r3, #0]
8002cd8: 2101 movs r1, #1
8002cda: 4618 mov r0, r3
8002cdc: f7ff f89e bl 8001e1c <LL_ADC_GetOffsetChannel>
8002ce0: 4603 mov r3, r0
8002ce2: f3c3 0312 ubfx r3, r3, #0, #19
8002ce6: 2b00 cmp r3, #0
8002ce8: d10a bne.n 8002d00 <HAL_ADC_ConfigChannel+0x220>
8002cea: 687b ldr r3, [r7, #4]
8002cec: 681b ldr r3, [r3, #0]
8002cee: 2101 movs r1, #1
8002cf0: 4618 mov r0, r3
8002cf2: f7ff f893 bl 8001e1c <LL_ADC_GetOffsetChannel>
8002cf6: 4603 mov r3, r0
8002cf8: 0e9b lsrs r3, r3, #26
8002cfa: f003 021f and.w r2, r3, #31
8002cfe: e01e b.n 8002d3e <HAL_ADC_ConfigChannel+0x25e>
8002d00: 687b ldr r3, [r7, #4]
8002d02: 681b ldr r3, [r3, #0]
8002d04: 2101 movs r1, #1
8002d06: 4618 mov r0, r3
8002d08: f7ff f888 bl 8001e1c <LL_ADC_GetOffsetChannel>
8002d0c: 4603 mov r3, r0
8002d0e: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002d12: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4
8002d16: fa93 f3a3 rbit r3, r3
8002d1a: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
return result;
8002d1e: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0
8002d22: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
if (value == 0U)
8002d26: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8
8002d2a: 2b00 cmp r3, #0
8002d2c: d101 bne.n 8002d32 <HAL_ADC_ConfigChannel+0x252>
return 32U;
8002d2e: 2320 movs r3, #32
8002d30: e004 b.n 8002d3c <HAL_ADC_ConfigChannel+0x25c>
return __builtin_clz(value);
8002d32: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8
8002d36: fab3 f383 clz r3, r3
8002d3a: b2db uxtb r3, r3
8002d3c: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
8002d3e: 683b ldr r3, [r7, #0]
8002d40: 681b ldr r3, [r3, #0]
8002d42: f3c3 0312 ubfx r3, r3, #0, #19
8002d46: 2b00 cmp r3, #0
8002d48: d105 bne.n 8002d56 <HAL_ADC_ConfigChannel+0x276>
8002d4a: 683b ldr r3, [r7, #0]
8002d4c: 681b ldr r3, [r3, #0]
8002d4e: 0e9b lsrs r3, r3, #26
8002d50: f003 031f and.w r3, r3, #31
8002d54: e018 b.n 8002d88 <HAL_ADC_ConfigChannel+0x2a8>
8002d56: 683b ldr r3, [r7, #0]
8002d58: 681b ldr r3, [r3, #0]
8002d5a: f8c7 3098 str.w r3, [r7, #152] ; 0x98
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002d5e: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98
8002d62: fa93 f3a3 rbit r3, r3
8002d66: f8c7 3094 str.w r3, [r7, #148] ; 0x94
return result;
8002d6a: f8d7 3094 ldr.w r3, [r7, #148] ; 0x94
8002d6e: f8c7 309c str.w r3, [r7, #156] ; 0x9c
if (value == 0U)
8002d72: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c
8002d76: 2b00 cmp r3, #0
8002d78: d101 bne.n 8002d7e <HAL_ADC_ConfigChannel+0x29e>
return 32U;
8002d7a: 2320 movs r3, #32
8002d7c: e004 b.n 8002d88 <HAL_ADC_ConfigChannel+0x2a8>
return __builtin_clz(value);
8002d7e: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c
8002d82: fab3 f383 clz r3, r3
8002d86: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
8002d88: 429a cmp r2, r3
8002d8a: d106 bne.n 8002d9a <HAL_ADC_ConfigChannel+0x2ba>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
8002d8c: 687b ldr r3, [r7, #4]
8002d8e: 681b ldr r3, [r3, #0]
8002d90: 2200 movs r2, #0
8002d92: 2101 movs r1, #1
8002d94: 4618 mov r0, r3
8002d96: f7ff f857 bl 8001e48 <LL_ADC_SetOffsetState>
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
8002d9a: 687b ldr r3, [r7, #4]
8002d9c: 681b ldr r3, [r3, #0]
8002d9e: 2102 movs r1, #2
8002da0: 4618 mov r0, r3
8002da2: f7ff f83b bl 8001e1c <LL_ADC_GetOffsetChannel>
8002da6: 4603 mov r3, r0
8002da8: f3c3 0312 ubfx r3, r3, #0, #19
8002dac: 2b00 cmp r3, #0
8002dae: d10a bne.n 8002dc6 <HAL_ADC_ConfigChannel+0x2e6>
8002db0: 687b ldr r3, [r7, #4]
8002db2: 681b ldr r3, [r3, #0]
8002db4: 2102 movs r1, #2
8002db6: 4618 mov r0, r3
8002db8: f7ff f830 bl 8001e1c <LL_ADC_GetOffsetChannel>
8002dbc: 4603 mov r3, r0
8002dbe: 0e9b lsrs r3, r3, #26
8002dc0: f003 021f and.w r2, r3, #31
8002dc4: e01e b.n 8002e04 <HAL_ADC_ConfigChannel+0x324>
8002dc6: 687b ldr r3, [r7, #4]
8002dc8: 681b ldr r3, [r3, #0]
8002dca: 2102 movs r1, #2
8002dcc: 4618 mov r0, r3
8002dce: f7ff f825 bl 8001e1c <LL_ADC_GetOffsetChannel>
8002dd2: 4603 mov r3, r0
8002dd4: f8c7 308c str.w r3, [r7, #140] ; 0x8c
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002dd8: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c
8002ddc: fa93 f3a3 rbit r3, r3
8002de0: f8c7 3088 str.w r3, [r7, #136] ; 0x88
return result;
8002de4: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88
8002de8: f8c7 3090 str.w r3, [r7, #144] ; 0x90
if (value == 0U)
8002dec: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90
8002df0: 2b00 cmp r3, #0
8002df2: d101 bne.n 8002df8 <HAL_ADC_ConfigChannel+0x318>
return 32U;
8002df4: 2320 movs r3, #32
8002df6: e004 b.n 8002e02 <HAL_ADC_ConfigChannel+0x322>
return __builtin_clz(value);
8002df8: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90
8002dfc: fab3 f383 clz r3, r3
8002e00: b2db uxtb r3, r3
8002e02: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
8002e04: 683b ldr r3, [r7, #0]
8002e06: 681b ldr r3, [r3, #0]
8002e08: f3c3 0312 ubfx r3, r3, #0, #19
8002e0c: 2b00 cmp r3, #0
8002e0e: d105 bne.n 8002e1c <HAL_ADC_ConfigChannel+0x33c>
8002e10: 683b ldr r3, [r7, #0]
8002e12: 681b ldr r3, [r3, #0]
8002e14: 0e9b lsrs r3, r3, #26
8002e16: f003 031f and.w r3, r3, #31
8002e1a: e016 b.n 8002e4a <HAL_ADC_ConfigChannel+0x36a>
8002e1c: 683b ldr r3, [r7, #0]
8002e1e: 681b ldr r3, [r3, #0]
8002e20: f8c7 3080 str.w r3, [r7, #128] ; 0x80
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002e24: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80
8002e28: fa93 f3a3 rbit r3, r3
8002e2c: 67fb str r3, [r7, #124] ; 0x7c
return result;
8002e2e: 6ffb ldr r3, [r7, #124] ; 0x7c
8002e30: f8c7 3084 str.w r3, [r7, #132] ; 0x84
if (value == 0U)
8002e34: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84
8002e38: 2b00 cmp r3, #0
8002e3a: d101 bne.n 8002e40 <HAL_ADC_ConfigChannel+0x360>
return 32U;
8002e3c: 2320 movs r3, #32
8002e3e: e004 b.n 8002e4a <HAL_ADC_ConfigChannel+0x36a>
return __builtin_clz(value);
8002e40: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84
8002e44: fab3 f383 clz r3, r3
8002e48: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
8002e4a: 429a cmp r2, r3
8002e4c: d106 bne.n 8002e5c <HAL_ADC_ConfigChannel+0x37c>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
8002e4e: 687b ldr r3, [r7, #4]
8002e50: 681b ldr r3, [r3, #0]
8002e52: 2200 movs r2, #0
8002e54: 2102 movs r1, #2
8002e56: 4618 mov r0, r3
8002e58: f7fe fff6 bl 8001e48 <LL_ADC_SetOffsetState>
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
8002e5c: 687b ldr r3, [r7, #4]
8002e5e: 681b ldr r3, [r3, #0]
8002e60: 2103 movs r1, #3
8002e62: 4618 mov r0, r3
8002e64: f7fe ffda bl 8001e1c <LL_ADC_GetOffsetChannel>
8002e68: 4603 mov r3, r0
8002e6a: f3c3 0312 ubfx r3, r3, #0, #19
8002e6e: 2b00 cmp r3, #0
8002e70: d10a bne.n 8002e88 <HAL_ADC_ConfigChannel+0x3a8>
8002e72: 687b ldr r3, [r7, #4]
8002e74: 681b ldr r3, [r3, #0]
8002e76: 2103 movs r1, #3
8002e78: 4618 mov r0, r3
8002e7a: f7fe ffcf bl 8001e1c <LL_ADC_GetOffsetChannel>
8002e7e: 4603 mov r3, r0
8002e80: 0e9b lsrs r3, r3, #26
8002e82: f003 021f and.w r2, r3, #31
8002e86: e017 b.n 8002eb8 <HAL_ADC_ConfigChannel+0x3d8>
8002e88: 687b ldr r3, [r7, #4]
8002e8a: 681b ldr r3, [r3, #0]
8002e8c: 2103 movs r1, #3
8002e8e: 4618 mov r0, r3
8002e90: f7fe ffc4 bl 8001e1c <LL_ADC_GetOffsetChannel>
8002e94: 4603 mov r3, r0
8002e96: 677b str r3, [r7, #116] ; 0x74
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002e98: 6f7b ldr r3, [r7, #116] ; 0x74
8002e9a: fa93 f3a3 rbit r3, r3
8002e9e: 673b str r3, [r7, #112] ; 0x70
return result;
8002ea0: 6f3b ldr r3, [r7, #112] ; 0x70
8002ea2: 67bb str r3, [r7, #120] ; 0x78
if (value == 0U)
8002ea4: 6fbb ldr r3, [r7, #120] ; 0x78
8002ea6: 2b00 cmp r3, #0
8002ea8: d101 bne.n 8002eae <HAL_ADC_ConfigChannel+0x3ce>
return 32U;
8002eaa: 2320 movs r3, #32
8002eac: e003 b.n 8002eb6 <HAL_ADC_ConfigChannel+0x3d6>
return __builtin_clz(value);
8002eae: 6fbb ldr r3, [r7, #120] ; 0x78
8002eb0: fab3 f383 clz r3, r3
8002eb4: b2db uxtb r3, r3
8002eb6: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
8002eb8: 683b ldr r3, [r7, #0]
8002eba: 681b ldr r3, [r3, #0]
8002ebc: f3c3 0312 ubfx r3, r3, #0, #19
8002ec0: 2b00 cmp r3, #0
8002ec2: d105 bne.n 8002ed0 <HAL_ADC_ConfigChannel+0x3f0>
8002ec4: 683b ldr r3, [r7, #0]
8002ec6: 681b ldr r3, [r3, #0]
8002ec8: 0e9b lsrs r3, r3, #26
8002eca: f003 031f and.w r3, r3, #31
8002ece: e011 b.n 8002ef4 <HAL_ADC_ConfigChannel+0x414>
8002ed0: 683b ldr r3, [r7, #0]
8002ed2: 681b ldr r3, [r3, #0]
8002ed4: 66bb str r3, [r7, #104] ; 0x68
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002ed6: 6ebb ldr r3, [r7, #104] ; 0x68
8002ed8: fa93 f3a3 rbit r3, r3
8002edc: 667b str r3, [r7, #100] ; 0x64
return result;
8002ede: 6e7b ldr r3, [r7, #100] ; 0x64
8002ee0: 66fb str r3, [r7, #108] ; 0x6c
if (value == 0U)
8002ee2: 6efb ldr r3, [r7, #108] ; 0x6c
8002ee4: 2b00 cmp r3, #0
8002ee6: d101 bne.n 8002eec <HAL_ADC_ConfigChannel+0x40c>
return 32U;
8002ee8: 2320 movs r3, #32
8002eea: e003 b.n 8002ef4 <HAL_ADC_ConfigChannel+0x414>
return __builtin_clz(value);
8002eec: 6efb ldr r3, [r7, #108] ; 0x6c
8002eee: fab3 f383 clz r3, r3
8002ef2: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
8002ef4: 429a cmp r2, r3
8002ef6: d106 bne.n 8002f06 <HAL_ADC_ConfigChannel+0x426>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
8002ef8: 687b ldr r3, [r7, #4]
8002efa: 681b ldr r3, [r3, #0]
8002efc: 2200 movs r2, #0
8002efe: 2103 movs r1, #3
8002f00: 4618 mov r0, r3
8002f02: f7fe ffa1 bl 8001e48 <LL_ADC_SetOffsetState>
}
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - Single or differential mode */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
8002f06: 687b ldr r3, [r7, #4]
8002f08: 681b ldr r3, [r3, #0]
8002f0a: 4618 mov r0, r3
8002f0c: f7ff f924 bl 8002158 <LL_ADC_IsEnabled>
8002f10: 4603 mov r3, r0
8002f12: 2b00 cmp r3, #0
8002f14: f040 8140 bne.w 8003198 <HAL_ADC_ConfigChannel+0x6b8>
{
/* Set mode single-ended or differential input of the selected ADC channel */
LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
8002f18: 687b ldr r3, [r7, #4]
8002f1a: 6818 ldr r0, [r3, #0]
8002f1c: 683b ldr r3, [r7, #0]
8002f1e: 6819 ldr r1, [r3, #0]
8002f20: 683b ldr r3, [r7, #0]
8002f22: 68db ldr r3, [r3, #12]
8002f24: 461a mov r2, r3
8002f26: f7ff f871 bl 800200c <LL_ADC_SetChannelSingleDiff>
/* Configuration of differential mode */
if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
8002f2a: 683b ldr r3, [r7, #0]
8002f2c: 68db ldr r3, [r3, #12]
8002f2e: 4a8f ldr r2, [pc, #572] ; (800316c <HAL_ADC_ConfigChannel+0x68c>)
8002f30: 4293 cmp r3, r2
8002f32: f040 8131 bne.w 8003198 <HAL_ADC_ConfigChannel+0x6b8>
{
/* Set sampling time of the selected ADC channel */
/* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002f36: 687b ldr r3, [r7, #4]
8002f38: 6818 ldr r0, [r3, #0]
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
8002f3a: 683b ldr r3, [r7, #0]
8002f3c: 681b ldr r3, [r3, #0]
8002f3e: f3c3 0312 ubfx r3, r3, #0, #19
8002f42: 2b00 cmp r3, #0
8002f44: d10b bne.n 8002f5e <HAL_ADC_ConfigChannel+0x47e>
8002f46: 683b ldr r3, [r7, #0]
8002f48: 681b ldr r3, [r3, #0]
8002f4a: 0e9b lsrs r3, r3, #26
8002f4c: 3301 adds r3, #1
8002f4e: f003 031f and.w r3, r3, #31
8002f52: 2b09 cmp r3, #9
8002f54: bf94 ite ls
8002f56: 2301 movls r3, #1
8002f58: 2300 movhi r3, #0
8002f5a: b2db uxtb r3, r3
8002f5c: e019 b.n 8002f92 <HAL_ADC_ConfigChannel+0x4b2>
8002f5e: 683b ldr r3, [r7, #0]
8002f60: 681b ldr r3, [r3, #0]
8002f62: 65fb str r3, [r7, #92] ; 0x5c
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002f64: 6dfb ldr r3, [r7, #92] ; 0x5c
8002f66: fa93 f3a3 rbit r3, r3
8002f6a: 65bb str r3, [r7, #88] ; 0x58
return result;
8002f6c: 6dbb ldr r3, [r7, #88] ; 0x58
8002f6e: 663b str r3, [r7, #96] ; 0x60
if (value == 0U)
8002f70: 6e3b ldr r3, [r7, #96] ; 0x60
8002f72: 2b00 cmp r3, #0
8002f74: d101 bne.n 8002f7a <HAL_ADC_ConfigChannel+0x49a>
return 32U;
8002f76: 2320 movs r3, #32
8002f78: e003 b.n 8002f82 <HAL_ADC_ConfigChannel+0x4a2>
return __builtin_clz(value);
8002f7a: 6e3b ldr r3, [r7, #96] ; 0x60
8002f7c: fab3 f383 clz r3, r3
8002f80: b2db uxtb r3, r3
8002f82: 3301 adds r3, #1
8002f84: f003 031f and.w r3, r3, #31
8002f88: 2b09 cmp r3, #9
8002f8a: bf94 ite ls
8002f8c: 2301 movls r3, #1
8002f8e: 2300 movhi r3, #0
8002f90: b2db uxtb r3, r3
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002f92: 2b00 cmp r3, #0
8002f94: d079 beq.n 800308a <HAL_ADC_ConfigChannel+0x5aa>
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
8002f96: 683b ldr r3, [r7, #0]
8002f98: 681b ldr r3, [r3, #0]
8002f9a: f3c3 0312 ubfx r3, r3, #0, #19
8002f9e: 2b00 cmp r3, #0
8002fa0: d107 bne.n 8002fb2 <HAL_ADC_ConfigChannel+0x4d2>
8002fa2: 683b ldr r3, [r7, #0]
8002fa4: 681b ldr r3, [r3, #0]
8002fa6: 0e9b lsrs r3, r3, #26
8002fa8: 3301 adds r3, #1
8002faa: 069b lsls r3, r3, #26
8002fac: f003 42f8 and.w r2, r3, #2080374784 ; 0x7c000000
8002fb0: e015 b.n 8002fde <HAL_ADC_ConfigChannel+0x4fe>
8002fb2: 683b ldr r3, [r7, #0]
8002fb4: 681b ldr r3, [r3, #0]
8002fb6: 653b str r3, [r7, #80] ; 0x50
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002fb8: 6d3b ldr r3, [r7, #80] ; 0x50
8002fba: fa93 f3a3 rbit r3, r3
8002fbe: 64fb str r3, [r7, #76] ; 0x4c
return result;
8002fc0: 6cfb ldr r3, [r7, #76] ; 0x4c
8002fc2: 657b str r3, [r7, #84] ; 0x54
if (value == 0U)
8002fc4: 6d7b ldr r3, [r7, #84] ; 0x54
8002fc6: 2b00 cmp r3, #0
8002fc8: d101 bne.n 8002fce <HAL_ADC_ConfigChannel+0x4ee>
return 32U;
8002fca: 2320 movs r3, #32
8002fcc: e003 b.n 8002fd6 <HAL_ADC_ConfigChannel+0x4f6>
return __builtin_clz(value);
8002fce: 6d7b ldr r3, [r7, #84] ; 0x54
8002fd0: fab3 f383 clz r3, r3
8002fd4: b2db uxtb r3, r3
8002fd6: 3301 adds r3, #1
8002fd8: 069b lsls r3, r3, #26
8002fda: f003 42f8 and.w r2, r3, #2080374784 ; 0x7c000000
8002fde: 683b ldr r3, [r7, #0]
8002fe0: 681b ldr r3, [r3, #0]
8002fe2: f3c3 0312 ubfx r3, r3, #0, #19
8002fe6: 2b00 cmp r3, #0
8002fe8: d109 bne.n 8002ffe <HAL_ADC_ConfigChannel+0x51e>
8002fea: 683b ldr r3, [r7, #0]
8002fec: 681b ldr r3, [r3, #0]
8002fee: 0e9b lsrs r3, r3, #26
8002ff0: 3301 adds r3, #1
8002ff2: f003 031f and.w r3, r3, #31
8002ff6: 2101 movs r1, #1
8002ff8: fa01 f303 lsl.w r3, r1, r3
8002ffc: e017 b.n 800302e <HAL_ADC_ConfigChannel+0x54e>
8002ffe: 683b ldr r3, [r7, #0]
8003000: 681b ldr r3, [r3, #0]
8003002: 647b str r3, [r7, #68] ; 0x44
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003004: 6c7b ldr r3, [r7, #68] ; 0x44
8003006: fa93 f3a3 rbit r3, r3
800300a: 643b str r3, [r7, #64] ; 0x40
return result;
800300c: 6c3b ldr r3, [r7, #64] ; 0x40
800300e: 64bb str r3, [r7, #72] ; 0x48
if (value == 0U)
8003010: 6cbb ldr r3, [r7, #72] ; 0x48
8003012: 2b00 cmp r3, #0
8003014: d101 bne.n 800301a <HAL_ADC_ConfigChannel+0x53a>
return 32U;
8003016: 2320 movs r3, #32
8003018: e003 b.n 8003022 <HAL_ADC_ConfigChannel+0x542>
return __builtin_clz(value);
800301a: 6cbb ldr r3, [r7, #72] ; 0x48
800301c: fab3 f383 clz r3, r3
8003020: b2db uxtb r3, r3
8003022: 3301 adds r3, #1
8003024: f003 031f and.w r3, r3, #31
8003028: 2101 movs r1, #1
800302a: fa01 f303 lsl.w r3, r1, r3
800302e: ea42 0103 orr.w r1, r2, r3
8003032: 683b ldr r3, [r7, #0]
8003034: 681b ldr r3, [r3, #0]
8003036: f3c3 0312 ubfx r3, r3, #0, #19
800303a: 2b00 cmp r3, #0
800303c: d10a bne.n 8003054 <HAL_ADC_ConfigChannel+0x574>
800303e: 683b ldr r3, [r7, #0]
8003040: 681b ldr r3, [r3, #0]
8003042: 0e9b lsrs r3, r3, #26
8003044: 3301 adds r3, #1
8003046: f003 021f and.w r2, r3, #31
800304a: 4613 mov r3, r2
800304c: 005b lsls r3, r3, #1
800304e: 4413 add r3, r2
8003050: 051b lsls r3, r3, #20
8003052: e018 b.n 8003086 <HAL_ADC_ConfigChannel+0x5a6>
8003054: 683b ldr r3, [r7, #0]
8003056: 681b ldr r3, [r3, #0]
8003058: 63bb str r3, [r7, #56] ; 0x38
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800305a: 6bbb ldr r3, [r7, #56] ; 0x38
800305c: fa93 f3a3 rbit r3, r3
8003060: 637b str r3, [r7, #52] ; 0x34
return result;
8003062: 6b7b ldr r3, [r7, #52] ; 0x34
8003064: 63fb str r3, [r7, #60] ; 0x3c
if (value == 0U)
8003066: 6bfb ldr r3, [r7, #60] ; 0x3c
8003068: 2b00 cmp r3, #0
800306a: d101 bne.n 8003070 <HAL_ADC_ConfigChannel+0x590>
return 32U;
800306c: 2320 movs r3, #32
800306e: e003 b.n 8003078 <HAL_ADC_ConfigChannel+0x598>
return __builtin_clz(value);
8003070: 6bfb ldr r3, [r7, #60] ; 0x3c
8003072: fab3 f383 clz r3, r3
8003076: b2db uxtb r3, r3
8003078: 3301 adds r3, #1
800307a: f003 021f and.w r2, r3, #31
800307e: 4613 mov r3, r2
8003080: 005b lsls r3, r3, #1
8003082: 4413 add r3, r2
8003084: 051b lsls r3, r3, #20
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8003086: 430b orrs r3, r1
8003088: e081 b.n 800318e <HAL_ADC_ConfigChannel+0x6ae>
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
800308a: 683b ldr r3, [r7, #0]
800308c: 681b ldr r3, [r3, #0]
800308e: f3c3 0312 ubfx r3, r3, #0, #19
8003092: 2b00 cmp r3, #0
8003094: d107 bne.n 80030a6 <HAL_ADC_ConfigChannel+0x5c6>
8003096: 683b ldr r3, [r7, #0]
8003098: 681b ldr r3, [r3, #0]
800309a: 0e9b lsrs r3, r3, #26
800309c: 3301 adds r3, #1
800309e: 069b lsls r3, r3, #26
80030a0: f003 42f8 and.w r2, r3, #2080374784 ; 0x7c000000
80030a4: e015 b.n 80030d2 <HAL_ADC_ConfigChannel+0x5f2>
80030a6: 683b ldr r3, [r7, #0]
80030a8: 681b ldr r3, [r3, #0]
80030aa: 62fb str r3, [r7, #44] ; 0x2c
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80030ac: 6afb ldr r3, [r7, #44] ; 0x2c
80030ae: fa93 f3a3 rbit r3, r3
80030b2: 62bb str r3, [r7, #40] ; 0x28
return result;
80030b4: 6abb ldr r3, [r7, #40] ; 0x28
80030b6: 633b str r3, [r7, #48] ; 0x30
if (value == 0U)
80030b8: 6b3b ldr r3, [r7, #48] ; 0x30
80030ba: 2b00 cmp r3, #0
80030bc: d101 bne.n 80030c2 <HAL_ADC_ConfigChannel+0x5e2>
return 32U;
80030be: 2320 movs r3, #32
80030c0: e003 b.n 80030ca <HAL_ADC_ConfigChannel+0x5ea>
return __builtin_clz(value);
80030c2: 6b3b ldr r3, [r7, #48] ; 0x30
80030c4: fab3 f383 clz r3, r3
80030c8: b2db uxtb r3, r3
80030ca: 3301 adds r3, #1
80030cc: 069b lsls r3, r3, #26
80030ce: f003 42f8 and.w r2, r3, #2080374784 ; 0x7c000000
80030d2: 683b ldr r3, [r7, #0]
80030d4: 681b ldr r3, [r3, #0]
80030d6: f3c3 0312 ubfx r3, r3, #0, #19
80030da: 2b00 cmp r3, #0
80030dc: d109 bne.n 80030f2 <HAL_ADC_ConfigChannel+0x612>
80030de: 683b ldr r3, [r7, #0]
80030e0: 681b ldr r3, [r3, #0]
80030e2: 0e9b lsrs r3, r3, #26
80030e4: 3301 adds r3, #1
80030e6: f003 031f and.w r3, r3, #31
80030ea: 2101 movs r1, #1
80030ec: fa01 f303 lsl.w r3, r1, r3
80030f0: e017 b.n 8003122 <HAL_ADC_ConfigChannel+0x642>
80030f2: 683b ldr r3, [r7, #0]
80030f4: 681b ldr r3, [r3, #0]
80030f6: 623b str r3, [r7, #32]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80030f8: 6a3b ldr r3, [r7, #32]
80030fa: fa93 f3a3 rbit r3, r3
80030fe: 61fb str r3, [r7, #28]
return result;
8003100: 69fb ldr r3, [r7, #28]
8003102: 627b str r3, [r7, #36] ; 0x24
if (value == 0U)
8003104: 6a7b ldr r3, [r7, #36] ; 0x24
8003106: 2b00 cmp r3, #0
8003108: d101 bne.n 800310e <HAL_ADC_ConfigChannel+0x62e>
return 32U;
800310a: 2320 movs r3, #32
800310c: e003 b.n 8003116 <HAL_ADC_ConfigChannel+0x636>
return __builtin_clz(value);
800310e: 6a7b ldr r3, [r7, #36] ; 0x24
8003110: fab3 f383 clz r3, r3
8003114: b2db uxtb r3, r3
8003116: 3301 adds r3, #1
8003118: f003 031f and.w r3, r3, #31
800311c: 2101 movs r1, #1
800311e: fa01 f303 lsl.w r3, r1, r3
8003122: ea42 0103 orr.w r1, r2, r3
8003126: 683b ldr r3, [r7, #0]
8003128: 681b ldr r3, [r3, #0]
800312a: f3c3 0312 ubfx r3, r3, #0, #19
800312e: 2b00 cmp r3, #0
8003130: d10d bne.n 800314e <HAL_ADC_ConfigChannel+0x66e>
8003132: 683b ldr r3, [r7, #0]
8003134: 681b ldr r3, [r3, #0]
8003136: 0e9b lsrs r3, r3, #26
8003138: 3301 adds r3, #1
800313a: f003 021f and.w r2, r3, #31
800313e: 4613 mov r3, r2
8003140: 005b lsls r3, r3, #1
8003142: 4413 add r3, r2
8003144: 3b1e subs r3, #30
8003146: 051b lsls r3, r3, #20
8003148: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
800314c: e01e b.n 800318c <HAL_ADC_ConfigChannel+0x6ac>
800314e: 683b ldr r3, [r7, #0]
8003150: 681b ldr r3, [r3, #0]
8003152: 617b str r3, [r7, #20]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003154: 697b ldr r3, [r7, #20]
8003156: fa93 f3a3 rbit r3, r3
800315a: 613b str r3, [r7, #16]
return result;
800315c: 693b ldr r3, [r7, #16]
800315e: 61bb str r3, [r7, #24]
if (value == 0U)
8003160: 69bb ldr r3, [r7, #24]
8003162: 2b00 cmp r3, #0
8003164: d104 bne.n 8003170 <HAL_ADC_ConfigChannel+0x690>
return 32U;
8003166: 2320 movs r3, #32
8003168: e006 b.n 8003178 <HAL_ADC_ConfigChannel+0x698>
800316a: bf00 nop
800316c: 407f0000 .word 0x407f0000
return __builtin_clz(value);
8003170: 69bb ldr r3, [r7, #24]
8003172: fab3 f383 clz r3, r3
8003176: b2db uxtb r3, r3
8003178: 3301 adds r3, #1
800317a: f003 021f and.w r2, r3, #31
800317e: 4613 mov r3, r2
8003180: 005b lsls r3, r3, #1
8003182: 4413 add r3, r2
8003184: 3b1e subs r3, #30
8003186: 051b lsls r3, r3, #20
8003188: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
LL_ADC_SetChannelSamplingTime(hadc->Instance,
800318c: 430b orrs r3, r1
800318e: 683a ldr r2, [r7, #0]
8003190: 6892 ldr r2, [r2, #8]
8003192: 4619 mov r1, r3
8003194: f7fe ff0e bl 8001fb4 <LL_ADC_SetChannelSamplingTime>
/* If internal channel selected, enable dedicated internal buffers and */
/* paths. */
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit(). */
if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
8003198: 683b ldr r3, [r7, #0]
800319a: 681a ldr r2, [r3, #0]
800319c: 4b3f ldr r3, [pc, #252] ; (800329c <HAL_ADC_ConfigChannel+0x7bc>)
800319e: 4013 ands r3, r2
80031a0: 2b00 cmp r3, #0
80031a2: d071 beq.n 8003288 <HAL_ADC_ConfigChannel+0x7a8>
{
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
80031a4: 483e ldr r0, [pc, #248] ; (80032a0 <HAL_ADC_ConfigChannel+0x7c0>)
80031a6: f7fe fe07 bl 8001db8 <LL_ADC_GetCommonPathInternalCh>
80031aa: f8c7 00c4 str.w r0, [r7, #196] ; 0xc4
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
if (((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5))
80031ae: 683b ldr r3, [r7, #0]
80031b0: 681b ldr r3, [r3, #0]
80031b2: 4a3c ldr r2, [pc, #240] ; (80032a4 <HAL_ADC_ConfigChannel+0x7c4>)
80031b4: 4293 cmp r3, r2
80031b6: d004 beq.n 80031c2 <HAL_ADC_ConfigChannel+0x6e2>
80031b8: 683b ldr r3, [r7, #0]
80031ba: 681b ldr r3, [r3, #0]
80031bc: 4a3a ldr r2, [pc, #232] ; (80032a8 <HAL_ADC_ConfigChannel+0x7c8>)
80031be: 4293 cmp r3, r2
80031c0: d127 bne.n 8003212 <HAL_ADC_ConfigChannel+0x732>
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
80031c2: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4
80031c6: f403 0300 and.w r3, r3, #8388608 ; 0x800000
80031ca: 2b00 cmp r3, #0
80031cc: d121 bne.n 8003212 <HAL_ADC_ConfigChannel+0x732>
{
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
80031ce: 687b ldr r3, [r7, #4]
80031d0: 681b ldr r3, [r3, #0]
80031d2: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000
80031d6: d157 bne.n 8003288 <HAL_ADC_ConfigChannel+0x7a8>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
80031d8: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4
80031dc: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
80031e0: 4619 mov r1, r3
80031e2: 482f ldr r0, [pc, #188] ; (80032a0 <HAL_ADC_ConfigChannel+0x7c0>)
80031e4: f7fe fdd5 bl 8001d92 <LL_ADC_SetCommonPathInternalCh>
/* Delay for temperature sensor stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
80031e8: 4b30 ldr r3, [pc, #192] ; (80032ac <HAL_ADC_ConfigChannel+0x7cc>)
80031ea: 681b ldr r3, [r3, #0]
80031ec: 099b lsrs r3, r3, #6
80031ee: 4a30 ldr r2, [pc, #192] ; (80032b0 <HAL_ADC_ConfigChannel+0x7d0>)
80031f0: fba2 2303 umull r2, r3, r2, r3
80031f4: 099b lsrs r3, r3, #6
80031f6: 1c5a adds r2, r3, #1
80031f8: 4613 mov r3, r2
80031fa: 005b lsls r3, r3, #1
80031fc: 4413 add r3, r2
80031fe: 009b lsls r3, r3, #2
8003200: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8003202: e002 b.n 800320a <HAL_ADC_ConfigChannel+0x72a>
{
wait_loop_index--;
8003204: 68fb ldr r3, [r7, #12]
8003206: 3b01 subs r3, #1
8003208: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
800320a: 68fb ldr r3, [r7, #12]
800320c: 2b00 cmp r3, #0
800320e: d1f9 bne.n 8003204 <HAL_ADC_ConfigChannel+0x724>
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
8003210: e03a b.n 8003288 <HAL_ADC_ConfigChannel+0x7a8>
}
}
}
else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
8003212: 683b ldr r3, [r7, #0]
8003214: 681b ldr r3, [r3, #0]
8003216: 4a27 ldr r2, [pc, #156] ; (80032b4 <HAL_ADC_ConfigChannel+0x7d4>)
8003218: 4293 cmp r3, r2
800321a: d113 bne.n 8003244 <HAL_ADC_ConfigChannel+0x764>
800321c: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4
8003220: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
8003224: 2b00 cmp r3, #0
8003226: d10d bne.n 8003244 <HAL_ADC_ConfigChannel+0x764>
{
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
8003228: 687b ldr r3, [r7, #4]
800322a: 681b ldr r3, [r3, #0]
800322c: 4a22 ldr r2, [pc, #136] ; (80032b8 <HAL_ADC_ConfigChannel+0x7d8>)
800322e: 4293 cmp r3, r2
8003230: d02a beq.n 8003288 <HAL_ADC_ConfigChannel+0x7a8>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
8003232: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4
8003236: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
800323a: 4619 mov r1, r3
800323c: 4818 ldr r0, [pc, #96] ; (80032a0 <HAL_ADC_ConfigChannel+0x7c0>)
800323e: f7fe fda8 bl 8001d92 <LL_ADC_SetCommonPathInternalCh>
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
8003242: e021 b.n 8003288 <HAL_ADC_ConfigChannel+0x7a8>
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
}
}
else if ((sConfig->Channel == ADC_CHANNEL_VREFINT)
8003244: 683b ldr r3, [r7, #0]
8003246: 681b ldr r3, [r3, #0]
8003248: 4a1c ldr r2, [pc, #112] ; (80032bc <HAL_ADC_ConfigChannel+0x7dc>)
800324a: 4293 cmp r3, r2
800324c: d11c bne.n 8003288 <HAL_ADC_ConfigChannel+0x7a8>
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
800324e: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4
8003252: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8003256: 2b00 cmp r3, #0
8003258: d116 bne.n 8003288 <HAL_ADC_ConfigChannel+0x7a8>
{
if (ADC_VREFINT_INSTANCE(hadc))
800325a: 687b ldr r3, [r7, #4]
800325c: 681b ldr r3, [r3, #0]
800325e: 4a16 ldr r2, [pc, #88] ; (80032b8 <HAL_ADC_ConfigChannel+0x7d8>)
8003260: 4293 cmp r3, r2
8003262: d011 beq.n 8003288 <HAL_ADC_ConfigChannel+0x7a8>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
8003264: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4
8003268: f443 0380 orr.w r3, r3, #4194304 ; 0x400000
800326c: 4619 mov r1, r3
800326e: 480c ldr r0, [pc, #48] ; (80032a0 <HAL_ADC_ConfigChannel+0x7c0>)
8003270: f7fe fd8f bl 8001d92 <LL_ADC_SetCommonPathInternalCh>
8003274: e008 b.n 8003288 <HAL_ADC_ConfigChannel+0x7a8>
/* channel could be done on neither of the channel configuration structure */
/* parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8003276: 687b ldr r3, [r7, #4]
8003278: 6ddb ldr r3, [r3, #92] ; 0x5c
800327a: f043 0220 orr.w r2, r3, #32
800327e: 687b ldr r3, [r7, #4]
8003280: 65da str r2, [r3, #92] ; 0x5c
tmp_hal_status = HAL_ERROR;
8003282: 2301 movs r3, #1
8003284: f887 30d7 strb.w r3, [r7, #215] ; 0xd7
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8003288: 687b ldr r3, [r7, #4]
800328a: 2200 movs r2, #0
800328c: f883 2058 strb.w r2, [r3, #88] ; 0x58
/* Return function status */
return tmp_hal_status;
8003290: f897 30d7 ldrb.w r3, [r7, #215] ; 0xd7
}
8003294: 4618 mov r0, r3
8003296: 37d8 adds r7, #216 ; 0xd8
8003298: 46bd mov sp, r7
800329a: bd80 pop {r7, pc}
800329c: 80080000 .word 0x80080000
80032a0: 50000300 .word 0x50000300
80032a4: c3210000 .word 0xc3210000
80032a8: 90c00010 .word 0x90c00010
80032ac: 20000004 .word 0x20000004
80032b0: 053e2d63 .word 0x053e2d63
80032b4: c7520000 .word 0xc7520000
80032b8: 50000100 .word 0x50000100
80032bc: cb840000 .word 0xcb840000
080032c0 <ADC_Enable>:
* and voltage regulator must be enabled (done into HAL_ADC_Init()).
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
{
80032c0: b580 push {r7, lr}
80032c2: b084 sub sp, #16
80032c4: af00 add r7, sp, #0
80032c6: 6078 str r0, [r7, #4]
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
/* causes: ADC clock not running, ...). */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
80032c8: 687b ldr r3, [r7, #4]
80032ca: 681b ldr r3, [r3, #0]
80032cc: 4618 mov r0, r3
80032ce: f7fe ff43 bl 8002158 <LL_ADC_IsEnabled>
80032d2: 4603 mov r3, r0
80032d4: 2b00 cmp r3, #0
80032d6: d14d bne.n 8003374 <ADC_Enable+0xb4>
{
/* Check if conditions to enable the ADC are fulfilled */
if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
80032d8: 687b ldr r3, [r7, #4]
80032da: 681b ldr r3, [r3, #0]
80032dc: 689a ldr r2, [r3, #8]
80032de: 4b28 ldr r3, [pc, #160] ; (8003380 <ADC_Enable+0xc0>)
80032e0: 4013 ands r3, r2
80032e2: 2b00 cmp r3, #0
80032e4: d00d beq.n 8003302 <ADC_Enable+0x42>
| ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80032e6: 687b ldr r3, [r7, #4]
80032e8: 6ddb ldr r3, [r3, #92] ; 0x5c
80032ea: f043 0210 orr.w r2, r3, #16
80032ee: 687b ldr r3, [r7, #4]
80032f0: 65da str r2, [r3, #92] ; 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80032f2: 687b ldr r3, [r7, #4]
80032f4: 6e1b ldr r3, [r3, #96] ; 0x60
80032f6: f043 0201 orr.w r2, r3, #1
80032fa: 687b ldr r3, [r7, #4]
80032fc: 661a str r2, [r3, #96] ; 0x60
return HAL_ERROR;
80032fe: 2301 movs r3, #1
8003300: e039 b.n 8003376 <ADC_Enable+0xb6>
}
/* Enable the ADC peripheral */
LL_ADC_Enable(hadc->Instance);
8003302: 687b ldr r3, [r7, #4]
8003304: 681b ldr r3, [r3, #0]
8003306: 4618 mov r0, r3
8003308: f7fe ff12 bl 8002130 <LL_ADC_Enable>
/* Wait for ADC effectively enabled */
tickstart = HAL_GetTick();
800330c: f7fe fd22 bl 8001d54 <HAL_GetTick>
8003310: 60f8 str r0, [r7, #12]
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
8003312: e028 b.n 8003366 <ADC_Enable+0xa6>
The workaround is to continue setting ADEN until ADRDY is becomes 1.
Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
4 ADC clock cycle duration */
/* Note: Test of ADC enabled required due to hardware constraint to */
/* not enable ADC if already enabled. */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
8003314: 687b ldr r3, [r7, #4]
8003316: 681b ldr r3, [r3, #0]
8003318: 4618 mov r0, r3
800331a: f7fe ff1d bl 8002158 <LL_ADC_IsEnabled>
800331e: 4603 mov r3, r0
8003320: 2b00 cmp r3, #0
8003322: d104 bne.n 800332e <ADC_Enable+0x6e>
{
LL_ADC_Enable(hadc->Instance);
8003324: 687b ldr r3, [r7, #4]
8003326: 681b ldr r3, [r3, #0]
8003328: 4618 mov r0, r3
800332a: f7fe ff01 bl 8002130 <LL_ADC_Enable>
}
if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
800332e: f7fe fd11 bl 8001d54 <HAL_GetTick>
8003332: 4602 mov r2, r0
8003334: 68fb ldr r3, [r7, #12]
8003336: 1ad3 subs r3, r2, r3
8003338: 2b02 cmp r3, #2
800333a: d914 bls.n 8003366 <ADC_Enable+0xa6>
{
/* New check to avoid false timeout detection in case of preemption */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
800333c: 687b ldr r3, [r7, #4]
800333e: 681b ldr r3, [r3, #0]
8003340: 681b ldr r3, [r3, #0]
8003342: f003 0301 and.w r3, r3, #1
8003346: 2b01 cmp r3, #1
8003348: d00d beq.n 8003366 <ADC_Enable+0xa6>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800334a: 687b ldr r3, [r7, #4]
800334c: 6ddb ldr r3, [r3, #92] ; 0x5c
800334e: f043 0210 orr.w r2, r3, #16
8003352: 687b ldr r3, [r7, #4]
8003354: 65da str r2, [r3, #92] ; 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8003356: 687b ldr r3, [r7, #4]
8003358: 6e1b ldr r3, [r3, #96] ; 0x60
800335a: f043 0201 orr.w r2, r3, #1
800335e: 687b ldr r3, [r7, #4]
8003360: 661a str r2, [r3, #96] ; 0x60
return HAL_ERROR;
8003362: 2301 movs r3, #1
8003364: e007 b.n 8003376 <ADC_Enable+0xb6>
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
8003366: 687b ldr r3, [r7, #4]
8003368: 681b ldr r3, [r3, #0]
800336a: 681b ldr r3, [r3, #0]
800336c: f003 0301 and.w r3, r3, #1
8003370: 2b01 cmp r3, #1
8003372: d1cf bne.n 8003314 <ADC_Enable+0x54>
}
}
}
/* Return HAL status */
return HAL_OK;
8003374: 2300 movs r3, #0
}
8003376: 4618 mov r0, r3
8003378: 3710 adds r7, #16
800337a: 46bd mov sp, r7
800337c: bd80 pop {r7, pc}
800337e: bf00 nop
8003380: 8000003f .word 0x8000003f
08003384 <ADC_DMAConvCplt>:
* @brief DMA transfer complete callback.
* @param hdma pointer to DMA handle.
* @retval None
*/
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
{
8003384: b580 push {r7, lr}
8003386: b084 sub sp, #16
8003388: af00 add r7, sp, #0
800338a: 6078 str r0, [r7, #4]
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
800338c: 687b ldr r3, [r7, #4]
800338e: 6a9b ldr r3, [r3, #40] ; 0x28
8003390: 60fb str r3, [r7, #12]
/* Update state machine on conversion status if not in error state */
if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
8003392: 68fb ldr r3, [r7, #12]
8003394: 6ddb ldr r3, [r3, #92] ; 0x5c
8003396: f003 0350 and.w r3, r3, #80 ; 0x50
800339a: 2b00 cmp r3, #0
800339c: d14b bne.n 8003436 <ADC_DMAConvCplt+0xb2>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
800339e: 68fb ldr r3, [r7, #12]
80033a0: 6ddb ldr r3, [r3, #92] ; 0x5c
80033a2: f443 7200 orr.w r2, r3, #512 ; 0x200
80033a6: 68fb ldr r3, [r7, #12]
80033a8: 65da str r2, [r3, #92] ; 0x5c
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going */
/* to disable interruption. */
/* Is it the end of the regular sequence ? */
if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
80033aa: 68fb ldr r3, [r7, #12]
80033ac: 681b ldr r3, [r3, #0]
80033ae: 681b ldr r3, [r3, #0]
80033b0: f003 0308 and.w r3, r3, #8
80033b4: 2b00 cmp r3, #0
80033b6: d021 beq.n 80033fc <ADC_DMAConvCplt+0x78>
{
/* Are conversions software-triggered ? */
if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
80033b8: 68fb ldr r3, [r7, #12]
80033ba: 681b ldr r3, [r3, #0]
80033bc: 4618 mov r0, r3
80033be: f7fe fda7 bl 8001f10 <LL_ADC_REG_IsTriggerSourceSWStart>
80033c2: 4603 mov r3, r0
80033c4: 2b00 cmp r3, #0
80033c6: d032 beq.n 800342e <ADC_DMAConvCplt+0xaa>
{
/* Is CONT bit set ? */
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL)
80033c8: 68fb ldr r3, [r7, #12]
80033ca: 681b ldr r3, [r3, #0]
80033cc: 68db ldr r3, [r3, #12]
80033ce: f403 5300 and.w r3, r3, #8192 ; 0x2000
80033d2: 2b00 cmp r3, #0
80033d4: d12b bne.n 800342e <ADC_DMAConvCplt+0xaa>
{
/* CONT bit is not set, no more conversions expected */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
80033d6: 68fb ldr r3, [r7, #12]
80033d8: 6ddb ldr r3, [r3, #92] ; 0x5c
80033da: f423 7280 bic.w r2, r3, #256 ; 0x100
80033de: 68fb ldr r3, [r7, #12]
80033e0: 65da str r2, [r3, #92] ; 0x5c
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
80033e2: 68fb ldr r3, [r7, #12]
80033e4: 6ddb ldr r3, [r3, #92] ; 0x5c
80033e6: f403 5380 and.w r3, r3, #4096 ; 0x1000
80033ea: 2b00 cmp r3, #0
80033ec: d11f bne.n 800342e <ADC_DMAConvCplt+0xaa>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
80033ee: 68fb ldr r3, [r7, #12]
80033f0: 6ddb ldr r3, [r3, #92] ; 0x5c
80033f2: f043 0201 orr.w r2, r3, #1
80033f6: 68fb ldr r3, [r7, #12]
80033f8: 65da str r2, [r3, #92] ; 0x5c
80033fa: e018 b.n 800342e <ADC_DMAConvCplt+0xaa>
}
else
{
/* DMA End of Transfer interrupt was triggered but conversions sequence
is not over. If DMACFG is set to 0, conversions are stopped. */
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL)
80033fc: 68fb ldr r3, [r7, #12]
80033fe: 681b ldr r3, [r3, #0]
8003400: 68db ldr r3, [r3, #12]
8003402: f003 0302 and.w r3, r3, #2
8003406: 2b00 cmp r3, #0
8003408: d111 bne.n 800342e <ADC_DMAConvCplt+0xaa>
{
/* DMACFG bit is not set, conversions are stopped. */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
800340a: 68fb ldr r3, [r7, #12]
800340c: 6ddb ldr r3, [r3, #92] ; 0x5c
800340e: f423 7280 bic.w r2, r3, #256 ; 0x100
8003412: 68fb ldr r3, [r7, #12]
8003414: 65da str r2, [r3, #92] ; 0x5c
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
8003416: 68fb ldr r3, [r7, #12]
8003418: 6ddb ldr r3, [r3, #92] ; 0x5c
800341a: f403 5380 and.w r3, r3, #4096 ; 0x1000
800341e: 2b00 cmp r3, #0
8003420: d105 bne.n 800342e <ADC_DMAConvCplt+0xaa>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
8003422: 68fb ldr r3, [r7, #12]
8003424: 6ddb ldr r3, [r3, #92] ; 0x5c
8003426: f043 0201 orr.w r2, r3, #1
800342a: 68fb ldr r3, [r7, #12]
800342c: 65da str r2, [r3, #92] ; 0x5c
/* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvCpltCallback(hadc);
#else
HAL_ADC_ConvCpltCallback(hadc);
800342e: 68f8 ldr r0, [r7, #12]
8003430: f7fd f938 bl 80006a4 <HAL_ADC_ConvCpltCallback>
{
/* Call ADC DMA error callback */
hadc->DMA_Handle->XferErrorCallback(hdma);
}
}
}
8003434: e00e b.n 8003454 <ADC_DMAConvCplt+0xd0>
if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
8003436: 68fb ldr r3, [r7, #12]
8003438: 6ddb ldr r3, [r3, #92] ; 0x5c
800343a: f003 0310 and.w r3, r3, #16
800343e: 2b00 cmp r3, #0
8003440: d003 beq.n 800344a <ADC_DMAConvCplt+0xc6>
HAL_ADC_ErrorCallback(hadc);
8003442: 68f8 ldr r0, [r7, #12]
8003444: f7ff fb42 bl 8002acc <HAL_ADC_ErrorCallback>
}
8003448: e004 b.n 8003454 <ADC_DMAConvCplt+0xd0>
hadc->DMA_Handle->XferErrorCallback(hdma);
800344a: 68fb ldr r3, [r7, #12]
800344c: 6d5b ldr r3, [r3, #84] ; 0x54
800344e: 6b5b ldr r3, [r3, #52] ; 0x34
8003450: 6878 ldr r0, [r7, #4]
8003452: 4798 blx r3
}
8003454: bf00 nop
8003456: 3710 adds r7, #16
8003458: 46bd mov sp, r7
800345a: bd80 pop {r7, pc}
0800345c <ADC_DMAHalfConvCplt>:
* @brief DMA half transfer complete callback.
* @param hdma pointer to DMA handle.
* @retval None
*/
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
{
800345c: b580 push {r7, lr}
800345e: b084 sub sp, #16
8003460: af00 add r7, sp, #0
8003462: 6078 str r0, [r7, #4]
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
8003464: 687b ldr r3, [r7, #4]
8003466: 6a9b ldr r3, [r3, #40] ; 0x28
8003468: 60fb str r3, [r7, #12]
/* Half conversion callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvHalfCpltCallback(hadc);
#else
HAL_ADC_ConvHalfCpltCallback(hadc);
800346a: 68f8 ldr r0, [r7, #12]
800346c: f7ff fb1a bl 8002aa4 <HAL_ADC_ConvHalfCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
8003470: bf00 nop
8003472: 3710 adds r7, #16
8003474: 46bd mov sp, r7
8003476: bd80 pop {r7, pc}
08003478 <ADC_DMAError>:
* @brief DMA error callback.
* @param hdma pointer to DMA handle.
* @retval None
*/
void ADC_DMAError(DMA_HandleTypeDef *hdma)
{
8003478: b580 push {r7, lr}
800347a: b084 sub sp, #16
800347c: af00 add r7, sp, #0
800347e: 6078 str r0, [r7, #4]
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
8003480: 687b ldr r3, [r7, #4]
8003482: 6a9b ldr r3, [r3, #40] ; 0x28
8003484: 60fb str r3, [r7, #12]
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
8003486: 68fb ldr r3, [r7, #12]
8003488: 6ddb ldr r3, [r3, #92] ; 0x5c
800348a: f043 0240 orr.w r2, r3, #64 ; 0x40
800348e: 68fb ldr r3, [r7, #12]
8003490: 65da str r2, [r3, #92] ; 0x5c
/* Set ADC error code to DMA error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
8003492: 68fb ldr r3, [r7, #12]
8003494: 6e1b ldr r3, [r3, #96] ; 0x60
8003496: f043 0204 orr.w r2, r3, #4
800349a: 68fb ldr r3, [r7, #12]
800349c: 661a str r2, [r3, #96] ; 0x60
/* Error callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ErrorCallback(hadc);
#else
HAL_ADC_ErrorCallback(hadc);
800349e: 68f8 ldr r0, [r7, #12]
80034a0: f7ff fb14 bl 8002acc <HAL_ADC_ErrorCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
80034a4: bf00 nop
80034a6: 3710 adds r7, #16
80034a8: 46bd mov sp, r7
80034aa: bd80 pop {r7, pc}
080034ac <LL_ADC_IsEnabled>:
{
80034ac: b480 push {r7}
80034ae: b083 sub sp, #12
80034b0: af00 add r7, sp, #0
80034b2: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
80034b4: 687b ldr r3, [r7, #4]
80034b6: 689b ldr r3, [r3, #8]
80034b8: f003 0301 and.w r3, r3, #1
80034bc: 2b01 cmp r3, #1
80034be: d101 bne.n 80034c4 <LL_ADC_IsEnabled+0x18>
80034c0: 2301 movs r3, #1
80034c2: e000 b.n 80034c6 <LL_ADC_IsEnabled+0x1a>
80034c4: 2300 movs r3, #0
}
80034c6: 4618 mov r0, r3
80034c8: 370c adds r7, #12
80034ca: 46bd mov sp, r7
80034cc: f85d 7b04 ldr.w r7, [sp], #4
80034d0: 4770 bx lr
080034d2 <LL_ADC_REG_IsConversionOngoing>:
{
80034d2: b480 push {r7}
80034d4: b083 sub sp, #12
80034d6: af00 add r7, sp, #0
80034d8: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
80034da: 687b ldr r3, [r7, #4]
80034dc: 689b ldr r3, [r3, #8]
80034de: f003 0304 and.w r3, r3, #4
80034e2: 2b04 cmp r3, #4
80034e4: d101 bne.n 80034ea <LL_ADC_REG_IsConversionOngoing+0x18>
80034e6: 2301 movs r3, #1
80034e8: e000 b.n 80034ec <LL_ADC_REG_IsConversionOngoing+0x1a>
80034ea: 2300 movs r3, #0
}
80034ec: 4618 mov r0, r3
80034ee: 370c adds r7, #12
80034f0: 46bd mov sp, r7
80034f2: f85d 7b04 ldr.w r7, [sp], #4
80034f6: 4770 bx lr
080034f8 <HAL_ADCEx_InjectedConvCpltCallback>:
* @brief Injected conversion complete callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
{
80034f8: b480 push {r7}
80034fa: b083 sub sp, #12
80034fc: af00 add r7, sp, #0
80034fe: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
*/
}
8003500: bf00 nop
8003502: 370c adds r7, #12
8003504: 46bd mov sp, r7
8003506: f85d 7b04 ldr.w r7, [sp], #4
800350a: 4770 bx lr
0800350c <HAL_ADCEx_InjectedQueueOverflowCallback>:
contexts).
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
{
800350c: b480 push {r7}
800350e: b083 sub sp, #12
8003510: af00 add r7, sp, #0
8003512: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
*/
}
8003514: bf00 nop
8003516: 370c adds r7, #12
8003518: 46bd mov sp, r7
800351a: f85d 7b04 ldr.w r7, [sp], #4
800351e: 4770 bx lr
08003520 <HAL_ADCEx_LevelOutOfWindow2Callback>:
* @brief Analog watchdog 2 callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
{
8003520: b480 push {r7}
8003522: b083 sub sp, #12
8003524: af00 add r7, sp, #0
8003526: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
*/
}
8003528: bf00 nop
800352a: 370c adds r7, #12
800352c: 46bd mov sp, r7
800352e: f85d 7b04 ldr.w r7, [sp], #4
8003532: 4770 bx lr
08003534 <HAL_ADCEx_LevelOutOfWindow3Callback>:
* @brief Analog watchdog 3 callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
{
8003534: b480 push {r7}
8003536: b083 sub sp, #12
8003538: af00 add r7, sp, #0
800353a: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
*/
}
800353c: bf00 nop
800353e: 370c adds r7, #12
8003540: 46bd mov sp, r7
8003542: f85d 7b04 ldr.w r7, [sp], #4
8003546: 4770 bx lr
08003548 <HAL_ADCEx_EndOfSamplingCallback>:
* @brief End Of Sampling callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
{
8003548: b480 push {r7}
800354a: b083 sub sp, #12
800354c: af00 add r7, sp, #0
800354e: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
*/
}
8003550: bf00 nop
8003552: 370c adds r7, #12
8003554: 46bd mov sp, r7
8003556: f85d 7b04 ldr.w r7, [sp], #4
800355a: 4770 bx lr
0800355c <HAL_ADCEx_MultiModeConfigChannel>:
* @param hadc Master ADC handle
* @param multimode Structure of ADC multimode configuration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
{
800355c: b590 push {r4, r7, lr}
800355e: b0a1 sub sp, #132 ; 0x84
8003560: af00 add r7, sp, #0
8003562: 6078 str r0, [r7, #4]
8003564: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8003566: 2300 movs r3, #0
8003568: f887 307f strb.w r3, [r7, #127] ; 0x7f
assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode));
assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
}
/* Process locked */
__HAL_LOCK(hadc);
800356c: 687b ldr r3, [r7, #4]
800356e: f893 3058 ldrb.w r3, [r3, #88] ; 0x58
8003572: 2b01 cmp r3, #1
8003574: d101 bne.n 800357a <HAL_ADCEx_MultiModeConfigChannel+0x1e>
8003576: 2302 movs r3, #2
8003578: e08b b.n 8003692 <HAL_ADCEx_MultiModeConfigChannel+0x136>
800357a: 687b ldr r3, [r7, #4]
800357c: 2201 movs r2, #1
800357e: f883 2058 strb.w r2, [r3, #88] ; 0x58
/* Temporary handle minimum initialization */
__HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
8003582: 2300 movs r3, #0
8003584: 667b str r3, [r7, #100] ; 0x64
ADC_CLEAR_ERRORCODE(&tmphadcSlave);
8003586: 2300 movs r3, #0
8003588: 66bb str r3, [r7, #104] ; 0x68
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
800358a: 687b ldr r3, [r7, #4]
800358c: 681b ldr r3, [r3, #0]
800358e: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000
8003592: d102 bne.n 800359a <HAL_ADCEx_MultiModeConfigChannel+0x3e>
8003594: 4b41 ldr r3, [pc, #260] ; (800369c <HAL_ADCEx_MultiModeConfigChannel+0x140>)
8003596: 60bb str r3, [r7, #8]
8003598: e001 b.n 800359e <HAL_ADCEx_MultiModeConfigChannel+0x42>
800359a: 2300 movs r3, #0
800359c: 60bb str r3, [r7, #8]
if (tmphadcSlave.Instance == NULL)
800359e: 68bb ldr r3, [r7, #8]
80035a0: 2b00 cmp r3, #0
80035a2: d10b bne.n 80035bc <HAL_ADCEx_MultiModeConfigChannel+0x60>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
80035a4: 687b ldr r3, [r7, #4]
80035a6: 6ddb ldr r3, [r3, #92] ; 0x5c
80035a8: f043 0220 orr.w r2, r3, #32
80035ac: 687b ldr r3, [r7, #4]
80035ae: 65da str r2, [r3, #92] ; 0x5c
/* Process unlocked */
__HAL_UNLOCK(hadc);
80035b0: 687b ldr r3, [r7, #4]
80035b2: 2200 movs r2, #0
80035b4: f883 2058 strb.w r2, [r3, #88] ; 0x58
return HAL_ERROR;
80035b8: 2301 movs r3, #1
80035ba: e06a b.n 8003692 <HAL_ADCEx_MultiModeConfigChannel+0x136>
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Multimode DMA configuration */
/* - Multimode DMA mode */
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
80035bc: 68bb ldr r3, [r7, #8]
80035be: 4618 mov r0, r3
80035c0: f7ff ff87 bl 80034d2 <LL_ADC_REG_IsConversionOngoing>
80035c4: 67b8 str r0, [r7, #120] ; 0x78
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
80035c6: 687b ldr r3, [r7, #4]
80035c8: 681b ldr r3, [r3, #0]
80035ca: 4618 mov r0, r3
80035cc: f7ff ff81 bl 80034d2 <LL_ADC_REG_IsConversionOngoing>
80035d0: 4603 mov r3, r0
80035d2: 2b00 cmp r3, #0
80035d4: d14c bne.n 8003670 <HAL_ADCEx_MultiModeConfigChannel+0x114>
&& (tmphadcSlave_conversion_on_going == 0UL))
80035d6: 6fbb ldr r3, [r7, #120] ; 0x78
80035d8: 2b00 cmp r3, #0
80035da: d149 bne.n 8003670 <HAL_ADCEx_MultiModeConfigChannel+0x114>
{
/* Pointer to the common control register */
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
80035dc: 4b30 ldr r3, [pc, #192] ; (80036a0 <HAL_ADCEx_MultiModeConfigChannel+0x144>)
80035de: 677b str r3, [r7, #116] ; 0x74
/* If multimode is selected, configure all multimode parameters. */
/* Otherwise, reset multimode parameters (can be used in case of */
/* transition from multimode to independent mode). */
if (multimode->Mode != ADC_MODE_INDEPENDENT)
80035e0: 683b ldr r3, [r7, #0]
80035e2: 681b ldr r3, [r3, #0]
80035e4: 2b00 cmp r3, #0
80035e6: d028 beq.n 800363a <HAL_ADCEx_MultiModeConfigChannel+0xde>
{
MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
80035e8: 6f7b ldr r3, [r7, #116] ; 0x74
80035ea: 689b ldr r3, [r3, #8]
80035ec: f423 4260 bic.w r2, r3, #57344 ; 0xe000
80035f0: 683b ldr r3, [r7, #0]
80035f2: 6859 ldr r1, [r3, #4]
80035f4: 687b ldr r3, [r7, #4]
80035f6: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
80035fa: 035b lsls r3, r3, #13
80035fc: 430b orrs r3, r1
80035fe: 431a orrs r2, r3
8003600: 6f7b ldr r3, [r7, #116] ; 0x74
8003602: 609a str r2, [r3, #8]
/* from 1 to 10 clock cycles for 10 bits, */
/* from 1 to 8 clock cycles for 8 bits */
/* from 1 to 6 clock cycles for 6 bits */
/* If a higher delay is selected, it will be clipped to maximum delay */
/* range */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
8003604: f04f 40a0 mov.w r0, #1342177280 ; 0x50000000
8003608: f7ff ff50 bl 80034ac <LL_ADC_IsEnabled>
800360c: 4604 mov r4, r0
800360e: 4823 ldr r0, [pc, #140] ; (800369c <HAL_ADCEx_MultiModeConfigChannel+0x140>)
8003610: f7ff ff4c bl 80034ac <LL_ADC_IsEnabled>
8003614: 4603 mov r3, r0
8003616: 4323 orrs r3, r4
8003618: 2b00 cmp r3, #0
800361a: d133 bne.n 8003684 <HAL_ADCEx_MultiModeConfigChannel+0x128>
{
MODIFY_REG(tmpADC_Common->CCR,
800361c: 6f7b ldr r3, [r7, #116] ; 0x74
800361e: 689b ldr r3, [r3, #8]
8003620: f423 6371 bic.w r3, r3, #3856 ; 0xf10
8003624: f023 030f bic.w r3, r3, #15
8003628: 683a ldr r2, [r7, #0]
800362a: 6811 ldr r1, [r2, #0]
800362c: 683a ldr r2, [r7, #0]
800362e: 6892 ldr r2, [r2, #8]
8003630: 430a orrs r2, r1
8003632: 431a orrs r2, r3
8003634: 6f7b ldr r3, [r7, #116] ; 0x74
8003636: 609a str r2, [r3, #8]
if (multimode->Mode != ADC_MODE_INDEPENDENT)
8003638: e024 b.n 8003684 <HAL_ADCEx_MultiModeConfigChannel+0x128>
);
}
}
else /* ADC_MODE_INDEPENDENT */
{
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
800363a: 6f7b ldr r3, [r7, #116] ; 0x74
800363c: 689b ldr r3, [r3, #8]
800363e: f423 4260 bic.w r2, r3, #57344 ; 0xe000
8003642: 6f7b ldr r3, [r7, #116] ; 0x74
8003644: 609a str r2, [r3, #8]
/* Parameters that can be updated only when ADC is disabled: */
/* - Multimode mode selection */
/* - Multimode delay */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
8003646: f04f 40a0 mov.w r0, #1342177280 ; 0x50000000
800364a: f7ff ff2f bl 80034ac <LL_ADC_IsEnabled>
800364e: 4604 mov r4, r0
8003650: 4812 ldr r0, [pc, #72] ; (800369c <HAL_ADCEx_MultiModeConfigChannel+0x140>)
8003652: f7ff ff2b bl 80034ac <LL_ADC_IsEnabled>
8003656: 4603 mov r3, r0
8003658: 4323 orrs r3, r4
800365a: 2b00 cmp r3, #0
800365c: d112 bne.n 8003684 <HAL_ADCEx_MultiModeConfigChannel+0x128>
{
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
800365e: 6f7b ldr r3, [r7, #116] ; 0x74
8003660: 689b ldr r3, [r3, #8]
8003662: f423 6371 bic.w r3, r3, #3856 ; 0xf10
8003666: f023 030f bic.w r3, r3, #15
800366a: 6f7a ldr r2, [r7, #116] ; 0x74
800366c: 6093 str r3, [r2, #8]
if (multimode->Mode != ADC_MODE_INDEPENDENT)
800366e: e009 b.n 8003684 <HAL_ADCEx_MultiModeConfigChannel+0x128>
/* If one of the ADC sharing the same common group is enabled, no update */
/* could be done on neither of the multimode structure parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8003670: 687b ldr r3, [r7, #4]
8003672: 6ddb ldr r3, [r3, #92] ; 0x5c
8003674: f043 0220 orr.w r2, r3, #32
8003678: 687b ldr r3, [r7, #4]
800367a: 65da str r2, [r3, #92] ; 0x5c
tmp_hal_status = HAL_ERROR;
800367c: 2301 movs r3, #1
800367e: f887 307f strb.w r3, [r7, #127] ; 0x7f
8003682: e000 b.n 8003686 <HAL_ADCEx_MultiModeConfigChannel+0x12a>
if (multimode->Mode != ADC_MODE_INDEPENDENT)
8003684: bf00 nop
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8003686: 687b ldr r3, [r7, #4]
8003688: 2200 movs r2, #0
800368a: f883 2058 strb.w r2, [r3, #88] ; 0x58
/* Return function status */
return tmp_hal_status;
800368e: f897 307f ldrb.w r3, [r7, #127] ; 0x7f
}
8003692: 4618 mov r0, r3
8003694: 3784 adds r7, #132 ; 0x84
8003696: 46bd mov sp, r7
8003698: bd90 pop {r4, r7, pc}
800369a: bf00 nop
800369c: 50000100 .word 0x50000100
80036a0: 50000300 .word 0x50000300
080036a4 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80036a4: b480 push {r7}
80036a6: b085 sub sp, #20
80036a8: af00 add r7, sp, #0
80036aa: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80036ac: 687b ldr r3, [r7, #4]
80036ae: f003 0307 and.w r3, r3, #7
80036b2: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
80036b4: 4b0c ldr r3, [pc, #48] ; (80036e8 <__NVIC_SetPriorityGrouping+0x44>)
80036b6: 68db ldr r3, [r3, #12]
80036b8: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
80036ba: 68ba ldr r2, [r7, #8]
80036bc: f64f 03ff movw r3, #63743 ; 0xf8ff
80036c0: 4013 ands r3, r2
80036c2: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
80036c4: 68fb ldr r3, [r7, #12]
80036c6: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
80036c8: 68bb ldr r3, [r7, #8]
80036ca: 4313 orrs r3, r2
reg_value = (reg_value |
80036cc: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
80036d0: f443 3300 orr.w r3, r3, #131072 ; 0x20000
80036d4: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
80036d6: 4a04 ldr r2, [pc, #16] ; (80036e8 <__NVIC_SetPriorityGrouping+0x44>)
80036d8: 68bb ldr r3, [r7, #8]
80036da: 60d3 str r3, [r2, #12]
}
80036dc: bf00 nop
80036de: 3714 adds r7, #20
80036e0: 46bd mov sp, r7
80036e2: f85d 7b04 ldr.w r7, [sp], #4
80036e6: 4770 bx lr
80036e8: e000ed00 .word 0xe000ed00
080036ec <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80036ec: b480 push {r7}
80036ee: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80036f0: 4b04 ldr r3, [pc, #16] ; (8003704 <__NVIC_GetPriorityGrouping+0x18>)
80036f2: 68db ldr r3, [r3, #12]
80036f4: 0a1b lsrs r3, r3, #8
80036f6: f003 0307 and.w r3, r3, #7
}
80036fa: 4618 mov r0, r3
80036fc: 46bd mov sp, r7
80036fe: f85d 7b04 ldr.w r7, [sp], #4
8003702: 4770 bx lr
8003704: e000ed00 .word 0xe000ed00
08003708 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8003708: b480 push {r7}
800370a: b083 sub sp, #12
800370c: af00 add r7, sp, #0
800370e: 4603 mov r3, r0
8003710: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8003712: f997 3007 ldrsb.w r3, [r7, #7]
8003716: 2b00 cmp r3, #0
8003718: db0b blt.n 8003732 <__NVIC_EnableIRQ+0x2a>
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
800371a: 79fb ldrb r3, [r7, #7]
800371c: f003 021f and.w r2, r3, #31
8003720: 4907 ldr r1, [pc, #28] ; (8003740 <__NVIC_EnableIRQ+0x38>)
8003722: f997 3007 ldrsb.w r3, [r7, #7]
8003726: 095b lsrs r3, r3, #5
8003728: 2001 movs r0, #1
800372a: fa00 f202 lsl.w r2, r0, r2
800372e: f841 2023 str.w r2, [r1, r3, lsl #2]
__COMPILER_BARRIER();
}
}
8003732: bf00 nop
8003734: 370c adds r7, #12
8003736: 46bd mov sp, r7
8003738: f85d 7b04 ldr.w r7, [sp], #4
800373c: 4770 bx lr
800373e: bf00 nop
8003740: e000e100 .word 0xe000e100
08003744 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8003744: b480 push {r7}
8003746: b083 sub sp, #12
8003748: af00 add r7, sp, #0
800374a: 4603 mov r3, r0
800374c: 6039 str r1, [r7, #0]
800374e: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8003750: f997 3007 ldrsb.w r3, [r7, #7]
8003754: 2b00 cmp r3, #0
8003756: db0a blt.n 800376e <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8003758: 683b ldr r3, [r7, #0]
800375a: b2da uxtb r2, r3
800375c: 490c ldr r1, [pc, #48] ; (8003790 <__NVIC_SetPriority+0x4c>)
800375e: f997 3007 ldrsb.w r3, [r7, #7]
8003762: 0112 lsls r2, r2, #4
8003764: b2d2 uxtb r2, r2
8003766: 440b add r3, r1
8003768: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
800376c: e00a b.n 8003784 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800376e: 683b ldr r3, [r7, #0]
8003770: b2da uxtb r2, r3
8003772: 4908 ldr r1, [pc, #32] ; (8003794 <__NVIC_SetPriority+0x50>)
8003774: 79fb ldrb r3, [r7, #7]
8003776: f003 030f and.w r3, r3, #15
800377a: 3b04 subs r3, #4
800377c: 0112 lsls r2, r2, #4
800377e: b2d2 uxtb r2, r2
8003780: 440b add r3, r1
8003782: 761a strb r2, [r3, #24]
}
8003784: bf00 nop
8003786: 370c adds r7, #12
8003788: 46bd mov sp, r7
800378a: f85d 7b04 ldr.w r7, [sp], #4
800378e: 4770 bx lr
8003790: e000e100 .word 0xe000e100
8003794: e000ed00 .word 0xe000ed00
08003798 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8003798: b480 push {r7}
800379a: b089 sub sp, #36 ; 0x24
800379c: af00 add r7, sp, #0
800379e: 60f8 str r0, [r7, #12]
80037a0: 60b9 str r1, [r7, #8]
80037a2: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80037a4: 68fb ldr r3, [r7, #12]
80037a6: f003 0307 and.w r3, r3, #7
80037aa: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80037ac: 69fb ldr r3, [r7, #28]
80037ae: f1c3 0307 rsb r3, r3, #7
80037b2: 2b04 cmp r3, #4
80037b4: bf28 it cs
80037b6: 2304 movcs r3, #4
80037b8: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80037ba: 69fb ldr r3, [r7, #28]
80037bc: 3304 adds r3, #4
80037be: 2b06 cmp r3, #6
80037c0: d902 bls.n 80037c8 <NVIC_EncodePriority+0x30>
80037c2: 69fb ldr r3, [r7, #28]
80037c4: 3b03 subs r3, #3
80037c6: e000 b.n 80037ca <NVIC_EncodePriority+0x32>
80037c8: 2300 movs r3, #0
80037ca: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80037cc: f04f 32ff mov.w r2, #4294967295
80037d0: 69bb ldr r3, [r7, #24]
80037d2: fa02 f303 lsl.w r3, r2, r3
80037d6: 43da mvns r2, r3
80037d8: 68bb ldr r3, [r7, #8]
80037da: 401a ands r2, r3
80037dc: 697b ldr r3, [r7, #20]
80037de: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
80037e0: f04f 31ff mov.w r1, #4294967295
80037e4: 697b ldr r3, [r7, #20]
80037e6: fa01 f303 lsl.w r3, r1, r3
80037ea: 43d9 mvns r1, r3
80037ec: 687b ldr r3, [r7, #4]
80037ee: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80037f0: 4313 orrs r3, r2
);
}
80037f2: 4618 mov r0, r3
80037f4: 3724 adds r7, #36 ; 0x24
80037f6: 46bd mov sp, r7
80037f8: f85d 7b04 ldr.w r7, [sp], #4
80037fc: 4770 bx lr
...
08003800 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8003800: b580 push {r7, lr}
8003802: b082 sub sp, #8
8003804: af00 add r7, sp, #0
8003806: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8003808: 687b ldr r3, [r7, #4]
800380a: 3b01 subs r3, #1
800380c: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
8003810: d301 bcc.n 8003816 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8003812: 2301 movs r3, #1
8003814: e00f b.n 8003836 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8003816: 4a0a ldr r2, [pc, #40] ; (8003840 <SysTick_Config+0x40>)
8003818: 687b ldr r3, [r7, #4]
800381a: 3b01 subs r3, #1
800381c: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
800381e: 210f movs r1, #15
8003820: f04f 30ff mov.w r0, #4294967295
8003824: f7ff ff8e bl 8003744 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8003828: 4b05 ldr r3, [pc, #20] ; (8003840 <SysTick_Config+0x40>)
800382a: 2200 movs r2, #0
800382c: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
800382e: 4b04 ldr r3, [pc, #16] ; (8003840 <SysTick_Config+0x40>)
8003830: 2207 movs r2, #7
8003832: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8003834: 2300 movs r3, #0
}
8003836: 4618 mov r0, r3
8003838: 3708 adds r7, #8
800383a: 46bd mov sp, r7
800383c: bd80 pop {r7, pc}
800383e: bf00 nop
8003840: e000e010 .word 0xe000e010
08003844 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8003844: b580 push {r7, lr}
8003846: b082 sub sp, #8
8003848: af00 add r7, sp, #0
800384a: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
800384c: 6878 ldr r0, [r7, #4]
800384e: f7ff ff29 bl 80036a4 <__NVIC_SetPriorityGrouping>
}
8003852: bf00 nop
8003854: 3708 adds r7, #8
8003856: 46bd mov sp, r7
8003858: bd80 pop {r7, pc}
0800385a <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
800385a: b580 push {r7, lr}
800385c: b086 sub sp, #24
800385e: af00 add r7, sp, #0
8003860: 4603 mov r3, r0
8003862: 60b9 str r1, [r7, #8]
8003864: 607a str r2, [r7, #4]
8003866: 73fb strb r3, [r7, #15]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8003868: f7ff ff40 bl 80036ec <__NVIC_GetPriorityGrouping>
800386c: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
800386e: 687a ldr r2, [r7, #4]
8003870: 68b9 ldr r1, [r7, #8]
8003872: 6978 ldr r0, [r7, #20]
8003874: f7ff ff90 bl 8003798 <NVIC_EncodePriority>
8003878: 4602 mov r2, r0
800387a: f997 300f ldrsb.w r3, [r7, #15]
800387e: 4611 mov r1, r2
8003880: 4618 mov r0, r3
8003882: f7ff ff5f bl 8003744 <__NVIC_SetPriority>
}
8003886: bf00 nop
8003888: 3718 adds r7, #24
800388a: 46bd mov sp, r7
800388c: bd80 pop {r7, pc}
0800388e <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
800388e: b580 push {r7, lr}
8003890: b082 sub sp, #8
8003892: af00 add r7, sp, #0
8003894: 4603 mov r3, r0
8003896: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8003898: f997 3007 ldrsb.w r3, [r7, #7]
800389c: 4618 mov r0, r3
800389e: f7ff ff33 bl 8003708 <__NVIC_EnableIRQ>
}
80038a2: bf00 nop
80038a4: 3708 adds r7, #8
80038a6: 46bd mov sp, r7
80038a8: bd80 pop {r7, pc}
080038aa <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80038aa: b580 push {r7, lr}
80038ac: b082 sub sp, #8
80038ae: af00 add r7, sp, #0
80038b0: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
80038b2: 6878 ldr r0, [r7, #4]
80038b4: f7ff ffa4 bl 8003800 <SysTick_Config>
80038b8: 4603 mov r3, r0
}
80038ba: 4618 mov r0, r3
80038bc: 3708 adds r7, #8
80038be: 46bd mov sp, r7
80038c0: bd80 pop {r7, pc}
...
080038c4 <HAL_DMA_Init>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
80038c4: b580 push {r7, lr}
80038c6: b084 sub sp, #16
80038c8: af00 add r7, sp, #0
80038ca: 6078 str r0, [r7, #4]
uint32_t tmp;
/* Check the DMA handle allocation */
if (hdma == NULL)
80038cc: 687b ldr r3, [r7, #4]
80038ce: 2b00 cmp r3, #0
80038d0: d101 bne.n 80038d6 <HAL_DMA_Init+0x12>
{
return HAL_ERROR;
80038d2: 2301 movs r3, #1
80038d4: e08d b.n 80039f2 <HAL_DMA_Init+0x12e>
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
/* Compute the channel index */
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
80038d6: 687b ldr r3, [r7, #4]
80038d8: 681b ldr r3, [r3, #0]
80038da: 461a mov r2, r3
80038dc: 4b47 ldr r3, [pc, #284] ; (80039fc <HAL_DMA_Init+0x138>)
80038de: 429a cmp r2, r3
80038e0: d80f bhi.n 8003902 <HAL_DMA_Init+0x3e>
{
/* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
80038e2: 687b ldr r3, [r7, #4]
80038e4: 681b ldr r3, [r3, #0]
80038e6: 461a mov r2, r3
80038e8: 4b45 ldr r3, [pc, #276] ; (8003a00 <HAL_DMA_Init+0x13c>)
80038ea: 4413 add r3, r2
80038ec: 4a45 ldr r2, [pc, #276] ; (8003a04 <HAL_DMA_Init+0x140>)
80038ee: fba2 2303 umull r2, r3, r2, r3
80038f2: 091b lsrs r3, r3, #4
80038f4: 009a lsls r2, r3, #2
80038f6: 687b ldr r3, [r7, #4]
80038f8: 645a str r2, [r3, #68] ; 0x44
hdma->DmaBaseAddress = DMA1;
80038fa: 687b ldr r3, [r7, #4]
80038fc: 4a42 ldr r2, [pc, #264] ; (8003a08 <HAL_DMA_Init+0x144>)
80038fe: 641a str r2, [r3, #64] ; 0x40
8003900: e00e b.n 8003920 <HAL_DMA_Init+0x5c>
}
else
{
/* DMA2 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
8003902: 687b ldr r3, [r7, #4]
8003904: 681b ldr r3, [r3, #0]
8003906: 461a mov r2, r3
8003908: 4b40 ldr r3, [pc, #256] ; (8003a0c <HAL_DMA_Init+0x148>)
800390a: 4413 add r3, r2
800390c: 4a3d ldr r2, [pc, #244] ; (8003a04 <HAL_DMA_Init+0x140>)
800390e: fba2 2303 umull r2, r3, r2, r3
8003912: 091b lsrs r3, r3, #4
8003914: 009a lsls r2, r3, #2
8003916: 687b ldr r3, [r7, #4]
8003918: 645a str r2, [r3, #68] ; 0x44
hdma->DmaBaseAddress = DMA2;
800391a: 687b ldr r3, [r7, #4]
800391c: 4a3c ldr r2, [pc, #240] ; (8003a10 <HAL_DMA_Init+0x14c>)
800391e: 641a str r2, [r3, #64] ; 0x40
}
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
8003920: 687b ldr r3, [r7, #4]
8003922: 2202 movs r2, #2
8003924: f883 2025 strb.w r2, [r3, #37] ; 0x25
/* Get the CR register value */
tmp = hdma->Instance->CCR;
8003928: 687b ldr r3, [r7, #4]
800392a: 681b ldr r3, [r3, #0]
800392c: 681b ldr r3, [r3, #0]
800392e: 60fb str r3, [r7, #12]
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE |
8003930: 68fb ldr r3, [r7, #12]
8003932: f423 43ff bic.w r3, r3, #32640 ; 0x7f80
8003936: f023 0370 bic.w r3, r3, #112 ; 0x70
800393a: 60fb str r3, [r7, #12]
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC |
DMA_CCR_DIR | DMA_CCR_MEM2MEM));
/* Prepare the DMA Channel configuration */
tmp |= hdma->Init.Direction |
800393c: 687b ldr r3, [r7, #4]
800393e: 689a ldr r2, [r3, #8]
hdma->Init.PeriphInc | hdma->Init.MemInc |
8003940: 687b ldr r3, [r7, #4]
8003942: 68db ldr r3, [r3, #12]
tmp |= hdma->Init.Direction |
8003944: 431a orrs r2, r3
hdma->Init.PeriphInc | hdma->Init.MemInc |
8003946: 687b ldr r3, [r7, #4]
8003948: 691b ldr r3, [r3, #16]
800394a: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
800394c: 687b ldr r3, [r7, #4]
800394e: 695b ldr r3, [r3, #20]
hdma->Init.PeriphInc | hdma->Init.MemInc |
8003950: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
8003952: 687b ldr r3, [r7, #4]
8003954: 699b ldr r3, [r3, #24]
8003956: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
8003958: 687b ldr r3, [r7, #4]
800395a: 69db ldr r3, [r3, #28]
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
800395c: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
800395e: 687b ldr r3, [r7, #4]
8003960: 6a1b ldr r3, [r3, #32]
8003962: 4313 orrs r3, r2
tmp |= hdma->Init.Direction |
8003964: 68fa ldr r2, [r7, #12]
8003966: 4313 orrs r3, r2
8003968: 60fb str r3, [r7, #12]
/* Write to DMA Channel CR register */
hdma->Instance->CCR = tmp;
800396a: 687b ldr r3, [r7, #4]
800396c: 681b ldr r3, [r3, #0]
800396e: 68fa ldr r2, [r7, #12]
8003970: 601a str r2, [r3, #0]
/* Initialize parameters for DMAMUX channel :
DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
*/
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
8003972: 6878 ldr r0, [r7, #4]
8003974: f000 f9b6 bl 8003ce4 <DMA_CalcDMAMUXChannelBaseAndMask>
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
8003978: 687b ldr r3, [r7, #4]
800397a: 689b ldr r3, [r3, #8]
800397c: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
8003980: d102 bne.n 8003988 <HAL_DMA_Init+0xc4>
{
/* if memory to memory force the request to 0*/
hdma->Init.Request = DMA_REQUEST_MEM2MEM;
8003982: 687b ldr r3, [r7, #4]
8003984: 2200 movs r2, #0
8003986: 605a str r2, [r3, #4]
}
/* Set peripheral request to DMAMUX channel */
hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
8003988: 687b ldr r3, [r7, #4]
800398a: 685a ldr r2, [r3, #4]
800398c: 687b ldr r3, [r7, #4]
800398e: 6c9b ldr r3, [r3, #72] ; 0x48
8003990: b2d2 uxtb r2, r2
8003992: 601a str r2, [r3, #0]
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8003994: 687b ldr r3, [r7, #4]
8003996: 6cdb ldr r3, [r3, #76] ; 0x4c
8003998: 687a ldr r2, [r7, #4]
800399a: 6d12 ldr r2, [r2, #80] ; 0x50
800399c: 605a str r2, [r3, #4]
if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
800399e: 687b ldr r3, [r7, #4]
80039a0: 685b ldr r3, [r3, #4]
80039a2: 2b00 cmp r3, #0
80039a4: d010 beq.n 80039c8 <HAL_DMA_Init+0x104>
80039a6: 687b ldr r3, [r7, #4]
80039a8: 685b ldr r3, [r3, #4]
80039aa: 2b04 cmp r3, #4
80039ac: d80c bhi.n 80039c8 <HAL_DMA_Init+0x104>
{
/* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
*/
DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
80039ae: 6878 ldr r0, [r7, #4]
80039b0: f000 f9d6 bl 8003d60 <DMA_CalcDMAMUXRequestGenBaseAndMask>
/* Reset the DMAMUX request generator register*/
hdma->DMAmuxRequestGen->RGCR = 0U;
80039b4: 687b ldr r3, [r7, #4]
80039b6: 6d5b ldr r3, [r3, #84] ; 0x54
80039b8: 2200 movs r2, #0
80039ba: 601a str r2, [r3, #0]
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
80039bc: 687b ldr r3, [r7, #4]
80039be: 6d9b ldr r3, [r3, #88] ; 0x58
80039c0: 687a ldr r2, [r7, #4]
80039c2: 6dd2 ldr r2, [r2, #92] ; 0x5c
80039c4: 605a str r2, [r3, #4]
80039c6: e008 b.n 80039da <HAL_DMA_Init+0x116>
}
else
{
hdma->DMAmuxRequestGen = 0U;
80039c8: 687b ldr r3, [r7, #4]
80039ca: 2200 movs r2, #0
80039cc: 655a str r2, [r3, #84] ; 0x54
hdma->DMAmuxRequestGenStatus = 0U;
80039ce: 687b ldr r3, [r7, #4]
80039d0: 2200 movs r2, #0
80039d2: 659a str r2, [r3, #88] ; 0x58
hdma->DMAmuxRequestGenStatusMask = 0U;
80039d4: 687b ldr r3, [r7, #4]
80039d6: 2200 movs r2, #0
80039d8: 65da str r2, [r3, #92] ; 0x5c
}
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
80039da: 687b ldr r3, [r7, #4]
80039dc: 2200 movs r2, #0
80039de: 63da str r2, [r3, #60] ; 0x3c
/* Initialize the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
80039e0: 687b ldr r3, [r7, #4]
80039e2: 2201 movs r2, #1
80039e4: f883 2025 strb.w r2, [r3, #37] ; 0x25
/* Allocate lock resource and initialize it */
hdma->Lock = HAL_UNLOCKED;
80039e8: 687b ldr r3, [r7, #4]
80039ea: 2200 movs r2, #0
80039ec: f883 2024 strb.w r2, [r3, #36] ; 0x24
return HAL_OK;
80039f0: 2300 movs r3, #0
}
80039f2: 4618 mov r0, r3
80039f4: 3710 adds r7, #16
80039f6: 46bd mov sp, r7
80039f8: bd80 pop {r7, pc}
80039fa: bf00 nop
80039fc: 40020407 .word 0x40020407
8003a00: bffdfff8 .word 0xbffdfff8
8003a04: cccccccd .word 0xcccccccd
8003a08: 40020000 .word 0x40020000
8003a0c: bffdfbf8 .word 0xbffdfbf8
8003a10: 40020400 .word 0x40020400
08003a14 <HAL_DMA_Start_IT>:
* @param DataLength The length of data to be transferred from source to destination (up to 256Kbytes-1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
uint32_t DataLength)
{
8003a14: b580 push {r7, lr}
8003a16: b086 sub sp, #24
8003a18: af00 add r7, sp, #0
8003a1a: 60f8 str r0, [r7, #12]
8003a1c: 60b9 str r1, [r7, #8]
8003a1e: 607a str r2, [r7, #4]
8003a20: 603b str r3, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
8003a22: 2300 movs r3, #0
8003a24: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Process locked */
__HAL_LOCK(hdma);
8003a26: 68fb ldr r3, [r7, #12]
8003a28: f893 3024 ldrb.w r3, [r3, #36] ; 0x24
8003a2c: 2b01 cmp r3, #1
8003a2e: d101 bne.n 8003a34 <HAL_DMA_Start_IT+0x20>
8003a30: 2302 movs r3, #2
8003a32: e066 b.n 8003b02 <HAL_DMA_Start_IT+0xee>
8003a34: 68fb ldr r3, [r7, #12]
8003a36: 2201 movs r2, #1
8003a38: f883 2024 strb.w r2, [r3, #36] ; 0x24
if (HAL_DMA_STATE_READY == hdma->State)
8003a3c: 68fb ldr r3, [r7, #12]
8003a3e: f893 3025 ldrb.w r3, [r3, #37] ; 0x25
8003a42: b2db uxtb r3, r3
8003a44: 2b01 cmp r3, #1
8003a46: d155 bne.n 8003af4 <HAL_DMA_Start_IT+0xe0>
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
8003a48: 68fb ldr r3, [r7, #12]
8003a4a: 2202 movs r2, #2
8003a4c: f883 2025 strb.w r2, [r3, #37] ; 0x25
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8003a50: 68fb ldr r3, [r7, #12]
8003a52: 2200 movs r2, #0
8003a54: 63da str r2, [r3, #60] ; 0x3c
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
8003a56: 68fb ldr r3, [r7, #12]
8003a58: 681b ldr r3, [r3, #0]
8003a5a: 681a ldr r2, [r3, #0]
8003a5c: 68fb ldr r3, [r7, #12]
8003a5e: 681b ldr r3, [r3, #0]
8003a60: f022 0201 bic.w r2, r2, #1
8003a64: 601a str r2, [r3, #0]
/* Configure the source, destination address and the data length & clear flags*/
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
8003a66: 683b ldr r3, [r7, #0]
8003a68: 687a ldr r2, [r7, #4]
8003a6a: 68b9 ldr r1, [r7, #8]
8003a6c: 68f8 ldr r0, [r7, #12]
8003a6e: f000 f8fb bl 8003c68 <DMA_SetConfig>
/* Enable the transfer complete interrupt */
/* Enable the transfer Error interrupt */
if (NULL != hdma->XferHalfCpltCallback)
8003a72: 68fb ldr r3, [r7, #12]
8003a74: 6b1b ldr r3, [r3, #48] ; 0x30
8003a76: 2b00 cmp r3, #0
8003a78: d008 beq.n 8003a8c <HAL_DMA_Start_IT+0x78>
{
/* Enable the Half transfer complete interrupt as well */
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8003a7a: 68fb ldr r3, [r7, #12]
8003a7c: 681b ldr r3, [r3, #0]
8003a7e: 681a ldr r2, [r3, #0]
8003a80: 68fb ldr r3, [r7, #12]
8003a82: 681b ldr r3, [r3, #0]
8003a84: f042 020e orr.w r2, r2, #14
8003a88: 601a str r2, [r3, #0]
8003a8a: e00f b.n 8003aac <HAL_DMA_Start_IT+0x98>
}
else
{
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
8003a8c: 68fb ldr r3, [r7, #12]
8003a8e: 681b ldr r3, [r3, #0]
8003a90: 681a ldr r2, [r3, #0]
8003a92: 68fb ldr r3, [r7, #12]
8003a94: 681b ldr r3, [r3, #0]
8003a96: f022 0204 bic.w r2, r2, #4
8003a9a: 601a str r2, [r3, #0]
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
8003a9c: 68fb ldr r3, [r7, #12]
8003a9e: 681b ldr r3, [r3, #0]
8003aa0: 681a ldr r2, [r3, #0]
8003aa2: 68fb ldr r3, [r7, #12]
8003aa4: 681b ldr r3, [r3, #0]
8003aa6: f042 020a orr.w r2, r2, #10
8003aaa: 601a str r2, [r3, #0]
}
/* Check if DMAMUX Synchronization is enabled*/
if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
8003aac: 68fb ldr r3, [r7, #12]
8003aae: 6c9b ldr r3, [r3, #72] ; 0x48
8003ab0: 681b ldr r3, [r3, #0]
8003ab2: f403 3380 and.w r3, r3, #65536 ; 0x10000
8003ab6: 2b00 cmp r3, #0
8003ab8: d007 beq.n 8003aca <HAL_DMA_Start_IT+0xb6>
{
/* Enable DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
8003aba: 68fb ldr r3, [r7, #12]
8003abc: 6c9b ldr r3, [r3, #72] ; 0x48
8003abe: 681a ldr r2, [r3, #0]
8003ac0: 68fb ldr r3, [r7, #12]
8003ac2: 6c9b ldr r3, [r3, #72] ; 0x48
8003ac4: f442 7280 orr.w r2, r2, #256 ; 0x100
8003ac8: 601a str r2, [r3, #0]
}
if (hdma->DMAmuxRequestGen != 0U)
8003aca: 68fb ldr r3, [r7, #12]
8003acc: 6d5b ldr r3, [r3, #84] ; 0x54
8003ace: 2b00 cmp r3, #0
8003ad0: d007 beq.n 8003ae2 <HAL_DMA_Start_IT+0xce>
{
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
/* enable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
8003ad2: 68fb ldr r3, [r7, #12]
8003ad4: 6d5b ldr r3, [r3, #84] ; 0x54
8003ad6: 681a ldr r2, [r3, #0]
8003ad8: 68fb ldr r3, [r7, #12]
8003ada: 6d5b ldr r3, [r3, #84] ; 0x54
8003adc: f442 7280 orr.w r2, r2, #256 ; 0x100
8003ae0: 601a str r2, [r3, #0]
}
/* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma);
8003ae2: 68fb ldr r3, [r7, #12]
8003ae4: 681b ldr r3, [r3, #0]
8003ae6: 681a ldr r2, [r3, #0]
8003ae8: 68fb ldr r3, [r7, #12]
8003aea: 681b ldr r3, [r3, #0]
8003aec: f042 0201 orr.w r2, r2, #1
8003af0: 601a str r2, [r3, #0]
8003af2: e005 b.n 8003b00 <HAL_DMA_Start_IT+0xec>
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003af4: 68fb ldr r3, [r7, #12]
8003af6: 2200 movs r2, #0
8003af8: f883 2024 strb.w r2, [r3, #36] ; 0x24
/* Remain BUSY */
status = HAL_BUSY;
8003afc: 2302 movs r3, #2
8003afe: 75fb strb r3, [r7, #23]
}
return status;
8003b00: 7dfb ldrb r3, [r7, #23]
}
8003b02: 4618 mov r0, r3
8003b04: 3718 adds r7, #24
8003b06: 46bd mov sp, r7
8003b08: bd80 pop {r7, pc}
08003b0a <HAL_DMA_IRQHandler>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval None
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
8003b0a: b580 push {r7, lr}
8003b0c: b084 sub sp, #16
8003b0e: af00 add r7, sp, #0
8003b10: 6078 str r0, [r7, #4]
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
8003b12: 687b ldr r3, [r7, #4]
8003b14: 6c1b ldr r3, [r3, #64] ; 0x40
8003b16: 681b ldr r3, [r3, #0]
8003b18: 60fb str r3, [r7, #12]
uint32_t source_it = hdma->Instance->CCR;
8003b1a: 687b ldr r3, [r7, #4]
8003b1c: 681b ldr r3, [r3, #0]
8003b1e: 681b ldr r3, [r3, #0]
8003b20: 60bb str r3, [r7, #8]
/* Half Transfer Complete Interrupt management ******************************/
if ((0U != (flag_it & ((uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU)))) && (0U != (source_it & DMA_IT_HT)))
8003b22: 687b ldr r3, [r7, #4]
8003b24: 6c5b ldr r3, [r3, #68] ; 0x44
8003b26: f003 031f and.w r3, r3, #31
8003b2a: 2204 movs r2, #4
8003b2c: 409a lsls r2, r3
8003b2e: 68fb ldr r3, [r7, #12]
8003b30: 4013 ands r3, r2
8003b32: 2b00 cmp r3, #0
8003b34: d026 beq.n 8003b84 <HAL_DMA_IRQHandler+0x7a>
8003b36: 68bb ldr r3, [r7, #8]
8003b38: f003 0304 and.w r3, r3, #4
8003b3c: 2b00 cmp r3, #0
8003b3e: d021 beq.n 8003b84 <HAL_DMA_IRQHandler+0x7a>
{
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
8003b40: 687b ldr r3, [r7, #4]
8003b42: 681b ldr r3, [r3, #0]
8003b44: 681b ldr r3, [r3, #0]
8003b46: f003 0320 and.w r3, r3, #32
8003b4a: 2b00 cmp r3, #0
8003b4c: d107 bne.n 8003b5e <HAL_DMA_IRQHandler+0x54>
{
/* Disable the half transfer interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
8003b4e: 687b ldr r3, [r7, #4]
8003b50: 681b ldr r3, [r3, #0]
8003b52: 681a ldr r2, [r3, #0]
8003b54: 687b ldr r3, [r7, #4]
8003b56: 681b ldr r3, [r3, #0]
8003b58: f022 0204 bic.w r2, r2, #4
8003b5c: 601a str r2, [r3, #0]
}
/* Clear the half transfer complete flag */
hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1FU));
8003b5e: 687b ldr r3, [r7, #4]
8003b60: 6c5b ldr r3, [r3, #68] ; 0x44
8003b62: f003 021f and.w r2, r3, #31
8003b66: 687b ldr r3, [r7, #4]
8003b68: 6c1b ldr r3, [r3, #64] ; 0x40
8003b6a: 2104 movs r1, #4
8003b6c: fa01 f202 lsl.w r2, r1, r2
8003b70: 605a str r2, [r3, #4]
/* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */
if (hdma->XferHalfCpltCallback != NULL)
8003b72: 687b ldr r3, [r7, #4]
8003b74: 6b1b ldr r3, [r3, #48] ; 0x30
8003b76: 2b00 cmp r3, #0
8003b78: d071 beq.n 8003c5e <HAL_DMA_IRQHandler+0x154>
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
8003b7a: 687b ldr r3, [r7, #4]
8003b7c: 6b1b ldr r3, [r3, #48] ; 0x30
8003b7e: 6878 ldr r0, [r7, #4]
8003b80: 4798 blx r3
if (hdma->XferHalfCpltCallback != NULL)
8003b82: e06c b.n 8003c5e <HAL_DMA_IRQHandler+0x154>
}
}
/* Transfer Complete Interrupt management ***********************************/
else if ((0U != (flag_it & ((uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU))))
8003b84: 687b ldr r3, [r7, #4]
8003b86: 6c5b ldr r3, [r3, #68] ; 0x44
8003b88: f003 031f and.w r3, r3, #31
8003b8c: 2202 movs r2, #2
8003b8e: 409a lsls r2, r3
8003b90: 68fb ldr r3, [r7, #12]
8003b92: 4013 ands r3, r2
8003b94: 2b00 cmp r3, #0
8003b96: d02e beq.n 8003bf6 <HAL_DMA_IRQHandler+0xec>
&& (0U != (source_it & DMA_IT_TC)))
8003b98: 68bb ldr r3, [r7, #8]
8003b9a: f003 0302 and.w r3, r3, #2
8003b9e: 2b00 cmp r3, #0
8003ba0: d029 beq.n 8003bf6 <HAL_DMA_IRQHandler+0xec>
{
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
8003ba2: 687b ldr r3, [r7, #4]
8003ba4: 681b ldr r3, [r3, #0]
8003ba6: 681b ldr r3, [r3, #0]
8003ba8: f003 0320 and.w r3, r3, #32
8003bac: 2b00 cmp r3, #0
8003bae: d10b bne.n 8003bc8 <HAL_DMA_IRQHandler+0xbe>
{
/* Disable the transfer complete and error interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
8003bb0: 687b ldr r3, [r7, #4]
8003bb2: 681b ldr r3, [r3, #0]
8003bb4: 681a ldr r2, [r3, #0]
8003bb6: 687b ldr r3, [r7, #4]
8003bb8: 681b ldr r3, [r3, #0]
8003bba: f022 020a bic.w r2, r2, #10
8003bbe: 601a str r2, [r3, #0]
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8003bc0: 687b ldr r3, [r7, #4]
8003bc2: 2201 movs r2, #1
8003bc4: f883 2025 strb.w r2, [r3, #37] ; 0x25
}
/* Clear the transfer complete flag */
hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1FU));
8003bc8: 687b ldr r3, [r7, #4]
8003bca: 6c5b ldr r3, [r3, #68] ; 0x44
8003bcc: f003 021f and.w r2, r3, #31
8003bd0: 687b ldr r3, [r7, #4]
8003bd2: 6c1b ldr r3, [r3, #64] ; 0x40
8003bd4: 2102 movs r1, #2
8003bd6: fa01 f202 lsl.w r2, r1, r2
8003bda: 605a str r2, [r3, #4]
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003bdc: 687b ldr r3, [r7, #4]
8003bde: 2200 movs r2, #0
8003be0: f883 2024 strb.w r2, [r3, #36] ; 0x24
if (hdma->XferCpltCallback != NULL)
8003be4: 687b ldr r3, [r7, #4]
8003be6: 6adb ldr r3, [r3, #44] ; 0x2c
8003be8: 2b00 cmp r3, #0
8003bea: d038 beq.n 8003c5e <HAL_DMA_IRQHandler+0x154>
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);
8003bec: 687b ldr r3, [r7, #4]
8003bee: 6adb ldr r3, [r3, #44] ; 0x2c
8003bf0: 6878 ldr r0, [r7, #4]
8003bf2: 4798 blx r3
if (hdma->XferCpltCallback != NULL)
8003bf4: e033 b.n 8003c5e <HAL_DMA_IRQHandler+0x154>
}
}
/* Transfer Error Interrupt management **************************************/
else if ((0U != (flag_it & ((uint32_t)DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1FU))))
8003bf6: 687b ldr r3, [r7, #4]
8003bf8: 6c5b ldr r3, [r3, #68] ; 0x44
8003bfa: f003 031f and.w r3, r3, #31
8003bfe: 2208 movs r2, #8
8003c00: 409a lsls r2, r3
8003c02: 68fb ldr r3, [r7, #12]
8003c04: 4013 ands r3, r2
8003c06: 2b00 cmp r3, #0
8003c08: d02a beq.n 8003c60 <HAL_DMA_IRQHandler+0x156>
&& (0U != (source_it & DMA_IT_TE)))
8003c0a: 68bb ldr r3, [r7, #8]
8003c0c: f003 0308 and.w r3, r3, #8
8003c10: 2b00 cmp r3, #0
8003c12: d025 beq.n 8003c60 <HAL_DMA_IRQHandler+0x156>
{
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Disable ALL DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8003c14: 687b ldr r3, [r7, #4]
8003c16: 681b ldr r3, [r3, #0]
8003c18: 681a ldr r2, [r3, #0]
8003c1a: 687b ldr r3, [r7, #4]
8003c1c: 681b ldr r3, [r3, #0]
8003c1e: f022 020e bic.w r2, r2, #14
8003c22: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
8003c24: 687b ldr r3, [r7, #4]
8003c26: 6c5b ldr r3, [r3, #68] ; 0x44
8003c28: f003 021f and.w r2, r3, #31
8003c2c: 687b ldr r3, [r7, #4]
8003c2e: 6c1b ldr r3, [r3, #64] ; 0x40
8003c30: 2101 movs r1, #1
8003c32: fa01 f202 lsl.w r2, r1, r2
8003c36: 605a str r2, [r3, #4]
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
8003c38: 687b ldr r3, [r7, #4]
8003c3a: 2201 movs r2, #1
8003c3c: 63da str r2, [r3, #60] ; 0x3c
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8003c3e: 687b ldr r3, [r7, #4]
8003c40: 2201 movs r2, #1
8003c42: f883 2025 strb.w r2, [r3, #37] ; 0x25
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003c46: 687b ldr r3, [r7, #4]
8003c48: 2200 movs r2, #0
8003c4a: f883 2024 strb.w r2, [r3, #36] ; 0x24
if (hdma->XferErrorCallback != NULL)
8003c4e: 687b ldr r3, [r7, #4]
8003c50: 6b5b ldr r3, [r3, #52] ; 0x34
8003c52: 2b00 cmp r3, #0
8003c54: d004 beq.n 8003c60 <HAL_DMA_IRQHandler+0x156>
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
8003c56: 687b ldr r3, [r7, #4]
8003c58: 6b5b ldr r3, [r3, #52] ; 0x34
8003c5a: 6878 ldr r0, [r7, #4]
8003c5c: 4798 blx r3
}
else
{
/* Nothing To Do */
}
return;
8003c5e: bf00 nop
8003c60: bf00 nop
}
8003c62: 3710 adds r7, #16
8003c64: 46bd mov sp, r7
8003c66: bd80 pop {r7, pc}
08003c68 <DMA_SetConfig>:
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
8003c68: b480 push {r7}
8003c6a: b085 sub sp, #20
8003c6c: af00 add r7, sp, #0
8003c6e: 60f8 str r0, [r7, #12]
8003c70: 60b9 str r1, [r7, #8]
8003c72: 607a str r2, [r7, #4]
8003c74: 603b str r3, [r7, #0]
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8003c76: 68fb ldr r3, [r7, #12]
8003c78: 6cdb ldr r3, [r3, #76] ; 0x4c
8003c7a: 68fa ldr r2, [r7, #12]
8003c7c: 6d12 ldr r2, [r2, #80] ; 0x50
8003c7e: 605a str r2, [r3, #4]
if (hdma->DMAmuxRequestGen != 0U)
8003c80: 68fb ldr r3, [r7, #12]
8003c82: 6d5b ldr r3, [r3, #84] ; 0x54
8003c84: 2b00 cmp r3, #0
8003c86: d004 beq.n 8003c92 <DMA_SetConfig+0x2a>
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
8003c88: 68fb ldr r3, [r7, #12]
8003c8a: 6d9b ldr r3, [r3, #88] ; 0x58
8003c8c: 68fa ldr r2, [r7, #12]
8003c8e: 6dd2 ldr r2, [r2, #92] ; 0x5c
8003c90: 605a str r2, [r3, #4]
}
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
8003c92: 68fb ldr r3, [r7, #12]
8003c94: 6c5b ldr r3, [r3, #68] ; 0x44
8003c96: f003 021f and.w r2, r3, #31
8003c9a: 68fb ldr r3, [r7, #12]
8003c9c: 6c1b ldr r3, [r3, #64] ; 0x40
8003c9e: 2101 movs r1, #1
8003ca0: fa01 f202 lsl.w r2, r1, r2
8003ca4: 605a str r2, [r3, #4]
/* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength;
8003ca6: 68fb ldr r3, [r7, #12]
8003ca8: 681b ldr r3, [r3, #0]
8003caa: 683a ldr r2, [r7, #0]
8003cac: 605a str r2, [r3, #4]
/* Memory to Peripheral */
if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
8003cae: 68fb ldr r3, [r7, #12]
8003cb0: 689b ldr r3, [r3, #8]
8003cb2: 2b10 cmp r3, #16
8003cb4: d108 bne.n 8003cc8 <DMA_SetConfig+0x60>
{
/* Configure DMA Channel destination address */
hdma->Instance->CPAR = DstAddress;
8003cb6: 68fb ldr r3, [r7, #12]
8003cb8: 681b ldr r3, [r3, #0]
8003cba: 687a ldr r2, [r7, #4]
8003cbc: 609a str r2, [r3, #8]
/* Configure DMA Channel source address */
hdma->Instance->CMAR = SrcAddress;
8003cbe: 68fb ldr r3, [r7, #12]
8003cc0: 681b ldr r3, [r3, #0]
8003cc2: 68ba ldr r2, [r7, #8]
8003cc4: 60da str r2, [r3, #12]
hdma->Instance->CPAR = SrcAddress;
/* Configure DMA Channel destination address */
hdma->Instance->CMAR = DstAddress;
}
}
8003cc6: e007 b.n 8003cd8 <DMA_SetConfig+0x70>
hdma->Instance->CPAR = SrcAddress;
8003cc8: 68fb ldr r3, [r7, #12]
8003cca: 681b ldr r3, [r3, #0]
8003ccc: 68ba ldr r2, [r7, #8]
8003cce: 609a str r2, [r3, #8]
hdma->Instance->CMAR = DstAddress;
8003cd0: 68fb ldr r3, [r7, #12]
8003cd2: 681b ldr r3, [r3, #0]
8003cd4: 687a ldr r2, [r7, #4]
8003cd6: 60da str r2, [r3, #12]
}
8003cd8: bf00 nop
8003cda: 3714 adds r7, #20
8003cdc: 46bd mov sp, r7
8003cde: f85d 7b04 ldr.w r7, [sp], #4
8003ce2: 4770 bx lr
08003ce4 <DMA_CalcDMAMUXChannelBaseAndMask>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval None
*/
static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
{
8003ce4: b480 push {r7}
8003ce6: b087 sub sp, #28
8003ce8: af00 add r7, sp, #0
8003cea: 6078 str r0, [r7, #4]
uint32_t dmamux_base_addr;
uint32_t channel_number;
DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase;
/* check if instance is not outside the DMA channel range */
if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1)
8003cec: 687b ldr r3, [r7, #4]
8003cee: 681b ldr r3, [r3, #0]
8003cf0: 461a mov r2, r3
8003cf2: 4b16 ldr r3, [pc, #88] ; (8003d4c <DMA_CalcDMAMUXChannelBaseAndMask+0x68>)
8003cf4: 429a cmp r2, r3
8003cf6: d802 bhi.n 8003cfe <DMA_CalcDMAMUXChannelBaseAndMask+0x1a>
{
/* DMA1 */
DMAMUX1_ChannelBase = DMAMUX1_Channel0;
8003cf8: 4b15 ldr r3, [pc, #84] ; (8003d50 <DMA_CalcDMAMUXChannelBaseAndMask+0x6c>)
8003cfa: 617b str r3, [r7, #20]
8003cfc: e001 b.n 8003d02 <DMA_CalcDMAMUXChannelBaseAndMask+0x1e>
{
/* DMA2 */
#if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx) || defined (STM32G491xx) || defined (STM32G4A1xx)
DMAMUX1_ChannelBase = DMAMUX1_Channel8;
#elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB)
DMAMUX1_ChannelBase = DMAMUX1_Channel6;
8003cfe: 4b15 ldr r3, [pc, #84] ; (8003d54 <DMA_CalcDMAMUXChannelBaseAndMask+0x70>)
8003d00: 617b str r3, [r7, #20]
#else
DMAMUX1_ChannelBase = DMAMUX1_Channel7;
#endif /* STM32G4x1xx) */
}
dmamux_base_addr = (uint32_t)DMAMUX1_ChannelBase;
8003d02: 697b ldr r3, [r7, #20]
8003d04: 613b str r3, [r7, #16]
channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
8003d06: 687b ldr r3, [r7, #4]
8003d08: 681b ldr r3, [r3, #0]
8003d0a: b2db uxtb r3, r3
8003d0c: 3b08 subs r3, #8
8003d0e: 4a12 ldr r2, [pc, #72] ; (8003d58 <DMA_CalcDMAMUXChannelBaseAndMask+0x74>)
8003d10: fba2 2303 umull r2, r3, r2, r3
8003d14: 091b lsrs r3, r3, #4
8003d16: 60fb str r3, [r7, #12]
hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)(dmamux_base_addr + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)));
8003d18: 687b ldr r3, [r7, #4]
8003d1a: 6c5b ldr r3, [r3, #68] ; 0x44
8003d1c: 089b lsrs r3, r3, #2
8003d1e: 009a lsls r2, r3, #2
8003d20: 693b ldr r3, [r7, #16]
8003d22: 4413 add r3, r2
8003d24: 461a mov r2, r3
8003d26: 687b ldr r3, [r7, #4]
8003d28: 649a str r2, [r3, #72] ; 0x48
hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
8003d2a: 687b ldr r3, [r7, #4]
8003d2c: 4a0b ldr r2, [pc, #44] ; (8003d5c <DMA_CalcDMAMUXChannelBaseAndMask+0x78>)
8003d2e: 64da str r2, [r3, #76] ; 0x4c
hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU);
8003d30: 68fb ldr r3, [r7, #12]
8003d32: f003 031f and.w r3, r3, #31
8003d36: 2201 movs r2, #1
8003d38: 409a lsls r2, r3
8003d3a: 687b ldr r3, [r7, #4]
8003d3c: 651a str r2, [r3, #80] ; 0x50
}
8003d3e: bf00 nop
8003d40: 371c adds r7, #28
8003d42: 46bd mov sp, r7
8003d44: f85d 7b04 ldr.w r7, [sp], #4
8003d48: 4770 bx lr
8003d4a: bf00 nop
8003d4c: 40020407 .word 0x40020407
8003d50: 40020800 .word 0x40020800
8003d54: 40020820 .word 0x40020820
8003d58: cccccccd .word 0xcccccccd
8003d5c: 40020880 .word 0x40020880
08003d60 <DMA_CalcDMAMUXRequestGenBaseAndMask>:
* the configuration information for the specified DMA Channel.
* @retval None
*/
static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
{
8003d60: b480 push {r7}
8003d62: b085 sub sp, #20
8003d64: af00 add r7, sp, #0
8003d66: 6078 str r0, [r7, #4]
uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
8003d68: 687b ldr r3, [r7, #4]
8003d6a: 685b ldr r3, [r3, #4]
8003d6c: b2db uxtb r3, r3
8003d6e: 60fb str r3, [r7, #12]
/* DMA Channels are connected to DMAMUX1 request generator blocks*/
hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
8003d70: 68fa ldr r2, [r7, #12]
8003d72: 4b0b ldr r3, [pc, #44] ; (8003da0 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x40>)
8003d74: 4413 add r3, r2
8003d76: 009b lsls r3, r3, #2
8003d78: 461a mov r2, r3
8003d7a: 687b ldr r3, [r7, #4]
8003d7c: 655a str r2, [r3, #84] ; 0x54
hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
8003d7e: 687b ldr r3, [r7, #4]
8003d80: 4a08 ldr r2, [pc, #32] ; (8003da4 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x44>)
8003d82: 659a str r2, [r3, #88] ; 0x58
hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x1FU);
8003d84: 68fb ldr r3, [r7, #12]
8003d86: 3b01 subs r3, #1
8003d88: f003 031f and.w r3, r3, #31
8003d8c: 2201 movs r2, #1
8003d8e: 409a lsls r2, r3
8003d90: 687b ldr r3, [r7, #4]
8003d92: 65da str r2, [r3, #92] ; 0x5c
}
8003d94: bf00 nop
8003d96: 3714 adds r7, #20
8003d98: 46bd mov sp, r7
8003d9a: f85d 7b04 ldr.w r7, [sp], #4
8003d9e: 4770 bx lr
8003da0: 1000823f .word 0x1000823f
8003da4: 40020940 .word 0x40020940
08003da8 <HAL_FDCAN_Init>:
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
{
8003da8: b580 push {r7, lr}
8003daa: b084 sub sp, #16
8003dac: af00 add r7, sp, #0
8003dae: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Check FDCAN handle */
if (hfdcan == NULL)
8003db0: 687b ldr r3, [r7, #4]
8003db2: 2b00 cmp r3, #0
8003db4: d101 bne.n 8003dba <HAL_FDCAN_Init+0x12>
{
return HAL_ERROR;
8003db6: 2301 movs r3, #1
8003db8: e147 b.n 800404a <HAL_FDCAN_Init+0x2a2>
/* Init the low level hardware: CLOCK, NVIC */
hfdcan->MspInitCallback(hfdcan);
}
#else
if (hfdcan->State == HAL_FDCAN_STATE_RESET)
8003dba: 687b ldr r3, [r7, #4]
8003dbc: f893 305c ldrb.w r3, [r3, #92] ; 0x5c
8003dc0: b2db uxtb r3, r3
8003dc2: 2b00 cmp r3, #0
8003dc4: d106 bne.n 8003dd4 <HAL_FDCAN_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hfdcan->Lock = HAL_UNLOCKED;
8003dc6: 687b ldr r3, [r7, #4]
8003dc8: 2200 movs r2, #0
8003dca: f883 205d strb.w r2, [r3, #93] ; 0x5d
/* Init the low level hardware: CLOCK, NVIC */
HAL_FDCAN_MspInit(hfdcan);
8003dce: 6878 ldr r0, [r7, #4]
8003dd0: f7fd fd30 bl 8001834 <HAL_FDCAN_MspInit>
}
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
/* Exit from Sleep mode */
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
8003dd4: 687b ldr r3, [r7, #4]
8003dd6: 681b ldr r3, [r3, #0]
8003dd8: 699a ldr r2, [r3, #24]
8003dda: 687b ldr r3, [r7, #4]
8003ddc: 681b ldr r3, [r3, #0]
8003dde: f022 0210 bic.w r2, r2, #16
8003de2: 619a str r2, [r3, #24]
/* Get tick */
tickstart = HAL_GetTick();
8003de4: f7fd ffb6 bl 8001d54 <HAL_GetTick>
8003de8: 60f8 str r0, [r7, #12]
/* Check Sleep mode acknowledge */
while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
8003dea: e012 b.n 8003e12 <HAL_FDCAN_Init+0x6a>
{
if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
8003dec: f7fd ffb2 bl 8001d54 <HAL_GetTick>
8003df0: 4602 mov r2, r0
8003df2: 68fb ldr r3, [r7, #12]
8003df4: 1ad3 subs r3, r2, r3
8003df6: 2b0a cmp r3, #10
8003df8: d90b bls.n 8003e12 <HAL_FDCAN_Init+0x6a>
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
8003dfa: 687b ldr r3, [r7, #4]
8003dfc: 6e1b ldr r3, [r3, #96] ; 0x60
8003dfe: f043 0201 orr.w r2, r3, #1
8003e02: 687b ldr r3, [r7, #4]
8003e04: 661a str r2, [r3, #96] ; 0x60
/* Change FDCAN state */
hfdcan->State = HAL_FDCAN_STATE_ERROR;
8003e06: 687b ldr r3, [r7, #4]
8003e08: 2203 movs r2, #3
8003e0a: f883 205c strb.w r2, [r3, #92] ; 0x5c
return HAL_ERROR;
8003e0e: 2301 movs r3, #1
8003e10: e11b b.n 800404a <HAL_FDCAN_Init+0x2a2>
while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
8003e12: 687b ldr r3, [r7, #4]
8003e14: 681b ldr r3, [r3, #0]
8003e16: 699b ldr r3, [r3, #24]
8003e18: f003 0308 and.w r3, r3, #8
8003e1c: 2b08 cmp r3, #8
8003e1e: d0e5 beq.n 8003dec <HAL_FDCAN_Init+0x44>
}
}
/* Request initialisation */
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
8003e20: 687b ldr r3, [r7, #4]
8003e22: 681b ldr r3, [r3, #0]
8003e24: 699a ldr r2, [r3, #24]
8003e26: 687b ldr r3, [r7, #4]
8003e28: 681b ldr r3, [r3, #0]
8003e2a: f042 0201 orr.w r2, r2, #1
8003e2e: 619a str r2, [r3, #24]
/* Get tick */
tickstart = HAL_GetTick();
8003e30: f7fd ff90 bl 8001d54 <HAL_GetTick>
8003e34: 60f8 str r0, [r7, #12]
/* Wait until the INIT bit into CCCR register is set */
while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
8003e36: e012 b.n 8003e5e <HAL_FDCAN_Init+0xb6>
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
8003e38: f7fd ff8c bl 8001d54 <HAL_GetTick>
8003e3c: 4602 mov r2, r0
8003e3e: 68fb ldr r3, [r7, #12]
8003e40: 1ad3 subs r3, r2, r3
8003e42: 2b0a cmp r3, #10
8003e44: d90b bls.n 8003e5e <HAL_FDCAN_Init+0xb6>
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
8003e46: 687b ldr r3, [r7, #4]
8003e48: 6e1b ldr r3, [r3, #96] ; 0x60
8003e4a: f043 0201 orr.w r2, r3, #1
8003e4e: 687b ldr r3, [r7, #4]
8003e50: 661a str r2, [r3, #96] ; 0x60
/* Change FDCAN state */
hfdcan->State = HAL_FDCAN_STATE_ERROR;
8003e52: 687b ldr r3, [r7, #4]
8003e54: 2203 movs r2, #3
8003e56: f883 205c strb.w r2, [r3, #92] ; 0x5c
return HAL_ERROR;
8003e5a: 2301 movs r3, #1
8003e5c: e0f5 b.n 800404a <HAL_FDCAN_Init+0x2a2>
while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
8003e5e: 687b ldr r3, [r7, #4]
8003e60: 681b ldr r3, [r3, #0]
8003e62: 699b ldr r3, [r3, #24]
8003e64: f003 0301 and.w r3, r3, #1
8003e68: 2b00 cmp r3, #0
8003e6a: d0e5 beq.n 8003e38 <HAL_FDCAN_Init+0x90>
}
}
/* Enable configuration change */
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
8003e6c: 687b ldr r3, [r7, #4]
8003e6e: 681b ldr r3, [r3, #0]
8003e70: 699a ldr r2, [r3, #24]
8003e72: 687b ldr r3, [r7, #4]
8003e74: 681b ldr r3, [r3, #0]
8003e76: f042 0202 orr.w r2, r2, #2
8003e7a: 619a str r2, [r3, #24]
/* Check FDCAN instance */
if (hfdcan->Instance == FDCAN1)
8003e7c: 687b ldr r3, [r7, #4]
8003e7e: 681b ldr r3, [r3, #0]
8003e80: 4a74 ldr r2, [pc, #464] ; (8004054 <HAL_FDCAN_Init+0x2ac>)
8003e82: 4293 cmp r3, r2
8003e84: d103 bne.n 8003e8e <HAL_FDCAN_Init+0xe6>
{
/* Configure Clock divider */
FDCAN_CONFIG->CKDIV = hfdcan->Init.ClockDivider;
8003e86: 4a74 ldr r2, [pc, #464] ; (8004058 <HAL_FDCAN_Init+0x2b0>)
8003e88: 687b ldr r3, [r7, #4]
8003e8a: 685b ldr r3, [r3, #4]
8003e8c: 6013 str r3, [r2, #0]
}
/* Set the no automatic retransmission */
if (hfdcan->Init.AutoRetransmission == ENABLE)
8003e8e: 687b ldr r3, [r7, #4]
8003e90: 7c1b ldrb r3, [r3, #16]
8003e92: 2b01 cmp r3, #1
8003e94: d108 bne.n 8003ea8 <HAL_FDCAN_Init+0x100>
{
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
8003e96: 687b ldr r3, [r7, #4]
8003e98: 681b ldr r3, [r3, #0]
8003e9a: 699a ldr r2, [r3, #24]
8003e9c: 687b ldr r3, [r7, #4]
8003e9e: 681b ldr r3, [r3, #0]
8003ea0: f022 0240 bic.w r2, r2, #64 ; 0x40
8003ea4: 619a str r2, [r3, #24]
8003ea6: e007 b.n 8003eb8 <HAL_FDCAN_Init+0x110>
}
else
{
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
8003ea8: 687b ldr r3, [r7, #4]
8003eaa: 681b ldr r3, [r3, #0]
8003eac: 699a ldr r2, [r3, #24]
8003eae: 687b ldr r3, [r7, #4]
8003eb0: 681b ldr r3, [r3, #0]
8003eb2: f042 0240 orr.w r2, r2, #64 ; 0x40
8003eb6: 619a str r2, [r3, #24]
}
/* Set the transmit pause feature */
if (hfdcan->Init.TransmitPause == ENABLE)
8003eb8: 687b ldr r3, [r7, #4]
8003eba: 7c5b ldrb r3, [r3, #17]
8003ebc: 2b01 cmp r3, #1
8003ebe: d108 bne.n 8003ed2 <HAL_FDCAN_Init+0x12a>
{
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
8003ec0: 687b ldr r3, [r7, #4]
8003ec2: 681b ldr r3, [r3, #0]
8003ec4: 699a ldr r2, [r3, #24]
8003ec6: 687b ldr r3, [r7, #4]
8003ec8: 681b ldr r3, [r3, #0]
8003eca: f442 4280 orr.w r2, r2, #16384 ; 0x4000
8003ece: 619a str r2, [r3, #24]
8003ed0: e007 b.n 8003ee2 <HAL_FDCAN_Init+0x13a>
}
else
{
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
8003ed2: 687b ldr r3, [r7, #4]
8003ed4: 681b ldr r3, [r3, #0]
8003ed6: 699a ldr r2, [r3, #24]
8003ed8: 687b ldr r3, [r7, #4]
8003eda: 681b ldr r3, [r3, #0]
8003edc: f422 4280 bic.w r2, r2, #16384 ; 0x4000
8003ee0: 619a str r2, [r3, #24]
}
/* Set the Protocol Exception Handling */
if (hfdcan->Init.ProtocolException == ENABLE)
8003ee2: 687b ldr r3, [r7, #4]
8003ee4: 7c9b ldrb r3, [r3, #18]
8003ee6: 2b01 cmp r3, #1
8003ee8: d108 bne.n 8003efc <HAL_FDCAN_Init+0x154>
{
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
8003eea: 687b ldr r3, [r7, #4]
8003eec: 681b ldr r3, [r3, #0]
8003eee: 699a ldr r2, [r3, #24]
8003ef0: 687b ldr r3, [r7, #4]
8003ef2: 681b ldr r3, [r3, #0]
8003ef4: f422 5280 bic.w r2, r2, #4096 ; 0x1000
8003ef8: 619a str r2, [r3, #24]
8003efa: e007 b.n 8003f0c <HAL_FDCAN_Init+0x164>
}
else
{
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
8003efc: 687b ldr r3, [r7, #4]
8003efe: 681b ldr r3, [r3, #0]
8003f00: 699a ldr r2, [r3, #24]
8003f02: 687b ldr r3, [r7, #4]
8003f04: 681b ldr r3, [r3, #0]
8003f06: f442 5280 orr.w r2, r2, #4096 ; 0x1000
8003f0a: 619a str r2, [r3, #24]
}
/* Set FDCAN Frame Format */
MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat);
8003f0c: 687b ldr r3, [r7, #4]
8003f0e: 681b ldr r3, [r3, #0]
8003f10: 699b ldr r3, [r3, #24]
8003f12: f423 7140 bic.w r1, r3, #768 ; 0x300
8003f16: 687b ldr r3, [r7, #4]
8003f18: 689a ldr r2, [r3, #8]
8003f1a: 687b ldr r3, [r7, #4]
8003f1c: 681b ldr r3, [r3, #0]
8003f1e: 430a orrs r2, r1
8003f20: 619a str r2, [r3, #24]
/* Reset FDCAN Operation Mode */
CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM));
8003f22: 687b ldr r3, [r7, #4]
8003f24: 681b ldr r3, [r3, #0]
8003f26: 699a ldr r2, [r3, #24]
8003f28: 687b ldr r3, [r7, #4]
8003f2a: 681b ldr r3, [r3, #0]
8003f2c: f022 02a4 bic.w r2, r2, #164 ; 0xa4
8003f30: 619a str r2, [r3, #24]
CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
8003f32: 687b ldr r3, [r7, #4]
8003f34: 681b ldr r3, [r3, #0]
8003f36: 691a ldr r2, [r3, #16]
8003f38: 687b ldr r3, [r7, #4]
8003f3a: 681b ldr r3, [r3, #0]
8003f3c: f022 0210 bic.w r2, r2, #16
8003f40: 611a str r2, [r3, #16]
CCCR.TEST | 0 | 0 | 0 | 1 | 1
CCCR.MON | 0 | 0 | 1 | 1 | 0
TEST.LBCK | 0 | 0 | 0 | 1 | 1
CCCR.ASM | 0 | 1 | 0 | 0 | 0
*/
if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION)
8003f42: 687b ldr r3, [r7, #4]
8003f44: 68db ldr r3, [r3, #12]
8003f46: 2b01 cmp r3, #1
8003f48: d108 bne.n 8003f5c <HAL_FDCAN_Init+0x1b4>
{
/* Enable Restricted Operation mode */
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
8003f4a: 687b ldr r3, [r7, #4]
8003f4c: 681b ldr r3, [r3, #0]
8003f4e: 699a ldr r2, [r3, #24]
8003f50: 687b ldr r3, [r7, #4]
8003f52: 681b ldr r3, [r3, #0]
8003f54: f042 0204 orr.w r2, r2, #4
8003f58: 619a str r2, [r3, #24]
8003f5a: e02c b.n 8003fb6 <HAL_FDCAN_Init+0x20e>
}
else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL)
8003f5c: 687b ldr r3, [r7, #4]
8003f5e: 68db ldr r3, [r3, #12]
8003f60: 2b00 cmp r3, #0
8003f62: d028 beq.n 8003fb6 <HAL_FDCAN_Init+0x20e>
{
if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING)
8003f64: 687b ldr r3, [r7, #4]
8003f66: 68db ldr r3, [r3, #12]
8003f68: 2b02 cmp r3, #2
8003f6a: d01c beq.n 8003fa6 <HAL_FDCAN_Init+0x1fe>
{
/* Enable write access to TEST register */
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);
8003f6c: 687b ldr r3, [r7, #4]
8003f6e: 681b ldr r3, [r3, #0]
8003f70: 699a ldr r2, [r3, #24]
8003f72: 687b ldr r3, [r7, #4]
8003f74: 681b ldr r3, [r3, #0]
8003f76: f042 0280 orr.w r2, r2, #128 ; 0x80
8003f7a: 619a str r2, [r3, #24]
/* Enable LoopBack mode */
SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
8003f7c: 687b ldr r3, [r7, #4]
8003f7e: 681b ldr r3, [r3, #0]
8003f80: 691a ldr r2, [r3, #16]
8003f82: 687b ldr r3, [r7, #4]
8003f84: 681b ldr r3, [r3, #0]
8003f86: f042 0210 orr.w r2, r2, #16
8003f8a: 611a str r2, [r3, #16]
if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK)
8003f8c: 687b ldr r3, [r7, #4]
8003f8e: 68db ldr r3, [r3, #12]
8003f90: 2b03 cmp r3, #3
8003f92: d110 bne.n 8003fb6 <HAL_FDCAN_Init+0x20e>
{
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
8003f94: 687b ldr r3, [r7, #4]
8003f96: 681b ldr r3, [r3, #0]
8003f98: 699a ldr r2, [r3, #24]
8003f9a: 687b ldr r3, [r7, #4]
8003f9c: 681b ldr r3, [r3, #0]
8003f9e: f042 0220 orr.w r2, r2, #32
8003fa2: 619a str r2, [r3, #24]
8003fa4: e007 b.n 8003fb6 <HAL_FDCAN_Init+0x20e>
}
}
else
{
/* Enable bus monitoring mode */
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
8003fa6: 687b ldr r3, [r7, #4]
8003fa8: 681b ldr r3, [r3, #0]
8003faa: 699a ldr r2, [r3, #24]
8003fac: 687b ldr r3, [r7, #4]
8003fae: 681b ldr r3, [r3, #0]
8003fb0: f042 0220 orr.w r2, r2, #32
8003fb4: 619a str r2, [r3, #24]
{
/* Nothing to do: normal mode */
}
/* Set the nominal bit timing register */
hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
8003fb6: 687b ldr r3, [r7, #4]
8003fb8: 699b ldr r3, [r3, #24]
8003fba: 3b01 subs r3, #1
8003fbc: 065a lsls r2, r3, #25
(((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos) | \
8003fbe: 687b ldr r3, [r7, #4]
8003fc0: 69db ldr r3, [r3, #28]
8003fc2: 3b01 subs r3, #1
8003fc4: 021b lsls r3, r3, #8
hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
8003fc6: 431a orrs r2, r3
(((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos) | \
8003fc8: 687b ldr r3, [r7, #4]
8003fca: 6a1b ldr r3, [r3, #32]
8003fcc: 3b01 subs r3, #1
(((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos) | \
8003fce: ea42 0103 orr.w r1, r2, r3
(((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos));
8003fd2: 687b ldr r3, [r7, #4]
8003fd4: 695b ldr r3, [r3, #20]
8003fd6: 3b01 subs r3, #1
8003fd8: 041a lsls r2, r3, #16
hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
8003fda: 687b ldr r3, [r7, #4]
8003fdc: 681b ldr r3, [r3, #0]
(((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos) | \
8003fde: 430a orrs r2, r1
hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
8003fe0: 61da str r2, [r3, #28]
/* If FD operation with BRS is selected, set the data bit timing register */
if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
8003fe2: 687b ldr r3, [r7, #4]
8003fe4: 689b ldr r3, [r3, #8]
8003fe6: f5b3 7f40 cmp.w r3, #768 ; 0x300
8003fea: d115 bne.n 8004018 <HAL_FDCAN_Init+0x270>
{
hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
8003fec: 687b ldr r3, [r7, #4]
8003fee: 6a9b ldr r3, [r3, #40] ; 0x28
8003ff0: 1e5a subs r2, r3, #1
(((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) | \
8003ff2: 687b ldr r3, [r7, #4]
8003ff4: 6adb ldr r3, [r3, #44] ; 0x2c
8003ff6: 3b01 subs r3, #1
8003ff8: 021b lsls r3, r3, #8
hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
8003ffa: 431a orrs r2, r3
(((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) | \
8003ffc: 687b ldr r3, [r7, #4]
8003ffe: 6b1b ldr r3, [r3, #48] ; 0x30
8004000: 3b01 subs r3, #1
8004002: 011b lsls r3, r3, #4
(((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) | \
8004004: ea42 0103 orr.w r1, r2, r3
(((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos));
8004008: 687b ldr r3, [r7, #4]
800400a: 6a5b ldr r3, [r3, #36] ; 0x24
800400c: 3b01 subs r3, #1
800400e: 041a lsls r2, r3, #16
hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
8004010: 687b ldr r3, [r7, #4]
8004012: 681b ldr r3, [r3, #0]
(((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) | \
8004014: 430a orrs r2, r1
hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
8004016: 60da str r2, [r3, #12]
}
/* Select between Tx FIFO and Tx Queue operation modes */
SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
8004018: 687b ldr r3, [r7, #4]
800401a: 681b ldr r3, [r3, #0]
800401c: f8d3 10c0 ldr.w r1, [r3, #192] ; 0xc0
8004020: 687b ldr r3, [r7, #4]
8004022: 6bda ldr r2, [r3, #60] ; 0x3c
8004024: 687b ldr r3, [r7, #4]
8004026: 681b ldr r3, [r3, #0]
8004028: 430a orrs r2, r1
800402a: f8c3 20c0 str.w r2, [r3, #192] ; 0xc0
/* Calculate each RAM block address */
FDCAN_CalcultateRamBlockAddresses(hfdcan);
800402e: 6878 ldr r0, [r7, #4]
8004030: f000 fc6e bl 8004910 <FDCAN_CalcultateRamBlockAddresses>
/* Initialize the Latest Tx request buffer index */
hfdcan->LatestTxFifoQRequest = 0U;
8004034: 687b ldr r3, [r7, #4]
8004036: 2200 movs r2, #0
8004038: 659a str r2, [r3, #88] ; 0x58
/* Initialize the error code */
hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
800403a: 687b ldr r3, [r7, #4]
800403c: 2200 movs r2, #0
800403e: 661a str r2, [r3, #96] ; 0x60
/* Initialize the FDCAN state */
hfdcan->State = HAL_FDCAN_STATE_READY;
8004040: 687b ldr r3, [r7, #4]
8004042: 2201 movs r2, #1
8004044: f883 205c strb.w r2, [r3, #92] ; 0x5c
/* Return function status */
return HAL_OK;
8004048: 2300 movs r3, #0
}
800404a: 4618 mov r0, r3
800404c: 3710 adds r7, #16
800404e: 46bd mov sp, r7
8004050: bd80 pop {r7, pc}
8004052: bf00 nop
8004054: 40006400 .word 0x40006400
8004058: 40006500 .word 0x40006500
0800405c <HAL_FDCAN_ConfigFilter>:
* @param sFilterConfig pointer to an FDCAN_FilterTypeDef structure that
* contains the filter configuration information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
{
800405c: b480 push {r7}
800405e: b087 sub sp, #28
8004060: af00 add r7, sp, #0
8004062: 6078 str r0, [r7, #4]
8004064: 6039 str r1, [r7, #0]
uint32_t FilterElementW1;
uint32_t FilterElementW2;
uint32_t *FilterAddress;
HAL_FDCAN_StateTypeDef state = hfdcan->State;
8004066: 687b ldr r3, [r7, #4]
8004068: f893 305c ldrb.w r3, [r3, #92] ; 0x5c
800406c: 75fb strb r3, [r7, #23]
if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
800406e: 7dfb ldrb r3, [r7, #23]
8004070: 2b01 cmp r3, #1
8004072: d002 beq.n 800407a <HAL_FDCAN_ConfigFilter+0x1e>
8004074: 7dfb ldrb r3, [r7, #23]
8004076: 2b02 cmp r3, #2
8004078: d13d bne.n 80040f6 <HAL_FDCAN_ConfigFilter+0x9a>
{
/* Check function parameters */
assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType));
assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig));
if (sFilterConfig->IdType == FDCAN_STANDARD_ID)
800407a: 683b ldr r3, [r7, #0]
800407c: 681b ldr r3, [r3, #0]
800407e: 2b00 cmp r3, #0
8004080: d119 bne.n 80040b6 <HAL_FDCAN_ConfigFilter+0x5a>
assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU));
assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU));
assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType));
/* Build filter element */
FilterElementW1 = ((sFilterConfig->FilterType << 30U) |
8004082: 683b ldr r3, [r7, #0]
8004084: 689b ldr r3, [r3, #8]
8004086: 079a lsls r2, r3, #30
(sFilterConfig->FilterConfig << 27U) |
8004088: 683b ldr r3, [r7, #0]
800408a: 68db ldr r3, [r3, #12]
800408c: 06db lsls r3, r3, #27
FilterElementW1 = ((sFilterConfig->FilterType << 30U) |
800408e: 431a orrs r2, r3
(sFilterConfig->FilterID1 << 16U) |
8004090: 683b ldr r3, [r7, #0]
8004092: 691b ldr r3, [r3, #16]
8004094: 041b lsls r3, r3, #16
(sFilterConfig->FilterConfig << 27U) |
8004096: 431a orrs r2, r3
sFilterConfig->FilterID2);
8004098: 683b ldr r3, [r7, #0]
800409a: 695b ldr r3, [r3, #20]
FilterElementW1 = ((sFilterConfig->FilterType << 30U) |
800409c: 4313 orrs r3, r2
800409e: 613b str r3, [r7, #16]
/* Calculate filter address */
FilterAddress = (uint32_t *)(hfdcan->msgRam.StandardFilterSA + (sFilterConfig->FilterIndex * SRAMCAN_FLS_SIZE));
80040a0: 687b ldr r3, [r7, #4]
80040a2: 6c1a ldr r2, [r3, #64] ; 0x40
80040a4: 683b ldr r3, [r7, #0]
80040a6: 685b ldr r3, [r3, #4]
80040a8: 009b lsls r3, r3, #2
80040aa: 4413 add r3, r2
80040ac: 60bb str r3, [r7, #8]
/* Write filter element to the message RAM */
*FilterAddress = FilterElementW1;
80040ae: 68bb ldr r3, [r7, #8]
80040b0: 693a ldr r2, [r7, #16]
80040b2: 601a str r2, [r3, #0]
80040b4: e01d b.n 80040f2 <HAL_FDCAN_ConfigFilter+0x96>
assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU));
assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU));
assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType));
/* Build first word of filter element */
FilterElementW1 = ((sFilterConfig->FilterConfig << 29U) | sFilterConfig->FilterID1);
80040b6: 683b ldr r3, [r7, #0]
80040b8: 68db ldr r3, [r3, #12]
80040ba: 075a lsls r2, r3, #29
80040bc: 683b ldr r3, [r7, #0]
80040be: 691b ldr r3, [r3, #16]
80040c0: 4313 orrs r3, r2
80040c2: 613b str r3, [r7, #16]
/* Build second word of filter element */
FilterElementW2 = ((sFilterConfig->FilterType << 30U) | sFilterConfig->FilterID2);
80040c4: 683b ldr r3, [r7, #0]
80040c6: 689b ldr r3, [r3, #8]
80040c8: 079a lsls r2, r3, #30
80040ca: 683b ldr r3, [r7, #0]
80040cc: 695b ldr r3, [r3, #20]
80040ce: 4313 orrs r3, r2
80040d0: 60fb str r3, [r7, #12]
/* Calculate filter address */
FilterAddress = (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA + (sFilterConfig->FilterIndex * SRAMCAN_FLE_SIZE));
80040d2: 687b ldr r3, [r7, #4]
80040d4: 6c5a ldr r2, [r3, #68] ; 0x44
80040d6: 683b ldr r3, [r7, #0]
80040d8: 685b ldr r3, [r3, #4]
80040da: 00db lsls r3, r3, #3
80040dc: 4413 add r3, r2
80040de: 60bb str r3, [r7, #8]
/* Write filter element to the message RAM */
*FilterAddress = FilterElementW1;
80040e0: 68bb ldr r3, [r7, #8]
80040e2: 693a ldr r2, [r7, #16]
80040e4: 601a str r2, [r3, #0]
FilterAddress++;
80040e6: 68bb ldr r3, [r7, #8]
80040e8: 3304 adds r3, #4
80040ea: 60bb str r3, [r7, #8]
*FilterAddress = FilterElementW2;
80040ec: 68bb ldr r3, [r7, #8]
80040ee: 68fa ldr r2, [r7, #12]
80040f0: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
80040f2: 2300 movs r3, #0
80040f4: e006 b.n 8004104 <HAL_FDCAN_ConfigFilter+0xa8>
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
80040f6: 687b ldr r3, [r7, #4]
80040f8: 6e1b ldr r3, [r3, #96] ; 0x60
80040fa: f043 0202 orr.w r2, r3, #2
80040fe: 687b ldr r3, [r7, #4]
8004100: 661a str r2, [r3, #96] ; 0x60
return HAL_ERROR;
8004102: 2301 movs r3, #1
}
}
8004104: 4618 mov r0, r3
8004106: 371c adds r7, #28
8004108: 46bd mov sp, r7
800410a: f85d 7b04 ldr.w r7, [sp], #4
800410e: 4770 bx lr
08004110 <HAL_FDCAN_ConfigGlobalFilter>:
HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
uint32_t NonMatchingStd,
uint32_t NonMatchingExt,
uint32_t RejectRemoteStd,
uint32_t RejectRemoteExt)
{
8004110: b480 push {r7}
8004112: b085 sub sp, #20
8004114: af00 add r7, sp, #0
8004116: 60f8 str r0, [r7, #12]
8004118: 60b9 str r1, [r7, #8]
800411a: 607a str r2, [r7, #4]
800411c: 603b str r3, [r7, #0]
assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd));
assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt));
assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteStd));
assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteExt));
if (hfdcan->State == HAL_FDCAN_STATE_READY)
800411e: 68fb ldr r3, [r7, #12]
8004120: f893 305c ldrb.w r3, [r3, #92] ; 0x5c
8004124: b2db uxtb r3, r3
8004126: 2b01 cmp r3, #1
8004128: d116 bne.n 8004158 <HAL_FDCAN_ConfigGlobalFilter+0x48>
{
/* Configure global filter */
MODIFY_REG(hfdcan->Instance->RXGFC, (FDCAN_RXGFC_ANFS |
800412a: 68fb ldr r3, [r7, #12]
800412c: 681b ldr r3, [r3, #0]
800412e: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
8004132: f023 013f bic.w r1, r3, #63 ; 0x3f
8004136: 68bb ldr r3, [r7, #8]
8004138: 011a lsls r2, r3, #4
800413a: 687b ldr r3, [r7, #4]
800413c: 009b lsls r3, r3, #2
800413e: 431a orrs r2, r3
8004140: 683b ldr r3, [r7, #0]
8004142: 005b lsls r3, r3, #1
8004144: 431a orrs r2, r3
8004146: 69bb ldr r3, [r7, #24]
8004148: 431a orrs r2, r3
800414a: 68fb ldr r3, [r7, #12]
800414c: 681b ldr r3, [r3, #0]
800414e: 430a orrs r2, r1
8004150: f8c3 2080 str.w r2, [r3, #128] ; 0x80
(NonMatchingExt << FDCAN_RXGFC_ANFE_Pos) |
(RejectRemoteStd << FDCAN_RXGFC_RRFS_Pos) |
(RejectRemoteExt << FDCAN_RXGFC_RRFE_Pos)));
/* Return function status */
return HAL_OK;
8004154: 2300 movs r3, #0
8004156: e006 b.n 8004166 <HAL_FDCAN_ConfigGlobalFilter+0x56>
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
8004158: 68fb ldr r3, [r7, #12]
800415a: 6e1b ldr r3, [r3, #96] ; 0x60
800415c: f043 0204 orr.w r2, r3, #4
8004160: 68fb ldr r3, [r7, #12]
8004162: 661a str r2, [r3, #96] ; 0x60
return HAL_ERROR;
8004164: 2301 movs r3, #1
}
}
8004166: 4618 mov r0, r3
8004168: 3714 adds r7, #20
800416a: 46bd mov sp, r7
800416c: f85d 7b04 ldr.w r7, [sp], #4
8004170: 4770 bx lr
08004172 <HAL_FDCAN_Start>:
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan)
{
8004172: b480 push {r7}
8004174: b083 sub sp, #12
8004176: af00 add r7, sp, #0
8004178: 6078 str r0, [r7, #4]
if (hfdcan->State == HAL_FDCAN_STATE_READY)
800417a: 687b ldr r3, [r7, #4]
800417c: f893 305c ldrb.w r3, [r3, #92] ; 0x5c
8004180: b2db uxtb r3, r3
8004182: 2b01 cmp r3, #1
8004184: d110 bne.n 80041a8 <HAL_FDCAN_Start+0x36>
{
/* Change FDCAN peripheral state */
hfdcan->State = HAL_FDCAN_STATE_BUSY;
8004186: 687b ldr r3, [r7, #4]
8004188: 2202 movs r2, #2
800418a: f883 205c strb.w r2, [r3, #92] ; 0x5c
/* Request leave initialisation */
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
800418e: 687b ldr r3, [r7, #4]
8004190: 681b ldr r3, [r3, #0]
8004192: 699a ldr r2, [r3, #24]
8004194: 687b ldr r3, [r7, #4]
8004196: 681b ldr r3, [r3, #0]
8004198: f022 0201 bic.w r2, r2, #1
800419c: 619a str r2, [r3, #24]
/* Reset the FDCAN ErrorCode */
hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
800419e: 687b ldr r3, [r7, #4]
80041a0: 2200 movs r2, #0
80041a2: 661a str r2, [r3, #96] ; 0x60
/* Return function status */
return HAL_OK;
80041a4: 2300 movs r3, #0
80041a6: e006 b.n 80041b6 <HAL_FDCAN_Start+0x44>
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
80041a8: 687b ldr r3, [r7, #4]
80041aa: 6e1b ldr r3, [r3, #96] ; 0x60
80041ac: f043 0204 orr.w r2, r3, #4
80041b0: 687b ldr r3, [r7, #4]
80041b2: 661a str r2, [r3, #96] ; 0x60
return HAL_ERROR;
80041b4: 2301 movs r3, #1
}
}
80041b6: 4618 mov r0, r3
80041b8: 370c adds r7, #12
80041ba: 46bd mov sp, r7
80041bc: f85d 7b04 ldr.w r7, [sp], #4
80041c0: 4770 bx lr
080041c2 <HAL_FDCAN_AddMessageToTxFifoQ>:
* @param pTxData pointer to a buffer containing the payload of the Tx frame.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader,
uint8_t *pTxData)
{
80041c2: b580 push {r7, lr}
80041c4: b086 sub sp, #24
80041c6: af00 add r7, sp, #0
80041c8: 60f8 str r0, [r7, #12]
80041ca: 60b9 str r1, [r7, #8]
80041cc: 607a str r2, [r7, #4]
assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
80041ce: 68fb ldr r3, [r7, #12]
80041d0: f893 305c ldrb.w r3, [r3, #92] ; 0x5c
80041d4: b2db uxtb r3, r3
80041d6: 2b02 cmp r3, #2
80041d8: d12c bne.n 8004234 <HAL_FDCAN_AddMessageToTxFifoQ+0x72>
{
/* Check that the Tx FIFO/Queue is not full */
if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U)
80041da: 68fb ldr r3, [r7, #12]
80041dc: 681b ldr r3, [r3, #0]
80041de: f8d3 30c4 ldr.w r3, [r3, #196] ; 0xc4
80041e2: f403 1300 and.w r3, r3, #2097152 ; 0x200000
80041e6: 2b00 cmp r3, #0
80041e8: d007 beq.n 80041fa <HAL_FDCAN_AddMessageToTxFifoQ+0x38>
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL;
80041ea: 68fb ldr r3, [r7, #12]
80041ec: 6e1b ldr r3, [r3, #96] ; 0x60
80041ee: f443 7200 orr.w r2, r3, #512 ; 0x200
80041f2: 68fb ldr r3, [r7, #12]
80041f4: 661a str r2, [r3, #96] ; 0x60
return HAL_ERROR;
80041f6: 2301 movs r3, #1
80041f8: e023 b.n 8004242 <HAL_FDCAN_AddMessageToTxFifoQ+0x80>
}
else
{
/* Retrieve the Tx FIFO PutIndex */
PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos);
80041fa: 68fb ldr r3, [r7, #12]
80041fc: 681b ldr r3, [r3, #0]
80041fe: f8d3 30c4 ldr.w r3, [r3, #196] ; 0xc4
8004202: 0c1b lsrs r3, r3, #16
8004204: f003 0303 and.w r3, r3, #3
8004208: 617b str r3, [r7, #20]
/* Add the message to the Tx FIFO/Queue */
FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex);
800420a: 697b ldr r3, [r7, #20]
800420c: 687a ldr r2, [r7, #4]
800420e: 68b9 ldr r1, [r7, #8]
8004210: 68f8 ldr r0, [r7, #12]
8004212: f000 fbd3 bl 80049bc <FDCAN_CopyMessageToRAM>
/* Activate the corresponding transmission request */
hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex);
8004216: 68fb ldr r3, [r7, #12]
8004218: 681b ldr r3, [r3, #0]
800421a: 2101 movs r1, #1
800421c: 697a ldr r2, [r7, #20]
800421e: fa01 f202 lsl.w r2, r1, r2
8004222: f8c3 20cc str.w r2, [r3, #204] ; 0xcc
/* Store the Latest Tx FIFO/Queue Request Buffer Index */
hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex);
8004226: 2201 movs r2, #1
8004228: 697b ldr r3, [r7, #20]
800422a: 409a lsls r2, r3
800422c: 68fb ldr r3, [r7, #12]
800422e: 659a str r2, [r3, #88] ; 0x58
}
/* Return function status */
return HAL_OK;
8004230: 2300 movs r3, #0
8004232: e006 b.n 8004242 <HAL_FDCAN_AddMessageToTxFifoQ+0x80>
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
8004234: 68fb ldr r3, [r7, #12]
8004236: 6e1b ldr r3, [r3, #96] ; 0x60
8004238: f043 0208 orr.w r2, r3, #8
800423c: 68fb ldr r3, [r7, #12]
800423e: 661a str r2, [r3, #96] ; 0x60
return HAL_ERROR;
8004240: 2301 movs r3, #1
}
}
8004242: 4618 mov r0, r3
8004244: 3718 adds r7, #24
8004246: 46bd mov sp, r7
8004248: bd80 pop {r7, pc}
...
0800424c <HAL_FDCAN_GetRxMessage>:
* @param pRxData pointer to a buffer where the payload of the Rx frame will be stored.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
{
800424c: b480 push {r7}
800424e: b08b sub sp, #44 ; 0x2c
8004250: af00 add r7, sp, #0
8004252: 60f8 str r0, [r7, #12]
8004254: 60b9 str r1, [r7, #8]
8004256: 607a str r2, [r7, #4]
8004258: 603b str r3, [r7, #0]
uint32_t *RxAddress;
uint8_t *pData;
uint32_t ByteCounter;
uint32_t GetIndex;
HAL_FDCAN_StateTypeDef state = hfdcan->State;
800425a: 68fb ldr r3, [r7, #12]
800425c: f893 305c ldrb.w r3, [r3, #92] ; 0x5c
8004260: 76fb strb r3, [r7, #27]
/* Check function parameters */
assert_param(IS_FDCAN_RX_FIFO(RxLocation));
if (state == HAL_FDCAN_STATE_BUSY)
8004262: 7efb ldrb r3, [r7, #27]
8004264: 2b02 cmp r3, #2
8004266: f040 80bc bne.w 80043e2 <HAL_FDCAN_GetRxMessage+0x196>
{
if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
800426a: 68bb ldr r3, [r7, #8]
800426c: 2b40 cmp r3, #64 ; 0x40
800426e: d121 bne.n 80042b4 <HAL_FDCAN_GetRxMessage+0x68>
{
/* Check that the Rx FIFO 0 is not empty */
if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U)
8004270: 68fb ldr r3, [r7, #12]
8004272: 681b ldr r3, [r3, #0]
8004274: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8004278: f003 030f and.w r3, r3, #15
800427c: 2b00 cmp r3, #0
800427e: d107 bne.n 8004290 <HAL_FDCAN_GetRxMessage+0x44>
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
8004280: 68fb ldr r3, [r7, #12]
8004282: 6e1b ldr r3, [r3, #96] ; 0x60
8004284: f443 7280 orr.w r2, r3, #256 ; 0x100
8004288: 68fb ldr r3, [r7, #12]
800428a: 661a str r2, [r3, #96] ; 0x60
return HAL_ERROR;
800428c: 2301 movs r3, #1
800428e: e0af b.n 80043f0 <HAL_FDCAN_GetRxMessage+0x1a4>
}
else
{
/* Calculate Rx FIFO 0 element address */
GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
8004290: 68fb ldr r3, [r7, #12]
8004292: 681b ldr r3, [r3, #0]
8004294: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8004298: 0a1b lsrs r3, r3, #8
800429a: f003 0303 and.w r3, r3, #3
800429e: 61fb str r3, [r7, #28]
RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * SRAMCAN_RF0_SIZE));
80042a0: 68fb ldr r3, [r7, #12]
80042a2: 6c99 ldr r1, [r3, #72] ; 0x48
80042a4: 69fa ldr r2, [r7, #28]
80042a6: 4613 mov r3, r2
80042a8: 00db lsls r3, r3, #3
80042aa: 4413 add r3, r2
80042ac: 00db lsls r3, r3, #3
80042ae: 440b add r3, r1
80042b0: 627b str r3, [r7, #36] ; 0x24
80042b2: e020 b.n 80042f6 <HAL_FDCAN_GetRxMessage+0xaa>
}
}
else /* Rx element is assigned to the Rx FIFO 1 */
{
/* Check that the Rx FIFO 1 is not empty */
if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U)
80042b4: 68fb ldr r3, [r7, #12]
80042b6: 681b ldr r3, [r3, #0]
80042b8: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98
80042bc: f003 030f and.w r3, r3, #15
80042c0: 2b00 cmp r3, #0
80042c2: d107 bne.n 80042d4 <HAL_FDCAN_GetRxMessage+0x88>
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
80042c4: 68fb ldr r3, [r7, #12]
80042c6: 6e1b ldr r3, [r3, #96] ; 0x60
80042c8: f443 7280 orr.w r2, r3, #256 ; 0x100
80042cc: 68fb ldr r3, [r7, #12]
80042ce: 661a str r2, [r3, #96] ; 0x60
return HAL_ERROR;
80042d0: 2301 movs r3, #1
80042d2: e08d b.n 80043f0 <HAL_FDCAN_GetRxMessage+0x1a4>
}
else
{
/* Calculate Rx FIFO 1 element address */
GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
80042d4: 68fb ldr r3, [r7, #12]
80042d6: 681b ldr r3, [r3, #0]
80042d8: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98
80042dc: 0a1b lsrs r3, r3, #8
80042de: f003 0303 and.w r3, r3, #3
80042e2: 61fb str r3, [r7, #28]
RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * SRAMCAN_RF1_SIZE));
80042e4: 68fb ldr r3, [r7, #12]
80042e6: 6cd9 ldr r1, [r3, #76] ; 0x4c
80042e8: 69fa ldr r2, [r7, #28]
80042ea: 4613 mov r3, r2
80042ec: 00db lsls r3, r3, #3
80042ee: 4413 add r3, r2
80042f0: 00db lsls r3, r3, #3
80042f2: 440b add r3, r1
80042f4: 627b str r3, [r7, #36] ; 0x24
}
}
/* Retrieve IdType */
pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD;
80042f6: 6a7b ldr r3, [r7, #36] ; 0x24
80042f8: 681b ldr r3, [r3, #0]
80042fa: f003 4280 and.w r2, r3, #1073741824 ; 0x40000000
80042fe: 687b ldr r3, [r7, #4]
8004300: 605a str r2, [r3, #4]
/* Retrieve Identifier */
if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
8004302: 687b ldr r3, [r7, #4]
8004304: 685b ldr r3, [r3, #4]
8004306: 2b00 cmp r3, #0
8004308: d107 bne.n 800431a <HAL_FDCAN_GetRxMessage+0xce>
{
pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
800430a: 6a7b ldr r3, [r7, #36] ; 0x24
800430c: 681b ldr r3, [r3, #0]
800430e: 0c9b lsrs r3, r3, #18
8004310: f3c3 020a ubfx r2, r3, #0, #11
8004314: 687b ldr r3, [r7, #4]
8004316: 601a str r2, [r3, #0]
8004318: e005 b.n 8004326 <HAL_FDCAN_GetRxMessage+0xda>
}
else /* Extended ID element */
{
pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID);
800431a: 6a7b ldr r3, [r7, #36] ; 0x24
800431c: 681b ldr r3, [r3, #0]
800431e: f023 4260 bic.w r2, r3, #3758096384 ; 0xe0000000
8004322: 687b ldr r3, [r7, #4]
8004324: 601a str r2, [r3, #0]
}
/* Retrieve RxFrameType */
pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR);
8004326: 6a7b ldr r3, [r7, #36] ; 0x24
8004328: 681b ldr r3, [r3, #0]
800432a: f003 5200 and.w r2, r3, #536870912 ; 0x20000000
800432e: 687b ldr r3, [r7, #4]
8004330: 609a str r2, [r3, #8]
/* Retrieve ErrorStateIndicator */
pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI);
8004332: 6a7b ldr r3, [r7, #36] ; 0x24
8004334: 681b ldr r3, [r3, #0]
8004336: f003 4200 and.w r2, r3, #2147483648 ; 0x80000000
800433a: 687b ldr r3, [r7, #4]
800433c: 611a str r2, [r3, #16]
/* Increment RxAddress pointer to second word of Rx FIFO element */
RxAddress++;
800433e: 6a7b ldr r3, [r7, #36] ; 0x24
8004340: 3304 adds r3, #4
8004342: 627b str r3, [r7, #36] ; 0x24
/* Retrieve RxTimestamp */
pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
8004344: 6a7b ldr r3, [r7, #36] ; 0x24
8004346: 681b ldr r3, [r3, #0]
8004348: b29a uxth r2, r3
800434a: 687b ldr r3, [r7, #4]
800434c: 61da str r2, [r3, #28]
/* Retrieve DataLength */
pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC);
800434e: 6a7b ldr r3, [r7, #36] ; 0x24
8004350: 681b ldr r3, [r3, #0]
8004352: f403 2270 and.w r2, r3, #983040 ; 0xf0000
8004356: 687b ldr r3, [r7, #4]
8004358: 60da str r2, [r3, #12]
/* Retrieve BitRateSwitch */
pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
800435a: 6a7b ldr r3, [r7, #36] ; 0x24
800435c: 681b ldr r3, [r3, #0]
800435e: f403 1280 and.w r2, r3, #1048576 ; 0x100000
8004362: 687b ldr r3, [r7, #4]
8004364: 615a str r2, [r3, #20]
/* Retrieve FDFormat */
pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);
8004366: 6a7b ldr r3, [r7, #36] ; 0x24
8004368: 681b ldr r3, [r3, #0]
800436a: f403 1200 and.w r2, r3, #2097152 ; 0x200000
800436e: 687b ldr r3, [r7, #4]
8004370: 619a str r2, [r3, #24]
/* Retrieve FilterIndex */
pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24U);
8004372: 6a7b ldr r3, [r7, #36] ; 0x24
8004374: 681b ldr r3, [r3, #0]
8004376: 0e1b lsrs r3, r3, #24
8004378: f003 027f and.w r2, r3, #127 ; 0x7f
800437c: 687b ldr r3, [r7, #4]
800437e: 621a str r2, [r3, #32]
/* Retrieve NonMatchingFrame */
pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31U);
8004380: 6a7b ldr r3, [r7, #36] ; 0x24
8004382: 681b ldr r3, [r3, #0]
8004384: 0fda lsrs r2, r3, #31
8004386: 687b ldr r3, [r7, #4]
8004388: 625a str r2, [r3, #36] ; 0x24
/* Increment RxAddress pointer to payload of Rx FIFO element */
RxAddress++;
800438a: 6a7b ldr r3, [r7, #36] ; 0x24
800438c: 3304 adds r3, #4
800438e: 627b str r3, [r7, #36] ; 0x24
/* Retrieve Rx payload */
pData = (uint8_t *)RxAddress;
8004390: 6a7b ldr r3, [r7, #36] ; 0x24
8004392: 617b str r3, [r7, #20]
for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16U]; ByteCounter++)
8004394: 2300 movs r3, #0
8004396: 623b str r3, [r7, #32]
8004398: e00a b.n 80043b0 <HAL_FDCAN_GetRxMessage+0x164>
{
pRxData[ByteCounter] = pData[ByteCounter];
800439a: 697a ldr r2, [r7, #20]
800439c: 6a3b ldr r3, [r7, #32]
800439e: 441a add r2, r3
80043a0: 6839 ldr r1, [r7, #0]
80043a2: 6a3b ldr r3, [r7, #32]
80043a4: 440b add r3, r1
80043a6: 7812 ldrb r2, [r2, #0]
80043a8: 701a strb r2, [r3, #0]
for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16U]; ByteCounter++)
80043aa: 6a3b ldr r3, [r7, #32]
80043ac: 3301 adds r3, #1
80043ae: 623b str r3, [r7, #32]
80043b0: 687b ldr r3, [r7, #4]
80043b2: 68db ldr r3, [r3, #12]
80043b4: 0c1b lsrs r3, r3, #16
80043b6: 4a11 ldr r2, [pc, #68] ; (80043fc <HAL_FDCAN_GetRxMessage+0x1b0>)
80043b8: 5cd3 ldrb r3, [r2, r3]
80043ba: 461a mov r2, r3
80043bc: 6a3b ldr r3, [r7, #32]
80043be: 4293 cmp r3, r2
80043c0: d3eb bcc.n 800439a <HAL_FDCAN_GetRxMessage+0x14e>
}
if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
80043c2: 68bb ldr r3, [r7, #8]
80043c4: 2b40 cmp r3, #64 ; 0x40
80043c6: d105 bne.n 80043d4 <HAL_FDCAN_GetRxMessage+0x188>
{
/* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */
hfdcan->Instance->RXF0A = GetIndex;
80043c8: 68fb ldr r3, [r7, #12]
80043ca: 681b ldr r3, [r3, #0]
80043cc: 69fa ldr r2, [r7, #28]
80043ce: f8c3 2094 str.w r2, [r3, #148] ; 0x94
80043d2: e004 b.n 80043de <HAL_FDCAN_GetRxMessage+0x192>
}
else /* Rx element is assigned to the Rx FIFO 1 */
{
/* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */
hfdcan->Instance->RXF1A = GetIndex;
80043d4: 68fb ldr r3, [r7, #12]
80043d6: 681b ldr r3, [r3, #0]
80043d8: 69fa ldr r2, [r7, #28]
80043da: f8c3 209c str.w r2, [r3, #156] ; 0x9c
}
/* Return function status */
return HAL_OK;
80043de: 2300 movs r3, #0
80043e0: e006 b.n 80043f0 <HAL_FDCAN_GetRxMessage+0x1a4>
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
80043e2: 68fb ldr r3, [r7, #12]
80043e4: 6e1b ldr r3, [r3, #96] ; 0x60
80043e6: f043 0208 orr.w r2, r3, #8
80043ea: 68fb ldr r3, [r7, #12]
80043ec: 661a str r2, [r3, #96] ; 0x60
return HAL_ERROR;
80043ee: 2301 movs r3, #1
}
}
80043f0: 4618 mov r0, r3
80043f2: 372c adds r7, #44 ; 0x2c
80043f4: 46bd mov sp, r7
80043f6: f85d 7b04 ldr.w r7, [sp], #4
80043fa: 4770 bx lr
80043fc: 08007cc0 .word 0x08007cc0
08004400 <HAL_FDCAN_ActivateNotification>:
* - FDCAN_IT_TX_ABORT_COMPLETE
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
uint32_t BufferIndexes)
{
8004400: b480 push {r7}
8004402: b087 sub sp, #28
8004404: af00 add r7, sp, #0
8004406: 60f8 str r0, [r7, #12]
8004408: 60b9 str r1, [r7, #8]
800440a: 607a str r2, [r7, #4]
HAL_FDCAN_StateTypeDef state = hfdcan->State;
800440c: 68fb ldr r3, [r7, #12]
800440e: f893 305c ldrb.w r3, [r3, #92] ; 0x5c
8004412: 75fb strb r3, [r7, #23]
if ((ActiveITs & (FDCAN_IT_TX_COMPLETE | FDCAN_IT_TX_ABORT_COMPLETE)) != 0U)
{
assert_param(IS_FDCAN_TX_LOCATION_LIST(BufferIndexes));
}
if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
8004414: 7dfb ldrb r3, [r7, #23]
8004416: 2b01 cmp r3, #1
8004418: d003 beq.n 8004422 <HAL_FDCAN_ActivateNotification+0x22>
800441a: 7dfb ldrb r3, [r7, #23]
800441c: 2b02 cmp r3, #2
800441e: f040 80c8 bne.w 80045b2 <HAL_FDCAN_ActivateNotification+0x1b2>
{
/* Get interrupts line selection */
ITs_lines_selection = hfdcan->Instance->ILS;
8004422: 68fb ldr r3, [r7, #12]
8004424: 681b ldr r3, [r3, #0]
8004426: 6d9b ldr r3, [r3, #88] ; 0x58
8004428: 613b str r3, [r7, #16]
/* Enable Interrupt lines */
if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U)
800442a: 68bb ldr r3, [r7, #8]
800442c: f003 0307 and.w r3, r3, #7
8004430: 2b00 cmp r3, #0
8004432: d004 beq.n 800443e <HAL_FDCAN_ActivateNotification+0x3e>
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) == 0U)) || \
8004434: 693b ldr r3, [r7, #16]
8004436: f003 0301 and.w r3, r3, #1
800443a: 2b00 cmp r3, #0
800443c: d03b beq.n 80044b6 <HAL_FDCAN_ActivateNotification+0xb6>
(((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U)
800443e: 68bb ldr r3, [r7, #8]
8004440: f003 0338 and.w r3, r3, #56 ; 0x38
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) == 0U)) || \
8004444: 2b00 cmp r3, #0
8004446: d004 beq.n 8004452 <HAL_FDCAN_ActivateNotification+0x52>
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) == 0U)) || \
8004448: 693b ldr r3, [r7, #16]
800444a: f003 0302 and.w r3, r3, #2
800444e: 2b00 cmp r3, #0
8004450: d031 beq.n 80044b6 <HAL_FDCAN_ActivateNotification+0xb6>
(((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U)
8004452: 68bb ldr r3, [r7, #8]
8004454: f403 73e0 and.w r3, r3, #448 ; 0x1c0
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) == 0U)) || \
8004458: 2b00 cmp r3, #0
800445a: d004 beq.n 8004466 <HAL_FDCAN_ActivateNotification+0x66>
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) == 0U)) || \
800445c: 693b ldr r3, [r7, #16]
800445e: f003 0304 and.w r3, r3, #4
8004462: 2b00 cmp r3, #0
8004464: d027 beq.n 80044b6 <HAL_FDCAN_ActivateNotification+0xb6>
(((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U)
8004466: 68bb ldr r3, [r7, #8]
8004468: f403 53f0 and.w r3, r3, #7680 ; 0x1e00
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) == 0U)) || \
800446c: 2b00 cmp r3, #0
800446e: d004 beq.n 800447a <HAL_FDCAN_ActivateNotification+0x7a>
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) || \
8004470: 693b ldr r3, [r7, #16]
8004472: f003 0308 and.w r3, r3, #8
8004476: 2b00 cmp r3, #0
8004478: d01d beq.n 80044b6 <HAL_FDCAN_ActivateNotification+0xb6>
(((ActiveITs & FDCAN_IT_LIST_MISC) != 0U)
800447a: 68bb ldr r3, [r7, #8]
800447c: f403 4360 and.w r3, r3, #57344 ; 0xe000
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) || \
8004480: 2b00 cmp r3, #0
8004482: d004 beq.n 800448e <HAL_FDCAN_ActivateNotification+0x8e>
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) == 0U)) || \
8004484: 693b ldr r3, [r7, #16]
8004486: f003 0310 and.w r3, r3, #16
800448a: 2b00 cmp r3, #0
800448c: d013 beq.n 80044b6 <HAL_FDCAN_ActivateNotification+0xb6>
(((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
800448e: 68bb ldr r3, [r7, #8]
8004490: f403 3340 and.w r3, r3, #196608 ; 0x30000
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) == 0U)) || \
8004494: 2b00 cmp r3, #0
8004496: d004 beq.n 80044a2 <HAL_FDCAN_ActivateNotification+0xa2>
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \
8004498: 693b ldr r3, [r7, #16]
800449a: f003 0320 and.w r3, r3, #32
800449e: 2b00 cmp r3, #0
80044a0: d009 beq.n 80044b6 <HAL_FDCAN_ActivateNotification+0xb6>
(((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
80044a2: 68bb ldr r3, [r7, #8]
80044a4: f403 037c and.w r3, r3, #16515072 ; 0xfc0000
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \
80044a8: 2b00 cmp r3, #0
80044aa: d00c beq.n 80044c6 <HAL_FDCAN_ActivateNotification+0xc6>
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U)))
80044ac: 693b ldr r3, [r7, #16]
80044ae: f003 0340 and.w r3, r3, #64 ; 0x40
80044b2: 2b00 cmp r3, #0
80044b4: d107 bne.n 80044c6 <HAL_FDCAN_ActivateNotification+0xc6>
{
/* Enable Interrupt line 0 */
SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
80044b6: 68fb ldr r3, [r7, #12]
80044b8: 681b ldr r3, [r3, #0]
80044ba: 6dda ldr r2, [r3, #92] ; 0x5c
80044bc: 68fb ldr r3, [r7, #12]
80044be: 681b ldr r3, [r3, #0]
80044c0: f042 0201 orr.w r2, r2, #1
80044c4: 65da str r2, [r3, #92] ; 0x5c
}
if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U)
80044c6: 68bb ldr r3, [r7, #8]
80044c8: f003 0307 and.w r3, r3, #7
80044cc: 2b00 cmp r3, #0
80044ce: d004 beq.n 80044da <HAL_FDCAN_ActivateNotification+0xda>
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) != 0U)) || \
80044d0: 693b ldr r3, [r7, #16]
80044d2: f003 0301 and.w r3, r3, #1
80044d6: 2b00 cmp r3, #0
80044d8: d13b bne.n 8004552 <HAL_FDCAN_ActivateNotification+0x152>
(((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U)
80044da: 68bb ldr r3, [r7, #8]
80044dc: f003 0338 and.w r3, r3, #56 ; 0x38
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) != 0U)) || \
80044e0: 2b00 cmp r3, #0
80044e2: d004 beq.n 80044ee <HAL_FDCAN_ActivateNotification+0xee>
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) != 0U)) || \
80044e4: 693b ldr r3, [r7, #16]
80044e6: f003 0302 and.w r3, r3, #2
80044ea: 2b00 cmp r3, #0
80044ec: d131 bne.n 8004552 <HAL_FDCAN_ActivateNotification+0x152>
(((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U)
80044ee: 68bb ldr r3, [r7, #8]
80044f0: f403 73e0 and.w r3, r3, #448 ; 0x1c0
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) != 0U)) || \
80044f4: 2b00 cmp r3, #0
80044f6: d004 beq.n 8004502 <HAL_FDCAN_ActivateNotification+0x102>
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) != 0U)) || \
80044f8: 693b ldr r3, [r7, #16]
80044fa: f003 0304 and.w r3, r3, #4
80044fe: 2b00 cmp r3, #0
8004500: d127 bne.n 8004552 <HAL_FDCAN_ActivateNotification+0x152>
(((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U)
8004502: 68bb ldr r3, [r7, #8]
8004504: f403 53f0 and.w r3, r3, #7680 ; 0x1e00
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) != 0U)) || \
8004508: 2b00 cmp r3, #0
800450a: d004 beq.n 8004516 <HAL_FDCAN_ActivateNotification+0x116>
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) || \
800450c: 693b ldr r3, [r7, #16]
800450e: f003 0308 and.w r3, r3, #8
8004512: 2b00 cmp r3, #0
8004514: d11d bne.n 8004552 <HAL_FDCAN_ActivateNotification+0x152>
(((ActiveITs & FDCAN_IT_LIST_MISC) != 0U)
8004516: 68bb ldr r3, [r7, #8]
8004518: f403 4360 and.w r3, r3, #57344 ; 0xe000
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) || \
800451c: 2b00 cmp r3, #0
800451e: d004 beq.n 800452a <HAL_FDCAN_ActivateNotification+0x12a>
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) != 0U)) || \
8004520: 693b ldr r3, [r7, #16]
8004522: f003 0310 and.w r3, r3, #16
8004526: 2b00 cmp r3, #0
8004528: d113 bne.n 8004552 <HAL_FDCAN_ActivateNotification+0x152>
(((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
800452a: 68bb ldr r3, [r7, #8]
800452c: f403 3340 and.w r3, r3, #196608 ; 0x30000
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) != 0U)) || \
8004530: 2b00 cmp r3, #0
8004532: d004 beq.n 800453e <HAL_FDCAN_ActivateNotification+0x13e>
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \
8004534: 693b ldr r3, [r7, #16]
8004536: f003 0320 and.w r3, r3, #32
800453a: 2b00 cmp r3, #0
800453c: d109 bne.n 8004552 <HAL_FDCAN_ActivateNotification+0x152>
(((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
800453e: 68bb ldr r3, [r7, #8]
8004540: f403 037c and.w r3, r3, #16515072 ; 0xfc0000
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \
8004544: 2b00 cmp r3, #0
8004546: d00c beq.n 8004562 <HAL_FDCAN_ActivateNotification+0x162>
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U)))
8004548: 693b ldr r3, [r7, #16]
800454a: f003 0340 and.w r3, r3, #64 ; 0x40
800454e: 2b00 cmp r3, #0
8004550: d007 beq.n 8004562 <HAL_FDCAN_ActivateNotification+0x162>
{
/* Enable Interrupt line 1 */
SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
8004552: 68fb ldr r3, [r7, #12]
8004554: 681b ldr r3, [r3, #0]
8004556: 6dda ldr r2, [r3, #92] ; 0x5c
8004558: 68fb ldr r3, [r7, #12]
800455a: 681b ldr r3, [r3, #0]
800455c: f042 0202 orr.w r2, r2, #2
8004560: 65da str r2, [r3, #92] ; 0x5c
}
if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
8004562: 68bb ldr r3, [r7, #8]
8004564: f003 0380 and.w r3, r3, #128 ; 0x80
8004568: 2b00 cmp r3, #0
800456a: d009 beq.n 8004580 <HAL_FDCAN_ActivateNotification+0x180>
{
/* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register,
but interrupt will only occur if TC is enabled in IE register */
SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
800456c: 68fb ldr r3, [r7, #12]
800456e: 681b ldr r3, [r3, #0]
8004570: f8d3 10dc ldr.w r1, [r3, #220] ; 0xdc
8004574: 68fb ldr r3, [r7, #12]
8004576: 681b ldr r3, [r3, #0]
8004578: 687a ldr r2, [r7, #4]
800457a: 430a orrs r2, r1
800457c: f8c3 20dc str.w r2, [r3, #220] ; 0xdc
}
if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
8004580: 68bb ldr r3, [r7, #8]
8004582: f403 7380 and.w r3, r3, #256 ; 0x100
8004586: 2b00 cmp r3, #0
8004588: d009 beq.n 800459e <HAL_FDCAN_ActivateNotification+0x19e>
{
/* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register,
but interrupt will only occur if TCF is enabled in IE register */
SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
800458a: 68fb ldr r3, [r7, #12]
800458c: 681b ldr r3, [r3, #0]
800458e: f8d3 10e0 ldr.w r1, [r3, #224] ; 0xe0
8004592: 68fb ldr r3, [r7, #12]
8004594: 681b ldr r3, [r3, #0]
8004596: 687a ldr r2, [r7, #4]
8004598: 430a orrs r2, r1
800459a: f8c3 20e0 str.w r2, [r3, #224] ; 0xe0
}
/* Enable the selected interrupts */
__HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs);
800459e: 68fb ldr r3, [r7, #12]
80045a0: 681b ldr r3, [r3, #0]
80045a2: 6d59 ldr r1, [r3, #84] ; 0x54
80045a4: 68fb ldr r3, [r7, #12]
80045a6: 681b ldr r3, [r3, #0]
80045a8: 68ba ldr r2, [r7, #8]
80045aa: 430a orrs r2, r1
80045ac: 655a str r2, [r3, #84] ; 0x54
/* Return function status */
return HAL_OK;
80045ae: 2300 movs r3, #0
80045b0: e006 b.n 80045c0 <HAL_FDCAN_ActivateNotification+0x1c0>
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
80045b2: 68fb ldr r3, [r7, #12]
80045b4: 6e1b ldr r3, [r3, #96] ; 0x60
80045b6: f043 0202 orr.w r2, r3, #2
80045ba: 68fb ldr r3, [r7, #12]
80045bc: 661a str r2, [r3, #96] ; 0x60
return HAL_ERROR;
80045be: 2301 movs r3, #1
}
}
80045c0: 4618 mov r0, r3
80045c2: 371c adds r7, #28
80045c4: 46bd mov sp, r7
80045c6: f85d 7b04 ldr.w r7, [sp], #4
80045ca: 4770 bx lr
080045cc <HAL_FDCAN_IRQHandler>:
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
{
80045cc: b580 push {r7, lr}
80045ce: b08a sub sp, #40 ; 0x28
80045d0: af00 add r7, sp, #0
80045d2: 6078 str r0, [r7, #4]
uint32_t Errors;
uint32_t ErrorStatusITs;
uint32_t TransmittedBuffers;
uint32_t AbortedBuffers;
TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
80045d4: 687b ldr r3, [r7, #4]
80045d6: 681b ldr r3, [r3, #0]
80045d8: 6d1b ldr r3, [r3, #80] ; 0x50
80045da: f403 53e0 and.w r3, r3, #7168 ; 0x1c00
80045de: 627b str r3, [r7, #36] ; 0x24
TxEventFifoITs &= hfdcan->Instance->IE;
80045e0: 687b ldr r3, [r7, #4]
80045e2: 681b ldr r3, [r3, #0]
80045e4: 6d5b ldr r3, [r3, #84] ; 0x54
80045e6: 6a7a ldr r2, [r7, #36] ; 0x24
80045e8: 4013 ands r3, r2
80045ea: 627b str r3, [r7, #36] ; 0x24
RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK;
80045ec: 687b ldr r3, [r7, #4]
80045ee: 681b ldr r3, [r3, #0]
80045f0: 6d1b ldr r3, [r3, #80] ; 0x50
80045f2: f003 0307 and.w r3, r3, #7
80045f6: 623b str r3, [r7, #32]
RxFifo0ITs &= hfdcan->Instance->IE;
80045f8: 687b ldr r3, [r7, #4]
80045fa: 681b ldr r3, [r3, #0]
80045fc: 6d5b ldr r3, [r3, #84] ; 0x54
80045fe: 6a3a ldr r2, [r7, #32]
8004600: 4013 ands r3, r2
8004602: 623b str r3, [r7, #32]
RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK;
8004604: 687b ldr r3, [r7, #4]
8004606: 681b ldr r3, [r3, #0]
8004608: 6d1b ldr r3, [r3, #80] ; 0x50
800460a: f003 0338 and.w r3, r3, #56 ; 0x38
800460e: 61fb str r3, [r7, #28]
RxFifo1ITs &= hfdcan->Instance->IE;
8004610: 687b ldr r3, [r7, #4]
8004612: 681b ldr r3, [r3, #0]
8004614: 6d5b ldr r3, [r3, #84] ; 0x54
8004616: 69fa ldr r2, [r7, #28]
8004618: 4013 ands r3, r2
800461a: 61fb str r3, [r7, #28]
Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK;
800461c: 687b ldr r3, [r7, #4]
800461e: 681b ldr r3, [r3, #0]
8004620: 6d1b ldr r3, [r3, #80] ; 0x50
8004622: f403 0371 and.w r3, r3, #15794176 ; 0xf10000
8004626: 61bb str r3, [r7, #24]
Errors &= hfdcan->Instance->IE;
8004628: 687b ldr r3, [r7, #4]
800462a: 681b ldr r3, [r3, #0]
800462c: 6d5b ldr r3, [r3, #84] ; 0x54
800462e: 69ba ldr r2, [r7, #24]
8004630: 4013 ands r3, r2
8004632: 61bb str r3, [r7, #24]
ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
8004634: 687b ldr r3, [r7, #4]
8004636: 681b ldr r3, [r3, #0]
8004638: 6d1b ldr r3, [r3, #80] ; 0x50
800463a: f403 2360 and.w r3, r3, #917504 ; 0xe0000
800463e: 617b str r3, [r7, #20]
ErrorStatusITs &= hfdcan->Instance->IE;
8004640: 687b ldr r3, [r7, #4]
8004642: 681b ldr r3, [r3, #0]
8004644: 6d5b ldr r3, [r3, #84] ; 0x54
8004646: 697a ldr r2, [r7, #20]
8004648: 4013 ands r3, r2
800464a: 617b str r3, [r7, #20]
/* High Priority Message interrupt management *******************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != 0U)
800464c: 687b ldr r3, [r7, #4]
800464e: 681b ldr r3, [r3, #0]
8004650: 6d1b ldr r3, [r3, #80] ; 0x50
8004652: f003 0340 and.w r3, r3, #64 ; 0x40
8004656: 2b00 cmp r3, #0
8004658: d00d beq.n 8004676 <HAL_FDCAN_IRQHandler+0xaa>
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != 0U)
800465a: 687b ldr r3, [r7, #4]
800465c: 681b ldr r3, [r3, #0]
800465e: 6d5b ldr r3, [r3, #84] ; 0x54
8004660: f003 0340 and.w r3, r3, #64 ; 0x40
8004664: 2b00 cmp r3, #0
8004666: d006 beq.n 8004676 <HAL_FDCAN_IRQHandler+0xaa>
{
/* Clear the High Priority Message flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
8004668: 687b ldr r3, [r7, #4]
800466a: 681b ldr r3, [r3, #0]
800466c: 2240 movs r2, #64 ; 0x40
800466e: 651a str r2, [r3, #80] ; 0x50
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->HighPriorityMessageCallback(hfdcan);
#else
/* High Priority Message Callback */
HAL_FDCAN_HighPriorityMessageCallback(hfdcan);
8004670: 6878 ldr r0, [r7, #4]
8004672: f000 f92e bl 80048d2 <HAL_FDCAN_HighPriorityMessageCallback>
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
}
/* Transmission Abort interrupt management **********************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE) != 0U)
8004676: 687b ldr r3, [r7, #4]
8004678: 681b ldr r3, [r3, #0]
800467a: 6d1b ldr r3, [r3, #80] ; 0x50
800467c: f403 7380 and.w r3, r3, #256 ; 0x100
8004680: 2b00 cmp r3, #0
8004682: d01b beq.n 80046bc <HAL_FDCAN_IRQHandler+0xf0>
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
8004684: 687b ldr r3, [r7, #4]
8004686: 681b ldr r3, [r3, #0]
8004688: 6d5b ldr r3, [r3, #84] ; 0x54
800468a: f403 7380 and.w r3, r3, #256 ; 0x100
800468e: 2b00 cmp r3, #0
8004690: d014 beq.n 80046bc <HAL_FDCAN_IRQHandler+0xf0>
{
/* List of aborted monitored buffers */
AbortedBuffers = hfdcan->Instance->TXBCF;
8004692: 687b ldr r3, [r7, #4]
8004694: 681b ldr r3, [r3, #0]
8004696: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8
800469a: 613b str r3, [r7, #16]
AbortedBuffers &= hfdcan->Instance->TXBCIE;
800469c: 687b ldr r3, [r7, #4]
800469e: 681b ldr r3, [r3, #0]
80046a0: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0
80046a4: 693a ldr r2, [r7, #16]
80046a6: 4013 ands r3, r2
80046a8: 613b str r3, [r7, #16]
/* Clear the Transmission Cancellation flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE);
80046aa: 687b ldr r3, [r7, #4]
80046ac: 681b ldr r3, [r3, #0]
80046ae: f44f 7280 mov.w r2, #256 ; 0x100
80046b2: 651a str r2, [r3, #80] ; 0x50
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers);
#else
/* Transmission Cancellation Callback */
HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers);
80046b4: 6939 ldr r1, [r7, #16]
80046b6: 6878 ldr r0, [r7, #4]
80046b8: f000 f8ec bl 8004894 <HAL_FDCAN_TxBufferAbortCallback>
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
}
/* Tx event FIFO interrupts management **************************************/
if (TxEventFifoITs != 0U)
80046bc: 6a7b ldr r3, [r7, #36] ; 0x24
80046be: 2b00 cmp r3, #0
80046c0: d007 beq.n 80046d2 <HAL_FDCAN_IRQHandler+0x106>
{
/* Clear the Tx Event FIFO flags */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs);
80046c2: 687b ldr r3, [r7, #4]
80046c4: 681b ldr r3, [r3, #0]
80046c6: 6a7a ldr r2, [r7, #36] ; 0x24
80046c8: 651a str r2, [r3, #80] ; 0x50
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs);
#else
/* Tx Event FIFO Callback */
HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs);
80046ca: 6a79 ldr r1, [r7, #36] ; 0x24
80046cc: 6878 ldr r0, [r7, #4]
80046ce: f000 f8b6 bl 800483e <HAL_FDCAN_TxEventFifoCallback>
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
/* Rx FIFO 0 interrupts management ******************************************/
if (RxFifo0ITs != 0U)
80046d2: 6a3b ldr r3, [r7, #32]
80046d4: 2b00 cmp r3, #0
80046d6: d007 beq.n 80046e8 <HAL_FDCAN_IRQHandler+0x11c>
{
/* Clear the Rx FIFO 0 flags */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs);
80046d8: 687b ldr r3, [r7, #4]
80046da: 681b ldr r3, [r3, #0]
80046dc: 6a3a ldr r2, [r7, #32]
80046de: 651a str r2, [r3, #80] ; 0x50
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs);
#else
/* Rx FIFO 0 Callback */
HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs);
80046e0: 6a39 ldr r1, [r7, #32]
80046e2: 6878 ldr r0, [r7, #4]
80046e4: f7fc fa0a bl 8000afc <HAL_FDCAN_RxFifo0Callback>
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
/* Rx FIFO 1 interrupts management ******************************************/
if (RxFifo1ITs != 0U)
80046e8: 69fb ldr r3, [r7, #28]
80046ea: 2b00 cmp r3, #0
80046ec: d007 beq.n 80046fe <HAL_FDCAN_IRQHandler+0x132>
{
/* Clear the Rx FIFO 1 flags */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs);
80046ee: 687b ldr r3, [r7, #4]
80046f0: 681b ldr r3, [r3, #0]
80046f2: 69fa ldr r2, [r7, #28]
80046f4: 651a str r2, [r3, #80] ; 0x50
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs);
#else
/* Rx FIFO 1 Callback */
HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs);
80046f6: 69f9 ldr r1, [r7, #28]
80046f8: 6878 ldr r0, [r7, #4]
80046fa: f000 f8ab bl 8004854 <HAL_FDCAN_RxFifo1Callback>
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
/* Tx FIFO empty interrupt management ***************************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY) != 0U)
80046fe: 687b ldr r3, [r7, #4]
8004700: 681b ldr r3, [r3, #0]
8004702: 6d1b ldr r3, [r3, #80] ; 0x50
8004704: f403 7300 and.w r3, r3, #512 ; 0x200
8004708: 2b00 cmp r3, #0
800470a: d00e beq.n 800472a <HAL_FDCAN_IRQHandler+0x15e>
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_FIFO_EMPTY) != 0U)
800470c: 687b ldr r3, [r7, #4]
800470e: 681b ldr r3, [r3, #0]
8004710: 6d5b ldr r3, [r3, #84] ; 0x54
8004712: f403 7300 and.w r3, r3, #512 ; 0x200
8004716: 2b00 cmp r3, #0
8004718: d007 beq.n 800472a <HAL_FDCAN_IRQHandler+0x15e>
{
/* Clear the Tx FIFO empty flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
800471a: 687b ldr r3, [r7, #4]
800471c: 681b ldr r3, [r3, #0]
800471e: f44f 7200 mov.w r2, #512 ; 0x200
8004722: 651a str r2, [r3, #80] ; 0x50
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->TxFifoEmptyCallback(hfdcan);
#else
/* Tx FIFO empty Callback */
HAL_FDCAN_TxFifoEmptyCallback(hfdcan);
8004724: 6878 ldr r0, [r7, #4]
8004726: f000 f8a0 bl 800486a <HAL_FDCAN_TxFifoEmptyCallback>
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
}
/* Transmission Complete interrupt management *******************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE) != 0U)
800472a: 687b ldr r3, [r7, #4]
800472c: 681b ldr r3, [r3, #0]
800472e: 6d1b ldr r3, [r3, #80] ; 0x50
8004730: f003 0380 and.w r3, r3, #128 ; 0x80
8004734: 2b00 cmp r3, #0
8004736: d01a beq.n 800476e <HAL_FDCAN_IRQHandler+0x1a2>
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_COMPLETE) != 0U)
8004738: 687b ldr r3, [r7, #4]
800473a: 681b ldr r3, [r3, #0]
800473c: 6d5b ldr r3, [r3, #84] ; 0x54
800473e: f003 0380 and.w r3, r3, #128 ; 0x80
8004742: 2b00 cmp r3, #0
8004744: d013 beq.n 800476e <HAL_FDCAN_IRQHandler+0x1a2>
{
/* List of transmitted monitored buffers */
TransmittedBuffers = hfdcan->Instance->TXBTO;
8004746: 687b ldr r3, [r7, #4]
8004748: 681b ldr r3, [r3, #0]
800474a: f8d3 30d4 ldr.w r3, [r3, #212] ; 0xd4
800474e: 60fb str r3, [r7, #12]
TransmittedBuffers &= hfdcan->Instance->TXBTIE;
8004750: 687b ldr r3, [r7, #4]
8004752: 681b ldr r3, [r3, #0]
8004754: f8d3 30dc ldr.w r3, [r3, #220] ; 0xdc
8004758: 68fa ldr r2, [r7, #12]
800475a: 4013 ands r3, r2
800475c: 60fb str r3, [r7, #12]
/* Clear the Transmission Complete flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE);
800475e: 687b ldr r3, [r7, #4]
8004760: 681b ldr r3, [r3, #0]
8004762: 2280 movs r2, #128 ; 0x80
8004764: 651a str r2, [r3, #80] ; 0x50
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
#else
/* Transmission Complete Callback */
HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
8004766: 68f9 ldr r1, [r7, #12]
8004768: 6878 ldr r0, [r7, #4]
800476a: f000 f888 bl 800487e <HAL_FDCAN_TxBufferCompleteCallback>
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
}
/* Timestamp Wraparound interrupt management ********************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != 0U)
800476e: 687b ldr r3, [r7, #4]
8004770: 681b ldr r3, [r3, #0]
8004772: 6d1b ldr r3, [r3, #80] ; 0x50
8004774: f403 5300 and.w r3, r3, #8192 ; 0x2000
8004778: 2b00 cmp r3, #0
800477a: d00e beq.n 800479a <HAL_FDCAN_IRQHandler+0x1ce>
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMESTAMP_WRAPAROUND) != 0U)
800477c: 687b ldr r3, [r7, #4]
800477e: 681b ldr r3, [r3, #0]
8004780: 6d5b ldr r3, [r3, #84] ; 0x54
8004782: f403 5300 and.w r3, r3, #8192 ; 0x2000
8004786: 2b00 cmp r3, #0
8004788: d007 beq.n 800479a <HAL_FDCAN_IRQHandler+0x1ce>
{
/* Clear the Timestamp Wraparound flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
800478a: 687b ldr r3, [r7, #4]
800478c: 681b ldr r3, [r3, #0]
800478e: f44f 5200 mov.w r2, #8192 ; 0x2000
8004792: 651a str r2, [r3, #80] ; 0x50
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->TimestampWraparoundCallback(hfdcan);
#else
/* Timestamp Wraparound Callback */
HAL_FDCAN_TimestampWraparoundCallback(hfdcan);
8004794: 6878 ldr r0, [r7, #4]
8004796: f000 f888 bl 80048aa <HAL_FDCAN_TimestampWraparoundCallback>
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
}
/* Timeout Occurred interrupt management ************************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED) != 0U)
800479a: 687b ldr r3, [r7, #4]
800479c: 681b ldr r3, [r3, #0]
800479e: 6d1b ldr r3, [r3, #80] ; 0x50
80047a0: f403 4300 and.w r3, r3, #32768 ; 0x8000
80047a4: 2b00 cmp r3, #0
80047a6: d00e beq.n 80047c6 <HAL_FDCAN_IRQHandler+0x1fa>
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMEOUT_OCCURRED) != 0U)
80047a8: 687b ldr r3, [r7, #4]
80047aa: 681b ldr r3, [r3, #0]
80047ac: 6d5b ldr r3, [r3, #84] ; 0x54
80047ae: f403 4300 and.w r3, r3, #32768 ; 0x8000
80047b2: 2b00 cmp r3, #0
80047b4: d007 beq.n 80047c6 <HAL_FDCAN_IRQHandler+0x1fa>
{
/* Clear the Timeout Occurred flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
80047b6: 687b ldr r3, [r7, #4]
80047b8: 681b ldr r3, [r3, #0]
80047ba: f44f 4200 mov.w r2, #32768 ; 0x8000
80047be: 651a str r2, [r3, #80] ; 0x50
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->TimeoutOccurredCallback(hfdcan);
#else
/* Timeout Occurred Callback */
HAL_FDCAN_TimeoutOccurredCallback(hfdcan);
80047c0: 6878 ldr r0, [r7, #4]
80047c2: f000 f87c bl 80048be <HAL_FDCAN_TimeoutOccurredCallback>
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
}
/* Message RAM access failure interrupt management **************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE) != 0U)
80047c6: 687b ldr r3, [r7, #4]
80047c8: 681b ldr r3, [r3, #0]
80047ca: 6d1b ldr r3, [r3, #80] ; 0x50
80047cc: f403 4380 and.w r3, r3, #16384 ; 0x4000
80047d0: 2b00 cmp r3, #0
80047d2: d011 beq.n 80047f8 <HAL_FDCAN_IRQHandler+0x22c>
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RAM_ACCESS_FAILURE) != 0U)
80047d4: 687b ldr r3, [r7, #4]
80047d6: 681b ldr r3, [r3, #0]
80047d8: 6d5b ldr r3, [r3, #84] ; 0x54
80047da: f403 4380 and.w r3, r3, #16384 ; 0x4000
80047de: 2b00 cmp r3, #0
80047e0: d00a beq.n 80047f8 <HAL_FDCAN_IRQHandler+0x22c>
{
/* Clear the Message RAM access failure flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
80047e2: 687b ldr r3, [r7, #4]
80047e4: 681b ldr r3, [r3, #0]
80047e6: f44f 4280 mov.w r2, #16384 ; 0x4000
80047ea: 651a str r2, [r3, #80] ; 0x50
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS;
80047ec: 687b ldr r3, [r7, #4]
80047ee: 6e1b ldr r3, [r3, #96] ; 0x60
80047f0: f043 0280 orr.w r2, r3, #128 ; 0x80
80047f4: 687b ldr r3, [r7, #4]
80047f6: 661a str r2, [r3, #96] ; 0x60
}
}
/* Error Status interrupts management ***************************************/
if (ErrorStatusITs != 0U)
80047f8: 697b ldr r3, [r7, #20]
80047fa: 2b00 cmp r3, #0
80047fc: d007 beq.n 800480e <HAL_FDCAN_IRQHandler+0x242>
{
/* Clear the Error flags */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs);
80047fe: 687b ldr r3, [r7, #4]
8004800: 681b ldr r3, [r3, #0]
8004802: 697a ldr r2, [r7, #20]
8004804: 651a str r2, [r3, #80] ; 0x50
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs);
#else
/* Error Status Callback */
HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs);
8004806: 6979 ldr r1, [r7, #20]
8004808: 6878 ldr r0, [r7, #4]
800480a: f000 f876 bl 80048fa <HAL_FDCAN_ErrorStatusCallback>
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
/* Error interrupts management **********************************************/
if (Errors != 0U)
800480e: 69bb ldr r3, [r7, #24]
8004810: 2b00 cmp r3, #0
8004812: d009 beq.n 8004828 <HAL_FDCAN_IRQHandler+0x25c>
{
/* Clear the Error flags */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors);
8004814: 687b ldr r3, [r7, #4]
8004816: 681b ldr r3, [r3, #0]
8004818: 69ba ldr r2, [r7, #24]
800481a: 651a str r2, [r3, #80] ; 0x50
/* Update error code */
hfdcan->ErrorCode |= Errors;
800481c: 687b ldr r3, [r7, #4]
800481e: 6e1a ldr r2, [r3, #96] ; 0x60
8004820: 69bb ldr r3, [r7, #24]
8004822: 431a orrs r2, r3
8004824: 687b ldr r3, [r7, #4]
8004826: 661a str r2, [r3, #96] ; 0x60
}
if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE)
8004828: 687b ldr r3, [r7, #4]
800482a: 6e1b ldr r3, [r3, #96] ; 0x60
800482c: 2b00 cmp r3, #0
800482e: d002 beq.n 8004836 <HAL_FDCAN_IRQHandler+0x26a>
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->ErrorCallback(hfdcan);
#else
/* Error Callback */
HAL_FDCAN_ErrorCallback(hfdcan);
8004830: 6878 ldr r0, [r7, #4]
8004832: f000 f858 bl 80048e6 <HAL_FDCAN_ErrorCallback>
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
}
8004836: bf00 nop
8004838: 3728 adds r7, #40 ; 0x28
800483a: 46bd mov sp, r7
800483c: bd80 pop {r7, pc}
0800483e <HAL_FDCAN_TxEventFifoCallback>:
* @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signalled.
* This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts.
* @retval None
*/
__weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
{
800483e: b480 push {r7}
8004840: b083 sub sp, #12
8004842: af00 add r7, sp, #0
8004844: 6078 str r0, [r7, #4]
8004846: 6039 str r1, [r7, #0]
UNUSED(TxEventFifoITs);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
*/
}
8004848: bf00 nop
800484a: 370c adds r7, #12
800484c: 46bd mov sp, r7
800484e: f85d 7b04 ldr.w r7, [sp], #4
8004852: 4770 bx lr
08004854 <HAL_FDCAN_RxFifo1Callback>:
* @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signalled.
* This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts.
* @retval None
*/
__weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
{
8004854: b480 push {r7}
8004856: b083 sub sp, #12
8004858: af00 add r7, sp, #0
800485a: 6078 str r0, [r7, #4]
800485c: 6039 str r1, [r7, #0]
UNUSED(RxFifo1ITs);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
*/
}
800485e: bf00 nop
8004860: 370c adds r7, #12
8004862: 46bd mov sp, r7
8004864: f85d 7b04 ldr.w r7, [sp], #4
8004868: 4770 bx lr
0800486a <HAL_FDCAN_TxFifoEmptyCallback>:
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval None
*/
__weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
{
800486a: b480 push {r7}
800486c: b083 sub sp, #12
800486e: af00 add r7, sp, #0
8004870: 6078 str r0, [r7, #4]
UNUSED(hfdcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
*/
}
8004872: bf00 nop
8004874: 370c adds r7, #12
8004876: 46bd mov sp, r7
8004878: f85d 7b04 ldr.w r7, [sp], #4
800487c: 4770 bx lr
0800487e <HAL_FDCAN_TxBufferCompleteCallback>:
* @param BufferIndexes Indexes of the transmitted buffers.
* This parameter can be any combination of @arg FDCAN_Tx_location.
* @retval None
*/
__weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
{
800487e: b480 push {r7}
8004880: b083 sub sp, #12
8004882: af00 add r7, sp, #0
8004884: 6078 str r0, [r7, #4]
8004886: 6039 str r1, [r7, #0]
UNUSED(BufferIndexes);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
*/
}
8004888: bf00 nop
800488a: 370c adds r7, #12
800488c: 46bd mov sp, r7
800488e: f85d 7b04 ldr.w r7, [sp], #4
8004892: 4770 bx lr
08004894 <HAL_FDCAN_TxBufferAbortCallback>:
* @param BufferIndexes Indexes of the aborted buffers.
* This parameter can be any combination of @arg FDCAN_Tx_location.
* @retval None
*/
__weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
{
8004894: b480 push {r7}
8004896: b083 sub sp, #12
8004898: af00 add r7, sp, #0
800489a: 6078 str r0, [r7, #4]
800489c: 6039 str r1, [r7, #0]
UNUSED(BufferIndexes);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
*/
}
800489e: bf00 nop
80048a0: 370c adds r7, #12
80048a2: 46bd mov sp, r7
80048a4: f85d 7b04 ldr.w r7, [sp], #4
80048a8: 4770 bx lr
080048aa <HAL_FDCAN_TimestampWraparoundCallback>:
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval None
*/
__weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan)
{
80048aa: b480 push {r7}
80048ac: b083 sub sp, #12
80048ae: af00 add r7, sp, #0
80048b0: 6078 str r0, [r7, #4]
UNUSED(hfdcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
*/
}
80048b2: bf00 nop
80048b4: 370c adds r7, #12
80048b6: 46bd mov sp, r7
80048b8: f85d 7b04 ldr.w r7, [sp], #4
80048bc: 4770 bx lr
080048be <HAL_FDCAN_TimeoutOccurredCallback>:
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval None
*/
__weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan)
{
80048be: b480 push {r7}
80048c0: b083 sub sp, #12
80048c2: af00 add r7, sp, #0
80048c4: 6078 str r0, [r7, #4]
UNUSED(hfdcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
*/
}
80048c6: bf00 nop
80048c8: 370c adds r7, #12
80048ca: 46bd mov sp, r7
80048cc: f85d 7b04 ldr.w r7, [sp], #4
80048d0: 4770 bx lr
080048d2 <HAL_FDCAN_HighPriorityMessageCallback>:
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval None
*/
__weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan)
{
80048d2: b480 push {r7}
80048d4: b083 sub sp, #12
80048d6: af00 add r7, sp, #0
80048d8: 6078 str r0, [r7, #4]
UNUSED(hfdcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
*/
}
80048da: bf00 nop
80048dc: 370c adds r7, #12
80048de: 46bd mov sp, r7
80048e0: f85d 7b04 ldr.w r7, [sp], #4
80048e4: 4770 bx lr
080048e6 <HAL_FDCAN_ErrorCallback>:
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval None
*/
__weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
{
80048e6: b480 push {r7}
80048e8: b083 sub sp, #12
80048ea: af00 add r7, sp, #0
80048ec: 6078 str r0, [r7, #4]
UNUSED(hfdcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_ErrorCallback could be implemented in the user file
*/
}
80048ee: bf00 nop
80048f0: 370c adds r7, #12
80048f2: 46bd mov sp, r7
80048f4: f85d 7b04 ldr.w r7, [sp], #4
80048f8: 4770 bx lr
080048fa <HAL_FDCAN_ErrorStatusCallback>:
* @param ErrorStatusITs indicates which Error Status interrupts are signaled.
* This parameter can be any combination of @arg FDCAN_Error_Status_Interrupts.
* @retval None
*/
__weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
{
80048fa: b480 push {r7}
80048fc: b083 sub sp, #12
80048fe: af00 add r7, sp, #0
8004900: 6078 str r0, [r7, #4]
8004902: 6039 str r1, [r7, #0]
UNUSED(ErrorStatusITs);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file
*/
}
8004904: bf00 nop
8004906: 370c adds r7, #12
8004908: 46bd mov sp, r7
800490a: f85d 7b04 ldr.w r7, [sp], #4
800490e: 4770 bx lr
08004910 <FDCAN_CalcultateRamBlockAddresses>:
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval none
*/
static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
{
8004910: b480 push {r7}
8004912: b085 sub sp, #20
8004914: af00 add r7, sp, #0
8004916: 6078 str r0, [r7, #4]
uint32_t RAMcounter;
uint32_t SramCanInstanceBase = SRAMCAN_BASE;
8004918: 4b27 ldr r3, [pc, #156] ; (80049b8 <FDCAN_CalcultateRamBlockAddresses+0xa8>)
800491a: 60bb str r3, [r7, #8]
SramCanInstanceBase += SRAMCAN_SIZE * 2U;
}
#endif /* FDCAN3 */
/* Standard filter list start address */
hfdcan->msgRam.StandardFilterSA = SramCanInstanceBase + SRAMCAN_FLSSA;
800491c: 687b ldr r3, [r7, #4]
800491e: 68ba ldr r2, [r7, #8]
8004920: 641a str r2, [r3, #64] ; 0x40
/* Standard filter elements number */
MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_RXGFC_LSS_Pos));
8004922: 687b ldr r3, [r7, #4]
8004924: 681b ldr r3, [r3, #0]
8004926: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
800492a: f423 11f8 bic.w r1, r3, #2031616 ; 0x1f0000
800492e: 687b ldr r3, [r7, #4]
8004930: 6b5b ldr r3, [r3, #52] ; 0x34
8004932: 041a lsls r2, r3, #16
8004934: 687b ldr r3, [r7, #4]
8004936: 681b ldr r3, [r3, #0]
8004938: 430a orrs r2, r1
800493a: f8c3 2080 str.w r2, [r3, #128] ; 0x80
/* Extended filter list start address */
hfdcan->msgRam.ExtendedFilterSA = SramCanInstanceBase + SRAMCAN_FLESA;
800493e: 68bb ldr r3, [r7, #8]
8004940: f103 0270 add.w r2, r3, #112 ; 0x70
8004944: 687b ldr r3, [r7, #4]
8004946: 645a str r2, [r3, #68] ; 0x44
/* Extended filter elements number */
MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_RXGFC_LSE_Pos));
8004948: 687b ldr r3, [r7, #4]
800494a: 681b ldr r3, [r3, #0]
800494c: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
8004950: f023 6170 bic.w r1, r3, #251658240 ; 0xf000000
8004954: 687b ldr r3, [r7, #4]
8004956: 6b9b ldr r3, [r3, #56] ; 0x38
8004958: 061a lsls r2, r3, #24
800495a: 687b ldr r3, [r7, #4]
800495c: 681b ldr r3, [r3, #0]
800495e: 430a orrs r2, r1
8004960: f8c3 2080 str.w r2, [r3, #128] ; 0x80
/* Rx FIFO 0 start address */
hfdcan->msgRam.RxFIFO0SA = SramCanInstanceBase + SRAMCAN_RF0SA;
8004964: 68bb ldr r3, [r7, #8]
8004966: f103 02b0 add.w r2, r3, #176 ; 0xb0
800496a: 687b ldr r3, [r7, #4]
800496c: 649a str r2, [r3, #72] ; 0x48
/* Rx FIFO 1 start address */
hfdcan->msgRam.RxFIFO1SA = SramCanInstanceBase + SRAMCAN_RF1SA;
800496e: 68bb ldr r3, [r7, #8]
8004970: f503 72c4 add.w r2, r3, #392 ; 0x188
8004974: 687b ldr r3, [r7, #4]
8004976: 64da str r2, [r3, #76] ; 0x4c
/* Tx event FIFO start address */
hfdcan->msgRam.TxEventFIFOSA = SramCanInstanceBase + SRAMCAN_TEFSA;
8004978: 68bb ldr r3, [r7, #8]
800497a: f503 7218 add.w r2, r3, #608 ; 0x260
800497e: 687b ldr r3, [r7, #4]
8004980: 651a str r2, [r3, #80] ; 0x50
/* Tx FIFO/queue start address */
hfdcan->msgRam.TxFIFOQSA = SramCanInstanceBase + SRAMCAN_TFQSA;
8004982: 68bb ldr r3, [r7, #8]
8004984: f503 721e add.w r2, r3, #632 ; 0x278
8004988: 687b ldr r3, [r7, #4]
800498a: 655a str r2, [r3, #84] ; 0x54
/* Flush the allocated Message RAM area */
for (RAMcounter = SramCanInstanceBase; RAMcounter < (SramCanInstanceBase + SRAMCAN_SIZE); RAMcounter += 4U)
800498c: 68bb ldr r3, [r7, #8]
800498e: 60fb str r3, [r7, #12]
8004990: e005 b.n 800499e <FDCAN_CalcultateRamBlockAddresses+0x8e>
{
*(uint32_t *)(RAMcounter) = 0x00000000U;
8004992: 68fb ldr r3, [r7, #12]
8004994: 2200 movs r2, #0
8004996: 601a str r2, [r3, #0]
for (RAMcounter = SramCanInstanceBase; RAMcounter < (SramCanInstanceBase + SRAMCAN_SIZE); RAMcounter += 4U)
8004998: 68fb ldr r3, [r7, #12]
800499a: 3304 adds r3, #4
800499c: 60fb str r3, [r7, #12]
800499e: 68bb ldr r3, [r7, #8]
80049a0: f503 7354 add.w r3, r3, #848 ; 0x350
80049a4: 68fa ldr r2, [r7, #12]
80049a6: 429a cmp r2, r3
80049a8: d3f3 bcc.n 8004992 <FDCAN_CalcultateRamBlockAddresses+0x82>
}
}
80049aa: bf00 nop
80049ac: bf00 nop
80049ae: 3714 adds r7, #20
80049b0: 46bd mov sp, r7
80049b2: f85d 7b04 ldr.w r7, [sp], #4
80049b6: 4770 bx lr
80049b8: 4000a400 .word 0x4000a400
080049bc <FDCAN_CopyMessageToRAM>:
* @param BufferIndex index of the buffer to be configured.
* @retval none
*/
static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData,
uint32_t BufferIndex)
{
80049bc: b480 push {r7}
80049be: b089 sub sp, #36 ; 0x24
80049c0: af00 add r7, sp, #0
80049c2: 60f8 str r0, [r7, #12]
80049c4: 60b9 str r1, [r7, #8]
80049c6: 607a str r2, [r7, #4]
80049c8: 603b str r3, [r7, #0]
uint32_t TxElementW2;
uint32_t *TxAddress;
uint32_t ByteCounter;
/* Build first word of Tx header element */
if (pTxHeader->IdType == FDCAN_STANDARD_ID)
80049ca: 68bb ldr r3, [r7, #8]
80049cc: 685b ldr r3, [r3, #4]
80049ce: 2b00 cmp r3, #0
80049d0: d10a bne.n 80049e8 <FDCAN_CopyMessageToRAM+0x2c>
{
TxElementW1 = (pTxHeader->ErrorStateIndicator |
80049d2: 68bb ldr r3, [r7, #8]
80049d4: 691a ldr r2, [r3, #16]
FDCAN_STANDARD_ID |
pTxHeader->TxFrameType |
80049d6: 68bb ldr r3, [r7, #8]
80049d8: 689b ldr r3, [r3, #8]
FDCAN_STANDARD_ID |
80049da: 431a orrs r2, r3
(pTxHeader->Identifier << 18U));
80049dc: 68bb ldr r3, [r7, #8]
80049de: 681b ldr r3, [r3, #0]
80049e0: 049b lsls r3, r3, #18
TxElementW1 = (pTxHeader->ErrorStateIndicator |
80049e2: 4313 orrs r3, r2
80049e4: 61fb str r3, [r7, #28]
80049e6: e00a b.n 80049fe <FDCAN_CopyMessageToRAM+0x42>
}
else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
{
TxElementW1 = (pTxHeader->ErrorStateIndicator |
80049e8: 68bb ldr r3, [r7, #8]
80049ea: 691a ldr r2, [r3, #16]
FDCAN_EXTENDED_ID |
pTxHeader->TxFrameType |
80049ec: 68bb ldr r3, [r7, #8]
80049ee: 689b ldr r3, [r3, #8]
FDCAN_EXTENDED_ID |
80049f0: 431a orrs r2, r3
pTxHeader->Identifier);
80049f2: 68bb ldr r3, [r7, #8]
80049f4: 681b ldr r3, [r3, #0]
pTxHeader->TxFrameType |
80049f6: 4313 orrs r3, r2
TxElementW1 = (pTxHeader->ErrorStateIndicator |
80049f8: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000
80049fc: 61fb str r3, [r7, #28]
}
/* Build second word of Tx header element */
TxElementW2 = ((pTxHeader->MessageMarker << 24U) |
80049fe: 68bb ldr r3, [r7, #8]
8004a00: 6a1b ldr r3, [r3, #32]
8004a02: 061a lsls r2, r3, #24
pTxHeader->TxEventFifoControl |
8004a04: 68bb ldr r3, [r7, #8]
8004a06: 69db ldr r3, [r3, #28]
TxElementW2 = ((pTxHeader->MessageMarker << 24U) |
8004a08: 431a orrs r2, r3
pTxHeader->FDFormat |
8004a0a: 68bb ldr r3, [r7, #8]
8004a0c: 699b ldr r3, [r3, #24]
pTxHeader->TxEventFifoControl |
8004a0e: 431a orrs r2, r3
pTxHeader->BitRateSwitch |
8004a10: 68bb ldr r3, [r7, #8]
8004a12: 695b ldr r3, [r3, #20]
pTxHeader->FDFormat |
8004a14: 431a orrs r2, r3
pTxHeader->DataLength);
8004a16: 68bb ldr r3, [r7, #8]
8004a18: 68db ldr r3, [r3, #12]
TxElementW2 = ((pTxHeader->MessageMarker << 24U) |
8004a1a: 4313 orrs r3, r2
8004a1c: 613b str r3, [r7, #16]
/* Calculate Tx element address */
TxAddress = (uint32_t *)(hfdcan->msgRam.TxFIFOQSA + (BufferIndex * SRAMCAN_TFQ_SIZE));
8004a1e: 68fb ldr r3, [r7, #12]
8004a20: 6d59 ldr r1, [r3, #84] ; 0x54
8004a22: 683a ldr r2, [r7, #0]
8004a24: 4613 mov r3, r2
8004a26: 00db lsls r3, r3, #3
8004a28: 4413 add r3, r2
8004a2a: 00db lsls r3, r3, #3
8004a2c: 440b add r3, r1
8004a2e: 61bb str r3, [r7, #24]
/* Write Tx element header to the message RAM */
*TxAddress = TxElementW1;
8004a30: 69bb ldr r3, [r7, #24]
8004a32: 69fa ldr r2, [r7, #28]
8004a34: 601a str r2, [r3, #0]
TxAddress++;
8004a36: 69bb ldr r3, [r7, #24]
8004a38: 3304 adds r3, #4
8004a3a: 61bb str r3, [r7, #24]
*TxAddress = TxElementW2;
8004a3c: 69bb ldr r3, [r7, #24]
8004a3e: 693a ldr r2, [r7, #16]
8004a40: 601a str r2, [r3, #0]
TxAddress++;
8004a42: 69bb ldr r3, [r7, #24]
8004a44: 3304 adds r3, #4
8004a46: 61bb str r3, [r7, #24]
/* Write Tx payload to the message RAM */
for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16U]; ByteCounter += 4U)
8004a48: 2300 movs r3, #0
8004a4a: 617b str r3, [r7, #20]
8004a4c: e020 b.n 8004a90 <FDCAN_CopyMessageToRAM+0xd4>
{
*TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) |
8004a4e: 697b ldr r3, [r7, #20]
8004a50: 3303 adds r3, #3
8004a52: 687a ldr r2, [r7, #4]
8004a54: 4413 add r3, r2
8004a56: 781b ldrb r3, [r3, #0]
8004a58: 061a lsls r2, r3, #24
((uint32_t)pTxData[ByteCounter + 2U] << 16U) |
8004a5a: 697b ldr r3, [r7, #20]
8004a5c: 3302 adds r3, #2
8004a5e: 6879 ldr r1, [r7, #4]
8004a60: 440b add r3, r1
8004a62: 781b ldrb r3, [r3, #0]
8004a64: 041b lsls r3, r3, #16
*TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) |
8004a66: 431a orrs r2, r3
((uint32_t)pTxData[ByteCounter + 1U] << 8U) |
8004a68: 697b ldr r3, [r7, #20]
8004a6a: 3301 adds r3, #1
8004a6c: 6879 ldr r1, [r7, #4]
8004a6e: 440b add r3, r1
8004a70: 781b ldrb r3, [r3, #0]
8004a72: 021b lsls r3, r3, #8
((uint32_t)pTxData[ByteCounter + 2U] << 16U) |
8004a74: 4313 orrs r3, r2
(uint32_t)pTxData[ByteCounter]);
8004a76: 6879 ldr r1, [r7, #4]
8004a78: 697a ldr r2, [r7, #20]
8004a7a: 440a add r2, r1
8004a7c: 7812 ldrb r2, [r2, #0]
((uint32_t)pTxData[ByteCounter + 1U] << 8U) |
8004a7e: 431a orrs r2, r3
*TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) |
8004a80: 69bb ldr r3, [r7, #24]
8004a82: 601a str r2, [r3, #0]
TxAddress++;
8004a84: 69bb ldr r3, [r7, #24]
8004a86: 3304 adds r3, #4
8004a88: 61bb str r3, [r7, #24]
for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16U]; ByteCounter += 4U)
8004a8a: 697b ldr r3, [r7, #20]
8004a8c: 3304 adds r3, #4
8004a8e: 617b str r3, [r7, #20]
8004a90: 68bb ldr r3, [r7, #8]
8004a92: 68db ldr r3, [r3, #12]
8004a94: 0c1b lsrs r3, r3, #16
8004a96: 4a06 ldr r2, [pc, #24] ; (8004ab0 <FDCAN_CopyMessageToRAM+0xf4>)
8004a98: 5cd3 ldrb r3, [r2, r3]
8004a9a: 461a mov r2, r3
8004a9c: 697b ldr r3, [r7, #20]
8004a9e: 4293 cmp r3, r2
8004aa0: d3d5 bcc.n 8004a4e <FDCAN_CopyMessageToRAM+0x92>
}
}
8004aa2: bf00 nop
8004aa4: bf00 nop
8004aa6: 3724 adds r7, #36 ; 0x24
8004aa8: 46bd mov sp, r7
8004aaa: f85d 7b04 ldr.w r7, [sp], #4
8004aae: 4770 bx lr
8004ab0: 08007cc0 .word 0x08007cc0
08004ab4 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8004ab4: b480 push {r7}
8004ab6: b087 sub sp, #28
8004ab8: af00 add r7, sp, #0
8004aba: 6078 str r0, [r7, #4]
8004abc: 6039 str r1, [r7, #0]
uint32_t position = 0x00U;
8004abe: 2300 movs r3, #0
8004ac0: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0U)
8004ac2: e15a b.n 8004d7a <HAL_GPIO_Init+0x2c6>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1UL << position);
8004ac4: 683b ldr r3, [r7, #0]
8004ac6: 681a ldr r2, [r3, #0]
8004ac8: 2101 movs r1, #1
8004aca: 697b ldr r3, [r7, #20]
8004acc: fa01 f303 lsl.w r3, r1, r3
8004ad0: 4013 ands r3, r2
8004ad2: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8004ad4: 68fb ldr r3, [r7, #12]
8004ad6: 2b00 cmp r3, #0
8004ad8: f000 814c beq.w 8004d74 <HAL_GPIO_Init+0x2c0>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8004adc: 683b ldr r3, [r7, #0]
8004ade: 685b ldr r3, [r3, #4]
8004ae0: f003 0303 and.w r3, r3, #3
8004ae4: 2b01 cmp r3, #1
8004ae6: d005 beq.n 8004af4 <HAL_GPIO_Init+0x40>
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8004ae8: 683b ldr r3, [r7, #0]
8004aea: 685b ldr r3, [r3, #4]
8004aec: f003 0303 and.w r3, r3, #3
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8004af0: 2b02 cmp r3, #2
8004af2: d130 bne.n 8004b56 <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8004af4: 687b ldr r3, [r7, #4]
8004af6: 689b ldr r3, [r3, #8]
8004af8: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
8004afa: 697b ldr r3, [r7, #20]
8004afc: 005b lsls r3, r3, #1
8004afe: 2203 movs r2, #3
8004b00: fa02 f303 lsl.w r3, r2, r3
8004b04: 43db mvns r3, r3
8004b06: 693a ldr r2, [r7, #16]
8004b08: 4013 ands r3, r2
8004b0a: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2U));
8004b0c: 683b ldr r3, [r7, #0]
8004b0e: 68da ldr r2, [r3, #12]
8004b10: 697b ldr r3, [r7, #20]
8004b12: 005b lsls r3, r3, #1
8004b14: fa02 f303 lsl.w r3, r2, r3
8004b18: 693a ldr r2, [r7, #16]
8004b1a: 4313 orrs r3, r2
8004b1c: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8004b1e: 687b ldr r3, [r7, #4]
8004b20: 693a ldr r2, [r7, #16]
8004b22: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8004b24: 687b ldr r3, [r7, #4]
8004b26: 685b ldr r3, [r3, #4]
8004b28: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT0 << position) ;
8004b2a: 2201 movs r2, #1
8004b2c: 697b ldr r3, [r7, #20]
8004b2e: fa02 f303 lsl.w r3, r2, r3
8004b32: 43db mvns r3, r3
8004b34: 693a ldr r2, [r7, #16]
8004b36: 4013 ands r3, r2
8004b38: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8004b3a: 683b ldr r3, [r7, #0]
8004b3c: 685b ldr r3, [r3, #4]
8004b3e: 091b lsrs r3, r3, #4
8004b40: f003 0201 and.w r2, r3, #1
8004b44: 697b ldr r3, [r7, #20]
8004b46: fa02 f303 lsl.w r3, r2, r3
8004b4a: 693a ldr r2, [r7, #16]
8004b4c: 4313 orrs r3, r2
8004b4e: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8004b50: 687b ldr r3, [r7, #4]
8004b52: 693a ldr r2, [r7, #16]
8004b54: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8004b56: 683b ldr r3, [r7, #0]
8004b58: 685b ldr r3, [r3, #4]
8004b5a: f003 0303 and.w r3, r3, #3
8004b5e: 2b03 cmp r3, #3
8004b60: d017 beq.n 8004b92 <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8004b62: 687b ldr r3, [r7, #4]
8004b64: 68db ldr r3, [r3, #12]
8004b66: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
8004b68: 697b ldr r3, [r7, #20]
8004b6a: 005b lsls r3, r3, #1
8004b6c: 2203 movs r2, #3
8004b6e: fa02 f303 lsl.w r3, r2, r3
8004b72: 43db mvns r3, r3
8004b74: 693a ldr r2, [r7, #16]
8004b76: 4013 ands r3, r2
8004b78: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2U));
8004b7a: 683b ldr r3, [r7, #0]
8004b7c: 689a ldr r2, [r3, #8]
8004b7e: 697b ldr r3, [r7, #20]
8004b80: 005b lsls r3, r3, #1
8004b82: fa02 f303 lsl.w r3, r2, r3
8004b86: 693a ldr r2, [r7, #16]
8004b88: 4313 orrs r3, r2
8004b8a: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
8004b8c: 687b ldr r3, [r7, #4]
8004b8e: 693a ldr r2, [r7, #16]
8004b90: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8004b92: 683b ldr r3, [r7, #0]
8004b94: 685b ldr r3, [r3, #4]
8004b96: f003 0303 and.w r3, r3, #3
8004b9a: 2b02 cmp r3, #2
8004b9c: d123 bne.n 8004be6 <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
8004b9e: 697b ldr r3, [r7, #20]
8004ba0: 08da lsrs r2, r3, #3
8004ba2: 687b ldr r3, [r7, #4]
8004ba4: 3208 adds r2, #8
8004ba6: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8004baa: 613b str r3, [r7, #16]
temp &= ~(0xFU << ((position & 0x07U) * 4U));
8004bac: 697b ldr r3, [r7, #20]
8004bae: f003 0307 and.w r3, r3, #7
8004bb2: 009b lsls r3, r3, #2
8004bb4: 220f movs r2, #15
8004bb6: fa02 f303 lsl.w r3, r2, r3
8004bba: 43db mvns r3, r3
8004bbc: 693a ldr r2, [r7, #16]
8004bbe: 4013 ands r3, r2
8004bc0: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
8004bc2: 683b ldr r3, [r7, #0]
8004bc4: 691a ldr r2, [r3, #16]
8004bc6: 697b ldr r3, [r7, #20]
8004bc8: f003 0307 and.w r3, r3, #7
8004bcc: 009b lsls r3, r3, #2
8004bce: fa02 f303 lsl.w r3, r2, r3
8004bd2: 693a ldr r2, [r7, #16]
8004bd4: 4313 orrs r3, r2
8004bd6: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3U] = temp;
8004bd8: 697b ldr r3, [r7, #20]
8004bda: 08da lsrs r2, r3, #3
8004bdc: 687b ldr r3, [r7, #4]
8004bde: 3208 adds r2, #8
8004be0: 6939 ldr r1, [r7, #16]
8004be2: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8004be6: 687b ldr r3, [r7, #4]
8004be8: 681b ldr r3, [r3, #0]
8004bea: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
8004bec: 697b ldr r3, [r7, #20]
8004bee: 005b lsls r3, r3, #1
8004bf0: 2203 movs r2, #3
8004bf2: fa02 f303 lsl.w r3, r2, r3
8004bf6: 43db mvns r3, r3
8004bf8: 693a ldr r2, [r7, #16]
8004bfa: 4013 ands r3, r2
8004bfc: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
8004bfe: 683b ldr r3, [r7, #0]
8004c00: 685b ldr r3, [r3, #4]
8004c02: f003 0203 and.w r2, r3, #3
8004c06: 697b ldr r3, [r7, #20]
8004c08: 005b lsls r3, r3, #1
8004c0a: fa02 f303 lsl.w r3, r2, r3
8004c0e: 693a ldr r2, [r7, #16]
8004c10: 4313 orrs r3, r2
8004c12: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8004c14: 687b ldr r3, [r7, #4]
8004c16: 693a ldr r2, [r7, #16]
8004c18: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8004c1a: 683b ldr r3, [r7, #0]
8004c1c: 685b ldr r3, [r3, #4]
8004c1e: f403 3340 and.w r3, r3, #196608 ; 0x30000
8004c22: 2b00 cmp r3, #0
8004c24: f000 80a6 beq.w 8004d74 <HAL_GPIO_Init+0x2c0>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8004c28: 4b5b ldr r3, [pc, #364] ; (8004d98 <HAL_GPIO_Init+0x2e4>)
8004c2a: 6e1b ldr r3, [r3, #96] ; 0x60
8004c2c: 4a5a ldr r2, [pc, #360] ; (8004d98 <HAL_GPIO_Init+0x2e4>)
8004c2e: f043 0301 orr.w r3, r3, #1
8004c32: 6613 str r3, [r2, #96] ; 0x60
8004c34: 4b58 ldr r3, [pc, #352] ; (8004d98 <HAL_GPIO_Init+0x2e4>)
8004c36: 6e1b ldr r3, [r3, #96] ; 0x60
8004c38: f003 0301 and.w r3, r3, #1
8004c3c: 60bb str r3, [r7, #8]
8004c3e: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2U];
8004c40: 4a56 ldr r2, [pc, #344] ; (8004d9c <HAL_GPIO_Init+0x2e8>)
8004c42: 697b ldr r3, [r7, #20]
8004c44: 089b lsrs r3, r3, #2
8004c46: 3302 adds r3, #2
8004c48: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8004c4c: 613b str r3, [r7, #16]
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
8004c4e: 697b ldr r3, [r7, #20]
8004c50: f003 0303 and.w r3, r3, #3
8004c54: 009b lsls r3, r3, #2
8004c56: 220f movs r2, #15
8004c58: fa02 f303 lsl.w r3, r2, r3
8004c5c: 43db mvns r3, r3
8004c5e: 693a ldr r2, [r7, #16]
8004c60: 4013 ands r3, r2
8004c62: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
8004c64: 687b ldr r3, [r7, #4]
8004c66: f1b3 4f90 cmp.w r3, #1207959552 ; 0x48000000
8004c6a: d01f beq.n 8004cac <HAL_GPIO_Init+0x1f8>
8004c6c: 687b ldr r3, [r7, #4]
8004c6e: 4a4c ldr r2, [pc, #304] ; (8004da0 <HAL_GPIO_Init+0x2ec>)
8004c70: 4293 cmp r3, r2
8004c72: d019 beq.n 8004ca8 <HAL_GPIO_Init+0x1f4>
8004c74: 687b ldr r3, [r7, #4]
8004c76: 4a4b ldr r2, [pc, #300] ; (8004da4 <HAL_GPIO_Init+0x2f0>)
8004c78: 4293 cmp r3, r2
8004c7a: d013 beq.n 8004ca4 <HAL_GPIO_Init+0x1f0>
8004c7c: 687b ldr r3, [r7, #4]
8004c7e: 4a4a ldr r2, [pc, #296] ; (8004da8 <HAL_GPIO_Init+0x2f4>)
8004c80: 4293 cmp r3, r2
8004c82: d00d beq.n 8004ca0 <HAL_GPIO_Init+0x1ec>
8004c84: 687b ldr r3, [r7, #4]
8004c86: 4a49 ldr r2, [pc, #292] ; (8004dac <HAL_GPIO_Init+0x2f8>)
8004c88: 4293 cmp r3, r2
8004c8a: d007 beq.n 8004c9c <HAL_GPIO_Init+0x1e8>
8004c8c: 687b ldr r3, [r7, #4]
8004c8e: 4a48 ldr r2, [pc, #288] ; (8004db0 <HAL_GPIO_Init+0x2fc>)
8004c90: 4293 cmp r3, r2
8004c92: d101 bne.n 8004c98 <HAL_GPIO_Init+0x1e4>
8004c94: 2305 movs r3, #5
8004c96: e00a b.n 8004cae <HAL_GPIO_Init+0x1fa>
8004c98: 2306 movs r3, #6
8004c9a: e008 b.n 8004cae <HAL_GPIO_Init+0x1fa>
8004c9c: 2304 movs r3, #4
8004c9e: e006 b.n 8004cae <HAL_GPIO_Init+0x1fa>
8004ca0: 2303 movs r3, #3
8004ca2: e004 b.n 8004cae <HAL_GPIO_Init+0x1fa>
8004ca4: 2302 movs r3, #2
8004ca6: e002 b.n 8004cae <HAL_GPIO_Init+0x1fa>
8004ca8: 2301 movs r3, #1
8004caa: e000 b.n 8004cae <HAL_GPIO_Init+0x1fa>
8004cac: 2300 movs r3, #0
8004cae: 697a ldr r2, [r7, #20]
8004cb0: f002 0203 and.w r2, r2, #3
8004cb4: 0092 lsls r2, r2, #2
8004cb6: 4093 lsls r3, r2
8004cb8: 693a ldr r2, [r7, #16]
8004cba: 4313 orrs r3, r2
8004cbc: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2U] = temp;
8004cbe: 4937 ldr r1, [pc, #220] ; (8004d9c <HAL_GPIO_Init+0x2e8>)
8004cc0: 697b ldr r3, [r7, #20]
8004cc2: 089b lsrs r3, r3, #2
8004cc4: 3302 adds r3, #2
8004cc6: 693a ldr r2, [r7, #16]
8004cc8: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
8004ccc: 4b39 ldr r3, [pc, #228] ; (8004db4 <HAL_GPIO_Init+0x300>)
8004cce: 689b ldr r3, [r3, #8]
8004cd0: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8004cd2: 68fb ldr r3, [r7, #12]
8004cd4: 43db mvns r3, r3
8004cd6: 693a ldr r2, [r7, #16]
8004cd8: 4013 ands r3, r2
8004cda: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
8004cdc: 683b ldr r3, [r7, #0]
8004cde: 685b ldr r3, [r3, #4]
8004ce0: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8004ce4: 2b00 cmp r3, #0
8004ce6: d003 beq.n 8004cf0 <HAL_GPIO_Init+0x23c>
{
temp |= iocurrent;
8004ce8: 693a ldr r2, [r7, #16]
8004cea: 68fb ldr r3, [r7, #12]
8004cec: 4313 orrs r3, r2
8004cee: 613b str r3, [r7, #16]
}
EXTI->RTSR1 = temp;
8004cf0: 4a30 ldr r2, [pc, #192] ; (8004db4 <HAL_GPIO_Init+0x300>)
8004cf2: 693b ldr r3, [r7, #16]
8004cf4: 6093 str r3, [r2, #8]
temp = EXTI->FTSR1;
8004cf6: 4b2f ldr r3, [pc, #188] ; (8004db4 <HAL_GPIO_Init+0x300>)
8004cf8: 68db ldr r3, [r3, #12]
8004cfa: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8004cfc: 68fb ldr r3, [r7, #12]
8004cfe: 43db mvns r3, r3
8004d00: 693a ldr r2, [r7, #16]
8004d02: 4013 ands r3, r2
8004d04: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
8004d06: 683b ldr r3, [r7, #0]
8004d08: 685b ldr r3, [r3, #4]
8004d0a: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8004d0e: 2b00 cmp r3, #0
8004d10: d003 beq.n 8004d1a <HAL_GPIO_Init+0x266>
{
temp |= iocurrent;
8004d12: 693a ldr r2, [r7, #16]
8004d14: 68fb ldr r3, [r7, #12]
8004d16: 4313 orrs r3, r2
8004d18: 613b str r3, [r7, #16]
}
EXTI->FTSR1 = temp;
8004d1a: 4a26 ldr r2, [pc, #152] ; (8004db4 <HAL_GPIO_Init+0x300>)
8004d1c: 693b ldr r3, [r7, #16]
8004d1e: 60d3 str r3, [r2, #12]
temp = EXTI->EMR1;
8004d20: 4b24 ldr r3, [pc, #144] ; (8004db4 <HAL_GPIO_Init+0x300>)
8004d22: 685b ldr r3, [r3, #4]
8004d24: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8004d26: 68fb ldr r3, [r7, #12]
8004d28: 43db mvns r3, r3
8004d2a: 693a ldr r2, [r7, #16]
8004d2c: 4013 ands r3, r2
8004d2e: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
8004d30: 683b ldr r3, [r7, #0]
8004d32: 685b ldr r3, [r3, #4]
8004d34: f403 3300 and.w r3, r3, #131072 ; 0x20000
8004d38: 2b00 cmp r3, #0
8004d3a: d003 beq.n 8004d44 <HAL_GPIO_Init+0x290>
{
temp |= iocurrent;
8004d3c: 693a ldr r2, [r7, #16]
8004d3e: 68fb ldr r3, [r7, #12]
8004d40: 4313 orrs r3, r2
8004d42: 613b str r3, [r7, #16]
}
EXTI->EMR1 = temp;
8004d44: 4a1b ldr r2, [pc, #108] ; (8004db4 <HAL_GPIO_Init+0x300>)
8004d46: 693b ldr r3, [r7, #16]
8004d48: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR1;
8004d4a: 4b1a ldr r3, [pc, #104] ; (8004db4 <HAL_GPIO_Init+0x300>)
8004d4c: 681b ldr r3, [r3, #0]
8004d4e: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8004d50: 68fb ldr r3, [r7, #12]
8004d52: 43db mvns r3, r3
8004d54: 693a ldr r2, [r7, #16]
8004d56: 4013 ands r3, r2
8004d58: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
8004d5a: 683b ldr r3, [r7, #0]
8004d5c: 685b ldr r3, [r3, #4]
8004d5e: f403 3380 and.w r3, r3, #65536 ; 0x10000
8004d62: 2b00 cmp r3, #0
8004d64: d003 beq.n 8004d6e <HAL_GPIO_Init+0x2ba>
{
temp |= iocurrent;
8004d66: 693a ldr r2, [r7, #16]
8004d68: 68fb ldr r3, [r7, #12]
8004d6a: 4313 orrs r3, r2
8004d6c: 613b str r3, [r7, #16]
}
EXTI->IMR1 = temp;
8004d6e: 4a11 ldr r2, [pc, #68] ; (8004db4 <HAL_GPIO_Init+0x300>)
8004d70: 693b ldr r3, [r7, #16]
8004d72: 6013 str r3, [r2, #0]
}
}
position++;
8004d74: 697b ldr r3, [r7, #20]
8004d76: 3301 adds r3, #1
8004d78: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0U)
8004d7a: 683b ldr r3, [r7, #0]
8004d7c: 681a ldr r2, [r3, #0]
8004d7e: 697b ldr r3, [r7, #20]
8004d80: fa22 f303 lsr.w r3, r2, r3
8004d84: 2b00 cmp r3, #0
8004d86: f47f ae9d bne.w 8004ac4 <HAL_GPIO_Init+0x10>
}
}
8004d8a: bf00 nop
8004d8c: bf00 nop
8004d8e: 371c adds r7, #28
8004d90: 46bd mov sp, r7
8004d92: f85d 7b04 ldr.w r7, [sp], #4
8004d96: 4770 bx lr
8004d98: 40021000 .word 0x40021000
8004d9c: 40010000 .word 0x40010000
8004da0: 48000400 .word 0x48000400
8004da4: 48000800 .word 0x48000800
8004da8: 48000c00 .word 0x48000c00
8004dac: 48001000 .word 0x48001000
8004db0: 48001400 .word 0x48001400
8004db4: 40010400 .word 0x40010400
08004db8 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8004db8: b480 push {r7}
8004dba: b083 sub sp, #12
8004dbc: af00 add r7, sp, #0
8004dbe: 6078 str r0, [r7, #4]
8004dc0: 460b mov r3, r1
8004dc2: 807b strh r3, [r7, #2]
8004dc4: 4613 mov r3, r2
8004dc6: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8004dc8: 787b ldrb r3, [r7, #1]
8004dca: 2b00 cmp r3, #0
8004dcc: d003 beq.n 8004dd6 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8004dce: 887a ldrh r2, [r7, #2]
8004dd0: 687b ldr r3, [r7, #4]
8004dd2: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
8004dd4: e002 b.n 8004ddc <HAL_GPIO_WritePin+0x24>
GPIOx->BRR = (uint32_t)GPIO_Pin;
8004dd6: 887a ldrh r2, [r7, #2]
8004dd8: 687b ldr r3, [r7, #4]
8004dda: 629a str r2, [r3, #40] ; 0x28
}
8004ddc: bf00 nop
8004dde: 370c adds r7, #12
8004de0: 46bd mov sp, r7
8004de2: f85d 7b04 ldr.w r7, [sp], #4
8004de6: 4770 bx lr
08004de8 <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
8004de8: b580 push {r7, lr}
8004dea: b082 sub sp, #8
8004dec: af00 add r7, sp, #0
8004dee: 6078 str r0, [r7, #4]
/* Check the I2C handle allocation */
if (hi2c == NULL)
8004df0: 687b ldr r3, [r7, #4]
8004df2: 2b00 cmp r3, #0
8004df4: d101 bne.n 8004dfa <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
8004df6: 2301 movs r3, #1
8004df8: e081 b.n 8004efe <HAL_I2C_Init+0x116>
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
8004dfa: 687b ldr r3, [r7, #4]
8004dfc: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8004e00: b2db uxtb r3, r3
8004e02: 2b00 cmp r3, #0
8004e04: d106 bne.n 8004e14 <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
8004e06: 687b ldr r3, [r7, #4]
8004e08: 2200 movs r2, #0
8004e0a: f883 2040 strb.w r2, [r3, #64] ; 0x40
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
8004e0e: 6878 ldr r0, [r7, #4]
8004e10: f7fc fd7a bl 8001908 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
8004e14: 687b ldr r3, [r7, #4]
8004e16: 2224 movs r2, #36 ; 0x24
8004e18: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8004e1c: 687b ldr r3, [r7, #4]
8004e1e: 681b ldr r3, [r3, #0]
8004e20: 681a ldr r2, [r3, #0]
8004e22: 687b ldr r3, [r7, #4]
8004e24: 681b ldr r3, [r3, #0]
8004e26: f022 0201 bic.w r2, r2, #1
8004e2a: 601a str r2, [r3, #0]
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
/* Configure I2Cx: Frequency range */
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
8004e2c: 687b ldr r3, [r7, #4]
8004e2e: 685a ldr r2, [r3, #4]
8004e30: 687b ldr r3, [r7, #4]
8004e32: 681b ldr r3, [r3, #0]
8004e34: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
8004e38: 611a str r2, [r3, #16]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
8004e3a: 687b ldr r3, [r7, #4]
8004e3c: 681b ldr r3, [r3, #0]
8004e3e: 689a ldr r2, [r3, #8]
8004e40: 687b ldr r3, [r7, #4]
8004e42: 681b ldr r3, [r3, #0]
8004e44: f422 4200 bic.w r2, r2, #32768 ; 0x8000
8004e48: 609a str r2, [r3, #8]
/* Configure I2Cx: Own Address1 and ack own address1 mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
8004e4a: 687b ldr r3, [r7, #4]
8004e4c: 68db ldr r3, [r3, #12]
8004e4e: 2b01 cmp r3, #1
8004e50: d107 bne.n 8004e62 <HAL_I2C_Init+0x7a>
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
8004e52: 687b ldr r3, [r7, #4]
8004e54: 689a ldr r2, [r3, #8]
8004e56: 687b ldr r3, [r7, #4]
8004e58: 681b ldr r3, [r3, #0]
8004e5a: f442 4200 orr.w r2, r2, #32768 ; 0x8000
8004e5e: 609a str r2, [r3, #8]
8004e60: e006 b.n 8004e70 <HAL_I2C_Init+0x88>
}
else /* I2C_ADDRESSINGMODE_10BIT */
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
8004e62: 687b ldr r3, [r7, #4]
8004e64: 689a ldr r2, [r3, #8]
8004e66: 687b ldr r3, [r7, #4]
8004e68: 681b ldr r3, [r3, #0]
8004e6a: f442 4204 orr.w r2, r2, #33792 ; 0x8400
8004e6e: 609a str r2, [r3, #8]
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
8004e70: 687b ldr r3, [r7, #4]
8004e72: 68db ldr r3, [r3, #12]
8004e74: 2b02 cmp r3, #2
8004e76: d104 bne.n 8004e82 <HAL_I2C_Init+0x9a>
{
hi2c->Instance->CR2 = (I2C_CR2_ADD10);
8004e78: 687b ldr r3, [r7, #4]
8004e7a: 681b ldr r3, [r3, #0]
8004e7c: f44f 6200 mov.w r2, #2048 ; 0x800
8004e80: 605a str r2, [r3, #4]
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
8004e82: 687b ldr r3, [r7, #4]
8004e84: 681b ldr r3, [r3, #0]
8004e86: 685b ldr r3, [r3, #4]
8004e88: 687a ldr r2, [r7, #4]
8004e8a: 6812 ldr r2, [r2, #0]
8004e8c: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
8004e90: f443 4300 orr.w r3, r3, #32768 ; 0x8000
8004e94: 6053 str r3, [r2, #4]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Disable Own Address2 before set the Own Address2 configuration */
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
8004e96: 687b ldr r3, [r7, #4]
8004e98: 681b ldr r3, [r3, #0]
8004e9a: 68da ldr r2, [r3, #12]
8004e9c: 687b ldr r3, [r7, #4]
8004e9e: 681b ldr r3, [r3, #0]
8004ea0: f422 4200 bic.w r2, r2, #32768 ; 0x8000
8004ea4: 60da str r2, [r3, #12]
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
8004ea6: 687b ldr r3, [r7, #4]
8004ea8: 691a ldr r2, [r3, #16]
8004eaa: 687b ldr r3, [r7, #4]
8004eac: 695b ldr r3, [r3, #20]
8004eae: ea42 0103 orr.w r1, r2, r3
(hi2c->Init.OwnAddress2Masks << 8));
8004eb2: 687b ldr r3, [r7, #4]
8004eb4: 699b ldr r3, [r3, #24]
8004eb6: 021a lsls r2, r3, #8
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
8004eb8: 687b ldr r3, [r7, #4]
8004eba: 681b ldr r3, [r3, #0]
8004ebc: 430a orrs r2, r1
8004ebe: 60da str r2, [r3, #12]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
8004ec0: 687b ldr r3, [r7, #4]
8004ec2: 69d9 ldr r1, [r3, #28]
8004ec4: 687b ldr r3, [r7, #4]
8004ec6: 6a1a ldr r2, [r3, #32]
8004ec8: 687b ldr r3, [r7, #4]
8004eca: 681b ldr r3, [r3, #0]
8004ecc: 430a orrs r2, r1
8004ece: 601a str r2, [r3, #0]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
8004ed0: 687b ldr r3, [r7, #4]
8004ed2: 681b ldr r3, [r3, #0]
8004ed4: 681a ldr r2, [r3, #0]
8004ed6: 687b ldr r3, [r7, #4]
8004ed8: 681b ldr r3, [r3, #0]
8004eda: f042 0201 orr.w r2, r2, #1
8004ede: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8004ee0: 687b ldr r3, [r7, #4]
8004ee2: 2200 movs r2, #0
8004ee4: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8004ee6: 687b ldr r3, [r7, #4]
8004ee8: 2220 movs r2, #32
8004eea: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->PreviousState = I2C_STATE_NONE;
8004eee: 687b ldr r3, [r7, #4]
8004ef0: 2200 movs r2, #0
8004ef2: 631a str r2, [r3, #48] ; 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
8004ef4: 687b ldr r3, [r7, #4]
8004ef6: 2200 movs r2, #0
8004ef8: f883 2042 strb.w r2, [r3, #66] ; 0x42
return HAL_OK;
8004efc: 2300 movs r3, #0
}
8004efe: 4618 mov r0, r3
8004f00: 3708 adds r7, #8
8004f02: 46bd mov sp, r7
8004f04: bd80 pop {r7, pc}
...
08004f08 <HAL_I2C_Master_Transmit>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout)
{
8004f08: b580 push {r7, lr}
8004f0a: b088 sub sp, #32
8004f0c: af02 add r7, sp, #8
8004f0e: 60f8 str r0, [r7, #12]
8004f10: 607a str r2, [r7, #4]
8004f12: 461a mov r2, r3
8004f14: 460b mov r3, r1
8004f16: 817b strh r3, [r7, #10]
8004f18: 4613 mov r3, r2
8004f1a: 813b strh r3, [r7, #8]
uint32_t tickstart;
if (hi2c->State == HAL_I2C_STATE_READY)
8004f1c: 68fb ldr r3, [r7, #12]
8004f1e: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8004f22: b2db uxtb r3, r3
8004f24: 2b20 cmp r3, #32
8004f26: f040 80da bne.w 80050de <HAL_I2C_Master_Transmit+0x1d6>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8004f2a: 68fb ldr r3, [r7, #12]
8004f2c: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
8004f30: 2b01 cmp r3, #1
8004f32: d101 bne.n 8004f38 <HAL_I2C_Master_Transmit+0x30>
8004f34: 2302 movs r3, #2
8004f36: e0d3 b.n 80050e0 <HAL_I2C_Master_Transmit+0x1d8>
8004f38: 68fb ldr r3, [r7, #12]
8004f3a: 2201 movs r2, #1
8004f3c: f883 2040 strb.w r2, [r3, #64] ; 0x40
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
8004f40: f7fc ff08 bl 8001d54 <HAL_GetTick>
8004f44: 6178 str r0, [r7, #20]
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
8004f46: 697b ldr r3, [r7, #20]
8004f48: 9300 str r3, [sp, #0]
8004f4a: 2319 movs r3, #25
8004f4c: 2201 movs r2, #1
8004f4e: f44f 4100 mov.w r1, #32768 ; 0x8000
8004f52: 68f8 ldr r0, [r7, #12]
8004f54: f000 f8f0 bl 8005138 <I2C_WaitOnFlagUntilTimeout>
8004f58: 4603 mov r3, r0
8004f5a: 2b00 cmp r3, #0
8004f5c: d001 beq.n 8004f62 <HAL_I2C_Master_Transmit+0x5a>
{
return HAL_ERROR;
8004f5e: 2301 movs r3, #1
8004f60: e0be b.n 80050e0 <HAL_I2C_Master_Transmit+0x1d8>
}
hi2c->State = HAL_I2C_STATE_BUSY_TX;
8004f62: 68fb ldr r3, [r7, #12]
8004f64: 2221 movs r2, #33 ; 0x21
8004f66: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_MASTER;
8004f6a: 68fb ldr r3, [r7, #12]
8004f6c: 2210 movs r2, #16
8004f6e: f883 2042 strb.w r2, [r3, #66] ; 0x42
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8004f72: 68fb ldr r3, [r7, #12]
8004f74: 2200 movs r2, #0
8004f76: 645a str r2, [r3, #68] ; 0x44
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
8004f78: 68fb ldr r3, [r7, #12]
8004f7a: 687a ldr r2, [r7, #4]
8004f7c: 625a str r2, [r3, #36] ; 0x24
hi2c->XferCount = Size;
8004f7e: 68fb ldr r3, [r7, #12]
8004f80: 893a ldrh r2, [r7, #8]
8004f82: 855a strh r2, [r3, #42] ; 0x2a
hi2c->XferISR = NULL;
8004f84: 68fb ldr r3, [r7, #12]
8004f86: 2200 movs r2, #0
8004f88: 635a str r2, [r3, #52] ; 0x34
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
8004f8a: 68fb ldr r3, [r7, #12]
8004f8c: 8d5b ldrh r3, [r3, #42] ; 0x2a
8004f8e: b29b uxth r3, r3
8004f90: 2bff cmp r3, #255 ; 0xff
8004f92: d90e bls.n 8004fb2 <HAL_I2C_Master_Transmit+0xaa>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
8004f94: 68fb ldr r3, [r7, #12]
8004f96: 22ff movs r2, #255 ; 0xff
8004f98: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
8004f9a: 68fb ldr r3, [r7, #12]
8004f9c: 8d1b ldrh r3, [r3, #40] ; 0x28
8004f9e: b2da uxtb r2, r3
8004fa0: 8979 ldrh r1, [r7, #10]
8004fa2: 4b51 ldr r3, [pc, #324] ; (80050e8 <HAL_I2C_Master_Transmit+0x1e0>)
8004fa4: 9300 str r3, [sp, #0]
8004fa6: f04f 7380 mov.w r3, #16777216 ; 0x1000000
8004faa: 68f8 ldr r0, [r7, #12]
8004fac: f000 fa6c bl 8005488 <I2C_TransferConfig>
8004fb0: e06c b.n 800508c <HAL_I2C_Master_Transmit+0x184>
I2C_GENERATE_START_WRITE);
}
else
{
hi2c->XferSize = hi2c->XferCount;
8004fb2: 68fb ldr r3, [r7, #12]
8004fb4: 8d5b ldrh r3, [r3, #42] ; 0x2a
8004fb6: b29a uxth r2, r3
8004fb8: 68fb ldr r3, [r7, #12]
8004fba: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
8004fbc: 68fb ldr r3, [r7, #12]
8004fbe: 8d1b ldrh r3, [r3, #40] ; 0x28
8004fc0: b2da uxtb r2, r3
8004fc2: 8979 ldrh r1, [r7, #10]
8004fc4: 4b48 ldr r3, [pc, #288] ; (80050e8 <HAL_I2C_Master_Transmit+0x1e0>)
8004fc6: 9300 str r3, [sp, #0]
8004fc8: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8004fcc: 68f8 ldr r0, [r7, #12]
8004fce: f000 fa5b bl 8005488 <I2C_TransferConfig>
I2C_GENERATE_START_WRITE);
}
while (hi2c->XferCount > 0U)
8004fd2: e05b b.n 800508c <HAL_I2C_Master_Transmit+0x184>
{
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8004fd4: 697a ldr r2, [r7, #20]
8004fd6: 6a39 ldr r1, [r7, #32]
8004fd8: 68f8 ldr r0, [r7, #12]
8004fda: f000 f8ed bl 80051b8 <I2C_WaitOnTXISFlagUntilTimeout>
8004fde: 4603 mov r3, r0
8004fe0: 2b00 cmp r3, #0
8004fe2: d001 beq.n 8004fe8 <HAL_I2C_Master_Transmit+0xe0>
{
return HAL_ERROR;
8004fe4: 2301 movs r3, #1
8004fe6: e07b b.n 80050e0 <HAL_I2C_Master_Transmit+0x1d8>
}
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
8004fe8: 68fb ldr r3, [r7, #12]
8004fea: 6a5b ldr r3, [r3, #36] ; 0x24
8004fec: 781a ldrb r2, [r3, #0]
8004fee: 68fb ldr r3, [r7, #12]
8004ff0: 681b ldr r3, [r3, #0]
8004ff2: 629a str r2, [r3, #40] ; 0x28
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8004ff4: 68fb ldr r3, [r7, #12]
8004ff6: 6a5b ldr r3, [r3, #36] ; 0x24
8004ff8: 1c5a adds r2, r3, #1
8004ffa: 68fb ldr r3, [r7, #12]
8004ffc: 625a str r2, [r3, #36] ; 0x24
hi2c->XferCount--;
8004ffe: 68fb ldr r3, [r7, #12]
8005000: 8d5b ldrh r3, [r3, #42] ; 0x2a
8005002: b29b uxth r3, r3
8005004: 3b01 subs r3, #1
8005006: b29a uxth r2, r3
8005008: 68fb ldr r3, [r7, #12]
800500a: 855a strh r2, [r3, #42] ; 0x2a
hi2c->XferSize--;
800500c: 68fb ldr r3, [r7, #12]
800500e: 8d1b ldrh r3, [r3, #40] ; 0x28
8005010: 3b01 subs r3, #1
8005012: b29a uxth r2, r3
8005014: 68fb ldr r3, [r7, #12]
8005016: 851a strh r2, [r3, #40] ; 0x28
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
8005018: 68fb ldr r3, [r7, #12]
800501a: 8d5b ldrh r3, [r3, #42] ; 0x2a
800501c: b29b uxth r3, r3
800501e: 2b00 cmp r3, #0
8005020: d034 beq.n 800508c <HAL_I2C_Master_Transmit+0x184>
8005022: 68fb ldr r3, [r7, #12]
8005024: 8d1b ldrh r3, [r3, #40] ; 0x28
8005026: 2b00 cmp r3, #0
8005028: d130 bne.n 800508c <HAL_I2C_Master_Transmit+0x184>
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
800502a: 697b ldr r3, [r7, #20]
800502c: 9300 str r3, [sp, #0]
800502e: 6a3b ldr r3, [r7, #32]
8005030: 2200 movs r2, #0
8005032: 2180 movs r1, #128 ; 0x80
8005034: 68f8 ldr r0, [r7, #12]
8005036: f000 f87f bl 8005138 <I2C_WaitOnFlagUntilTimeout>
800503a: 4603 mov r3, r0
800503c: 2b00 cmp r3, #0
800503e: d001 beq.n 8005044 <HAL_I2C_Master_Transmit+0x13c>
{
return HAL_ERROR;
8005040: 2301 movs r3, #1
8005042: e04d b.n 80050e0 <HAL_I2C_Master_Transmit+0x1d8>
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
8005044: 68fb ldr r3, [r7, #12]
8005046: 8d5b ldrh r3, [r3, #42] ; 0x2a
8005048: b29b uxth r3, r3
800504a: 2bff cmp r3, #255 ; 0xff
800504c: d90e bls.n 800506c <HAL_I2C_Master_Transmit+0x164>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
800504e: 68fb ldr r3, [r7, #12]
8005050: 22ff movs r2, #255 ; 0xff
8005052: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
8005054: 68fb ldr r3, [r7, #12]
8005056: 8d1b ldrh r3, [r3, #40] ; 0x28
8005058: b2da uxtb r2, r3
800505a: 8979 ldrh r1, [r7, #10]
800505c: 2300 movs r3, #0
800505e: 9300 str r3, [sp, #0]
8005060: f04f 7380 mov.w r3, #16777216 ; 0x1000000
8005064: 68f8 ldr r0, [r7, #12]
8005066: f000 fa0f bl 8005488 <I2C_TransferConfig>
800506a: e00f b.n 800508c <HAL_I2C_Master_Transmit+0x184>
I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
800506c: 68fb ldr r3, [r7, #12]
800506e: 8d5b ldrh r3, [r3, #42] ; 0x2a
8005070: b29a uxth r2, r3
8005072: 68fb ldr r3, [r7, #12]
8005074: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
8005076: 68fb ldr r3, [r7, #12]
8005078: 8d1b ldrh r3, [r3, #40] ; 0x28
800507a: b2da uxtb r2, r3
800507c: 8979 ldrh r1, [r7, #10]
800507e: 2300 movs r3, #0
8005080: 9300 str r3, [sp, #0]
8005082: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8005086: 68f8 ldr r0, [r7, #12]
8005088: f000 f9fe bl 8005488 <I2C_TransferConfig>
while (hi2c->XferCount > 0U)
800508c: 68fb ldr r3, [r7, #12]
800508e: 8d5b ldrh r3, [r3, #42] ; 0x2a
8005090: b29b uxth r3, r3
8005092: 2b00 cmp r3, #0
8005094: d19e bne.n 8004fd4 <HAL_I2C_Master_Transmit+0xcc>
}
}
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8005096: 697a ldr r2, [r7, #20]
8005098: 6a39 ldr r1, [r7, #32]
800509a: 68f8 ldr r0, [r7, #12]
800509c: f000 f8cc bl 8005238 <I2C_WaitOnSTOPFlagUntilTimeout>
80050a0: 4603 mov r3, r0
80050a2: 2b00 cmp r3, #0
80050a4: d001 beq.n 80050aa <HAL_I2C_Master_Transmit+0x1a2>
{
return HAL_ERROR;
80050a6: 2301 movs r3, #1
80050a8: e01a b.n 80050e0 <HAL_I2C_Master_Transmit+0x1d8>
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
80050aa: 68fb ldr r3, [r7, #12]
80050ac: 681b ldr r3, [r3, #0]
80050ae: 2220 movs r2, #32
80050b0: 61da str r2, [r3, #28]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
80050b2: 68fb ldr r3, [r7, #12]
80050b4: 681b ldr r3, [r3, #0]
80050b6: 6859 ldr r1, [r3, #4]
80050b8: 68fb ldr r3, [r7, #12]
80050ba: 681a ldr r2, [r3, #0]
80050bc: 4b0b ldr r3, [pc, #44] ; (80050ec <HAL_I2C_Master_Transmit+0x1e4>)
80050be: 400b ands r3, r1
80050c0: 6053 str r3, [r2, #4]
hi2c->State = HAL_I2C_STATE_READY;
80050c2: 68fb ldr r3, [r7, #12]
80050c4: 2220 movs r2, #32
80050c6: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
80050ca: 68fb ldr r3, [r7, #12]
80050cc: 2200 movs r2, #0
80050ce: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80050d2: 68fb ldr r3, [r7, #12]
80050d4: 2200 movs r2, #0
80050d6: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_OK;
80050da: 2300 movs r3, #0
80050dc: e000 b.n 80050e0 <HAL_I2C_Master_Transmit+0x1d8>
}
else
{
return HAL_BUSY;
80050de: 2302 movs r3, #2
}
}
80050e0: 4618 mov r0, r3
80050e2: 3718 adds r7, #24
80050e4: 46bd mov sp, r7
80050e6: bd80 pop {r7, pc}
80050e8: 80002000 .word 0x80002000
80050ec: fe00e800 .word 0xfe00e800
080050f0 <I2C_Flush_TXDR>:
* @brief I2C Tx data register flush process.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
{
80050f0: b480 push {r7}
80050f2: b083 sub sp, #12
80050f4: af00 add r7, sp, #0
80050f6: 6078 str r0, [r7, #4]
/* If a pending TXIS flag is set */
/* Write a dummy data in TXDR to clear it */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
80050f8: 687b ldr r3, [r7, #4]
80050fa: 681b ldr r3, [r3, #0]
80050fc: 699b ldr r3, [r3, #24]
80050fe: f003 0302 and.w r3, r3, #2
8005102: 2b02 cmp r3, #2
8005104: d103 bne.n 800510e <I2C_Flush_TXDR+0x1e>
{
hi2c->Instance->TXDR = 0x00U;
8005106: 687b ldr r3, [r7, #4]
8005108: 681b ldr r3, [r3, #0]
800510a: 2200 movs r2, #0
800510c: 629a str r2, [r3, #40] ; 0x28
}
/* Flush TX register if not empty */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
800510e: 687b ldr r3, [r7, #4]
8005110: 681b ldr r3, [r3, #0]
8005112: 699b ldr r3, [r3, #24]
8005114: f003 0301 and.w r3, r3, #1
8005118: 2b01 cmp r3, #1
800511a: d007 beq.n 800512c <I2C_Flush_TXDR+0x3c>
{
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
800511c: 687b ldr r3, [r7, #4]
800511e: 681b ldr r3, [r3, #0]
8005120: 699a ldr r2, [r3, #24]
8005122: 687b ldr r3, [r7, #4]
8005124: 681b ldr r3, [r3, #0]
8005126: f042 0201 orr.w r2, r2, #1
800512a: 619a str r2, [r3, #24]
}
}
800512c: bf00 nop
800512e: 370c adds r7, #12
8005130: 46bd mov sp, r7
8005132: f85d 7b04 ldr.w r7, [sp], #4
8005136: 4770 bx lr
08005138 <I2C_WaitOnFlagUntilTimeout>:
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
uint32_t Timeout, uint32_t Tickstart)
{
8005138: b580 push {r7, lr}
800513a: b084 sub sp, #16
800513c: af00 add r7, sp, #0
800513e: 60f8 str r0, [r7, #12]
8005140: 60b9 str r1, [r7, #8]
8005142: 603b str r3, [r7, #0]
8005144: 4613 mov r3, r2
8005146: 71fb strb r3, [r7, #7]
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
8005148: e022 b.n 8005190 <I2C_WaitOnFlagUntilTimeout+0x58>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
800514a: 683b ldr r3, [r7, #0]
800514c: f1b3 3fff cmp.w r3, #4294967295
8005150: d01e beq.n 8005190 <I2C_WaitOnFlagUntilTimeout+0x58>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8005152: f7fc fdff bl 8001d54 <HAL_GetTick>
8005156: 4602 mov r2, r0
8005158: 69bb ldr r3, [r7, #24]
800515a: 1ad3 subs r3, r2, r3
800515c: 683a ldr r2, [r7, #0]
800515e: 429a cmp r2, r3
8005160: d302 bcc.n 8005168 <I2C_WaitOnFlagUntilTimeout+0x30>
8005162: 683b ldr r3, [r7, #0]
8005164: 2b00 cmp r3, #0
8005166: d113 bne.n 8005190 <I2C_WaitOnFlagUntilTimeout+0x58>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8005168: 68fb ldr r3, [r7, #12]
800516a: 6c5b ldr r3, [r3, #68] ; 0x44
800516c: f043 0220 orr.w r2, r3, #32
8005170: 68fb ldr r3, [r7, #12]
8005172: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8005174: 68fb ldr r3, [r7, #12]
8005176: 2220 movs r2, #32
8005178: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
800517c: 68fb ldr r3, [r7, #12]
800517e: 2200 movs r2, #0
8005180: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8005184: 68fb ldr r3, [r7, #12]
8005186: 2200 movs r2, #0
8005188: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
800518c: 2301 movs r3, #1
800518e: e00f b.n 80051b0 <I2C_WaitOnFlagUntilTimeout+0x78>
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
8005190: 68fb ldr r3, [r7, #12]
8005192: 681b ldr r3, [r3, #0]
8005194: 699a ldr r2, [r3, #24]
8005196: 68bb ldr r3, [r7, #8]
8005198: 4013 ands r3, r2
800519a: 68ba ldr r2, [r7, #8]
800519c: 429a cmp r2, r3
800519e: bf0c ite eq
80051a0: 2301 moveq r3, #1
80051a2: 2300 movne r3, #0
80051a4: b2db uxtb r3, r3
80051a6: 461a mov r2, r3
80051a8: 79fb ldrb r3, [r7, #7]
80051aa: 429a cmp r2, r3
80051ac: d0cd beq.n 800514a <I2C_WaitOnFlagUntilTimeout+0x12>
}
}
}
return HAL_OK;
80051ae: 2300 movs r3, #0
}
80051b0: 4618 mov r0, r3
80051b2: 3710 adds r7, #16
80051b4: 46bd mov sp, r7
80051b6: bd80 pop {r7, pc}
080051b8 <I2C_WaitOnTXISFlagUntilTimeout>:
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart)
{
80051b8: b580 push {r7, lr}
80051ba: b084 sub sp, #16
80051bc: af00 add r7, sp, #0
80051be: 60f8 str r0, [r7, #12]
80051c0: 60b9 str r1, [r7, #8]
80051c2: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
80051c4: e02c b.n 8005220 <I2C_WaitOnTXISFlagUntilTimeout+0x68>
{
/* Check if an error is detected */
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
80051c6: 687a ldr r2, [r7, #4]
80051c8: 68b9 ldr r1, [r7, #8]
80051ca: 68f8 ldr r0, [r7, #12]
80051cc: f000 f870 bl 80052b0 <I2C_IsErrorOccurred>
80051d0: 4603 mov r3, r0
80051d2: 2b00 cmp r3, #0
80051d4: d001 beq.n 80051da <I2C_WaitOnTXISFlagUntilTimeout+0x22>
{
return HAL_ERROR;
80051d6: 2301 movs r3, #1
80051d8: e02a b.n 8005230 <I2C_WaitOnTXISFlagUntilTimeout+0x78>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
80051da: 68bb ldr r3, [r7, #8]
80051dc: f1b3 3fff cmp.w r3, #4294967295
80051e0: d01e beq.n 8005220 <I2C_WaitOnTXISFlagUntilTimeout+0x68>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
80051e2: f7fc fdb7 bl 8001d54 <HAL_GetTick>
80051e6: 4602 mov r2, r0
80051e8: 687b ldr r3, [r7, #4]
80051ea: 1ad3 subs r3, r2, r3
80051ec: 68ba ldr r2, [r7, #8]
80051ee: 429a cmp r2, r3
80051f0: d302 bcc.n 80051f8 <I2C_WaitOnTXISFlagUntilTimeout+0x40>
80051f2: 68bb ldr r3, [r7, #8]
80051f4: 2b00 cmp r3, #0
80051f6: d113 bne.n 8005220 <I2C_WaitOnTXISFlagUntilTimeout+0x68>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
80051f8: 68fb ldr r3, [r7, #12]
80051fa: 6c5b ldr r3, [r3, #68] ; 0x44
80051fc: f043 0220 orr.w r2, r3, #32
8005200: 68fb ldr r3, [r7, #12]
8005202: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8005204: 68fb ldr r3, [r7, #12]
8005206: 2220 movs r2, #32
8005208: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
800520c: 68fb ldr r3, [r7, #12]
800520e: 2200 movs r2, #0
8005210: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8005214: 68fb ldr r3, [r7, #12]
8005216: 2200 movs r2, #0
8005218: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
800521c: 2301 movs r3, #1
800521e: e007 b.n 8005230 <I2C_WaitOnTXISFlagUntilTimeout+0x78>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
8005220: 68fb ldr r3, [r7, #12]
8005222: 681b ldr r3, [r3, #0]
8005224: 699b ldr r3, [r3, #24]
8005226: f003 0302 and.w r3, r3, #2
800522a: 2b02 cmp r3, #2
800522c: d1cb bne.n 80051c6 <I2C_WaitOnTXISFlagUntilTimeout+0xe>
}
}
}
return HAL_OK;
800522e: 2300 movs r3, #0
}
8005230: 4618 mov r0, r3
8005232: 3710 adds r7, #16
8005234: 46bd mov sp, r7
8005236: bd80 pop {r7, pc}
08005238 <I2C_WaitOnSTOPFlagUntilTimeout>:
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart)
{
8005238: b580 push {r7, lr}
800523a: b084 sub sp, #16
800523c: af00 add r7, sp, #0
800523e: 60f8 str r0, [r7, #12]
8005240: 60b9 str r1, [r7, #8]
8005242: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8005244: e028 b.n 8005298 <I2C_WaitOnSTOPFlagUntilTimeout+0x60>
{
/* Check if an error is detected */
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
8005246: 687a ldr r2, [r7, #4]
8005248: 68b9 ldr r1, [r7, #8]
800524a: 68f8 ldr r0, [r7, #12]
800524c: f000 f830 bl 80052b0 <I2C_IsErrorOccurred>
8005250: 4603 mov r3, r0
8005252: 2b00 cmp r3, #0
8005254: d001 beq.n 800525a <I2C_WaitOnSTOPFlagUntilTimeout+0x22>
{
return HAL_ERROR;
8005256: 2301 movs r3, #1
8005258: e026 b.n 80052a8 <I2C_WaitOnSTOPFlagUntilTimeout+0x70>
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
800525a: f7fc fd7b bl 8001d54 <HAL_GetTick>
800525e: 4602 mov r2, r0
8005260: 687b ldr r3, [r7, #4]
8005262: 1ad3 subs r3, r2, r3
8005264: 68ba ldr r2, [r7, #8]
8005266: 429a cmp r2, r3
8005268: d302 bcc.n 8005270 <I2C_WaitOnSTOPFlagUntilTimeout+0x38>
800526a: 68bb ldr r3, [r7, #8]
800526c: 2b00 cmp r3, #0
800526e: d113 bne.n 8005298 <I2C_WaitOnSTOPFlagUntilTimeout+0x60>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8005270: 68fb ldr r3, [r7, #12]
8005272: 6c5b ldr r3, [r3, #68] ; 0x44
8005274: f043 0220 orr.w r2, r3, #32
8005278: 68fb ldr r3, [r7, #12]
800527a: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
800527c: 68fb ldr r3, [r7, #12]
800527e: 2220 movs r2, #32
8005280: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8005284: 68fb ldr r3, [r7, #12]
8005286: 2200 movs r2, #0
8005288: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800528c: 68fb ldr r3, [r7, #12]
800528e: 2200 movs r2, #0
8005290: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8005294: 2301 movs r3, #1
8005296: e007 b.n 80052a8 <I2C_WaitOnSTOPFlagUntilTimeout+0x70>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8005298: 68fb ldr r3, [r7, #12]
800529a: 681b ldr r3, [r3, #0]
800529c: 699b ldr r3, [r3, #24]
800529e: f003 0320 and.w r3, r3, #32
80052a2: 2b20 cmp r3, #32
80052a4: d1cf bne.n 8005246 <I2C_WaitOnSTOPFlagUntilTimeout+0xe>
}
}
return HAL_OK;
80052a6: 2300 movs r3, #0
}
80052a8: 4618 mov r0, r3
80052aa: 3710 adds r7, #16
80052ac: 46bd mov sp, r7
80052ae: bd80 pop {r7, pc}
080052b0 <I2C_IsErrorOccurred>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
80052b0: b580 push {r7, lr}
80052b2: b08a sub sp, #40 ; 0x28
80052b4: af00 add r7, sp, #0
80052b6: 60f8 str r0, [r7, #12]
80052b8: 60b9 str r1, [r7, #8]
80052ba: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80052bc: 2300 movs r3, #0
80052be: f887 3027 strb.w r3, [r7, #39] ; 0x27
uint32_t itflag = hi2c->Instance->ISR;
80052c2: 68fb ldr r3, [r7, #12]
80052c4: 681b ldr r3, [r3, #0]
80052c6: 699b ldr r3, [r3, #24]
80052c8: 61bb str r3, [r7, #24]
uint32_t error_code = 0;
80052ca: 2300 movs r3, #0
80052cc: 623b str r3, [r7, #32]
uint32_t tickstart = Tickstart;
80052ce: 687b ldr r3, [r7, #4]
80052d0: 61fb str r3, [r7, #28]
uint32_t tmp1;
HAL_I2C_ModeTypeDef tmp2;
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
80052d2: 69bb ldr r3, [r7, #24]
80052d4: f003 0310 and.w r3, r3, #16
80052d8: 2b00 cmp r3, #0
80052da: d075 beq.n 80053c8 <I2C_IsErrorOccurred+0x118>
{
/* Clear NACKF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
80052dc: 68fb ldr r3, [r7, #12]
80052de: 681b ldr r3, [r3, #0]
80052e0: 2210 movs r2, #16
80052e2: 61da str r2, [r3, #28]
/* Wait until STOP Flag is set or timeout occurred */
/* AutoEnd should be initiate after AF */
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
80052e4: e056 b.n 8005394 <I2C_IsErrorOccurred+0xe4>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
80052e6: 68bb ldr r3, [r7, #8]
80052e8: f1b3 3fff cmp.w r3, #4294967295
80052ec: d052 beq.n 8005394 <I2C_IsErrorOccurred+0xe4>
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
80052ee: f7fc fd31 bl 8001d54 <HAL_GetTick>
80052f2: 4602 mov r2, r0
80052f4: 69fb ldr r3, [r7, #28]
80052f6: 1ad3 subs r3, r2, r3
80052f8: 68ba ldr r2, [r7, #8]
80052fa: 429a cmp r2, r3
80052fc: d302 bcc.n 8005304 <I2C_IsErrorOccurred+0x54>
80052fe: 68bb ldr r3, [r7, #8]
8005300: 2b00 cmp r3, #0
8005302: d147 bne.n 8005394 <I2C_IsErrorOccurred+0xe4>
{
tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
8005304: 68fb ldr r3, [r7, #12]
8005306: 681b ldr r3, [r3, #0]
8005308: 685b ldr r3, [r3, #4]
800530a: f403 4380 and.w r3, r3, #16384 ; 0x4000
800530e: 617b str r3, [r7, #20]
tmp2 = hi2c->Mode;
8005310: 68fb ldr r3, [r7, #12]
8005312: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
8005316: 74fb strb r3, [r7, #19]
/* In case of I2C still busy, try to regenerate a STOP manually */
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
8005318: 68fb ldr r3, [r7, #12]
800531a: 681b ldr r3, [r3, #0]
800531c: 699b ldr r3, [r3, #24]
800531e: f403 4300 and.w r3, r3, #32768 ; 0x8000
8005322: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
8005326: d12e bne.n 8005386 <I2C_IsErrorOccurred+0xd6>
8005328: 697b ldr r3, [r7, #20]
800532a: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
800532e: d02a beq.n 8005386 <I2C_IsErrorOccurred+0xd6>
(tmp1 != I2C_CR2_STOP) && \
8005330: 7cfb ldrb r3, [r7, #19]
8005332: 2b20 cmp r3, #32
8005334: d027 beq.n 8005386 <I2C_IsErrorOccurred+0xd6>
(tmp2 != HAL_I2C_MODE_SLAVE))
{
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
8005336: 68fb ldr r3, [r7, #12]
8005338: 681b ldr r3, [r3, #0]
800533a: 685a ldr r2, [r3, #4]
800533c: 68fb ldr r3, [r7, #12]
800533e: 681b ldr r3, [r3, #0]
8005340: f442 4280 orr.w r2, r2, #16384 ; 0x4000
8005344: 605a str r2, [r3, #4]
/* Update Tick with new reference */
tickstart = HAL_GetTick();
8005346: f7fc fd05 bl 8001d54 <HAL_GetTick>
800534a: 61f8 str r0, [r7, #28]
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
800534c: e01b b.n 8005386 <I2C_IsErrorOccurred+0xd6>
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
800534e: f7fc fd01 bl 8001d54 <HAL_GetTick>
8005352: 4602 mov r2, r0
8005354: 69fb ldr r3, [r7, #28]
8005356: 1ad3 subs r3, r2, r3
8005358: 2b19 cmp r3, #25
800535a: d914 bls.n 8005386 <I2C_IsErrorOccurred+0xd6>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
800535c: 68fb ldr r3, [r7, #12]
800535e: 6c5b ldr r3, [r3, #68] ; 0x44
8005360: f043 0220 orr.w r2, r3, #32
8005364: 68fb ldr r3, [r7, #12]
8005366: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8005368: 68fb ldr r3, [r7, #12]
800536a: 2220 movs r2, #32
800536c: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8005370: 68fb ldr r3, [r7, #12]
8005372: 2200 movs r2, #0
8005374: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8005378: 68fb ldr r3, [r7, #12]
800537a: 2200 movs r2, #0
800537c: f883 2040 strb.w r2, [r3, #64] ; 0x40
status = HAL_ERROR;
8005380: 2301 movs r3, #1
8005382: f887 3027 strb.w r3, [r7, #39] ; 0x27
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8005386: 68fb ldr r3, [r7, #12]
8005388: 681b ldr r3, [r3, #0]
800538a: 699b ldr r3, [r3, #24]
800538c: f003 0320 and.w r3, r3, #32
8005390: 2b20 cmp r3, #32
8005392: d1dc bne.n 800534e <I2C_IsErrorOccurred+0x9e>
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
8005394: 68fb ldr r3, [r7, #12]
8005396: 681b ldr r3, [r3, #0]
8005398: 699b ldr r3, [r3, #24]
800539a: f003 0320 and.w r3, r3, #32
800539e: 2b20 cmp r3, #32
80053a0: d003 beq.n 80053aa <I2C_IsErrorOccurred+0xfa>
80053a2: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80053a6: 2b00 cmp r3, #0
80053a8: d09d beq.n 80052e6 <I2C_IsErrorOccurred+0x36>
}
}
}
/* In case STOP Flag is detected, clear it */
if (status == HAL_OK)
80053aa: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80053ae: 2b00 cmp r3, #0
80053b0: d103 bne.n 80053ba <I2C_IsErrorOccurred+0x10a>
{
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
80053b2: 68fb ldr r3, [r7, #12]
80053b4: 681b ldr r3, [r3, #0]
80053b6: 2220 movs r2, #32
80053b8: 61da str r2, [r3, #28]
}
error_code |= HAL_I2C_ERROR_AF;
80053ba: 6a3b ldr r3, [r7, #32]
80053bc: f043 0304 orr.w r3, r3, #4
80053c0: 623b str r3, [r7, #32]
status = HAL_ERROR;
80053c2: 2301 movs r3, #1
80053c4: f887 3027 strb.w r3, [r7, #39] ; 0x27
}
/* Refresh Content of Status register */
itflag = hi2c->Instance->ISR;
80053c8: 68fb ldr r3, [r7, #12]
80053ca: 681b ldr r3, [r3, #0]
80053cc: 699b ldr r3, [r3, #24]
80053ce: 61bb str r3, [r7, #24]
/* Then verify if an additional errors occurs */
/* Check if a Bus error occurred */
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
80053d0: 69bb ldr r3, [r7, #24]
80053d2: f403 7380 and.w r3, r3, #256 ; 0x100
80053d6: 2b00 cmp r3, #0
80053d8: d00b beq.n 80053f2 <I2C_IsErrorOccurred+0x142>
{
error_code |= HAL_I2C_ERROR_BERR;
80053da: 6a3b ldr r3, [r7, #32]
80053dc: f043 0301 orr.w r3, r3, #1
80053e0: 623b str r3, [r7, #32]
/* Clear BERR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
80053e2: 68fb ldr r3, [r7, #12]
80053e4: 681b ldr r3, [r3, #0]
80053e6: f44f 7280 mov.w r2, #256 ; 0x100
80053ea: 61da str r2, [r3, #28]
status = HAL_ERROR;
80053ec: 2301 movs r3, #1
80053ee: f887 3027 strb.w r3, [r7, #39] ; 0x27
}
/* Check if an Over-Run/Under-Run error occurred */
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
80053f2: 69bb ldr r3, [r7, #24]
80053f4: f403 6380 and.w r3, r3, #1024 ; 0x400
80053f8: 2b00 cmp r3, #0
80053fa: d00b beq.n 8005414 <I2C_IsErrorOccurred+0x164>
{
error_code |= HAL_I2C_ERROR_OVR;
80053fc: 6a3b ldr r3, [r7, #32]
80053fe: f043 0308 orr.w r3, r3, #8
8005402: 623b str r3, [r7, #32]
/* Clear OVR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
8005404: 68fb ldr r3, [r7, #12]
8005406: 681b ldr r3, [r3, #0]
8005408: f44f 6280 mov.w r2, #1024 ; 0x400
800540c: 61da str r2, [r3, #28]
status = HAL_ERROR;
800540e: 2301 movs r3, #1
8005410: f887 3027 strb.w r3, [r7, #39] ; 0x27
}
/* Check if an Arbitration Loss error occurred */
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
8005414: 69bb ldr r3, [r7, #24]
8005416: f403 7300 and.w r3, r3, #512 ; 0x200
800541a: 2b00 cmp r3, #0
800541c: d00b beq.n 8005436 <I2C_IsErrorOccurred+0x186>
{
error_code |= HAL_I2C_ERROR_ARLO;
800541e: 6a3b ldr r3, [r7, #32]
8005420: f043 0302 orr.w r3, r3, #2
8005424: 623b str r3, [r7, #32]
/* Clear ARLO flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
8005426: 68fb ldr r3, [r7, #12]
8005428: 681b ldr r3, [r3, #0]
800542a: f44f 7200 mov.w r2, #512 ; 0x200
800542e: 61da str r2, [r3, #28]
status = HAL_ERROR;
8005430: 2301 movs r3, #1
8005432: f887 3027 strb.w r3, [r7, #39] ; 0x27
}
if (status != HAL_OK)
8005436: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
800543a: 2b00 cmp r3, #0
800543c: d01c beq.n 8005478 <I2C_IsErrorOccurred+0x1c8>
{
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
800543e: 68f8 ldr r0, [r7, #12]
8005440: f7ff fe56 bl 80050f0 <I2C_Flush_TXDR>
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
8005444: 68fb ldr r3, [r7, #12]
8005446: 681b ldr r3, [r3, #0]
8005448: 6859 ldr r1, [r3, #4]
800544a: 68fb ldr r3, [r7, #12]
800544c: 681a ldr r2, [r3, #0]
800544e: 4b0d ldr r3, [pc, #52] ; (8005484 <I2C_IsErrorOccurred+0x1d4>)
8005450: 400b ands r3, r1
8005452: 6053 str r3, [r2, #4]
hi2c->ErrorCode |= error_code;
8005454: 68fb ldr r3, [r7, #12]
8005456: 6c5a ldr r2, [r3, #68] ; 0x44
8005458: 6a3b ldr r3, [r7, #32]
800545a: 431a orrs r2, r3
800545c: 68fb ldr r3, [r7, #12]
800545e: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8005460: 68fb ldr r3, [r7, #12]
8005462: 2220 movs r2, #32
8005464: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8005468: 68fb ldr r3, [r7, #12]
800546a: 2200 movs r2, #0
800546c: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8005470: 68fb ldr r3, [r7, #12]
8005472: 2200 movs r2, #0
8005474: f883 2040 strb.w r2, [r3, #64] ; 0x40
}
return status;
8005478: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
}
800547c: 4618 mov r0, r3
800547e: 3728 adds r7, #40 ; 0x28
8005480: 46bd mov sp, r7
8005482: bd80 pop {r7, pc}
8005484: fe00e800 .word 0xfe00e800
08005488 <I2C_TransferConfig>:
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
uint32_t Request)
{
8005488: b480 push {r7}
800548a: b087 sub sp, #28
800548c: af00 add r7, sp, #0
800548e: 60f8 str r0, [r7, #12]
8005490: 607b str r3, [r7, #4]
8005492: 460b mov r3, r1
8005494: 817b strh r3, [r7, #10]
8005496: 4613 mov r3, r2
8005498: 727b strb r3, [r7, #9]
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request));
/* Declaration of tmp to prevent undefined behavior of volatile usage */
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
800549a: 897b ldrh r3, [r7, #10]
800549c: f3c3 0209 ubfx r2, r3, #0, #10
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
80054a0: 7a7b ldrb r3, [r7, #9]
80054a2: 041b lsls r3, r3, #16
80054a4: f403 037f and.w r3, r3, #16711680 ; 0xff0000
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
80054a8: 431a orrs r2, r3
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
80054aa: 687b ldr r3, [r7, #4]
80054ac: 431a orrs r2, r3
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
80054ae: 6a3b ldr r3, [r7, #32]
80054b0: 4313 orrs r3, r2
80054b2: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000
80054b6: 617b str r3, [r7, #20]
(uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
/* update CR2 register */
MODIFY_REG(hi2c->Instance->CR2, \
80054b8: 68fb ldr r3, [r7, #12]
80054ba: 681b ldr r3, [r3, #0]
80054bc: 685a ldr r2, [r3, #4]
80054be: 6a3b ldr r3, [r7, #32]
80054c0: 0d5b lsrs r3, r3, #21
80054c2: f403 6180 and.w r1, r3, #1024 ; 0x400
80054c6: 4b08 ldr r3, [pc, #32] ; (80054e8 <I2C_TransferConfig+0x60>)
80054c8: 430b orrs r3, r1
80054ca: 43db mvns r3, r3
80054cc: ea02 0103 and.w r1, r2, r3
80054d0: 68fb ldr r3, [r7, #12]
80054d2: 681b ldr r3, [r3, #0]
80054d4: 697a ldr r2, [r7, #20]
80054d6: 430a orrs r2, r1
80054d8: 605a str r2, [r3, #4]
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
I2C_CR2_START | I2C_CR2_STOP)), tmp);
}
80054da: bf00 nop
80054dc: 371c adds r7, #28
80054de: 46bd mov sp, r7
80054e0: f85d 7b04 ldr.w r7, [sp], #4
80054e4: 4770 bx lr
80054e6: bf00 nop
80054e8: 03ff63ff .word 0x03ff63ff
080054ec <HAL_I2CEx_ConfigAnalogFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
80054ec: b480 push {r7}
80054ee: b083 sub sp, #12
80054f0: af00 add r7, sp, #0
80054f2: 6078 str r0, [r7, #4]
80054f4: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
80054f6: 687b ldr r3, [r7, #4]
80054f8: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
80054fc: b2db uxtb r3, r3
80054fe: 2b20 cmp r3, #32
8005500: d138 bne.n 8005574 <HAL_I2CEx_ConfigAnalogFilter+0x88>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8005502: 687b ldr r3, [r7, #4]
8005504: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
8005508: 2b01 cmp r3, #1
800550a: d101 bne.n 8005510 <HAL_I2CEx_ConfigAnalogFilter+0x24>
800550c: 2302 movs r3, #2
800550e: e032 b.n 8005576 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
8005510: 687b ldr r3, [r7, #4]
8005512: 2201 movs r2, #1
8005514: f883 2040 strb.w r2, [r3, #64] ; 0x40
hi2c->State = HAL_I2C_STATE_BUSY;
8005518: 687b ldr r3, [r7, #4]
800551a: 2224 movs r2, #36 ; 0x24
800551c: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8005520: 687b ldr r3, [r7, #4]
8005522: 681b ldr r3, [r3, #0]
8005524: 681a ldr r2, [r3, #0]
8005526: 687b ldr r3, [r7, #4]
8005528: 681b ldr r3, [r3, #0]
800552a: f022 0201 bic.w r2, r2, #1
800552e: 601a str r2, [r3, #0]
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
8005530: 687b ldr r3, [r7, #4]
8005532: 681b ldr r3, [r3, #0]
8005534: 681a ldr r2, [r3, #0]
8005536: 687b ldr r3, [r7, #4]
8005538: 681b ldr r3, [r3, #0]
800553a: f422 5280 bic.w r2, r2, #4096 ; 0x1000
800553e: 601a str r2, [r3, #0]
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
8005540: 687b ldr r3, [r7, #4]
8005542: 681b ldr r3, [r3, #0]
8005544: 6819 ldr r1, [r3, #0]
8005546: 687b ldr r3, [r7, #4]
8005548: 681b ldr r3, [r3, #0]
800554a: 683a ldr r2, [r7, #0]
800554c: 430a orrs r2, r1
800554e: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
8005550: 687b ldr r3, [r7, #4]
8005552: 681b ldr r3, [r3, #0]
8005554: 681a ldr r2, [r3, #0]
8005556: 687b ldr r3, [r7, #4]
8005558: 681b ldr r3, [r3, #0]
800555a: f042 0201 orr.w r2, r2, #1
800555e: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
8005560: 687b ldr r3, [r7, #4]
8005562: 2220 movs r2, #32
8005564: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8005568: 687b ldr r3, [r7, #4]
800556a: 2200 movs r2, #0
800556c: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_OK;
8005570: 2300 movs r3, #0
8005572: e000 b.n 8005576 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
}
else
{
return HAL_BUSY;
8005574: 2302 movs r3, #2
}
}
8005576: 4618 mov r0, r3
8005578: 370c adds r7, #12
800557a: 46bd mov sp, r7
800557c: f85d 7b04 ldr.w r7, [sp], #4
8005580: 4770 bx lr
08005582 <HAL_I2CEx_ConfigDigitalFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
8005582: b480 push {r7}
8005584: b085 sub sp, #20
8005586: af00 add r7, sp, #0
8005588: 6078 str r0, [r7, #4]
800558a: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
800558c: 687b ldr r3, [r7, #4]
800558e: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8005592: b2db uxtb r3, r3
8005594: 2b20 cmp r3, #32
8005596: d139 bne.n 800560c <HAL_I2CEx_ConfigDigitalFilter+0x8a>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8005598: 687b ldr r3, [r7, #4]
800559a: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
800559e: 2b01 cmp r3, #1
80055a0: d101 bne.n 80055a6 <HAL_I2CEx_ConfigDigitalFilter+0x24>
80055a2: 2302 movs r3, #2
80055a4: e033 b.n 800560e <HAL_I2CEx_ConfigDigitalFilter+0x8c>
80055a6: 687b ldr r3, [r7, #4]
80055a8: 2201 movs r2, #1
80055aa: f883 2040 strb.w r2, [r3, #64] ; 0x40
hi2c->State = HAL_I2C_STATE_BUSY;
80055ae: 687b ldr r3, [r7, #4]
80055b0: 2224 movs r2, #36 ; 0x24
80055b2: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
80055b6: 687b ldr r3, [r7, #4]
80055b8: 681b ldr r3, [r3, #0]
80055ba: 681a ldr r2, [r3, #0]
80055bc: 687b ldr r3, [r7, #4]
80055be: 681b ldr r3, [r3, #0]
80055c0: f022 0201 bic.w r2, r2, #1
80055c4: 601a str r2, [r3, #0]
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
80055c6: 687b ldr r3, [r7, #4]
80055c8: 681b ldr r3, [r3, #0]
80055ca: 681b ldr r3, [r3, #0]
80055cc: 60fb str r3, [r7, #12]
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
80055ce: 68fb ldr r3, [r7, #12]
80055d0: f423 6370 bic.w r3, r3, #3840 ; 0xf00
80055d4: 60fb str r3, [r7, #12]
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
80055d6: 683b ldr r3, [r7, #0]
80055d8: 021b lsls r3, r3, #8
80055da: 68fa ldr r2, [r7, #12]
80055dc: 4313 orrs r3, r2
80055de: 60fb str r3, [r7, #12]
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
80055e0: 687b ldr r3, [r7, #4]
80055e2: 681b ldr r3, [r3, #0]
80055e4: 68fa ldr r2, [r7, #12]
80055e6: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
80055e8: 687b ldr r3, [r7, #4]
80055ea: 681b ldr r3, [r3, #0]
80055ec: 681a ldr r2, [r3, #0]
80055ee: 687b ldr r3, [r7, #4]
80055f0: 681b ldr r3, [r3, #0]
80055f2: f042 0201 orr.w r2, r2, #1
80055f6: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
80055f8: 687b ldr r3, [r7, #4]
80055fa: 2220 movs r2, #32
80055fc: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8005600: 687b ldr r3, [r7, #4]
8005602: 2200 movs r2, #0
8005604: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_OK;
8005608: 2300 movs r3, #0
800560a: e000 b.n 800560e <HAL_I2CEx_ConfigDigitalFilter+0x8c>
}
else
{
return HAL_BUSY;
800560c: 2302 movs r3, #2
}
}
800560e: 4618 mov r0, r3
8005610: 3714 adds r7, #20
8005612: 46bd mov sp, r7
8005614: f85d 7b04 ldr.w r7, [sp], #4
8005618: 4770 bx lr
...
0800561c <HAL_PWREx_ControlVoltageScaling>:
* cleared before returning the status. If the flag is not cleared within
* 50 microseconds, HAL_TIMEOUT status is reported.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
800561c: b480 push {r7}
800561e: b085 sub sp, #20
8005620: af00 add r7, sp, #0
8005622: 6078 str r0, [r7, #4]
uint32_t wait_loop_index;
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)
8005624: 687b ldr r3, [r7, #4]
8005626: 2b00 cmp r3, #0
8005628: d141 bne.n 80056ae <HAL_PWREx_ControlVoltageScaling+0x92>
{
/* If current range is range 2 */
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
800562a: 4b4b ldr r3, [pc, #300] ; (8005758 <HAL_PWREx_ControlVoltageScaling+0x13c>)
800562c: 681b ldr r3, [r3, #0]
800562e: f403 63c0 and.w r3, r3, #1536 ; 0x600
8005632: f5b3 6f80 cmp.w r3, #1024 ; 0x400
8005636: d131 bne.n 800569c <HAL_PWREx_ControlVoltageScaling+0x80>
{
/* Make sure Range 1 Boost is enabled */
CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
8005638: 4b47 ldr r3, [pc, #284] ; (8005758 <HAL_PWREx_ControlVoltageScaling+0x13c>)
800563a: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
800563e: 4a46 ldr r2, [pc, #280] ; (8005758 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8005640: f423 7380 bic.w r3, r3, #256 ; 0x100
8005644: f8c2 3080 str.w r3, [r2, #128] ; 0x80
/* Set Range 1 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
8005648: 4b43 ldr r3, [pc, #268] ; (8005758 <HAL_PWREx_ControlVoltageScaling+0x13c>)
800564a: 681b ldr r3, [r3, #0]
800564c: f423 63c0 bic.w r3, r3, #1536 ; 0x600
8005650: 4a41 ldr r2, [pc, #260] ; (8005758 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8005652: f443 7300 orr.w r3, r3, #512 ; 0x200
8005656: 6013 str r3, [r2, #0]
/* Wait until VOSF is cleared */
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
8005658: 4b40 ldr r3, [pc, #256] ; (800575c <HAL_PWREx_ControlVoltageScaling+0x140>)
800565a: 681b ldr r3, [r3, #0]
800565c: 2232 movs r2, #50 ; 0x32
800565e: fb02 f303 mul.w r3, r2, r3
8005662: 4a3f ldr r2, [pc, #252] ; (8005760 <HAL_PWREx_ControlVoltageScaling+0x144>)
8005664: fba2 2303 umull r2, r3, r2, r3
8005668: 0c9b lsrs r3, r3, #18
800566a: 3301 adds r3, #1
800566c: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
800566e: e002 b.n 8005676 <HAL_PWREx_ControlVoltageScaling+0x5a>
{
wait_loop_index--;
8005670: 68fb ldr r3, [r7, #12]
8005672: 3b01 subs r3, #1
8005674: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
8005676: 4b38 ldr r3, [pc, #224] ; (8005758 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8005678: 695b ldr r3, [r3, #20]
800567a: f403 6380 and.w r3, r3, #1024 ; 0x400
800567e: f5b3 6f80 cmp.w r3, #1024 ; 0x400
8005682: d102 bne.n 800568a <HAL_PWREx_ControlVoltageScaling+0x6e>
8005684: 68fb ldr r3, [r7, #12]
8005686: 2b00 cmp r3, #0
8005688: d1f2 bne.n 8005670 <HAL_PWREx_ControlVoltageScaling+0x54>
}
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
800568a: 4b33 ldr r3, [pc, #204] ; (8005758 <HAL_PWREx_ControlVoltageScaling+0x13c>)
800568c: 695b ldr r3, [r3, #20]
800568e: f403 6380 and.w r3, r3, #1024 ; 0x400
8005692: f5b3 6f80 cmp.w r3, #1024 ; 0x400
8005696: d158 bne.n 800574a <HAL_PWREx_ControlVoltageScaling+0x12e>
{
return HAL_TIMEOUT;
8005698: 2303 movs r3, #3
800569a: e057 b.n 800574c <HAL_PWREx_ControlVoltageScaling+0x130>
}
/* If current range is range 1 normal or boost mode */
else
{
/* Enable Range 1 Boost (no issue if bit already reset) */
CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
800569c: 4b2e ldr r3, [pc, #184] ; (8005758 <HAL_PWREx_ControlVoltageScaling+0x13c>)
800569e: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
80056a2: 4a2d ldr r2, [pc, #180] ; (8005758 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80056a4: f423 7380 bic.w r3, r3, #256 ; 0x100
80056a8: f8c2 3080 str.w r3, [r2, #128] ; 0x80
80056ac: e04d b.n 800574a <HAL_PWREx_ControlVoltageScaling+0x12e>
}
}
else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
80056ae: 687b ldr r3, [r7, #4]
80056b0: f5b3 7f00 cmp.w r3, #512 ; 0x200
80056b4: d141 bne.n 800573a <HAL_PWREx_ControlVoltageScaling+0x11e>
{
/* If current range is range 2 */
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
80056b6: 4b28 ldr r3, [pc, #160] ; (8005758 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80056b8: 681b ldr r3, [r3, #0]
80056ba: f403 63c0 and.w r3, r3, #1536 ; 0x600
80056be: f5b3 6f80 cmp.w r3, #1024 ; 0x400
80056c2: d131 bne.n 8005728 <HAL_PWREx_ControlVoltageScaling+0x10c>
{
/* Make sure Range 1 Boost is disabled */
SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
80056c4: 4b24 ldr r3, [pc, #144] ; (8005758 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80056c6: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
80056ca: 4a23 ldr r2, [pc, #140] ; (8005758 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80056cc: f443 7380 orr.w r3, r3, #256 ; 0x100
80056d0: f8c2 3080 str.w r3, [r2, #128] ; 0x80
/* Set Range 1 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
80056d4: 4b20 ldr r3, [pc, #128] ; (8005758 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80056d6: 681b ldr r3, [r3, #0]
80056d8: f423 63c0 bic.w r3, r3, #1536 ; 0x600
80056dc: 4a1e ldr r2, [pc, #120] ; (8005758 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80056de: f443 7300 orr.w r3, r3, #512 ; 0x200
80056e2: 6013 str r3, [r2, #0]
/* Wait until VOSF is cleared */
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
80056e4: 4b1d ldr r3, [pc, #116] ; (800575c <HAL_PWREx_ControlVoltageScaling+0x140>)
80056e6: 681b ldr r3, [r3, #0]
80056e8: 2232 movs r2, #50 ; 0x32
80056ea: fb02 f303 mul.w r3, r2, r3
80056ee: 4a1c ldr r2, [pc, #112] ; (8005760 <HAL_PWREx_ControlVoltageScaling+0x144>)
80056f0: fba2 2303 umull r2, r3, r2, r3
80056f4: 0c9b lsrs r3, r3, #18
80056f6: 3301 adds r3, #1
80056f8: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
80056fa: e002 b.n 8005702 <HAL_PWREx_ControlVoltageScaling+0xe6>
{
wait_loop_index--;
80056fc: 68fb ldr r3, [r7, #12]
80056fe: 3b01 subs r3, #1
8005700: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
8005702: 4b15 ldr r3, [pc, #84] ; (8005758 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8005704: 695b ldr r3, [r3, #20]
8005706: f403 6380 and.w r3, r3, #1024 ; 0x400
800570a: f5b3 6f80 cmp.w r3, #1024 ; 0x400
800570e: d102 bne.n 8005716 <HAL_PWREx_ControlVoltageScaling+0xfa>
8005710: 68fb ldr r3, [r7, #12]
8005712: 2b00 cmp r3, #0
8005714: d1f2 bne.n 80056fc <HAL_PWREx_ControlVoltageScaling+0xe0>
}
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
8005716: 4b10 ldr r3, [pc, #64] ; (8005758 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8005718: 695b ldr r3, [r3, #20]
800571a: f403 6380 and.w r3, r3, #1024 ; 0x400
800571e: f5b3 6f80 cmp.w r3, #1024 ; 0x400
8005722: d112 bne.n 800574a <HAL_PWREx_ControlVoltageScaling+0x12e>
{
return HAL_TIMEOUT;
8005724: 2303 movs r3, #3
8005726: e011 b.n 800574c <HAL_PWREx_ControlVoltageScaling+0x130>
}
/* If current range is range 1 normal or boost mode */
else
{
/* Disable Range 1 Boost (no issue if bit already set) */
SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
8005728: 4b0b ldr r3, [pc, #44] ; (8005758 <HAL_PWREx_ControlVoltageScaling+0x13c>)
800572a: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
800572e: 4a0a ldr r2, [pc, #40] ; (8005758 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8005730: f443 7380 orr.w r3, r3, #256 ; 0x100
8005734: f8c2 3080 str.w r3, [r2, #128] ; 0x80
8005738: e007 b.n 800574a <HAL_PWREx_ControlVoltageScaling+0x12e>
}
}
else
{
/* Set Range 2 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
800573a: 4b07 ldr r3, [pc, #28] ; (8005758 <HAL_PWREx_ControlVoltageScaling+0x13c>)
800573c: 681b ldr r3, [r3, #0]
800573e: f423 63c0 bic.w r3, r3, #1536 ; 0x600
8005742: 4a05 ldr r2, [pc, #20] ; (8005758 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8005744: f443 6380 orr.w r3, r3, #1024 ; 0x400
8005748: 6013 str r3, [r2, #0]
/* No need to wait for VOSF to be cleared for this transition */
/* PWR_CR5_R1MODE bit setting has no effect in Range 2 */
}
return HAL_OK;
800574a: 2300 movs r3, #0
}
800574c: 4618 mov r0, r3
800574e: 3714 adds r7, #20
8005750: 46bd mov sp, r7
8005752: f85d 7b04 ldr.w r7, [sp], #4
8005756: 4770 bx lr
8005758: 40007000 .word 0x40007000
800575c: 20000004 .word 0x20000004
8005760: 431bde83 .word 0x431bde83
08005764 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8005764: b580 push {r7, lr}
8005766: b088 sub sp, #32
8005768: af00 add r7, sp, #0
800576a: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t temp_sysclksrc;
uint32_t temp_pllckcfg;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
800576c: 687b ldr r3, [r7, #4]
800576e: 2b00 cmp r3, #0
8005770: d101 bne.n 8005776 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8005772: 2301 movs r3, #1
8005774: e306 b.n 8005d84 <HAL_RCC_OscConfig+0x620>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8005776: 687b ldr r3, [r7, #4]
8005778: 681b ldr r3, [r3, #0]
800577a: f003 0301 and.w r3, r3, #1
800577e: 2b00 cmp r3, #0
8005780: d075 beq.n 800586e <HAL_RCC_OscConfig+0x10a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
8005782: 4b97 ldr r3, [pc, #604] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
8005784: 689b ldr r3, [r3, #8]
8005786: f003 030c and.w r3, r3, #12
800578a: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
800578c: 4b94 ldr r3, [pc, #592] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
800578e: 68db ldr r3, [r3, #12]
8005790: f003 0303 and.w r3, r3, #3
8005794: 617b str r3, [r7, #20]
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE))
8005796: 69bb ldr r3, [r7, #24]
8005798: 2b0c cmp r3, #12
800579a: d102 bne.n 80057a2 <HAL_RCC_OscConfig+0x3e>
800579c: 697b ldr r3, [r7, #20]
800579e: 2b03 cmp r3, #3
80057a0: d002 beq.n 80057a8 <HAL_RCC_OscConfig+0x44>
80057a2: 69bb ldr r3, [r7, #24]
80057a4: 2b08 cmp r3, #8
80057a6: d10b bne.n 80057c0 <HAL_RCC_OscConfig+0x5c>
{
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80057a8: 4b8d ldr r3, [pc, #564] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
80057aa: 681b ldr r3, [r3, #0]
80057ac: f403 3300 and.w r3, r3, #131072 ; 0x20000
80057b0: 2b00 cmp r3, #0
80057b2: d05b beq.n 800586c <HAL_RCC_OscConfig+0x108>
80057b4: 687b ldr r3, [r7, #4]
80057b6: 685b ldr r3, [r3, #4]
80057b8: 2b00 cmp r3, #0
80057ba: d157 bne.n 800586c <HAL_RCC_OscConfig+0x108>
{
return HAL_ERROR;
80057bc: 2301 movs r3, #1
80057be: e2e1 b.n 8005d84 <HAL_RCC_OscConfig+0x620>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80057c0: 687b ldr r3, [r7, #4]
80057c2: 685b ldr r3, [r3, #4]
80057c4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80057c8: d106 bne.n 80057d8 <HAL_RCC_OscConfig+0x74>
80057ca: 4b85 ldr r3, [pc, #532] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
80057cc: 681b ldr r3, [r3, #0]
80057ce: 4a84 ldr r2, [pc, #528] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
80057d0: f443 3380 orr.w r3, r3, #65536 ; 0x10000
80057d4: 6013 str r3, [r2, #0]
80057d6: e01d b.n 8005814 <HAL_RCC_OscConfig+0xb0>
80057d8: 687b ldr r3, [r7, #4]
80057da: 685b ldr r3, [r3, #4]
80057dc: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
80057e0: d10c bne.n 80057fc <HAL_RCC_OscConfig+0x98>
80057e2: 4b7f ldr r3, [pc, #508] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
80057e4: 681b ldr r3, [r3, #0]
80057e6: 4a7e ldr r2, [pc, #504] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
80057e8: f443 2380 orr.w r3, r3, #262144 ; 0x40000
80057ec: 6013 str r3, [r2, #0]
80057ee: 4b7c ldr r3, [pc, #496] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
80057f0: 681b ldr r3, [r3, #0]
80057f2: 4a7b ldr r2, [pc, #492] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
80057f4: f443 3380 orr.w r3, r3, #65536 ; 0x10000
80057f8: 6013 str r3, [r2, #0]
80057fa: e00b b.n 8005814 <HAL_RCC_OscConfig+0xb0>
80057fc: 4b78 ldr r3, [pc, #480] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
80057fe: 681b ldr r3, [r3, #0]
8005800: 4a77 ldr r2, [pc, #476] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
8005802: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8005806: 6013 str r3, [r2, #0]
8005808: 4b75 ldr r3, [pc, #468] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
800580a: 681b ldr r3, [r3, #0]
800580c: 4a74 ldr r2, [pc, #464] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
800580e: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8005812: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8005814: 687b ldr r3, [r7, #4]
8005816: 685b ldr r3, [r3, #4]
8005818: 2b00 cmp r3, #0
800581a: d013 beq.n 8005844 <HAL_RCC_OscConfig+0xe0>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800581c: f7fc fa9a bl 8001d54 <HAL_GetTick>
8005820: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8005822: e008 b.n 8005836 <HAL_RCC_OscConfig+0xd2>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8005824: f7fc fa96 bl 8001d54 <HAL_GetTick>
8005828: 4602 mov r2, r0
800582a: 693b ldr r3, [r7, #16]
800582c: 1ad3 subs r3, r2, r3
800582e: 2b64 cmp r3, #100 ; 0x64
8005830: d901 bls.n 8005836 <HAL_RCC_OscConfig+0xd2>
{
return HAL_TIMEOUT;
8005832: 2303 movs r3, #3
8005834: e2a6 b.n 8005d84 <HAL_RCC_OscConfig+0x620>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8005836: 4b6a ldr r3, [pc, #424] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
8005838: 681b ldr r3, [r3, #0]
800583a: f403 3300 and.w r3, r3, #131072 ; 0x20000
800583e: 2b00 cmp r3, #0
8005840: d0f0 beq.n 8005824 <HAL_RCC_OscConfig+0xc0>
8005842: e014 b.n 800586e <HAL_RCC_OscConfig+0x10a>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8005844: f7fc fa86 bl 8001d54 <HAL_GetTick>
8005848: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
800584a: e008 b.n 800585e <HAL_RCC_OscConfig+0xfa>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
800584c: f7fc fa82 bl 8001d54 <HAL_GetTick>
8005850: 4602 mov r2, r0
8005852: 693b ldr r3, [r7, #16]
8005854: 1ad3 subs r3, r2, r3
8005856: 2b64 cmp r3, #100 ; 0x64
8005858: d901 bls.n 800585e <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
800585a: 2303 movs r3, #3
800585c: e292 b.n 8005d84 <HAL_RCC_OscConfig+0x620>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
800585e: 4b60 ldr r3, [pc, #384] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
8005860: 681b ldr r3, [r3, #0]
8005862: f403 3300 and.w r3, r3, #131072 ; 0x20000
8005866: 2b00 cmp r3, #0
8005868: d1f0 bne.n 800584c <HAL_RCC_OscConfig+0xe8>
800586a: e000 b.n 800586e <HAL_RCC_OscConfig+0x10a>
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
800586c: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
800586e: 687b ldr r3, [r7, #4]
8005870: 681b ldr r3, [r3, #0]
8005872: f003 0302 and.w r3, r3, #2
8005876: 2b00 cmp r3, #0
8005878: d075 beq.n 8005966 <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
800587a: 4b59 ldr r3, [pc, #356] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
800587c: 689b ldr r3, [r3, #8]
800587e: f003 030c and.w r3, r3, #12
8005882: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
8005884: 4b56 ldr r3, [pc, #344] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
8005886: 68db ldr r3, [r3, #12]
8005888: f003 0303 and.w r3, r3, #3
800588c: 617b str r3, [r7, #20]
if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI))
800588e: 69bb ldr r3, [r7, #24]
8005890: 2b0c cmp r3, #12
8005892: d102 bne.n 800589a <HAL_RCC_OscConfig+0x136>
8005894: 697b ldr r3, [r7, #20]
8005896: 2b02 cmp r3, #2
8005898: d002 beq.n 80058a0 <HAL_RCC_OscConfig+0x13c>
800589a: 69bb ldr r3, [r7, #24]
800589c: 2b04 cmp r3, #4
800589e: d11f bne.n 80058e0 <HAL_RCC_OscConfig+0x17c>
{
/* When HSI is used as system clock it will not be disabled */
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
80058a0: 4b4f ldr r3, [pc, #316] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
80058a2: 681b ldr r3, [r3, #0]
80058a4: f403 6380 and.w r3, r3, #1024 ; 0x400
80058a8: 2b00 cmp r3, #0
80058aa: d005 beq.n 80058b8 <HAL_RCC_OscConfig+0x154>
80058ac: 687b ldr r3, [r7, #4]
80058ae: 68db ldr r3, [r3, #12]
80058b0: 2b00 cmp r3, #0
80058b2: d101 bne.n 80058b8 <HAL_RCC_OscConfig+0x154>
{
return HAL_ERROR;
80058b4: 2301 movs r3, #1
80058b6: e265 b.n 8005d84 <HAL_RCC_OscConfig+0x620>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80058b8: 4b49 ldr r3, [pc, #292] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
80058ba: 685b ldr r3, [r3, #4]
80058bc: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000
80058c0: 687b ldr r3, [r7, #4]
80058c2: 691b ldr r3, [r3, #16]
80058c4: 061b lsls r3, r3, #24
80058c6: 4946 ldr r1, [pc, #280] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
80058c8: 4313 orrs r3, r2
80058ca: 604b str r3, [r1, #4]
/* Adapt Systick interrupt period */
if (HAL_InitTick(uwTickPrio) != HAL_OK)
80058cc: 4b45 ldr r3, [pc, #276] ; (80059e4 <HAL_RCC_OscConfig+0x280>)
80058ce: 681b ldr r3, [r3, #0]
80058d0: 4618 mov r0, r3
80058d2: f7fc f9f3 bl 8001cbc <HAL_InitTick>
80058d6: 4603 mov r3, r0
80058d8: 2b00 cmp r3, #0
80058da: d043 beq.n 8005964 <HAL_RCC_OscConfig+0x200>
{
return HAL_ERROR;
80058dc: 2301 movs r3, #1
80058de: e251 b.n 8005d84 <HAL_RCC_OscConfig+0x620>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
80058e0: 687b ldr r3, [r7, #4]
80058e2: 68db ldr r3, [r3, #12]
80058e4: 2b00 cmp r3, #0
80058e6: d023 beq.n 8005930 <HAL_RCC_OscConfig+0x1cc>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
80058e8: 4b3d ldr r3, [pc, #244] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
80058ea: 681b ldr r3, [r3, #0]
80058ec: 4a3c ldr r2, [pc, #240] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
80058ee: f443 7380 orr.w r3, r3, #256 ; 0x100
80058f2: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80058f4: f7fc fa2e bl 8001d54 <HAL_GetTick>
80058f8: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
80058fa: e008 b.n 800590e <HAL_RCC_OscConfig+0x1aa>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80058fc: f7fc fa2a bl 8001d54 <HAL_GetTick>
8005900: 4602 mov r2, r0
8005902: 693b ldr r3, [r7, #16]
8005904: 1ad3 subs r3, r2, r3
8005906: 2b02 cmp r3, #2
8005908: d901 bls.n 800590e <HAL_RCC_OscConfig+0x1aa>
{
return HAL_TIMEOUT;
800590a: 2303 movs r3, #3
800590c: e23a b.n 8005d84 <HAL_RCC_OscConfig+0x620>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
800590e: 4b34 ldr r3, [pc, #208] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
8005910: 681b ldr r3, [r3, #0]
8005912: f403 6380 and.w r3, r3, #1024 ; 0x400
8005916: 2b00 cmp r3, #0
8005918: d0f0 beq.n 80058fc <HAL_RCC_OscConfig+0x198>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800591a: 4b31 ldr r3, [pc, #196] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
800591c: 685b ldr r3, [r3, #4]
800591e: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000
8005922: 687b ldr r3, [r7, #4]
8005924: 691b ldr r3, [r3, #16]
8005926: 061b lsls r3, r3, #24
8005928: 492d ldr r1, [pc, #180] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
800592a: 4313 orrs r3, r2
800592c: 604b str r3, [r1, #4]
800592e: e01a b.n 8005966 <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8005930: 4b2b ldr r3, [pc, #172] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
8005932: 681b ldr r3, [r3, #0]
8005934: 4a2a ldr r2, [pc, #168] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
8005936: f423 7380 bic.w r3, r3, #256 ; 0x100
800593a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800593c: f7fc fa0a bl 8001d54 <HAL_GetTick>
8005940: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8005942: e008 b.n 8005956 <HAL_RCC_OscConfig+0x1f2>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8005944: f7fc fa06 bl 8001d54 <HAL_GetTick>
8005948: 4602 mov r2, r0
800594a: 693b ldr r3, [r7, #16]
800594c: 1ad3 subs r3, r2, r3
800594e: 2b02 cmp r3, #2
8005950: d901 bls.n 8005956 <HAL_RCC_OscConfig+0x1f2>
{
return HAL_TIMEOUT;
8005952: 2303 movs r3, #3
8005954: e216 b.n 8005d84 <HAL_RCC_OscConfig+0x620>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8005956: 4b22 ldr r3, [pc, #136] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
8005958: 681b ldr r3, [r3, #0]
800595a: f403 6380 and.w r3, r3, #1024 ; 0x400
800595e: 2b00 cmp r3, #0
8005960: d1f0 bne.n 8005944 <HAL_RCC_OscConfig+0x1e0>
8005962: e000 b.n 8005966 <HAL_RCC_OscConfig+0x202>
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8005964: bf00 nop
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8005966: 687b ldr r3, [r7, #4]
8005968: 681b ldr r3, [r3, #0]
800596a: f003 0308 and.w r3, r3, #8
800596e: 2b00 cmp r3, #0
8005970: d041 beq.n 80059f6 <HAL_RCC_OscConfig+0x292>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8005972: 687b ldr r3, [r7, #4]
8005974: 695b ldr r3, [r3, #20]
8005976: 2b00 cmp r3, #0
8005978: d01c beq.n 80059b4 <HAL_RCC_OscConfig+0x250>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
800597a: 4b19 ldr r3, [pc, #100] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
800597c: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
8005980: 4a17 ldr r2, [pc, #92] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
8005982: f043 0301 orr.w r3, r3, #1
8005986: f8c2 3094 str.w r3, [r2, #148] ; 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
800598a: f7fc f9e3 bl 8001d54 <HAL_GetTick>
800598e: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8005990: e008 b.n 80059a4 <HAL_RCC_OscConfig+0x240>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8005992: f7fc f9df bl 8001d54 <HAL_GetTick>
8005996: 4602 mov r2, r0
8005998: 693b ldr r3, [r7, #16]
800599a: 1ad3 subs r3, r2, r3
800599c: 2b02 cmp r3, #2
800599e: d901 bls.n 80059a4 <HAL_RCC_OscConfig+0x240>
{
return HAL_TIMEOUT;
80059a0: 2303 movs r3, #3
80059a2: e1ef b.n 8005d84 <HAL_RCC_OscConfig+0x620>
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
80059a4: 4b0e ldr r3, [pc, #56] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
80059a6: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
80059aa: f003 0302 and.w r3, r3, #2
80059ae: 2b00 cmp r3, #0
80059b0: d0ef beq.n 8005992 <HAL_RCC_OscConfig+0x22e>
80059b2: e020 b.n 80059f6 <HAL_RCC_OscConfig+0x292>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80059b4: 4b0a ldr r3, [pc, #40] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
80059b6: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
80059ba: 4a09 ldr r2, [pc, #36] ; (80059e0 <HAL_RCC_OscConfig+0x27c>)
80059bc: f023 0301 bic.w r3, r3, #1
80059c0: f8c2 3094 str.w r3, [r2, #148] ; 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
80059c4: f7fc f9c6 bl 8001d54 <HAL_GetTick>
80059c8: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
80059ca: e00d b.n 80059e8 <HAL_RCC_OscConfig+0x284>
{
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80059cc: f7fc f9c2 bl 8001d54 <HAL_GetTick>
80059d0: 4602 mov r2, r0
80059d2: 693b ldr r3, [r7, #16]
80059d4: 1ad3 subs r3, r2, r3
80059d6: 2b02 cmp r3, #2
80059d8: d906 bls.n 80059e8 <HAL_RCC_OscConfig+0x284>
{
return HAL_TIMEOUT;
80059da: 2303 movs r3, #3
80059dc: e1d2 b.n 8005d84 <HAL_RCC_OscConfig+0x620>
80059de: bf00 nop
80059e0: 40021000 .word 0x40021000
80059e4: 20000008 .word 0x20000008
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
80059e8: 4b8c ldr r3, [pc, #560] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
80059ea: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
80059ee: f003 0302 and.w r3, r3, #2
80059f2: 2b00 cmp r3, #0
80059f4: d1ea bne.n 80059cc <HAL_RCC_OscConfig+0x268>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
80059f6: 687b ldr r3, [r7, #4]
80059f8: 681b ldr r3, [r3, #0]
80059fa: f003 0304 and.w r3, r3, #4
80059fe: 2b00 cmp r3, #0
8005a00: f000 80a6 beq.w 8005b50 <HAL_RCC_OscConfig+0x3ec>
{
FlagStatus pwrclkchanged = RESET;
8005a04: 2300 movs r3, #0
8005a06: 77fb strb r3, [r7, #31]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain if necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
8005a08: 4b84 ldr r3, [pc, #528] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005a0a: 6d9b ldr r3, [r3, #88] ; 0x58
8005a0c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8005a10: 2b00 cmp r3, #0
8005a12: d101 bne.n 8005a18 <HAL_RCC_OscConfig+0x2b4>
8005a14: 2301 movs r3, #1
8005a16: e000 b.n 8005a1a <HAL_RCC_OscConfig+0x2b6>
8005a18: 2300 movs r3, #0
8005a1a: 2b00 cmp r3, #0
8005a1c: d00d beq.n 8005a3a <HAL_RCC_OscConfig+0x2d6>
{
__HAL_RCC_PWR_CLK_ENABLE();
8005a1e: 4b7f ldr r3, [pc, #508] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005a20: 6d9b ldr r3, [r3, #88] ; 0x58
8005a22: 4a7e ldr r2, [pc, #504] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005a24: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8005a28: 6593 str r3, [r2, #88] ; 0x58
8005a2a: 4b7c ldr r3, [pc, #496] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005a2c: 6d9b ldr r3, [r3, #88] ; 0x58
8005a2e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8005a32: 60fb str r3, [r7, #12]
8005a34: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
8005a36: 2301 movs r3, #1
8005a38: 77fb strb r3, [r7, #31]
}
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8005a3a: 4b79 ldr r3, [pc, #484] ; (8005c20 <HAL_RCC_OscConfig+0x4bc>)
8005a3c: 681b ldr r3, [r3, #0]
8005a3e: f403 7380 and.w r3, r3, #256 ; 0x100
8005a42: 2b00 cmp r3, #0
8005a44: d118 bne.n 8005a78 <HAL_RCC_OscConfig+0x314>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8005a46: 4b76 ldr r3, [pc, #472] ; (8005c20 <HAL_RCC_OscConfig+0x4bc>)
8005a48: 681b ldr r3, [r3, #0]
8005a4a: 4a75 ldr r2, [pc, #468] ; (8005c20 <HAL_RCC_OscConfig+0x4bc>)
8005a4c: f443 7380 orr.w r3, r3, #256 ; 0x100
8005a50: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8005a52: f7fc f97f bl 8001d54 <HAL_GetTick>
8005a56: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8005a58: e008 b.n 8005a6c <HAL_RCC_OscConfig+0x308>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8005a5a: f7fc f97b bl 8001d54 <HAL_GetTick>
8005a5e: 4602 mov r2, r0
8005a60: 693b ldr r3, [r7, #16]
8005a62: 1ad3 subs r3, r2, r3
8005a64: 2b02 cmp r3, #2
8005a66: d901 bls.n 8005a6c <HAL_RCC_OscConfig+0x308>
{
return HAL_TIMEOUT;
8005a68: 2303 movs r3, #3
8005a6a: e18b b.n 8005d84 <HAL_RCC_OscConfig+0x620>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8005a6c: 4b6c ldr r3, [pc, #432] ; (8005c20 <HAL_RCC_OscConfig+0x4bc>)
8005a6e: 681b ldr r3, [r3, #0]
8005a70: f403 7380 and.w r3, r3, #256 ; 0x100
8005a74: 2b00 cmp r3, #0
8005a76: d0f0 beq.n 8005a5a <HAL_RCC_OscConfig+0x2f6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8005a78: 687b ldr r3, [r7, #4]
8005a7a: 689b ldr r3, [r3, #8]
8005a7c: 2b01 cmp r3, #1
8005a7e: d108 bne.n 8005a92 <HAL_RCC_OscConfig+0x32e>
8005a80: 4b66 ldr r3, [pc, #408] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005a82: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8005a86: 4a65 ldr r2, [pc, #404] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005a88: f043 0301 orr.w r3, r3, #1
8005a8c: f8c2 3090 str.w r3, [r2, #144] ; 0x90
8005a90: e024 b.n 8005adc <HAL_RCC_OscConfig+0x378>
8005a92: 687b ldr r3, [r7, #4]
8005a94: 689b ldr r3, [r3, #8]
8005a96: 2b05 cmp r3, #5
8005a98: d110 bne.n 8005abc <HAL_RCC_OscConfig+0x358>
8005a9a: 4b60 ldr r3, [pc, #384] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005a9c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8005aa0: 4a5e ldr r2, [pc, #376] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005aa2: f043 0304 orr.w r3, r3, #4
8005aa6: f8c2 3090 str.w r3, [r2, #144] ; 0x90
8005aaa: 4b5c ldr r3, [pc, #368] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005aac: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8005ab0: 4a5a ldr r2, [pc, #360] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005ab2: f043 0301 orr.w r3, r3, #1
8005ab6: f8c2 3090 str.w r3, [r2, #144] ; 0x90
8005aba: e00f b.n 8005adc <HAL_RCC_OscConfig+0x378>
8005abc: 4b57 ldr r3, [pc, #348] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005abe: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8005ac2: 4a56 ldr r2, [pc, #344] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005ac4: f023 0301 bic.w r3, r3, #1
8005ac8: f8c2 3090 str.w r3, [r2, #144] ; 0x90
8005acc: 4b53 ldr r3, [pc, #332] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005ace: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8005ad2: 4a52 ldr r2, [pc, #328] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005ad4: f023 0304 bic.w r3, r3, #4
8005ad8: f8c2 3090 str.w r3, [r2, #144] ; 0x90
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8005adc: 687b ldr r3, [r7, #4]
8005ade: 689b ldr r3, [r3, #8]
8005ae0: 2b00 cmp r3, #0
8005ae2: d016 beq.n 8005b12 <HAL_RCC_OscConfig+0x3ae>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8005ae4: f7fc f936 bl 8001d54 <HAL_GetTick>
8005ae8: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8005aea: e00a b.n 8005b02 <HAL_RCC_OscConfig+0x39e>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8005aec: f7fc f932 bl 8001d54 <HAL_GetTick>
8005af0: 4602 mov r2, r0
8005af2: 693b ldr r3, [r7, #16]
8005af4: 1ad3 subs r3, r2, r3
8005af6: f241 3288 movw r2, #5000 ; 0x1388
8005afa: 4293 cmp r3, r2
8005afc: d901 bls.n 8005b02 <HAL_RCC_OscConfig+0x39e>
{
return HAL_TIMEOUT;
8005afe: 2303 movs r3, #3
8005b00: e140 b.n 8005d84 <HAL_RCC_OscConfig+0x620>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8005b02: 4b46 ldr r3, [pc, #280] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005b04: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8005b08: f003 0302 and.w r3, r3, #2
8005b0c: 2b00 cmp r3, #0
8005b0e: d0ed beq.n 8005aec <HAL_RCC_OscConfig+0x388>
8005b10: e015 b.n 8005b3e <HAL_RCC_OscConfig+0x3da>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8005b12: f7fc f91f bl 8001d54 <HAL_GetTick>
8005b16: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8005b18: e00a b.n 8005b30 <HAL_RCC_OscConfig+0x3cc>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8005b1a: f7fc f91b bl 8001d54 <HAL_GetTick>
8005b1e: 4602 mov r2, r0
8005b20: 693b ldr r3, [r7, #16]
8005b22: 1ad3 subs r3, r2, r3
8005b24: f241 3288 movw r2, #5000 ; 0x1388
8005b28: 4293 cmp r3, r2
8005b2a: d901 bls.n 8005b30 <HAL_RCC_OscConfig+0x3cc>
{
return HAL_TIMEOUT;
8005b2c: 2303 movs r3, #3
8005b2e: e129 b.n 8005d84 <HAL_RCC_OscConfig+0x620>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8005b30: 4b3a ldr r3, [pc, #232] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005b32: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8005b36: f003 0302 and.w r3, r3, #2
8005b3a: 2b00 cmp r3, #0
8005b3c: d1ed bne.n 8005b1a <HAL_RCC_OscConfig+0x3b6>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
8005b3e: 7ffb ldrb r3, [r7, #31]
8005b40: 2b01 cmp r3, #1
8005b42: d105 bne.n 8005b50 <HAL_RCC_OscConfig+0x3ec>
{
__HAL_RCC_PWR_CLK_DISABLE();
8005b44: 4b35 ldr r3, [pc, #212] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005b46: 6d9b ldr r3, [r3, #88] ; 0x58
8005b48: 4a34 ldr r2, [pc, #208] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005b4a: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8005b4e: 6593 str r3, [r2, #88] ; 0x58
}
}
/*------------------------------ HSI48 Configuration -----------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
8005b50: 687b ldr r3, [r7, #4]
8005b52: 681b ldr r3, [r3, #0]
8005b54: f003 0320 and.w r3, r3, #32
8005b58: 2b00 cmp r3, #0
8005b5a: d03c beq.n 8005bd6 <HAL_RCC_OscConfig+0x472>
{
/* Check the parameters */
assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
/* Check the HSI48 State */
if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
8005b5c: 687b ldr r3, [r7, #4]
8005b5e: 699b ldr r3, [r3, #24]
8005b60: 2b00 cmp r3, #0
8005b62: d01c beq.n 8005b9e <HAL_RCC_OscConfig+0x43a>
{
/* Enable the Internal Low Speed oscillator (HSI48). */
__HAL_RCC_HSI48_ENABLE();
8005b64: 4b2d ldr r3, [pc, #180] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005b66: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98
8005b6a: 4a2c ldr r2, [pc, #176] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005b6c: f043 0301 orr.w r3, r3, #1
8005b70: f8c2 3098 str.w r3, [r2, #152] ; 0x98
/* Get Start Tick*/
tickstart = HAL_GetTick();
8005b74: f7fc f8ee bl 8001d54 <HAL_GetTick>
8005b78: 6138 str r0, [r7, #16]
/* Wait till HSI48 is ready */
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
8005b7a: e008 b.n 8005b8e <HAL_RCC_OscConfig+0x42a>
{
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
8005b7c: f7fc f8ea bl 8001d54 <HAL_GetTick>
8005b80: 4602 mov r2, r0
8005b82: 693b ldr r3, [r7, #16]
8005b84: 1ad3 subs r3, r2, r3
8005b86: 2b02 cmp r3, #2
8005b88: d901 bls.n 8005b8e <HAL_RCC_OscConfig+0x42a>
{
return HAL_TIMEOUT;
8005b8a: 2303 movs r3, #3
8005b8c: e0fa b.n 8005d84 <HAL_RCC_OscConfig+0x620>
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
8005b8e: 4b23 ldr r3, [pc, #140] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005b90: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98
8005b94: f003 0302 and.w r3, r3, #2
8005b98: 2b00 cmp r3, #0
8005b9a: d0ef beq.n 8005b7c <HAL_RCC_OscConfig+0x418>
8005b9c: e01b b.n 8005bd6 <HAL_RCC_OscConfig+0x472>
}
}
else
{
/* Disable the Internal Low Speed oscillator (HSI48). */
__HAL_RCC_HSI48_DISABLE();
8005b9e: 4b1f ldr r3, [pc, #124] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005ba0: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98
8005ba4: 4a1d ldr r2, [pc, #116] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005ba6: f023 0301 bic.w r3, r3, #1
8005baa: f8c2 3098 str.w r3, [r2, #152] ; 0x98
/* Get Start Tick*/
tickstart = HAL_GetTick();
8005bae: f7fc f8d1 bl 8001d54 <HAL_GetTick>
8005bb2: 6138 str r0, [r7, #16]
/* Wait till HSI48 is disabled */
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
8005bb4: e008 b.n 8005bc8 <HAL_RCC_OscConfig+0x464>
{
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
8005bb6: f7fc f8cd bl 8001d54 <HAL_GetTick>
8005bba: 4602 mov r2, r0
8005bbc: 693b ldr r3, [r7, #16]
8005bbe: 1ad3 subs r3, r2, r3
8005bc0: 2b02 cmp r3, #2
8005bc2: d901 bls.n 8005bc8 <HAL_RCC_OscConfig+0x464>
{
return HAL_TIMEOUT;
8005bc4: 2303 movs r3, #3
8005bc6: e0dd b.n 8005d84 <HAL_RCC_OscConfig+0x620>
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
8005bc8: 4b14 ldr r3, [pc, #80] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005bca: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98
8005bce: f003 0302 and.w r3, r3, #2
8005bd2: 2b00 cmp r3, #0
8005bd4: d1ef bne.n 8005bb6 <HAL_RCC_OscConfig+0x452>
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
8005bd6: 687b ldr r3, [r7, #4]
8005bd8: 69db ldr r3, [r3, #28]
8005bda: 2b00 cmp r3, #0
8005bdc: f000 80d1 beq.w 8005d82 <HAL_RCC_OscConfig+0x61e>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
8005be0: 4b0e ldr r3, [pc, #56] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005be2: 689b ldr r3, [r3, #8]
8005be4: f003 030c and.w r3, r3, #12
8005be8: 2b0c cmp r3, #12
8005bea: f000 808b beq.w 8005d04 <HAL_RCC_OscConfig+0x5a0>
{
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
8005bee: 687b ldr r3, [r7, #4]
8005bf0: 69db ldr r3, [r3, #28]
8005bf2: 2b02 cmp r3, #2
8005bf4: d15e bne.n 8005cb4 <HAL_RCC_OscConfig+0x550>
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8005bf6: 4b09 ldr r3, [pc, #36] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005bf8: 681b ldr r3, [r3, #0]
8005bfa: 4a08 ldr r2, [pc, #32] ; (8005c1c <HAL_RCC_OscConfig+0x4b8>)
8005bfc: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
8005c00: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8005c02: f7fc f8a7 bl 8001d54 <HAL_GetTick>
8005c06: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8005c08: e00c b.n 8005c24 <HAL_RCC_OscConfig+0x4c0>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8005c0a: f7fc f8a3 bl 8001d54 <HAL_GetTick>
8005c0e: 4602 mov r2, r0
8005c10: 693b ldr r3, [r7, #16]
8005c12: 1ad3 subs r3, r2, r3
8005c14: 2b02 cmp r3, #2
8005c16: d905 bls.n 8005c24 <HAL_RCC_OscConfig+0x4c0>
{
return HAL_TIMEOUT;
8005c18: 2303 movs r3, #3
8005c1a: e0b3 b.n 8005d84 <HAL_RCC_OscConfig+0x620>
8005c1c: 40021000 .word 0x40021000
8005c20: 40007000 .word 0x40007000
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8005c24: 4b59 ldr r3, [pc, #356] ; (8005d8c <HAL_RCC_OscConfig+0x628>)
8005c26: 681b ldr r3, [r3, #0]
8005c28: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8005c2c: 2b00 cmp r3, #0
8005c2e: d1ec bne.n 8005c0a <HAL_RCC_OscConfig+0x4a6>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8005c30: 4b56 ldr r3, [pc, #344] ; (8005d8c <HAL_RCC_OscConfig+0x628>)
8005c32: 68da ldr r2, [r3, #12]
8005c34: 4b56 ldr r3, [pc, #344] ; (8005d90 <HAL_RCC_OscConfig+0x62c>)
8005c36: 4013 ands r3, r2
8005c38: 687a ldr r2, [r7, #4]
8005c3a: 6a11 ldr r1, [r2, #32]
8005c3c: 687a ldr r2, [r7, #4]
8005c3e: 6a52 ldr r2, [r2, #36] ; 0x24
8005c40: 3a01 subs r2, #1
8005c42: 0112 lsls r2, r2, #4
8005c44: 4311 orrs r1, r2
8005c46: 687a ldr r2, [r7, #4]
8005c48: 6a92 ldr r2, [r2, #40] ; 0x28
8005c4a: 0212 lsls r2, r2, #8
8005c4c: 4311 orrs r1, r2
8005c4e: 687a ldr r2, [r7, #4]
8005c50: 6b12 ldr r2, [r2, #48] ; 0x30
8005c52: 0852 lsrs r2, r2, #1
8005c54: 3a01 subs r2, #1
8005c56: 0552 lsls r2, r2, #21
8005c58: 4311 orrs r1, r2
8005c5a: 687a ldr r2, [r7, #4]
8005c5c: 6b52 ldr r2, [r2, #52] ; 0x34
8005c5e: 0852 lsrs r2, r2, #1
8005c60: 3a01 subs r2, #1
8005c62: 0652 lsls r2, r2, #25
8005c64: 4311 orrs r1, r2
8005c66: 687a ldr r2, [r7, #4]
8005c68: 6ad2 ldr r2, [r2, #44] ; 0x2c
8005c6a: 06d2 lsls r2, r2, #27
8005c6c: 430a orrs r2, r1
8005c6e: 4947 ldr r1, [pc, #284] ; (8005d8c <HAL_RCC_OscConfig+0x628>)
8005c70: 4313 orrs r3, r2
8005c72: 60cb str r3, [r1, #12]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8005c74: 4b45 ldr r3, [pc, #276] ; (8005d8c <HAL_RCC_OscConfig+0x628>)
8005c76: 681b ldr r3, [r3, #0]
8005c78: 4a44 ldr r2, [pc, #272] ; (8005d8c <HAL_RCC_OscConfig+0x628>)
8005c7a: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
8005c7e: 6013 str r3, [r2, #0]
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
8005c80: 4b42 ldr r3, [pc, #264] ; (8005d8c <HAL_RCC_OscConfig+0x628>)
8005c82: 68db ldr r3, [r3, #12]
8005c84: 4a41 ldr r2, [pc, #260] ; (8005d8c <HAL_RCC_OscConfig+0x628>)
8005c86: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
8005c8a: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8005c8c: f7fc f862 bl 8001d54 <HAL_GetTick>
8005c90: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8005c92: e008 b.n 8005ca6 <HAL_RCC_OscConfig+0x542>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8005c94: f7fc f85e bl 8001d54 <HAL_GetTick>
8005c98: 4602 mov r2, r0
8005c9a: 693b ldr r3, [r7, #16]
8005c9c: 1ad3 subs r3, r2, r3
8005c9e: 2b02 cmp r3, #2
8005ca0: d901 bls.n 8005ca6 <HAL_RCC_OscConfig+0x542>
{
return HAL_TIMEOUT;
8005ca2: 2303 movs r3, #3
8005ca4: e06e b.n 8005d84 <HAL_RCC_OscConfig+0x620>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8005ca6: 4b39 ldr r3, [pc, #228] ; (8005d8c <HAL_RCC_OscConfig+0x628>)
8005ca8: 681b ldr r3, [r3, #0]
8005caa: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8005cae: 2b00 cmp r3, #0
8005cb0: d0f0 beq.n 8005c94 <HAL_RCC_OscConfig+0x530>
8005cb2: e066 b.n 8005d82 <HAL_RCC_OscConfig+0x61e>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8005cb4: 4b35 ldr r3, [pc, #212] ; (8005d8c <HAL_RCC_OscConfig+0x628>)
8005cb6: 681b ldr r3, [r3, #0]
8005cb8: 4a34 ldr r2, [pc, #208] ; (8005d8c <HAL_RCC_OscConfig+0x628>)
8005cba: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
8005cbe: 6013 str r3, [r2, #0]
/* Disable all PLL outputs to save power if no PLLs on */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
8005cc0: 4b32 ldr r3, [pc, #200] ; (8005d8c <HAL_RCC_OscConfig+0x628>)
8005cc2: 68db ldr r3, [r3, #12]
8005cc4: 4a31 ldr r2, [pc, #196] ; (8005d8c <HAL_RCC_OscConfig+0x628>)
8005cc6: f023 0303 bic.w r3, r3, #3
8005cca: 60d3 str r3, [r2, #12]
__HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK);
8005ccc: 4b2f ldr r3, [pc, #188] ; (8005d8c <HAL_RCC_OscConfig+0x628>)
8005cce: 68db ldr r3, [r3, #12]
8005cd0: 4a2e ldr r2, [pc, #184] ; (8005d8c <HAL_RCC_OscConfig+0x628>)
8005cd2: f023 7388 bic.w r3, r3, #17825792 ; 0x1100000
8005cd6: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8005cda: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8005cdc: f7fc f83a bl 8001d54 <HAL_GetTick>
8005ce0: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8005ce2: e008 b.n 8005cf6 <HAL_RCC_OscConfig+0x592>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8005ce4: f7fc f836 bl 8001d54 <HAL_GetTick>
8005ce8: 4602 mov r2, r0
8005cea: 693b ldr r3, [r7, #16]
8005cec: 1ad3 subs r3, r2, r3
8005cee: 2b02 cmp r3, #2
8005cf0: d901 bls.n 8005cf6 <HAL_RCC_OscConfig+0x592>
{
return HAL_TIMEOUT;
8005cf2: 2303 movs r3, #3
8005cf4: e046 b.n 8005d84 <HAL_RCC_OscConfig+0x620>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8005cf6: 4b25 ldr r3, [pc, #148] ; (8005d8c <HAL_RCC_OscConfig+0x628>)
8005cf8: 681b ldr r3, [r3, #0]
8005cfa: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8005cfe: 2b00 cmp r3, #0
8005d00: d1f0 bne.n 8005ce4 <HAL_RCC_OscConfig+0x580>
8005d02: e03e b.n 8005d82 <HAL_RCC_OscConfig+0x61e>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8005d04: 687b ldr r3, [r7, #4]
8005d06: 69db ldr r3, [r3, #28]
8005d08: 2b01 cmp r3, #1
8005d0a: d101 bne.n 8005d10 <HAL_RCC_OscConfig+0x5ac>
{
return HAL_ERROR;
8005d0c: 2301 movs r3, #1
8005d0e: e039 b.n 8005d84 <HAL_RCC_OscConfig+0x620>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
temp_pllckcfg = RCC->PLLCFGR;
8005d10: 4b1e ldr r3, [pc, #120] ; (8005d8c <HAL_RCC_OscConfig+0x628>)
8005d12: 68db ldr r3, [r3, #12]
8005d14: 617b str r3, [r7, #20]
if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8005d16: 697b ldr r3, [r7, #20]
8005d18: f003 0203 and.w r2, r3, #3
8005d1c: 687b ldr r3, [r7, #4]
8005d1e: 6a1b ldr r3, [r3, #32]
8005d20: 429a cmp r2, r3
8005d22: d12c bne.n 8005d7e <HAL_RCC_OscConfig+0x61a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
8005d24: 697b ldr r3, [r7, #20]
8005d26: f003 02f0 and.w r2, r3, #240 ; 0xf0
8005d2a: 687b ldr r3, [r7, #4]
8005d2c: 6a5b ldr r3, [r3, #36] ; 0x24
8005d2e: 3b01 subs r3, #1
8005d30: 011b lsls r3, r3, #4
if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8005d32: 429a cmp r2, r3
8005d34: d123 bne.n 8005d7e <HAL_RCC_OscConfig+0x61a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
8005d36: 697b ldr r3, [r7, #20]
8005d38: f403 42fe and.w r2, r3, #32512 ; 0x7f00
8005d3c: 687b ldr r3, [r7, #4]
8005d3e: 6a9b ldr r3, [r3, #40] ; 0x28
8005d40: 021b lsls r3, r3, #8
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
8005d42: 429a cmp r2, r3
8005d44: d11b bne.n 8005d7e <HAL_RCC_OscConfig+0x61a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
8005d46: 697b ldr r3, [r7, #20]
8005d48: f003 4278 and.w r2, r3, #4160749568 ; 0xf8000000
8005d4c: 687b ldr r3, [r7, #4]
8005d4e: 6adb ldr r3, [r3, #44] ; 0x2c
8005d50: 06db lsls r3, r3, #27
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
8005d52: 429a cmp r2, r3
8005d54: d113 bne.n 8005d7e <HAL_RCC_OscConfig+0x61a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
8005d56: 697b ldr r3, [r7, #20]
8005d58: f403 02c0 and.w r2, r3, #6291456 ; 0x600000
8005d5c: 687b ldr r3, [r7, #4]
8005d5e: 6b1b ldr r3, [r3, #48] ; 0x30
8005d60: 085b lsrs r3, r3, #1
8005d62: 3b01 subs r3, #1
8005d64: 055b lsls r3, r3, #21
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
8005d66: 429a cmp r2, r3
8005d68: d109 bne.n 8005d7e <HAL_RCC_OscConfig+0x61a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
8005d6a: 697b ldr r3, [r7, #20]
8005d6c: f003 62c0 and.w r2, r3, #100663296 ; 0x6000000
8005d70: 687b ldr r3, [r7, #4]
8005d72: 6b5b ldr r3, [r3, #52] ; 0x34
8005d74: 085b lsrs r3, r3, #1
8005d76: 3b01 subs r3, #1
8005d78: 065b lsls r3, r3, #25
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
8005d7a: 429a cmp r2, r3
8005d7c: d001 beq.n 8005d82 <HAL_RCC_OscConfig+0x61e>
{
return HAL_ERROR;
8005d7e: 2301 movs r3, #1
8005d80: e000 b.n 8005d84 <HAL_RCC_OscConfig+0x620>
}
}
}
}
return HAL_OK;
8005d82: 2300 movs r3, #0
}
8005d84: 4618 mov r0, r3
8005d86: 3720 adds r7, #32
8005d88: 46bd mov sp, r7
8005d8a: bd80 pop {r7, pc}
8005d8c: 40021000 .word 0x40021000
8005d90: 019f800c .word 0x019f800c
08005d94 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8005d94: b580 push {r7, lr}
8005d96: b086 sub sp, #24
8005d98: af00 add r7, sp, #0
8005d9a: 6078 str r0, [r7, #4]
8005d9c: 6039 str r1, [r7, #0]
uint32_t tickstart;
uint32_t pllfreq;
uint32_t hpre = RCC_SYSCLK_DIV1;
8005d9e: 2300 movs r3, #0
8005da0: 617b str r3, [r7, #20]
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8005da2: 687b ldr r3, [r7, #4]
8005da4: 2b00 cmp r3, #0
8005da6: d101 bne.n 8005dac <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
8005da8: 2301 movs r3, #1
8005daa: e11e b.n 8005fea <HAL_RCC_ClockConfig+0x256>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8005dac: 4b91 ldr r3, [pc, #580] ; (8005ff4 <HAL_RCC_ClockConfig+0x260>)
8005dae: 681b ldr r3, [r3, #0]
8005db0: f003 030f and.w r3, r3, #15
8005db4: 683a ldr r2, [r7, #0]
8005db6: 429a cmp r2, r3
8005db8: d910 bls.n 8005ddc <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8005dba: 4b8e ldr r3, [pc, #568] ; (8005ff4 <HAL_RCC_ClockConfig+0x260>)
8005dbc: 681b ldr r3, [r3, #0]
8005dbe: f023 020f bic.w r2, r3, #15
8005dc2: 498c ldr r1, [pc, #560] ; (8005ff4 <HAL_RCC_ClockConfig+0x260>)
8005dc4: 683b ldr r3, [r7, #0]
8005dc6: 4313 orrs r3, r2
8005dc8: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8005dca: 4b8a ldr r3, [pc, #552] ; (8005ff4 <HAL_RCC_ClockConfig+0x260>)
8005dcc: 681b ldr r3, [r3, #0]
8005dce: f003 030f and.w r3, r3, #15
8005dd2: 683a ldr r2, [r7, #0]
8005dd4: 429a cmp r2, r3
8005dd6: d001 beq.n 8005ddc <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
8005dd8: 2301 movs r3, #1
8005dda: e106 b.n 8005fea <HAL_RCC_ClockConfig+0x256>
}
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8005ddc: 687b ldr r3, [r7, #4]
8005dde: 681b ldr r3, [r3, #0]
8005de0: f003 0301 and.w r3, r3, #1
8005de4: 2b00 cmp r3, #0
8005de6: d073 beq.n 8005ed0 <HAL_RCC_ClockConfig+0x13c>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* PLL is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8005de8: 687b ldr r3, [r7, #4]
8005dea: 685b ldr r3, [r3, #4]
8005dec: 2b03 cmp r3, #3
8005dee: d129 bne.n 8005e44 <HAL_RCC_ClockConfig+0xb0>
{
/* Check the PLL ready flag */
if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8005df0: 4b81 ldr r3, [pc, #516] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005df2: 681b ldr r3, [r3, #0]
8005df4: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8005df8: 2b00 cmp r3, #0
8005dfa: d101 bne.n 8005e00 <HAL_RCC_ClockConfig+0x6c>
{
return HAL_ERROR;
8005dfc: 2301 movs r3, #1
8005dfe: e0f4 b.n 8005fea <HAL_RCC_ClockConfig+0x256>
}
/* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */
/* Compute target PLL output frequency */
pllfreq = RCC_GetSysClockFreqFromPLLSource();
8005e00: f000 f964 bl 80060cc <RCC_GetSysClockFreqFromPLLSource>
8005e04: 6138 str r0, [r7, #16]
/* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */
if(pllfreq > 80000000U)
8005e06: 693b ldr r3, [r7, #16]
8005e08: 4a7c ldr r2, [pc, #496] ; (8005ffc <HAL_RCC_ClockConfig+0x268>)
8005e0a: 4293 cmp r3, r2
8005e0c: d93f bls.n 8005e8e <HAL_RCC_ClockConfig+0xfa>
{
if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
8005e0e: 4b7a ldr r3, [pc, #488] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005e10: 689b ldr r3, [r3, #8]
8005e12: f003 03f0 and.w r3, r3, #240 ; 0xf0
8005e16: 2b00 cmp r3, #0
8005e18: d009 beq.n 8005e2e <HAL_RCC_ClockConfig+0x9a>
(((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
8005e1a: 687b ldr r3, [r7, #4]
8005e1c: 681b ldr r3, [r3, #0]
8005e1e: f003 0302 and.w r3, r3, #2
if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
8005e22: 2b00 cmp r3, #0
8005e24: d033 beq.n 8005e8e <HAL_RCC_ClockConfig+0xfa>
(RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1))))
8005e26: 687b ldr r3, [r7, #4]
8005e28: 689b ldr r3, [r3, #8]
(((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
8005e2a: 2b00 cmp r3, #0
8005e2c: d12f bne.n 8005e8e <HAL_RCC_ClockConfig+0xfa>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
8005e2e: 4b72 ldr r3, [pc, #456] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005e30: 689b ldr r3, [r3, #8]
8005e32: f023 03f0 bic.w r3, r3, #240 ; 0xf0
8005e36: 4a70 ldr r2, [pc, #448] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005e38: f043 0380 orr.w r3, r3, #128 ; 0x80
8005e3c: 6093 str r3, [r2, #8]
hpre = RCC_SYSCLK_DIV2;
8005e3e: 2380 movs r3, #128 ; 0x80
8005e40: 617b str r3, [r7, #20]
8005e42: e024 b.n 8005e8e <HAL_RCC_ClockConfig+0xfa>
}
}
else
{
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8005e44: 687b ldr r3, [r7, #4]
8005e46: 685b ldr r3, [r3, #4]
8005e48: 2b02 cmp r3, #2
8005e4a: d107 bne.n 8005e5c <HAL_RCC_ClockConfig+0xc8>
{
/* Check the HSE ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8005e4c: 4b6a ldr r3, [pc, #424] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005e4e: 681b ldr r3, [r3, #0]
8005e50: f403 3300 and.w r3, r3, #131072 ; 0x20000
8005e54: 2b00 cmp r3, #0
8005e56: d109 bne.n 8005e6c <HAL_RCC_ClockConfig+0xd8>
{
return HAL_ERROR;
8005e58: 2301 movs r3, #1
8005e5a: e0c6 b.n 8005fea <HAL_RCC_ClockConfig+0x256>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8005e5c: 4b66 ldr r3, [pc, #408] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005e5e: 681b ldr r3, [r3, #0]
8005e60: f403 6380 and.w r3, r3, #1024 ; 0x400
8005e64: 2b00 cmp r3, #0
8005e66: d101 bne.n 8005e6c <HAL_RCC_ClockConfig+0xd8>
{
return HAL_ERROR;
8005e68: 2301 movs r3, #1
8005e6a: e0be b.n 8005fea <HAL_RCC_ClockConfig+0x256>
}
}
/* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */
pllfreq = HAL_RCC_GetSysClockFreq();
8005e6c: f000 f8ce bl 800600c <HAL_RCC_GetSysClockFreq>
8005e70: 6138 str r0, [r7, #16]
/* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */
if(pllfreq > 80000000U)
8005e72: 693b ldr r3, [r7, #16]
8005e74: 4a61 ldr r2, [pc, #388] ; (8005ffc <HAL_RCC_ClockConfig+0x268>)
8005e76: 4293 cmp r3, r2
8005e78: d909 bls.n 8005e8e <HAL_RCC_ClockConfig+0xfa>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
8005e7a: 4b5f ldr r3, [pc, #380] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005e7c: 689b ldr r3, [r3, #8]
8005e7e: f023 03f0 bic.w r3, r3, #240 ; 0xf0
8005e82: 4a5d ldr r2, [pc, #372] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005e84: f043 0380 orr.w r3, r3, #128 ; 0x80
8005e88: 6093 str r3, [r2, #8]
hpre = RCC_SYSCLK_DIV2;
8005e8a: 2380 movs r3, #128 ; 0x80
8005e8c: 617b str r3, [r7, #20]
}
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
8005e8e: 4b5a ldr r3, [pc, #360] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005e90: 689b ldr r3, [r3, #8]
8005e92: f023 0203 bic.w r2, r3, #3
8005e96: 687b ldr r3, [r7, #4]
8005e98: 685b ldr r3, [r3, #4]
8005e9a: 4957 ldr r1, [pc, #348] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005e9c: 4313 orrs r3, r2
8005e9e: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8005ea0: f7fb ff58 bl 8001d54 <HAL_GetTick>
8005ea4: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8005ea6: e00a b.n 8005ebe <HAL_RCC_ClockConfig+0x12a>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8005ea8: f7fb ff54 bl 8001d54 <HAL_GetTick>
8005eac: 4602 mov r2, r0
8005eae: 68fb ldr r3, [r7, #12]
8005eb0: 1ad3 subs r3, r2, r3
8005eb2: f241 3288 movw r2, #5000 ; 0x1388
8005eb6: 4293 cmp r3, r2
8005eb8: d901 bls.n 8005ebe <HAL_RCC_ClockConfig+0x12a>
{
return HAL_TIMEOUT;
8005eba: 2303 movs r3, #3
8005ebc: e095 b.n 8005fea <HAL_RCC_ClockConfig+0x256>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8005ebe: 4b4e ldr r3, [pc, #312] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005ec0: 689b ldr r3, [r3, #8]
8005ec2: f003 020c and.w r2, r3, #12
8005ec6: 687b ldr r3, [r7, #4]
8005ec8: 685b ldr r3, [r3, #4]
8005eca: 009b lsls r3, r3, #2
8005ecc: 429a cmp r2, r3
8005ece: d1eb bne.n 8005ea8 <HAL_RCC_ClockConfig+0x114>
}
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8005ed0: 687b ldr r3, [r7, #4]
8005ed2: 681b ldr r3, [r3, #0]
8005ed4: f003 0302 and.w r3, r3, #2
8005ed8: 2b00 cmp r3, #0
8005eda: d023 beq.n 8005f24 <HAL_RCC_ClockConfig+0x190>
{
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8005edc: 687b ldr r3, [r7, #4]
8005ede: 681b ldr r3, [r3, #0]
8005ee0: f003 0304 and.w r3, r3, #4
8005ee4: 2b00 cmp r3, #0
8005ee6: d005 beq.n 8005ef4 <HAL_RCC_ClockConfig+0x160>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8005ee8: 4b43 ldr r3, [pc, #268] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005eea: 689b ldr r3, [r3, #8]
8005eec: 4a42 ldr r2, [pc, #264] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005eee: f443 63e0 orr.w r3, r3, #1792 ; 0x700
8005ef2: 6093 str r3, [r2, #8]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8005ef4: 687b ldr r3, [r7, #4]
8005ef6: 681b ldr r3, [r3, #0]
8005ef8: f003 0308 and.w r3, r3, #8
8005efc: 2b00 cmp r3, #0
8005efe: d007 beq.n 8005f10 <HAL_RCC_ClockConfig+0x17c>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16);
8005f00: 4b3d ldr r3, [pc, #244] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005f02: 689b ldr r3, [r3, #8]
8005f04: f423 537c bic.w r3, r3, #16128 ; 0x3f00
8005f08: 4a3b ldr r2, [pc, #236] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005f0a: f443 63e0 orr.w r3, r3, #1792 ; 0x700
8005f0e: 6093 str r3, [r2, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8005f10: 4b39 ldr r3, [pc, #228] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005f12: 689b ldr r3, [r3, #8]
8005f14: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8005f18: 687b ldr r3, [r7, #4]
8005f1a: 689b ldr r3, [r3, #8]
8005f1c: 4936 ldr r1, [pc, #216] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005f1e: 4313 orrs r3, r2
8005f20: 608b str r3, [r1, #8]
8005f22: e008 b.n 8005f36 <HAL_RCC_ClockConfig+0x1a2>
}
else
{
/* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */
if(hpre == RCC_SYSCLK_DIV2)
8005f24: 697b ldr r3, [r7, #20]
8005f26: 2b80 cmp r3, #128 ; 0x80
8005f28: d105 bne.n 8005f36 <HAL_RCC_ClockConfig+0x1a2>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
8005f2a: 4b33 ldr r3, [pc, #204] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005f2c: 689b ldr r3, [r3, #8]
8005f2e: 4a32 ldr r2, [pc, #200] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005f30: f023 03f0 bic.w r3, r3, #240 ; 0xf0
8005f34: 6093 str r3, [r2, #8]
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8005f36: 4b2f ldr r3, [pc, #188] ; (8005ff4 <HAL_RCC_ClockConfig+0x260>)
8005f38: 681b ldr r3, [r3, #0]
8005f3a: f003 030f and.w r3, r3, #15
8005f3e: 683a ldr r2, [r7, #0]
8005f40: 429a cmp r2, r3
8005f42: d21d bcs.n 8005f80 <HAL_RCC_ClockConfig+0x1ec>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8005f44: 4b2b ldr r3, [pc, #172] ; (8005ff4 <HAL_RCC_ClockConfig+0x260>)
8005f46: 681b ldr r3, [r3, #0]
8005f48: f023 020f bic.w r2, r3, #15
8005f4c: 4929 ldr r1, [pc, #164] ; (8005ff4 <HAL_RCC_ClockConfig+0x260>)
8005f4e: 683b ldr r3, [r7, #0]
8005f50: 4313 orrs r3, r2
8005f52: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by polling the FLASH_ACR register */
tickstart = HAL_GetTick();
8005f54: f7fb fefe bl 8001d54 <HAL_GetTick>
8005f58: 60f8 str r0, [r7, #12]
while (__HAL_FLASH_GET_LATENCY() != FLatency)
8005f5a: e00a b.n 8005f72 <HAL_RCC_ClockConfig+0x1de>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8005f5c: f7fb fefa bl 8001d54 <HAL_GetTick>
8005f60: 4602 mov r2, r0
8005f62: 68fb ldr r3, [r7, #12]
8005f64: 1ad3 subs r3, r2, r3
8005f66: f241 3288 movw r2, #5000 ; 0x1388
8005f6a: 4293 cmp r3, r2
8005f6c: d901 bls.n 8005f72 <HAL_RCC_ClockConfig+0x1de>
{
return HAL_TIMEOUT;
8005f6e: 2303 movs r3, #3
8005f70: e03b b.n 8005fea <HAL_RCC_ClockConfig+0x256>
while (__HAL_FLASH_GET_LATENCY() != FLatency)
8005f72: 4b20 ldr r3, [pc, #128] ; (8005ff4 <HAL_RCC_ClockConfig+0x260>)
8005f74: 681b ldr r3, [r3, #0]
8005f76: f003 030f and.w r3, r3, #15
8005f7a: 683a ldr r2, [r7, #0]
8005f7c: 429a cmp r2, r3
8005f7e: d1ed bne.n 8005f5c <HAL_RCC_ClockConfig+0x1c8>
}
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8005f80: 687b ldr r3, [r7, #4]
8005f82: 681b ldr r3, [r3, #0]
8005f84: f003 0304 and.w r3, r3, #4
8005f88: 2b00 cmp r3, #0
8005f8a: d008 beq.n 8005f9e <HAL_RCC_ClockConfig+0x20a>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8005f8c: 4b1a ldr r3, [pc, #104] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005f8e: 689b ldr r3, [r3, #8]
8005f90: f423 62e0 bic.w r2, r3, #1792 ; 0x700
8005f94: 687b ldr r3, [r7, #4]
8005f96: 68db ldr r3, [r3, #12]
8005f98: 4917 ldr r1, [pc, #92] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005f9a: 4313 orrs r3, r2
8005f9c: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8005f9e: 687b ldr r3, [r7, #4]
8005fa0: 681b ldr r3, [r3, #0]
8005fa2: f003 0308 and.w r3, r3, #8
8005fa6: 2b00 cmp r3, #0
8005fa8: d009 beq.n 8005fbe <HAL_RCC_ClockConfig+0x22a>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
8005faa: 4b13 ldr r3, [pc, #76] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005fac: 689b ldr r3, [r3, #8]
8005fae: f423 5260 bic.w r2, r3, #14336 ; 0x3800
8005fb2: 687b ldr r3, [r7, #4]
8005fb4: 691b ldr r3, [r3, #16]
8005fb6: 00db lsls r3, r3, #3
8005fb8: 490f ldr r1, [pc, #60] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005fba: 4313 orrs r3, r2
8005fbc: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
8005fbe: f000 f825 bl 800600c <HAL_RCC_GetSysClockFreq>
8005fc2: 4602 mov r2, r0
8005fc4: 4b0c ldr r3, [pc, #48] ; (8005ff8 <HAL_RCC_ClockConfig+0x264>)
8005fc6: 689b ldr r3, [r3, #8]
8005fc8: 091b lsrs r3, r3, #4
8005fca: f003 030f and.w r3, r3, #15
8005fce: 490c ldr r1, [pc, #48] ; (8006000 <HAL_RCC_ClockConfig+0x26c>)
8005fd0: 5ccb ldrb r3, [r1, r3]
8005fd2: f003 031f and.w r3, r3, #31
8005fd6: fa22 f303 lsr.w r3, r2, r3
8005fda: 4a0a ldr r2, [pc, #40] ; (8006004 <HAL_RCC_ClockConfig+0x270>)
8005fdc: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
return HAL_InitTick(uwTickPrio);
8005fde: 4b0a ldr r3, [pc, #40] ; (8006008 <HAL_RCC_ClockConfig+0x274>)
8005fe0: 681b ldr r3, [r3, #0]
8005fe2: 4618 mov r0, r3
8005fe4: f7fb fe6a bl 8001cbc <HAL_InitTick>
8005fe8: 4603 mov r3, r0
}
8005fea: 4618 mov r0, r3
8005fec: 3718 adds r7, #24
8005fee: 46bd mov sp, r7
8005ff0: bd80 pop {r7, pc}
8005ff2: bf00 nop
8005ff4: 40022000 .word 0x40022000
8005ff8: 40021000 .word 0x40021000
8005ffc: 04c4b400 .word 0x04c4b400
8006000: 08007cb0 .word 0x08007cb0
8006004: 20000004 .word 0x20000004
8006008: 20000008 .word 0x20000008
0800600c <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
800600c: b480 push {r7}
800600e: b087 sub sp, #28
8006010: af00 add r7, sp, #0
uint32_t pllvco, pllsource, pllr, pllm;
uint32_t sysclockfreq;
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
8006012: 4b2c ldr r3, [pc, #176] ; (80060c4 <HAL_RCC_GetSysClockFreq+0xb8>)
8006014: 689b ldr r3, [r3, #8]
8006016: f003 030c and.w r3, r3, #12
800601a: 2b04 cmp r3, #4
800601c: d102 bne.n 8006024 <HAL_RCC_GetSysClockFreq+0x18>
{
/* HSI used as system clock source */
sysclockfreq = HSI_VALUE;
800601e: 4b2a ldr r3, [pc, #168] ; (80060c8 <HAL_RCC_GetSysClockFreq+0xbc>)
8006020: 613b str r3, [r7, #16]
8006022: e047 b.n 80060b4 <HAL_RCC_GetSysClockFreq+0xa8>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
8006024: 4b27 ldr r3, [pc, #156] ; (80060c4 <HAL_RCC_GetSysClockFreq+0xb8>)
8006026: 689b ldr r3, [r3, #8]
8006028: f003 030c and.w r3, r3, #12
800602c: 2b08 cmp r3, #8
800602e: d102 bne.n 8006036 <HAL_RCC_GetSysClockFreq+0x2a>
{
/* HSE used as system clock source */
sysclockfreq = HSE_VALUE;
8006030: 4b25 ldr r3, [pc, #148] ; (80060c8 <HAL_RCC_GetSysClockFreq+0xbc>)
8006032: 613b str r3, [r7, #16]
8006034: e03e b.n 80060b4 <HAL_RCC_GetSysClockFreq+0xa8>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
8006036: 4b23 ldr r3, [pc, #140] ; (80060c4 <HAL_RCC_GetSysClockFreq+0xb8>)
8006038: 689b ldr r3, [r3, #8]
800603a: f003 030c and.w r3, r3, #12
800603e: 2b0c cmp r3, #12
8006040: d136 bne.n 80060b0 <HAL_RCC_GetSysClockFreq+0xa4>
/* PLL used as system clock source */
/* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
8006042: 4b20 ldr r3, [pc, #128] ; (80060c4 <HAL_RCC_GetSysClockFreq+0xb8>)
8006044: 68db ldr r3, [r3, #12]
8006046: f003 0303 and.w r3, r3, #3
800604a: 60fb str r3, [r7, #12]
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
800604c: 4b1d ldr r3, [pc, #116] ; (80060c4 <HAL_RCC_GetSysClockFreq+0xb8>)
800604e: 68db ldr r3, [r3, #12]
8006050: 091b lsrs r3, r3, #4
8006052: f003 030f and.w r3, r3, #15
8006056: 3301 adds r3, #1
8006058: 60bb str r3, [r7, #8]
switch (pllsource)
800605a: 68fb ldr r3, [r7, #12]
800605c: 2b03 cmp r3, #3
800605e: d10c bne.n 800607a <HAL_RCC_GetSysClockFreq+0x6e>
{
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
8006060: 4a19 ldr r2, [pc, #100] ; (80060c8 <HAL_RCC_GetSysClockFreq+0xbc>)
8006062: 68bb ldr r3, [r7, #8]
8006064: fbb2 f3f3 udiv r3, r2, r3
8006068: 4a16 ldr r2, [pc, #88] ; (80060c4 <HAL_RCC_GetSysClockFreq+0xb8>)
800606a: 68d2 ldr r2, [r2, #12]
800606c: 0a12 lsrs r2, r2, #8
800606e: f002 027f and.w r2, r2, #127 ; 0x7f
8006072: fb02 f303 mul.w r3, r2, r3
8006076: 617b str r3, [r7, #20]
break;
8006078: e00c b.n 8006094 <HAL_RCC_GetSysClockFreq+0x88>
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
default:
pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
800607a: 4a13 ldr r2, [pc, #76] ; (80060c8 <HAL_RCC_GetSysClockFreq+0xbc>)
800607c: 68bb ldr r3, [r7, #8]
800607e: fbb2 f3f3 udiv r3, r2, r3
8006082: 4a10 ldr r2, [pc, #64] ; (80060c4 <HAL_RCC_GetSysClockFreq+0xb8>)
8006084: 68d2 ldr r2, [r2, #12]
8006086: 0a12 lsrs r2, r2, #8
8006088: f002 027f and.w r2, r2, #127 ; 0x7f
800608c: fb02 f303 mul.w r3, r2, r3
8006090: 617b str r3, [r7, #20]
break;
8006092: bf00 nop
}
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
8006094: 4b0b ldr r3, [pc, #44] ; (80060c4 <HAL_RCC_GetSysClockFreq+0xb8>)
8006096: 68db ldr r3, [r3, #12]
8006098: 0e5b lsrs r3, r3, #25
800609a: f003 0303 and.w r3, r3, #3
800609e: 3301 adds r3, #1
80060a0: 005b lsls r3, r3, #1
80060a2: 607b str r3, [r7, #4]
sysclockfreq = pllvco/pllr;
80060a4: 697a ldr r2, [r7, #20]
80060a6: 687b ldr r3, [r7, #4]
80060a8: fbb2 f3f3 udiv r3, r2, r3
80060ac: 613b str r3, [r7, #16]
80060ae: e001 b.n 80060b4 <HAL_RCC_GetSysClockFreq+0xa8>
}
else
{
sysclockfreq = 0U;
80060b0: 2300 movs r3, #0
80060b2: 613b str r3, [r7, #16]
}
return sysclockfreq;
80060b4: 693b ldr r3, [r7, #16]
}
80060b6: 4618 mov r0, r3
80060b8: 371c adds r7, #28
80060ba: 46bd mov sp, r7
80060bc: f85d 7b04 ldr.w r7, [sp], #4
80060c0: 4770 bx lr
80060c2: bf00 nop
80060c4: 40021000 .word 0x40021000
80060c8: 00f42400 .word 0x00f42400
080060cc <RCC_GetSysClockFreqFromPLLSource>:
/**
* @brief Compute SYSCLK frequency based on PLL SYSCLK source.
* @retval SYSCLK frequency
*/
static uint32_t RCC_GetSysClockFreqFromPLLSource(void)
{
80060cc: b480 push {r7}
80060ce: b087 sub sp, #28
80060d0: af00 add r7, sp, #0
uint32_t sysclockfreq;
/* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
80060d2: 4b1e ldr r3, [pc, #120] ; (800614c <RCC_GetSysClockFreqFromPLLSource+0x80>)
80060d4: 68db ldr r3, [r3, #12]
80060d6: f003 0303 and.w r3, r3, #3
80060da: 613b str r3, [r7, #16]
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
80060dc: 4b1b ldr r3, [pc, #108] ; (800614c <RCC_GetSysClockFreqFromPLLSource+0x80>)
80060de: 68db ldr r3, [r3, #12]
80060e0: 091b lsrs r3, r3, #4
80060e2: f003 030f and.w r3, r3, #15
80060e6: 3301 adds r3, #1
80060e8: 60fb str r3, [r7, #12]
switch (pllsource)
80060ea: 693b ldr r3, [r7, #16]
80060ec: 2b03 cmp r3, #3
80060ee: d10c bne.n 800610a <RCC_GetSysClockFreqFromPLLSource+0x3e>
{
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
80060f0: 4a17 ldr r2, [pc, #92] ; (8006150 <RCC_GetSysClockFreqFromPLLSource+0x84>)
80060f2: 68fb ldr r3, [r7, #12]
80060f4: fbb2 f3f3 udiv r3, r2, r3
80060f8: 4a14 ldr r2, [pc, #80] ; (800614c <RCC_GetSysClockFreqFromPLLSource+0x80>)
80060fa: 68d2 ldr r2, [r2, #12]
80060fc: 0a12 lsrs r2, r2, #8
80060fe: f002 027f and.w r2, r2, #127 ; 0x7f
8006102: fb02 f303 mul.w r3, r2, r3
8006106: 617b str r3, [r7, #20]
break;
8006108: e00c b.n 8006124 <RCC_GetSysClockFreqFromPLLSource+0x58>
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
default:
pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
800610a: 4a11 ldr r2, [pc, #68] ; (8006150 <RCC_GetSysClockFreqFromPLLSource+0x84>)
800610c: 68fb ldr r3, [r7, #12]
800610e: fbb2 f3f3 udiv r3, r2, r3
8006112: 4a0e ldr r2, [pc, #56] ; (800614c <RCC_GetSysClockFreqFromPLLSource+0x80>)
8006114: 68d2 ldr r2, [r2, #12]
8006116: 0a12 lsrs r2, r2, #8
8006118: f002 027f and.w r2, r2, #127 ; 0x7f
800611c: fb02 f303 mul.w r3, r2, r3
8006120: 617b str r3, [r7, #20]
break;
8006122: bf00 nop
}
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
8006124: 4b09 ldr r3, [pc, #36] ; (800614c <RCC_GetSysClockFreqFromPLLSource+0x80>)
8006126: 68db ldr r3, [r3, #12]
8006128: 0e5b lsrs r3, r3, #25
800612a: f003 0303 and.w r3, r3, #3
800612e: 3301 adds r3, #1
8006130: 005b lsls r3, r3, #1
8006132: 60bb str r3, [r7, #8]
sysclockfreq = pllvco/pllr;
8006134: 697a ldr r2, [r7, #20]
8006136: 68bb ldr r3, [r7, #8]
8006138: fbb2 f3f3 udiv r3, r2, r3
800613c: 607b str r3, [r7, #4]
return sysclockfreq;
800613e: 687b ldr r3, [r7, #4]
}
8006140: 4618 mov r0, r3
8006142: 371c adds r7, #28
8006144: 46bd mov sp, r7
8006146: f85d 7b04 ldr.w r7, [sp], #4
800614a: 4770 bx lr
800614c: 40021000 .word 0x40021000
8006150: 00f42400 .word 0x00f42400
08006154 <HAL_RCCEx_PeriphCLKConfig>:
* the RTC clock source: in this case the access to Backup domain is enabled.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8006154: b580 push {r7, lr}
8006156: b086 sub sp, #24
8006158: af00 add r7, sp, #0
800615a: 6078 str r0, [r7, #4]
uint32_t tmpregister;
uint32_t tickstart;
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
800615c: 2300 movs r3, #0
800615e: 74fb strb r3, [r7, #19]
HAL_StatusTypeDef status = HAL_OK; /* Final status */
8006160: 2300 movs r3, #0
8006162: 74bb strb r3, [r7, #18]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*-------------------------- RTC clock source configuration ----------------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
8006164: 687b ldr r3, [r7, #4]
8006166: 681b ldr r3, [r3, #0]
8006168: f403 2300 and.w r3, r3, #524288 ; 0x80000
800616c: 2b00 cmp r3, #0
800616e: f000 8098 beq.w 80062a2 <HAL_RCCEx_PeriphCLKConfig+0x14e>
{
FlagStatus pwrclkchanged = RESET;
8006172: 2300 movs r3, #0
8006174: 747b strb r3, [r7, #17]
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8006176: 4b43 ldr r3, [pc, #268] ; (8006284 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006178: 6d9b ldr r3, [r3, #88] ; 0x58
800617a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800617e: 2b00 cmp r3, #0
8006180: d10d bne.n 800619e <HAL_RCCEx_PeriphCLKConfig+0x4a>
{
__HAL_RCC_PWR_CLK_ENABLE();
8006182: 4b40 ldr r3, [pc, #256] ; (8006284 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006184: 6d9b ldr r3, [r3, #88] ; 0x58
8006186: 4a3f ldr r2, [pc, #252] ; (8006284 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006188: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
800618c: 6593 str r3, [r2, #88] ; 0x58
800618e: 4b3d ldr r3, [pc, #244] ; (8006284 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006190: 6d9b ldr r3, [r3, #88] ; 0x58
8006192: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8006196: 60bb str r3, [r7, #8]
8006198: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
800619a: 2301 movs r3, #1
800619c: 747b strb r3, [r7, #17]
}
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
800619e: 4b3a ldr r3, [pc, #232] ; (8006288 <HAL_RCCEx_PeriphCLKConfig+0x134>)
80061a0: 681b ldr r3, [r3, #0]
80061a2: 4a39 ldr r2, [pc, #228] ; (8006288 <HAL_RCCEx_PeriphCLKConfig+0x134>)
80061a4: f443 7380 orr.w r3, r3, #256 ; 0x100
80061a8: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80061aa: f7fb fdd3 bl 8001d54 <HAL_GetTick>
80061ae: 60f8 str r0, [r7, #12]
while((PWR->CR1 & PWR_CR1_DBP) == 0U)
80061b0: e009 b.n 80061c6 <HAL_RCCEx_PeriphCLKConfig+0x72>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80061b2: f7fb fdcf bl 8001d54 <HAL_GetTick>
80061b6: 4602 mov r2, r0
80061b8: 68fb ldr r3, [r7, #12]
80061ba: 1ad3 subs r3, r2, r3
80061bc: 2b02 cmp r3, #2
80061be: d902 bls.n 80061c6 <HAL_RCCEx_PeriphCLKConfig+0x72>
{
ret = HAL_TIMEOUT;
80061c0: 2303 movs r3, #3
80061c2: 74fb strb r3, [r7, #19]
break;
80061c4: e005 b.n 80061d2 <HAL_RCCEx_PeriphCLKConfig+0x7e>
while((PWR->CR1 & PWR_CR1_DBP) == 0U)
80061c6: 4b30 ldr r3, [pc, #192] ; (8006288 <HAL_RCCEx_PeriphCLKConfig+0x134>)
80061c8: 681b ldr r3, [r3, #0]
80061ca: f403 7380 and.w r3, r3, #256 ; 0x100
80061ce: 2b00 cmp r3, #0
80061d0: d0ef beq.n 80061b2 <HAL_RCCEx_PeriphCLKConfig+0x5e>
}
}
if(ret == HAL_OK)
80061d2: 7cfb ldrb r3, [r7, #19]
80061d4: 2b00 cmp r3, #0
80061d6: d159 bne.n 800628c <HAL_RCCEx_PeriphCLKConfig+0x138>
{
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
80061d8: 4b2a ldr r3, [pc, #168] ; (8006284 <HAL_RCCEx_PeriphCLKConfig+0x130>)
80061da: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80061de: f403 7340 and.w r3, r3, #768 ; 0x300
80061e2: 617b str r3, [r7, #20]
if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
80061e4: 697b ldr r3, [r7, #20]
80061e6: 2b00 cmp r3, #0
80061e8: d01e beq.n 8006228 <HAL_RCCEx_PeriphCLKConfig+0xd4>
80061ea: 687b ldr r3, [r7, #4]
80061ec: 6c1b ldr r3, [r3, #64] ; 0x40
80061ee: 697a ldr r2, [r7, #20]
80061f0: 429a cmp r2, r3
80061f2: d019 beq.n 8006228 <HAL_RCCEx_PeriphCLKConfig+0xd4>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
80061f4: 4b23 ldr r3, [pc, #140] ; (8006284 <HAL_RCCEx_PeriphCLKConfig+0x130>)
80061f6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80061fa: f423 7340 bic.w r3, r3, #768 ; 0x300
80061fe: 617b str r3, [r7, #20]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8006200: 4b20 ldr r3, [pc, #128] ; (8006284 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006202: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8006206: 4a1f ldr r2, [pc, #124] ; (8006284 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006208: f443 3380 orr.w r3, r3, #65536 ; 0x10000
800620c: f8c2 3090 str.w r3, [r2, #144] ; 0x90
__HAL_RCC_BACKUPRESET_RELEASE();
8006210: 4b1c ldr r3, [pc, #112] ; (8006284 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006212: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8006216: 4a1b ldr r2, [pc, #108] ; (8006284 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006218: f423 3380 bic.w r3, r3, #65536 ; 0x10000
800621c: f8c2 3090 str.w r3, [r2, #144] ; 0x90
/* Restore the Content of BDCR register */
RCC->BDCR = tmpregister;
8006220: 4a18 ldr r2, [pc, #96] ; (8006284 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006222: 697b ldr r3, [r7, #20]
8006224: f8c2 3090 str.w r3, [r2, #144] ; 0x90
}
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
8006228: 697b ldr r3, [r7, #20]
800622a: f003 0301 and.w r3, r3, #1
800622e: 2b00 cmp r3, #0
8006230: d016 beq.n 8006260 <HAL_RCCEx_PeriphCLKConfig+0x10c>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8006232: f7fb fd8f bl 8001d54 <HAL_GetTick>
8006236: 60f8 str r0, [r7, #12]
/* Wait till LSE is ready */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8006238: e00b b.n 8006252 <HAL_RCCEx_PeriphCLKConfig+0xfe>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800623a: f7fb fd8b bl 8001d54 <HAL_GetTick>
800623e: 4602 mov r2, r0
8006240: 68fb ldr r3, [r7, #12]
8006242: 1ad3 subs r3, r2, r3
8006244: f241 3288 movw r2, #5000 ; 0x1388
8006248: 4293 cmp r3, r2
800624a: d902 bls.n 8006252 <HAL_RCCEx_PeriphCLKConfig+0xfe>
{
ret = HAL_TIMEOUT;
800624c: 2303 movs r3, #3
800624e: 74fb strb r3, [r7, #19]
break;
8006250: e006 b.n 8006260 <HAL_RCCEx_PeriphCLKConfig+0x10c>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8006252: 4b0c ldr r3, [pc, #48] ; (8006284 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006254: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8006258: f003 0302 and.w r3, r3, #2
800625c: 2b00 cmp r3, #0
800625e: d0ec beq.n 800623a <HAL_RCCEx_PeriphCLKConfig+0xe6>
}
}
}
if(ret == HAL_OK)
8006260: 7cfb ldrb r3, [r7, #19]
8006262: 2b00 cmp r3, #0
8006264: d10b bne.n 800627e <HAL_RCCEx_PeriphCLKConfig+0x12a>
{
/* Apply new RTC clock source selection */
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8006266: 4b07 ldr r3, [pc, #28] ; (8006284 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006268: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800626c: f423 7240 bic.w r2, r3, #768 ; 0x300
8006270: 687b ldr r3, [r7, #4]
8006272: 6c1b ldr r3, [r3, #64] ; 0x40
8006274: 4903 ldr r1, [pc, #12] ; (8006284 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006276: 4313 orrs r3, r2
8006278: f8c1 3090 str.w r3, [r1, #144] ; 0x90
800627c: e008 b.n 8006290 <HAL_RCCEx_PeriphCLKConfig+0x13c>
}
else
{
/* set overall return value */
status = ret;
800627e: 7cfb ldrb r3, [r7, #19]
8006280: 74bb strb r3, [r7, #18]
8006282: e005 b.n 8006290 <HAL_RCCEx_PeriphCLKConfig+0x13c>
8006284: 40021000 .word 0x40021000
8006288: 40007000 .word 0x40007000
}
}
else
{
/* set overall return value */
status = ret;
800628c: 7cfb ldrb r3, [r7, #19]
800628e: 74bb strb r3, [r7, #18]
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8006290: 7c7b ldrb r3, [r7, #17]
8006292: 2b01 cmp r3, #1
8006294: d105 bne.n 80062a2 <HAL_RCCEx_PeriphCLKConfig+0x14e>
{
__HAL_RCC_PWR_CLK_DISABLE();
8006296: 4ba6 ldr r3, [pc, #664] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8006298: 6d9b ldr r3, [r3, #88] ; 0x58
800629a: 4aa5 ldr r2, [pc, #660] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800629c: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
80062a0: 6593 str r3, [r2, #88] ; 0x58
}
}
/*-------------------------- USART1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
80062a2: 687b ldr r3, [r7, #4]
80062a4: 681b ldr r3, [r3, #0]
80062a6: f003 0301 and.w r3, r3, #1
80062aa: 2b00 cmp r3, #0
80062ac: d00a beq.n 80062c4 <HAL_RCCEx_PeriphCLKConfig+0x170>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
80062ae: 4ba0 ldr r3, [pc, #640] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80062b0: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80062b4: f023 0203 bic.w r2, r3, #3
80062b8: 687b ldr r3, [r7, #4]
80062ba: 685b ldr r3, [r3, #4]
80062bc: 499c ldr r1, [pc, #624] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80062be: 4313 orrs r3, r2
80062c0: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
/*-------------------------- USART2 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
80062c4: 687b ldr r3, [r7, #4]
80062c6: 681b ldr r3, [r3, #0]
80062c8: f003 0302 and.w r3, r3, #2
80062cc: 2b00 cmp r3, #0
80062ce: d00a beq.n 80062e6 <HAL_RCCEx_PeriphCLKConfig+0x192>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
80062d0: 4b97 ldr r3, [pc, #604] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80062d2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80062d6: f023 020c bic.w r2, r3, #12
80062da: 687b ldr r3, [r7, #4]
80062dc: 689b ldr r3, [r3, #8]
80062de: 4994 ldr r1, [pc, #592] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80062e0: 4313 orrs r3, r2
80062e2: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
/*-------------------------- USART3 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
80062e6: 687b ldr r3, [r7, #4]
80062e8: 681b ldr r3, [r3, #0]
80062ea: f003 0304 and.w r3, r3, #4
80062ee: 2b00 cmp r3, #0
80062f0: d00a beq.n 8006308 <HAL_RCCEx_PeriphCLKConfig+0x1b4>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
80062f2: 4b8f ldr r3, [pc, #572] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80062f4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80062f8: f023 0230 bic.w r2, r3, #48 ; 0x30
80062fc: 687b ldr r3, [r7, #4]
80062fe: 68db ldr r3, [r3, #12]
8006300: 498b ldr r1, [pc, #556] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8006302: 4313 orrs r3, r2
8006304: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
#if defined(UART4)
/*-------------------------- UART4 clock source configuration --------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
8006308: 687b ldr r3, [r7, #4]
800630a: 681b ldr r3, [r3, #0]
800630c: f003 0308 and.w r3, r3, #8
8006310: 2b00 cmp r3, #0
8006312: d00a beq.n 800632a <HAL_RCCEx_PeriphCLKConfig+0x1d6>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
8006314: 4b86 ldr r3, [pc, #536] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8006316: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800631a: f023 02c0 bic.w r2, r3, #192 ; 0xc0
800631e: 687b ldr r3, [r7, #4]
8006320: 691b ldr r3, [r3, #16]
8006322: 4983 ldr r1, [pc, #524] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8006324: 4313 orrs r3, r2
8006326: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
#endif /* UART5 */
/*-------------------------- LPUART1 clock source configuration ------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
800632a: 687b ldr r3, [r7, #4]
800632c: 681b ldr r3, [r3, #0]
800632e: f003 0320 and.w r3, r3, #32
8006332: 2b00 cmp r3, #0
8006334: d00a beq.n 800634c <HAL_RCCEx_PeriphCLKConfig+0x1f8>
{
/* Check the parameters */
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
/* Configure the LPUAR1 clock source */
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
8006336: 4b7e ldr r3, [pc, #504] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8006338: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800633c: f423 6240 bic.w r2, r3, #3072 ; 0xc00
8006340: 687b ldr r3, [r7, #4]
8006342: 695b ldr r3, [r3, #20]
8006344: 497a ldr r1, [pc, #488] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8006346: 4313 orrs r3, r2
8006348: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
/*-------------------------- I2C1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
800634c: 687b ldr r3, [r7, #4]
800634e: 681b ldr r3, [r3, #0]
8006350: f003 0340 and.w r3, r3, #64 ; 0x40
8006354: 2b00 cmp r3, #0
8006356: d00a beq.n 800636e <HAL_RCCEx_PeriphCLKConfig+0x21a>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
8006358: 4b75 ldr r3, [pc, #468] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800635a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800635e: f423 5240 bic.w r2, r3, #12288 ; 0x3000
8006362: 687b ldr r3, [r7, #4]
8006364: 699b ldr r3, [r3, #24]
8006366: 4972 ldr r1, [pc, #456] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8006368: 4313 orrs r3, r2
800636a: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
/*-------------------------- I2C2 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
800636e: 687b ldr r3, [r7, #4]
8006370: 681b ldr r3, [r3, #0]
8006372: f003 0380 and.w r3, r3, #128 ; 0x80
8006376: 2b00 cmp r3, #0
8006378: d00a beq.n 8006390 <HAL_RCCEx_PeriphCLKConfig+0x23c>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
800637a: 4b6d ldr r3, [pc, #436] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800637c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8006380: f423 4240 bic.w r2, r3, #49152 ; 0xc000
8006384: 687b ldr r3, [r7, #4]
8006386: 69db ldr r3, [r3, #28]
8006388: 4969 ldr r1, [pc, #420] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800638a: 4313 orrs r3, r2
800638c: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
/*-------------------------- I2C3 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
8006390: 687b ldr r3, [r7, #4]
8006392: 681b ldr r3, [r3, #0]
8006394: f403 7380 and.w r3, r3, #256 ; 0x100
8006398: 2b00 cmp r3, #0
800639a: d00a beq.n 80063b2 <HAL_RCCEx_PeriphCLKConfig+0x25e>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
800639c: 4b64 ldr r3, [pc, #400] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800639e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80063a2: f423 3240 bic.w r2, r3, #196608 ; 0x30000
80063a6: 687b ldr r3, [r7, #4]
80063a8: 6a1b ldr r3, [r3, #32]
80063aa: 4961 ldr r1, [pc, #388] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80063ac: 4313 orrs r3, r2
80063ae: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
#endif /* I2C4 */
/*-------------------------- LPTIM1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
80063b2: 687b ldr r3, [r7, #4]
80063b4: 681b ldr r3, [r3, #0]
80063b6: f403 7300 and.w r3, r3, #512 ; 0x200
80063ba: 2b00 cmp r3, #0
80063bc: d00a beq.n 80063d4 <HAL_RCCEx_PeriphCLKConfig+0x280>
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
/* Configure the LPTIM1 clock source */
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
80063be: 4b5c ldr r3, [pc, #368] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80063c0: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80063c4: f423 2240 bic.w r2, r3, #786432 ; 0xc0000
80063c8: 687b ldr r3, [r7, #4]
80063ca: 6a5b ldr r3, [r3, #36] ; 0x24
80063cc: 4958 ldr r1, [pc, #352] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80063ce: 4313 orrs r3, r2
80063d0: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
/*-------------------------- SAI1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
80063d4: 687b ldr r3, [r7, #4]
80063d6: 681b ldr r3, [r3, #0]
80063d8: f403 6380 and.w r3, r3, #1024 ; 0x400
80063dc: 2b00 cmp r3, #0
80063de: d015 beq.n 800640c <HAL_RCCEx_PeriphCLKConfig+0x2b8>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
/* Configure the SAI1 interface clock source */
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
80063e0: 4b53 ldr r3, [pc, #332] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80063e2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80063e6: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
80063ea: 687b ldr r3, [r7, #4]
80063ec: 6a9b ldr r3, [r3, #40] ; 0x28
80063ee: 4950 ldr r1, [pc, #320] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80063f0: 4313 orrs r3, r2
80063f2: f8c1 3088 str.w r3, [r1, #136] ; 0x88
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL)
80063f6: 687b ldr r3, [r7, #4]
80063f8: 6a9b ldr r3, [r3, #40] ; 0x28
80063fa: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
80063fe: d105 bne.n 800640c <HAL_RCCEx_PeriphCLKConfig+0x2b8>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8006400: 4b4b ldr r3, [pc, #300] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8006402: 68db ldr r3, [r3, #12]
8006404: 4a4a ldr r2, [pc, #296] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8006406: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
800640a: 60d3 str r3, [r2, #12]
}
}
/*-------------------------- I2S clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
800640c: 687b ldr r3, [r7, #4]
800640e: 681b ldr r3, [r3, #0]
8006410: f403 6300 and.w r3, r3, #2048 ; 0x800
8006414: 2b00 cmp r3, #0
8006416: d015 beq.n 8006444 <HAL_RCCEx_PeriphCLKConfig+0x2f0>
{
/* Check the parameters */
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
/* Configure the I2S interface clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
8006418: 4b45 ldr r3, [pc, #276] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800641a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800641e: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
8006422: 687b ldr r3, [r7, #4]
8006424: 6adb ldr r3, [r3, #44] ; 0x2c
8006426: 4942 ldr r1, [pc, #264] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8006428: 4313 orrs r3, r2
800642a: f8c1 3088 str.w r3, [r1, #136] ; 0x88
if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL)
800642e: 687b ldr r3, [r7, #4]
8006430: 6adb ldr r3, [r3, #44] ; 0x2c
8006432: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
8006436: d105 bne.n 8006444 <HAL_RCCEx_PeriphCLKConfig+0x2f0>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8006438: 4b3d ldr r3, [pc, #244] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800643a: 68db ldr r3, [r3, #12]
800643c: 4a3c ldr r2, [pc, #240] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800643e: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
8006442: 60d3 str r3, [r2, #12]
}
}
#if defined(FDCAN1)
/*-------------------------- FDCAN clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
8006444: 687b ldr r3, [r7, #4]
8006446: 681b ldr r3, [r3, #0]
8006448: f403 5380 and.w r3, r3, #4096 ; 0x1000
800644c: 2b00 cmp r3, #0
800644e: d015 beq.n 800647c <HAL_RCCEx_PeriphCLKConfig+0x328>
{
/* Check the parameters */
assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
/* Configure the FDCAN interface clock source */
__HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
8006450: 4b37 ldr r3, [pc, #220] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8006452: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8006456: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000
800645a: 687b ldr r3, [r7, #4]
800645c: 6b1b ldr r3, [r3, #48] ; 0x30
800645e: 4934 ldr r1, [pc, #208] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8006460: 4313 orrs r3, r2
8006462: f8c1 3088 str.w r3, [r1, #136] ; 0x88
if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL)
8006466: 687b ldr r3, [r7, #4]
8006468: 6b1b ldr r3, [r3, #48] ; 0x30
800646a: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
800646e: d105 bne.n 800647c <HAL_RCCEx_PeriphCLKConfig+0x328>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8006470: 4b2f ldr r3, [pc, #188] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8006472: 68db ldr r3, [r3, #12]
8006474: 4a2e ldr r2, [pc, #184] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8006476: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
800647a: 60d3 str r3, [r2, #12]
#endif /* FDCAN1 */
#if defined(USB)
/*-------------------------- USB clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
800647c: 687b ldr r3, [r7, #4]
800647e: 681b ldr r3, [r3, #0]
8006480: f403 5300 and.w r3, r3, #8192 ; 0x2000
8006484: 2b00 cmp r3, #0
8006486: d015 beq.n 80064b4 <HAL_RCCEx_PeriphCLKConfig+0x360>
{
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
8006488: 4b29 ldr r3, [pc, #164] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800648a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800648e: f023 6240 bic.w r2, r3, #201326592 ; 0xc000000
8006492: 687b ldr r3, [r7, #4]
8006494: 6b5b ldr r3, [r3, #52] ; 0x34
8006496: 4926 ldr r1, [pc, #152] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8006498: 4313 orrs r3, r2
800649a: f8c1 3088 str.w r3, [r1, #136] ; 0x88
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
800649e: 687b ldr r3, [r7, #4]
80064a0: 6b5b ldr r3, [r3, #52] ; 0x34
80064a2: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
80064a6: d105 bne.n 80064b4 <HAL_RCCEx_PeriphCLKConfig+0x360>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
80064a8: 4b21 ldr r3, [pc, #132] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80064aa: 68db ldr r3, [r3, #12]
80064ac: 4a20 ldr r2, [pc, #128] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80064ae: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
80064b2: 60d3 str r3, [r2, #12]
}
#endif /* USB */
/*-------------------------- RNG clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
80064b4: 687b ldr r3, [r7, #4]
80064b6: 681b ldr r3, [r3, #0]
80064b8: f403 4380 and.w r3, r3, #16384 ; 0x4000
80064bc: 2b00 cmp r3, #0
80064be: d015 beq.n 80064ec <HAL_RCCEx_PeriphCLKConfig+0x398>
{
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
80064c0: 4b1b ldr r3, [pc, #108] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80064c2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80064c6: f023 6240 bic.w r2, r3, #201326592 ; 0xc000000
80064ca: 687b ldr r3, [r7, #4]
80064cc: 6b9b ldr r3, [r3, #56] ; 0x38
80064ce: 4918 ldr r1, [pc, #96] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80064d0: 4313 orrs r3, r2
80064d2: f8c1 3088 str.w r3, [r1, #136] ; 0x88
if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
80064d6: 687b ldr r3, [r7, #4]
80064d8: 6b9b ldr r3, [r3, #56] ; 0x38
80064da: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
80064de: d105 bne.n 80064ec <HAL_RCCEx_PeriphCLKConfig+0x398>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
80064e0: 4b13 ldr r3, [pc, #76] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80064e2: 68db ldr r3, [r3, #12]
80064e4: 4a12 ldr r2, [pc, #72] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80064e6: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
80064ea: 60d3 str r3, [r2, #12]
}
}
/*-------------------------- ADC12 clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
80064ec: 687b ldr r3, [r7, #4]
80064ee: 681b ldr r3, [r3, #0]
80064f0: f403 4300 and.w r3, r3, #32768 ; 0x8000
80064f4: 2b00 cmp r3, #0
80064f6: d015 beq.n 8006524 <HAL_RCCEx_PeriphCLKConfig+0x3d0>
{
/* Check the parameters */
assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection));
/* Configure the ADC12 interface clock source */
__HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
80064f8: 4b0d ldr r3, [pc, #52] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80064fa: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80064fe: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000
8006502: 687b ldr r3, [r7, #4]
8006504: 6bdb ldr r3, [r3, #60] ; 0x3c
8006506: 490a ldr r1, [pc, #40] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8006508: 4313 orrs r3, r2
800650a: f8c1 3088 str.w r3, [r1, #136] ; 0x88
if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL)
800650e: 687b ldr r3, [r7, #4]
8006510: 6bdb ldr r3, [r3, #60] ; 0x3c
8006512: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
8006516: d105 bne.n 8006524 <HAL_RCCEx_PeriphCLKConfig+0x3d0>
{
/* Enable PLLADCCLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
8006518: 4b05 ldr r3, [pc, #20] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800651a: 68db ldr r3, [r3, #12]
800651c: 4a04 ldr r2, [pc, #16] ; (8006530 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800651e: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8006522: 60d3 str r3, [r2, #12]
}
}
#endif /* QUADSPI */
return status;
8006524: 7cbb ldrb r3, [r7, #18]
}
8006526: 4618 mov r0, r3
8006528: 3718 adds r7, #24
800652a: 46bd mov sp, r7
800652c: bd80 pop {r7, pc}
800652e: bf00 nop
8006530: 40021000 .word 0x40021000
08006534 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8006534: b580 push {r7, lr}
8006536: b082 sub sp, #8
8006538: af00 add r7, sp, #0
800653a: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
800653c: 687b ldr r3, [r7, #4]
800653e: 2b00 cmp r3, #0
8006540: d101 bne.n 8006546 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8006542: 2301 movs r3, #1
8006544: e049 b.n 80065da <HAL_TIM_Base_Init+0xa6>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8006546: 687b ldr r3, [r7, #4]
8006548: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
800654c: b2db uxtb r3, r3
800654e: 2b00 cmp r3, #0
8006550: d106 bne.n 8006560 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8006552: 687b ldr r3, [r7, #4]
8006554: 2200 movs r2, #0
8006556: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
800655a: 6878 ldr r0, [r7, #4]
800655c: f7fb fa4a bl 80019f4 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8006560: 687b ldr r3, [r7, #4]
8006562: 2202 movs r2, #2
8006564: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8006568: 687b ldr r3, [r7, #4]
800656a: 681a ldr r2, [r3, #0]
800656c: 687b ldr r3, [r7, #4]
800656e: 3304 adds r3, #4
8006570: 4619 mov r1, r3
8006572: 4610 mov r0, r2
8006574: f000 fe50 bl 8007218 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8006578: 687b ldr r3, [r7, #4]
800657a: 2201 movs r2, #1
800657c: f883 2048 strb.w r2, [r3, #72] ; 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8006580: 687b ldr r3, [r7, #4]
8006582: 2201 movs r2, #1
8006584: f883 203e strb.w r2, [r3, #62] ; 0x3e
8006588: 687b ldr r3, [r7, #4]
800658a: 2201 movs r2, #1
800658c: f883 203f strb.w r2, [r3, #63] ; 0x3f
8006590: 687b ldr r3, [r7, #4]
8006592: 2201 movs r2, #1
8006594: f883 2040 strb.w r2, [r3, #64] ; 0x40
8006598: 687b ldr r3, [r7, #4]
800659a: 2201 movs r2, #1
800659c: f883 2041 strb.w r2, [r3, #65] ; 0x41
80065a0: 687b ldr r3, [r7, #4]
80065a2: 2201 movs r2, #1
80065a4: f883 2042 strb.w r2, [r3, #66] ; 0x42
80065a8: 687b ldr r3, [r7, #4]
80065aa: 2201 movs r2, #1
80065ac: f883 2043 strb.w r2, [r3, #67] ; 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80065b0: 687b ldr r3, [r7, #4]
80065b2: 2201 movs r2, #1
80065b4: f883 2044 strb.w r2, [r3, #68] ; 0x44
80065b8: 687b ldr r3, [r7, #4]
80065ba: 2201 movs r2, #1
80065bc: f883 2045 strb.w r2, [r3, #69] ; 0x45
80065c0: 687b ldr r3, [r7, #4]
80065c2: 2201 movs r2, #1
80065c4: f883 2046 strb.w r2, [r3, #70] ; 0x46
80065c8: 687b ldr r3, [r7, #4]
80065ca: 2201 movs r2, #1
80065cc: f883 2047 strb.w r2, [r3, #71] ; 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
80065d0: 687b ldr r3, [r7, #4]
80065d2: 2201 movs r2, #1
80065d4: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
80065d8: 2300 movs r3, #0
}
80065da: 4618 mov r0, r3
80065dc: 3708 adds r7, #8
80065de: 46bd mov sp, r7
80065e0: bd80 pop {r7, pc}
...
080065e4 <HAL_TIM_Base_Start>:
* @brief Starts the TIM Base generation.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
{
80065e4: b480 push {r7}
80065e6: b085 sub sp, #20
80065e8: af00 add r7, sp, #0
80065ea: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Check the TIM state */
if (htim->State != HAL_TIM_STATE_READY)
80065ec: 687b ldr r3, [r7, #4]
80065ee: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
80065f2: b2db uxtb r3, r3
80065f4: 2b01 cmp r3, #1
80065f6: d001 beq.n 80065fc <HAL_TIM_Base_Start+0x18>
{
return HAL_ERROR;
80065f8: 2301 movs r3, #1
80065fa: e042 b.n 8006682 <HAL_TIM_Base_Start+0x9e>
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
80065fc: 687b ldr r3, [r7, #4]
80065fe: 2202 movs r2, #2
8006600: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8006604: 687b ldr r3, [r7, #4]
8006606: 681b ldr r3, [r3, #0]
8006608: 4a21 ldr r2, [pc, #132] ; (8006690 <HAL_TIM_Base_Start+0xac>)
800660a: 4293 cmp r3, r2
800660c: d018 beq.n 8006640 <HAL_TIM_Base_Start+0x5c>
800660e: 687b ldr r3, [r7, #4]
8006610: 681b ldr r3, [r3, #0]
8006612: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8006616: d013 beq.n 8006640 <HAL_TIM_Base_Start+0x5c>
8006618: 687b ldr r3, [r7, #4]
800661a: 681b ldr r3, [r3, #0]
800661c: 4a1d ldr r2, [pc, #116] ; (8006694 <HAL_TIM_Base_Start+0xb0>)
800661e: 4293 cmp r3, r2
8006620: d00e beq.n 8006640 <HAL_TIM_Base_Start+0x5c>
8006622: 687b ldr r3, [r7, #4]
8006624: 681b ldr r3, [r3, #0]
8006626: 4a1c ldr r2, [pc, #112] ; (8006698 <HAL_TIM_Base_Start+0xb4>)
8006628: 4293 cmp r3, r2
800662a: d009 beq.n 8006640 <HAL_TIM_Base_Start+0x5c>
800662c: 687b ldr r3, [r7, #4]
800662e: 681b ldr r3, [r3, #0]
8006630: 4a1a ldr r2, [pc, #104] ; (800669c <HAL_TIM_Base_Start+0xb8>)
8006632: 4293 cmp r3, r2
8006634: d004 beq.n 8006640 <HAL_TIM_Base_Start+0x5c>
8006636: 687b ldr r3, [r7, #4]
8006638: 681b ldr r3, [r3, #0]
800663a: 4a19 ldr r2, [pc, #100] ; (80066a0 <HAL_TIM_Base_Start+0xbc>)
800663c: 4293 cmp r3, r2
800663e: d115 bne.n 800666c <HAL_TIM_Base_Start+0x88>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8006640: 687b ldr r3, [r7, #4]
8006642: 681b ldr r3, [r3, #0]
8006644: 689a ldr r2, [r3, #8]
8006646: 4b17 ldr r3, [pc, #92] ; (80066a4 <HAL_TIM_Base_Start+0xc0>)
8006648: 4013 ands r3, r2
800664a: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
800664c: 68fb ldr r3, [r7, #12]
800664e: 2b06 cmp r3, #6
8006650: d015 beq.n 800667e <HAL_TIM_Base_Start+0x9a>
8006652: 68fb ldr r3, [r7, #12]
8006654: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8006658: d011 beq.n 800667e <HAL_TIM_Base_Start+0x9a>
{
__HAL_TIM_ENABLE(htim);
800665a: 687b ldr r3, [r7, #4]
800665c: 681b ldr r3, [r3, #0]
800665e: 681a ldr r2, [r3, #0]
8006660: 687b ldr r3, [r7, #4]
8006662: 681b ldr r3, [r3, #0]
8006664: f042 0201 orr.w r2, r2, #1
8006668: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
800666a: e008 b.n 800667e <HAL_TIM_Base_Start+0x9a>
}
}
else
{
__HAL_TIM_ENABLE(htim);
800666c: 687b ldr r3, [r7, #4]
800666e: 681b ldr r3, [r3, #0]
8006670: 681a ldr r2, [r3, #0]
8006672: 687b ldr r3, [r7, #4]
8006674: 681b ldr r3, [r3, #0]
8006676: f042 0201 orr.w r2, r2, #1
800667a: 601a str r2, [r3, #0]
800667c: e000 b.n 8006680 <HAL_TIM_Base_Start+0x9c>
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
800667e: bf00 nop
}
/* Return function status */
return HAL_OK;
8006680: 2300 movs r3, #0
}
8006682: 4618 mov r0, r3
8006684: 3714 adds r7, #20
8006686: 46bd mov sp, r7
8006688: f85d 7b04 ldr.w r7, [sp], #4
800668c: 4770 bx lr
800668e: bf00 nop
8006690: 40012c00 .word 0x40012c00
8006694: 40000400 .word 0x40000400
8006698: 40000800 .word 0x40000800
800669c: 40013400 .word 0x40013400
80066a0: 40014000 .word 0x40014000
80066a4: 00010007 .word 0x00010007
080066a8 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
80066a8: b580 push {r7, lr}
80066aa: b082 sub sp, #8
80066ac: af00 add r7, sp, #0
80066ae: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
80066b0: 687b ldr r3, [r7, #4]
80066b2: 2b00 cmp r3, #0
80066b4: d101 bne.n 80066ba <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
80066b6: 2301 movs r3, #1
80066b8: e049 b.n 800674e <HAL_TIM_PWM_Init+0xa6>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
80066ba: 687b ldr r3, [r7, #4]
80066bc: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
80066c0: b2db uxtb r3, r3
80066c2: 2b00 cmp r3, #0
80066c4: d106 bne.n 80066d4 <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
80066c6: 687b ldr r3, [r7, #4]
80066c8: 2200 movs r2, #0
80066ca: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
80066ce: 6878 ldr r0, [r7, #4]
80066d0: f000 f841 bl 8006756 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
80066d4: 687b ldr r3, [r7, #4]
80066d6: 2202 movs r2, #2
80066d8: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
80066dc: 687b ldr r3, [r7, #4]
80066de: 681a ldr r2, [r3, #0]
80066e0: 687b ldr r3, [r7, #4]
80066e2: 3304 adds r3, #4
80066e4: 4619 mov r1, r3
80066e6: 4610 mov r0, r2
80066e8: f000 fd96 bl 8007218 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
80066ec: 687b ldr r3, [r7, #4]
80066ee: 2201 movs r2, #1
80066f0: f883 2048 strb.w r2, [r3, #72] ; 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80066f4: 687b ldr r3, [r7, #4]
80066f6: 2201 movs r2, #1
80066f8: f883 203e strb.w r2, [r3, #62] ; 0x3e
80066fc: 687b ldr r3, [r7, #4]
80066fe: 2201 movs r2, #1
8006700: f883 203f strb.w r2, [r3, #63] ; 0x3f
8006704: 687b ldr r3, [r7, #4]
8006706: 2201 movs r2, #1
8006708: f883 2040 strb.w r2, [r3, #64] ; 0x40
800670c: 687b ldr r3, [r7, #4]
800670e: 2201 movs r2, #1
8006710: f883 2041 strb.w r2, [r3, #65] ; 0x41
8006714: 687b ldr r3, [r7, #4]
8006716: 2201 movs r2, #1
8006718: f883 2042 strb.w r2, [r3, #66] ; 0x42
800671c: 687b ldr r3, [r7, #4]
800671e: 2201 movs r2, #1
8006720: f883 2043 strb.w r2, [r3, #67] ; 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8006724: 687b ldr r3, [r7, #4]
8006726: 2201 movs r2, #1
8006728: f883 2044 strb.w r2, [r3, #68] ; 0x44
800672c: 687b ldr r3, [r7, #4]
800672e: 2201 movs r2, #1
8006730: f883 2045 strb.w r2, [r3, #69] ; 0x45
8006734: 687b ldr r3, [r7, #4]
8006736: 2201 movs r2, #1
8006738: f883 2046 strb.w r2, [r3, #70] ; 0x46
800673c: 687b ldr r3, [r7, #4]
800673e: 2201 movs r2, #1
8006740: f883 2047 strb.w r2, [r3, #71] ; 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8006744: 687b ldr r3, [r7, #4]
8006746: 2201 movs r2, #1
8006748: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
800674c: 2300 movs r3, #0
}
800674e: 4618 mov r0, r3
8006750: 3708 adds r7, #8
8006752: 46bd mov sp, r7
8006754: bd80 pop {r7, pc}
08006756 <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
8006756: b480 push {r7}
8006758: b083 sub sp, #12
800675a: af00 add r7, sp, #0
800675c: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
800675e: bf00 nop
8006760: 370c adds r7, #12
8006762: 46bd mov sp, r7
8006764: f85d 7b04 ldr.w r7, [sp], #4
8006768: 4770 bx lr
...
0800676c <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
800676c: b580 push {r7, lr}
800676e: b084 sub sp, #16
8006770: af00 add r7, sp, #0
8006772: 6078 str r0, [r7, #4]
8006774: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
8006776: 683b ldr r3, [r7, #0]
8006778: 2b00 cmp r3, #0
800677a: d109 bne.n 8006790 <HAL_TIM_PWM_Start+0x24>
800677c: 687b ldr r3, [r7, #4]
800677e: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
8006782: b2db uxtb r3, r3
8006784: 2b01 cmp r3, #1
8006786: bf14 ite ne
8006788: 2301 movne r3, #1
800678a: 2300 moveq r3, #0
800678c: b2db uxtb r3, r3
800678e: e03c b.n 800680a <HAL_TIM_PWM_Start+0x9e>
8006790: 683b ldr r3, [r7, #0]
8006792: 2b04 cmp r3, #4
8006794: d109 bne.n 80067aa <HAL_TIM_PWM_Start+0x3e>
8006796: 687b ldr r3, [r7, #4]
8006798: f893 303f ldrb.w r3, [r3, #63] ; 0x3f
800679c: b2db uxtb r3, r3
800679e: 2b01 cmp r3, #1
80067a0: bf14 ite ne
80067a2: 2301 movne r3, #1
80067a4: 2300 moveq r3, #0
80067a6: b2db uxtb r3, r3
80067a8: e02f b.n 800680a <HAL_TIM_PWM_Start+0x9e>
80067aa: 683b ldr r3, [r7, #0]
80067ac: 2b08 cmp r3, #8
80067ae: d109 bne.n 80067c4 <HAL_TIM_PWM_Start+0x58>
80067b0: 687b ldr r3, [r7, #4]
80067b2: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
80067b6: b2db uxtb r3, r3
80067b8: 2b01 cmp r3, #1
80067ba: bf14 ite ne
80067bc: 2301 movne r3, #1
80067be: 2300 moveq r3, #0
80067c0: b2db uxtb r3, r3
80067c2: e022 b.n 800680a <HAL_TIM_PWM_Start+0x9e>
80067c4: 683b ldr r3, [r7, #0]
80067c6: 2b0c cmp r3, #12
80067c8: d109 bne.n 80067de <HAL_TIM_PWM_Start+0x72>
80067ca: 687b ldr r3, [r7, #4]
80067cc: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
80067d0: b2db uxtb r3, r3
80067d2: 2b01 cmp r3, #1
80067d4: bf14 ite ne
80067d6: 2301 movne r3, #1
80067d8: 2300 moveq r3, #0
80067da: b2db uxtb r3, r3
80067dc: e015 b.n 800680a <HAL_TIM_PWM_Start+0x9e>
80067de: 683b ldr r3, [r7, #0]
80067e0: 2b10 cmp r3, #16
80067e2: d109 bne.n 80067f8 <HAL_TIM_PWM_Start+0x8c>
80067e4: 687b ldr r3, [r7, #4]
80067e6: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
80067ea: b2db uxtb r3, r3
80067ec: 2b01 cmp r3, #1
80067ee: bf14 ite ne
80067f0: 2301 movne r3, #1
80067f2: 2300 moveq r3, #0
80067f4: b2db uxtb r3, r3
80067f6: e008 b.n 800680a <HAL_TIM_PWM_Start+0x9e>
80067f8: 687b ldr r3, [r7, #4]
80067fa: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
80067fe: b2db uxtb r3, r3
8006800: 2b01 cmp r3, #1
8006802: bf14 ite ne
8006804: 2301 movne r3, #1
8006806: 2300 moveq r3, #0
8006808: b2db uxtb r3, r3
800680a: 2b00 cmp r3, #0
800680c: d001 beq.n 8006812 <HAL_TIM_PWM_Start+0xa6>
{
return HAL_ERROR;
800680e: 2301 movs r3, #1
8006810: e097 b.n 8006942 <HAL_TIM_PWM_Start+0x1d6>
}
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
8006812: 683b ldr r3, [r7, #0]
8006814: 2b00 cmp r3, #0
8006816: d104 bne.n 8006822 <HAL_TIM_PWM_Start+0xb6>
8006818: 687b ldr r3, [r7, #4]
800681a: 2202 movs r2, #2
800681c: f883 203e strb.w r2, [r3, #62] ; 0x3e
8006820: e023 b.n 800686a <HAL_TIM_PWM_Start+0xfe>
8006822: 683b ldr r3, [r7, #0]
8006824: 2b04 cmp r3, #4
8006826: d104 bne.n 8006832 <HAL_TIM_PWM_Start+0xc6>
8006828: 687b ldr r3, [r7, #4]
800682a: 2202 movs r2, #2
800682c: f883 203f strb.w r2, [r3, #63] ; 0x3f
8006830: e01b b.n 800686a <HAL_TIM_PWM_Start+0xfe>
8006832: 683b ldr r3, [r7, #0]
8006834: 2b08 cmp r3, #8
8006836: d104 bne.n 8006842 <HAL_TIM_PWM_Start+0xd6>
8006838: 687b ldr r3, [r7, #4]
800683a: 2202 movs r2, #2
800683c: f883 2040 strb.w r2, [r3, #64] ; 0x40
8006840: e013 b.n 800686a <HAL_TIM_PWM_Start+0xfe>
8006842: 683b ldr r3, [r7, #0]
8006844: 2b0c cmp r3, #12
8006846: d104 bne.n 8006852 <HAL_TIM_PWM_Start+0xe6>
8006848: 687b ldr r3, [r7, #4]
800684a: 2202 movs r2, #2
800684c: f883 2041 strb.w r2, [r3, #65] ; 0x41
8006850: e00b b.n 800686a <HAL_TIM_PWM_Start+0xfe>
8006852: 683b ldr r3, [r7, #0]
8006854: 2b10 cmp r3, #16
8006856: d104 bne.n 8006862 <HAL_TIM_PWM_Start+0xf6>
8006858: 687b ldr r3, [r7, #4]
800685a: 2202 movs r2, #2
800685c: f883 2042 strb.w r2, [r3, #66] ; 0x42
8006860: e003 b.n 800686a <HAL_TIM_PWM_Start+0xfe>
8006862: 687b ldr r3, [r7, #4]
8006864: 2202 movs r2, #2
8006866: f883 2043 strb.w r2, [r3, #67] ; 0x43
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
800686a: 687b ldr r3, [r7, #4]
800686c: 681b ldr r3, [r3, #0]
800686e: 2201 movs r2, #1
8006870: 6839 ldr r1, [r7, #0]
8006872: 4618 mov r0, r3
8006874: f001 f8f2 bl 8007a5c <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
8006878: 687b ldr r3, [r7, #4]
800687a: 681b ldr r3, [r3, #0]
800687c: 4a33 ldr r2, [pc, #204] ; (800694c <HAL_TIM_PWM_Start+0x1e0>)
800687e: 4293 cmp r3, r2
8006880: d013 beq.n 80068aa <HAL_TIM_PWM_Start+0x13e>
8006882: 687b ldr r3, [r7, #4]
8006884: 681b ldr r3, [r3, #0]
8006886: 4a32 ldr r2, [pc, #200] ; (8006950 <HAL_TIM_PWM_Start+0x1e4>)
8006888: 4293 cmp r3, r2
800688a: d00e beq.n 80068aa <HAL_TIM_PWM_Start+0x13e>
800688c: 687b ldr r3, [r7, #4]
800688e: 681b ldr r3, [r3, #0]
8006890: 4a30 ldr r2, [pc, #192] ; (8006954 <HAL_TIM_PWM_Start+0x1e8>)
8006892: 4293 cmp r3, r2
8006894: d009 beq.n 80068aa <HAL_TIM_PWM_Start+0x13e>
8006896: 687b ldr r3, [r7, #4]
8006898: 681b ldr r3, [r3, #0]
800689a: 4a2f ldr r2, [pc, #188] ; (8006958 <HAL_TIM_PWM_Start+0x1ec>)
800689c: 4293 cmp r3, r2
800689e: d004 beq.n 80068aa <HAL_TIM_PWM_Start+0x13e>
80068a0: 687b ldr r3, [r7, #4]
80068a2: 681b ldr r3, [r3, #0]
80068a4: 4a2d ldr r2, [pc, #180] ; (800695c <HAL_TIM_PWM_Start+0x1f0>)
80068a6: 4293 cmp r3, r2
80068a8: d101 bne.n 80068ae <HAL_TIM_PWM_Start+0x142>
80068aa: 2301 movs r3, #1
80068ac: e000 b.n 80068b0 <HAL_TIM_PWM_Start+0x144>
80068ae: 2300 movs r3, #0
80068b0: 2b00 cmp r3, #0
80068b2: d007 beq.n 80068c4 <HAL_TIM_PWM_Start+0x158>
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
80068b4: 687b ldr r3, [r7, #4]
80068b6: 681b ldr r3, [r3, #0]
80068b8: 6c5a ldr r2, [r3, #68] ; 0x44
80068ba: 687b ldr r3, [r7, #4]
80068bc: 681b ldr r3, [r3, #0]
80068be: f442 4200 orr.w r2, r2, #32768 ; 0x8000
80068c2: 645a str r2, [r3, #68] ; 0x44
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80068c4: 687b ldr r3, [r7, #4]
80068c6: 681b ldr r3, [r3, #0]
80068c8: 4a20 ldr r2, [pc, #128] ; (800694c <HAL_TIM_PWM_Start+0x1e0>)
80068ca: 4293 cmp r3, r2
80068cc: d018 beq.n 8006900 <HAL_TIM_PWM_Start+0x194>
80068ce: 687b ldr r3, [r7, #4]
80068d0: 681b ldr r3, [r3, #0]
80068d2: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
80068d6: d013 beq.n 8006900 <HAL_TIM_PWM_Start+0x194>
80068d8: 687b ldr r3, [r7, #4]
80068da: 681b ldr r3, [r3, #0]
80068dc: 4a20 ldr r2, [pc, #128] ; (8006960 <HAL_TIM_PWM_Start+0x1f4>)
80068de: 4293 cmp r3, r2
80068e0: d00e beq.n 8006900 <HAL_TIM_PWM_Start+0x194>
80068e2: 687b ldr r3, [r7, #4]
80068e4: 681b ldr r3, [r3, #0]
80068e6: 4a1f ldr r2, [pc, #124] ; (8006964 <HAL_TIM_PWM_Start+0x1f8>)
80068e8: 4293 cmp r3, r2
80068ea: d009 beq.n 8006900 <HAL_TIM_PWM_Start+0x194>
80068ec: 687b ldr r3, [r7, #4]
80068ee: 681b ldr r3, [r3, #0]
80068f0: 4a17 ldr r2, [pc, #92] ; (8006950 <HAL_TIM_PWM_Start+0x1e4>)
80068f2: 4293 cmp r3, r2
80068f4: d004 beq.n 8006900 <HAL_TIM_PWM_Start+0x194>
80068f6: 687b ldr r3, [r7, #4]
80068f8: 681b ldr r3, [r3, #0]
80068fa: 4a16 ldr r2, [pc, #88] ; (8006954 <HAL_TIM_PWM_Start+0x1e8>)
80068fc: 4293 cmp r3, r2
80068fe: d115 bne.n 800692c <HAL_TIM_PWM_Start+0x1c0>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8006900: 687b ldr r3, [r7, #4]
8006902: 681b ldr r3, [r3, #0]
8006904: 689a ldr r2, [r3, #8]
8006906: 4b18 ldr r3, [pc, #96] ; (8006968 <HAL_TIM_PWM_Start+0x1fc>)
8006908: 4013 ands r3, r2
800690a: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
800690c: 68fb ldr r3, [r7, #12]
800690e: 2b06 cmp r3, #6
8006910: d015 beq.n 800693e <HAL_TIM_PWM_Start+0x1d2>
8006912: 68fb ldr r3, [r7, #12]
8006914: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8006918: d011 beq.n 800693e <HAL_TIM_PWM_Start+0x1d2>
{
__HAL_TIM_ENABLE(htim);
800691a: 687b ldr r3, [r7, #4]
800691c: 681b ldr r3, [r3, #0]
800691e: 681a ldr r2, [r3, #0]
8006920: 687b ldr r3, [r7, #4]
8006922: 681b ldr r3, [r3, #0]
8006924: f042 0201 orr.w r2, r2, #1
8006928: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
800692a: e008 b.n 800693e <HAL_TIM_PWM_Start+0x1d2>
}
}
else
{
__HAL_TIM_ENABLE(htim);
800692c: 687b ldr r3, [r7, #4]
800692e: 681b ldr r3, [r3, #0]
8006930: 681a ldr r2, [r3, #0]
8006932: 687b ldr r3, [r7, #4]
8006934: 681b ldr r3, [r3, #0]
8006936: f042 0201 orr.w r2, r2, #1
800693a: 601a str r2, [r3, #0]
800693c: e000 b.n 8006940 <HAL_TIM_PWM_Start+0x1d4>
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
800693e: bf00 nop
}
/* Return function status */
return HAL_OK;
8006940: 2300 movs r3, #0
}
8006942: 4618 mov r0, r3
8006944: 3710 adds r7, #16
8006946: 46bd mov sp, r7
8006948: bd80 pop {r7, pc}
800694a: bf00 nop
800694c: 40012c00 .word 0x40012c00
8006950: 40013400 .word 0x40013400
8006954: 40014000 .word 0x40014000
8006958: 40014400 .word 0x40014400
800695c: 40014800 .word 0x40014800
8006960: 40000400 .word 0x40000400
8006964: 40000800 .word 0x40000800
8006968: 00010007 .word 0x00010007
0800696c <HAL_TIM_PWM_Stop>:
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
800696c: b580 push {r7, lr}
800696e: b082 sub sp, #8
8006970: af00 add r7, sp, #0
8006972: 6078 str r0, [r7, #4]
8006974: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
8006976: 687b ldr r3, [r7, #4]
8006978: 681b ldr r3, [r3, #0]
800697a: 2200 movs r2, #0
800697c: 6839 ldr r1, [r7, #0]
800697e: 4618 mov r0, r3
8006980: f001 f86c bl 8007a5c <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
8006984: 687b ldr r3, [r7, #4]
8006986: 681b ldr r3, [r3, #0]
8006988: 4a3e ldr r2, [pc, #248] ; (8006a84 <HAL_TIM_PWM_Stop+0x118>)
800698a: 4293 cmp r3, r2
800698c: d013 beq.n 80069b6 <HAL_TIM_PWM_Stop+0x4a>
800698e: 687b ldr r3, [r7, #4]
8006990: 681b ldr r3, [r3, #0]
8006992: 4a3d ldr r2, [pc, #244] ; (8006a88 <HAL_TIM_PWM_Stop+0x11c>)
8006994: 4293 cmp r3, r2
8006996: d00e beq.n 80069b6 <HAL_TIM_PWM_Stop+0x4a>
8006998: 687b ldr r3, [r7, #4]
800699a: 681b ldr r3, [r3, #0]
800699c: 4a3b ldr r2, [pc, #236] ; (8006a8c <HAL_TIM_PWM_Stop+0x120>)
800699e: 4293 cmp r3, r2
80069a0: d009 beq.n 80069b6 <HAL_TIM_PWM_Stop+0x4a>
80069a2: 687b ldr r3, [r7, #4]
80069a4: 681b ldr r3, [r3, #0]
80069a6: 4a3a ldr r2, [pc, #232] ; (8006a90 <HAL_TIM_PWM_Stop+0x124>)
80069a8: 4293 cmp r3, r2
80069aa: d004 beq.n 80069b6 <HAL_TIM_PWM_Stop+0x4a>
80069ac: 687b ldr r3, [r7, #4]
80069ae: 681b ldr r3, [r3, #0]
80069b0: 4a38 ldr r2, [pc, #224] ; (8006a94 <HAL_TIM_PWM_Stop+0x128>)
80069b2: 4293 cmp r3, r2
80069b4: d101 bne.n 80069ba <HAL_TIM_PWM_Stop+0x4e>
80069b6: 2301 movs r3, #1
80069b8: e000 b.n 80069bc <HAL_TIM_PWM_Stop+0x50>
80069ba: 2300 movs r3, #0
80069bc: 2b00 cmp r3, #0
80069be: d017 beq.n 80069f0 <HAL_TIM_PWM_Stop+0x84>
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
80069c0: 687b ldr r3, [r7, #4]
80069c2: 681b ldr r3, [r3, #0]
80069c4: 6a1a ldr r2, [r3, #32]
80069c6: f241 1311 movw r3, #4369 ; 0x1111
80069ca: 4013 ands r3, r2
80069cc: 2b00 cmp r3, #0
80069ce: d10f bne.n 80069f0 <HAL_TIM_PWM_Stop+0x84>
80069d0: 687b ldr r3, [r7, #4]
80069d2: 681b ldr r3, [r3, #0]
80069d4: 6a1a ldr r2, [r3, #32]
80069d6: f244 4344 movw r3, #17476 ; 0x4444
80069da: 4013 ands r3, r2
80069dc: 2b00 cmp r3, #0
80069de: d107 bne.n 80069f0 <HAL_TIM_PWM_Stop+0x84>
80069e0: 687b ldr r3, [r7, #4]
80069e2: 681b ldr r3, [r3, #0]
80069e4: 6c5a ldr r2, [r3, #68] ; 0x44
80069e6: 687b ldr r3, [r7, #4]
80069e8: 681b ldr r3, [r3, #0]
80069ea: f422 4200 bic.w r2, r2, #32768 ; 0x8000
80069ee: 645a str r2, [r3, #68] ; 0x44
}
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
80069f0: 687b ldr r3, [r7, #4]
80069f2: 681b ldr r3, [r3, #0]
80069f4: 6a1a ldr r2, [r3, #32]
80069f6: f241 1311 movw r3, #4369 ; 0x1111
80069fa: 4013 ands r3, r2
80069fc: 2b00 cmp r3, #0
80069fe: d10f bne.n 8006a20 <HAL_TIM_PWM_Stop+0xb4>
8006a00: 687b ldr r3, [r7, #4]
8006a02: 681b ldr r3, [r3, #0]
8006a04: 6a1a ldr r2, [r3, #32]
8006a06: f244 4344 movw r3, #17476 ; 0x4444
8006a0a: 4013 ands r3, r2
8006a0c: 2b00 cmp r3, #0
8006a0e: d107 bne.n 8006a20 <HAL_TIM_PWM_Stop+0xb4>
8006a10: 687b ldr r3, [r7, #4]
8006a12: 681b ldr r3, [r3, #0]
8006a14: 681a ldr r2, [r3, #0]
8006a16: 687b ldr r3, [r7, #4]
8006a18: 681b ldr r3, [r3, #0]
8006a1a: f022 0201 bic.w r2, r2, #1
8006a1e: 601a str r2, [r3, #0]
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
8006a20: 683b ldr r3, [r7, #0]
8006a22: 2b00 cmp r3, #0
8006a24: d104 bne.n 8006a30 <HAL_TIM_PWM_Stop+0xc4>
8006a26: 687b ldr r3, [r7, #4]
8006a28: 2201 movs r2, #1
8006a2a: f883 203e strb.w r2, [r3, #62] ; 0x3e
8006a2e: e023 b.n 8006a78 <HAL_TIM_PWM_Stop+0x10c>
8006a30: 683b ldr r3, [r7, #0]
8006a32: 2b04 cmp r3, #4
8006a34: d104 bne.n 8006a40 <HAL_TIM_PWM_Stop+0xd4>
8006a36: 687b ldr r3, [r7, #4]
8006a38: 2201 movs r2, #1
8006a3a: f883 203f strb.w r2, [r3, #63] ; 0x3f
8006a3e: e01b b.n 8006a78 <HAL_TIM_PWM_Stop+0x10c>
8006a40: 683b ldr r3, [r7, #0]
8006a42: 2b08 cmp r3, #8
8006a44: d104 bne.n 8006a50 <HAL_TIM_PWM_Stop+0xe4>
8006a46: 687b ldr r3, [r7, #4]
8006a48: 2201 movs r2, #1
8006a4a: f883 2040 strb.w r2, [r3, #64] ; 0x40
8006a4e: e013 b.n 8006a78 <HAL_TIM_PWM_Stop+0x10c>
8006a50: 683b ldr r3, [r7, #0]
8006a52: 2b0c cmp r3, #12
8006a54: d104 bne.n 8006a60 <HAL_TIM_PWM_Stop+0xf4>
8006a56: 687b ldr r3, [r7, #4]
8006a58: 2201 movs r2, #1
8006a5a: f883 2041 strb.w r2, [r3, #65] ; 0x41
8006a5e: e00b b.n 8006a78 <HAL_TIM_PWM_Stop+0x10c>
8006a60: 683b ldr r3, [r7, #0]
8006a62: 2b10 cmp r3, #16
8006a64: d104 bne.n 8006a70 <HAL_TIM_PWM_Stop+0x104>
8006a66: 687b ldr r3, [r7, #4]
8006a68: 2201 movs r2, #1
8006a6a: f883 2042 strb.w r2, [r3, #66] ; 0x42
8006a6e: e003 b.n 8006a78 <HAL_TIM_PWM_Stop+0x10c>
8006a70: 687b ldr r3, [r7, #4]
8006a72: 2201 movs r2, #1
8006a74: f883 2043 strb.w r2, [r3, #67] ; 0x43
/* Return function status */
return HAL_OK;
8006a78: 2300 movs r3, #0
}
8006a7a: 4618 mov r0, r3
8006a7c: 3708 adds r7, #8
8006a7e: 46bd mov sp, r7
8006a80: bd80 pop {r7, pc}
8006a82: bf00 nop
8006a84: 40012c00 .word 0x40012c00
8006a88: 40013400 .word 0x40013400
8006a8c: 40014000 .word 0x40014000
8006a90: 40014400 .word 0x40014400
8006a94: 40014800 .word 0x40014800
08006a98 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8006a98: b580 push {r7, lr}
8006a9a: b082 sub sp, #8
8006a9c: af00 add r7, sp, #0
8006a9e: 6078 str r0, [r7, #4]
/* Capture compare 1 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
8006aa0: 687b ldr r3, [r7, #4]
8006aa2: 681b ldr r3, [r3, #0]
8006aa4: 691b ldr r3, [r3, #16]
8006aa6: f003 0302 and.w r3, r3, #2
8006aaa: 2b02 cmp r3, #2
8006aac: d122 bne.n 8006af4 <HAL_TIM_IRQHandler+0x5c>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
8006aae: 687b ldr r3, [r7, #4]
8006ab0: 681b ldr r3, [r3, #0]
8006ab2: 68db ldr r3, [r3, #12]
8006ab4: f003 0302 and.w r3, r3, #2
8006ab8: 2b02 cmp r3, #2
8006aba: d11b bne.n 8006af4 <HAL_TIM_IRQHandler+0x5c>
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
8006abc: 687b ldr r3, [r7, #4]
8006abe: 681b ldr r3, [r3, #0]
8006ac0: f06f 0202 mvn.w r2, #2
8006ac4: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8006ac6: 687b ldr r3, [r7, #4]
8006ac8: 2201 movs r2, #1
8006aca: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8006acc: 687b ldr r3, [r7, #4]
8006ace: 681b ldr r3, [r3, #0]
8006ad0: 699b ldr r3, [r3, #24]
8006ad2: f003 0303 and.w r3, r3, #3
8006ad6: 2b00 cmp r3, #0
8006ad8: d003 beq.n 8006ae2 <HAL_TIM_IRQHandler+0x4a>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8006ada: 6878 ldr r0, [r7, #4]
8006adc: f000 fb7e bl 80071dc <HAL_TIM_IC_CaptureCallback>
8006ae0: e005 b.n 8006aee <HAL_TIM_IRQHandler+0x56>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8006ae2: 6878 ldr r0, [r7, #4]
8006ae4: f000 fb70 bl 80071c8 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8006ae8: 6878 ldr r0, [r7, #4]
8006aea: f000 fb81 bl 80071f0 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8006aee: 687b ldr r3, [r7, #4]
8006af0: 2200 movs r2, #0
8006af2: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
8006af4: 687b ldr r3, [r7, #4]
8006af6: 681b ldr r3, [r3, #0]
8006af8: 691b ldr r3, [r3, #16]
8006afa: f003 0304 and.w r3, r3, #4
8006afe: 2b04 cmp r3, #4
8006b00: d122 bne.n 8006b48 <HAL_TIM_IRQHandler+0xb0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
8006b02: 687b ldr r3, [r7, #4]
8006b04: 681b ldr r3, [r3, #0]
8006b06: 68db ldr r3, [r3, #12]
8006b08: f003 0304 and.w r3, r3, #4
8006b0c: 2b04 cmp r3, #4
8006b0e: d11b bne.n 8006b48 <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
8006b10: 687b ldr r3, [r7, #4]
8006b12: 681b ldr r3, [r3, #0]
8006b14: f06f 0204 mvn.w r2, #4
8006b18: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8006b1a: 687b ldr r3, [r7, #4]
8006b1c: 2202 movs r2, #2
8006b1e: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8006b20: 687b ldr r3, [r7, #4]
8006b22: 681b ldr r3, [r3, #0]
8006b24: 699b ldr r3, [r3, #24]
8006b26: f403 7340 and.w r3, r3, #768 ; 0x300
8006b2a: 2b00 cmp r3, #0
8006b2c: d003 beq.n 8006b36 <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8006b2e: 6878 ldr r0, [r7, #4]
8006b30: f000 fb54 bl 80071dc <HAL_TIM_IC_CaptureCallback>
8006b34: e005 b.n 8006b42 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8006b36: 6878 ldr r0, [r7, #4]
8006b38: f000 fb46 bl 80071c8 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8006b3c: 6878 ldr r0, [r7, #4]
8006b3e: f000 fb57 bl 80071f0 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8006b42: 687b ldr r3, [r7, #4]
8006b44: 2200 movs r2, #0
8006b46: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
8006b48: 687b ldr r3, [r7, #4]
8006b4a: 681b ldr r3, [r3, #0]
8006b4c: 691b ldr r3, [r3, #16]
8006b4e: f003 0308 and.w r3, r3, #8
8006b52: 2b08 cmp r3, #8
8006b54: d122 bne.n 8006b9c <HAL_TIM_IRQHandler+0x104>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
8006b56: 687b ldr r3, [r7, #4]
8006b58: 681b ldr r3, [r3, #0]
8006b5a: 68db ldr r3, [r3, #12]
8006b5c: f003 0308 and.w r3, r3, #8
8006b60: 2b08 cmp r3, #8
8006b62: d11b bne.n 8006b9c <HAL_TIM_IRQHandler+0x104>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
8006b64: 687b ldr r3, [r7, #4]
8006b66: 681b ldr r3, [r3, #0]
8006b68: f06f 0208 mvn.w r2, #8
8006b6c: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8006b6e: 687b ldr r3, [r7, #4]
8006b70: 2204 movs r2, #4
8006b72: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8006b74: 687b ldr r3, [r7, #4]
8006b76: 681b ldr r3, [r3, #0]
8006b78: 69db ldr r3, [r3, #28]
8006b7a: f003 0303 and.w r3, r3, #3
8006b7e: 2b00 cmp r3, #0
8006b80: d003 beq.n 8006b8a <HAL_TIM_IRQHandler+0xf2>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8006b82: 6878 ldr r0, [r7, #4]
8006b84: f000 fb2a bl 80071dc <HAL_TIM_IC_CaptureCallback>
8006b88: e005 b.n 8006b96 <HAL_TIM_IRQHandler+0xfe>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8006b8a: 6878 ldr r0, [r7, #4]
8006b8c: f000 fb1c bl 80071c8 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8006b90: 6878 ldr r0, [r7, #4]
8006b92: f000 fb2d bl 80071f0 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8006b96: 687b ldr r3, [r7, #4]
8006b98: 2200 movs r2, #0
8006b9a: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
8006b9c: 687b ldr r3, [r7, #4]
8006b9e: 681b ldr r3, [r3, #0]
8006ba0: 691b ldr r3, [r3, #16]
8006ba2: f003 0310 and.w r3, r3, #16
8006ba6: 2b10 cmp r3, #16
8006ba8: d122 bne.n 8006bf0 <HAL_TIM_IRQHandler+0x158>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
8006baa: 687b ldr r3, [r7, #4]
8006bac: 681b ldr r3, [r3, #0]
8006bae: 68db ldr r3, [r3, #12]
8006bb0: f003 0310 and.w r3, r3, #16
8006bb4: 2b10 cmp r3, #16
8006bb6: d11b bne.n 8006bf0 <HAL_TIM_IRQHandler+0x158>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
8006bb8: 687b ldr r3, [r7, #4]
8006bba: 681b ldr r3, [r3, #0]
8006bbc: f06f 0210 mvn.w r2, #16
8006bc0: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8006bc2: 687b ldr r3, [r7, #4]
8006bc4: 2208 movs r2, #8
8006bc6: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8006bc8: 687b ldr r3, [r7, #4]
8006bca: 681b ldr r3, [r3, #0]
8006bcc: 69db ldr r3, [r3, #28]
8006bce: f403 7340 and.w r3, r3, #768 ; 0x300
8006bd2: 2b00 cmp r3, #0
8006bd4: d003 beq.n 8006bde <HAL_TIM_IRQHandler+0x146>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8006bd6: 6878 ldr r0, [r7, #4]
8006bd8: f000 fb00 bl 80071dc <HAL_TIM_IC_CaptureCallback>
8006bdc: e005 b.n 8006bea <HAL_TIM_IRQHandler+0x152>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8006bde: 6878 ldr r0, [r7, #4]
8006be0: f000 faf2 bl 80071c8 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8006be4: 6878 ldr r0, [r7, #4]
8006be6: f000 fb03 bl 80071f0 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8006bea: 687b ldr r3, [r7, #4]
8006bec: 2200 movs r2, #0
8006bee: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
8006bf0: 687b ldr r3, [r7, #4]
8006bf2: 681b ldr r3, [r3, #0]
8006bf4: 691b ldr r3, [r3, #16]
8006bf6: f003 0301 and.w r3, r3, #1
8006bfa: 2b01 cmp r3, #1
8006bfc: d10e bne.n 8006c1c <HAL_TIM_IRQHandler+0x184>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
8006bfe: 687b ldr r3, [r7, #4]
8006c00: 681b ldr r3, [r3, #0]
8006c02: 68db ldr r3, [r3, #12]
8006c04: f003 0301 and.w r3, r3, #1
8006c08: 2b01 cmp r3, #1
8006c0a: d107 bne.n 8006c1c <HAL_TIM_IRQHandler+0x184>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
8006c0c: 687b ldr r3, [r7, #4]
8006c0e: 681b ldr r3, [r3, #0]
8006c10: f06f 0201 mvn.w r2, #1
8006c14: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8006c16: 6878 ldr r0, [r7, #4]
8006c18: f000 facc bl 80071b4 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
8006c1c: 687b ldr r3, [r7, #4]
8006c1e: 681b ldr r3, [r3, #0]
8006c20: 691b ldr r3, [r3, #16]
8006c22: f003 0380 and.w r3, r3, #128 ; 0x80
8006c26: 2b80 cmp r3, #128 ; 0x80
8006c28: d10e bne.n 8006c48 <HAL_TIM_IRQHandler+0x1b0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8006c2a: 687b ldr r3, [r7, #4]
8006c2c: 681b ldr r3, [r3, #0]
8006c2e: 68db ldr r3, [r3, #12]
8006c30: f003 0380 and.w r3, r3, #128 ; 0x80
8006c34: 2b80 cmp r3, #128 ; 0x80
8006c36: d107 bne.n 8006c48 <HAL_TIM_IRQHandler+0x1b0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
8006c38: 687b ldr r3, [r7, #4]
8006c3a: 681b ldr r3, [r3, #0]
8006c3c: f06f 0280 mvn.w r2, #128 ; 0x80
8006c40: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
8006c42: 6878 ldr r0, [r7, #4]
8006c44: f000 ffbc bl 8007bc0 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break2 input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
8006c48: 687b ldr r3, [r7, #4]
8006c4a: 681b ldr r3, [r3, #0]
8006c4c: 691b ldr r3, [r3, #16]
8006c4e: f403 7380 and.w r3, r3, #256 ; 0x100
8006c52: f5b3 7f80 cmp.w r3, #256 ; 0x100
8006c56: d10e bne.n 8006c76 <HAL_TIM_IRQHandler+0x1de>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8006c58: 687b ldr r3, [r7, #4]
8006c5a: 681b ldr r3, [r3, #0]
8006c5c: 68db ldr r3, [r3, #12]
8006c5e: f003 0380 and.w r3, r3, #128 ; 0x80
8006c62: 2b80 cmp r3, #128 ; 0x80
8006c64: d107 bne.n 8006c76 <HAL_TIM_IRQHandler+0x1de>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
8006c66: 687b ldr r3, [r7, #4]
8006c68: 681b ldr r3, [r3, #0]
8006c6a: f46f 7280 mvn.w r2, #256 ; 0x100
8006c6e: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->Break2Callback(htim);
#else
HAL_TIMEx_Break2Callback(htim);
8006c70: 6878 ldr r0, [r7, #4]
8006c72: f000 ffaf bl 8007bd4 <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
8006c76: 687b ldr r3, [r7, #4]
8006c78: 681b ldr r3, [r3, #0]
8006c7a: 691b ldr r3, [r3, #16]
8006c7c: f003 0340 and.w r3, r3, #64 ; 0x40
8006c80: 2b40 cmp r3, #64 ; 0x40
8006c82: d10e bne.n 8006ca2 <HAL_TIM_IRQHandler+0x20a>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
8006c84: 687b ldr r3, [r7, #4]
8006c86: 681b ldr r3, [r3, #0]
8006c88: 68db ldr r3, [r3, #12]
8006c8a: f003 0340 and.w r3, r3, #64 ; 0x40
8006c8e: 2b40 cmp r3, #64 ; 0x40
8006c90: d107 bne.n 8006ca2 <HAL_TIM_IRQHandler+0x20a>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
8006c92: 687b ldr r3, [r7, #4]
8006c94: 681b ldr r3, [r3, #0]
8006c96: f06f 0240 mvn.w r2, #64 ; 0x40
8006c9a: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
8006c9c: 6878 ldr r0, [r7, #4]
8006c9e: f000 fab1 bl 8007204 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
8006ca2: 687b ldr r3, [r7, #4]
8006ca4: 681b ldr r3, [r3, #0]
8006ca6: 691b ldr r3, [r3, #16]
8006ca8: f003 0320 and.w r3, r3, #32
8006cac: 2b20 cmp r3, #32
8006cae: d10e bne.n 8006cce <HAL_TIM_IRQHandler+0x236>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
8006cb0: 687b ldr r3, [r7, #4]
8006cb2: 681b ldr r3, [r3, #0]
8006cb4: 68db ldr r3, [r3, #12]
8006cb6: f003 0320 and.w r3, r3, #32
8006cba: 2b20 cmp r3, #32
8006cbc: d107 bne.n 8006cce <HAL_TIM_IRQHandler+0x236>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
8006cbe: 687b ldr r3, [r7, #4]
8006cc0: 681b ldr r3, [r3, #0]
8006cc2: f06f 0220 mvn.w r2, #32
8006cc6: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8006cc8: 6878 ldr r0, [r7, #4]
8006cca: f000 ff6f bl 8007bac <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Encoder index event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_IDX) != RESET)
8006cce: 687b ldr r3, [r7, #4]
8006cd0: 681b ldr r3, [r3, #0]
8006cd2: 691b ldr r3, [r3, #16]
8006cd4: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8006cd8: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
8006cdc: d10f bne.n 8006cfe <HAL_TIM_IRQHandler+0x266>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_IDX) != RESET)
8006cde: 687b ldr r3, [r7, #4]
8006ce0: 681b ldr r3, [r3, #0]
8006ce2: 68db ldr r3, [r3, #12]
8006ce4: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8006ce8: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
8006cec: d107 bne.n 8006cfe <HAL_TIM_IRQHandler+0x266>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IDX);
8006cee: 687b ldr r3, [r7, #4]
8006cf0: 681b ldr r3, [r3, #0]
8006cf2: f46f 1280 mvn.w r2, #1048576 ; 0x100000
8006cf6: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->EncoderIndexCallback(htim);
#else
HAL_TIMEx_EncoderIndexCallback(htim);
8006cf8: 6878 ldr r0, [r7, #4]
8006cfa: f000 ff75 bl 8007be8 <HAL_TIMEx_EncoderIndexCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Direction change event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_DIR) != RESET)
8006cfe: 687b ldr r3, [r7, #4]
8006d00: 681b ldr r3, [r3, #0]
8006d02: 691b ldr r3, [r3, #16]
8006d04: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8006d08: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000
8006d0c: d10f bne.n 8006d2e <HAL_TIM_IRQHandler+0x296>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_DIR) != RESET)
8006d0e: 687b ldr r3, [r7, #4]
8006d10: 681b ldr r3, [r3, #0]
8006d12: 68db ldr r3, [r3, #12]
8006d14: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8006d18: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000
8006d1c: d107 bne.n 8006d2e <HAL_TIM_IRQHandler+0x296>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_DIR);
8006d1e: 687b ldr r3, [r7, #4]
8006d20: 681b ldr r3, [r3, #0]
8006d22: f46f 1200 mvn.w r2, #2097152 ; 0x200000
8006d26: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->DirectionChangeCallback(htim);
#else
HAL_TIMEx_DirectionChangeCallback(htim);
8006d28: 6878 ldr r0, [r7, #4]
8006d2a: f000 ff67 bl 8007bfc <HAL_TIMEx_DirectionChangeCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Index error event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_IERR) != RESET)
8006d2e: 687b ldr r3, [r7, #4]
8006d30: 681b ldr r3, [r3, #0]
8006d32: 691b ldr r3, [r3, #16]
8006d34: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8006d38: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
8006d3c: d10f bne.n 8006d5e <HAL_TIM_IRQHandler+0x2c6>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_IERR) != RESET)
8006d3e: 687b ldr r3, [r7, #4]
8006d40: 681b ldr r3, [r3, #0]
8006d42: 68db ldr r3, [r3, #12]
8006d44: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8006d48: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
8006d4c: d107 bne.n 8006d5e <HAL_TIM_IRQHandler+0x2c6>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IERR);
8006d4e: 687b ldr r3, [r7, #4]
8006d50: 681b ldr r3, [r3, #0]
8006d52: f46f 0280 mvn.w r2, #4194304 ; 0x400000
8006d56: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IndexErrorCallback(htim);
#else
HAL_TIMEx_IndexErrorCallback(htim);
8006d58: 6878 ldr r0, [r7, #4]
8006d5a: f000 ff59 bl 8007c10 <HAL_TIMEx_IndexErrorCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Transition error event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TERR) != RESET)
8006d5e: 687b ldr r3, [r7, #4]
8006d60: 681b ldr r3, [r3, #0]
8006d62: 691b ldr r3, [r3, #16]
8006d64: f403 0300 and.w r3, r3, #8388608 ; 0x800000
8006d68: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000
8006d6c: d10f bne.n 8006d8e <HAL_TIM_IRQHandler+0x2f6>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TERR) != RESET)
8006d6e: 687b ldr r3, [r7, #4]
8006d70: 681b ldr r3, [r3, #0]
8006d72: 68db ldr r3, [r3, #12]
8006d74: f403 0300 and.w r3, r3, #8388608 ; 0x800000
8006d78: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000
8006d7c: d107 bne.n 8006d8e <HAL_TIM_IRQHandler+0x2f6>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_TERR);
8006d7e: 687b ldr r3, [r7, #4]
8006d80: 681b ldr r3, [r3, #0]
8006d82: f46f 0200 mvn.w r2, #8388608 ; 0x800000
8006d86: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TransitionErrorCallback(htim);
#else
HAL_TIMEx_TransitionErrorCallback(htim);
8006d88: 6878 ldr r0, [r7, #4]
8006d8a: f000 ff4b bl 8007c24 <HAL_TIMEx_TransitionErrorCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8006d8e: bf00 nop
8006d90: 3708 adds r7, #8
8006d92: 46bd mov sp, r7
8006d94: bd80 pop {r7, pc}
...
08006d98 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8006d98: b580 push {r7, lr}
8006d9a: b086 sub sp, #24
8006d9c: af00 add r7, sp, #0
8006d9e: 60f8 str r0, [r7, #12]
8006da0: 60b9 str r1, [r7, #8]
8006da2: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8006da4: 2300 movs r3, #0
8006da6: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
8006da8: 68fb ldr r3, [r7, #12]
8006daa: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8006dae: 2b01 cmp r3, #1
8006db0: d101 bne.n 8006db6 <HAL_TIM_PWM_ConfigChannel+0x1e>
8006db2: 2302 movs r3, #2
8006db4: e0ff b.n 8006fb6 <HAL_TIM_PWM_ConfigChannel+0x21e>
8006db6: 68fb ldr r3, [r7, #12]
8006db8: 2201 movs r2, #1
8006dba: f883 203c strb.w r2, [r3, #60] ; 0x3c
switch (Channel)
8006dbe: 687b ldr r3, [r7, #4]
8006dc0: 2b14 cmp r3, #20
8006dc2: f200 80f0 bhi.w 8006fa6 <HAL_TIM_PWM_ConfigChannel+0x20e>
8006dc6: a201 add r2, pc, #4 ; (adr r2, 8006dcc <HAL_TIM_PWM_ConfigChannel+0x34>)
8006dc8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8006dcc: 08006e21 .word 0x08006e21
8006dd0: 08006fa7 .word 0x08006fa7
8006dd4: 08006fa7 .word 0x08006fa7
8006dd8: 08006fa7 .word 0x08006fa7
8006ddc: 08006e61 .word 0x08006e61
8006de0: 08006fa7 .word 0x08006fa7
8006de4: 08006fa7 .word 0x08006fa7
8006de8: 08006fa7 .word 0x08006fa7
8006dec: 08006ea3 .word 0x08006ea3
8006df0: 08006fa7 .word 0x08006fa7
8006df4: 08006fa7 .word 0x08006fa7
8006df8: 08006fa7 .word 0x08006fa7
8006dfc: 08006ee3 .word 0x08006ee3
8006e00: 08006fa7 .word 0x08006fa7
8006e04: 08006fa7 .word 0x08006fa7
8006e08: 08006fa7 .word 0x08006fa7
8006e0c: 08006f25 .word 0x08006f25
8006e10: 08006fa7 .word 0x08006fa7
8006e14: 08006fa7 .word 0x08006fa7
8006e18: 08006fa7 .word 0x08006fa7
8006e1c: 08006f65 .word 0x08006f65
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8006e20: 68fb ldr r3, [r7, #12]
8006e22: 681b ldr r3, [r3, #0]
8006e24: 68b9 ldr r1, [r7, #8]
8006e26: 4618 mov r0, r3
8006e28: f000 fa86 bl 8007338 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8006e2c: 68fb ldr r3, [r7, #12]
8006e2e: 681b ldr r3, [r3, #0]
8006e30: 699a ldr r2, [r3, #24]
8006e32: 68fb ldr r3, [r7, #12]
8006e34: 681b ldr r3, [r3, #0]
8006e36: f042 0208 orr.w r2, r2, #8
8006e3a: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8006e3c: 68fb ldr r3, [r7, #12]
8006e3e: 681b ldr r3, [r3, #0]
8006e40: 699a ldr r2, [r3, #24]
8006e42: 68fb ldr r3, [r7, #12]
8006e44: 681b ldr r3, [r3, #0]
8006e46: f022 0204 bic.w r2, r2, #4
8006e4a: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8006e4c: 68fb ldr r3, [r7, #12]
8006e4e: 681b ldr r3, [r3, #0]
8006e50: 6999 ldr r1, [r3, #24]
8006e52: 68bb ldr r3, [r7, #8]
8006e54: 691a ldr r2, [r3, #16]
8006e56: 68fb ldr r3, [r7, #12]
8006e58: 681b ldr r3, [r3, #0]
8006e5a: 430a orrs r2, r1
8006e5c: 619a str r2, [r3, #24]
break;
8006e5e: e0a5 b.n 8006fac <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8006e60: 68fb ldr r3, [r7, #12]
8006e62: 681b ldr r3, [r3, #0]
8006e64: 68b9 ldr r1, [r7, #8]
8006e66: 4618 mov r0, r3
8006e68: f000 faf6 bl 8007458 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8006e6c: 68fb ldr r3, [r7, #12]
8006e6e: 681b ldr r3, [r3, #0]
8006e70: 699a ldr r2, [r3, #24]
8006e72: 68fb ldr r3, [r7, #12]
8006e74: 681b ldr r3, [r3, #0]
8006e76: f442 6200 orr.w r2, r2, #2048 ; 0x800
8006e7a: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8006e7c: 68fb ldr r3, [r7, #12]
8006e7e: 681b ldr r3, [r3, #0]
8006e80: 699a ldr r2, [r3, #24]
8006e82: 68fb ldr r3, [r7, #12]
8006e84: 681b ldr r3, [r3, #0]
8006e86: f422 6280 bic.w r2, r2, #1024 ; 0x400
8006e8a: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8006e8c: 68fb ldr r3, [r7, #12]
8006e8e: 681b ldr r3, [r3, #0]
8006e90: 6999 ldr r1, [r3, #24]
8006e92: 68bb ldr r3, [r7, #8]
8006e94: 691b ldr r3, [r3, #16]
8006e96: 021a lsls r2, r3, #8
8006e98: 68fb ldr r3, [r7, #12]
8006e9a: 681b ldr r3, [r3, #0]
8006e9c: 430a orrs r2, r1
8006e9e: 619a str r2, [r3, #24]
break;
8006ea0: e084 b.n 8006fac <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
8006ea2: 68fb ldr r3, [r7, #12]
8006ea4: 681b ldr r3, [r3, #0]
8006ea6: 68b9 ldr r1, [r7, #8]
8006ea8: 4618 mov r0, r3
8006eaa: f000 fb5f bl 800756c <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
8006eae: 68fb ldr r3, [r7, #12]
8006eb0: 681b ldr r3, [r3, #0]
8006eb2: 69da ldr r2, [r3, #28]
8006eb4: 68fb ldr r3, [r7, #12]
8006eb6: 681b ldr r3, [r3, #0]
8006eb8: f042 0208 orr.w r2, r2, #8
8006ebc: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
8006ebe: 68fb ldr r3, [r7, #12]
8006ec0: 681b ldr r3, [r3, #0]
8006ec2: 69da ldr r2, [r3, #28]
8006ec4: 68fb ldr r3, [r7, #12]
8006ec6: 681b ldr r3, [r3, #0]
8006ec8: f022 0204 bic.w r2, r2, #4
8006ecc: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
8006ece: 68fb ldr r3, [r7, #12]
8006ed0: 681b ldr r3, [r3, #0]
8006ed2: 69d9 ldr r1, [r3, #28]
8006ed4: 68bb ldr r3, [r7, #8]
8006ed6: 691a ldr r2, [r3, #16]
8006ed8: 68fb ldr r3, [r7, #12]
8006eda: 681b ldr r3, [r3, #0]
8006edc: 430a orrs r2, r1
8006ede: 61da str r2, [r3, #28]
break;
8006ee0: e064 b.n 8006fac <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8006ee2: 68fb ldr r3, [r7, #12]
8006ee4: 681b ldr r3, [r3, #0]
8006ee6: 68b9 ldr r1, [r7, #8]
8006ee8: 4618 mov r0, r3
8006eea: f000 fbc7 bl 800767c <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
8006eee: 68fb ldr r3, [r7, #12]
8006ef0: 681b ldr r3, [r3, #0]
8006ef2: 69da ldr r2, [r3, #28]
8006ef4: 68fb ldr r3, [r7, #12]
8006ef6: 681b ldr r3, [r3, #0]
8006ef8: f442 6200 orr.w r2, r2, #2048 ; 0x800
8006efc: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
8006efe: 68fb ldr r3, [r7, #12]
8006f00: 681b ldr r3, [r3, #0]
8006f02: 69da ldr r2, [r3, #28]
8006f04: 68fb ldr r3, [r7, #12]
8006f06: 681b ldr r3, [r3, #0]
8006f08: f422 6280 bic.w r2, r2, #1024 ; 0x400
8006f0c: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
8006f0e: 68fb ldr r3, [r7, #12]
8006f10: 681b ldr r3, [r3, #0]
8006f12: 69d9 ldr r1, [r3, #28]
8006f14: 68bb ldr r3, [r7, #8]
8006f16: 691b ldr r3, [r3, #16]
8006f18: 021a lsls r2, r3, #8
8006f1a: 68fb ldr r3, [r7, #12]
8006f1c: 681b ldr r3, [r3, #0]
8006f1e: 430a orrs r2, r1
8006f20: 61da str r2, [r3, #28]
break;
8006f22: e043 b.n 8006fac <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
/* Configure the Channel 5 in PWM mode */
TIM_OC5_SetConfig(htim->Instance, sConfig);
8006f24: 68fb ldr r3, [r7, #12]
8006f26: 681b ldr r3, [r3, #0]
8006f28: 68b9 ldr r1, [r7, #8]
8006f2a: 4618 mov r0, r3
8006f2c: f000 fc30 bl 8007790 <TIM_OC5_SetConfig>
/* Set the Preload enable bit for channel5*/
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
8006f30: 68fb ldr r3, [r7, #12]
8006f32: 681b ldr r3, [r3, #0]
8006f34: 6d1a ldr r2, [r3, #80] ; 0x50
8006f36: 68fb ldr r3, [r7, #12]
8006f38: 681b ldr r3, [r3, #0]
8006f3a: f042 0208 orr.w r2, r2, #8
8006f3e: 651a str r2, [r3, #80] ; 0x50
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
8006f40: 68fb ldr r3, [r7, #12]
8006f42: 681b ldr r3, [r3, #0]
8006f44: 6d1a ldr r2, [r3, #80] ; 0x50
8006f46: 68fb ldr r3, [r7, #12]
8006f48: 681b ldr r3, [r3, #0]
8006f4a: f022 0204 bic.w r2, r2, #4
8006f4e: 651a str r2, [r3, #80] ; 0x50
htim->Instance->CCMR3 |= sConfig->OCFastMode;
8006f50: 68fb ldr r3, [r7, #12]
8006f52: 681b ldr r3, [r3, #0]
8006f54: 6d19 ldr r1, [r3, #80] ; 0x50
8006f56: 68bb ldr r3, [r7, #8]
8006f58: 691a ldr r2, [r3, #16]
8006f5a: 68fb ldr r3, [r7, #12]
8006f5c: 681b ldr r3, [r3, #0]
8006f5e: 430a orrs r2, r1
8006f60: 651a str r2, [r3, #80] ; 0x50
break;
8006f62: e023 b.n 8006fac <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
/* Configure the Channel 6 in PWM mode */
TIM_OC6_SetConfig(htim->Instance, sConfig);
8006f64: 68fb ldr r3, [r7, #12]
8006f66: 681b ldr r3, [r3, #0]
8006f68: 68b9 ldr r1, [r7, #8]
8006f6a: 4618 mov r0, r3
8006f6c: f000 fc74 bl 8007858 <TIM_OC6_SetConfig>
/* Set the Preload enable bit for channel6 */
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
8006f70: 68fb ldr r3, [r7, #12]
8006f72: 681b ldr r3, [r3, #0]
8006f74: 6d1a ldr r2, [r3, #80] ; 0x50
8006f76: 68fb ldr r3, [r7, #12]
8006f78: 681b ldr r3, [r3, #0]
8006f7a: f442 6200 orr.w r2, r2, #2048 ; 0x800
8006f7e: 651a str r2, [r3, #80] ; 0x50
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
8006f80: 68fb ldr r3, [r7, #12]
8006f82: 681b ldr r3, [r3, #0]
8006f84: 6d1a ldr r2, [r3, #80] ; 0x50
8006f86: 68fb ldr r3, [r7, #12]
8006f88: 681b ldr r3, [r3, #0]
8006f8a: f422 6280 bic.w r2, r2, #1024 ; 0x400
8006f8e: 651a str r2, [r3, #80] ; 0x50
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
8006f90: 68fb ldr r3, [r7, #12]
8006f92: 681b ldr r3, [r3, #0]
8006f94: 6d19 ldr r1, [r3, #80] ; 0x50
8006f96: 68bb ldr r3, [r7, #8]
8006f98: 691b ldr r3, [r3, #16]
8006f9a: 021a lsls r2, r3, #8
8006f9c: 68fb ldr r3, [r7, #12]
8006f9e: 681b ldr r3, [r3, #0]
8006fa0: 430a orrs r2, r1
8006fa2: 651a str r2, [r3, #80] ; 0x50
break;
8006fa4: e002 b.n 8006fac <HAL_TIM_PWM_ConfigChannel+0x214>
}
default:
status = HAL_ERROR;
8006fa6: 2301 movs r3, #1
8006fa8: 75fb strb r3, [r7, #23]
break;
8006faa: bf00 nop
}
__HAL_UNLOCK(htim);
8006fac: 68fb ldr r3, [r7, #12]
8006fae: 2200 movs r2, #0
8006fb0: f883 203c strb.w r2, [r3, #60] ; 0x3c
return status;
8006fb4: 7dfb ldrb r3, [r7, #23]
}
8006fb6: 4618 mov r0, r3
8006fb8: 3718 adds r7, #24
8006fba: 46bd mov sp, r7
8006fbc: bd80 pop {r7, pc}
8006fbe: bf00 nop
08006fc0 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
{
8006fc0: b580 push {r7, lr}
8006fc2: b084 sub sp, #16
8006fc4: af00 add r7, sp, #0
8006fc6: 6078 str r0, [r7, #4]
8006fc8: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
8006fca: 2300 movs r3, #0
8006fcc: 73fb strb r3, [r7, #15]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
8006fce: 687b ldr r3, [r7, #4]
8006fd0: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8006fd4: 2b01 cmp r3, #1
8006fd6: d101 bne.n 8006fdc <HAL_TIM_ConfigClockSource+0x1c>
8006fd8: 2302 movs r3, #2
8006fda: e0de b.n 800719a <HAL_TIM_ConfigClockSource+0x1da>
8006fdc: 687b ldr r3, [r7, #4]
8006fde: 2201 movs r2, #1
8006fe0: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
8006fe4: 687b ldr r3, [r7, #4]
8006fe6: 2202 movs r2, #2
8006fe8: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
8006fec: 687b ldr r3, [r7, #4]
8006fee: 681b ldr r3, [r3, #0]
8006ff0: 689b ldr r3, [r3, #8]
8006ff2: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
8006ff4: 68bb ldr r3, [r7, #8]
8006ff6: f423 1344 bic.w r3, r3, #3211264 ; 0x310000
8006ffa: f023 0377 bic.w r3, r3, #119 ; 0x77
8006ffe: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8007000: 68bb ldr r3, [r7, #8]
8007002: f423 437f bic.w r3, r3, #65280 ; 0xff00
8007006: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
8007008: 687b ldr r3, [r7, #4]
800700a: 681b ldr r3, [r3, #0]
800700c: 68ba ldr r2, [r7, #8]
800700e: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
8007010: 683b ldr r3, [r7, #0]
8007012: 681b ldr r3, [r3, #0]
8007014: 4a63 ldr r2, [pc, #396] ; (80071a4 <HAL_TIM_ConfigClockSource+0x1e4>)
8007016: 4293 cmp r3, r2
8007018: f000 80a9 beq.w 800716e <HAL_TIM_ConfigClockSource+0x1ae>
800701c: 4a61 ldr r2, [pc, #388] ; (80071a4 <HAL_TIM_ConfigClockSource+0x1e4>)
800701e: 4293 cmp r3, r2
8007020: f200 80ae bhi.w 8007180 <HAL_TIM_ConfigClockSource+0x1c0>
8007024: 4a60 ldr r2, [pc, #384] ; (80071a8 <HAL_TIM_ConfigClockSource+0x1e8>)
8007026: 4293 cmp r3, r2
8007028: f000 80a1 beq.w 800716e <HAL_TIM_ConfigClockSource+0x1ae>
800702c: 4a5e ldr r2, [pc, #376] ; (80071a8 <HAL_TIM_ConfigClockSource+0x1e8>)
800702e: 4293 cmp r3, r2
8007030: f200 80a6 bhi.w 8007180 <HAL_TIM_ConfigClockSource+0x1c0>
8007034: 4a5d ldr r2, [pc, #372] ; (80071ac <HAL_TIM_ConfigClockSource+0x1ec>)
8007036: 4293 cmp r3, r2
8007038: f000 8099 beq.w 800716e <HAL_TIM_ConfigClockSource+0x1ae>
800703c: 4a5b ldr r2, [pc, #364] ; (80071ac <HAL_TIM_ConfigClockSource+0x1ec>)
800703e: 4293 cmp r3, r2
8007040: f200 809e bhi.w 8007180 <HAL_TIM_ConfigClockSource+0x1c0>
8007044: 4a5a ldr r2, [pc, #360] ; (80071b0 <HAL_TIM_ConfigClockSource+0x1f0>)
8007046: 4293 cmp r3, r2
8007048: f000 8091 beq.w 800716e <HAL_TIM_ConfigClockSource+0x1ae>
800704c: 4a58 ldr r2, [pc, #352] ; (80071b0 <HAL_TIM_ConfigClockSource+0x1f0>)
800704e: 4293 cmp r3, r2
8007050: f200 8096 bhi.w 8007180 <HAL_TIM_ConfigClockSource+0x1c0>
8007054: f1b3 1f10 cmp.w r3, #1048592 ; 0x100010
8007058: f000 8089 beq.w 800716e <HAL_TIM_ConfigClockSource+0x1ae>
800705c: f1b3 1f10 cmp.w r3, #1048592 ; 0x100010
8007060: f200 808e bhi.w 8007180 <HAL_TIM_ConfigClockSource+0x1c0>
8007064: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
8007068: d03e beq.n 80070e8 <HAL_TIM_ConfigClockSource+0x128>
800706a: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
800706e: f200 8087 bhi.w 8007180 <HAL_TIM_ConfigClockSource+0x1c0>
8007072: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8007076: f000 8086 beq.w 8007186 <HAL_TIM_ConfigClockSource+0x1c6>
800707a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
800707e: d87f bhi.n 8007180 <HAL_TIM_ConfigClockSource+0x1c0>
8007080: 2b70 cmp r3, #112 ; 0x70
8007082: d01a beq.n 80070ba <HAL_TIM_ConfigClockSource+0xfa>
8007084: 2b70 cmp r3, #112 ; 0x70
8007086: d87b bhi.n 8007180 <HAL_TIM_ConfigClockSource+0x1c0>
8007088: 2b60 cmp r3, #96 ; 0x60
800708a: d050 beq.n 800712e <HAL_TIM_ConfigClockSource+0x16e>
800708c: 2b60 cmp r3, #96 ; 0x60
800708e: d877 bhi.n 8007180 <HAL_TIM_ConfigClockSource+0x1c0>
8007090: 2b50 cmp r3, #80 ; 0x50
8007092: d03c beq.n 800710e <HAL_TIM_ConfigClockSource+0x14e>
8007094: 2b50 cmp r3, #80 ; 0x50
8007096: d873 bhi.n 8007180 <HAL_TIM_ConfigClockSource+0x1c0>
8007098: 2b40 cmp r3, #64 ; 0x40
800709a: d058 beq.n 800714e <HAL_TIM_ConfigClockSource+0x18e>
800709c: 2b40 cmp r3, #64 ; 0x40
800709e: d86f bhi.n 8007180 <HAL_TIM_ConfigClockSource+0x1c0>
80070a0: 2b30 cmp r3, #48 ; 0x30
80070a2: d064 beq.n 800716e <HAL_TIM_ConfigClockSource+0x1ae>
80070a4: 2b30 cmp r3, #48 ; 0x30
80070a6: d86b bhi.n 8007180 <HAL_TIM_ConfigClockSource+0x1c0>
80070a8: 2b20 cmp r3, #32
80070aa: d060 beq.n 800716e <HAL_TIM_ConfigClockSource+0x1ae>
80070ac: 2b20 cmp r3, #32
80070ae: d867 bhi.n 8007180 <HAL_TIM_ConfigClockSource+0x1c0>
80070b0: 2b00 cmp r3, #0
80070b2: d05c beq.n 800716e <HAL_TIM_ConfigClockSource+0x1ae>
80070b4: 2b10 cmp r3, #16
80070b6: d05a beq.n 800716e <HAL_TIM_ConfigClockSource+0x1ae>
80070b8: e062 b.n 8007180 <HAL_TIM_ConfigClockSource+0x1c0>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
80070ba: 687b ldr r3, [r7, #4]
80070bc: 6818 ldr r0, [r3, #0]
80070be: 683b ldr r3, [r7, #0]
80070c0: 6899 ldr r1, [r3, #8]
80070c2: 683b ldr r3, [r7, #0]
80070c4: 685a ldr r2, [r3, #4]
80070c6: 683b ldr r3, [r7, #0]
80070c8: 68db ldr r3, [r3, #12]
80070ca: f000 fca7 bl 8007a1c <TIM_ETR_SetConfig>
sClockSourceConfig->ClockPrescaler,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
80070ce: 687b ldr r3, [r7, #4]
80070d0: 681b ldr r3, [r3, #0]
80070d2: 689b ldr r3, [r3, #8]
80070d4: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
80070d6: 68bb ldr r3, [r7, #8]
80070d8: f043 0377 orr.w r3, r3, #119 ; 0x77
80070dc: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
80070de: 687b ldr r3, [r7, #4]
80070e0: 681b ldr r3, [r3, #0]
80070e2: 68ba ldr r2, [r7, #8]
80070e4: 609a str r2, [r3, #8]
break;
80070e6: e04f b.n 8007188 <HAL_TIM_ConfigClockSource+0x1c8>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
80070e8: 687b ldr r3, [r7, #4]
80070ea: 6818 ldr r0, [r3, #0]
80070ec: 683b ldr r3, [r7, #0]
80070ee: 6899 ldr r1, [r3, #8]
80070f0: 683b ldr r3, [r7, #0]
80070f2: 685a ldr r2, [r3, #4]
80070f4: 683b ldr r3, [r7, #0]
80070f6: 68db ldr r3, [r3, #12]
80070f8: f000 fc90 bl 8007a1c <TIM_ETR_SetConfig>
sClockSourceConfig->ClockPrescaler,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
80070fc: 687b ldr r3, [r7, #4]
80070fe: 681b ldr r3, [r3, #0]
8007100: 689a ldr r2, [r3, #8]
8007102: 687b ldr r3, [r7, #4]
8007104: 681b ldr r3, [r3, #0]
8007106: f442 4280 orr.w r2, r2, #16384 ; 0x4000
800710a: 609a str r2, [r3, #8]
break;
800710c: e03c b.n 8007188 <HAL_TIM_ConfigClockSource+0x1c8>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
800710e: 687b ldr r3, [r7, #4]
8007110: 6818 ldr r0, [r3, #0]
8007112: 683b ldr r3, [r7, #0]
8007114: 6859 ldr r1, [r3, #4]
8007116: 683b ldr r3, [r7, #0]
8007118: 68db ldr r3, [r3, #12]
800711a: 461a mov r2, r3
800711c: f000 fc02 bl 8007924 <TIM_TI1_ConfigInputStage>
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
8007120: 687b ldr r3, [r7, #4]
8007122: 681b ldr r3, [r3, #0]
8007124: 2150 movs r1, #80 ; 0x50
8007126: 4618 mov r0, r3
8007128: f000 fc5b bl 80079e2 <TIM_ITRx_SetConfig>
break;
800712c: e02c b.n 8007188 <HAL_TIM_ConfigClockSource+0x1c8>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
800712e: 687b ldr r3, [r7, #4]
8007130: 6818 ldr r0, [r3, #0]
8007132: 683b ldr r3, [r7, #0]
8007134: 6859 ldr r1, [r3, #4]
8007136: 683b ldr r3, [r7, #0]
8007138: 68db ldr r3, [r3, #12]
800713a: 461a mov r2, r3
800713c: f000 fc21 bl 8007982 <TIM_TI2_ConfigInputStage>
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
8007140: 687b ldr r3, [r7, #4]
8007142: 681b ldr r3, [r3, #0]
8007144: 2160 movs r1, #96 ; 0x60
8007146: 4618 mov r0, r3
8007148: f000 fc4b bl 80079e2 <TIM_ITRx_SetConfig>
break;
800714c: e01c b.n 8007188 <HAL_TIM_ConfigClockSource+0x1c8>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
800714e: 687b ldr r3, [r7, #4]
8007150: 6818 ldr r0, [r3, #0]
8007152: 683b ldr r3, [r7, #0]
8007154: 6859 ldr r1, [r3, #4]
8007156: 683b ldr r3, [r7, #0]
8007158: 68db ldr r3, [r3, #12]
800715a: 461a mov r2, r3
800715c: f000 fbe2 bl 8007924 <TIM_TI1_ConfigInputStage>
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
8007160: 687b ldr r3, [r7, #4]
8007162: 681b ldr r3, [r3, #0]
8007164: 2140 movs r1, #64 ; 0x40
8007166: 4618 mov r0, r3
8007168: f000 fc3b bl 80079e2 <TIM_ITRx_SetConfig>
break;
800716c: e00c b.n 8007188 <HAL_TIM_ConfigClockSource+0x1c8>
case TIM_CLOCKSOURCE_ITR11:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
800716e: 687b ldr r3, [r7, #4]
8007170: 681a ldr r2, [r3, #0]
8007172: 683b ldr r3, [r7, #0]
8007174: 681b ldr r3, [r3, #0]
8007176: 4619 mov r1, r3
8007178: 4610 mov r0, r2
800717a: f000 fc32 bl 80079e2 <TIM_ITRx_SetConfig>
break;
800717e: e003 b.n 8007188 <HAL_TIM_ConfigClockSource+0x1c8>
}
default:
status = HAL_ERROR;
8007180: 2301 movs r3, #1
8007182: 73fb strb r3, [r7, #15]
break;
8007184: e000 b.n 8007188 <HAL_TIM_ConfigClockSource+0x1c8>
break;
8007186: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
8007188: 687b ldr r3, [r7, #4]
800718a: 2201 movs r2, #1
800718c: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
8007190: 687b ldr r3, [r7, #4]
8007192: 2200 movs r2, #0
8007194: f883 203c strb.w r2, [r3, #60] ; 0x3c
return status;
8007198: 7bfb ldrb r3, [r7, #15]
}
800719a: 4618 mov r0, r3
800719c: 3710 adds r7, #16
800719e: 46bd mov sp, r7
80071a0: bd80 pop {r7, pc}
80071a2: bf00 nop
80071a4: 00100070 .word 0x00100070
80071a8: 00100040 .word 0x00100040
80071ac: 00100030 .word 0x00100030
80071b0: 00100020 .word 0x00100020
080071b4 <HAL_TIM_PeriodElapsedCallback>:
* @brief Period elapsed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
80071b4: b480 push {r7}
80071b6: b083 sub sp, #12
80071b8: af00 add r7, sp, #0
80071ba: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
*/
}
80071bc: bf00 nop
80071be: 370c adds r7, #12
80071c0: 46bd mov sp, r7
80071c2: f85d 7b04 ldr.w r7, [sp], #4
80071c6: 4770 bx lr
080071c8 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
80071c8: b480 push {r7}
80071ca: b083 sub sp, #12
80071cc: af00 add r7, sp, #0
80071ce: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
80071d0: bf00 nop
80071d2: 370c adds r7, #12
80071d4: 46bd mov sp, r7
80071d6: f85d 7b04 ldr.w r7, [sp], #4
80071da: 4770 bx lr
080071dc <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
80071dc: b480 push {r7}
80071de: b083 sub sp, #12
80071e0: af00 add r7, sp, #0
80071e2: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
80071e4: bf00 nop
80071e6: 370c adds r7, #12
80071e8: 46bd mov sp, r7
80071ea: f85d 7b04 ldr.w r7, [sp], #4
80071ee: 4770 bx lr
080071f0 <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
80071f0: b480 push {r7}
80071f2: b083 sub sp, #12
80071f4: af00 add r7, sp, #0
80071f6: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
80071f8: bf00 nop
80071fa: 370c adds r7, #12
80071fc: 46bd mov sp, r7
80071fe: f85d 7b04 ldr.w r7, [sp], #4
8007202: 4770 bx lr
08007204 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
8007204: b480 push {r7}
8007206: b083 sub sp, #12
8007208: af00 add r7, sp, #0
800720a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
800720c: bf00 nop
800720e: 370c adds r7, #12
8007210: 46bd mov sp, r7
8007212: f85d 7b04 ldr.w r7, [sp], #4
8007216: 4770 bx lr
08007218 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
8007218: b480 push {r7}
800721a: b085 sub sp, #20
800721c: af00 add r7, sp, #0
800721e: 6078 str r0, [r7, #4]
8007220: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8007222: 687b ldr r3, [r7, #4]
8007224: 681b ldr r3, [r3, #0]
8007226: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8007228: 687b ldr r3, [r7, #4]
800722a: 4a3c ldr r2, [pc, #240] ; (800731c <TIM_Base_SetConfig+0x104>)
800722c: 4293 cmp r3, r2
800722e: d00f beq.n 8007250 <TIM_Base_SetConfig+0x38>
8007230: 687b ldr r3, [r7, #4]
8007232: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8007236: d00b beq.n 8007250 <TIM_Base_SetConfig+0x38>
8007238: 687b ldr r3, [r7, #4]
800723a: 4a39 ldr r2, [pc, #228] ; (8007320 <TIM_Base_SetConfig+0x108>)
800723c: 4293 cmp r3, r2
800723e: d007 beq.n 8007250 <TIM_Base_SetConfig+0x38>
8007240: 687b ldr r3, [r7, #4]
8007242: 4a38 ldr r2, [pc, #224] ; (8007324 <TIM_Base_SetConfig+0x10c>)
8007244: 4293 cmp r3, r2
8007246: d003 beq.n 8007250 <TIM_Base_SetConfig+0x38>
8007248: 687b ldr r3, [r7, #4]
800724a: 4a37 ldr r2, [pc, #220] ; (8007328 <TIM_Base_SetConfig+0x110>)
800724c: 4293 cmp r3, r2
800724e: d108 bne.n 8007262 <TIM_Base_SetConfig+0x4a>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8007250: 68fb ldr r3, [r7, #12]
8007252: f023 0370 bic.w r3, r3, #112 ; 0x70
8007256: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8007258: 683b ldr r3, [r7, #0]
800725a: 685b ldr r3, [r3, #4]
800725c: 68fa ldr r2, [r7, #12]
800725e: 4313 orrs r3, r2
8007260: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8007262: 687b ldr r3, [r7, #4]
8007264: 4a2d ldr r2, [pc, #180] ; (800731c <TIM_Base_SetConfig+0x104>)
8007266: 4293 cmp r3, r2
8007268: d01b beq.n 80072a2 <TIM_Base_SetConfig+0x8a>
800726a: 687b ldr r3, [r7, #4]
800726c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8007270: d017 beq.n 80072a2 <TIM_Base_SetConfig+0x8a>
8007272: 687b ldr r3, [r7, #4]
8007274: 4a2a ldr r2, [pc, #168] ; (8007320 <TIM_Base_SetConfig+0x108>)
8007276: 4293 cmp r3, r2
8007278: d013 beq.n 80072a2 <TIM_Base_SetConfig+0x8a>
800727a: 687b ldr r3, [r7, #4]
800727c: 4a29 ldr r2, [pc, #164] ; (8007324 <TIM_Base_SetConfig+0x10c>)
800727e: 4293 cmp r3, r2
8007280: d00f beq.n 80072a2 <TIM_Base_SetConfig+0x8a>
8007282: 687b ldr r3, [r7, #4]
8007284: 4a28 ldr r2, [pc, #160] ; (8007328 <TIM_Base_SetConfig+0x110>)
8007286: 4293 cmp r3, r2
8007288: d00b beq.n 80072a2 <TIM_Base_SetConfig+0x8a>
800728a: 687b ldr r3, [r7, #4]
800728c: 4a27 ldr r2, [pc, #156] ; (800732c <TIM_Base_SetConfig+0x114>)
800728e: 4293 cmp r3, r2
8007290: d007 beq.n 80072a2 <TIM_Base_SetConfig+0x8a>
8007292: 687b ldr r3, [r7, #4]
8007294: 4a26 ldr r2, [pc, #152] ; (8007330 <TIM_Base_SetConfig+0x118>)
8007296: 4293 cmp r3, r2
8007298: d003 beq.n 80072a2 <TIM_Base_SetConfig+0x8a>
800729a: 687b ldr r3, [r7, #4]
800729c: 4a25 ldr r2, [pc, #148] ; (8007334 <TIM_Base_SetConfig+0x11c>)
800729e: 4293 cmp r3, r2
80072a0: d108 bne.n 80072b4 <TIM_Base_SetConfig+0x9c>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
80072a2: 68fb ldr r3, [r7, #12]
80072a4: f423 7340 bic.w r3, r3, #768 ; 0x300
80072a8: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
80072aa: 683b ldr r3, [r7, #0]
80072ac: 68db ldr r3, [r3, #12]
80072ae: 68fa ldr r2, [r7, #12]
80072b0: 4313 orrs r3, r2
80072b2: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
80072b4: 68fb ldr r3, [r7, #12]
80072b6: f023 0280 bic.w r2, r3, #128 ; 0x80
80072ba: 683b ldr r3, [r7, #0]
80072bc: 695b ldr r3, [r3, #20]
80072be: 4313 orrs r3, r2
80072c0: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
80072c2: 687b ldr r3, [r7, #4]
80072c4: 68fa ldr r2, [r7, #12]
80072c6: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
80072c8: 683b ldr r3, [r7, #0]
80072ca: 689a ldr r2, [r3, #8]
80072cc: 687b ldr r3, [r7, #4]
80072ce: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
80072d0: 683b ldr r3, [r7, #0]
80072d2: 681a ldr r2, [r3, #0]
80072d4: 687b ldr r3, [r7, #4]
80072d6: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
80072d8: 687b ldr r3, [r7, #4]
80072da: 4a10 ldr r2, [pc, #64] ; (800731c <TIM_Base_SetConfig+0x104>)
80072dc: 4293 cmp r3, r2
80072de: d00f beq.n 8007300 <TIM_Base_SetConfig+0xe8>
80072e0: 687b ldr r3, [r7, #4]
80072e2: 4a11 ldr r2, [pc, #68] ; (8007328 <TIM_Base_SetConfig+0x110>)
80072e4: 4293 cmp r3, r2
80072e6: d00b beq.n 8007300 <TIM_Base_SetConfig+0xe8>
80072e8: 687b ldr r3, [r7, #4]
80072ea: 4a10 ldr r2, [pc, #64] ; (800732c <TIM_Base_SetConfig+0x114>)
80072ec: 4293 cmp r3, r2
80072ee: d007 beq.n 8007300 <TIM_Base_SetConfig+0xe8>
80072f0: 687b ldr r3, [r7, #4]
80072f2: 4a0f ldr r2, [pc, #60] ; (8007330 <TIM_Base_SetConfig+0x118>)
80072f4: 4293 cmp r3, r2
80072f6: d003 beq.n 8007300 <TIM_Base_SetConfig+0xe8>
80072f8: 687b ldr r3, [r7, #4]
80072fa: 4a0e ldr r2, [pc, #56] ; (8007334 <TIM_Base_SetConfig+0x11c>)
80072fc: 4293 cmp r3, r2
80072fe: d103 bne.n 8007308 <TIM_Base_SetConfig+0xf0>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8007300: 683b ldr r3, [r7, #0]
8007302: 691a ldr r2, [r3, #16]
8007304: 687b ldr r3, [r7, #4]
8007306: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8007308: 687b ldr r3, [r7, #4]
800730a: 2201 movs r2, #1
800730c: 615a str r2, [r3, #20]
}
800730e: bf00 nop
8007310: 3714 adds r7, #20
8007312: 46bd mov sp, r7
8007314: f85d 7b04 ldr.w r7, [sp], #4
8007318: 4770 bx lr
800731a: bf00 nop
800731c: 40012c00 .word 0x40012c00
8007320: 40000400 .word 0x40000400
8007324: 40000800 .word 0x40000800
8007328: 40013400 .word 0x40013400
800732c: 40014000 .word 0x40014000
8007330: 40014400 .word 0x40014400
8007334: 40014800 .word 0x40014800
08007338 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8007338: b480 push {r7}
800733a: b087 sub sp, #28
800733c: af00 add r7, sp, #0
800733e: 6078 str r0, [r7, #4]
8007340: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
8007342: 687b ldr r3, [r7, #4]
8007344: 6a1b ldr r3, [r3, #32]
8007346: f023 0201 bic.w r2, r3, #1
800734a: 687b ldr r3, [r7, #4]
800734c: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800734e: 687b ldr r3, [r7, #4]
8007350: 6a1b ldr r3, [r3, #32]
8007352: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8007354: 687b ldr r3, [r7, #4]
8007356: 685b ldr r3, [r3, #4]
8007358: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
800735a: 687b ldr r3, [r7, #4]
800735c: 699b ldr r3, [r3, #24]
800735e: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
8007360: 68fb ldr r3, [r7, #12]
8007362: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8007366: f023 0370 bic.w r3, r3, #112 ; 0x70
800736a: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
800736c: 68fb ldr r3, [r7, #12]
800736e: f023 0303 bic.w r3, r3, #3
8007372: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8007374: 683b ldr r3, [r7, #0]
8007376: 681b ldr r3, [r3, #0]
8007378: 68fa ldr r2, [r7, #12]
800737a: 4313 orrs r3, r2
800737c: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
800737e: 697b ldr r3, [r7, #20]
8007380: f023 0302 bic.w r3, r3, #2
8007384: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
8007386: 683b ldr r3, [r7, #0]
8007388: 689b ldr r3, [r3, #8]
800738a: 697a ldr r2, [r7, #20]
800738c: 4313 orrs r3, r2
800738e: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8007390: 687b ldr r3, [r7, #4]
8007392: 4a2c ldr r2, [pc, #176] ; (8007444 <TIM_OC1_SetConfig+0x10c>)
8007394: 4293 cmp r3, r2
8007396: d00f beq.n 80073b8 <TIM_OC1_SetConfig+0x80>
8007398: 687b ldr r3, [r7, #4]
800739a: 4a2b ldr r2, [pc, #172] ; (8007448 <TIM_OC1_SetConfig+0x110>)
800739c: 4293 cmp r3, r2
800739e: d00b beq.n 80073b8 <TIM_OC1_SetConfig+0x80>
80073a0: 687b ldr r3, [r7, #4]
80073a2: 4a2a ldr r2, [pc, #168] ; (800744c <TIM_OC1_SetConfig+0x114>)
80073a4: 4293 cmp r3, r2
80073a6: d007 beq.n 80073b8 <TIM_OC1_SetConfig+0x80>
80073a8: 687b ldr r3, [r7, #4]
80073aa: 4a29 ldr r2, [pc, #164] ; (8007450 <TIM_OC1_SetConfig+0x118>)
80073ac: 4293 cmp r3, r2
80073ae: d003 beq.n 80073b8 <TIM_OC1_SetConfig+0x80>
80073b0: 687b ldr r3, [r7, #4]
80073b2: 4a28 ldr r2, [pc, #160] ; (8007454 <TIM_OC1_SetConfig+0x11c>)
80073b4: 4293 cmp r3, r2
80073b6: d10c bne.n 80073d2 <TIM_OC1_SetConfig+0x9a>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
80073b8: 697b ldr r3, [r7, #20]
80073ba: f023 0308 bic.w r3, r3, #8
80073be: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
80073c0: 683b ldr r3, [r7, #0]
80073c2: 68db ldr r3, [r3, #12]
80073c4: 697a ldr r2, [r7, #20]
80073c6: 4313 orrs r3, r2
80073c8: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
80073ca: 697b ldr r3, [r7, #20]
80073cc: f023 0304 bic.w r3, r3, #4
80073d0: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
80073d2: 687b ldr r3, [r7, #4]
80073d4: 4a1b ldr r2, [pc, #108] ; (8007444 <TIM_OC1_SetConfig+0x10c>)
80073d6: 4293 cmp r3, r2
80073d8: d00f beq.n 80073fa <TIM_OC1_SetConfig+0xc2>
80073da: 687b ldr r3, [r7, #4]
80073dc: 4a1a ldr r2, [pc, #104] ; (8007448 <TIM_OC1_SetConfig+0x110>)
80073de: 4293 cmp r3, r2
80073e0: d00b beq.n 80073fa <TIM_OC1_SetConfig+0xc2>
80073e2: 687b ldr r3, [r7, #4]
80073e4: 4a19 ldr r2, [pc, #100] ; (800744c <TIM_OC1_SetConfig+0x114>)
80073e6: 4293 cmp r3, r2
80073e8: d007 beq.n 80073fa <TIM_OC1_SetConfig+0xc2>
80073ea: 687b ldr r3, [r7, #4]
80073ec: 4a18 ldr r2, [pc, #96] ; (8007450 <TIM_OC1_SetConfig+0x118>)
80073ee: 4293 cmp r3, r2
80073f0: d003 beq.n 80073fa <TIM_OC1_SetConfig+0xc2>
80073f2: 687b ldr r3, [r7, #4]
80073f4: 4a17 ldr r2, [pc, #92] ; (8007454 <TIM_OC1_SetConfig+0x11c>)
80073f6: 4293 cmp r3, r2
80073f8: d111 bne.n 800741e <TIM_OC1_SetConfig+0xe6>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
80073fa: 693b ldr r3, [r7, #16]
80073fc: f423 7380 bic.w r3, r3, #256 ; 0x100
8007400: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
8007402: 693b ldr r3, [r7, #16]
8007404: f423 7300 bic.w r3, r3, #512 ; 0x200
8007408: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
800740a: 683b ldr r3, [r7, #0]
800740c: 695b ldr r3, [r3, #20]
800740e: 693a ldr r2, [r7, #16]
8007410: 4313 orrs r3, r2
8007412: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
8007414: 683b ldr r3, [r7, #0]
8007416: 699b ldr r3, [r3, #24]
8007418: 693a ldr r2, [r7, #16]
800741a: 4313 orrs r3, r2
800741c: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800741e: 687b ldr r3, [r7, #4]
8007420: 693a ldr r2, [r7, #16]
8007422: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8007424: 687b ldr r3, [r7, #4]
8007426: 68fa ldr r2, [r7, #12]
8007428: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
800742a: 683b ldr r3, [r7, #0]
800742c: 685a ldr r2, [r3, #4]
800742e: 687b ldr r3, [r7, #4]
8007430: 635a str r2, [r3, #52] ; 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8007432: 687b ldr r3, [r7, #4]
8007434: 697a ldr r2, [r7, #20]
8007436: 621a str r2, [r3, #32]
}
8007438: bf00 nop
800743a: 371c adds r7, #28
800743c: 46bd mov sp, r7
800743e: f85d 7b04 ldr.w r7, [sp], #4
8007442: 4770 bx lr
8007444: 40012c00 .word 0x40012c00
8007448: 40013400 .word 0x40013400
800744c: 40014000 .word 0x40014000
8007450: 40014400 .word 0x40014400
8007454: 40014800 .word 0x40014800
08007458 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8007458: b480 push {r7}
800745a: b087 sub sp, #28
800745c: af00 add r7, sp, #0
800745e: 6078 str r0, [r7, #4]
8007460: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8007462: 687b ldr r3, [r7, #4]
8007464: 6a1b ldr r3, [r3, #32]
8007466: f023 0210 bic.w r2, r3, #16
800746a: 687b ldr r3, [r7, #4]
800746c: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800746e: 687b ldr r3, [r7, #4]
8007470: 6a1b ldr r3, [r3, #32]
8007472: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8007474: 687b ldr r3, [r7, #4]
8007476: 685b ldr r3, [r3, #4]
8007478: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
800747a: 687b ldr r3, [r7, #4]
800747c: 699b ldr r3, [r3, #24]
800747e: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
8007480: 68fb ldr r3, [r7, #12]
8007482: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
8007486: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
800748a: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
800748c: 68fb ldr r3, [r7, #12]
800748e: f423 7340 bic.w r3, r3, #768 ; 0x300
8007492: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8007494: 683b ldr r3, [r7, #0]
8007496: 681b ldr r3, [r3, #0]
8007498: 021b lsls r3, r3, #8
800749a: 68fa ldr r2, [r7, #12]
800749c: 4313 orrs r3, r2
800749e: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
80074a0: 697b ldr r3, [r7, #20]
80074a2: f023 0320 bic.w r3, r3, #32
80074a6: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
80074a8: 683b ldr r3, [r7, #0]
80074aa: 689b ldr r3, [r3, #8]
80074ac: 011b lsls r3, r3, #4
80074ae: 697a ldr r2, [r7, #20]
80074b0: 4313 orrs r3, r2
80074b2: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
80074b4: 687b ldr r3, [r7, #4]
80074b6: 4a28 ldr r2, [pc, #160] ; (8007558 <TIM_OC2_SetConfig+0x100>)
80074b8: 4293 cmp r3, r2
80074ba: d003 beq.n 80074c4 <TIM_OC2_SetConfig+0x6c>
80074bc: 687b ldr r3, [r7, #4]
80074be: 4a27 ldr r2, [pc, #156] ; (800755c <TIM_OC2_SetConfig+0x104>)
80074c0: 4293 cmp r3, r2
80074c2: d10d bne.n 80074e0 <TIM_OC2_SetConfig+0x88>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
80074c4: 697b ldr r3, [r7, #20]
80074c6: f023 0380 bic.w r3, r3, #128 ; 0x80
80074ca: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
80074cc: 683b ldr r3, [r7, #0]
80074ce: 68db ldr r3, [r3, #12]
80074d0: 011b lsls r3, r3, #4
80074d2: 697a ldr r2, [r7, #20]
80074d4: 4313 orrs r3, r2
80074d6: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
80074d8: 697b ldr r3, [r7, #20]
80074da: f023 0340 bic.w r3, r3, #64 ; 0x40
80074de: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
80074e0: 687b ldr r3, [r7, #4]
80074e2: 4a1d ldr r2, [pc, #116] ; (8007558 <TIM_OC2_SetConfig+0x100>)
80074e4: 4293 cmp r3, r2
80074e6: d00f beq.n 8007508 <TIM_OC2_SetConfig+0xb0>
80074e8: 687b ldr r3, [r7, #4]
80074ea: 4a1c ldr r2, [pc, #112] ; (800755c <TIM_OC2_SetConfig+0x104>)
80074ec: 4293 cmp r3, r2
80074ee: d00b beq.n 8007508 <TIM_OC2_SetConfig+0xb0>
80074f0: 687b ldr r3, [r7, #4]
80074f2: 4a1b ldr r2, [pc, #108] ; (8007560 <TIM_OC2_SetConfig+0x108>)
80074f4: 4293 cmp r3, r2
80074f6: d007 beq.n 8007508 <TIM_OC2_SetConfig+0xb0>
80074f8: 687b ldr r3, [r7, #4]
80074fa: 4a1a ldr r2, [pc, #104] ; (8007564 <TIM_OC2_SetConfig+0x10c>)
80074fc: 4293 cmp r3, r2
80074fe: d003 beq.n 8007508 <TIM_OC2_SetConfig+0xb0>
8007500: 687b ldr r3, [r7, #4]
8007502: 4a19 ldr r2, [pc, #100] ; (8007568 <TIM_OC2_SetConfig+0x110>)
8007504: 4293 cmp r3, r2
8007506: d113 bne.n 8007530 <TIM_OC2_SetConfig+0xd8>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8007508: 693b ldr r3, [r7, #16]
800750a: f423 6380 bic.w r3, r3, #1024 ; 0x400
800750e: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
8007510: 693b ldr r3, [r7, #16]
8007512: f423 6300 bic.w r3, r3, #2048 ; 0x800
8007516: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
8007518: 683b ldr r3, [r7, #0]
800751a: 695b ldr r3, [r3, #20]
800751c: 009b lsls r3, r3, #2
800751e: 693a ldr r2, [r7, #16]
8007520: 4313 orrs r3, r2
8007522: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8007524: 683b ldr r3, [r7, #0]
8007526: 699b ldr r3, [r3, #24]
8007528: 009b lsls r3, r3, #2
800752a: 693a ldr r2, [r7, #16]
800752c: 4313 orrs r3, r2
800752e: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8007530: 687b ldr r3, [r7, #4]
8007532: 693a ldr r2, [r7, #16]
8007534: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8007536: 687b ldr r3, [r7, #4]
8007538: 68fa ldr r2, [r7, #12]
800753a: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
800753c: 683b ldr r3, [r7, #0]
800753e: 685a ldr r2, [r3, #4]
8007540: 687b ldr r3, [r7, #4]
8007542: 639a str r2, [r3, #56] ; 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8007544: 687b ldr r3, [r7, #4]
8007546: 697a ldr r2, [r7, #20]
8007548: 621a str r2, [r3, #32]
}
800754a: bf00 nop
800754c: 371c adds r7, #28
800754e: 46bd mov sp, r7
8007550: f85d 7b04 ldr.w r7, [sp], #4
8007554: 4770 bx lr
8007556: bf00 nop
8007558: 40012c00 .word 0x40012c00
800755c: 40013400 .word 0x40013400
8007560: 40014000 .word 0x40014000
8007564: 40014400 .word 0x40014400
8007568: 40014800 .word 0x40014800
0800756c <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
800756c: b480 push {r7}
800756e: b087 sub sp, #28
8007570: af00 add r7, sp, #0
8007572: 6078 str r0, [r7, #4]
8007574: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8007576: 687b ldr r3, [r7, #4]
8007578: 6a1b ldr r3, [r3, #32]
800757a: f423 7280 bic.w r2, r3, #256 ; 0x100
800757e: 687b ldr r3, [r7, #4]
8007580: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8007582: 687b ldr r3, [r7, #4]
8007584: 6a1b ldr r3, [r3, #32]
8007586: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8007588: 687b ldr r3, [r7, #4]
800758a: 685b ldr r3, [r3, #4]
800758c: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800758e: 687b ldr r3, [r7, #4]
8007590: 69db ldr r3, [r3, #28]
8007592: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
8007594: 68fb ldr r3, [r7, #12]
8007596: f423 3380 bic.w r3, r3, #65536 ; 0x10000
800759a: f023 0370 bic.w r3, r3, #112 ; 0x70
800759e: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
80075a0: 68fb ldr r3, [r7, #12]
80075a2: f023 0303 bic.w r3, r3, #3
80075a6: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
80075a8: 683b ldr r3, [r7, #0]
80075aa: 681b ldr r3, [r3, #0]
80075ac: 68fa ldr r2, [r7, #12]
80075ae: 4313 orrs r3, r2
80075b0: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
80075b2: 697b ldr r3, [r7, #20]
80075b4: f423 7300 bic.w r3, r3, #512 ; 0x200
80075b8: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
80075ba: 683b ldr r3, [r7, #0]
80075bc: 689b ldr r3, [r3, #8]
80075be: 021b lsls r3, r3, #8
80075c0: 697a ldr r2, [r7, #20]
80075c2: 4313 orrs r3, r2
80075c4: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
80075c6: 687b ldr r3, [r7, #4]
80075c8: 4a27 ldr r2, [pc, #156] ; (8007668 <TIM_OC3_SetConfig+0xfc>)
80075ca: 4293 cmp r3, r2
80075cc: d003 beq.n 80075d6 <TIM_OC3_SetConfig+0x6a>
80075ce: 687b ldr r3, [r7, #4]
80075d0: 4a26 ldr r2, [pc, #152] ; (800766c <TIM_OC3_SetConfig+0x100>)
80075d2: 4293 cmp r3, r2
80075d4: d10d bne.n 80075f2 <TIM_OC3_SetConfig+0x86>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
80075d6: 697b ldr r3, [r7, #20]
80075d8: f423 6300 bic.w r3, r3, #2048 ; 0x800
80075dc: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
80075de: 683b ldr r3, [r7, #0]
80075e0: 68db ldr r3, [r3, #12]
80075e2: 021b lsls r3, r3, #8
80075e4: 697a ldr r2, [r7, #20]
80075e6: 4313 orrs r3, r2
80075e8: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
80075ea: 697b ldr r3, [r7, #20]
80075ec: f423 6380 bic.w r3, r3, #1024 ; 0x400
80075f0: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
80075f2: 687b ldr r3, [r7, #4]
80075f4: 4a1c ldr r2, [pc, #112] ; (8007668 <TIM_OC3_SetConfig+0xfc>)
80075f6: 4293 cmp r3, r2
80075f8: d00f beq.n 800761a <TIM_OC3_SetConfig+0xae>
80075fa: 687b ldr r3, [r7, #4]
80075fc: 4a1b ldr r2, [pc, #108] ; (800766c <TIM_OC3_SetConfig+0x100>)
80075fe: 4293 cmp r3, r2
8007600: d00b beq.n 800761a <TIM_OC3_SetConfig+0xae>
8007602: 687b ldr r3, [r7, #4]
8007604: 4a1a ldr r2, [pc, #104] ; (8007670 <TIM_OC3_SetConfig+0x104>)
8007606: 4293 cmp r3, r2
8007608: d007 beq.n 800761a <TIM_OC3_SetConfig+0xae>
800760a: 687b ldr r3, [r7, #4]
800760c: 4a19 ldr r2, [pc, #100] ; (8007674 <TIM_OC3_SetConfig+0x108>)
800760e: 4293 cmp r3, r2
8007610: d003 beq.n 800761a <TIM_OC3_SetConfig+0xae>
8007612: 687b ldr r3, [r7, #4]
8007614: 4a18 ldr r2, [pc, #96] ; (8007678 <TIM_OC3_SetConfig+0x10c>)
8007616: 4293 cmp r3, r2
8007618: d113 bne.n 8007642 <TIM_OC3_SetConfig+0xd6>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
800761a: 693b ldr r3, [r7, #16]
800761c: f423 5380 bic.w r3, r3, #4096 ; 0x1000
8007620: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
8007622: 693b ldr r3, [r7, #16]
8007624: f423 5300 bic.w r3, r3, #8192 ; 0x2000
8007628: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
800762a: 683b ldr r3, [r7, #0]
800762c: 695b ldr r3, [r3, #20]
800762e: 011b lsls r3, r3, #4
8007630: 693a ldr r2, [r7, #16]
8007632: 4313 orrs r3, r2
8007634: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
8007636: 683b ldr r3, [r7, #0]
8007638: 699b ldr r3, [r3, #24]
800763a: 011b lsls r3, r3, #4
800763c: 693a ldr r2, [r7, #16]
800763e: 4313 orrs r3, r2
8007640: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8007642: 687b ldr r3, [r7, #4]
8007644: 693a ldr r2, [r7, #16]
8007646: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8007648: 687b ldr r3, [r7, #4]
800764a: 68fa ldr r2, [r7, #12]
800764c: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
800764e: 683b ldr r3, [r7, #0]
8007650: 685a ldr r2, [r3, #4]
8007652: 687b ldr r3, [r7, #4]
8007654: 63da str r2, [r3, #60] ; 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8007656: 687b ldr r3, [r7, #4]
8007658: 697a ldr r2, [r7, #20]
800765a: 621a str r2, [r3, #32]
}
800765c: bf00 nop
800765e: 371c adds r7, #28
8007660: 46bd mov sp, r7
8007662: f85d 7b04 ldr.w r7, [sp], #4
8007666: 4770 bx lr
8007668: 40012c00 .word 0x40012c00
800766c: 40013400 .word 0x40013400
8007670: 40014000 .word 0x40014000
8007674: 40014400 .word 0x40014400
8007678: 40014800 .word 0x40014800
0800767c <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
800767c: b480 push {r7}
800767e: b087 sub sp, #28
8007680: af00 add r7, sp, #0
8007682: 6078 str r0, [r7, #4]
8007684: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
8007686: 687b ldr r3, [r7, #4]
8007688: 6a1b ldr r3, [r3, #32]
800768a: f423 5280 bic.w r2, r3, #4096 ; 0x1000
800768e: 687b ldr r3, [r7, #4]
8007690: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8007692: 687b ldr r3, [r7, #4]
8007694: 6a1b ldr r3, [r3, #32]
8007696: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8007698: 687b ldr r3, [r7, #4]
800769a: 685b ldr r3, [r3, #4]
800769c: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800769e: 687b ldr r3, [r7, #4]
80076a0: 69db ldr r3, [r3, #28]
80076a2: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
80076a4: 68fb ldr r3, [r7, #12]
80076a6: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
80076aa: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
80076ae: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
80076b0: 68fb ldr r3, [r7, #12]
80076b2: f423 7340 bic.w r3, r3, #768 ; 0x300
80076b6: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
80076b8: 683b ldr r3, [r7, #0]
80076ba: 681b ldr r3, [r3, #0]
80076bc: 021b lsls r3, r3, #8
80076be: 68fa ldr r2, [r7, #12]
80076c0: 4313 orrs r3, r2
80076c2: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
80076c4: 697b ldr r3, [r7, #20]
80076c6: f423 5300 bic.w r3, r3, #8192 ; 0x2000
80076ca: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
80076cc: 683b ldr r3, [r7, #0]
80076ce: 689b ldr r3, [r3, #8]
80076d0: 031b lsls r3, r3, #12
80076d2: 697a ldr r2, [r7, #20]
80076d4: 4313 orrs r3, r2
80076d6: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4))
80076d8: 687b ldr r3, [r7, #4]
80076da: 4a28 ldr r2, [pc, #160] ; (800777c <TIM_OC4_SetConfig+0x100>)
80076dc: 4293 cmp r3, r2
80076de: d003 beq.n 80076e8 <TIM_OC4_SetConfig+0x6c>
80076e0: 687b ldr r3, [r7, #4]
80076e2: 4a27 ldr r2, [pc, #156] ; (8007780 <TIM_OC4_SetConfig+0x104>)
80076e4: 4293 cmp r3, r2
80076e6: d10d bne.n 8007704 <TIM_OC4_SetConfig+0x88>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC4NP;
80076e8: 697b ldr r3, [r7, #20]
80076ea: f423 4300 bic.w r3, r3, #32768 ; 0x8000
80076ee: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 12U);
80076f0: 683b ldr r3, [r7, #0]
80076f2: 68db ldr r3, [r3, #12]
80076f4: 031b lsls r3, r3, #12
80076f6: 697a ldr r2, [r7, #20]
80076f8: 4313 orrs r3, r2
80076fa: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC4NE;
80076fc: 697b ldr r3, [r7, #20]
80076fe: f423 4380 bic.w r3, r3, #16384 ; 0x4000
8007702: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8007704: 687b ldr r3, [r7, #4]
8007706: 4a1d ldr r2, [pc, #116] ; (800777c <TIM_OC4_SetConfig+0x100>)
8007708: 4293 cmp r3, r2
800770a: d00f beq.n 800772c <TIM_OC4_SetConfig+0xb0>
800770c: 687b ldr r3, [r7, #4]
800770e: 4a1c ldr r2, [pc, #112] ; (8007780 <TIM_OC4_SetConfig+0x104>)
8007710: 4293 cmp r3, r2
8007712: d00b beq.n 800772c <TIM_OC4_SetConfig+0xb0>
8007714: 687b ldr r3, [r7, #4]
8007716: 4a1b ldr r2, [pc, #108] ; (8007784 <TIM_OC4_SetConfig+0x108>)
8007718: 4293 cmp r3, r2
800771a: d007 beq.n 800772c <TIM_OC4_SetConfig+0xb0>
800771c: 687b ldr r3, [r7, #4]
800771e: 4a1a ldr r2, [pc, #104] ; (8007788 <TIM_OC4_SetConfig+0x10c>)
8007720: 4293 cmp r3, r2
8007722: d003 beq.n 800772c <TIM_OC4_SetConfig+0xb0>
8007724: 687b ldr r3, [r7, #4]
8007726: 4a19 ldr r2, [pc, #100] ; (800778c <TIM_OC4_SetConfig+0x110>)
8007728: 4293 cmp r3, r2
800772a: d113 bne.n 8007754 <TIM_OC4_SetConfig+0xd8>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
800772c: 693b ldr r3, [r7, #16]
800772e: f423 4380 bic.w r3, r3, #16384 ; 0x4000
8007732: 613b str r3, [r7, #16]
/* Reset the Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4N;
8007734: 693b ldr r3, [r7, #16]
8007736: f423 4300 bic.w r3, r3, #32768 ; 0x8000
800773a: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
800773c: 683b ldr r3, [r7, #0]
800773e: 695b ldr r3, [r3, #20]
8007740: 019b lsls r3, r3, #6
8007742: 693a ldr r2, [r7, #16]
8007744: 4313 orrs r3, r2
8007746: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 6U);
8007748: 683b ldr r3, [r7, #0]
800774a: 699b ldr r3, [r3, #24]
800774c: 019b lsls r3, r3, #6
800774e: 693a ldr r2, [r7, #16]
8007750: 4313 orrs r3, r2
8007752: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8007754: 687b ldr r3, [r7, #4]
8007756: 693a ldr r2, [r7, #16]
8007758: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
800775a: 687b ldr r3, [r7, #4]
800775c: 68fa ldr r2, [r7, #12]
800775e: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
8007760: 683b ldr r3, [r7, #0]
8007762: 685a ldr r2, [r3, #4]
8007764: 687b ldr r3, [r7, #4]
8007766: 641a str r2, [r3, #64] ; 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8007768: 687b ldr r3, [r7, #4]
800776a: 697a ldr r2, [r7, #20]
800776c: 621a str r2, [r3, #32]
}
800776e: bf00 nop
8007770: 371c adds r7, #28
8007772: 46bd mov sp, r7
8007774: f85d 7b04 ldr.w r7, [sp], #4
8007778: 4770 bx lr
800777a: bf00 nop
800777c: 40012c00 .word 0x40012c00
8007780: 40013400 .word 0x40013400
8007784: 40014000 .word 0x40014000
8007788: 40014400 .word 0x40014400
800778c: 40014800 .word 0x40014800
08007790 <TIM_OC5_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
TIM_OC_InitTypeDef *OC_Config)
{
8007790: b480 push {r7}
8007792: b087 sub sp, #28
8007794: af00 add r7, sp, #0
8007796: 6078 str r0, [r7, #4]
8007798: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
800779a: 687b ldr r3, [r7, #4]
800779c: 6a1b ldr r3, [r3, #32]
800779e: f423 3280 bic.w r2, r3, #65536 ; 0x10000
80077a2: 687b ldr r3, [r7, #4]
80077a4: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80077a6: 687b ldr r3, [r7, #4]
80077a8: 6a1b ldr r3, [r3, #32]
80077aa: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80077ac: 687b ldr r3, [r7, #4]
80077ae: 685b ldr r3, [r3, #4]
80077b0: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
80077b2: 687b ldr r3, [r7, #4]
80077b4: 6d1b ldr r3, [r3, #80] ; 0x50
80077b6: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC5M);
80077b8: 68fb ldr r3, [r7, #12]
80077ba: f423 3380 bic.w r3, r3, #65536 ; 0x10000
80077be: f023 0370 bic.w r3, r3, #112 ; 0x70
80077c2: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
80077c4: 683b ldr r3, [r7, #0]
80077c6: 681b ldr r3, [r3, #0]
80077c8: 68fa ldr r2, [r7, #12]
80077ca: 4313 orrs r3, r2
80077cc: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
80077ce: 693b ldr r3, [r7, #16]
80077d0: f423 3300 bic.w r3, r3, #131072 ; 0x20000
80077d4: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 16U);
80077d6: 683b ldr r3, [r7, #0]
80077d8: 689b ldr r3, [r3, #8]
80077da: 041b lsls r3, r3, #16
80077dc: 693a ldr r2, [r7, #16]
80077de: 4313 orrs r3, r2
80077e0: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
80077e2: 687b ldr r3, [r7, #4]
80077e4: 4a17 ldr r2, [pc, #92] ; (8007844 <TIM_OC5_SetConfig+0xb4>)
80077e6: 4293 cmp r3, r2
80077e8: d00f beq.n 800780a <TIM_OC5_SetConfig+0x7a>
80077ea: 687b ldr r3, [r7, #4]
80077ec: 4a16 ldr r2, [pc, #88] ; (8007848 <TIM_OC5_SetConfig+0xb8>)
80077ee: 4293 cmp r3, r2
80077f0: d00b beq.n 800780a <TIM_OC5_SetConfig+0x7a>
80077f2: 687b ldr r3, [r7, #4]
80077f4: 4a15 ldr r2, [pc, #84] ; (800784c <TIM_OC5_SetConfig+0xbc>)
80077f6: 4293 cmp r3, r2
80077f8: d007 beq.n 800780a <TIM_OC5_SetConfig+0x7a>
80077fa: 687b ldr r3, [r7, #4]
80077fc: 4a14 ldr r2, [pc, #80] ; (8007850 <TIM_OC5_SetConfig+0xc0>)
80077fe: 4293 cmp r3, r2
8007800: d003 beq.n 800780a <TIM_OC5_SetConfig+0x7a>
8007802: 687b ldr r3, [r7, #4]
8007804: 4a13 ldr r2, [pc, #76] ; (8007854 <TIM_OC5_SetConfig+0xc4>)
8007806: 4293 cmp r3, r2
8007808: d109 bne.n 800781e <TIM_OC5_SetConfig+0x8e>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
800780a: 697b ldr r3, [r7, #20]
800780c: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8007810: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 8U);
8007812: 683b ldr r3, [r7, #0]
8007814: 695b ldr r3, [r3, #20]
8007816: 021b lsls r3, r3, #8
8007818: 697a ldr r2, [r7, #20]
800781a: 4313 orrs r3, r2
800781c: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800781e: 687b ldr r3, [r7, #4]
8007820: 697a ldr r2, [r7, #20]
8007822: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
8007824: 687b ldr r3, [r7, #4]
8007826: 68fa ldr r2, [r7, #12]
8007828: 651a str r2, [r3, #80] ; 0x50
/* Set the Capture Compare Register value */
TIMx->CCR5 = OC_Config->Pulse;
800782a: 683b ldr r3, [r7, #0]
800782c: 685a ldr r2, [r3, #4]
800782e: 687b ldr r3, [r7, #4]
8007830: 649a str r2, [r3, #72] ; 0x48
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8007832: 687b ldr r3, [r7, #4]
8007834: 693a ldr r2, [r7, #16]
8007836: 621a str r2, [r3, #32]
}
8007838: bf00 nop
800783a: 371c adds r7, #28
800783c: 46bd mov sp, r7
800783e: f85d 7b04 ldr.w r7, [sp], #4
8007842: 4770 bx lr
8007844: 40012c00 .word 0x40012c00
8007848: 40013400 .word 0x40013400
800784c: 40014000 .word 0x40014000
8007850: 40014400 .word 0x40014400
8007854: 40014800 .word 0x40014800
08007858 <TIM_OC6_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
TIM_OC_InitTypeDef *OC_Config)
{
8007858: b480 push {r7}
800785a: b087 sub sp, #28
800785c: af00 add r7, sp, #0
800785e: 6078 str r0, [r7, #4]
8007860: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
8007862: 687b ldr r3, [r7, #4]
8007864: 6a1b ldr r3, [r3, #32]
8007866: f423 1280 bic.w r2, r3, #1048576 ; 0x100000
800786a: 687b ldr r3, [r7, #4]
800786c: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800786e: 687b ldr r3, [r7, #4]
8007870: 6a1b ldr r3, [r3, #32]
8007872: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8007874: 687b ldr r3, [r7, #4]
8007876: 685b ldr r3, [r3, #4]
8007878: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
800787a: 687b ldr r3, [r7, #4]
800787c: 6d1b ldr r3, [r3, #80] ; 0x50
800787e: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
8007880: 68fb ldr r3, [r7, #12]
8007882: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
8007886: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
800788a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800788c: 683b ldr r3, [r7, #0]
800788e: 681b ldr r3, [r3, #0]
8007890: 021b lsls r3, r3, #8
8007892: 68fa ldr r2, [r7, #12]
8007894: 4313 orrs r3, r2
8007896: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
8007898: 693b ldr r3, [r7, #16]
800789a: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
800789e: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 20U);
80078a0: 683b ldr r3, [r7, #0]
80078a2: 689b ldr r3, [r3, #8]
80078a4: 051b lsls r3, r3, #20
80078a6: 693a ldr r2, [r7, #16]
80078a8: 4313 orrs r3, r2
80078aa: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
80078ac: 687b ldr r3, [r7, #4]
80078ae: 4a18 ldr r2, [pc, #96] ; (8007910 <TIM_OC6_SetConfig+0xb8>)
80078b0: 4293 cmp r3, r2
80078b2: d00f beq.n 80078d4 <TIM_OC6_SetConfig+0x7c>
80078b4: 687b ldr r3, [r7, #4]
80078b6: 4a17 ldr r2, [pc, #92] ; (8007914 <TIM_OC6_SetConfig+0xbc>)
80078b8: 4293 cmp r3, r2
80078ba: d00b beq.n 80078d4 <TIM_OC6_SetConfig+0x7c>
80078bc: 687b ldr r3, [r7, #4]
80078be: 4a16 ldr r2, [pc, #88] ; (8007918 <TIM_OC6_SetConfig+0xc0>)
80078c0: 4293 cmp r3, r2
80078c2: d007 beq.n 80078d4 <TIM_OC6_SetConfig+0x7c>
80078c4: 687b ldr r3, [r7, #4]
80078c6: 4a15 ldr r2, [pc, #84] ; (800791c <TIM_OC6_SetConfig+0xc4>)
80078c8: 4293 cmp r3, r2
80078ca: d003 beq.n 80078d4 <TIM_OC6_SetConfig+0x7c>
80078cc: 687b ldr r3, [r7, #4]
80078ce: 4a14 ldr r2, [pc, #80] ; (8007920 <TIM_OC6_SetConfig+0xc8>)
80078d0: 4293 cmp r3, r2
80078d2: d109 bne.n 80078e8 <TIM_OC6_SetConfig+0x90>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
80078d4: 697b ldr r3, [r7, #20]
80078d6: f423 2380 bic.w r3, r3, #262144 ; 0x40000
80078da: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 10U);
80078dc: 683b ldr r3, [r7, #0]
80078de: 695b ldr r3, [r3, #20]
80078e0: 029b lsls r3, r3, #10
80078e2: 697a ldr r2, [r7, #20]
80078e4: 4313 orrs r3, r2
80078e6: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80078e8: 687b ldr r3, [r7, #4]
80078ea: 697a ldr r2, [r7, #20]
80078ec: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
80078ee: 687b ldr r3, [r7, #4]
80078f0: 68fa ldr r2, [r7, #12]
80078f2: 651a str r2, [r3, #80] ; 0x50
/* Set the Capture Compare Register value */
TIMx->CCR6 = OC_Config->Pulse;
80078f4: 683b ldr r3, [r7, #0]
80078f6: 685a ldr r2, [r3, #4]
80078f8: 687b ldr r3, [r7, #4]
80078fa: 64da str r2, [r3, #76] ; 0x4c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80078fc: 687b ldr r3, [r7, #4]
80078fe: 693a ldr r2, [r7, #16]
8007900: 621a str r2, [r3, #32]
}
8007902: bf00 nop
8007904: 371c adds r7, #28
8007906: 46bd mov sp, r7
8007908: f85d 7b04 ldr.w r7, [sp], #4
800790c: 4770 bx lr
800790e: bf00 nop
8007910: 40012c00 .word 0x40012c00
8007914: 40013400 .word 0x40013400
8007918: 40014000 .word 0x40014000
800791c: 40014400 .word 0x40014400
8007920: 40014800 .word 0x40014800
08007924 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8007924: b480 push {r7}
8007926: b087 sub sp, #28
8007928: af00 add r7, sp, #0
800792a: 60f8 str r0, [r7, #12]
800792c: 60b9 str r1, [r7, #8]
800792e: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
8007930: 68fb ldr r3, [r7, #12]
8007932: 6a1b ldr r3, [r3, #32]
8007934: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
8007936: 68fb ldr r3, [r7, #12]
8007938: 6a1b ldr r3, [r3, #32]
800793a: f023 0201 bic.w r2, r3, #1
800793e: 68fb ldr r3, [r7, #12]
8007940: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8007942: 68fb ldr r3, [r7, #12]
8007944: 699b ldr r3, [r3, #24]
8007946: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8007948: 693b ldr r3, [r7, #16]
800794a: f023 03f0 bic.w r3, r3, #240 ; 0xf0
800794e: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
8007950: 687b ldr r3, [r7, #4]
8007952: 011b lsls r3, r3, #4
8007954: 693a ldr r2, [r7, #16]
8007956: 4313 orrs r3, r2
8007958: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
800795a: 697b ldr r3, [r7, #20]
800795c: f023 030a bic.w r3, r3, #10
8007960: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
8007962: 697a ldr r2, [r7, #20]
8007964: 68bb ldr r3, [r7, #8]
8007966: 4313 orrs r3, r2
8007968: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
800796a: 68fb ldr r3, [r7, #12]
800796c: 693a ldr r2, [r7, #16]
800796e: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8007970: 68fb ldr r3, [r7, #12]
8007972: 697a ldr r2, [r7, #20]
8007974: 621a str r2, [r3, #32]
}
8007976: bf00 nop
8007978: 371c adds r7, #28
800797a: 46bd mov sp, r7
800797c: f85d 7b04 ldr.w r7, [sp], #4
8007980: 4770 bx lr
08007982 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8007982: b480 push {r7}
8007984: b087 sub sp, #28
8007986: af00 add r7, sp, #0
8007988: 60f8 str r0, [r7, #12]
800798a: 60b9 str r1, [r7, #8]
800798c: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
800798e: 68fb ldr r3, [r7, #12]
8007990: 6a1b ldr r3, [r3, #32]
8007992: f023 0210 bic.w r2, r3, #16
8007996: 68fb ldr r3, [r7, #12]
8007998: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
800799a: 68fb ldr r3, [r7, #12]
800799c: 699b ldr r3, [r3, #24]
800799e: 617b str r3, [r7, #20]
tmpccer = TIMx->CCER;
80079a0: 68fb ldr r3, [r7, #12]
80079a2: 6a1b ldr r3, [r3, #32]
80079a4: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
80079a6: 697b ldr r3, [r7, #20]
80079a8: f423 4370 bic.w r3, r3, #61440 ; 0xf000
80079ac: 617b str r3, [r7, #20]
tmpccmr1 |= (TIM_ICFilter << 12U);
80079ae: 687b ldr r3, [r7, #4]
80079b0: 031b lsls r3, r3, #12
80079b2: 697a ldr r2, [r7, #20]
80079b4: 4313 orrs r3, r2
80079b6: 617b str r3, [r7, #20]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
80079b8: 693b ldr r3, [r7, #16]
80079ba: f023 03a0 bic.w r3, r3, #160 ; 0xa0
80079be: 613b str r3, [r7, #16]
tmpccer |= (TIM_ICPolarity << 4U);
80079c0: 68bb ldr r3, [r7, #8]
80079c2: 011b lsls r3, r3, #4
80079c4: 693a ldr r2, [r7, #16]
80079c6: 4313 orrs r3, r2
80079c8: 613b str r3, [r7, #16]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
80079ca: 68fb ldr r3, [r7, #12]
80079cc: 697a ldr r2, [r7, #20]
80079ce: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
80079d0: 68fb ldr r3, [r7, #12]
80079d2: 693a ldr r2, [r7, #16]
80079d4: 621a str r2, [r3, #32]
}
80079d6: bf00 nop
80079d8: 371c adds r7, #28
80079da: 46bd mov sp, r7
80079dc: f85d 7b04 ldr.w r7, [sp], #4
80079e0: 4770 bx lr
080079e2 <TIM_ITRx_SetConfig>:
* (*) Value not defined in all devices.
*
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
80079e2: b480 push {r7}
80079e4: b085 sub sp, #20
80079e6: af00 add r7, sp, #0
80079e8: 6078 str r0, [r7, #4]
80079ea: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
80079ec: 687b ldr r3, [r7, #4]
80079ee: 689b ldr r3, [r3, #8]
80079f0: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
80079f2: 68fb ldr r3, [r7, #12]
80079f4: f423 1340 bic.w r3, r3, #3145728 ; 0x300000
80079f8: f023 0370 bic.w r3, r3, #112 ; 0x70
80079fc: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
80079fe: 683a ldr r2, [r7, #0]
8007a00: 68fb ldr r3, [r7, #12]
8007a02: 4313 orrs r3, r2
8007a04: f043 0307 orr.w r3, r3, #7
8007a08: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8007a0a: 687b ldr r3, [r7, #4]
8007a0c: 68fa ldr r2, [r7, #12]
8007a0e: 609a str r2, [r3, #8]
}
8007a10: bf00 nop
8007a12: 3714 adds r7, #20
8007a14: 46bd mov sp, r7
8007a16: f85d 7b04 ldr.w r7, [sp], #4
8007a1a: 4770 bx lr
08007a1c <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
8007a1c: b480 push {r7}
8007a1e: b087 sub sp, #28
8007a20: af00 add r7, sp, #0
8007a22: 60f8 str r0, [r7, #12]
8007a24: 60b9 str r1, [r7, #8]
8007a26: 607a str r2, [r7, #4]
8007a28: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
8007a2a: 68fb ldr r3, [r7, #12]
8007a2c: 689b ldr r3, [r3, #8]
8007a2e: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8007a30: 697b ldr r3, [r7, #20]
8007a32: f423 437f bic.w r3, r3, #65280 ; 0xff00
8007a36: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8007a38: 683b ldr r3, [r7, #0]
8007a3a: 021a lsls r2, r3, #8
8007a3c: 687b ldr r3, [r7, #4]
8007a3e: 431a orrs r2, r3
8007a40: 68bb ldr r3, [r7, #8]
8007a42: 4313 orrs r3, r2
8007a44: 697a ldr r2, [r7, #20]
8007a46: 4313 orrs r3, r2
8007a48: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8007a4a: 68fb ldr r3, [r7, #12]
8007a4c: 697a ldr r2, [r7, #20]
8007a4e: 609a str r2, [r3, #8]
}
8007a50: bf00 nop
8007a52: 371c adds r7, #28
8007a54: 46bd mov sp, r7
8007a56: f85d 7b04 ldr.w r7, [sp], #4
8007a5a: 4770 bx lr
08007a5c <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
8007a5c: b480 push {r7}
8007a5e: b087 sub sp, #28
8007a60: af00 add r7, sp, #0
8007a62: 60f8 str r0, [r7, #12]
8007a64: 60b9 str r1, [r7, #8]
8007a66: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8007a68: 68bb ldr r3, [r7, #8]
8007a6a: f003 031f and.w r3, r3, #31
8007a6e: 2201 movs r2, #1
8007a70: fa02 f303 lsl.w r3, r2, r3
8007a74: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
8007a76: 68fb ldr r3, [r7, #12]
8007a78: 6a1a ldr r2, [r3, #32]
8007a7a: 697b ldr r3, [r7, #20]
8007a7c: 43db mvns r3, r3
8007a7e: 401a ands r2, r3
8007a80: 68fb ldr r3, [r7, #12]
8007a82: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8007a84: 68fb ldr r3, [r7, #12]
8007a86: 6a1a ldr r2, [r3, #32]
8007a88: 68bb ldr r3, [r7, #8]
8007a8a: f003 031f and.w r3, r3, #31
8007a8e: 6879 ldr r1, [r7, #4]
8007a90: fa01 f303 lsl.w r3, r1, r3
8007a94: 431a orrs r2, r3
8007a96: 68fb ldr r3, [r7, #12]
8007a98: 621a str r2, [r3, #32]
}
8007a9a: bf00 nop
8007a9c: 371c adds r7, #28
8007a9e: 46bd mov sp, r7
8007aa0: f85d 7b04 ldr.w r7, [sp], #4
8007aa4: 4770 bx lr
...
08007aa8 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig)
{
8007aa8: b480 push {r7}
8007aaa: b085 sub sp, #20
8007aac: af00 add r7, sp, #0
8007aae: 6078 str r0, [r7, #4]
8007ab0: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8007ab2: 687b ldr r3, [r7, #4]
8007ab4: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8007ab8: 2b01 cmp r3, #1
8007aba: d101 bne.n 8007ac0 <HAL_TIMEx_MasterConfigSynchronization+0x18>
8007abc: 2302 movs r3, #2
8007abe: e065 b.n 8007b8c <HAL_TIMEx_MasterConfigSynchronization+0xe4>
8007ac0: 687b ldr r3, [r7, #4]
8007ac2: 2201 movs r2, #1
8007ac4: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8007ac8: 687b ldr r3, [r7, #4]
8007aca: 2202 movs r2, #2
8007acc: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8007ad0: 687b ldr r3, [r7, #4]
8007ad2: 681b ldr r3, [r3, #0]
8007ad4: 685b ldr r3, [r3, #4]
8007ad6: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8007ad8: 687b ldr r3, [r7, #4]
8007ada: 681b ldr r3, [r3, #0]
8007adc: 689b ldr r3, [r3, #8]
8007ade: 60bb str r3, [r7, #8]
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
8007ae0: 687b ldr r3, [r7, #4]
8007ae2: 681b ldr r3, [r3, #0]
8007ae4: 4a2c ldr r2, [pc, #176] ; (8007b98 <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
8007ae6: 4293 cmp r3, r2
8007ae8: d004 beq.n 8007af4 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
8007aea: 687b ldr r3, [r7, #4]
8007aec: 681b ldr r3, [r3, #0]
8007aee: 4a2b ldr r2, [pc, #172] ; (8007b9c <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
8007af0: 4293 cmp r3, r2
8007af2: d108 bne.n 8007b06 <HAL_TIMEx_MasterConfigSynchronization+0x5e>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
8007af4: 68fb ldr r3, [r7, #12]
8007af6: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
8007afa: 60fb str r3, [r7, #12]
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
8007afc: 683b ldr r3, [r7, #0]
8007afe: 685b ldr r3, [r3, #4]
8007b00: 68fa ldr r2, [r7, #12]
8007b02: 4313 orrs r3, r2
8007b04: 60fb str r3, [r7, #12]
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8007b06: 68fb ldr r3, [r7, #12]
8007b08: f023 7300 bic.w r3, r3, #33554432 ; 0x2000000
8007b0c: f023 0370 bic.w r3, r3, #112 ; 0x70
8007b10: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8007b12: 683b ldr r3, [r7, #0]
8007b14: 681b ldr r3, [r3, #0]
8007b16: 68fa ldr r2, [r7, #12]
8007b18: 4313 orrs r3, r2
8007b1a: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8007b1c: 687b ldr r3, [r7, #4]
8007b1e: 681b ldr r3, [r3, #0]
8007b20: 68fa ldr r2, [r7, #12]
8007b22: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8007b24: 687b ldr r3, [r7, #4]
8007b26: 681b ldr r3, [r3, #0]
8007b28: 4a1b ldr r2, [pc, #108] ; (8007b98 <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
8007b2a: 4293 cmp r3, r2
8007b2c: d018 beq.n 8007b60 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
8007b2e: 687b ldr r3, [r7, #4]
8007b30: 681b ldr r3, [r3, #0]
8007b32: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8007b36: d013 beq.n 8007b60 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
8007b38: 687b ldr r3, [r7, #4]
8007b3a: 681b ldr r3, [r3, #0]
8007b3c: 4a18 ldr r2, [pc, #96] ; (8007ba0 <HAL_TIMEx_MasterConfigSynchronization+0xf8>)
8007b3e: 4293 cmp r3, r2
8007b40: d00e beq.n 8007b60 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
8007b42: 687b ldr r3, [r7, #4]
8007b44: 681b ldr r3, [r3, #0]
8007b46: 4a17 ldr r2, [pc, #92] ; (8007ba4 <HAL_TIMEx_MasterConfigSynchronization+0xfc>)
8007b48: 4293 cmp r3, r2
8007b4a: d009 beq.n 8007b60 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
8007b4c: 687b ldr r3, [r7, #4]
8007b4e: 681b ldr r3, [r3, #0]
8007b50: 4a12 ldr r2, [pc, #72] ; (8007b9c <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
8007b52: 4293 cmp r3, r2
8007b54: d004 beq.n 8007b60 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
8007b56: 687b ldr r3, [r7, #4]
8007b58: 681b ldr r3, [r3, #0]
8007b5a: 4a13 ldr r2, [pc, #76] ; (8007ba8 <HAL_TIMEx_MasterConfigSynchronization+0x100>)
8007b5c: 4293 cmp r3, r2
8007b5e: d10c bne.n 8007b7a <HAL_TIMEx_MasterConfigSynchronization+0xd2>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8007b60: 68bb ldr r3, [r7, #8]
8007b62: f023 0380 bic.w r3, r3, #128 ; 0x80
8007b66: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8007b68: 683b ldr r3, [r7, #0]
8007b6a: 689b ldr r3, [r3, #8]
8007b6c: 68ba ldr r2, [r7, #8]
8007b6e: 4313 orrs r3, r2
8007b70: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8007b72: 687b ldr r3, [r7, #4]
8007b74: 681b ldr r3, [r3, #0]
8007b76: 68ba ldr r2, [r7, #8]
8007b78: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8007b7a: 687b ldr r3, [r7, #4]
8007b7c: 2201 movs r2, #1
8007b7e: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
8007b82: 687b ldr r3, [r7, #4]
8007b84: 2200 movs r2, #0
8007b86: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8007b8a: 2300 movs r3, #0
}
8007b8c: 4618 mov r0, r3
8007b8e: 3714 adds r7, #20
8007b90: 46bd mov sp, r7
8007b92: f85d 7b04 ldr.w r7, [sp], #4
8007b96: 4770 bx lr
8007b98: 40012c00 .word 0x40012c00
8007b9c: 40013400 .word 0x40013400
8007ba0: 40000400 .word 0x40000400
8007ba4: 40000800 .word 0x40000800
8007ba8: 40014000 .word 0x40014000
08007bac <HAL_TIMEx_CommutCallback>:
* @brief Hall commutation changed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
8007bac: b480 push {r7}
8007bae: b083 sub sp, #12
8007bb0: af00 add r7, sp, #0
8007bb2: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
8007bb4: bf00 nop
8007bb6: 370c adds r7, #12
8007bb8: 46bd mov sp, r7
8007bba: f85d 7b04 ldr.w r7, [sp], #4
8007bbe: 4770 bx lr
08007bc0 <HAL_TIMEx_BreakCallback>:
* @brief Hall Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
8007bc0: b480 push {r7}
8007bc2: b083 sub sp, #12
8007bc4: af00 add r7, sp, #0
8007bc6: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
8007bc8: bf00 nop
8007bca: 370c adds r7, #12
8007bcc: 46bd mov sp, r7
8007bce: f85d 7b04 ldr.w r7, [sp], #4
8007bd2: 4770 bx lr
08007bd4 <HAL_TIMEx_Break2Callback>:
* @brief Hall Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
8007bd4: b480 push {r7}
8007bd6: b083 sub sp, #12
8007bd8: af00 add r7, sp, #0
8007bda: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_Break2Callback could be implemented in the user file
*/
}
8007bdc: bf00 nop
8007bde: 370c adds r7, #12
8007be0: 46bd mov sp, r7
8007be2: f85d 7b04 ldr.w r7, [sp], #4
8007be6: 4770 bx lr
08007be8 <HAL_TIMEx_EncoderIndexCallback>:
* @brief Encoder index callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim)
{
8007be8: b480 push {r7}
8007bea: b083 sub sp, #12
8007bec: af00 add r7, sp, #0
8007bee: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file
*/
}
8007bf0: bf00 nop
8007bf2: 370c adds r7, #12
8007bf4: 46bd mov sp, r7
8007bf6: f85d 7b04 ldr.w r7, [sp], #4
8007bfa: 4770 bx lr
08007bfc <HAL_TIMEx_DirectionChangeCallback>:
* @brief Direction change callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim)
{
8007bfc: b480 push {r7}
8007bfe: b083 sub sp, #12
8007c00: af00 add r7, sp, #0
8007c02: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file
*/
}
8007c04: bf00 nop
8007c06: 370c adds r7, #12
8007c08: 46bd mov sp, r7
8007c0a: f85d 7b04 ldr.w r7, [sp], #4
8007c0e: 4770 bx lr
08007c10 <HAL_TIMEx_IndexErrorCallback>:
* @brief Index error callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim)
{
8007c10: b480 push {r7}
8007c12: b083 sub sp, #12
8007c14: af00 add r7, sp, #0
8007c16: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_IndexErrorCallback could be implemented in the user file
*/
}
8007c18: bf00 nop
8007c1a: 370c adds r7, #12
8007c1c: 46bd mov sp, r7
8007c1e: f85d 7b04 ldr.w r7, [sp], #4
8007c22: 4770 bx lr
08007c24 <HAL_TIMEx_TransitionErrorCallback>:
* @brief Transition error callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim)
{
8007c24: b480 push {r7}
8007c26: b083 sub sp, #12
8007c28: af00 add r7, sp, #0
8007c2a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file
*/
}
8007c2c: bf00 nop
8007c2e: 370c adds r7, #12
8007c30: 46bd mov sp, r7
8007c32: f85d 7b04 ldr.w r7, [sp], #4
8007c36: 4770 bx lr
08007c38 <__libc_init_array>:
8007c38: b570 push {r4, r5, r6, lr}
8007c3a: 4d0d ldr r5, [pc, #52] ; (8007c70 <__libc_init_array+0x38>)
8007c3c: 4c0d ldr r4, [pc, #52] ; (8007c74 <__libc_init_array+0x3c>)
8007c3e: 1b64 subs r4, r4, r5
8007c40: 10a4 asrs r4, r4, #2
8007c42: 2600 movs r6, #0
8007c44: 42a6 cmp r6, r4
8007c46: d109 bne.n 8007c5c <__libc_init_array+0x24>
8007c48: 4d0b ldr r5, [pc, #44] ; (8007c78 <__libc_init_array+0x40>)
8007c4a: 4c0c ldr r4, [pc, #48] ; (8007c7c <__libc_init_array+0x44>)
8007c4c: f000 f820 bl 8007c90 <_init>
8007c50: 1b64 subs r4, r4, r5
8007c52: 10a4 asrs r4, r4, #2
8007c54: 2600 movs r6, #0
8007c56: 42a6 cmp r6, r4
8007c58: d105 bne.n 8007c66 <__libc_init_array+0x2e>
8007c5a: bd70 pop {r4, r5, r6, pc}
8007c5c: f855 3b04 ldr.w r3, [r5], #4
8007c60: 4798 blx r3
8007c62: 3601 adds r6, #1
8007c64: e7ee b.n 8007c44 <__libc_init_array+0xc>
8007c66: f855 3b04 ldr.w r3, [r5], #4
8007c6a: 4798 blx r3
8007c6c: 3601 adds r6, #1
8007c6e: e7f2 b.n 8007c56 <__libc_init_array+0x1e>
8007c70: 08007cd0 .word 0x08007cd0
8007c74: 08007cd0 .word 0x08007cd0
8007c78: 08007cd0 .word 0x08007cd0
8007c7c: 08007cd4 .word 0x08007cd4
08007c80 <memset>:
8007c80: 4402 add r2, r0
8007c82: 4603 mov r3, r0
8007c84: 4293 cmp r3, r2
8007c86: d100 bne.n 8007c8a <memset+0xa>
8007c88: 4770 bx lr
8007c8a: f803 1b01 strb.w r1, [r3], #1
8007c8e: e7f9 b.n 8007c84 <memset+0x4>
08007c90 <_init>:
8007c90: b5f8 push {r3, r4, r5, r6, r7, lr}
8007c92: bf00 nop
8007c94: bcf8 pop {r3, r4, r5, r6, r7}
8007c96: bc08 pop {r3}
8007c98: 469e mov lr, r3
8007c9a: 4770 bx lr
08007c9c <_fini>:
8007c9c: b5f8 push {r3, r4, r5, r6, r7, lr}
8007c9e: bf00 nop
8007ca0: bcf8 pop {r3, r4, r5, r6, r7}
8007ca2: bc08 pop {r3}
8007ca4: 469e mov lr, r3
8007ca6: 4770 bx lr
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