ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "stm32f3xx_hal_cortex.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c"
20 .section .text.__NVIC_DisableIRQ,"ax",%progbits
21 .align 1
22 .syntax unified
23 .thumb
24 .thumb_func
26 __NVIC_DisableIRQ:
27 .LVL0:
28 .LFB106:
29 .file 2 "Drivers/CMSIS/Include/core_cm4.h"
1:Drivers/CMSIS/Include/core_cm4.h **** /**************************************************************************//**
2:Drivers/CMSIS/Include/core_cm4.h **** * @file core_cm4.h
3:Drivers/CMSIS/Include/core_cm4.h **** * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
4:Drivers/CMSIS/Include/core_cm4.h **** * @version V5.0.8
5:Drivers/CMSIS/Include/core_cm4.h **** * @date 04. June 2018
6:Drivers/CMSIS/Include/core_cm4.h **** ******************************************************************************/
7:Drivers/CMSIS/Include/core_cm4.h **** /*
8:Drivers/CMSIS/Include/core_cm4.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9:Drivers/CMSIS/Include/core_cm4.h **** *
10:Drivers/CMSIS/Include/core_cm4.h **** * SPDX-License-Identifier: Apache-2.0
11:Drivers/CMSIS/Include/core_cm4.h **** *
12:Drivers/CMSIS/Include/core_cm4.h **** * Licensed under the Apache License, Version 2.0 (the License); you may
13:Drivers/CMSIS/Include/core_cm4.h **** * not use this file except in compliance with the License.
14:Drivers/CMSIS/Include/core_cm4.h **** * You may obtain a copy of the License at
15:Drivers/CMSIS/Include/core_cm4.h **** *
16:Drivers/CMSIS/Include/core_cm4.h **** * www.apache.org/licenses/LICENSE-2.0
17:Drivers/CMSIS/Include/core_cm4.h **** *
18:Drivers/CMSIS/Include/core_cm4.h **** * Unless required by applicable law or agreed to in writing, software
19:Drivers/CMSIS/Include/core_cm4.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20:Drivers/CMSIS/Include/core_cm4.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21:Drivers/CMSIS/Include/core_cm4.h **** * See the License for the specific language governing permissions and
22:Drivers/CMSIS/Include/core_cm4.h **** * limitations under the License.
23:Drivers/CMSIS/Include/core_cm4.h **** */
24:Drivers/CMSIS/Include/core_cm4.h ****
25:Drivers/CMSIS/Include/core_cm4.h **** #if defined ( __ICCARM__ )
26:Drivers/CMSIS/Include/core_cm4.h **** #pragma system_include /* treat file as system include file for MISRA check */
27:Drivers/CMSIS/Include/core_cm4.h **** #elif defined (__clang__)
28:Drivers/CMSIS/Include/core_cm4.h **** #pragma clang system_header /* treat file as system include file */
29:Drivers/CMSIS/Include/core_cm4.h **** #endif
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30:Drivers/CMSIS/Include/core_cm4.h ****
31:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CORE_CM4_H_GENERIC
32:Drivers/CMSIS/Include/core_cm4.h **** #define __CORE_CM4_H_GENERIC
33:Drivers/CMSIS/Include/core_cm4.h ****
34:Drivers/CMSIS/Include/core_cm4.h **** #include <stdint.h>
35:Drivers/CMSIS/Include/core_cm4.h ****
36:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus
37:Drivers/CMSIS/Include/core_cm4.h **** extern "C" {
38:Drivers/CMSIS/Include/core_cm4.h **** #endif
39:Drivers/CMSIS/Include/core_cm4.h ****
40:Drivers/CMSIS/Include/core_cm4.h **** /**
41:Drivers/CMSIS/Include/core_cm4.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42:Drivers/CMSIS/Include/core_cm4.h **** CMSIS violates the following MISRA-C:2004 rules:
43:Drivers/CMSIS/Include/core_cm4.h ****
44:Drivers/CMSIS/Include/core_cm4.h **** \li Required Rule 8.5, object/function definition in header file.<br>
45:Drivers/CMSIS/Include/core_cm4.h **** Function definitions in header files are used to allow 'inlining'.
46:Drivers/CMSIS/Include/core_cm4.h ****
47:Drivers/CMSIS/Include/core_cm4.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48:Drivers/CMSIS/Include/core_cm4.h **** Unions are used for effective representation of core registers.
49:Drivers/CMSIS/Include/core_cm4.h ****
50:Drivers/CMSIS/Include/core_cm4.h **** \li Advisory Rule 19.7, Function-like macro defined.<br>
51:Drivers/CMSIS/Include/core_cm4.h **** Function-like macros are used to allow more efficient code.
52:Drivers/CMSIS/Include/core_cm4.h **** */
53:Drivers/CMSIS/Include/core_cm4.h ****
54:Drivers/CMSIS/Include/core_cm4.h ****
55:Drivers/CMSIS/Include/core_cm4.h **** /*******************************************************************************
56:Drivers/CMSIS/Include/core_cm4.h **** * CMSIS definitions
57:Drivers/CMSIS/Include/core_cm4.h **** ******************************************************************************/
58:Drivers/CMSIS/Include/core_cm4.h **** /**
59:Drivers/CMSIS/Include/core_cm4.h **** \ingroup Cortex_M4
60:Drivers/CMSIS/Include/core_cm4.h **** @{
61:Drivers/CMSIS/Include/core_cm4.h **** */
62:Drivers/CMSIS/Include/core_cm4.h ****
63:Drivers/CMSIS/Include/core_cm4.h **** #include "cmsis_version.h"
64:Drivers/CMSIS/Include/core_cm4.h ****
65:Drivers/CMSIS/Include/core_cm4.h **** /* CMSIS CM4 definitions */
66:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] C
67:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] C
68:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
69:Drivers/CMSIS/Include/core_cm4.h **** __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL
70:Drivers/CMSIS/Include/core_cm4.h ****
71:Drivers/CMSIS/Include/core_cm4.h **** #define __CORTEX_M (4U) /*!< Cortex-M Core */
72:Drivers/CMSIS/Include/core_cm4.h ****
73:Drivers/CMSIS/Include/core_cm4.h **** /** __FPU_USED indicates whether an FPU is used or not.
74:Drivers/CMSIS/Include/core_cm4.h **** For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun
75:Drivers/CMSIS/Include/core_cm4.h **** */
76:Drivers/CMSIS/Include/core_cm4.h **** #if defined ( __CC_ARM )
77:Drivers/CMSIS/Include/core_cm4.h **** #if defined __TARGET_FPU_VFP
78:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
79:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U
80:Drivers/CMSIS/Include/core_cm4.h **** #else
81:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
82:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U
83:Drivers/CMSIS/Include/core_cm4.h **** #endif
84:Drivers/CMSIS/Include/core_cm4.h **** #else
85:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U
86:Drivers/CMSIS/Include/core_cm4.h **** #endif
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87:Drivers/CMSIS/Include/core_cm4.h ****
88:Drivers/CMSIS/Include/core_cm4.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
89:Drivers/CMSIS/Include/core_cm4.h **** #if defined __ARM_PCS_VFP
90:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
91:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U
92:Drivers/CMSIS/Include/core_cm4.h **** #else
93:Drivers/CMSIS/Include/core_cm4.h **** #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN
94:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U
95:Drivers/CMSIS/Include/core_cm4.h **** #endif
96:Drivers/CMSIS/Include/core_cm4.h **** #else
97:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U
98:Drivers/CMSIS/Include/core_cm4.h **** #endif
99:Drivers/CMSIS/Include/core_cm4.h ****
100:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __GNUC__ )
101:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__)
102:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
103:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U
104:Drivers/CMSIS/Include/core_cm4.h **** #else
105:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
106:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U
107:Drivers/CMSIS/Include/core_cm4.h **** #endif
108:Drivers/CMSIS/Include/core_cm4.h **** #else
109:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U
110:Drivers/CMSIS/Include/core_cm4.h **** #endif
111:Drivers/CMSIS/Include/core_cm4.h ****
112:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __ICCARM__ )
113:Drivers/CMSIS/Include/core_cm4.h **** #if defined __ARMVFP__
114:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
115:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U
116:Drivers/CMSIS/Include/core_cm4.h **** #else
117:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
118:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U
119:Drivers/CMSIS/Include/core_cm4.h **** #endif
120:Drivers/CMSIS/Include/core_cm4.h **** #else
121:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U
122:Drivers/CMSIS/Include/core_cm4.h **** #endif
123:Drivers/CMSIS/Include/core_cm4.h ****
124:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __TI_ARM__ )
125:Drivers/CMSIS/Include/core_cm4.h **** #if defined __TI_VFP_SUPPORT__
126:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
127:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U
128:Drivers/CMSIS/Include/core_cm4.h **** #else
129:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
130:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U
131:Drivers/CMSIS/Include/core_cm4.h **** #endif
132:Drivers/CMSIS/Include/core_cm4.h **** #else
133:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U
134:Drivers/CMSIS/Include/core_cm4.h **** #endif
135:Drivers/CMSIS/Include/core_cm4.h ****
136:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __TASKING__ )
137:Drivers/CMSIS/Include/core_cm4.h **** #if defined __FPU_VFP__
138:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
139:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U
140:Drivers/CMSIS/Include/core_cm4.h **** #else
141:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
142:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U
143:Drivers/CMSIS/Include/core_cm4.h **** #endif
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144:Drivers/CMSIS/Include/core_cm4.h **** #else
145:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U
146:Drivers/CMSIS/Include/core_cm4.h **** #endif
147:Drivers/CMSIS/Include/core_cm4.h ****
148:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __CSMC__ )
149:Drivers/CMSIS/Include/core_cm4.h **** #if ( __CSMC__ & 0x400U)
150:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
151:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U
152:Drivers/CMSIS/Include/core_cm4.h **** #else
153:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
154:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U
155:Drivers/CMSIS/Include/core_cm4.h **** #endif
156:Drivers/CMSIS/Include/core_cm4.h **** #else
157:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U
158:Drivers/CMSIS/Include/core_cm4.h **** #endif
159:Drivers/CMSIS/Include/core_cm4.h ****
160:Drivers/CMSIS/Include/core_cm4.h **** #endif
161:Drivers/CMSIS/Include/core_cm4.h ****
162:Drivers/CMSIS/Include/core_cm4.h **** #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
163:Drivers/CMSIS/Include/core_cm4.h ****
164:Drivers/CMSIS/Include/core_cm4.h ****
165:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus
166:Drivers/CMSIS/Include/core_cm4.h **** }
167:Drivers/CMSIS/Include/core_cm4.h **** #endif
168:Drivers/CMSIS/Include/core_cm4.h ****
169:Drivers/CMSIS/Include/core_cm4.h **** #endif /* __CORE_CM4_H_GENERIC */
170:Drivers/CMSIS/Include/core_cm4.h ****
171:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CMSIS_GENERIC
172:Drivers/CMSIS/Include/core_cm4.h ****
173:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CORE_CM4_H_DEPENDANT
174:Drivers/CMSIS/Include/core_cm4.h **** #define __CORE_CM4_H_DEPENDANT
175:Drivers/CMSIS/Include/core_cm4.h ****
176:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus
177:Drivers/CMSIS/Include/core_cm4.h **** extern "C" {
178:Drivers/CMSIS/Include/core_cm4.h **** #endif
179:Drivers/CMSIS/Include/core_cm4.h ****
180:Drivers/CMSIS/Include/core_cm4.h **** /* check device defines and use defaults */
181:Drivers/CMSIS/Include/core_cm4.h **** #if defined __CHECK_DEVICE_DEFINES
182:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CM4_REV
183:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_REV 0x0000U
184:Drivers/CMSIS/Include/core_cm4.h **** #warning "__CM4_REV not defined in device header file; using default!"
185:Drivers/CMSIS/Include/core_cm4.h **** #endif
186:Drivers/CMSIS/Include/core_cm4.h ****
187:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __FPU_PRESENT
188:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_PRESENT 0U
189:Drivers/CMSIS/Include/core_cm4.h **** #warning "__FPU_PRESENT not defined in device header file; using default!"
190:Drivers/CMSIS/Include/core_cm4.h **** #endif
191:Drivers/CMSIS/Include/core_cm4.h ****
192:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __MPU_PRESENT
193:Drivers/CMSIS/Include/core_cm4.h **** #define __MPU_PRESENT 0U
194:Drivers/CMSIS/Include/core_cm4.h **** #warning "__MPU_PRESENT not defined in device header file; using default!"
195:Drivers/CMSIS/Include/core_cm4.h **** #endif
196:Drivers/CMSIS/Include/core_cm4.h ****
197:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __NVIC_PRIO_BITS
198:Drivers/CMSIS/Include/core_cm4.h **** #define __NVIC_PRIO_BITS 3U
199:Drivers/CMSIS/Include/core_cm4.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
200:Drivers/CMSIS/Include/core_cm4.h **** #endif
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201:Drivers/CMSIS/Include/core_cm4.h ****
202:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __Vendor_SysTickConfig
203:Drivers/CMSIS/Include/core_cm4.h **** #define __Vendor_SysTickConfig 0U
204:Drivers/CMSIS/Include/core_cm4.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
205:Drivers/CMSIS/Include/core_cm4.h **** #endif
206:Drivers/CMSIS/Include/core_cm4.h **** #endif
207:Drivers/CMSIS/Include/core_cm4.h ****
208:Drivers/CMSIS/Include/core_cm4.h **** /* IO definitions (access restrictions to peripheral registers) */
209:Drivers/CMSIS/Include/core_cm4.h **** /**
210:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines
211:Drivers/CMSIS/Include/core_cm4.h ****
212:Drivers/CMSIS/Include/core_cm4.h **** <strong>IO Type Qualifiers</strong> are used
213:Drivers/CMSIS/Include/core_cm4.h **** \li to specify the access to peripheral variables.
214:Drivers/CMSIS/Include/core_cm4.h **** \li for automatic generation of peripheral register debug information.
215:Drivers/CMSIS/Include/core_cm4.h **** */
216:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus
217:Drivers/CMSIS/Include/core_cm4.h **** #define __I volatile /*!< Defines 'read only' permissions */
218:Drivers/CMSIS/Include/core_cm4.h **** #else
219:Drivers/CMSIS/Include/core_cm4.h **** #define __I volatile const /*!< Defines 'read only' permissions */
220:Drivers/CMSIS/Include/core_cm4.h **** #endif
221:Drivers/CMSIS/Include/core_cm4.h **** #define __O volatile /*!< Defines 'write only' permissions */
222:Drivers/CMSIS/Include/core_cm4.h **** #define __IO volatile /*!< Defines 'read / write' permissions */
223:Drivers/CMSIS/Include/core_cm4.h ****
224:Drivers/CMSIS/Include/core_cm4.h **** /* following defines should be used for structure members */
225:Drivers/CMSIS/Include/core_cm4.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */
226:Drivers/CMSIS/Include/core_cm4.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */
227:Drivers/CMSIS/Include/core_cm4.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */
228:Drivers/CMSIS/Include/core_cm4.h ****
229:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group Cortex_M4 */
230:Drivers/CMSIS/Include/core_cm4.h ****
231:Drivers/CMSIS/Include/core_cm4.h ****
232:Drivers/CMSIS/Include/core_cm4.h ****
233:Drivers/CMSIS/Include/core_cm4.h **** /*******************************************************************************
234:Drivers/CMSIS/Include/core_cm4.h **** * Register Abstraction
235:Drivers/CMSIS/Include/core_cm4.h **** Core Register contain:
236:Drivers/CMSIS/Include/core_cm4.h **** - Core Register
237:Drivers/CMSIS/Include/core_cm4.h **** - Core NVIC Register
238:Drivers/CMSIS/Include/core_cm4.h **** - Core SCB Register
239:Drivers/CMSIS/Include/core_cm4.h **** - Core SysTick Register
240:Drivers/CMSIS/Include/core_cm4.h **** - Core Debug Register
241:Drivers/CMSIS/Include/core_cm4.h **** - Core MPU Register
242:Drivers/CMSIS/Include/core_cm4.h **** - Core FPU Register
243:Drivers/CMSIS/Include/core_cm4.h **** ******************************************************************************/
244:Drivers/CMSIS/Include/core_cm4.h **** /**
245:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_core_register Defines and Type Definitions
246:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions and defines for Cortex-M processor based devices.
247:Drivers/CMSIS/Include/core_cm4.h **** */
248:Drivers/CMSIS/Include/core_cm4.h ****
249:Drivers/CMSIS/Include/core_cm4.h **** /**
250:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register
251:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_CORE Status and Control Registers
252:Drivers/CMSIS/Include/core_cm4.h **** \brief Core Register type definitions.
253:Drivers/CMSIS/Include/core_cm4.h **** @{
254:Drivers/CMSIS/Include/core_cm4.h **** */
255:Drivers/CMSIS/Include/core_cm4.h ****
256:Drivers/CMSIS/Include/core_cm4.h **** /**
257:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Application Program Status Register (APSR).
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258:Drivers/CMSIS/Include/core_cm4.h **** */
259:Drivers/CMSIS/Include/core_cm4.h **** typedef union
260:Drivers/CMSIS/Include/core_cm4.h **** {
261:Drivers/CMSIS/Include/core_cm4.h **** struct
262:Drivers/CMSIS/Include/core_cm4.h **** {
263:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
264:Drivers/CMSIS/Include/core_cm4.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
265:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
266:Drivers/CMSIS/Include/core_cm4.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
267:Drivers/CMSIS/Include/core_cm4.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
268:Drivers/CMSIS/Include/core_cm4.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */
269:Drivers/CMSIS/Include/core_cm4.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
270:Drivers/CMSIS/Include/core_cm4.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */
271:Drivers/CMSIS/Include/core_cm4.h **** } b; /*!< Structure used for bit access */
272:Drivers/CMSIS/Include/core_cm4.h **** uint32_t w; /*!< Type used for word access */
273:Drivers/CMSIS/Include/core_cm4.h **** } APSR_Type;
274:Drivers/CMSIS/Include/core_cm4.h ****
275:Drivers/CMSIS/Include/core_cm4.h **** /* APSR Register Definitions */
276:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_N_Pos 31U /*!< APSR
277:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR
278:Drivers/CMSIS/Include/core_cm4.h ****
279:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Z_Pos 30U /*!< APSR
280:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR
281:Drivers/CMSIS/Include/core_cm4.h ****
282:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_C_Pos 29U /*!< APSR
283:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR
284:Drivers/CMSIS/Include/core_cm4.h ****
285:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_V_Pos 28U /*!< APSR
286:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR
287:Drivers/CMSIS/Include/core_cm4.h ****
288:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Q_Pos 27U /*!< APSR
289:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR
290:Drivers/CMSIS/Include/core_cm4.h ****
291:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_GE_Pos 16U /*!< APSR
292:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR
293:Drivers/CMSIS/Include/core_cm4.h ****
294:Drivers/CMSIS/Include/core_cm4.h ****
295:Drivers/CMSIS/Include/core_cm4.h **** /**
296:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Interrupt Program Status Register (IPSR).
297:Drivers/CMSIS/Include/core_cm4.h **** */
298:Drivers/CMSIS/Include/core_cm4.h **** typedef union
299:Drivers/CMSIS/Include/core_cm4.h **** {
300:Drivers/CMSIS/Include/core_cm4.h **** struct
301:Drivers/CMSIS/Include/core_cm4.h **** {
302:Drivers/CMSIS/Include/core_cm4.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
303:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
304:Drivers/CMSIS/Include/core_cm4.h **** } b; /*!< Structure used for bit access */
305:Drivers/CMSIS/Include/core_cm4.h **** uint32_t w; /*!< Type used for word access */
306:Drivers/CMSIS/Include/core_cm4.h **** } IPSR_Type;
307:Drivers/CMSIS/Include/core_cm4.h ****
308:Drivers/CMSIS/Include/core_cm4.h **** /* IPSR Register Definitions */
309:Drivers/CMSIS/Include/core_cm4.h **** #define IPSR_ISR_Pos 0U /*!< IPSR
310:Drivers/CMSIS/Include/core_cm4.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR
311:Drivers/CMSIS/Include/core_cm4.h ****
312:Drivers/CMSIS/Include/core_cm4.h ****
313:Drivers/CMSIS/Include/core_cm4.h **** /**
314:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 7
315:Drivers/CMSIS/Include/core_cm4.h **** */
316:Drivers/CMSIS/Include/core_cm4.h **** typedef union
317:Drivers/CMSIS/Include/core_cm4.h **** {
318:Drivers/CMSIS/Include/core_cm4.h **** struct
319:Drivers/CMSIS/Include/core_cm4.h **** {
320:Drivers/CMSIS/Include/core_cm4.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
321:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved0:1; /*!< bit: 9 Reserved */
322:Drivers/CMSIS/Include/core_cm4.h **** uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
323:Drivers/CMSIS/Include/core_cm4.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
324:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
325:Drivers/CMSIS/Include/core_cm4.h **** uint32_t T:1; /*!< bit: 24 Thumb bit */
326:Drivers/CMSIS/Include/core_cm4.h **** uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
327:Drivers/CMSIS/Include/core_cm4.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
328:Drivers/CMSIS/Include/core_cm4.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
329:Drivers/CMSIS/Include/core_cm4.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */
330:Drivers/CMSIS/Include/core_cm4.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
331:Drivers/CMSIS/Include/core_cm4.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */
332:Drivers/CMSIS/Include/core_cm4.h **** } b; /*!< Structure used for bit access */
333:Drivers/CMSIS/Include/core_cm4.h **** uint32_t w; /*!< Type used for word access */
334:Drivers/CMSIS/Include/core_cm4.h **** } xPSR_Type;
335:Drivers/CMSIS/Include/core_cm4.h ****
336:Drivers/CMSIS/Include/core_cm4.h **** /* xPSR Register Definitions */
337:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_N_Pos 31U /*!< xPSR
338:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR
339:Drivers/CMSIS/Include/core_cm4.h ****
340:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Z_Pos 30U /*!< xPSR
341:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR
342:Drivers/CMSIS/Include/core_cm4.h ****
343:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_C_Pos 29U /*!< xPSR
344:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR
345:Drivers/CMSIS/Include/core_cm4.h ****
346:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_V_Pos 28U /*!< xPSR
347:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR
348:Drivers/CMSIS/Include/core_cm4.h ****
349:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Q_Pos 27U /*!< xPSR
350:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR
351:Drivers/CMSIS/Include/core_cm4.h ****
352:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR
353:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR
354:Drivers/CMSIS/Include/core_cm4.h ****
355:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_T_Pos 24U /*!< xPSR
356:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR
357:Drivers/CMSIS/Include/core_cm4.h ****
358:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_GE_Pos 16U /*!< xPSR
359:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR
360:Drivers/CMSIS/Include/core_cm4.h ****
361:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR
362:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR
363:Drivers/CMSIS/Include/core_cm4.h ****
364:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ISR_Pos 0U /*!< xPSR
365:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR
366:Drivers/CMSIS/Include/core_cm4.h ****
367:Drivers/CMSIS/Include/core_cm4.h ****
368:Drivers/CMSIS/Include/core_cm4.h **** /**
369:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Control Registers (CONTROL).
370:Drivers/CMSIS/Include/core_cm4.h **** */
371:Drivers/CMSIS/Include/core_cm4.h **** typedef union
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 8
372:Drivers/CMSIS/Include/core_cm4.h **** {
373:Drivers/CMSIS/Include/core_cm4.h **** struct
374:Drivers/CMSIS/Include/core_cm4.h **** {
375:Drivers/CMSIS/Include/core_cm4.h **** uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
376:Drivers/CMSIS/Include/core_cm4.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
377:Drivers/CMSIS/Include/core_cm4.h **** uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
378:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
379:Drivers/CMSIS/Include/core_cm4.h **** } b; /*!< Structure used for bit access */
380:Drivers/CMSIS/Include/core_cm4.h **** uint32_t w; /*!< Type used for word access */
381:Drivers/CMSIS/Include/core_cm4.h **** } CONTROL_Type;
382:Drivers/CMSIS/Include/core_cm4.h ****
383:Drivers/CMSIS/Include/core_cm4.h **** /* CONTROL Register Definitions */
384:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_FPCA_Pos 2U /*!< CONT
385:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONT
386:Drivers/CMSIS/Include/core_cm4.h ****
387:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT
388:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT
389:Drivers/CMSIS/Include/core_cm4.h ****
390:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_nPRIV_Pos 0U /*!< CONT
391:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONT
392:Drivers/CMSIS/Include/core_cm4.h ****
393:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_CORE */
394:Drivers/CMSIS/Include/core_cm4.h ****
395:Drivers/CMSIS/Include/core_cm4.h ****
396:Drivers/CMSIS/Include/core_cm4.h **** /**
397:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register
398:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
399:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the NVIC Registers
400:Drivers/CMSIS/Include/core_cm4.h **** @{
401:Drivers/CMSIS/Include/core_cm4.h **** */
402:Drivers/CMSIS/Include/core_cm4.h ****
403:Drivers/CMSIS/Include/core_cm4.h **** /**
404:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
405:Drivers/CMSIS/Include/core_cm4.h **** */
406:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
407:Drivers/CMSIS/Include/core_cm4.h **** {
408:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
409:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[24U];
410:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register
411:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RSERVED1[24U];
412:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register *
413:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[24U];
414:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register
415:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED3[24U];
416:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
417:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED4[56U];
418:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bi
419:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED5[644U];
420:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regis
421:Drivers/CMSIS/Include/core_cm4.h **** } NVIC_Type;
422:Drivers/CMSIS/Include/core_cm4.h ****
423:Drivers/CMSIS/Include/core_cm4.h **** /* Software Triggered Interrupt Register Definitions */
424:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_STIR_INTID_Pos 0U /*!< STIR: I
425:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: I
426:Drivers/CMSIS/Include/core_cm4.h ****
427:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_NVIC */
428:Drivers/CMSIS/Include/core_cm4.h ****
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429:Drivers/CMSIS/Include/core_cm4.h ****
430:Drivers/CMSIS/Include/core_cm4.h **** /**
431:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register
432:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_SCB System Control Block (SCB)
433:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the System Control Block Registers
434:Drivers/CMSIS/Include/core_cm4.h **** @{
435:Drivers/CMSIS/Include/core_cm4.h **** */
436:Drivers/CMSIS/Include/core_cm4.h ****
437:Drivers/CMSIS/Include/core_cm4.h **** /**
438:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the System Control Block (SCB).
439:Drivers/CMSIS/Include/core_cm4.h **** */
440:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
441:Drivers/CMSIS/Include/core_cm4.h **** {
442:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
443:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi
444:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
445:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset
446:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
447:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register *
448:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registe
449:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State
450:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Regist
451:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
452:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
453:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register
454:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
455:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register
456:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
457:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
458:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
459:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
460:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regis
461:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[5U];
462:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regis
463:Drivers/CMSIS/Include/core_cm4.h **** } SCB_Type;
464:Drivers/CMSIS/Include/core_cm4.h ****
465:Drivers/CMSIS/Include/core_cm4.h **** /* SCB CPUID Register Definitions */
466:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB
467:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB
468:Drivers/CMSIS/Include/core_cm4.h ****
469:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB
470:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB
471:Drivers/CMSIS/Include/core_cm4.h ****
472:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB
473:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB
474:Drivers/CMSIS/Include/core_cm4.h ****
475:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB
476:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB
477:Drivers/CMSIS/Include/core_cm4.h ****
478:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB
479:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB
480:Drivers/CMSIS/Include/core_cm4.h ****
481:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Interrupt Control State Register Definitions */
482:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB
483:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB
484:Drivers/CMSIS/Include/core_cm4.h ****
485:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 10
486:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB
487:Drivers/CMSIS/Include/core_cm4.h ****
488:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB
489:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB
490:Drivers/CMSIS/Include/core_cm4.h ****
491:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB
492:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB
493:Drivers/CMSIS/Include/core_cm4.h ****
494:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB
495:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB
496:Drivers/CMSIS/Include/core_cm4.h ****
497:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB
498:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB
499:Drivers/CMSIS/Include/core_cm4.h ****
500:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB
501:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB
502:Drivers/CMSIS/Include/core_cm4.h ****
503:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB
504:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB
505:Drivers/CMSIS/Include/core_cm4.h ****
506:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB
507:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB
508:Drivers/CMSIS/Include/core_cm4.h ****
509:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB
510:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB
511:Drivers/CMSIS/Include/core_cm4.h ****
512:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Vector Table Offset Register Definitions */
513:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB
514:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB
515:Drivers/CMSIS/Include/core_cm4.h ****
516:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Application Interrupt and Reset Control Register Definitions */
517:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB
518:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB
519:Drivers/CMSIS/Include/core_cm4.h ****
520:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB
521:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB
522:Drivers/CMSIS/Include/core_cm4.h ****
523:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB
524:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB
525:Drivers/CMSIS/Include/core_cm4.h ****
526:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB
527:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB
528:Drivers/CMSIS/Include/core_cm4.h ****
529:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB
530:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB
531:Drivers/CMSIS/Include/core_cm4.h ****
532:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB
533:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB
534:Drivers/CMSIS/Include/core_cm4.h ****
535:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB
536:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB
537:Drivers/CMSIS/Include/core_cm4.h ****
538:Drivers/CMSIS/Include/core_cm4.h **** /* SCB System Control Register Definitions */
539:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB
540:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB
541:Drivers/CMSIS/Include/core_cm4.h ****
542:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 11
543:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB
544:Drivers/CMSIS/Include/core_cm4.h ****
545:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB
546:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB
547:Drivers/CMSIS/Include/core_cm4.h ****
548:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Configuration Control Register Definitions */
549:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB
550:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB
551:Drivers/CMSIS/Include/core_cm4.h ****
552:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB
553:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB
554:Drivers/CMSIS/Include/core_cm4.h ****
555:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB
556:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB
557:Drivers/CMSIS/Include/core_cm4.h ****
558:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB
559:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB
560:Drivers/CMSIS/Include/core_cm4.h ****
561:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB
562:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB
563:Drivers/CMSIS/Include/core_cm4.h ****
564:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB
565:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB
566:Drivers/CMSIS/Include/core_cm4.h ****
567:Drivers/CMSIS/Include/core_cm4.h **** /* SCB System Handler Control and State Register Definitions */
568:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB
569:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB
570:Drivers/CMSIS/Include/core_cm4.h ****
571:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB
572:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB
573:Drivers/CMSIS/Include/core_cm4.h ****
574:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB
575:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB
576:Drivers/CMSIS/Include/core_cm4.h ****
577:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB
578:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB
579:Drivers/CMSIS/Include/core_cm4.h ****
580:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB
581:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB
582:Drivers/CMSIS/Include/core_cm4.h ****
583:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB
584:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB
585:Drivers/CMSIS/Include/core_cm4.h ****
586:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB
587:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB
588:Drivers/CMSIS/Include/core_cm4.h ****
589:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB
590:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB
591:Drivers/CMSIS/Include/core_cm4.h ****
592:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB
593:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB
594:Drivers/CMSIS/Include/core_cm4.h ****
595:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB
596:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB
597:Drivers/CMSIS/Include/core_cm4.h ****
598:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB
599:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB
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600:Drivers/CMSIS/Include/core_cm4.h ****
601:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB
602:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB
603:Drivers/CMSIS/Include/core_cm4.h ****
604:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB
605:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB
606:Drivers/CMSIS/Include/core_cm4.h ****
607:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB
608:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB
609:Drivers/CMSIS/Include/core_cm4.h ****
610:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Configurable Fault Status Register Definitions */
611:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB
612:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB
613:Drivers/CMSIS/Include/core_cm4.h ****
614:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB
615:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB
616:Drivers/CMSIS/Include/core_cm4.h ****
617:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB
618:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB
619:Drivers/CMSIS/Include/core_cm4.h ****
620:Drivers/CMSIS/Include/core_cm4.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
621:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB
622:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB
623:Drivers/CMSIS/Include/core_cm4.h ****
624:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB
625:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB
626:Drivers/CMSIS/Include/core_cm4.h ****
627:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB
628:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB
629:Drivers/CMSIS/Include/core_cm4.h ****
630:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB
631:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB
632:Drivers/CMSIS/Include/core_cm4.h ****
633:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB
634:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB
635:Drivers/CMSIS/Include/core_cm4.h ****
636:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB
637:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB
638:Drivers/CMSIS/Include/core_cm4.h ****
639:Drivers/CMSIS/Include/core_cm4.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
640:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB
641:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB
642:Drivers/CMSIS/Include/core_cm4.h ****
643:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB
644:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB
645:Drivers/CMSIS/Include/core_cm4.h ****
646:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB
647:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB
648:Drivers/CMSIS/Include/core_cm4.h ****
649:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB
650:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB
651:Drivers/CMSIS/Include/core_cm4.h ****
652:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB
653:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB
654:Drivers/CMSIS/Include/core_cm4.h ****
655:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB
656:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB
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657:Drivers/CMSIS/Include/core_cm4.h ****
658:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB
659:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB
660:Drivers/CMSIS/Include/core_cm4.h ****
661:Drivers/CMSIS/Include/core_cm4.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
662:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB
663:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB
664:Drivers/CMSIS/Include/core_cm4.h ****
665:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB
666:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB
667:Drivers/CMSIS/Include/core_cm4.h ****
668:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB
669:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB
670:Drivers/CMSIS/Include/core_cm4.h ****
671:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB
672:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB
673:Drivers/CMSIS/Include/core_cm4.h ****
674:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB
675:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB
676:Drivers/CMSIS/Include/core_cm4.h ****
677:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB
678:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB
679:Drivers/CMSIS/Include/core_cm4.h ****
680:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Hard Fault Status Register Definitions */
681:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB
682:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB
683:Drivers/CMSIS/Include/core_cm4.h ****
684:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_FORCED_Pos 30U /*!< SCB
685:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB
686:Drivers/CMSIS/Include/core_cm4.h ****
687:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB
688:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB
689:Drivers/CMSIS/Include/core_cm4.h ****
690:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Debug Fault Status Register Definitions */
691:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB
692:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB
693:Drivers/CMSIS/Include/core_cm4.h ****
694:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB
695:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB
696:Drivers/CMSIS/Include/core_cm4.h ****
697:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB
698:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB
699:Drivers/CMSIS/Include/core_cm4.h ****
700:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_BKPT_Pos 1U /*!< SCB
701:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB
702:Drivers/CMSIS/Include/core_cm4.h ****
703:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_HALTED_Pos 0U /*!< SCB
704:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB
705:Drivers/CMSIS/Include/core_cm4.h ****
706:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SCB */
707:Drivers/CMSIS/Include/core_cm4.h ****
708:Drivers/CMSIS/Include/core_cm4.h ****
709:Drivers/CMSIS/Include/core_cm4.h **** /**
710:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register
711:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
712:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the System Control and ID Register not in the SCB
713:Drivers/CMSIS/Include/core_cm4.h **** @{
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714:Drivers/CMSIS/Include/core_cm4.h **** */
715:Drivers/CMSIS/Include/core_cm4.h ****
716:Drivers/CMSIS/Include/core_cm4.h **** /**
717:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the System Control and ID Register not in the SCB.
718:Drivers/CMSIS/Include/core_cm4.h **** */
719:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
720:Drivers/CMSIS/Include/core_cm4.h **** {
721:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[1U];
722:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Regist
723:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
724:Drivers/CMSIS/Include/core_cm4.h **** } SCnSCB_Type;
725:Drivers/CMSIS/Include/core_cm4.h ****
726:Drivers/CMSIS/Include/core_cm4.h **** /* Interrupt Controller Type Register Definitions */
727:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: I
728:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: I
729:Drivers/CMSIS/Include/core_cm4.h ****
730:Drivers/CMSIS/Include/core_cm4.h **** /* Auxiliary Control Register Definitions */
731:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR:
732:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR:
733:Drivers/CMSIS/Include/core_cm4.h ****
734:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR:
735:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR:
736:Drivers/CMSIS/Include/core_cm4.h ****
737:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR:
738:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR:
739:Drivers/CMSIS/Include/core_cm4.h ****
740:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR:
741:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR:
742:Drivers/CMSIS/Include/core_cm4.h ****
743:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR:
744:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR:
745:Drivers/CMSIS/Include/core_cm4.h ****
746:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SCnotSCB */
747:Drivers/CMSIS/Include/core_cm4.h ****
748:Drivers/CMSIS/Include/core_cm4.h ****
749:Drivers/CMSIS/Include/core_cm4.h **** /**
750:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register
751:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick)
752:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the System Timer Registers.
753:Drivers/CMSIS/Include/core_cm4.h **** @{
754:Drivers/CMSIS/Include/core_cm4.h **** */
755:Drivers/CMSIS/Include/core_cm4.h ****
756:Drivers/CMSIS/Include/core_cm4.h **** /**
757:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the System Timer (SysTick).
758:Drivers/CMSIS/Include/core_cm4.h **** */
759:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
760:Drivers/CMSIS/Include/core_cm4.h **** {
761:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis
762:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
763:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register *
764:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
765:Drivers/CMSIS/Include/core_cm4.h **** } SysTick_Type;
766:Drivers/CMSIS/Include/core_cm4.h ****
767:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Control / Status Register Definitions */
768:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT
769:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT
770:Drivers/CMSIS/Include/core_cm4.h ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 15
771:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT
772:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT
773:Drivers/CMSIS/Include/core_cm4.h ****
774:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT
775:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT
776:Drivers/CMSIS/Include/core_cm4.h ****
777:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT
778:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT
779:Drivers/CMSIS/Include/core_cm4.h ****
780:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Reload Register Definitions */
781:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT
782:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT
783:Drivers/CMSIS/Include/core_cm4.h ****
784:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Current Register Definitions */
785:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT
786:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT
787:Drivers/CMSIS/Include/core_cm4.h ****
788:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Calibration Register Definitions */
789:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT
790:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT
791:Drivers/CMSIS/Include/core_cm4.h ****
792:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT
793:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT
794:Drivers/CMSIS/Include/core_cm4.h ****
795:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT
796:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT
797:Drivers/CMSIS/Include/core_cm4.h ****
798:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SysTick */
799:Drivers/CMSIS/Include/core_cm4.h ****
800:Drivers/CMSIS/Include/core_cm4.h ****
801:Drivers/CMSIS/Include/core_cm4.h **** /**
802:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register
803:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
804:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
805:Drivers/CMSIS/Include/core_cm4.h **** @{
806:Drivers/CMSIS/Include/core_cm4.h **** */
807:Drivers/CMSIS/Include/core_cm4.h ****
808:Drivers/CMSIS/Include/core_cm4.h **** /**
809:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
810:Drivers/CMSIS/Include/core_cm4.h **** */
811:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
812:Drivers/CMSIS/Include/core_cm4.h **** {
813:Drivers/CMSIS/Include/core_cm4.h **** __OM union
814:Drivers/CMSIS/Include/core_cm4.h **** {
815:Drivers/CMSIS/Include/core_cm4.h **** __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
816:Drivers/CMSIS/Include/core_cm4.h **** __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
817:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
818:Drivers/CMSIS/Include/core_cm4.h **** } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
819:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[864U];
820:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
821:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED1[15U];
822:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
823:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[15U];
824:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
825:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED3[29U];
826:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register *
827:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 16
828:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Reg
829:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED4[43U];
830:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
831:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
832:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED5[6U];
833:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Re
834:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Re
835:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Re
836:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Re
837:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Re
838:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Re
839:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Re
840:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Re
841:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Re
842:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Re
843:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Re
844:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Re
845:Drivers/CMSIS/Include/core_cm4.h **** } ITM_Type;
846:Drivers/CMSIS/Include/core_cm4.h ****
847:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Trace Privilege Register Definitions */
848:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM
849:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM
850:Drivers/CMSIS/Include/core_cm4.h ****
851:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Trace Control Register Definitions */
852:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_BUSY_Pos 23U /*!< ITM
853:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM
854:Drivers/CMSIS/Include/core_cm4.h ****
855:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM
856:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM
857:Drivers/CMSIS/Include/core_cm4.h ****
858:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM
859:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM
860:Drivers/CMSIS/Include/core_cm4.h ****
861:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM
862:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM
863:Drivers/CMSIS/Include/core_cm4.h ****
864:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SWOENA_Pos 4U /*!< ITM
865:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM
866:Drivers/CMSIS/Include/core_cm4.h ****
867:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_DWTENA_Pos 3U /*!< ITM
868:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM
869:Drivers/CMSIS/Include/core_cm4.h ****
870:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM
871:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM
872:Drivers/CMSIS/Include/core_cm4.h ****
873:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSENA_Pos 1U /*!< ITM
874:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM
875:Drivers/CMSIS/Include/core_cm4.h ****
876:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_ITMENA_Pos 0U /*!< ITM
877:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM
878:Drivers/CMSIS/Include/core_cm4.h ****
879:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Integration Write Register Definitions */
880:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM
881:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM
882:Drivers/CMSIS/Include/core_cm4.h ****
883:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Integration Read Register Definitions */
884:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 17
885:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM
886:Drivers/CMSIS/Include/core_cm4.h ****
887:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Integration Mode Control Register Definitions */
888:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM
889:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM
890:Drivers/CMSIS/Include/core_cm4.h ****
891:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Lock Status Register Definitions */
892:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM
893:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM
894:Drivers/CMSIS/Include/core_cm4.h ****
895:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Access_Pos 1U /*!< ITM
896:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM
897:Drivers/CMSIS/Include/core_cm4.h ****
898:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Present_Pos 0U /*!< ITM
899:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM
900:Drivers/CMSIS/Include/core_cm4.h ****
901:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_ITM */
902:Drivers/CMSIS/Include/core_cm4.h ****
903:Drivers/CMSIS/Include/core_cm4.h ****
904:Drivers/CMSIS/Include/core_cm4.h **** /**
905:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register
906:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
907:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Data Watchpoint and Trace (DWT)
908:Drivers/CMSIS/Include/core_cm4.h **** @{
909:Drivers/CMSIS/Include/core_cm4.h **** */
910:Drivers/CMSIS/Include/core_cm4.h ****
911:Drivers/CMSIS/Include/core_cm4.h **** /**
912:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
913:Drivers/CMSIS/Include/core_cm4.h **** */
914:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
915:Drivers/CMSIS/Include/core_cm4.h **** {
916:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
917:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
918:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
919:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Registe
920:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
921:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
922:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Registe
923:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register
924:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
925:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
926:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
927:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[1U];
928:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
929:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
930:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
931:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED1[1U];
932:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
933:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
934:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
935:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[1U];
936:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
937:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
938:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
939:Drivers/CMSIS/Include/core_cm4.h **** } DWT_Type;
940:Drivers/CMSIS/Include/core_cm4.h ****
941:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Control Register Definitions */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 18
942:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTR
943:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTR
944:Drivers/CMSIS/Include/core_cm4.h ****
945:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTR
946:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTR
947:Drivers/CMSIS/Include/core_cm4.h ****
948:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTR
949:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTR
950:Drivers/CMSIS/Include/core_cm4.h ****
951:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTR
952:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTR
953:Drivers/CMSIS/Include/core_cm4.h ****
954:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTR
955:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTR
956:Drivers/CMSIS/Include/core_cm4.h ****
957:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTR
958:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTR
959:Drivers/CMSIS/Include/core_cm4.h ****
960:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTR
961:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTR
962:Drivers/CMSIS/Include/core_cm4.h ****
963:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTR
964:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTR
965:Drivers/CMSIS/Include/core_cm4.h ****
966:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTR
967:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTR
968:Drivers/CMSIS/Include/core_cm4.h ****
969:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTR
970:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTR
971:Drivers/CMSIS/Include/core_cm4.h ****
972:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTR
973:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTR
974:Drivers/CMSIS/Include/core_cm4.h ****
975:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTR
976:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTR
977:Drivers/CMSIS/Include/core_cm4.h ****
978:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTR
979:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTR
980:Drivers/CMSIS/Include/core_cm4.h ****
981:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTR
982:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTR
983:Drivers/CMSIS/Include/core_cm4.h ****
984:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTR
985:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTR
986:Drivers/CMSIS/Include/core_cm4.h ****
987:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTR
988:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTR
989:Drivers/CMSIS/Include/core_cm4.h ****
990:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTR
991:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTR
992:Drivers/CMSIS/Include/core_cm4.h ****
993:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTR
994:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTR
995:Drivers/CMSIS/Include/core_cm4.h ****
996:Drivers/CMSIS/Include/core_cm4.h **** /* DWT CPI Count Register Definitions */
997:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPI
998:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPI
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 19
999:Drivers/CMSIS/Include/core_cm4.h ****
1000:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Exception Overhead Count Register Definitions */
1001:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXC
1002:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXC
1003:Drivers/CMSIS/Include/core_cm4.h ****
1004:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Sleep Count Register Definitions */
1005:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLE
1006:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLE
1007:Drivers/CMSIS/Include/core_cm4.h ****
1008:Drivers/CMSIS/Include/core_cm4.h **** /* DWT LSU Count Register Definitions */
1009:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSU
1010:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSU
1011:Drivers/CMSIS/Include/core_cm4.h ****
1012:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Folded-instruction Count Register Definitions */
1013:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOL
1014:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOL
1015:Drivers/CMSIS/Include/core_cm4.h ****
1016:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Comparator Mask Register Definitions */
1017:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_MASK_MASK_Pos 0U /*!< DWT MAS
1018:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MAS
1019:Drivers/CMSIS/Include/core_cm4.h ****
1020:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Comparator Function Register Definitions */
1021:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUN
1022:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUN
1023:Drivers/CMSIS/Include/core_cm4.h ****
1024:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUN
1025:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUN
1026:Drivers/CMSIS/Include/core_cm4.h ****
1027:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUN
1028:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUN
1029:Drivers/CMSIS/Include/core_cm4.h ****
1030:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUN
1031:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUN
1032:Drivers/CMSIS/Include/core_cm4.h ****
1033:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUN
1034:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUN
1035:Drivers/CMSIS/Include/core_cm4.h ****
1036:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUN
1037:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUN
1038:Drivers/CMSIS/Include/core_cm4.h ****
1039:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUN
1040:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUN
1041:Drivers/CMSIS/Include/core_cm4.h ****
1042:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUN
1043:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUN
1044:Drivers/CMSIS/Include/core_cm4.h ****
1045:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUN
1046:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUN
1047:Drivers/CMSIS/Include/core_cm4.h ****
1048:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_DWT */
1049:Drivers/CMSIS/Include/core_cm4.h ****
1050:Drivers/CMSIS/Include/core_cm4.h ****
1051:Drivers/CMSIS/Include/core_cm4.h **** /**
1052:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register
1053:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_TPI Trace Port Interface (TPI)
1054:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Trace Port Interface (TPI)
1055:Drivers/CMSIS/Include/core_cm4.h **** @{
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 20
1056:Drivers/CMSIS/Include/core_cm4.h **** */
1057:Drivers/CMSIS/Include/core_cm4.h ****
1058:Drivers/CMSIS/Include/core_cm4.h **** /**
1059:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Trace Port Interface Register (TPI).
1060:Drivers/CMSIS/Include/core_cm4.h **** */
1061:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
1062:Drivers/CMSIS/Include/core_cm4.h **** {
1063:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Reg
1064:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Regis
1065:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[2U];
1066:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Reg
1067:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED1[55U];
1068:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register *
1069:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[131U];
1070:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Regis
1071:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Regi
1072:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counte
1073:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED3[759U];
1074:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1075:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1076:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1077:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED4[1U];
1078:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1079:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1080:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1081:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED5[39U];
1082:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1083:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1084:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED7[8U];
1085:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1086:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1087:Drivers/CMSIS/Include/core_cm4.h **** } TPI_Type;
1088:Drivers/CMSIS/Include/core_cm4.h ****
1089:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */
1090:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACP
1091:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACP
1092:Drivers/CMSIS/Include/core_cm4.h ****
1093:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Selected Pin Protocol Register Definitions */
1094:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPP
1095:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPP
1096:Drivers/CMSIS/Include/core_cm4.h ****
1097:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Formatter and Flush Status Register Definitions */
1098:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFS
1099:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFS
1100:Drivers/CMSIS/Include/core_cm4.h ****
1101:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFS
1102:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFS
1103:Drivers/CMSIS/Include/core_cm4.h ****
1104:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFS
1105:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFS
1106:Drivers/CMSIS/Include/core_cm4.h ****
1107:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFS
1108:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFS
1109:Drivers/CMSIS/Include/core_cm4.h ****
1110:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Formatter and Flush Control Register Definitions */
1111:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFC
1112:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFC
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 21
1113:Drivers/CMSIS/Include/core_cm4.h ****
1114:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFC
1115:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFC
1116:Drivers/CMSIS/Include/core_cm4.h ****
1117:Drivers/CMSIS/Include/core_cm4.h **** /* TPI TRIGGER Register Definitions */
1118:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRI
1119:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRI
1120:Drivers/CMSIS/Include/core_cm4.h ****
1121:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */
1122:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIF
1123:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIF
1124:Drivers/CMSIS/Include/core_cm4.h ****
1125:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIF
1126:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIF
1127:Drivers/CMSIS/Include/core_cm4.h ****
1128:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIF
1129:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIF
1130:Drivers/CMSIS/Include/core_cm4.h ****
1131:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIF
1132:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIF
1133:Drivers/CMSIS/Include/core_cm4.h ****
1134:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIF
1135:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIF
1136:Drivers/CMSIS/Include/core_cm4.h ****
1137:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIF
1138:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIF
1139:Drivers/CMSIS/Include/core_cm4.h ****
1140:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIF
1141:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIF
1142:Drivers/CMSIS/Include/core_cm4.h ****
1143:Drivers/CMSIS/Include/core_cm4.h **** /* TPI ITATBCTR2 Register Definitions */
1144:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITA
1145:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITA
1146:Drivers/CMSIS/Include/core_cm4.h ****
1147:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITA
1148:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITA
1149:Drivers/CMSIS/Include/core_cm4.h ****
1150:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */
1151:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIF
1152:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIF
1153:Drivers/CMSIS/Include/core_cm4.h ****
1154:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIF
1155:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIF
1156:Drivers/CMSIS/Include/core_cm4.h ****
1157:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIF
1158:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIF
1159:Drivers/CMSIS/Include/core_cm4.h ****
1160:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIF
1161:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIF
1162:Drivers/CMSIS/Include/core_cm4.h ****
1163:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIF
1164:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIF
1165:Drivers/CMSIS/Include/core_cm4.h ****
1166:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIF
1167:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIF
1168:Drivers/CMSIS/Include/core_cm4.h ****
1169:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIF
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 22
1170:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIF
1171:Drivers/CMSIS/Include/core_cm4.h ****
1172:Drivers/CMSIS/Include/core_cm4.h **** /* TPI ITATBCTR0 Register Definitions */
1173:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITA
1174:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITA
1175:Drivers/CMSIS/Include/core_cm4.h ****
1176:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITA
1177:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITA
1178:Drivers/CMSIS/Include/core_cm4.h ****
1179:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration Mode Control Register Definitions */
1180:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITC
1181:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITC
1182:Drivers/CMSIS/Include/core_cm4.h ****
1183:Drivers/CMSIS/Include/core_cm4.h **** /* TPI DEVID Register Definitions */
1184:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEV
1185:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEV
1186:Drivers/CMSIS/Include/core_cm4.h ****
1187:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEV
1188:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEV
1189:Drivers/CMSIS/Include/core_cm4.h ****
1190:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEV
1191:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEV
1192:Drivers/CMSIS/Include/core_cm4.h ****
1193:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEV
1194:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEV
1195:Drivers/CMSIS/Include/core_cm4.h ****
1196:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEV
1197:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEV
1198:Drivers/CMSIS/Include/core_cm4.h ****
1199:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEV
1200:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEV
1201:Drivers/CMSIS/Include/core_cm4.h ****
1202:Drivers/CMSIS/Include/core_cm4.h **** /* TPI DEVTYPE Register Definitions */
1203:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEV
1204:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEV
1205:Drivers/CMSIS/Include/core_cm4.h ****
1206:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEV
1207:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEV
1208:Drivers/CMSIS/Include/core_cm4.h ****
1209:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_TPI */
1210:Drivers/CMSIS/Include/core_cm4.h ****
1211:Drivers/CMSIS/Include/core_cm4.h ****
1212:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1213:Drivers/CMSIS/Include/core_cm4.h **** /**
1214:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register
1215:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1216:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Memory Protection Unit (MPU)
1217:Drivers/CMSIS/Include/core_cm4.h **** @{
1218:Drivers/CMSIS/Include/core_cm4.h **** */
1219:Drivers/CMSIS/Include/core_cm4.h ****
1220:Drivers/CMSIS/Include/core_cm4.h **** /**
1221:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Memory Protection Unit (MPU).
1222:Drivers/CMSIS/Include/core_cm4.h **** */
1223:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
1224:Drivers/CMSIS/Include/core_cm4.h **** {
1225:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1226:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 23
1227:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1228:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register
1229:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Re
1230:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address
1231:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and
1232:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address
1233:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and
1234:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address
1235:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and
1236:Drivers/CMSIS/Include/core_cm4.h **** } MPU_Type;
1237:Drivers/CMSIS/Include/core_cm4.h ****
1238:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_RALIASES 4U
1239:Drivers/CMSIS/Include/core_cm4.h ****
1240:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Type Register Definitions */
1241:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU
1242:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU
1243:Drivers/CMSIS/Include/core_cm4.h ****
1244:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_DREGION_Pos 8U /*!< MPU
1245:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU
1246:Drivers/CMSIS/Include/core_cm4.h ****
1247:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU
1248:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU
1249:Drivers/CMSIS/Include/core_cm4.h ****
1250:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Control Register Definitions */
1251:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU
1252:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU
1253:Drivers/CMSIS/Include/core_cm4.h ****
1254:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU
1255:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU
1256:Drivers/CMSIS/Include/core_cm4.h ****
1257:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU
1258:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU
1259:Drivers/CMSIS/Include/core_cm4.h ****
1260:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Number Register Definitions */
1261:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU
1262:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU
1263:Drivers/CMSIS/Include/core_cm4.h ****
1264:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Base Address Register Definitions */
1265:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_ADDR_Pos 5U /*!< MPU
1266:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU
1267:Drivers/CMSIS/Include/core_cm4.h ****
1268:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_VALID_Pos 4U /*!< MPU
1269:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU
1270:Drivers/CMSIS/Include/core_cm4.h ****
1271:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_REGION_Pos 0U /*!< MPU
1272:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU
1273:Drivers/CMSIS/Include/core_cm4.h ****
1274:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Attribute and Size Register Definitions */
1275:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ATTRS_Pos 16U /*!< MPU
1276:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU
1277:Drivers/CMSIS/Include/core_cm4.h ****
1278:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_XN_Pos 28U /*!< MPU
1279:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU
1280:Drivers/CMSIS/Include/core_cm4.h ****
1281:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU
1282:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU
1283:Drivers/CMSIS/Include/core_cm4.h ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 24
1284:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU
1285:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU
1286:Drivers/CMSIS/Include/core_cm4.h ****
1287:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_S_Pos 18U /*!< MPU
1288:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU
1289:Drivers/CMSIS/Include/core_cm4.h ****
1290:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_C_Pos 17U /*!< MPU
1291:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU
1292:Drivers/CMSIS/Include/core_cm4.h ****
1293:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_B_Pos 16U /*!< MPU
1294:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU
1295:Drivers/CMSIS/Include/core_cm4.h ****
1296:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU
1297:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU
1298:Drivers/CMSIS/Include/core_cm4.h ****
1299:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU
1300:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU
1301:Drivers/CMSIS/Include/core_cm4.h ****
1302:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ENABLE_Pos 0U /*!< MPU
1303:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU
1304:Drivers/CMSIS/Include/core_cm4.h ****
1305:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_MPU */
1306:Drivers/CMSIS/Include/core_cm4.h **** #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
1307:Drivers/CMSIS/Include/core_cm4.h ****
1308:Drivers/CMSIS/Include/core_cm4.h ****
1309:Drivers/CMSIS/Include/core_cm4.h **** /**
1310:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register
1311:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_FPU Floating Point Unit (FPU)
1312:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Floating Point Unit (FPU)
1313:Drivers/CMSIS/Include/core_cm4.h **** @{
1314:Drivers/CMSIS/Include/core_cm4.h **** */
1315:Drivers/CMSIS/Include/core_cm4.h ****
1316:Drivers/CMSIS/Include/core_cm4.h **** /**
1317:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Floating Point Unit (FPU).
1318:Drivers/CMSIS/Include/core_cm4.h **** */
1319:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
1320:Drivers/CMSIS/Include/core_cm4.h **** {
1321:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[1U];
1322:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control R
1323:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address R
1324:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Co
1325:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0
1326:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1
1327:Drivers/CMSIS/Include/core_cm4.h **** } FPU_Type;
1328:Drivers/CMSIS/Include/core_cm4.h ****
1329:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Context Control Register Definitions */
1330:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCC
1331:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCC
1332:Drivers/CMSIS/Include/core_cm4.h ****
1333:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCC
1334:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCC
1335:Drivers/CMSIS/Include/core_cm4.h ****
1336:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCC
1337:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCC
1338:Drivers/CMSIS/Include/core_cm4.h ****
1339:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCC
1340:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCC
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 25
1341:Drivers/CMSIS/Include/core_cm4.h ****
1342:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCC
1343:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCC
1344:Drivers/CMSIS/Include/core_cm4.h ****
1345:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCC
1346:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCC
1347:Drivers/CMSIS/Include/core_cm4.h ****
1348:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCC
1349:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCC
1350:Drivers/CMSIS/Include/core_cm4.h ****
1351:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_USER_Pos 1U /*!< FPCC
1352:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCC
1353:Drivers/CMSIS/Include/core_cm4.h ****
1354:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCC
1355:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCC
1356:Drivers/CMSIS/Include/core_cm4.h ****
1357:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Context Address Register Definitions */
1358:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCA
1359:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCA
1360:Drivers/CMSIS/Include/core_cm4.h ****
1361:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Default Status Control Register Definitions */
1362:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDS
1363:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDS
1364:Drivers/CMSIS/Include/core_cm4.h ****
1365:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_DN_Pos 25U /*!< FPDS
1366:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDS
1367:Drivers/CMSIS/Include/core_cm4.h ****
1368:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDS
1369:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDS
1370:Drivers/CMSIS/Include/core_cm4.h ****
1371:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDS
1372:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDS
1373:Drivers/CMSIS/Include/core_cm4.h ****
1374:Drivers/CMSIS/Include/core_cm4.h **** /* Media and FP Feature Register 0 Definitions */
1375:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR
1376:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR
1377:Drivers/CMSIS/Include/core_cm4.h ****
1378:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR
1379:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR
1380:Drivers/CMSIS/Include/core_cm4.h ****
1381:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR
1382:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR
1383:Drivers/CMSIS/Include/core_cm4.h ****
1384:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR
1385:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR
1386:Drivers/CMSIS/Include/core_cm4.h ****
1387:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR
1388:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR
1389:Drivers/CMSIS/Include/core_cm4.h ****
1390:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR
1391:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR
1392:Drivers/CMSIS/Include/core_cm4.h ****
1393:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR
1394:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR
1395:Drivers/CMSIS/Include/core_cm4.h ****
1396:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR
1397:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 26
1398:Drivers/CMSIS/Include/core_cm4.h ****
1399:Drivers/CMSIS/Include/core_cm4.h **** /* Media and FP Feature Register 1 Definitions */
1400:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR
1401:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR
1402:Drivers/CMSIS/Include/core_cm4.h ****
1403:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR
1404:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR
1405:Drivers/CMSIS/Include/core_cm4.h ****
1406:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR
1407:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR
1408:Drivers/CMSIS/Include/core_cm4.h ****
1409:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR
1410:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR
1411:Drivers/CMSIS/Include/core_cm4.h ****
1412:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_FPU */
1413:Drivers/CMSIS/Include/core_cm4.h ****
1414:Drivers/CMSIS/Include/core_cm4.h ****
1415:Drivers/CMSIS/Include/core_cm4.h **** /**
1416:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register
1417:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1418:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Core Debug Registers
1419:Drivers/CMSIS/Include/core_cm4.h **** @{
1420:Drivers/CMSIS/Include/core_cm4.h **** */
1421:Drivers/CMSIS/Include/core_cm4.h ****
1422:Drivers/CMSIS/Include/core_cm4.h **** /**
1423:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Core Debug Register (CoreDebug).
1424:Drivers/CMSIS/Include/core_cm4.h **** */
1425:Drivers/CMSIS/Include/core_cm4.h **** typedef struct
1426:Drivers/CMSIS/Include/core_cm4.h **** {
1427:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status
1428:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Reg
1429:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Registe
1430:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Cont
1431:Drivers/CMSIS/Include/core_cm4.h **** } CoreDebug_Type;
1432:Drivers/CMSIS/Include/core_cm4.h ****
1433:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Halting Control and Status Register Definitions */
1434:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< Core
1435:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< Core
1436:Drivers/CMSIS/Include/core_cm4.h ****
1437:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< Core
1438:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< Core
1439:Drivers/CMSIS/Include/core_cm4.h ****
1440:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< Core
1441:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< Core
1442:Drivers/CMSIS/Include/core_cm4.h ****
1443:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< Core
1444:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< Core
1445:Drivers/CMSIS/Include/core_cm4.h ****
1446:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< Core
1447:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< Core
1448:Drivers/CMSIS/Include/core_cm4.h ****
1449:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< Core
1450:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< Core
1451:Drivers/CMSIS/Include/core_cm4.h ****
1452:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< Core
1453:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< Core
1454:Drivers/CMSIS/Include/core_cm4.h ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 27
1455:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< Core
1456:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< Core
1457:Drivers/CMSIS/Include/core_cm4.h ****
1458:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< Core
1459:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< Core
1460:Drivers/CMSIS/Include/core_cm4.h ****
1461:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< Core
1462:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< Core
1463:Drivers/CMSIS/Include/core_cm4.h ****
1464:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< Core
1465:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< Core
1466:Drivers/CMSIS/Include/core_cm4.h ****
1467:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< Core
1468:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< Core
1469:Drivers/CMSIS/Include/core_cm4.h ****
1470:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Core Register Selector Register Definitions */
1471:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< Core
1472:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core
1473:Drivers/CMSIS/Include/core_cm4.h ****
1474:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< Core
1475:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< Core
1476:Drivers/CMSIS/Include/core_cm4.h ****
1477:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Exception and Monitor Control Register Definitions */
1478:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< Core
1479:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< Core
1480:Drivers/CMSIS/Include/core_cm4.h ****
1481:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< Core
1482:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< Core
1483:Drivers/CMSIS/Include/core_cm4.h ****
1484:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< Core
1485:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< Core
1486:Drivers/CMSIS/Include/core_cm4.h ****
1487:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< Core
1488:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< Core
1489:Drivers/CMSIS/Include/core_cm4.h ****
1490:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< Core
1491:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< Core
1492:Drivers/CMSIS/Include/core_cm4.h ****
1493:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< Core
1494:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< Core
1495:Drivers/CMSIS/Include/core_cm4.h ****
1496:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< Core
1497:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< Core
1498:Drivers/CMSIS/Include/core_cm4.h ****
1499:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< Core
1500:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< Core
1501:Drivers/CMSIS/Include/core_cm4.h ****
1502:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< Core
1503:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< Core
1504:Drivers/CMSIS/Include/core_cm4.h ****
1505:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< Core
1506:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< Core
1507:Drivers/CMSIS/Include/core_cm4.h ****
1508:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< Core
1509:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< Core
1510:Drivers/CMSIS/Include/core_cm4.h ****
1511:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< Core
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 28
1512:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< Core
1513:Drivers/CMSIS/Include/core_cm4.h ****
1514:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< Core
1515:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< Core
1516:Drivers/CMSIS/Include/core_cm4.h ****
1517:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_CoreDebug */
1518:Drivers/CMSIS/Include/core_cm4.h ****
1519:Drivers/CMSIS/Include/core_cm4.h ****
1520:Drivers/CMSIS/Include/core_cm4.h **** /**
1521:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register
1522:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_core_bitfield Core register bit field macros
1523:Drivers/CMSIS/Include/core_cm4.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1524:Drivers/CMSIS/Include/core_cm4.h **** @{
1525:Drivers/CMSIS/Include/core_cm4.h **** */
1526:Drivers/CMSIS/Include/core_cm4.h ****
1527:Drivers/CMSIS/Include/core_cm4.h **** /**
1528:Drivers/CMSIS/Include/core_cm4.h **** \brief Mask and shift a bit field value for use in a register bit range.
1529:Drivers/CMSIS/Include/core_cm4.h **** \param[in] field Name of the register bit field.
1530:Drivers/CMSIS/Include/core_cm4.h **** \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1531:Drivers/CMSIS/Include/core_cm4.h **** \return Masked and shifted value.
1532:Drivers/CMSIS/Include/core_cm4.h **** */
1533:Drivers/CMSIS/Include/core_cm4.h **** #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1534:Drivers/CMSIS/Include/core_cm4.h ****
1535:Drivers/CMSIS/Include/core_cm4.h **** /**
1536:Drivers/CMSIS/Include/core_cm4.h **** \brief Mask and shift a register value to extract a bit filed value.
1537:Drivers/CMSIS/Include/core_cm4.h **** \param[in] field Name of the register bit field.
1538:Drivers/CMSIS/Include/core_cm4.h **** \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1539:Drivers/CMSIS/Include/core_cm4.h **** \return Masked and shifted bit field value.
1540:Drivers/CMSIS/Include/core_cm4.h **** */
1541:Drivers/CMSIS/Include/core_cm4.h **** #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1542:Drivers/CMSIS/Include/core_cm4.h ****
1543:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_core_bitfield */
1544:Drivers/CMSIS/Include/core_cm4.h ****
1545:Drivers/CMSIS/Include/core_cm4.h ****
1546:Drivers/CMSIS/Include/core_cm4.h **** /**
1547:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register
1548:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_core_base Core Definitions
1549:Drivers/CMSIS/Include/core_cm4.h **** \brief Definitions for base addresses, unions, and structures.
1550:Drivers/CMSIS/Include/core_cm4.h **** @{
1551:Drivers/CMSIS/Include/core_cm4.h **** */
1552:Drivers/CMSIS/Include/core_cm4.h ****
1553:Drivers/CMSIS/Include/core_cm4.h **** /* Memory mapping of Core Hardware */
1554:Drivers/CMSIS/Include/core_cm4.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas
1555:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1556:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1557:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1558:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address
1559:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1560:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1561:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas
1562:Drivers/CMSIS/Include/core_cm4.h ****
1563:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register
1564:Drivers/CMSIS/Include/core_cm4.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct
1565:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st
1566:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc
1567:Drivers/CMSIS/Include/core_cm4.h **** #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct
1568:Drivers/CMSIS/Include/core_cm4.h **** #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 29
1569:Drivers/CMSIS/Include/core_cm4.h **** #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct
1570:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration
1571:Drivers/CMSIS/Include/core_cm4.h ****
1572:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1573:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit *
1574:Drivers/CMSIS/Include/core_cm4.h **** #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit *
1575:Drivers/CMSIS/Include/core_cm4.h **** #endif
1576:Drivers/CMSIS/Include/core_cm4.h ****
1577:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
1578:Drivers/CMSIS/Include/core_cm4.h **** #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
1579:Drivers/CMSIS/Include/core_cm4.h ****
1580:Drivers/CMSIS/Include/core_cm4.h **** /*@} */
1581:Drivers/CMSIS/Include/core_cm4.h ****
1582:Drivers/CMSIS/Include/core_cm4.h ****
1583:Drivers/CMSIS/Include/core_cm4.h ****
1584:Drivers/CMSIS/Include/core_cm4.h **** /*******************************************************************************
1585:Drivers/CMSIS/Include/core_cm4.h **** * Hardware Abstraction Layer
1586:Drivers/CMSIS/Include/core_cm4.h **** Core Function Interface contains:
1587:Drivers/CMSIS/Include/core_cm4.h **** - Core NVIC Functions
1588:Drivers/CMSIS/Include/core_cm4.h **** - Core SysTick Functions
1589:Drivers/CMSIS/Include/core_cm4.h **** - Core Debug Functions
1590:Drivers/CMSIS/Include/core_cm4.h **** - Core Register Access Functions
1591:Drivers/CMSIS/Include/core_cm4.h **** ******************************************************************************/
1592:Drivers/CMSIS/Include/core_cm4.h **** /**
1593:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1594:Drivers/CMSIS/Include/core_cm4.h **** */
1595:Drivers/CMSIS/Include/core_cm4.h ****
1596:Drivers/CMSIS/Include/core_cm4.h ****
1597:Drivers/CMSIS/Include/core_cm4.h ****
1598:Drivers/CMSIS/Include/core_cm4.h **** /* ########################## NVIC functions #################################### */
1599:Drivers/CMSIS/Include/core_cm4.h **** /**
1600:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_Core_FunctionInterface
1601:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1602:Drivers/CMSIS/Include/core_cm4.h **** \brief Functions that manage interrupts and exceptions via the NVIC.
1603:Drivers/CMSIS/Include/core_cm4.h **** @{
1604:Drivers/CMSIS/Include/core_cm4.h **** */
1605:Drivers/CMSIS/Include/core_cm4.h ****
1606:Drivers/CMSIS/Include/core_cm4.h **** #ifdef CMSIS_NVIC_VIRTUAL
1607:Drivers/CMSIS/Include/core_cm4.h **** #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1608:Drivers/CMSIS/Include/core_cm4.h **** #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1609:Drivers/CMSIS/Include/core_cm4.h **** #endif
1610:Drivers/CMSIS/Include/core_cm4.h **** #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1611:Drivers/CMSIS/Include/core_cm4.h **** #else
1612:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1613:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1614:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_EnableIRQ __NVIC_EnableIRQ
1615:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1616:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_DisableIRQ __NVIC_DisableIRQ
1617:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1618:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1619:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1620:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetActive __NVIC_GetActive
1621:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetPriority __NVIC_SetPriority
1622:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetPriority __NVIC_GetPriority
1623:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SystemReset __NVIC_SystemReset
1624:Drivers/CMSIS/Include/core_cm4.h **** #endif /* CMSIS_NVIC_VIRTUAL */
1625:Drivers/CMSIS/Include/core_cm4.h ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 30
1626:Drivers/CMSIS/Include/core_cm4.h **** #ifdef CMSIS_VECTAB_VIRTUAL
1627:Drivers/CMSIS/Include/core_cm4.h **** #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1628:Drivers/CMSIS/Include/core_cm4.h **** #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1629:Drivers/CMSIS/Include/core_cm4.h **** #endif
1630:Drivers/CMSIS/Include/core_cm4.h **** #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1631:Drivers/CMSIS/Include/core_cm4.h **** #else
1632:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetVector __NVIC_SetVector
1633:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetVector __NVIC_GetVector
1634:Drivers/CMSIS/Include/core_cm4.h **** #endif /* (CMSIS_VECTAB_VIRTUAL) */
1635:Drivers/CMSIS/Include/core_cm4.h ****
1636:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_USER_IRQ_OFFSET 16
1637:Drivers/CMSIS/Include/core_cm4.h ****
1638:Drivers/CMSIS/Include/core_cm4.h ****
1639:Drivers/CMSIS/Include/core_cm4.h **** /* The following EXC_RETURN values are saved the LR on exception entry */
1640:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after ret
1641:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after retu
1642:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after retu
1643:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after ret
1644:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after retu
1645:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after retu
1646:Drivers/CMSIS/Include/core_cm4.h ****
1647:Drivers/CMSIS/Include/core_cm4.h ****
1648:Drivers/CMSIS/Include/core_cm4.h **** /**
1649:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Priority Grouping
1650:Drivers/CMSIS/Include/core_cm4.h **** \details Sets the priority grouping field using the required unlock sequence.
1651:Drivers/CMSIS/Include/core_cm4.h **** The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1652:Drivers/CMSIS/Include/core_cm4.h **** Only values from 0..7 are used.
1653:Drivers/CMSIS/Include/core_cm4.h **** In case of a conflict between priority grouping and available
1654:Drivers/CMSIS/Include/core_cm4.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1655:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PriorityGroup Priority grouping field.
1656:Drivers/CMSIS/Include/core_cm4.h **** */
1657:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1658:Drivers/CMSIS/Include/core_cm4.h **** {
1659:Drivers/CMSIS/Include/core_cm4.h **** uint32_t reg_value;
1660:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a
1661:Drivers/CMSIS/Include/core_cm4.h ****
1662:Drivers/CMSIS/Include/core_cm4.h **** reg_value = SCB->AIRCR; /* read old register
1663:Drivers/CMSIS/Include/core_cm4.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
1664:Drivers/CMSIS/Include/core_cm4.h **** reg_value = (reg_value |
1665:Drivers/CMSIS/Include/core_cm4.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1666:Drivers/CMSIS/Include/core_cm4.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a
1667:Drivers/CMSIS/Include/core_cm4.h **** SCB->AIRCR = reg_value;
1668:Drivers/CMSIS/Include/core_cm4.h **** }
1669:Drivers/CMSIS/Include/core_cm4.h ****
1670:Drivers/CMSIS/Include/core_cm4.h ****
1671:Drivers/CMSIS/Include/core_cm4.h **** /**
1672:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Priority Grouping
1673:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the priority grouping field from the NVIC Interrupt Controller.
1674:Drivers/CMSIS/Include/core_cm4.h **** \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1675:Drivers/CMSIS/Include/core_cm4.h **** */
1676:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1677:Drivers/CMSIS/Include/core_cm4.h **** {
1678:Drivers/CMSIS/Include/core_cm4.h **** return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1679:Drivers/CMSIS/Include/core_cm4.h **** }
1680:Drivers/CMSIS/Include/core_cm4.h ****
1681:Drivers/CMSIS/Include/core_cm4.h ****
1682:Drivers/CMSIS/Include/core_cm4.h **** /**
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 31
1683:Drivers/CMSIS/Include/core_cm4.h **** \brief Enable Interrupt
1684:Drivers/CMSIS/Include/core_cm4.h **** \details Enables a device specific interrupt in the NVIC interrupt controller.
1685:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number.
1686:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative.
1687:Drivers/CMSIS/Include/core_cm4.h **** */
1688:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1689:Drivers/CMSIS/Include/core_cm4.h **** {
1690:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0)
1691:Drivers/CMSIS/Include/core_cm4.h **** {
1692:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1693:Drivers/CMSIS/Include/core_cm4.h **** }
1694:Drivers/CMSIS/Include/core_cm4.h **** }
1695:Drivers/CMSIS/Include/core_cm4.h ****
1696:Drivers/CMSIS/Include/core_cm4.h ****
1697:Drivers/CMSIS/Include/core_cm4.h **** /**
1698:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Interrupt Enable status
1699:Drivers/CMSIS/Include/core_cm4.h **** \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1700:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number.
1701:Drivers/CMSIS/Include/core_cm4.h **** \return 0 Interrupt is not enabled.
1702:Drivers/CMSIS/Include/core_cm4.h **** \return 1 Interrupt is enabled.
1703:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative.
1704:Drivers/CMSIS/Include/core_cm4.h **** */
1705:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1706:Drivers/CMSIS/Include/core_cm4.h **** {
1707:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0)
1708:Drivers/CMSIS/Include/core_cm4.h **** {
1709:Drivers/CMSIS/Include/core_cm4.h **** return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
1710:Drivers/CMSIS/Include/core_cm4.h **** }
1711:Drivers/CMSIS/Include/core_cm4.h **** else
1712:Drivers/CMSIS/Include/core_cm4.h **** {
1713:Drivers/CMSIS/Include/core_cm4.h **** return(0U);
1714:Drivers/CMSIS/Include/core_cm4.h **** }
1715:Drivers/CMSIS/Include/core_cm4.h **** }
1716:Drivers/CMSIS/Include/core_cm4.h ****
1717:Drivers/CMSIS/Include/core_cm4.h ****
1718:Drivers/CMSIS/Include/core_cm4.h **** /**
1719:Drivers/CMSIS/Include/core_cm4.h **** \brief Disable Interrupt
1720:Drivers/CMSIS/Include/core_cm4.h **** \details Disables a device specific interrupt in the NVIC interrupt controller.
1721:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number.
1722:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative.
1723:Drivers/CMSIS/Include/core_cm4.h **** */
1724:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1725:Drivers/CMSIS/Include/core_cm4.h **** {
30 .loc 2 1725 1 view -0
31 .cfi_startproc
32 @ args = 0, pretend = 0, frame = 0
33 @ frame_needed = 0, uses_anonymous_args = 0
34 @ link register save eliminated.
1726:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0)
35 .loc 2 1726 3 view .LVU1
36 .loc 2 1726 6 is_stmt 0 view .LVU2
37 0000 0028 cmp r0, #0
38 .LVL1:
39 .loc 2 1726 6 view .LVU3
40 0002 0CDB blt .L1
1727:Drivers/CMSIS/Include/core_cm4.h **** {
1728:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 32
41 .loc 2 1728 5 is_stmt 1 view .LVU4
42 .loc 2 1728 81 is_stmt 0 view .LVU5
43 0004 00F01F02 and r2, r0, #31
44 .loc 2 1728 34 view .LVU6
45 0008 4009 lsrs r0, r0, #5
46 .loc 2 1728 45 view .LVU7
47 000a 0123 movs r3, #1
48 000c 9340 lsls r3, r3, r2
49 .loc 2 1728 43 view .LVU8
50 000e 2030 adds r0, r0, #32
51 0010 034A ldr r2, .L3
52 0012 42F82030 str r3, [r2, r0, lsl #2]
1729:Drivers/CMSIS/Include/core_cm4.h **** __DSB();
53 .loc 2 1729 5 is_stmt 1 view .LVU9
54 .LBB32:
55 .LBI32:
56 .file 3 "Drivers/CMSIS/Include/cmsis_gcc.h"
1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h
3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file
4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4
5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018
6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/
7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9:Drivers/CMSIS/Include/cmsis_gcc.h **** *
10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0
11:Drivers/CMSIS/Include/cmsis_gcc.h **** *
12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may
13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License.
14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at
15:Drivers/CMSIS/Include/cmsis_gcc.h **** *
16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0
17:Drivers/CMSIS/Include/cmsis_gcc.h **** *
18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software
19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and
22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License.
23:Drivers/CMSIS/Include/cmsis_gcc.h **** */
24:Drivers/CMSIS/Include/cmsis_gcc.h ****
25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
27:Drivers/CMSIS/Include/cmsis_gcc.h ****
28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
33:Drivers/CMSIS/Include/cmsis_gcc.h ****
34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0)
37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
38:Drivers/CMSIS/Include/cmsis_gcc.h ****
39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 33
41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm
42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE
44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline
45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE
47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline
48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE
50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN
53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__))
54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED
56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used))
57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK
59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak))
60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED
62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1)))
63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT
65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION
68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1)))
69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */
71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; };
75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE
79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ
87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add
93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE
95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 34
98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ
103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add
109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED
111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x)))
112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT
114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict
115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
116:Drivers/CMSIS/Include/cmsis_gcc.h ****
117:Drivers/CMSIS/Include/cmsis_gcc.h ****
118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */
119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface
120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
122:Drivers/CMSIS/Include/cmsis_gcc.h **** */
123:Drivers/CMSIS/Include/cmsis_gcc.h ****
124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts
126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
128:Drivers/CMSIS/Include/cmsis_gcc.h **** */
129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
130:Drivers/CMSIS/Include/cmsis_gcc.h **** {
131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory");
132:Drivers/CMSIS/Include/cmsis_gcc.h **** }
133:Drivers/CMSIS/Include/cmsis_gcc.h ****
134:Drivers/CMSIS/Include/cmsis_gcc.h ****
135:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts
137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR.
138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
139:Drivers/CMSIS/Include/cmsis_gcc.h **** */
140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
141:Drivers/CMSIS/Include/cmsis_gcc.h **** {
142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory");
143:Drivers/CMSIS/Include/cmsis_gcc.h **** }
144:Drivers/CMSIS/Include/cmsis_gcc.h ****
145:Drivers/CMSIS/Include/cmsis_gcc.h ****
146:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register
148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register.
149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value
150:Drivers/CMSIS/Include/cmsis_gcc.h **** */
151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
152:Drivers/CMSIS/Include/cmsis_gcc.h **** {
153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
154:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 35
155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) );
156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
157:Drivers/CMSIS/Include/cmsis_gcc.h **** }
158:Drivers/CMSIS/Include/cmsis_gcc.h ****
159:Drivers/CMSIS/Include/cmsis_gcc.h ****
160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
161:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure)
163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode.
164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value
165:Drivers/CMSIS/Include/cmsis_gcc.h **** */
166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
167:Drivers/CMSIS/Include/cmsis_gcc.h **** {
168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
169:Drivers/CMSIS/Include/cmsis_gcc.h ****
170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
172:Drivers/CMSIS/Include/cmsis_gcc.h **** }
173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
174:Drivers/CMSIS/Include/cmsis_gcc.h ****
175:Drivers/CMSIS/Include/cmsis_gcc.h ****
176:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register
178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register.
179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set
180:Drivers/CMSIS/Include/cmsis_gcc.h **** */
181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
182:Drivers/CMSIS/Include/cmsis_gcc.h **** {
183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
184:Drivers/CMSIS/Include/cmsis_gcc.h **** }
185:Drivers/CMSIS/Include/cmsis_gcc.h ****
186:Drivers/CMSIS/Include/cmsis_gcc.h ****
187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
188:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure)
190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state.
191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set
192:Drivers/CMSIS/Include/cmsis_gcc.h **** */
193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
194:Drivers/CMSIS/Include/cmsis_gcc.h **** {
195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
196:Drivers/CMSIS/Include/cmsis_gcc.h **** }
197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
198:Drivers/CMSIS/Include/cmsis_gcc.h ****
199:Drivers/CMSIS/Include/cmsis_gcc.h ****
200:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register
202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register.
203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value
204:Drivers/CMSIS/Include/cmsis_gcc.h **** */
205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
206:Drivers/CMSIS/Include/cmsis_gcc.h **** {
207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
208:Drivers/CMSIS/Include/cmsis_gcc.h ****
209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
211:Drivers/CMSIS/Include/cmsis_gcc.h **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 36
212:Drivers/CMSIS/Include/cmsis_gcc.h ****
213:Drivers/CMSIS/Include/cmsis_gcc.h ****
214:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register
216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register.
217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value
218:Drivers/CMSIS/Include/cmsis_gcc.h **** */
219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
220:Drivers/CMSIS/Include/cmsis_gcc.h **** {
221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
222:Drivers/CMSIS/Include/cmsis_gcc.h ****
223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) );
224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
225:Drivers/CMSIS/Include/cmsis_gcc.h **** }
226:Drivers/CMSIS/Include/cmsis_gcc.h ****
227:Drivers/CMSIS/Include/cmsis_gcc.h ****
228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register
230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register.
231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value
232:Drivers/CMSIS/Include/cmsis_gcc.h **** */
233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
236:Drivers/CMSIS/Include/cmsis_gcc.h ****
237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
240:Drivers/CMSIS/Include/cmsis_gcc.h ****
241:Drivers/CMSIS/Include/cmsis_gcc.h ****
242:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer
244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP).
245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value
246:Drivers/CMSIS/Include/cmsis_gcc.h **** */
247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
248:Drivers/CMSIS/Include/cmsis_gcc.h **** {
249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
250:Drivers/CMSIS/Include/cmsis_gcc.h ****
251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) );
252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
253:Drivers/CMSIS/Include/cmsis_gcc.h **** }
254:Drivers/CMSIS/Include/cmsis_gcc.h ****
255:Drivers/CMSIS/Include/cmsis_gcc.h ****
256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
257:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure)
259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value
261:Drivers/CMSIS/Include/cmsis_gcc.h **** */
262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
263:Drivers/CMSIS/Include/cmsis_gcc.h **** {
264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
265:Drivers/CMSIS/Include/cmsis_gcc.h ****
266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
268:Drivers/CMSIS/Include/cmsis_gcc.h **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 37
269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
270:Drivers/CMSIS/Include/cmsis_gcc.h ****
271:Drivers/CMSIS/Include/cmsis_gcc.h ****
272:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer
274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP).
275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set
276:Drivers/CMSIS/Include/cmsis_gcc.h **** */
277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
278:Drivers/CMSIS/Include/cmsis_gcc.h **** {
279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
280:Drivers/CMSIS/Include/cmsis_gcc.h **** }
281:Drivers/CMSIS/Include/cmsis_gcc.h ****
282:Drivers/CMSIS/Include/cmsis_gcc.h ****
283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
284:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure)
286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set
288:Drivers/CMSIS/Include/cmsis_gcc.h **** */
289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
290:Drivers/CMSIS/Include/cmsis_gcc.h **** {
291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
294:Drivers/CMSIS/Include/cmsis_gcc.h ****
295:Drivers/CMSIS/Include/cmsis_gcc.h ****
296:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer
298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP).
299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value
300:Drivers/CMSIS/Include/cmsis_gcc.h **** */
301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
302:Drivers/CMSIS/Include/cmsis_gcc.h **** {
303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
304:Drivers/CMSIS/Include/cmsis_gcc.h ****
305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) );
306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
307:Drivers/CMSIS/Include/cmsis_gcc.h **** }
308:Drivers/CMSIS/Include/cmsis_gcc.h ****
309:Drivers/CMSIS/Include/cmsis_gcc.h ****
310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
311:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure)
313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value
315:Drivers/CMSIS/Include/cmsis_gcc.h **** */
316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
317:Drivers/CMSIS/Include/cmsis_gcc.h **** {
318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
319:Drivers/CMSIS/Include/cmsis_gcc.h ****
320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
322:Drivers/CMSIS/Include/cmsis_gcc.h **** }
323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
324:Drivers/CMSIS/Include/cmsis_gcc.h ****
325:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 38
326:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer
328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP).
329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set
330:Drivers/CMSIS/Include/cmsis_gcc.h **** */
331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
332:Drivers/CMSIS/Include/cmsis_gcc.h **** {
333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
334:Drivers/CMSIS/Include/cmsis_gcc.h **** }
335:Drivers/CMSIS/Include/cmsis_gcc.h ****
336:Drivers/CMSIS/Include/cmsis_gcc.h ****
337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
338:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure)
340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set
342:Drivers/CMSIS/Include/cmsis_gcc.h **** */
343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
344:Drivers/CMSIS/Include/cmsis_gcc.h **** {
345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
346:Drivers/CMSIS/Include/cmsis_gcc.h **** }
347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
348:Drivers/CMSIS/Include/cmsis_gcc.h ****
349:Drivers/CMSIS/Include/cmsis_gcc.h ****
350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure)
353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value
355:Drivers/CMSIS/Include/cmsis_gcc.h **** */
356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
359:Drivers/CMSIS/Include/cmsis_gcc.h ****
360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
362:Drivers/CMSIS/Include/cmsis_gcc.h **** }
363:Drivers/CMSIS/Include/cmsis_gcc.h ****
364:Drivers/CMSIS/Include/cmsis_gcc.h ****
365:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure)
367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set
369:Drivers/CMSIS/Include/cmsis_gcc.h **** */
370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
371:Drivers/CMSIS/Include/cmsis_gcc.h **** {
372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
373:Drivers/CMSIS/Include/cmsis_gcc.h **** }
374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
375:Drivers/CMSIS/Include/cmsis_gcc.h ****
376:Drivers/CMSIS/Include/cmsis_gcc.h ****
377:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask
379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register.
380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value
381:Drivers/CMSIS/Include/cmsis_gcc.h **** */
382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 39
383:Drivers/CMSIS/Include/cmsis_gcc.h **** {
384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
385:Drivers/CMSIS/Include/cmsis_gcc.h ****
386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
388:Drivers/CMSIS/Include/cmsis_gcc.h **** }
389:Drivers/CMSIS/Include/cmsis_gcc.h ****
390:Drivers/CMSIS/Include/cmsis_gcc.h ****
391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
392:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure)
394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value
396:Drivers/CMSIS/Include/cmsis_gcc.h **** */
397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
398:Drivers/CMSIS/Include/cmsis_gcc.h **** {
399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
400:Drivers/CMSIS/Include/cmsis_gcc.h ****
401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
403:Drivers/CMSIS/Include/cmsis_gcc.h **** }
404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
405:Drivers/CMSIS/Include/cmsis_gcc.h ****
406:Drivers/CMSIS/Include/cmsis_gcc.h ****
407:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask
409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register.
410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask
411:Drivers/CMSIS/Include/cmsis_gcc.h **** */
412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
413:Drivers/CMSIS/Include/cmsis_gcc.h **** {
414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
415:Drivers/CMSIS/Include/cmsis_gcc.h **** }
416:Drivers/CMSIS/Include/cmsis_gcc.h ****
417:Drivers/CMSIS/Include/cmsis_gcc.h ****
418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
419:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure)
421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask
423:Drivers/CMSIS/Include/cmsis_gcc.h **** */
424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
425:Drivers/CMSIS/Include/cmsis_gcc.h **** {
426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
427:Drivers/CMSIS/Include/cmsis_gcc.h **** }
428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
429:Drivers/CMSIS/Include/cmsis_gcc.h ****
430:Drivers/CMSIS/Include/cmsis_gcc.h ****
431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
434:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ
436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
438:Drivers/CMSIS/Include/cmsis_gcc.h **** */
439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 40
440:Drivers/CMSIS/Include/cmsis_gcc.h **** {
441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory");
442:Drivers/CMSIS/Include/cmsis_gcc.h **** }
443:Drivers/CMSIS/Include/cmsis_gcc.h ****
444:Drivers/CMSIS/Include/cmsis_gcc.h ****
445:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ
447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR.
448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
449:Drivers/CMSIS/Include/cmsis_gcc.h **** */
450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
451:Drivers/CMSIS/Include/cmsis_gcc.h **** {
452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory");
453:Drivers/CMSIS/Include/cmsis_gcc.h **** }
454:Drivers/CMSIS/Include/cmsis_gcc.h ****
455:Drivers/CMSIS/Include/cmsis_gcc.h ****
456:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority
458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register.
459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value
460:Drivers/CMSIS/Include/cmsis_gcc.h **** */
461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
462:Drivers/CMSIS/Include/cmsis_gcc.h **** {
463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
464:Drivers/CMSIS/Include/cmsis_gcc.h ****
465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) );
466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
467:Drivers/CMSIS/Include/cmsis_gcc.h **** }
468:Drivers/CMSIS/Include/cmsis_gcc.h ****
469:Drivers/CMSIS/Include/cmsis_gcc.h ****
470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
471:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure)
473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state.
474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value
475:Drivers/CMSIS/Include/cmsis_gcc.h **** */
476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
477:Drivers/CMSIS/Include/cmsis_gcc.h **** {
478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
479:Drivers/CMSIS/Include/cmsis_gcc.h ****
480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
484:Drivers/CMSIS/Include/cmsis_gcc.h ****
485:Drivers/CMSIS/Include/cmsis_gcc.h ****
486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority
488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register.
489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
490:Drivers/CMSIS/Include/cmsis_gcc.h **** */
491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
495:Drivers/CMSIS/Include/cmsis_gcc.h ****
496:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 41
497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
498:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure)
500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state.
501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
502:Drivers/CMSIS/Include/cmsis_gcc.h **** */
503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
504:Drivers/CMSIS/Include/cmsis_gcc.h **** {
505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
506:Drivers/CMSIS/Include/cmsis_gcc.h **** }
507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
508:Drivers/CMSIS/Include/cmsis_gcc.h ****
509:Drivers/CMSIS/Include/cmsis_gcc.h ****
510:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition
512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level.
514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
515:Drivers/CMSIS/Include/cmsis_gcc.h **** */
516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
517:Drivers/CMSIS/Include/cmsis_gcc.h **** {
518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
519:Drivers/CMSIS/Include/cmsis_gcc.h **** }
520:Drivers/CMSIS/Include/cmsis_gcc.h ****
521:Drivers/CMSIS/Include/cmsis_gcc.h ****
522:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask
524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register.
525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value
526:Drivers/CMSIS/Include/cmsis_gcc.h **** */
527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
528:Drivers/CMSIS/Include/cmsis_gcc.h **** {
529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
530:Drivers/CMSIS/Include/cmsis_gcc.h ****
531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
533:Drivers/CMSIS/Include/cmsis_gcc.h **** }
534:Drivers/CMSIS/Include/cmsis_gcc.h ****
535:Drivers/CMSIS/Include/cmsis_gcc.h ****
536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
537:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure)
539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state.
540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value
541:Drivers/CMSIS/Include/cmsis_gcc.h **** */
542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
543:Drivers/CMSIS/Include/cmsis_gcc.h **** {
544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
545:Drivers/CMSIS/Include/cmsis_gcc.h ****
546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
548:Drivers/CMSIS/Include/cmsis_gcc.h **** }
549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
550:Drivers/CMSIS/Include/cmsis_gcc.h ****
551:Drivers/CMSIS/Include/cmsis_gcc.h ****
552:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 42
554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register.
555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set
556:Drivers/CMSIS/Include/cmsis_gcc.h **** */
557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
558:Drivers/CMSIS/Include/cmsis_gcc.h **** {
559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
560:Drivers/CMSIS/Include/cmsis_gcc.h **** }
561:Drivers/CMSIS/Include/cmsis_gcc.h ****
562:Drivers/CMSIS/Include/cmsis_gcc.h ****
563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
564:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure)
566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state.
567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set
568:Drivers/CMSIS/Include/cmsis_gcc.h **** */
569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
570:Drivers/CMSIS/Include/cmsis_gcc.h **** {
571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
572:Drivers/CMSIS/Include/cmsis_gcc.h **** }
573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
574:Drivers/CMSIS/Include/cmsis_gcc.h ****
575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
578:Drivers/CMSIS/Include/cmsis_gcc.h ****
579:Drivers/CMSIS/Include/cmsis_gcc.h ****
580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
582:Drivers/CMSIS/Include/cmsis_gcc.h ****
583:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit
585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure
587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
588:Drivers/CMSIS/Include/cmsis_gcc.h ****
589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value
591:Drivers/CMSIS/Include/cmsis_gcc.h **** */
592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
593:Drivers/CMSIS/Include/cmsis_gcc.h **** {
594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) );
601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
603:Drivers/CMSIS/Include/cmsis_gcc.h **** }
604:Drivers/CMSIS/Include/cmsis_gcc.h ****
605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
606:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure)
608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always.
610:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 43
611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value
613:Drivers/CMSIS/Include/cmsis_gcc.h **** */
614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
615:Drivers/CMSIS/Include/cmsis_gcc.h **** {
616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
624:Drivers/CMSIS/Include/cmsis_gcc.h **** }
625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
626:Drivers/CMSIS/Include/cmsis_gcc.h ****
627:Drivers/CMSIS/Include/cmsis_gcc.h ****
628:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit
630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure
632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
633:Drivers/CMSIS/Include/cmsis_gcc.h ****
634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
636:Drivers/CMSIS/Include/cmsis_gcc.h **** */
637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
638:Drivers/CMSIS/Include/cmsis_gcc.h **** {
639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit;
643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
646:Drivers/CMSIS/Include/cmsis_gcc.h **** }
647:Drivers/CMSIS/Include/cmsis_gcc.h ****
648:Drivers/CMSIS/Include/cmsis_gcc.h ****
649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure)
652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored.
654:Drivers/CMSIS/Include/cmsis_gcc.h ****
655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
657:Drivers/CMSIS/Include/cmsis_gcc.h **** */
658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
659:Drivers/CMSIS/Include/cmsis_gcc.h **** {
660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit;
663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
666:Drivers/CMSIS/Include/cmsis_gcc.h **** }
667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 44
668:Drivers/CMSIS/Include/cmsis_gcc.h ****
669:Drivers/CMSIS/Include/cmsis_gcc.h ****
670:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit
672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure
674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
675:Drivers/CMSIS/Include/cmsis_gcc.h ****
676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value
678:Drivers/CMSIS/Include/cmsis_gcc.h **** */
679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
680:Drivers/CMSIS/Include/cmsis_gcc.h **** {
681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) );
688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
690:Drivers/CMSIS/Include/cmsis_gcc.h **** }
691:Drivers/CMSIS/Include/cmsis_gcc.h ****
692:Drivers/CMSIS/Include/cmsis_gcc.h ****
693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
694:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure)
696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always.
698:Drivers/CMSIS/Include/cmsis_gcc.h ****
699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value
701:Drivers/CMSIS/Include/cmsis_gcc.h **** */
702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
703:Drivers/CMSIS/Include/cmsis_gcc.h **** {
704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
712:Drivers/CMSIS/Include/cmsis_gcc.h **** }
713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
714:Drivers/CMSIS/Include/cmsis_gcc.h ****
715:Drivers/CMSIS/Include/cmsis_gcc.h ****
716:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit
718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure
720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
721:Drivers/CMSIS/Include/cmsis_gcc.h ****
722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
724:Drivers/CMSIS/Include/cmsis_gcc.h **** */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 45
725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit;
731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
734:Drivers/CMSIS/Include/cmsis_gcc.h **** }
735:Drivers/CMSIS/Include/cmsis_gcc.h ****
736:Drivers/CMSIS/Include/cmsis_gcc.h ****
737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
738:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure)
740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored.
742:Drivers/CMSIS/Include/cmsis_gcc.h ****
743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set
745:Drivers/CMSIS/Include/cmsis_gcc.h **** */
746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit;
751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
754:Drivers/CMSIS/Include/cmsis_gcc.h **** }
755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
756:Drivers/CMSIS/Include/cmsis_gcc.h ****
757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
759:Drivers/CMSIS/Include/cmsis_gcc.h ****
760:Drivers/CMSIS/Include/cmsis_gcc.h ****
761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR
763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register.
764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value
765:Drivers/CMSIS/Include/cmsis_gcc.h **** */
766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
767:Drivers/CMSIS/Include/cmsis_gcc.h **** {
768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr)
771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr();
775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
777:Drivers/CMSIS/Include/cmsis_gcc.h ****
778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 46
782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U);
783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
784:Drivers/CMSIS/Include/cmsis_gcc.h **** }
785:Drivers/CMSIS/Include/cmsis_gcc.h ****
786:Drivers/CMSIS/Include/cmsis_gcc.h ****
787:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR
789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register.
790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set
791:Drivers/CMSIS/Include/cmsis_gcc.h **** */
792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr);
801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr;
806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
807:Drivers/CMSIS/Include/cmsis_gcc.h **** }
808:Drivers/CMSIS/Include/cmsis_gcc.h ****
809:Drivers/CMSIS/Include/cmsis_gcc.h ****
810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
811:Drivers/CMSIS/Include/cmsis_gcc.h ****
812:Drivers/CMSIS/Include/cmsis_gcc.h ****
813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */
814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions
816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
817:Drivers/CMSIS/Include/cmsis_gcc.h **** */
818:Drivers/CMSIS/Include/cmsis_gcc.h ****
819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l"
821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */
822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
831:Drivers/CMSIS/Include/cmsis_gcc.h ****
832:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation
834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes.
835:Drivers/CMSIS/Include/cmsis_gcc.h **** */
836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop")
837:Drivers/CMSIS/Include/cmsis_gcc.h ****
838:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 47
839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt
840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
841:Drivers/CMSIS/Include/cmsis_gcc.h **** */
842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi")
843:Drivers/CMSIS/Include/cmsis_gcc.h ****
844:Drivers/CMSIS/Include/cmsis_gcc.h ****
845:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event
847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter
848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs.
849:Drivers/CMSIS/Include/cmsis_gcc.h **** */
850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe")
851:Drivers/CMSIS/Include/cmsis_gcc.h ****
852:Drivers/CMSIS/Include/cmsis_gcc.h ****
853:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event
855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
856:Drivers/CMSIS/Include/cmsis_gcc.h **** */
857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev")
858:Drivers/CMSIS/Include/cmsis_gcc.h ****
859:Drivers/CMSIS/Include/cmsis_gcc.h ****
860:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier
862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor,
863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory,
864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed.
865:Drivers/CMSIS/Include/cmsis_gcc.h **** */
866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
867:Drivers/CMSIS/Include/cmsis_gcc.h **** {
868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory");
869:Drivers/CMSIS/Include/cmsis_gcc.h **** }
870:Drivers/CMSIS/Include/cmsis_gcc.h ****
871:Drivers/CMSIS/Include/cmsis_gcc.h ****
872:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier
874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier.
875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete.
876:Drivers/CMSIS/Include/cmsis_gcc.h **** */
877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
57 .loc 3 877 27 view .LVU10
58 .LBB33:
878:Drivers/CMSIS/Include/cmsis_gcc.h **** {
879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory");
59 .loc 3 879 3 view .LVU11
60 .syntax unified
61 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
62 0016 BFF34F8F dsb 0xF
63 @ 0 "" 2
64 .thumb
65 .syntax unified
66 .LBE33:
67 .LBE32:
1730:Drivers/CMSIS/Include/core_cm4.h **** __ISB();
68 .loc 2 1730 5 view .LVU12
69 .LBB34:
70 .LBI34:
866:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 48
71 .loc 3 866 27 view .LVU13
72 .LBB35:
868:Drivers/CMSIS/Include/cmsis_gcc.h **** }
73 .loc 3 868 3 view .LVU14
74 .syntax unified
75 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
76 001a BFF36F8F isb 0xF
77 @ 0 "" 2
78 .thumb
79 .syntax unified
80 .L1:
81 .LBE35:
82 .LBE34:
1731:Drivers/CMSIS/Include/core_cm4.h **** }
1732:Drivers/CMSIS/Include/core_cm4.h **** }
83 .loc 2 1732 1 is_stmt 0 view .LVU15
84 001e 7047 bx lr
85 .L4:
86 .align 2
87 .L3:
88 0020 00E100E0 .word -536813312
89 .cfi_endproc
90 .LFE106:
92 .section .text.__NVIC_SetPriority,"ax",%progbits
93 .align 1
94 .syntax unified
95 .thumb
96 .thumb_func
98 __NVIC_SetPriority:
99 .LVL2:
100 .LFB111:
1733:Drivers/CMSIS/Include/core_cm4.h ****
1734:Drivers/CMSIS/Include/core_cm4.h ****
1735:Drivers/CMSIS/Include/core_cm4.h **** /**
1736:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Pending Interrupt
1737:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the NVIC pending register and returns the pending bit for the specified device spe
1738:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number.
1739:Drivers/CMSIS/Include/core_cm4.h **** \return 0 Interrupt status is not pending.
1740:Drivers/CMSIS/Include/core_cm4.h **** \return 1 Interrupt status is pending.
1741:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative.
1742:Drivers/CMSIS/Include/core_cm4.h **** */
1743:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1744:Drivers/CMSIS/Include/core_cm4.h **** {
1745:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0)
1746:Drivers/CMSIS/Include/core_cm4.h **** {
1747:Drivers/CMSIS/Include/core_cm4.h **** return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
1748:Drivers/CMSIS/Include/core_cm4.h **** }
1749:Drivers/CMSIS/Include/core_cm4.h **** else
1750:Drivers/CMSIS/Include/core_cm4.h **** {
1751:Drivers/CMSIS/Include/core_cm4.h **** return(0U);
1752:Drivers/CMSIS/Include/core_cm4.h **** }
1753:Drivers/CMSIS/Include/core_cm4.h **** }
1754:Drivers/CMSIS/Include/core_cm4.h ****
1755:Drivers/CMSIS/Include/core_cm4.h ****
1756:Drivers/CMSIS/Include/core_cm4.h **** /**
1757:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Pending Interrupt
1758:Drivers/CMSIS/Include/core_cm4.h **** \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 49
1759:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number.
1760:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative.
1761:Drivers/CMSIS/Include/core_cm4.h **** */
1762:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1763:Drivers/CMSIS/Include/core_cm4.h **** {
1764:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0)
1765:Drivers/CMSIS/Include/core_cm4.h **** {
1766:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1767:Drivers/CMSIS/Include/core_cm4.h **** }
1768:Drivers/CMSIS/Include/core_cm4.h **** }
1769:Drivers/CMSIS/Include/core_cm4.h ****
1770:Drivers/CMSIS/Include/core_cm4.h ****
1771:Drivers/CMSIS/Include/core_cm4.h **** /**
1772:Drivers/CMSIS/Include/core_cm4.h **** \brief Clear Pending Interrupt
1773:Drivers/CMSIS/Include/core_cm4.h **** \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1774:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number.
1775:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative.
1776:Drivers/CMSIS/Include/core_cm4.h **** */
1777:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1778:Drivers/CMSIS/Include/core_cm4.h **** {
1779:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0)
1780:Drivers/CMSIS/Include/core_cm4.h **** {
1781:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1782:Drivers/CMSIS/Include/core_cm4.h **** }
1783:Drivers/CMSIS/Include/core_cm4.h **** }
1784:Drivers/CMSIS/Include/core_cm4.h ****
1785:Drivers/CMSIS/Include/core_cm4.h ****
1786:Drivers/CMSIS/Include/core_cm4.h **** /**
1787:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Active Interrupt
1788:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the active register in the NVIC and returns the active bit for the device specific
1789:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number.
1790:Drivers/CMSIS/Include/core_cm4.h **** \return 0 Interrupt status is not active.
1791:Drivers/CMSIS/Include/core_cm4.h **** \return 1 Interrupt status is active.
1792:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative.
1793:Drivers/CMSIS/Include/core_cm4.h **** */
1794:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1795:Drivers/CMSIS/Include/core_cm4.h **** {
1796:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0)
1797:Drivers/CMSIS/Include/core_cm4.h **** {
1798:Drivers/CMSIS/Include/core_cm4.h **** return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
1799:Drivers/CMSIS/Include/core_cm4.h **** }
1800:Drivers/CMSIS/Include/core_cm4.h **** else
1801:Drivers/CMSIS/Include/core_cm4.h **** {
1802:Drivers/CMSIS/Include/core_cm4.h **** return(0U);
1803:Drivers/CMSIS/Include/core_cm4.h **** }
1804:Drivers/CMSIS/Include/core_cm4.h **** }
1805:Drivers/CMSIS/Include/core_cm4.h ****
1806:Drivers/CMSIS/Include/core_cm4.h ****
1807:Drivers/CMSIS/Include/core_cm4.h **** /**
1808:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Interrupt Priority
1809:Drivers/CMSIS/Include/core_cm4.h **** \details Sets the priority of a device specific interrupt or a processor exception.
1810:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt,
1811:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception.
1812:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number.
1813:Drivers/CMSIS/Include/core_cm4.h **** \param [in] priority Priority to set.
1814:Drivers/CMSIS/Include/core_cm4.h **** \note The priority cannot be set for every processor exception.
1815:Drivers/CMSIS/Include/core_cm4.h **** */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 50
1816:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1817:Drivers/CMSIS/Include/core_cm4.h **** {
101 .loc 2 1817 1 is_stmt 1 view -0
102 .cfi_startproc
103 @ args = 0, pretend = 0, frame = 0
104 @ frame_needed = 0, uses_anonymous_args = 0
105 @ link register save eliminated.
1818:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0)
106 .loc 2 1818 3 view .LVU17
107 .loc 2 1818 6 is_stmt 0 view .LVU18
108 0000 0028 cmp r0, #0
109 .LVL3:
110 .loc 2 1818 6 view .LVU19
111 0002 08DB blt .L6
1819:Drivers/CMSIS/Include/core_cm4.h **** {
1820:Drivers/CMSIS/Include/core_cm4.h **** NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (u
112 .loc 2 1820 5 is_stmt 1 view .LVU20
113 .loc 2 1820 48 is_stmt 0 view .LVU21
114 0004 0901 lsls r1, r1, #4
115 .LVL4:
116 .loc 2 1820 48 view .LVU22
117 0006 C9B2 uxtb r1, r1
118 .loc 2 1820 46 view .LVU23
119 0008 00F16040 add r0, r0, #-536870912
120 000c 00F56140 add r0, r0, #57600
121 0010 80F80013 strb r1, [r0, #768]
122 0014 7047 bx lr
123 .LVL5:
124 .L6:
1821:Drivers/CMSIS/Include/core_cm4.h **** }
1822:Drivers/CMSIS/Include/core_cm4.h **** else
1823:Drivers/CMSIS/Include/core_cm4.h **** {
1824:Drivers/CMSIS/Include/core_cm4.h **** SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (u
125 .loc 2 1824 5 is_stmt 1 view .LVU24
126 .loc 2 1824 32 is_stmt 0 view .LVU25
127 0016 00F00F00 and r0, r0, #15
128 .loc 2 1824 48 view .LVU26
129 001a 0901 lsls r1, r1, #4
130 .LVL6:
131 .loc 2 1824 48 view .LVU27
132 001c C9B2 uxtb r1, r1
133 .loc 2 1824 46 view .LVU28
134 001e 014B ldr r3, .L8
135 0020 1954 strb r1, [r3, r0]
1825:Drivers/CMSIS/Include/core_cm4.h **** }
1826:Drivers/CMSIS/Include/core_cm4.h **** }
136 .loc 2 1826 1 view .LVU29
137 0022 7047 bx lr
138 .L9:
139 .align 2
140 .L8:
141 0024 14ED00E0 .word -536810220
142 .cfi_endproc
143 .LFE111:
145 .section .text.__NVIC_GetPriority,"ax",%progbits
146 .align 1
147 .syntax unified
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 51
148 .thumb
149 .thumb_func
151 __NVIC_GetPriority:
152 .LVL7:
153 .LFB112:
1827:Drivers/CMSIS/Include/core_cm4.h ****
1828:Drivers/CMSIS/Include/core_cm4.h ****
1829:Drivers/CMSIS/Include/core_cm4.h **** /**
1830:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Interrupt Priority
1831:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the priority of a device specific interrupt or a processor exception.
1832:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt,
1833:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception.
1834:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number.
1835:Drivers/CMSIS/Include/core_cm4.h **** \return Interrupt Priority.
1836:Drivers/CMSIS/Include/core_cm4.h **** Value is aligned automatically to the implemented priority bits of the microc
1837:Drivers/CMSIS/Include/core_cm4.h **** */
1838:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1839:Drivers/CMSIS/Include/core_cm4.h **** {
154 .loc 2 1839 1 is_stmt 1 view -0
155 .cfi_startproc
156 @ args = 0, pretend = 0, frame = 0
157 @ frame_needed = 0, uses_anonymous_args = 0
158 @ link register save eliminated.
1840:Drivers/CMSIS/Include/core_cm4.h ****
1841:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0)
159 .loc 2 1841 3 view .LVU31
160 .loc 2 1841 6 is_stmt 0 view .LVU32
161 0000 0028 cmp r0, #0
162 .LVL8:
163 .loc 2 1841 6 view .LVU33
164 0002 07DB blt .L11
1842:Drivers/CMSIS/Include/core_cm4.h **** {
1843:Drivers/CMSIS/Include/core_cm4.h **** return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
165 .loc 2 1843 5 is_stmt 1 view .LVU34
166 .loc 2 1843 31 is_stmt 0 view .LVU35
167 0004 00F16040 add r0, r0, #-536870912
168 0008 00F56140 add r0, r0, #57600
169 000c 90F80003 ldrb r0, [r0, #768] @ zero_extendqisi2
170 .loc 2 1843 64 view .LVU36
171 0010 0009 lsrs r0, r0, #4
172 0012 7047 bx lr
173 .L11:
1844:Drivers/CMSIS/Include/core_cm4.h **** }
1845:Drivers/CMSIS/Include/core_cm4.h **** else
1846:Drivers/CMSIS/Include/core_cm4.h **** {
1847:Drivers/CMSIS/Include/core_cm4.h **** return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
174 .loc 2 1847 5 is_stmt 1 view .LVU37
175 .loc 2 1847 50 is_stmt 0 view .LVU38
176 0014 00F00F00 and r0, r0, #15
177 .loc 2 1847 31 view .LVU39
178 0018 014B ldr r3, .L13
179 001a 185C ldrb r0, [r3, r0] @ zero_extendqisi2
180 .loc 2 1847 64 view .LVU40
181 001c 0009 lsrs r0, r0, #4
1848:Drivers/CMSIS/Include/core_cm4.h **** }
1849:Drivers/CMSIS/Include/core_cm4.h **** }
182 .loc 2 1849 1 view .LVU41
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 52
183 001e 7047 bx lr
184 .L14:
185 .align 2
186 .L13:
187 0020 14ED00E0 .word -536810220
188 .cfi_endproc
189 .LFE112:
191 .section .text.NVIC_EncodePriority,"ax",%progbits
192 .align 1
193 .syntax unified
194 .thumb
195 .thumb_func
197 NVIC_EncodePriority:
198 .LVL9:
199 .LFB113:
1850:Drivers/CMSIS/Include/core_cm4.h ****
1851:Drivers/CMSIS/Include/core_cm4.h ****
1852:Drivers/CMSIS/Include/core_cm4.h **** /**
1853:Drivers/CMSIS/Include/core_cm4.h **** \brief Encode Priority
1854:Drivers/CMSIS/Include/core_cm4.h **** \details Encodes the priority for an interrupt with the given priority group,
1855:Drivers/CMSIS/Include/core_cm4.h **** preemptive priority value, and subpriority value.
1856:Drivers/CMSIS/Include/core_cm4.h **** In case of a conflict between priority grouping and available
1857:Drivers/CMSIS/Include/core_cm4.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1858:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PriorityGroup Used priority group.
1859:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PreemptPriority Preemptive priority value (starting from 0).
1860:Drivers/CMSIS/Include/core_cm4.h **** \param [in] SubPriority Subpriority value (starting from 0).
1861:Drivers/CMSIS/Include/core_cm4.h **** \return Encoded priority. Value can be used in the function \ref NVIC_SetP
1862:Drivers/CMSIS/Include/core_cm4.h **** */
1863:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin
1864:Drivers/CMSIS/Include/core_cm4.h **** {
200 .loc 2 1864 1 is_stmt 1 view -0
201 .cfi_startproc
202 @ args = 0, pretend = 0, frame = 0
203 @ frame_needed = 0, uses_anonymous_args = 0
204 .loc 2 1864 1 is_stmt 0 view .LVU43
205 0000 00B5 push {lr}
206 .cfi_def_cfa_offset 4
207 .cfi_offset 14, -4
1865:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used
208 .loc 2 1865 3 is_stmt 1 view .LVU44
209 .loc 2 1865 12 is_stmt 0 view .LVU45
210 0002 00F00700 and r0, r0, #7
211 .LVL10:
1866:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PreemptPriorityBits;
212 .loc 2 1866 3 is_stmt 1 view .LVU46
1867:Drivers/CMSIS/Include/core_cm4.h **** uint32_t SubPriorityBits;
213 .loc 2 1867 3 view .LVU47
1868:Drivers/CMSIS/Include/core_cm4.h ****
1869:Drivers/CMSIS/Include/core_cm4.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
214 .loc 2 1869 3 view .LVU48
215 .loc 2 1869 31 is_stmt 0 view .LVU49
216 0006 C0F1070C rsb ip, r0, #7
217 .loc 2 1869 23 view .LVU50
218 000a BCF1040F cmp ip, #4
219 000e 28BF it cs
220 0010 4FF0040C movcs ip, #4
221 .LVL11:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 53
1870:Drivers/CMSIS/Include/core_cm4.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
222 .loc 2 1870 3 is_stmt 1 view .LVU51
223 .loc 2 1870 44 is_stmt 0 view .LVU52
224 0014 031D adds r3, r0, #4
225 .loc 2 1870 109 view .LVU53
226 0016 062B cmp r3, #6
227 0018 0FD9 bls .L17
228 .loc 2 1870 109 discriminator 1 view .LVU54
229 001a C31E subs r3, r0, #3
230 .L16:
231 .LVL12:
1871:Drivers/CMSIS/Include/core_cm4.h ****
1872:Drivers/CMSIS/Include/core_cm4.h **** return (
232 .loc 2 1872 3 is_stmt 1 discriminator 4 view .LVU55
1873:Drivers/CMSIS/Include/core_cm4.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
233 .loc 2 1873 30 is_stmt 0 discriminator 4 view .LVU56
234 001c 4FF0FF3E mov lr, #-1
235 0020 0EFA0CF0 lsl r0, lr, ip
236 .LVL13:
237 .loc 2 1873 30 discriminator 4 view .LVU57
238 0024 21EA0001 bic r1, r1, r0
239 .LVL14:
240 .loc 2 1873 82 discriminator 4 view .LVU58
241 0028 9940 lsls r1, r1, r3
1874:Drivers/CMSIS/Include/core_cm4.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
242 .loc 2 1874 30 discriminator 4 view .LVU59
243 002a 0EFA03FE lsl lr, lr, r3
244 002e 22EA0E02 bic r2, r2, lr
245 .LVL15:
1875:Drivers/CMSIS/Include/core_cm4.h **** );
1876:Drivers/CMSIS/Include/core_cm4.h **** }
246 .loc 2 1876 1 discriminator 4 view .LVU60
247 0032 41EA0200 orr r0, r1, r2
248 0036 5DF804FB ldr pc, [sp], #4
249 .LVL16:
250 .L17:
1870:Drivers/CMSIS/Include/core_cm4.h ****
251 .loc 2 1870 109 view .LVU61
252 003a 0023 movs r3, #0
253 003c EEE7 b .L16
254 .cfi_endproc
255 .LFE113:
257 .section .text.NVIC_DecodePriority,"ax",%progbits
258 .align 1
259 .syntax unified
260 .thumb
261 .thumb_func
263 NVIC_DecodePriority:
264 .LVL17:
265 .LFB114:
1877:Drivers/CMSIS/Include/core_cm4.h ****
1878:Drivers/CMSIS/Include/core_cm4.h ****
1879:Drivers/CMSIS/Include/core_cm4.h **** /**
1880:Drivers/CMSIS/Include/core_cm4.h **** \brief Decode Priority
1881:Drivers/CMSIS/Include/core_cm4.h **** \details Decodes an interrupt priority value with a given priority group to
1882:Drivers/CMSIS/Include/core_cm4.h **** preemptive priority value and subpriority value.
1883:Drivers/CMSIS/Include/core_cm4.h **** In case of a conflict between priority grouping and available
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 54
1884:Drivers/CMSIS/Include/core_cm4.h **** priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1885:Drivers/CMSIS/Include/core_cm4.h **** \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC
1886:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PriorityGroup Used priority group.
1887:Drivers/CMSIS/Include/core_cm4.h **** \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1888:Drivers/CMSIS/Include/core_cm4.h **** \param [out] pSubPriority Subpriority value (starting from 0).
1889:Drivers/CMSIS/Include/core_cm4.h **** */
1890:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* cons
1891:Drivers/CMSIS/Include/core_cm4.h **** {
266 .loc 2 1891 1 is_stmt 1 view -0
267 .cfi_startproc
268 @ args = 0, pretend = 0, frame = 0
269 @ frame_needed = 0, uses_anonymous_args = 0
270 .loc 2 1891 1 is_stmt 0 view .LVU63
271 0000 10B5 push {r4, lr}
272 .cfi_def_cfa_offset 8
273 .cfi_offset 4, -8
274 .cfi_offset 14, -4
1892:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used
275 .loc 2 1892 3 is_stmt 1 view .LVU64
276 .loc 2 1892 12 is_stmt 0 view .LVU65
277 0002 01F00701 and r1, r1, #7
278 .LVL18:
1893:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PreemptPriorityBits;
279 .loc 2 1893 3 is_stmt 1 view .LVU66
1894:Drivers/CMSIS/Include/core_cm4.h **** uint32_t SubPriorityBits;
280 .loc 2 1894 3 view .LVU67
1895:Drivers/CMSIS/Include/core_cm4.h ****
1896:Drivers/CMSIS/Include/core_cm4.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
281 .loc 2 1896 3 view .LVU68
282 .loc 2 1896 31 is_stmt 0 view .LVU69
283 0006 C1F1070C rsb ip, r1, #7
284 .loc 2 1896 23 view .LVU70
285 000a BCF1040F cmp ip, #4
286 000e 28BF it cs
287 0010 4FF0040C movcs ip, #4
288 .LVL19:
1897:Drivers/CMSIS/Include/core_cm4.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
289 .loc 2 1897 3 is_stmt 1 view .LVU71
290 .loc 2 1897 44 is_stmt 0 view .LVU72
291 0014 0C1D adds r4, r1, #4
292 .loc 2 1897 109 view .LVU73
293 0016 062C cmp r4, #6
294 0018 0FD9 bls .L21
295 .loc 2 1897 109 discriminator 1 view .LVU74
296 001a 0339 subs r1, r1, #3
297 .LVL20:
298 .L20:
1898:Drivers/CMSIS/Include/core_cm4.h ****
1899:Drivers/CMSIS/Include/core_cm4.h **** *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1
299 .loc 2 1899 3 is_stmt 1 discriminator 4 view .LVU75
300 .loc 2 1899 33 is_stmt 0 discriminator 4 view .LVU76
301 001c 20FA01F4 lsr r4, r0, r1
302 .LVL21:
303 .loc 2 1899 53 discriminator 4 view .LVU77
304 0020 4FF0FF3E mov lr, #-1
305 0024 0EFA0CFC lsl ip, lr, ip
306 .LVL22:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 55
307 .loc 2 1899 53 discriminator 4 view .LVU78
308 0028 24EA0C04 bic r4, r4, ip
309 .loc 2 1899 21 discriminator 4 view .LVU79
310 002c 1460 str r4, [r2]
1900:Drivers/CMSIS/Include/core_cm4.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1
311 .loc 2 1900 3 is_stmt 1 discriminator 4 view .LVU80
312 .loc 2 1900 53 is_stmt 0 discriminator 4 view .LVU81
313 002e 0EFA01FE lsl lr, lr, r1
314 0032 20EA0E00 bic r0, r0, lr
315 .LVL23:
316 .loc 2 1900 21 discriminator 4 view .LVU82
317 0036 1860 str r0, [r3]
1901:Drivers/CMSIS/Include/core_cm4.h **** }
318 .loc 2 1901 1 discriminator 4 view .LVU83
319 0038 10BD pop {r4, pc}
320 .LVL24:
321 .L21:
1897:Drivers/CMSIS/Include/core_cm4.h ****
322 .loc 2 1897 109 view .LVU84
323 003a 0021 movs r1, #0
324 .LVL25:
1897:Drivers/CMSIS/Include/core_cm4.h ****
325 .loc 2 1897 109 view .LVU85
326 003c EEE7 b .L20
327 .cfi_endproc
328 .LFE114:
330 .section .text.__NVIC_SystemReset,"ax",%progbits
331 .align 1
332 .syntax unified
333 .thumb
334 .thumb_func
336 __NVIC_SystemReset:
337 .LFB117:
1902:Drivers/CMSIS/Include/core_cm4.h ****
1903:Drivers/CMSIS/Include/core_cm4.h ****
1904:Drivers/CMSIS/Include/core_cm4.h **** /**
1905:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Interrupt Vector
1906:Drivers/CMSIS/Include/core_cm4.h **** \details Sets an interrupt vector in SRAM based interrupt vector table.
1907:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt,
1908:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception.
1909:Drivers/CMSIS/Include/core_cm4.h **** VTOR must been relocated to SRAM before.
1910:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number
1911:Drivers/CMSIS/Include/core_cm4.h **** \param [in] vector Address of interrupt handler function
1912:Drivers/CMSIS/Include/core_cm4.h **** */
1913:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1914:Drivers/CMSIS/Include/core_cm4.h **** {
1915:Drivers/CMSIS/Include/core_cm4.h **** uint32_t *vectors = (uint32_t *)SCB->VTOR;
1916:Drivers/CMSIS/Include/core_cm4.h **** vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1917:Drivers/CMSIS/Include/core_cm4.h **** }
1918:Drivers/CMSIS/Include/core_cm4.h ****
1919:Drivers/CMSIS/Include/core_cm4.h ****
1920:Drivers/CMSIS/Include/core_cm4.h **** /**
1921:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Interrupt Vector
1922:Drivers/CMSIS/Include/core_cm4.h **** \details Reads an interrupt vector from interrupt vector table.
1923:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt,
1924:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception.
1925:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number.
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 56
1926:Drivers/CMSIS/Include/core_cm4.h **** \return Address of interrupt handler function
1927:Drivers/CMSIS/Include/core_cm4.h **** */
1928:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1929:Drivers/CMSIS/Include/core_cm4.h **** {
1930:Drivers/CMSIS/Include/core_cm4.h **** uint32_t *vectors = (uint32_t *)SCB->VTOR;
1931:Drivers/CMSIS/Include/core_cm4.h **** return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1932:Drivers/CMSIS/Include/core_cm4.h **** }
1933:Drivers/CMSIS/Include/core_cm4.h ****
1934:Drivers/CMSIS/Include/core_cm4.h ****
1935:Drivers/CMSIS/Include/core_cm4.h **** /**
1936:Drivers/CMSIS/Include/core_cm4.h **** \brief System Reset
1937:Drivers/CMSIS/Include/core_cm4.h **** \details Initiates a system reset request to reset the MCU.
1938:Drivers/CMSIS/Include/core_cm4.h **** */
1939:Drivers/CMSIS/Include/core_cm4.h **** __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1940:Drivers/CMSIS/Include/core_cm4.h **** {
338 .loc 2 1940 1 is_stmt 1 view -0
339 .cfi_startproc
340 @ Volatile: function does not return.
341 @ args = 0, pretend = 0, frame = 0
342 @ frame_needed = 0, uses_anonymous_args = 0
343 @ link register save eliminated.
1941:Drivers/CMSIS/Include/core_cm4.h **** __DSB(); /* Ensure all outstanding memor
344 .loc 2 1941 3 view .LVU87
345 .LBB36:
346 .LBI36:
877:Drivers/CMSIS/Include/cmsis_gcc.h **** {
347 .loc 3 877 27 view .LVU88
348 .LBB37:
349 .loc 3 879 3 view .LVU89
350 .syntax unified
351 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
352 0000 BFF34F8F dsb 0xF
353 @ 0 "" 2
354 .thumb
355 .syntax unified
356 .LBE37:
357 .LBE36:
1942:Drivers/CMSIS/Include/core_cm4.h **** buffered write are completed
1943:Drivers/CMSIS/Include/core_cm4.h **** SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
358 .loc 2 1943 3 view .LVU90
1944:Drivers/CMSIS/Include/core_cm4.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
359 .loc 2 1944 32 is_stmt 0 view .LVU91
360 0004 0549 ldr r1, .L25
361 0006 CA68 ldr r2, [r1, #12]
362 .loc 2 1944 40 view .LVU92
363 0008 02F4E062 and r2, r2, #1792
1943:Drivers/CMSIS/Include/core_cm4.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
364 .loc 2 1943 17 view .LVU93
365 000c 044B ldr r3, .L25+4
366 000e 1343 orrs r3, r3, r2
1943:Drivers/CMSIS/Include/core_cm4.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
367 .loc 2 1943 15 view .LVU94
368 0010 CB60 str r3, [r1, #12]
1945:Drivers/CMSIS/Include/core_cm4.h **** SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchange
1946:Drivers/CMSIS/Include/core_cm4.h **** __DSB(); /* Ensure completion of memory
369 .loc 2 1946 3 is_stmt 1 view .LVU95
370 .LBB38:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 57
371 .LBI38:
877:Drivers/CMSIS/Include/cmsis_gcc.h **** {
372 .loc 3 877 27 view .LVU96
373 .LBB39:
374 .loc 3 879 3 view .LVU97
375 .syntax unified
376 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
377 0012 BFF34F8F dsb 0xF
378 @ 0 "" 2
379 .thumb
380 .syntax unified
381 .L24:
382 .LBE39:
383 .LBE38:
1947:Drivers/CMSIS/Include/core_cm4.h ****
1948:Drivers/CMSIS/Include/core_cm4.h **** for(;;) /* wait until reset */
384 .loc 2 1948 3 discriminator 1 view .LVU98
1949:Drivers/CMSIS/Include/core_cm4.h **** {
1950:Drivers/CMSIS/Include/core_cm4.h **** __NOP();
385 .loc 2 1950 5 discriminator 1 view .LVU99
386 .syntax unified
387 @ 1950 "Drivers/CMSIS/Include/core_cm4.h" 1
388 0016 00BF nop
389 @ 0 "" 2
1948:Drivers/CMSIS/Include/core_cm4.h **** {
390 .loc 2 1948 3 discriminator 1 view .LVU100
391 .thumb
392 .syntax unified
393 0018 FDE7 b .L24
394 .L26:
395 001a 00BF .align 2
396 .L25:
397 001c 00ED00E0 .word -536810240
398 0020 0400FA05 .word 100270084
399 .cfi_endproc
400 .LFE117:
402 .section .text.HAL_NVIC_SetPriorityGrouping,"ax",%progbits
403 .align 1
404 .global HAL_NVIC_SetPriorityGrouping
405 .syntax unified
406 .thumb
407 .thumb_func
409 HAL_NVIC_SetPriorityGrouping:
410 .LVL26:
411 .LFB130:
1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ******************************************************************************
3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @file stm32f3xx_hal_cortex.c
4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @author MCD Application Team
5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief CORTEX HAL module driver.
6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This file provides firmware functions to manage the following
7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * functionalities of the CORTEX:
8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * + Initialization and de-initialization functions
9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * + Peripheral Control functions
10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** *
11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @verbatim
12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ==============================================================================
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 58
13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ##### How to use this driver #####
14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ==============================================================================
15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** [..]
17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** *** How to configure Interrupts using CORTEX HAL driver ***
18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ===========================================================
19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** [..]
20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** This section provides functions allowing to configure the NVIC interrupts (IRQ).
21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** The Cortex-M4 exceptions are managed by CMSIS functions.
22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function
24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** The pending IRQ priority will be managed only by the sub priority.
32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** -@- IRQ priority order (sorted by highest to lowest priority):
34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+@) Lowest pre-emption priority
35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+@) Lowest sub priority
36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+@) Lowest hardware priority (IRQ number)
37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** [..]
39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** *** How to configure Systick using CORTEX HAL driver ***
40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ========================================================
41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** [..]
42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** Setup SysTick Timer for time base
43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** is a CMSIS function that:
46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Configures the SysTick Reload register with value passed as function parameter.
47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Configures the SysTick IRQ priority to the lowest value (0x0FU).
48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Resets the SysTick Counter register.
49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Enables the SysTick Interrupt.
51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Starts the SysTick Counter.
52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** inside the stm32f3xx_hal_cortex.h file.
57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+) You can change the SysTick IRQ priority by calling the
59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS funct
61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+) To adjust the SysTick time base, use the following formula:
63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Reload Value should not exceed 0xFFFFFF
67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** @endverbatim
69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ******************************************************************************
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 59
70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @attention
71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** *
72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * Copyright (c) 2016 STMicroelectronics.
73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * All rights reserved.
74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** *
75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This software is licensed under terms that can be found in the LICENSE file in
76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * the root directory of this software component.
77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** *
79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ******************************************************************************
80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /*
83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** Additional Tables: CORTEX_NVIC_Priority_Table
84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** The table below gives the allowed values of the pre-emption priority and subpriority according
85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function
86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================================
87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority |
88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================================
89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_PRIORITYGROUP_0 | 0 | 0U-15 |
90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** | | | 4
91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** --------------------------------------------------------------------------------------------
92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_PRIORITYGROUP_1 | 0U-1 | 0U-7 |
93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** | | | 3
94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** --------------------------------------------------------------------------------------------
95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_PRIORITYGROUP_2 | 0U-3 | 0U-3 |
96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** | | | 2
97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** --------------------------------------------------------------------------------------------
98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_PRIORITYGROUP_3 | 0U-7 | 0U-1 |
99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** | | | 1
100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** --------------------------------------------------------------------------------------------
101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_PRIORITYGROUP_4 | 0U-15 | 0 |
102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** | | | 0
103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================================
104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Includes ------------------------------------------------------------------*/
108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** #include "stm32f3xx_hal.h"
109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** @addtogroup STM32F3xx_HAL_Driver
111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @{
112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** @defgroup CORTEX CORTEX
115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief CORTEX CORTEX HAL module driver
116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @{
117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** #ifdef HAL_CORTEX_MODULE_ENABLED
120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Private typedef -----------------------------------------------------------*/
122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Private define ------------------------------------------------------------*/
123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Private macro -------------------------------------------------------------*/
124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Private variables ---------------------------------------------------------*/
125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Private function prototypes -----------------------------------------------*/
126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Exported functions ---------------------------------------------------------*/
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 60
127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @{
130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Initialization and Configuration functions
135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** *
136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** @verbatim
137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ==============================================================================
138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ##### Initialization and de-initialization functions #####
139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ==============================================================================
140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** [..]
141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** This section provides the CORTEX HAL driver functions allowing to configure Interrupts
142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** Systick functionalities
143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** @endverbatim
145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @{
146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Sets the priority grouping field (pre-emption priority and subpriority)
151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * using the required unlock sequence.
152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param PriorityGroup The priority grouping bits length.
153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be one of the following values:
154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 4 bits for subpriority
156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 3 bits for subpriority
158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 2 bits for subpriority
160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 1 bits for subpriority
162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 0 bits for subpriority
164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * The pending IRQ priority will be managed only by the subpriority.
166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None
167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
412 .loc 1 169 1 view -0
413 .cfi_startproc
414 @ args = 0, pretend = 0, frame = 0
415 @ frame_needed = 0, uses_anonymous_args = 0
416 @ link register save eliminated.
170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */
171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
417 .loc 1 171 3 view .LVU102
172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_SetPriorityGrouping(PriorityGroup);
418 .loc 1 174 3 view .LVU103
419 .LBB40:
420 .LBI40:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 61
1657:Drivers/CMSIS/Include/core_cm4.h **** {
421 .loc 2 1657 22 view .LVU104
422 .LBB41:
1659:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a
423 .loc 2 1659 3 view .LVU105
1660:Drivers/CMSIS/Include/core_cm4.h ****
424 .loc 2 1660 3 view .LVU106
1662:Drivers/CMSIS/Include/core_cm4.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
425 .loc 2 1662 3 view .LVU107
1662:Drivers/CMSIS/Include/core_cm4.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
426 .loc 2 1662 14 is_stmt 0 view .LVU108
427 0000 074A ldr r2, .L28
428 0002 D368 ldr r3, [r2, #12]
429 .LVL27:
1663:Drivers/CMSIS/Include/core_cm4.h **** reg_value = (reg_value |
430 .loc 2 1663 3 is_stmt 1 view .LVU109
1663:Drivers/CMSIS/Include/core_cm4.h **** reg_value = (reg_value |
431 .loc 2 1663 13 is_stmt 0 view .LVU110
432 0004 23F4E063 bic r3, r3, #1792
433 .LVL28:
1663:Drivers/CMSIS/Include/core_cm4.h **** reg_value = (reg_value |
434 .loc 2 1663 13 view .LVU111
435 0008 1B04 lsls r3, r3, #16
436 000a 1B0C lsrs r3, r3, #16
437 .LVL29:
1664:Drivers/CMSIS/Include/core_cm4.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
438 .loc 2 1664 3 is_stmt 1 view .LVU112
1666:Drivers/CMSIS/Include/core_cm4.h **** SCB->AIRCR = reg_value;
439 .loc 2 1666 35 is_stmt 0 view .LVU113
440 000c 0002 lsls r0, r0, #8
441 .LVL30:
1666:Drivers/CMSIS/Include/core_cm4.h **** SCB->AIRCR = reg_value;
442 .loc 2 1666 35 view .LVU114
443 000e 00F4E060 and r0, r0, #1792
1665:Drivers/CMSIS/Include/core_cm4.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a
444 .loc 2 1665 62 view .LVU115
445 0012 0343 orrs r3, r3, r0
446 .LVL31:
1664:Drivers/CMSIS/Include/core_cm4.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
447 .loc 2 1664 14 view .LVU116
448 0014 43F0BF63 orr r3, r3, #100139008
449 0018 43F40033 orr r3, r3, #131072
450 .LVL32:
1667:Drivers/CMSIS/Include/core_cm4.h **** }
451 .loc 2 1667 3 is_stmt 1 view .LVU117
1667:Drivers/CMSIS/Include/core_cm4.h **** }
452 .loc 2 1667 14 is_stmt 0 view .LVU118
453 001c D360 str r3, [r2, #12]
454 .LVL33:
1667:Drivers/CMSIS/Include/core_cm4.h **** }
455 .loc 2 1667 14 view .LVU119
456 .LBE41:
457 .LBE40:
175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
458 .loc 1 175 1 view .LVU120
459 001e 7047 bx lr
460 .L29:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 62
461 .align 2
462 .L28:
463 0020 00ED00E0 .word -536810240
464 .cfi_endproc
465 .LFE130:
467 .section .text.HAL_NVIC_SetPriority,"ax",%progbits
468 .align 1
469 .global HAL_NVIC_SetPriority
470 .syntax unified
471 .thumb
472 .thumb_func
474 HAL_NVIC_SetPriority:
475 .LVL34:
476 .LFB131:
176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Sets the priority of an interrupt.
179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number
180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param PreemptPriority The pre-emption priority for the IRQn channel.
183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Pr
184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * A lower priority value indicates a higher priority
185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param SubPriority the subpriority level for the IRQ channel.
186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Pr
187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * A lower priority value indicates a higher priority.
188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None
189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
477 .loc 1 191 1 is_stmt 1 view -0
478 .cfi_startproc
479 @ args = 0, pretend = 0, frame = 0
480 @ frame_needed = 0, uses_anonymous_args = 0
481 .loc 1 191 1 is_stmt 0 view .LVU122
482 0000 10B5 push {r4, lr}
483 .cfi_def_cfa_offset 8
484 .cfi_offset 4, -8
485 .cfi_offset 14, -4
486 0002 0446 mov r4, r0
192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** uint32_t prioritygroup = 0x00U;
487 .loc 1 192 3 is_stmt 1 view .LVU123
488 .LVL35:
193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */
195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
489 .loc 1 195 3 view .LVU124
196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
490 .loc 1 196 3 view .LVU125
197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** prioritygroup = NVIC_GetPriorityGrouping();
491 .loc 1 198 3 view .LVU126
492 .LBB42:
493 .LBI42:
1676:Drivers/CMSIS/Include/core_cm4.h **** {
494 .loc 2 1676 26 view .LVU127
495 .LBB43:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 63
1678:Drivers/CMSIS/Include/core_cm4.h **** }
496 .loc 2 1678 3 view .LVU128
1678:Drivers/CMSIS/Include/core_cm4.h **** }
497 .loc 2 1678 26 is_stmt 0 view .LVU129
498 0004 054B ldr r3, .L32
499 0006 D868 ldr r0, [r3, #12]
500 .LVL36:
1678:Drivers/CMSIS/Include/core_cm4.h **** }
501 .loc 2 1678 26 view .LVU130
502 .LBE43:
503 .LBE42:
199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
504 .loc 1 200 3 is_stmt 1 view .LVU131
505 0008 C0F30220 ubfx r0, r0, #8, #3
506 .LVL37:
507 .loc 1 200 3 is_stmt 0 view .LVU132
508 000c FFF7FEFF bl NVIC_EncodePriority
509 .LVL38:
510 .loc 1 200 3 view .LVU133
511 0010 0146 mov r1, r0
512 0012 2046 mov r0, r4
513 0014 FFF7FEFF bl __NVIC_SetPriority
514 .LVL39:
201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
515 .loc 1 201 1 view .LVU134
516 0018 10BD pop {r4, pc}
517 .L33:
518 001a 00BF .align 2
519 .L32:
520 001c 00ED00E0 .word -536810240
521 .cfi_endproc
522 .LFE131:
524 .section .text.HAL_NVIC_EnableIRQ,"ax",%progbits
525 .align 1
526 .global HAL_NVIC_EnableIRQ
527 .syntax unified
528 .thumb
529 .thumb_func
531 HAL_NVIC_EnableIRQ:
532 .LVL40:
533 .LFB132:
202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Enables a device specific interrupt in the NVIC interrupt controller.
205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * function should be called before.
207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number
208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None
211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
534 .loc 1 213 1 is_stmt 1 view -0
535 .cfi_startproc
536 @ args = 0, pretend = 0, frame = 0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 64
537 @ frame_needed = 0, uses_anonymous_args = 0
538 @ link register save eliminated.
214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */
215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
539 .loc 1 215 3 view .LVU136
216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Enable interrupt */
218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_EnableIRQ(IRQn);
540 .loc 1 218 3 view .LVU137
541 .LBB44:
542 .LBI44:
1688:Drivers/CMSIS/Include/core_cm4.h **** {
543 .loc 2 1688 22 view .LVU138
544 .LBB45:
1690:Drivers/CMSIS/Include/core_cm4.h **** {
545 .loc 2 1690 3 view .LVU139
1690:Drivers/CMSIS/Include/core_cm4.h **** {
546 .loc 2 1690 6 is_stmt 0 view .LVU140
547 0000 0028 cmp r0, #0
548 .LVL41:
1690:Drivers/CMSIS/Include/core_cm4.h **** {
549 .loc 2 1690 6 view .LVU141
550 0002 07DB blt .L34
1692:Drivers/CMSIS/Include/core_cm4.h **** }
551 .loc 2 1692 5 is_stmt 1 view .LVU142
1692:Drivers/CMSIS/Include/core_cm4.h **** }
552 .loc 2 1692 81 is_stmt 0 view .LVU143
553 0004 00F01F02 and r2, r0, #31
1692:Drivers/CMSIS/Include/core_cm4.h **** }
554 .loc 2 1692 34 view .LVU144
555 0008 4009 lsrs r0, r0, #5
1692:Drivers/CMSIS/Include/core_cm4.h **** }
556 .loc 2 1692 45 view .LVU145
557 000a 0123 movs r3, #1
558 000c 9340 lsls r3, r3, r2
1692:Drivers/CMSIS/Include/core_cm4.h **** }
559 .loc 2 1692 43 view .LVU146
560 000e 024A ldr r2, .L36
561 0010 42F82030 str r3, [r2, r0, lsl #2]
562 .LVL42:
563 .L34:
1692:Drivers/CMSIS/Include/core_cm4.h **** }
564 .loc 2 1692 43 view .LVU147
565 .LBE45:
566 .LBE44:
219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
567 .loc 1 219 1 view .LVU148
568 0014 7047 bx lr
569 .L37:
570 0016 00BF .align 2
571 .L36:
572 0018 00E100E0 .word -536813312
573 .cfi_endproc
574 .LFE132:
576 .section .text.HAL_NVIC_DisableIRQ,"ax",%progbits
577 .align 1
578 .global HAL_NVIC_DisableIRQ
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 65
579 .syntax unified
580 .thumb
581 .thumb_func
583 HAL_NVIC_DisableIRQ:
584 .LVL43:
585 .LFB133:
220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Disables a device specific interrupt in the NVIC interrupt controller.
223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number
224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None
227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
586 .loc 1 229 1 is_stmt 1 view -0
587 .cfi_startproc
588 @ args = 0, pretend = 0, frame = 0
589 @ frame_needed = 0, uses_anonymous_args = 0
590 .loc 1 229 1 is_stmt 0 view .LVU150
591 0000 08B5 push {r3, lr}
592 .cfi_def_cfa_offset 8
593 .cfi_offset 3, -8
594 .cfi_offset 14, -4
230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */
231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
595 .loc 1 231 3 is_stmt 1 view .LVU151
232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Disable interrupt */
234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_DisableIRQ(IRQn);
596 .loc 1 234 3 view .LVU152
597 0002 FFF7FEFF bl __NVIC_DisableIRQ
598 .LVL44:
235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
599 .loc 1 235 1 is_stmt 0 view .LVU153
600 0006 08BD pop {r3, pc}
601 .cfi_endproc
602 .LFE133:
604 .section .text.HAL_NVIC_SystemReset,"ax",%progbits
605 .align 1
606 .global HAL_NVIC_SystemReset
607 .syntax unified
608 .thumb
609 .thumb_func
611 HAL_NVIC_SystemReset:
612 .LFB134:
236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Initiates a system reset request to reset the MCU.
239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None
240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_SystemReset(void)
242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
613 .loc 1 242 1 is_stmt 1 view -0
614 .cfi_startproc
615 @ Volatile: function does not return.
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 66
616 @ args = 0, pretend = 0, frame = 0
617 @ frame_needed = 0, uses_anonymous_args = 0
618 0000 08B5 push {r3, lr}
619 .cfi_def_cfa_offset 8
620 .cfi_offset 3, -8
621 .cfi_offset 14, -4
243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* System Reset */
244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_SystemReset();
622 .loc 1 244 3 view .LVU155
623 0002 FFF7FEFF bl __NVIC_SystemReset
624 .LVL45:
625 .cfi_endproc
626 .LFE134:
628 .section .text.HAL_SYSTICK_Config,"ax",%progbits
629 .align 1
630 .global HAL_SYSTICK_Config
631 .syntax unified
632 .thumb
633 .thumb_func
635 HAL_SYSTICK_Config:
636 .LVL46:
637 .LFB135:
245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * Counter is in free running mode to generate periodic interrupts.
250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval status: - 0 Function succeeded.
252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * - 1 Function failed.
253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
638 .loc 1 255 1 view -0
639 .cfi_startproc
640 @ args = 0, pretend = 0, frame = 0
641 @ frame_needed = 0, uses_anonymous_args = 0
642 @ link register save eliminated.
256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** return SysTick_Config(TicksNumb);
643 .loc 1 256 4 view .LVU157
644 .LBB46:
645 .LBI46:
1951:Drivers/CMSIS/Include/core_cm4.h **** }
1952:Drivers/CMSIS/Include/core_cm4.h **** }
1953:Drivers/CMSIS/Include/core_cm4.h ****
1954:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of CMSIS_Core_NVICFunctions */
1955:Drivers/CMSIS/Include/core_cm4.h ****
1956:Drivers/CMSIS/Include/core_cm4.h **** /* ########################## MPU functions #################################### */
1957:Drivers/CMSIS/Include/core_cm4.h ****
1958:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1959:Drivers/CMSIS/Include/core_cm4.h ****
1960:Drivers/CMSIS/Include/core_cm4.h **** #include "mpu_armv7.h"
1961:Drivers/CMSIS/Include/core_cm4.h ****
1962:Drivers/CMSIS/Include/core_cm4.h **** #endif
1963:Drivers/CMSIS/Include/core_cm4.h ****
1964:Drivers/CMSIS/Include/core_cm4.h ****
1965:Drivers/CMSIS/Include/core_cm4.h **** /* ########################## FPU functions #################################### */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 67
1966:Drivers/CMSIS/Include/core_cm4.h **** /**
1967:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_Core_FunctionInterface
1968:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_Core_FpuFunctions FPU Functions
1969:Drivers/CMSIS/Include/core_cm4.h **** \brief Function that provides FPU type.
1970:Drivers/CMSIS/Include/core_cm4.h **** @{
1971:Drivers/CMSIS/Include/core_cm4.h **** */
1972:Drivers/CMSIS/Include/core_cm4.h ****
1973:Drivers/CMSIS/Include/core_cm4.h **** /**
1974:Drivers/CMSIS/Include/core_cm4.h **** \brief get FPU type
1975:Drivers/CMSIS/Include/core_cm4.h **** \details returns the FPU type
1976:Drivers/CMSIS/Include/core_cm4.h **** \returns
1977:Drivers/CMSIS/Include/core_cm4.h **** - \b 0: No FPU
1978:Drivers/CMSIS/Include/core_cm4.h **** - \b 1: Single precision FPU
1979:Drivers/CMSIS/Include/core_cm4.h **** - \b 2: Double + Single precision FPU
1980:Drivers/CMSIS/Include/core_cm4.h **** */
1981:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t SCB_GetFPUType(void)
1982:Drivers/CMSIS/Include/core_cm4.h **** {
1983:Drivers/CMSIS/Include/core_cm4.h **** uint32_t mvfr0;
1984:Drivers/CMSIS/Include/core_cm4.h ****
1985:Drivers/CMSIS/Include/core_cm4.h **** mvfr0 = FPU->MVFR0;
1986:Drivers/CMSIS/Include/core_cm4.h **** if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
1987:Drivers/CMSIS/Include/core_cm4.h **** {
1988:Drivers/CMSIS/Include/core_cm4.h **** return 1U; /* Single precision FPU */
1989:Drivers/CMSIS/Include/core_cm4.h **** }
1990:Drivers/CMSIS/Include/core_cm4.h **** else
1991:Drivers/CMSIS/Include/core_cm4.h **** {
1992:Drivers/CMSIS/Include/core_cm4.h **** return 0U; /* No FPU */
1993:Drivers/CMSIS/Include/core_cm4.h **** }
1994:Drivers/CMSIS/Include/core_cm4.h **** }
1995:Drivers/CMSIS/Include/core_cm4.h ****
1996:Drivers/CMSIS/Include/core_cm4.h ****
1997:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of CMSIS_Core_FpuFunctions */
1998:Drivers/CMSIS/Include/core_cm4.h ****
1999:Drivers/CMSIS/Include/core_cm4.h ****
2000:Drivers/CMSIS/Include/core_cm4.h ****
2001:Drivers/CMSIS/Include/core_cm4.h **** /* ################################## SysTick function ########################################
2002:Drivers/CMSIS/Include/core_cm4.h **** /**
2003:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_Core_FunctionInterface
2004:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2005:Drivers/CMSIS/Include/core_cm4.h **** \brief Functions that configure the System.
2006:Drivers/CMSIS/Include/core_cm4.h **** @{
2007:Drivers/CMSIS/Include/core_cm4.h **** */
2008:Drivers/CMSIS/Include/core_cm4.h ****
2009:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2010:Drivers/CMSIS/Include/core_cm4.h ****
2011:Drivers/CMSIS/Include/core_cm4.h **** /**
2012:Drivers/CMSIS/Include/core_cm4.h **** \brief System Tick Configuration
2013:Drivers/CMSIS/Include/core_cm4.h **** \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2014:Drivers/CMSIS/Include/core_cm4.h **** Counter is in free running mode to generate periodic interrupts.
2015:Drivers/CMSIS/Include/core_cm4.h **** \param [in] ticks Number of ticks between two interrupts.
2016:Drivers/CMSIS/Include/core_cm4.h **** \return 0 Function succeeded.
2017:Drivers/CMSIS/Include/core_cm4.h **** \return 1 Function failed.
2018:Drivers/CMSIS/Include/core_cm4.h **** \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2019:Drivers/CMSIS/Include/core_cm4.h **** function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.
2020:Drivers/CMSIS/Include/core_cm4.h **** must contain a vendor-specific implementation of this function.
2021:Drivers/CMSIS/Include/core_cm4.h **** */
2022:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 68
646 .loc 2 2022 26 view .LVU158
647 .LBB47:
2023:Drivers/CMSIS/Include/core_cm4.h **** {
2024:Drivers/CMSIS/Include/core_cm4.h **** if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
648 .loc 2 2024 3 view .LVU159
649 .loc 2 2024 14 is_stmt 0 view .LVU160
650 0000 0138 subs r0, r0, #1
651 .LVL47:
652 .loc 2 2024 6 view .LVU161
653 0002 B0F1807F cmp r0, #16777216
654 0006 0BD2 bcs .L44
2025:Drivers/CMSIS/Include/core_cm4.h **** {
2026:Drivers/CMSIS/Include/core_cm4.h **** return (1UL); /* Reload value impossible */
2027:Drivers/CMSIS/Include/core_cm4.h **** }
2028:Drivers/CMSIS/Include/core_cm4.h ****
2029:Drivers/CMSIS/Include/core_cm4.h **** SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
655 .loc 2 2029 3 is_stmt 1 view .LVU162
656 .loc 2 2029 18 is_stmt 0 view .LVU163
657 0008 4FF0E023 mov r3, #-536813568
658 000c 5861 str r0, [r3, #20]
2030:Drivers/CMSIS/Include/core_cm4.h **** NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Int
659 .loc 2 2030 3 is_stmt 1 view .LVU164
660 .LVL48:
661 .LBB48:
662 .LBI48:
1816:Drivers/CMSIS/Include/core_cm4.h **** {
663 .loc 2 1816 22 view .LVU165
664 .LBB49:
1818:Drivers/CMSIS/Include/core_cm4.h **** {
665 .loc 2 1818 3 view .LVU166
1824:Drivers/CMSIS/Include/core_cm4.h **** }
666 .loc 2 1824 5 view .LVU167
1824:Drivers/CMSIS/Include/core_cm4.h **** }
667 .loc 2 1824 46 is_stmt 0 view .LVU168
668 000e 054A ldr r2, .L45
669 0010 F021 movs r1, #240
670 0012 82F82310 strb r1, [r2, #35]
671 .LVL49:
1824:Drivers/CMSIS/Include/core_cm4.h **** }
672 .loc 2 1824 46 view .LVU169
673 .LBE49:
674 .LBE48:
2031:Drivers/CMSIS/Include/core_cm4.h **** SysTick->VAL = 0UL; /* Load the SysTick Counter Val
675 .loc 2 2031 3 is_stmt 1 view .LVU170
676 .loc 2 2031 18 is_stmt 0 view .LVU171
677 0016 0020 movs r0, #0
678 .LVL50:
679 .loc 2 2031 18 view .LVU172
680 0018 9861 str r0, [r3, #24]
2032:Drivers/CMSIS/Include/core_cm4.h **** SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
681 .loc 2 2032 3 is_stmt 1 view .LVU173
682 .loc 2 2032 18 is_stmt 0 view .LVU174
683 001a 0722 movs r2, #7
684 001c 1A61 str r2, [r3, #16]
2033:Drivers/CMSIS/Include/core_cm4.h **** SysTick_CTRL_TICKINT_Msk |
2034:Drivers/CMSIS/Include/core_cm4.h **** SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTi
2035:Drivers/CMSIS/Include/core_cm4.h **** return (0UL); /* Function successful */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 69
685 .loc 2 2035 3 is_stmt 1 view .LVU175
686 .loc 2 2035 10 is_stmt 0 view .LVU176
687 001e 7047 bx lr
688 .L44:
2026:Drivers/CMSIS/Include/core_cm4.h **** }
689 .loc 2 2026 12 view .LVU177
690 0020 0120 movs r0, #1
691 .LVL51:
2026:Drivers/CMSIS/Include/core_cm4.h **** }
692 .loc 2 2026 12 view .LVU178
693 .LBE47:
694 .LBE46:
257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
695 .loc 1 257 1 view .LVU179
696 0022 7047 bx lr
697 .L46:
698 .align 2
699 .L45:
700 0024 00ED00E0 .word -536810240
701 .cfi_endproc
702 .LFE135:
704 .section .text.HAL_MPU_Disable,"ax",%progbits
705 .align 1
706 .global HAL_MPU_Disable
707 .syntax unified
708 .thumb
709 .thumb_func
711 HAL_MPU_Disable:
712 .LFB136:
258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @}
260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Cortex control functions
264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** *
265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** @verbatim
266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ==============================================================================
267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ##### Peripheral Control functions #####
268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ==============================================================================
269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** [..]
270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** This subsection provides a set of functions allowing to control the CORTEX
271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (NVIC, SYSTICK, MPU) functionalities.
272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** @endverbatim
275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @{
276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** #if (__MPU_PRESENT == 1U)
279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Disables the MPU also clears the HFNMIENA bit (ARM recommendation)
282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None
283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_MPU_Disable(void)
285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 70
713 .loc 1 285 1 is_stmt 1 view -0
714 .cfi_startproc
715 @ args = 0, pretend = 0, frame = 0
716 @ frame_needed = 0, uses_anonymous_args = 0
717 @ link register save eliminated.
286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Disable fault exceptions */
287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
718 .loc 1 287 3 view .LVU181
719 .loc 1 287 6 is_stmt 0 view .LVU182
720 0000 044B ldr r3, .L48
721 0002 5A6A ldr r2, [r3, #36]
722 .loc 1 287 14 view .LVU183
723 0004 22F48032 bic r2, r2, #65536
724 0008 5A62 str r2, [r3, #36]
288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Disable the MPU */
290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->CTRL = 0U;
725 .loc 1 290 3 is_stmt 1 view .LVU184
726 .loc 1 290 13 is_stmt 0 view .LVU185
727 000a 0022 movs r2, #0
728 000c C3F89420 str r2, [r3, #148]
291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
729 .loc 1 291 1 view .LVU186
730 0010 7047 bx lr
731 .L49:
732 0012 00BF .align 2
733 .L48:
734 0014 00ED00E0 .word -536810240
735 .cfi_endproc
736 .LFE136:
738 .section .text.HAL_MPU_Enable,"ax",%progbits
739 .align 1
740 .global HAL_MPU_Enable
741 .syntax unified
742 .thumb
743 .thumb_func
745 HAL_MPU_Enable:
746 .LVL52:
747 .LFB137:
292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Enables the MPU
295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param MPU_Control Specifies the control mode of the MPU during hard fault,
296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * NMI, FAULTMASK and privileged access to the default memory
297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be one of the following values:
298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg MPU_HFNMI_PRIVDEF_NONE
299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg MPU_HARDFAULT_NMI
300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg MPU_PRIVILEGED_DEFAULT
301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg MPU_HFNMI_PRIVDEF
302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None
303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_MPU_Enable(uint32_t MPU_Control)
305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
748 .loc 1 305 1 is_stmt 1 view -0
749 .cfi_startproc
750 @ args = 0, pretend = 0, frame = 0
751 @ frame_needed = 0, uses_anonymous_args = 0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 71
752 @ link register save eliminated.
306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Enable the MPU */
307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
753 .loc 1 307 3 view .LVU188
754 .loc 1 307 29 is_stmt 0 view .LVU189
755 0000 40F00100 orr r0, r0, #1
756 .LVL53:
757 .loc 1 307 15 view .LVU190
758 0004 034B ldr r3, .L51
759 0006 C3F89400 str r0, [r3, #148]
308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Enable fault exceptions */
310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
760 .loc 1 310 3 is_stmt 1 view .LVU191
761 .loc 1 310 6 is_stmt 0 view .LVU192
762 000a 5A6A ldr r2, [r3, #36]
763 .loc 1 310 14 view .LVU193
764 000c 42F48032 orr r2, r2, #65536
765 0010 5A62 str r2, [r3, #36]
311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
766 .loc 1 311 1 view .LVU194
767 0012 7047 bx lr
768 .L52:
769 .align 2
770 .L51:
771 0014 00ED00E0 .word -536810240
772 .cfi_endproc
773 .LFE137:
775 .section .text.HAL_MPU_ConfigRegion,"ax",%progbits
776 .align 1
777 .global HAL_MPU_ConfigRegion
778 .syntax unified
779 .thumb
780 .thumb_func
782 HAL_MPU_ConfigRegion:
783 .LVL54:
784 .LFB138:
312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Initializes and configures the Region and the memory to be protected.
315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * the initialization and configuration information.
317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None
318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
785 .loc 1 320 1 is_stmt 1 view -0
786 .cfi_startproc
787 @ args = 0, pretend = 0, frame = 0
788 @ frame_needed = 0, uses_anonymous_args = 0
789 @ link register save eliminated.
321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */
322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
790 .loc 1 322 3 view .LVU196
323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
791 .loc 1 323 3 view .LVU197
324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 72
325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Set the Region number */
326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->RNR = MPU_Init->Number;
792 .loc 1 326 3 view .LVU198
793 .loc 1 326 22 is_stmt 0 view .LVU199
794 0000 4278 ldrb r2, [r0, #1] @ zero_extendqisi2
795 .loc 1 326 12 view .LVU200
796 0002 164B ldr r3, .L56
797 0004 C3F89820 str r2, [r3, #152]
327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** if ((MPU_Init->Enable) != RESET)
798 .loc 1 328 3 is_stmt 1 view .LVU201
799 .loc 1 328 16 is_stmt 0 view .LVU202
800 0008 0378 ldrb r3, [r0] @ zero_extendqisi2
801 .loc 1 328 6 view .LVU203
802 000a FBB1 cbz r3, .L54
329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */
331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
803 .loc 1 331 5 is_stmt 1 view .LVU204
332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
804 .loc 1 332 5 view .LVU205
333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
805 .loc 1 333 5 view .LVU206
334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
806 .loc 1 334 5 view .LVU207
335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
807 .loc 1 335 5 view .LVU208
336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
808 .loc 1 336 5 view .LVU209
337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
809 .loc 1 337 5 view .LVU210
338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
810 .loc 1 338 5 view .LVU211
339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->RBAR = MPU_Init->BaseAddress;
811 .loc 1 340 5 view .LVU212
812 .loc 1 340 25 is_stmt 0 view .LVU213
813 000c 4368 ldr r3, [r0, #4]
814 .loc 1 340 15 view .LVU214
815 000e 134A ldr r2, .L56
816 0010 C2F89C30 str r3, [r2, #156]
341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
817 .loc 1 341 5 is_stmt 1 view .LVU215
818 .loc 1 341 36 is_stmt 0 view .LVU216
819 0014 017B ldrb r1, [r0, #12] @ zero_extendqisi2
342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
820 .loc 1 342 36 view .LVU217
821 0016 C37A ldrb r3, [r0, #11] @ zero_extendqisi2
822 .loc 1 342 62 view .LVU218
823 0018 1B06 lsls r3, r3, #24
341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
824 .loc 1 341 84 view .LVU219
825 001a 43EA0173 orr r3, r3, r1, lsl #28
343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
826 .loc 1 343 36 view .LVU220
827 001e 817A ldrb r1, [r0, #10] @ zero_extendqisi2
342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 73
828 .loc 1 342 84 view .LVU221
829 0020 43EAC143 orr r3, r3, r1, lsl #19
344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
830 .loc 1 344 36 view .LVU222
831 0024 417B ldrb r1, [r0, #13] @ zero_extendqisi2
343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
832 .loc 1 343 84 view .LVU223
833 0026 43EA8143 orr r3, r3, r1, lsl #18
345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
834 .loc 1 345 36 view .LVU224
835 002a 817B ldrb r1, [r0, #14] @ zero_extendqisi2
344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
836 .loc 1 344 84 view .LVU225
837 002c 43EA4143 orr r3, r3, r1, lsl #17
346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
838 .loc 1 346 36 view .LVU226
839 0030 C17B ldrb r1, [r0, #15] @ zero_extendqisi2
345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
840 .loc 1 345 84 view .LVU227
841 0032 43EA0143 orr r3, r3, r1, lsl #16
347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
842 .loc 1 347 36 view .LVU228
843 0036 417A ldrb r1, [r0, #9] @ zero_extendqisi2
346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
844 .loc 1 346 84 view .LVU229
845 0038 43EA0123 orr r3, r3, r1, lsl #8
348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
846 .loc 1 348 36 view .LVU230
847 003c 017A ldrb r1, [r0, #8] @ zero_extendqisi2
347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
848 .loc 1 347 84 view .LVU231
849 003e 43EA4103 orr r3, r3, r1, lsl #1
349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
850 .loc 1 349 36 view .LVU232
851 0042 0178 ldrb r1, [r0] @ zero_extendqisi2
348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
852 .loc 1 348 84 view .LVU233
853 0044 0B43 orrs r3, r3, r1
341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
854 .loc 1 341 15 view .LVU234
855 0046 C2F8A030 str r3, [r2, #160]
856 004a 7047 bx lr
857 .L54:
350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** else
352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->RBAR = 0x00U;
858 .loc 1 353 5 is_stmt 1 view .LVU235
859 .loc 1 353 15 is_stmt 0 view .LVU236
860 004c 034B ldr r3, .L56
861 004e 0022 movs r2, #0
862 0050 C3F89C20 str r2, [r3, #156]
354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->RASR = 0x00U;
863 .loc 1 354 5 is_stmt 1 view .LVU237
864 .loc 1 354 15 is_stmt 0 view .LVU238
865 0054 C3F8A020 str r2, [r3, #160]
355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 74
356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
866 .loc 1 356 1 view .LVU239
867 0058 7047 bx lr
868 .L57:
869 005a 00BF .align 2
870 .L56:
871 005c 00ED00E0 .word -536810240
872 .cfi_endproc
873 .LFE138:
875 .section .text.HAL_NVIC_GetPriorityGrouping,"ax",%progbits
876 .align 1
877 .global HAL_NVIC_GetPriorityGrouping
878 .syntax unified
879 .thumb
880 .thumb_func
882 HAL_NVIC_GetPriorityGrouping:
883 .LFB139:
357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** #endif /* __MPU_PRESENT */
358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPriorityGrouping(void)
364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
884 .loc 1 364 1 is_stmt 1 view -0
885 .cfi_startproc
886 @ args = 0, pretend = 0, frame = 0
887 @ frame_needed = 0, uses_anonymous_args = 0
888 @ link register save eliminated.
365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Get the PRIGROUP[10:8] field value */
366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** return NVIC_GetPriorityGrouping();
889 .loc 1 366 3 view .LVU241
890 .LBB50:
891 .LBI50:
1676:Drivers/CMSIS/Include/core_cm4.h **** {
892 .loc 2 1676 26 view .LVU242
893 .LBB51:
1678:Drivers/CMSIS/Include/core_cm4.h **** }
894 .loc 2 1678 3 view .LVU243
1678:Drivers/CMSIS/Include/core_cm4.h **** }
895 .loc 2 1678 26 is_stmt 0 view .LVU244
896 0000 024B ldr r3, .L59
897 0002 D868 ldr r0, [r3, #12]
898 .LBE51:
899 .LBE50:
367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
900 .loc 1 367 1 view .LVU245
901 0004 C0F30220 ubfx r0, r0, #8, #3
902 0008 7047 bx lr
903 .L60:
904 000a 00BF .align 2
905 .L59:
906 000c 00ED00E0 .word -536810240
907 .cfi_endproc
908 .LFE139:
910 .section .text.HAL_NVIC_GetPriority,"ax",%progbits
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 75
911 .align 1
912 .global HAL_NVIC_GetPriority
913 .syntax unified
914 .thumb
915 .thumb_func
917 HAL_NVIC_GetPriority:
918 .LVL55:
919 .LFB140:
368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Gets the priority of an interrupt.
371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number
372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param PriorityGroup: the priority grouping bits length.
375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be one of the following values:
376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 4 bits for subpriority
378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 3 bits for subpriority
380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 2 bits for subpriority
382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 1 bits for subpriority
384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 0 bits for subpriority
386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param pSubPriority Pointer on the Subpriority value (starting from 0).
388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None
389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint3
391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
920 .loc 1 391 1 is_stmt 1 view -0
921 .cfi_startproc
922 @ args = 0, pretend = 0, frame = 0
923 @ frame_needed = 0, uses_anonymous_args = 0
924 .loc 1 391 1 is_stmt 0 view .LVU247
925 0000 70B5 push {r4, r5, r6, lr}
926 .cfi_def_cfa_offset 16
927 .cfi_offset 4, -16
928 .cfi_offset 5, -12
929 .cfi_offset 6, -8
930 .cfi_offset 14, -4
931 0002 0C46 mov r4, r1
932 0004 1546 mov r5, r2
933 0006 1E46 mov r6, r3
392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */
393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
934 .loc 1 393 3 is_stmt 1 view .LVU248
394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Get priority for Cortex-M system or device specific interrupts */
395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
935 .loc 1 395 3 view .LVU249
936 0008 FFF7FEFF bl __NVIC_GetPriority
937 .LVL56:
938 .loc 1 395 3 is_stmt 0 view .LVU250
939 000c 3346 mov r3, r6
940 000e 2A46 mov r2, r5
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 76
941 0010 2146 mov r1, r4
942 0012 FFF7FEFF bl NVIC_DecodePriority
943 .LVL57:
396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
944 .loc 1 396 1 view .LVU251
945 0016 70BD pop {r4, r5, r6, pc}
946 .loc 1 396 1 view .LVU252
947 .cfi_endproc
948 .LFE140:
950 .section .text.HAL_NVIC_SetPendingIRQ,"ax",%progbits
951 .align 1
952 .global HAL_NVIC_SetPendingIRQ
953 .syntax unified
954 .thumb
955 .thumb_func
957 HAL_NVIC_SetPendingIRQ:
958 .LVL58:
959 .LFB141:
397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Sets Pending bit of an external interrupt.
400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number
401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None
404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
960 .loc 1 406 1 is_stmt 1 view -0
961 .cfi_startproc
962 @ args = 0, pretend = 0, frame = 0
963 @ frame_needed = 0, uses_anonymous_args = 0
964 @ link register save eliminated.
407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Set interrupt pending */
408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_SetPendingIRQ(IRQn);
965 .loc 1 408 3 view .LVU254
966 .LBB52:
967 .LBI52:
1762:Drivers/CMSIS/Include/core_cm4.h **** {
968 .loc 2 1762 22 view .LVU255
969 .LBB53:
1764:Drivers/CMSIS/Include/core_cm4.h **** {
970 .loc 2 1764 3 view .LVU256
1764:Drivers/CMSIS/Include/core_cm4.h **** {
971 .loc 2 1764 6 is_stmt 0 view .LVU257
972 0000 0028 cmp r0, #0
973 .LVL59:
1764:Drivers/CMSIS/Include/core_cm4.h **** {
974 .loc 2 1764 6 view .LVU258
975 0002 08DB blt .L63
1766:Drivers/CMSIS/Include/core_cm4.h **** }
976 .loc 2 1766 5 is_stmt 1 view .LVU259
1766:Drivers/CMSIS/Include/core_cm4.h **** }
977 .loc 2 1766 81 is_stmt 0 view .LVU260
978 0004 00F01F02 and r2, r0, #31
1766:Drivers/CMSIS/Include/core_cm4.h **** }
979 .loc 2 1766 34 view .LVU261
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 77
980 0008 4009 lsrs r0, r0, #5
1766:Drivers/CMSIS/Include/core_cm4.h **** }
981 .loc 2 1766 45 view .LVU262
982 000a 0123 movs r3, #1
983 000c 9340 lsls r3, r3, r2
1766:Drivers/CMSIS/Include/core_cm4.h **** }
984 .loc 2 1766 43 view .LVU263
985 000e 4030 adds r0, r0, #64
986 0010 014A ldr r2, .L65
987 0012 42F82030 str r3, [r2, r0, lsl #2]
988 .LVL60:
989 .L63:
1766:Drivers/CMSIS/Include/core_cm4.h **** }
990 .loc 2 1766 43 view .LVU264
991 .LBE53:
992 .LBE52:
409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
993 .loc 1 409 1 view .LVU265
994 0016 7047 bx lr
995 .L66:
996 .align 2
997 .L65:
998 0018 00E100E0 .word -536813312
999 .cfi_endproc
1000 .LFE141:
1002 .section .text.HAL_NVIC_GetPendingIRQ,"ax",%progbits
1003 .align 1
1004 .global HAL_NVIC_GetPendingIRQ
1005 .syntax unified
1006 .thumb
1007 .thumb_func
1009 HAL_NVIC_GetPendingIRQ:
1010 .LVL61:
1011 .LFB142:
410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Gets Pending Interrupt (reads the pending register in the NVIC
413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * and returns the pending bit for the specified interrupt).
414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number
415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval status: - 0 Interrupt status is not pending.
418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * - 1 Interrupt status is pending.
419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
1012 .loc 1 421 1 is_stmt 1 view -0
1013 .cfi_startproc
1014 @ args = 0, pretend = 0, frame = 0
1015 @ frame_needed = 0, uses_anonymous_args = 0
1016 @ link register save eliminated.
422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Return 1 if pending else 0U */
423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** return NVIC_GetPendingIRQ(IRQn);
1017 .loc 1 423 3 view .LVU267
1018 .LBB54:
1019 .LBI54:
1743:Drivers/CMSIS/Include/core_cm4.h **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 78
1020 .loc 2 1743 26 view .LVU268
1021 .LBB55:
1745:Drivers/CMSIS/Include/core_cm4.h **** {
1022 .loc 2 1745 3 view .LVU269
1745:Drivers/CMSIS/Include/core_cm4.h **** {
1023 .loc 2 1745 6 is_stmt 0 view .LVU270
1024 0000 0028 cmp r0, #0
1025 .LVL62:
1745:Drivers/CMSIS/Include/core_cm4.h **** {
1026 .loc 2 1745 6 view .LVU271
1027 0002 0BDB blt .L69
1747:Drivers/CMSIS/Include/core_cm4.h **** }
1028 .loc 2 1747 5 is_stmt 1 view .LVU272
1747:Drivers/CMSIS/Include/core_cm4.h **** }
1029 .loc 2 1747 54 is_stmt 0 view .LVU273
1030 0004 4309 lsrs r3, r0, #5
1747:Drivers/CMSIS/Include/core_cm4.h **** }
1031 .loc 2 1747 35 view .LVU274
1032 0006 4033 adds r3, r3, #64
1033 0008 054A ldr r2, .L70
1034 000a 52F82330 ldr r3, [r2, r3, lsl #2]
1747:Drivers/CMSIS/Include/core_cm4.h **** }
1035 .loc 2 1747 91 view .LVU275
1036 000e 00F01F00 and r0, r0, #31
1747:Drivers/CMSIS/Include/core_cm4.h **** }
1037 .loc 2 1747 103 view .LVU276
1038 0012 23FA00F0 lsr r0, r3, r0
1747:Drivers/CMSIS/Include/core_cm4.h **** }
1039 .loc 2 1747 12 view .LVU277
1040 0016 00F00100 and r0, r0, #1
1041 001a 7047 bx lr
1042 .L69:
1751:Drivers/CMSIS/Include/core_cm4.h **** }
1043 .loc 2 1751 11 view .LVU278
1044 001c 0020 movs r0, #0
1045 .LVL63:
1751:Drivers/CMSIS/Include/core_cm4.h **** }
1046 .loc 2 1751 11 view .LVU279
1047 .LBE55:
1048 .LBE54:
424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
1049 .loc 1 424 1 view .LVU280
1050 001e 7047 bx lr
1051 .L71:
1052 .align 2
1053 .L70:
1054 0020 00E100E0 .word -536813312
1055 .cfi_endproc
1056 .LFE142:
1058 .section .text.HAL_NVIC_ClearPendingIRQ,"ax",%progbits
1059 .align 1
1060 .global HAL_NVIC_ClearPendingIRQ
1061 .syntax unified
1062 .thumb
1063 .thumb_func
1065 HAL_NVIC_ClearPendingIRQ:
1066 .LVL64:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 79
1067 .LFB143:
425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Clears the pending bit of an external interrupt.
428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number
429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None
432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
1068 .loc 1 434 1 is_stmt 1 view -0
1069 .cfi_startproc
1070 @ args = 0, pretend = 0, frame = 0
1071 @ frame_needed = 0, uses_anonymous_args = 0
1072 @ link register save eliminated.
435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Clear pending interrupt */
436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_ClearPendingIRQ(IRQn);
1073 .loc 1 436 3 view .LVU282
1074 .LBB56:
1075 .LBI56:
1777:Drivers/CMSIS/Include/core_cm4.h **** {
1076 .loc 2 1777 22 view .LVU283
1077 .LBB57:
1779:Drivers/CMSIS/Include/core_cm4.h **** {
1078 .loc 2 1779 3 view .LVU284
1779:Drivers/CMSIS/Include/core_cm4.h **** {
1079 .loc 2 1779 6 is_stmt 0 view .LVU285
1080 0000 0028 cmp r0, #0
1081 .LVL65:
1779:Drivers/CMSIS/Include/core_cm4.h **** {
1082 .loc 2 1779 6 view .LVU286
1083 0002 08DB blt .L72
1781:Drivers/CMSIS/Include/core_cm4.h **** }
1084 .loc 2 1781 5 is_stmt 1 view .LVU287
1781:Drivers/CMSIS/Include/core_cm4.h **** }
1085 .loc 2 1781 81 is_stmt 0 view .LVU288
1086 0004 00F01F02 and r2, r0, #31
1781:Drivers/CMSIS/Include/core_cm4.h **** }
1087 .loc 2 1781 34 view .LVU289
1088 0008 4009 lsrs r0, r0, #5
1781:Drivers/CMSIS/Include/core_cm4.h **** }
1089 .loc 2 1781 45 view .LVU290
1090 000a 0123 movs r3, #1
1091 000c 9340 lsls r3, r3, r2
1781:Drivers/CMSIS/Include/core_cm4.h **** }
1092 .loc 2 1781 43 view .LVU291
1093 000e 6030 adds r0, r0, #96
1094 0010 014A ldr r2, .L74
1095 0012 42F82030 str r3, [r2, r0, lsl #2]
1096 .LVL66:
1097 .L72:
1781:Drivers/CMSIS/Include/core_cm4.h **** }
1098 .loc 2 1781 43 view .LVU292
1099 .LBE57:
1100 .LBE56:
437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 80
1101 .loc 1 437 1 view .LVU293
1102 0016 7047 bx lr
1103 .L75:
1104 .align 2
1105 .L74:
1106 0018 00E100E0 .word -536813312
1107 .cfi_endproc
1108 .LFE143:
1110 .section .text.HAL_NVIC_GetActive,"ax",%progbits
1111 .align 1
1112 .global HAL_NVIC_GetActive
1113 .syntax unified
1114 .thumb
1115 .thumb_func
1117 HAL_NVIC_GetActive:
1118 .LVL67:
1119 .LFB144:
438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number
442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval status: - 0 Interrupt status is not pending.
445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * - 1 Interrupt status is pending.
446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
1120 .loc 1 448 1 is_stmt 1 view -0
1121 .cfi_startproc
1122 @ args = 0, pretend = 0, frame = 0
1123 @ frame_needed = 0, uses_anonymous_args = 0
1124 @ link register save eliminated.
449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Return 1 if active else 0U */
450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** return NVIC_GetActive(IRQn);
1125 .loc 1 450 3 view .LVU295
1126 .LBB58:
1127 .LBI58:
1794:Drivers/CMSIS/Include/core_cm4.h **** {
1128 .loc 2 1794 26 view .LVU296
1129 .LBB59:
1796:Drivers/CMSIS/Include/core_cm4.h **** {
1130 .loc 2 1796 3 view .LVU297
1796:Drivers/CMSIS/Include/core_cm4.h **** {
1131 .loc 2 1796 6 is_stmt 0 view .LVU298
1132 0000 0028 cmp r0, #0
1133 .LVL68:
1796:Drivers/CMSIS/Include/core_cm4.h **** {
1134 .loc 2 1796 6 view .LVU299
1135 0002 0BDB blt .L78
1798:Drivers/CMSIS/Include/core_cm4.h **** }
1136 .loc 2 1798 5 is_stmt 1 view .LVU300
1798:Drivers/CMSIS/Include/core_cm4.h **** }
1137 .loc 2 1798 54 is_stmt 0 view .LVU301
1138 0004 4309 lsrs r3, r0, #5
1798:Drivers/CMSIS/Include/core_cm4.h **** }
1139 .loc 2 1798 35 view .LVU302
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 81
1140 0006 8033 adds r3, r3, #128
1141 0008 054A ldr r2, .L79
1142 000a 52F82330 ldr r3, [r2, r3, lsl #2]
1798:Drivers/CMSIS/Include/core_cm4.h **** }
1143 .loc 2 1798 91 view .LVU303
1144 000e 00F01F00 and r0, r0, #31
1798:Drivers/CMSIS/Include/core_cm4.h **** }
1145 .loc 2 1798 103 view .LVU304
1146 0012 23FA00F0 lsr r0, r3, r0
1798:Drivers/CMSIS/Include/core_cm4.h **** }
1147 .loc 2 1798 12 view .LVU305
1148 0016 00F00100 and r0, r0, #1
1149 001a 7047 bx lr
1150 .L78:
1802:Drivers/CMSIS/Include/core_cm4.h **** }
1151 .loc 2 1802 11 view .LVU306
1152 001c 0020 movs r0, #0
1153 .LVL69:
1802:Drivers/CMSIS/Include/core_cm4.h **** }
1154 .loc 2 1802 11 view .LVU307
1155 .LBE59:
1156 .LBE58:
451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
1157 .loc 1 451 1 view .LVU308
1158 001e 7047 bx lr
1159 .L80:
1160 .align 2
1161 .L79:
1162 0020 00E100E0 .word -536813312
1163 .cfi_endproc
1164 .LFE144:
1166 .section .text.HAL_SYSTICK_CLKSourceConfig,"ax",%progbits
1167 .align 1
1168 .global HAL_SYSTICK_CLKSourceConfig
1169 .syntax unified
1170 .thumb
1171 .thumb_func
1173 HAL_SYSTICK_CLKSourceConfig:
1174 .LVL70:
1175 .LFB145:
452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Configures the SysTick clock source.
455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param CLKSource specifies the SysTick clock source.
456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be one of the following values:
457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock
458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None
460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
1176 .loc 1 462 1 is_stmt 1 view -0
1177 .cfi_startproc
1178 @ args = 0, pretend = 0, frame = 0
1179 @ frame_needed = 0, uses_anonymous_args = 0
1180 @ link register save eliminated.
463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 82
464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
1181 .loc 1 464 3 view .LVU310
465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
1182 .loc 1 465 3 view .LVU311
1183 .loc 1 465 6 is_stmt 0 view .LVU312
1184 0000 0428 cmp r0, #4
1185 0002 06D0 beq .L84
466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** else
470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
1186 .loc 1 471 5 is_stmt 1 view .LVU313
1187 .loc 1 471 12 is_stmt 0 view .LVU314
1188 0004 4FF0E022 mov r2, #-536813568
1189 0008 1369 ldr r3, [r2, #16]
1190 .loc 1 471 19 view .LVU315
1191 000a 23F00403 bic r3, r3, #4
1192 000e 1361 str r3, [r2, #16]
472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
1193 .loc 1 473 1 view .LVU316
1194 0010 7047 bx lr
1195 .L84:
467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
1196 .loc 1 467 5 is_stmt 1 view .LVU317
467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
1197 .loc 1 467 12 is_stmt 0 view .LVU318
1198 0012 4FF0E022 mov r2, #-536813568
1199 0016 1369 ldr r3, [r2, #16]
467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
1200 .loc 1 467 19 view .LVU319
1201 0018 43F00403 orr r3, r3, #4
1202 001c 1361 str r3, [r2, #16]
1203 001e 7047 bx lr
1204 .cfi_endproc
1205 .LFE145:
1207 .section .text.HAL_SYSTICK_Callback,"ax",%progbits
1208 .align 1
1209 .weak HAL_SYSTICK_Callback
1210 .syntax unified
1211 .thumb
1212 .thumb_func
1214 HAL_SYSTICK_Callback:
1215 .LFB147:
474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief This function handles SYSTICK interrupt request.
477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None
478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_SYSTICK_IRQHandler(void)
480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** HAL_SYSTICK_Callback();
482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 83
485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief SYSTICK callback.
486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None
487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** __weak void HAL_SYSTICK_Callback(void)
489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
1216 .loc 1 489 1 is_stmt 1 view -0
1217 .cfi_startproc
1218 @ args = 0, pretend = 0, frame = 0
1219 @ frame_needed = 0, uses_anonymous_args = 0
1220 @ link register save eliminated.
490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* NOTE : This function Should not be modified, when the callback is needed,
491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** the HAL_SYSTICK_Callback could be implemented in the user file
492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
1221 .loc 1 493 1 view .LVU321
1222 0000 7047 bx lr
1223 .cfi_endproc
1224 .LFE147:
1226 .section .text.HAL_SYSTICK_IRQHandler,"ax",%progbits
1227 .align 1
1228 .global HAL_SYSTICK_IRQHandler
1229 .syntax unified
1230 .thumb
1231 .thumb_func
1233 HAL_SYSTICK_IRQHandler:
1234 .LFB146:
480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** HAL_SYSTICK_Callback();
1235 .loc 1 480 1 view -0
1236 .cfi_startproc
1237 @ args = 0, pretend = 0, frame = 0
1238 @ frame_needed = 0, uses_anonymous_args = 0
1239 0000 08B5 push {r3, lr}
1240 .cfi_def_cfa_offset 8
1241 .cfi_offset 3, -8
1242 .cfi_offset 14, -4
481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
1243 .loc 1 481 3 view .LVU323
1244 0002 FFF7FEFF bl HAL_SYSTICK_Callback
1245 .LVL71:
482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
1246 .loc 1 482 1 is_stmt 0 view .LVU324
1247 0006 08BD pop {r3, pc}
1248 .cfi_endproc
1249 .LFE146:
1251 .text
1252 .Letext0:
1253 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
1254 .file 5 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
1255 .file 6 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
1256 .file 7 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h"
1257 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 84
DEFINED SYMBOLS
*ABS*:00000000 stm32f3xx_hal_cortex.c
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:21 .text.__NVIC_DisableIRQ:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:26 .text.__NVIC_DisableIRQ:00000000 __NVIC_DisableIRQ
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:88 .text.__NVIC_DisableIRQ:00000020 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:93 .text.__NVIC_SetPriority:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:98 .text.__NVIC_SetPriority:00000000 __NVIC_SetPriority
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:141 .text.__NVIC_SetPriority:00000024 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:146 .text.__NVIC_GetPriority:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:151 .text.__NVIC_GetPriority:00000000 __NVIC_GetPriority
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:187 .text.__NVIC_GetPriority:00000020 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:192 .text.NVIC_EncodePriority:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:197 .text.NVIC_EncodePriority:00000000 NVIC_EncodePriority
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:258 .text.NVIC_DecodePriority:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:263 .text.NVIC_DecodePriority:00000000 NVIC_DecodePriority
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:331 .text.__NVIC_SystemReset:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:336 .text.__NVIC_SystemReset:00000000 __NVIC_SystemReset
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:397 .text.__NVIC_SystemReset:0000001c $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:403 .text.HAL_NVIC_SetPriorityGrouping:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:409 .text.HAL_NVIC_SetPriorityGrouping:00000000 HAL_NVIC_SetPriorityGrouping
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:463 .text.HAL_NVIC_SetPriorityGrouping:00000020 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:468 .text.HAL_NVIC_SetPriority:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:474 .text.HAL_NVIC_SetPriority:00000000 HAL_NVIC_SetPriority
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:520 .text.HAL_NVIC_SetPriority:0000001c $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:525 .text.HAL_NVIC_EnableIRQ:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:531 .text.HAL_NVIC_EnableIRQ:00000000 HAL_NVIC_EnableIRQ
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:572 .text.HAL_NVIC_EnableIRQ:00000018 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:577 .text.HAL_NVIC_DisableIRQ:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:583 .text.HAL_NVIC_DisableIRQ:00000000 HAL_NVIC_DisableIRQ
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:605 .text.HAL_NVIC_SystemReset:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:611 .text.HAL_NVIC_SystemReset:00000000 HAL_NVIC_SystemReset
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:629 .text.HAL_SYSTICK_Config:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:635 .text.HAL_SYSTICK_Config:00000000 HAL_SYSTICK_Config
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:700 .text.HAL_SYSTICK_Config:00000024 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:705 .text.HAL_MPU_Disable:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:711 .text.HAL_MPU_Disable:00000000 HAL_MPU_Disable
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:734 .text.HAL_MPU_Disable:00000014 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:739 .text.HAL_MPU_Enable:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:745 .text.HAL_MPU_Enable:00000000 HAL_MPU_Enable
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:771 .text.HAL_MPU_Enable:00000014 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:776 .text.HAL_MPU_ConfigRegion:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:782 .text.HAL_MPU_ConfigRegion:00000000 HAL_MPU_ConfigRegion
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:871 .text.HAL_MPU_ConfigRegion:0000005c $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:876 .text.HAL_NVIC_GetPriorityGrouping:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:882 .text.HAL_NVIC_GetPriorityGrouping:00000000 HAL_NVIC_GetPriorityGrouping
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:906 .text.HAL_NVIC_GetPriorityGrouping:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:911 .text.HAL_NVIC_GetPriority:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:917 .text.HAL_NVIC_GetPriority:00000000 HAL_NVIC_GetPriority
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:951 .text.HAL_NVIC_SetPendingIRQ:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:957 .text.HAL_NVIC_SetPendingIRQ:00000000 HAL_NVIC_SetPendingIRQ
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:998 .text.HAL_NVIC_SetPendingIRQ:00000018 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1003 .text.HAL_NVIC_GetPendingIRQ:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1009 .text.HAL_NVIC_GetPendingIRQ:00000000 HAL_NVIC_GetPendingIRQ
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1054 .text.HAL_NVIC_GetPendingIRQ:00000020 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1059 .text.HAL_NVIC_ClearPendingIRQ:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1065 .text.HAL_NVIC_ClearPendingIRQ:00000000 HAL_NVIC_ClearPendingIRQ
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1106 .text.HAL_NVIC_ClearPendingIRQ:00000018 $d
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 85
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1111 .text.HAL_NVIC_GetActive:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1117 .text.HAL_NVIC_GetActive:00000000 HAL_NVIC_GetActive
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1162 .text.HAL_NVIC_GetActive:00000020 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1167 .text.HAL_SYSTICK_CLKSourceConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1173 .text.HAL_SYSTICK_CLKSourceConfig:00000000 HAL_SYSTICK_CLKSourceConfig
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1208 .text.HAL_SYSTICK_Callback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1214 .text.HAL_SYSTICK_Callback:00000000 HAL_SYSTICK_Callback
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1227 .text.HAL_SYSTICK_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1233 .text.HAL_SYSTICK_IRQHandler:00000000 HAL_SYSTICK_IRQHandler
NO UNDEFINED SYMBOLS