FaSTTUBe/PDU_Code
37
1
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

gss active , current monitor after channel contr check

Browse Source
This commit is contained in:
n.jayaprakash 2024-05-15 21:16:02 +02:00
parent 4d202916e8
commit d9d7da87c0
109 changed files with 6531 additions and 148931 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
.vscode/launch.json vendored
View File

@ -3,7 +3,7 @@
{
"showDevDebugOutput": "parsed",
"cwd": "${workspaceRoot}",
"executable": "./build/PDU_FT23.elf",
"executable": "./build/PDU_FT24_Code.elf",
"name": "Debug STM32",
"request": "launch",
"type": "cortex-debug",
@ -17,7 +17,7 @@
{
"showDevDebugOutput": "parsed",
"cwd": "${workspaceRoot}",
"executable": "./build/PDU_FT23.elf",
"executable": "./build/PDU_FT24_Code.elf",
"name": "Attach STM32",
"request": "attach",
"type": "cortex-debug",

9
Core/Src/Channel_Control.c
View File

@ -35,14 +35,14 @@ void ChannelControl_init(I2C_HandleTypeDef* hi2c, TIM_HandleTypeDef* timer3,
void ChannelControl_UpdateGPIOs(PortExtenderGPIO UpdatePorts) { // ctrl + left click auf portextender
EN_Ports = UpdatePorts;
UpdatePorts.porta.alwayson = 1; // Always on stays always on
UpdatePorts.porta.alwayson = 1;// Always on stays always on
PCA9535_setGPIOPortOutput(PC9535_PORTA, UpdatePorts.porta.porta);
PCA9535_setGPIOPortOutput(PC9535_PORTB, UpdatePorts.portb.portb);
gpio_port_b testb={};
testb.en14=1;
PCA9535_setGPIOPortOutput(PC9535_PORTB, testb.portb);
testb.en16=1;
PCA9535_setGPIOPortOutput(PC9535_PORTB, testb.portb);
gpio_port_a testa={};
testa.en13=1;
testa.en1=1;
PCA9535_setGPIOPortOutput(PC9535_PORTA, testa.porta);
@ -50,6 +50,7 @@ void ChannelControl_UpdateGPIOs(PortExtenderGPIO UpdatePorts) { // ctrl + left c
void ChannelControl_UpdatePWMs(uint8_t radiatorfans,uint8_t tsacfans , uint8_t pwmaggregat,
uint8_t pwmpumps){
return;
pwmtimer3->Instance->CCR4 = pwmpumps << 8;

2
Core/Src/Current_Monitoring.c
View File

@ -55,7 +55,7 @@ void currentMonitor_init(ADC_HandleTypeDef* hadc1, ADC_HandleTypeDef* hadc2, //
adc2 = hadc2;
HAL_TIM_Base_Start(trigtim);
HAL_ADC_Start_DMA(hadc1, (uint32_t*)adc_channels1.adcbuffer, 7);
HAL_ADC_Start_DMA(hadc2, (uint32_t*)adc_channels2.adcbuffer, 4); // wie adc mit dma geht , red mit jasper
HAL_ADC_Start_DMA(hadc2, (uint32_t*)adc_channels2.adcbuffer, 7); // wie adc mit dma geht , red mit jasper
}
uint8_t currentMonitor_checklimits() { return 0; }

68
Core/Src/main.c
View File

@ -52,6 +52,7 @@ I2C_HandleTypeDef hi2c1;
TIM_HandleTypeDef htim2;
TIM_HandleTypeDef htim3;
TIM_HandleTypeDef htim6;
UART_HandleTypeDef huart1;
/* USER CODE BEGIN PV */
@ -68,6 +69,7 @@ static void MX_TIM2_Init(void);
static void MX_TIM3_Init(void);
static void MX_I2C1_Init(void);
static void MX_USART1_UART_Init(void);
static void MX_TIM6_Init(void);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
@ -116,19 +118,19 @@ int main(void)
MX_TIM3_Init();
MX_I2C1_Init();
MX_USART1_UART_Init();
MX_TIM6_Init();
/* USER CODE BEGIN 2 */
// HAL_GPIO_WritePin(Status_LED_GPIO_Port, Status_LED_Pin, GPIO_PIN_SET); // status led wird an gemacht , das leuchtet
currentMonitor_init(&hadc1, &hadc2, &htim6); // handler struktur ( handler adc1 .... usw )
ChannelControl_init(&hi2c1, &htim3, &htim2);
can_init(&hcan); // can bus initilisiert , kommunikation zum hauptsteuergeraet ( autobox )
// HAL_GPIO_WritePin(STATUS_LED2_GPIO_Port, STATUS_LED2_Pin, GPIO_PIN_SET); // status led wird an gemacht , das leuchtet
HAL_GPIO_WritePin(STATUS_LED1_GPIO_Port , STATUS_LED1_Pin , GPIO_PIN_SET);
HAL_GPIO_WritePin( GSS_GPIO_GPIO_Port, GSS_GPIO_Pin , GPIO_PIN_SET);
ChannelControl_init(&hi2c1, &htim3, &htim2);
// handler struktur ( handler adc1 .... usw )
can_init(&hcan); // can bus initilisiert , kommunikation zum hauptsteuergeraet ( autobox )
currentMonitor_init(&hadc1, &hadc2, &htim6);
uint32_t lasttick = HAL_GetTick(); // gibt dir zuruck die milisekunden seit start. ( es fangt an und dann milisekunden + 1 usw....)
HAL_TIM_Base_Start(&htim2);
HAL_TIM_Base_Start(&htim3);
HAL_GPIO_WritePin(STATUS_LED1_GPIO_Port , STATUS_LED1_Pin , GPIO_PIN_SET);
// Turn everything on manually (debug)
HAL_TIM_Base_Start(&htim2);
HAL_TIM_Base_Start(&htim3);
/* USER CODE END 2 */
/* Infinite loop */
@ -147,7 +149,7 @@ while(1)
if ((HAL_GetTick() - lasttick) > 100U) {
lasttick = HAL_GetTick();
//can_sendloop();
can_sendloop();
}
currentMonitor_checklimits(); // ob irgnwo ueberstrom getreten ist
@ -518,6 +520,44 @@ static void MX_TIM3_Init(void)
}
/**
* @brief TIM6 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM6_Init(void)
{
/* USER CODE BEGIN TIM6_Init 0 */
/* USER CODE END TIM6_Init 0 */
TIM_MasterConfigTypeDef sMasterConfig = {0};
/* USER CODE BEGIN TIM6_Init 1 */
/* USER CODE END TIM6_Init 1 */
htim6.Instance = TIM6;
htim6.Init.Prescaler = 400;
htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
htim6.Init.Period = 8000-1;
htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
{
Error_Handler();
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN TIM6_Init 2 */
/* USER CODE END TIM6_Init 2 */
}
/**
* @brief USART1 Initialization Function
* @param None
@ -571,15 +611,15 @@ static void MX_GPIO_Init(void)
__HAL_RCC_GPIOB_CLK_ENABLE();
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0|DSEL_3_Pin|DSEL_4_Pin|DSEL_5_Pin
HAL_GPIO_WritePin(GPIOB, GSS_GPIO_Pin|DSEL_3_Pin|DSEL_4_Pin|DSEL_5_Pin
|DSEL_6_Pin|DSEL_7_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, STATUS_LED1_Pin|STATUS_LED2_Pin|STATUS_LED3_Pin|STATUS_LED4_Pin, GPIO_PIN_RESET);
/*Configure GPIO pins : PB0 DSEL_3_Pin DSEL_4_Pin DSEL_5_Pin
/*Configure GPIO pins : GSS_GPIO_Pin DSEL_3_Pin DSEL_4_Pin DSEL_5_Pin
DSEL_6_Pin DSEL_7_Pin */
GPIO_InitStruct.Pin = GPIO_PIN_0|DSEL_3_Pin|DSEL_4_Pin|DSEL_5_Pin
GPIO_InitStruct.Pin = GSS_GPIO_Pin|DSEL_3_Pin|DSEL_4_Pin|DSEL_5_Pin
|DSEL_6_Pin|DSEL_7_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;

57
Debug/Core/Src/subdir.mk
View File

@ -1,57 +0,0 @@
################################################################################
# Automatically-generated file. Do not edit!
# Toolchain: GNU Tools for STM32 (10.3-2021.10)
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
C_SRCS += \
../Core/Src/CAN_Communication.c \
../Core/Src/Channel_Control.c \
../Core/Src/Current_Monitoring.c \
../Core/Src/PCA9535D_Driver.c \
../Core/Src/can-halal.c \
../Core/Src/main.c \
../Core/Src/stm32g4xx_hal_msp.c \
../Core/Src/stm32g4xx_it.c \
../Core/Src/syscalls.c \
../Core/Src/sysmem.c \
../Core/Src/system_stm32g4xx.c
OBJS += \
./Core/Src/CAN_Communication.o \
./Core/Src/Channel_Control.o \
./Core/Src/Current_Monitoring.o \
./Core/Src/PCA9535D_Driver.o \
./Core/Src/can-halal.o \
./Core/Src/main.o \
./Core/Src/stm32g4xx_hal_msp.o \
./Core/Src/stm32g4xx_it.o \
./Core/Src/syscalls.o \
./Core/Src/sysmem.o \
./Core/Src/system_stm32g4xx.o
C_DEPS += \
./Core/Src/CAN_Communication.d \
./Core/Src/Channel_Control.d \
./Core/Src/Current_Monitoring.d \
./Core/Src/PCA9535D_Driver.d \
./Core/Src/can-halal.d \
./Core/Src/main.d \
./Core/Src/stm32g4xx_hal_msp.d \
./Core/Src/stm32g4xx_it.d \
./Core/Src/syscalls.d \
./Core/Src/sysmem.d \
./Core/Src/system_stm32g4xx.d
# Each subdirectory must supply rules for building sources it contributes
Core/Src/%.o Core/Src/%.su: ../Core/Src/%.c Core/Src/subdir.mk
arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32G431xx -c -I../Core/Inc -I../Drivers/STM32G4xx_HAL_Driver/Inc -I../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32G4xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
clean: clean-Core-2f-Src
clean-Core-2f-Src:
-$(RM) ./Core/Src/CAN_Communication.d ./Core/Src/CAN_Communication.o ./Core/Src/CAN_Communication.su ./Core/Src/Channel_Control.d ./Core/Src/Channel_Control.o ./Core/Src/Channel_Control.su ./Core/Src/Current_Monitoring.d ./Core/Src/Current_Monitoring.o ./Core/Src/Current_Monitoring.su ./Core/Src/PCA9535D_Driver.d ./Core/Src/PCA9535D_Driver.o ./Core/Src/PCA9535D_Driver.su ./Core/Src/can-halal.d ./Core/Src/can-halal.o ./Core/Src/can-halal.su ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/stm32g4xx_hal_msp.d ./Core/Src/stm32g4xx_hal_msp.o ./Core/Src/stm32g4xx_hal_msp.su ./Core/Src/stm32g4xx_it.d ./Core/Src/stm32g4xx_it.o ./Core/Src/stm32g4xx_it.su ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32g4xx.d ./Core/Src/system_stm32g4xx.o ./Core/Src/system_stm32g4xx.su
.PHONY: clean-Core-2f-Src

27
Debug/Core/Startup/subdir.mk
View File

@ -1,27 +0,0 @@
################################################################################
# Automatically-generated file. Do not edit!
# Toolchain: GNU Tools for STM32 (10.3-2021.10)
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
S_SRCS += \
../Core/Startup/startup_stm32g431cbtx.s
OBJS += \
./Core/Startup/startup_stm32g431cbtx.o
S_DEPS += \
./Core/Startup/startup_stm32g431cbtx.d
# Each subdirectory must supply rules for building sources it contributes
Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk
arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" "$<"
clean: clean-Core-2f-Startup
clean-Core-2f-Startup:
-$(RM) ./Core/Startup/startup_stm32g431cbtx.d ./Core/Startup/startup_stm32g431cbtx.o
.PHONY: clean-Core-2f-Startup

87
Debug/Drivers/STM32G4xx_HAL_Driver/Src/subdir.mk
View File

@ -1,87 +0,0 @@
################################################################################
# Automatically-generated file. Do not edit!
# Toolchain: GNU Tools for STM32 (10.3-2021.10)
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
C_SRCS += \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c \
../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c
OBJS += \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.o
C_DEPS += \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.d \
./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.d
# Each subdirectory must supply rules for building sources it contributes
Drivers/STM32G4xx_HAL_Driver/Src/%.o Drivers/STM32G4xx_HAL_Driver/Src/%.su: ../Drivers/STM32G4xx_HAL_Driver/Src/%.c Drivers/STM32G4xx_HAL_Driver/Src/subdir.mk
arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32G431xx -c -I../Core/Inc -I../Drivers/STM32G4xx_HAL_Driver/Inc -I../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32G4xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
clean: clean-Drivers-2f-STM32G4xx_HAL_Driver-2f-Src
clean-Drivers-2f-STM32G4xx_HAL_Driver-2f-Src:
-$(RM) ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.su
.PHONY: clean-Drivers-2f-STM32G4xx_HAL_Driver-2f-Src

21794
Debug/PDU_FT23.list
View File

File diff suppressed because it is too large Load Diff

33
Debug/objects.list
View File

@ -1,33 +0,0 @@
"./Core/Src/CAN_Communication.o"
"./Core/Src/Channel_Control.o"
"./Core/Src/Current_Monitoring.o"
"./Core/Src/PCA9535D_Driver.o"
"./Core/Src/can-halal.o"
"./Core/Src/main.o"
"./Core/Src/stm32g4xx_hal_msp.o"
"./Core/Src/stm32g4xx_it.o"
"./Core/Src/syscalls.o"
"./Core/Src/sysmem.o"
"./Core/Src/system_stm32g4xx.o"
"./Core/Startup/startup_stm32g431cbtx.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o"
"./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.o"

9
Debug/objects.mk
View File

@ -1,9 +0,0 @@
################################################################################
# Automatically-generated file. Do not edit!
# Toolchain: GNU Tools for STM32 (10.3-2021.10)
################################################################################
USER_OBJS :=
LIBS :=

27
Debug/sources.mk
View File

@ -1,27 +0,0 @@
################################################################################
# Automatically-generated file. Do not edit!
# Toolchain: GNU Tools for STM32 (10.3-2021.10)
################################################################################
ELF_SRCS :=
OBJ_SRCS :=
S_SRCS :=
C_SRCS :=
S_UPPER_SRCS :=
O_SRCS :=
SIZE_OUTPUT :=
OBJDUMP_LIST :=
SU_FILES :=
EXECUTABLES :=
OBJS :=
MAP_FILES :=
S_DEPS :=
S_UPPER_DEPS :=
C_DEPS :=
# Every subdirectory with source files must be described here
SUBDIRS := \
Core/Src \
Core/Startup \
Drivers/STM32G4xx_HAL_Driver/Src \

3912
Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
View File

File diff suppressed because it is too large Load Diff

624
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h
View File

@ -1,624 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_H
#define STM32G4xx_HAL_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_conf.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup HAL HAL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{
*/
/** @defgroup HAL_TICK_FREQ Tick Frequency
* @{
*/
#define HAL_TICK_FREQ_10HZ 100U
#define HAL_TICK_FREQ_100HZ 10U
#define HAL_TICK_FREQ_1KHZ 1U
#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ
/**
* @}
*/
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
* @{
*/
/** @defgroup SYSCFG_BootMode Boot Mode
* @{
*/
#define SYSCFG_BOOT_MAINFLASH 0x00000000U
#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMMEMRMP_MODE_0
#if defined (FMC_BANK1)
#define SYSCFG_BOOT_FMC SYSCFG_MEMMEMRMP_MODE_1
#endif /* FMC_BANK1 */
#define SYSCFG_BOOT_SRAM (SYSCFG_MEMMEMRMP_MODE_1 | SYSCFG_MEMMEMRMP_MODE_0)
#if defined (QUADSPI)
#define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMMEMRMP_MODE_2 | SYSCFG_MEMMEMRMP_MODE_1)
#endif /* QUADSPI */
/**
* @}
*/
/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
* @{
*/
#define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */
#define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */
#define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */
#define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */
#define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */
#define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */
/**
* @}
*/
/** @defgroup SYSCFG_CCMSRAMWRP CCM Write protection
* @{
*/
#define SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< CCMSRAM Write protection page 0 */
#define SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< CCMSRAM Write protection page 1 */
#define SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< CCMSRAM Write protection page 2 */
#define SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< CCMSRAM Write protection page 3 */
#define SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< CCMSRAM Write protection page 4 */
#define SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< CCMSRAM Write protection page 5 */
#define SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< CCMSRAM Write protection page 6 */
#define SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< CCMSRAM Write protection page 7 */
#define SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< CCMSRAM Write protection page 8 */
#define SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< CCMSRAM Write protection page 9 */
#define SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */
#define SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */
#define SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< CCMSRAM Write protection page 12 */
#define SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< CCMSRAM Write protection page 13 */
#define SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< CCMSRAM Write protection page 14 */
#define SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< CCMSRAM Write protection page 15 */
#define SYSCFG_CCMSRAMWRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< CCMSRAM Write protection page 16 */
#define SYSCFG_CCMSRAMWRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< CCMSRAM Write protection page 17 */
#define SYSCFG_CCMSRAMWRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< CCMSRAM Write protection page 18 */
#define SYSCFG_CCMSRAMWRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< CCMSRAM Write protection page 19 */
#define SYSCFG_CCMSRAMWRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< CCMSRAM Write protection page 20 */
#define SYSCFG_CCMSRAMWRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< CCMSRAM Write protection page 21 */
#define SYSCFG_CCMSRAMWRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< CCMSRAM Write protection page 22 */
#define SYSCFG_CCMSRAMWRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< CCMSRAM Write protection page 23 */
#define SYSCFG_CCMSRAMWRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< CCMSRAM Write protection page 24 */
#define SYSCFG_CCMSRAMWRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< CCMSRAM Write protection page 25 */
#define SYSCFG_CCMSRAMWRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< CCMSRAM Write protection page 26 */
#define SYSCFG_CCMSRAMWRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< CCMSRAM Write protection page 27 */
#define SYSCFG_CCMSRAMWRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< CCMSRAM Write protection page 28 */
#define SYSCFG_CCMSRAMWRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< CCMSRAM Write protection page 29 */
#define SYSCFG_CCMSRAMWRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< CCMSRAM Write protection page 30 */
#define SYSCFG_CCMSRAMWRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< CCMSRAM Write protection page 31 */
/**
* @}
*/
#if defined(VREFBUF)
/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
* @{
*/
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0x00000000U /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) */
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V) */
#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V) */
/**
* @}
*/
/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
* @{
*/
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
/**
* @}
*/
#endif /* VREFBUF */
/** @defgroup SYSCFG_flags_definition Flags
* @{
*/
#define SYSCFG_FLAG_SRAM_PE SYSCFG_CFGR2_SPF /*!< SRAM parity error (first 32kB of SRAM1 + CCM SRAM) */
#define SYSCFG_FLAG_CCMSRAM_BUSY SYSCFG_SCSR_CCMBSY /*!< CCMSRAM busy by erase operation */
/**
* @}
*/
/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
* @{
*/
/** @brief Fast-mode Plus driving capability on a specific GPIO
*/
#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */
#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
* @{
*/
/** @brief Freeze/Unfreeze Peripherals in Debug mode
*/
#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_RTC_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_I2C3_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_LPTIM1_STOP */
#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)
#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
#endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */
#if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
#endif /* DBGMCU_APB2FZ_DBG_TIM1_STOP */
#if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)
#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
#endif /* DBGMCU_APB2FZ_DBG_TIM8_STOP */
#if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)
#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
#endif /* DBGMCU_APB2FZ_DBG_TIM15_STOP */
#if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)
#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
#endif /* DBGMCU_APB2FZ_DBG_TIM16_STOP */
#if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)
#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
#endif /* DBGMCU_APB2FZ_DBG_TIM17_STOP */
#if defined(DBGMCU_APB2FZ_DBG_TIM20_STOP)
#define __HAL_DBGMCU_FREEZE_TIM20() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM20() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP)
#endif /* DBGMCU_APB2FZ_DBG_TIM20_STOP */
#if defined(DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
#define __HAL_DBGMCU_FREEZE_HRTIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_HRTIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
#endif /* DBGMCU_APB2FZ_DBG_HRTIM1_STOP */
/**
* @}
*/
/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
* @{
*/
/** @brief Main Flash memory mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
/** @brief System Flash memory mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
/** @brief Embedded SRAM mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
#if defined (FMC_BANK1)
/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
#endif /* FMC_BANK1 */
#if defined (QUADSPI)
/** @brief QUADSPI mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))
#endif /* QUADSPI */
/**
* @brief Return the boot mode as configured by user.
* @retval The boot mode as configured by user. The returned value can be one
* of the following values:
* @arg @ref SYSCFG_BOOT_MAINFLASH
* @arg @ref SYSCFG_BOOT_SYSTEMFLASH
* @arg @ref SYSCFG_BOOT_FMC (*)
* @arg @ref SYSCFG_BOOT_QUADSPI (*)
* @arg @ref SYSCFG_BOOT_SRAM
* @note (*) availability depends on devices
*/
#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
/** @brief CCMSRAM page write protection enable macro
* @param __CCMSRAMWRP__: This parameter can be a value of @ref SYSCFG_CCMSRAMWRP
* @note write protection can only be disabled by a system reset
* @retval None
*/
/* Legacy define */
#define __HAL_SYSCFG_CCMSRAM_WRP_1_31_ENABLE __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE
#define __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE(__CCMSRAMWRP__) do {assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE((__CCMSRAMWRP__)));\
SET_BIT(SYSCFG->SWPR,(__CCMSRAMWRP__));\
}while(0)
/** @brief CCMSRAM page write protection unlock prior to erase
* @note Writing a wrong key reactivates the write protection
*/
#define __HAL_SYSCFG_CCMSRAM_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\
SYSCFG->SKR = 0x53;\
}while(0)
/** @brief CCMSRAM erase
* @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_CCMSRAM_BUSY) may be used to check end of erase
*/
#define __HAL_SYSCFG_CCMSRAM_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER)
/** @brief Floating Point Unit interrupt enable/disable macros
* @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts
*/
#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
}while(0)
#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
}while(0)
/** @brief SYSCFG Break ECC lock.
* Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
/** @brief SYSCFG Break Cortex-M4 Lockup lock.
* Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
/** @brief SYSCFG Break PVD lock.
* Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
/** @brief SYSCFG Break SRAM parity lock.
* Enable and lock the SRAM parity error (first 32kB of SRAM1 + CCM SRAM) signal connection to TIM1/8/15/16/17 Break input.
* @note The selected configuration is locked and can be unlocked by system reset.
*/
#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
/** @brief Check SYSCFG flag is set or not.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref SYSCFG_FLAG_SRAM_PE SRAM Parity Error Flag
* @arg @ref SYSCFG_FLAG_CCMSRAM_BUSY CCMSRAM Erase Ongoing
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_CCMBSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\
& (__FLAG__))!= 0U) ? 1U : 0U)
/** @brief Set the SPF bit to clear the SRAM Parity Error Flag.
*/
#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
/** @brief Fast-mode Plus driving capability enable/disable macros
* @param __FASTMODEPLUS__: This parameter can be a value of :
* @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
* @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
* @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
* @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
*/
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
}while(0)
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
}while(0)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
* @{
*/
#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \
((__CONFIG__) == SYSCFG_BREAK_PVD) || \
((__CONFIG__) == SYSCFG_BREAK_SRAMPARITY) || \
((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
#if (CCMSRAM_SIZE == 0x00008000UL) || (CCMSRAM_SIZE == 0x00004000UL)
#define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) ((__PAGE__) > 0U)
#elif (CCMSRAM_SIZE == 0x00002800UL)
#define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000003FFU))
#endif /* CCMSRAM_SIZE */
#if defined(VREFBUF)
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2))
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#endif /* VREFBUF */
#if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
#elif defined(SYSCFG_FASTMODEPLUS_PB8)
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))
#elif defined(SYSCFG_FASTMODEPLUS_PB9)
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
#else
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))
#endif /* SYSCFG_FASTMODEPLUS_PB */
/**
* @}
*/
/** @defgroup HAL_Private_Macros HAL Private Macros
* @{
*/
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
((FREQ) == HAL_TICK_FREQ_100HZ) || \
((FREQ) == HAL_TICK_FREQ_1KHZ))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions
* @{
*/
/** @addtogroup HAL_Exported_Functions_Group1
* @{
*/
/* Initialization and Configuration functions ******************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
* @{
*/
/* Peripheral Control functions ************************************************/
void HAL_IncTick(void);
void HAL_Delay(uint32_t Delay);
uint32_t HAL_GetTick(void);
uint32_t HAL_GetTickPrio(void);
HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq);
uint32_t HAL_GetTickFreq(void);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group3
* @{
*/
/* DBGMCU Peripheral Control functions *****************************************/
void HAL_DBGMCU_EnableDBGSleepMode(void);
void HAL_DBGMCU_DisableDBGSleepMode(void);
void HAL_DBGMCU_EnableDBGStopMode(void);
void HAL_DBGMCU_DisableDBGStopMode(void);
void HAL_DBGMCU_EnableDBGStandbyMode(void);
void HAL_DBGMCU_DisableDBGStandbyMode(void);
/**
* @}
*/
/* Exported variables ---------------------------------------------------------*/
/** @addtogroup HAL_Exported_Variables
* @{
*/
extern __IO uint32_t uwTick;
extern uint32_t uwTickPrio;
extern uint32_t uwTickFreq;
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group4
* @{
*/
/* SYSCFG Control functions ****************************************************/
void HAL_SYSCFG_CCMSRAMErase(void);
void HAL_SYSCFG_EnableMemorySwappingBank(void);
void HAL_SYSCFG_DisableMemorySwappingBank(void);
#if defined(VREFBUF)
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
void HAL_SYSCFG_DisableVREFBUF(void);
#endif /* VREFBUF */
void HAL_SYSCFG_EnableIOSwitchBooster(void);
void HAL_SYSCFG_DisableIOSwitchBooster(void);
void HAL_SYSCFG_EnableIOSwitchVDD(void);
void HAL_SYSCFG_DisableIOSwitchVDD(void);
void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_H */

2034
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h
View File

File diff suppressed because it is too large Load Diff

1393
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h
View File

File diff suppressed because it is too large Load Diff

419
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h
View File

@ -1,419 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32G4xx_HAL_CORTEX_H
#define __STM32G4xx_HAL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @defgroup CORTEX CORTEX
* @brief CORTEX HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
* @{
*/
#if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure
* @{
*/
typedef struct
{
uint8_t Enable; /*!< Specifies the status of the region.
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
uint8_t Number; /*!< Specifies the number of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
uint8_t Size; /*!< Specifies the size of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint8_t TypeExtField; /*!< Specifies the TEX field level.
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
uint8_t AccessPermission; /*!< Specifies the region access permission type.
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
uint8_t DisableExec; /*!< Specifies the instruction access status.
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
}MPU_Region_InitTypeDef;
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
* @{
*/
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{
*/
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bit for pre-emption priority,
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bit for pre-emption priority,
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority,
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority,
1 bit for subpriority */
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority,
0 bit for subpriority */
/**
* @}
*/
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
/**
* @}
*/
#if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
* @{
*/
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{
*/
#define MPU_REGION_ENABLE ((uint8_t)0x01)
#define MPU_REGION_DISABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{
*/
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{
*/
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{
*/
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
* @{
*/
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
#define MPU_TEX_LEVEL4 ((uint8_t)0x04)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{
*/
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and Configuration functions *****************************/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
/**
* @}
*/
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
* @brief Cortex control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
#if (__MPU_PRESENT == 1)
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
* @{
*/
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
((GROUP) == NVIC_PRIORITYGROUP_1) || \
((GROUP) == NVIC_PRIORITYGROUP_2) || \
((GROUP) == NVIC_PRIORITYGROUP_3) || \
((GROUP) == NVIC_PRIORITYGROUP_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
#if (__MPU_PRESENT == 1)
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
((STATE) == MPU_REGION_DISABLE))
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
((TYPE) == MPU_TEX_LEVEL1) || \
((TYPE) == MPU_TEX_LEVEL2) || \
((TYPE) == MPU_TEX_LEVEL4))
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RW) || \
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
((TYPE) == MPU_REGION_FULL_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RO) || \
((TYPE) == MPU_REGION_PRIV_RO_URO))
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
((NUMBER) == MPU_REGION_NUMBER1) || \
((NUMBER) == MPU_REGION_NUMBER2) || \
((NUMBER) == MPU_REGION_NUMBER3) || \
((NUMBER) == MPU_REGION_NUMBER4) || \
((NUMBER) == MPU_REGION_NUMBER5) || \
((NUMBER) == MPU_REGION_NUMBER6) || \
((NUMBER) == MPU_REGION_NUMBER7))
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
((SIZE) == MPU_REGION_SIZE_64B) || \
((SIZE) == MPU_REGION_SIZE_128B) || \
((SIZE) == MPU_REGION_SIZE_256B) || \
((SIZE) == MPU_REGION_SIZE_512B) || \
((SIZE) == MPU_REGION_SIZE_1KB) || \
((SIZE) == MPU_REGION_SIZE_2KB) || \
((SIZE) == MPU_REGION_SIZE_4KB) || \
((SIZE) == MPU_REGION_SIZE_8KB) || \
((SIZE) == MPU_REGION_SIZE_16KB) || \
((SIZE) == MPU_REGION_SIZE_32KB) || \
((SIZE) == MPU_REGION_SIZE_64KB) || \
((SIZE) == MPU_REGION_SIZE_128KB) || \
((SIZE) == MPU_REGION_SIZE_256KB) || \
((SIZE) == MPU_REGION_SIZE_512KB) || \
((SIZE) == MPU_REGION_SIZE_1MB) || \
((SIZE) == MPU_REGION_SIZE_2MB) || \
((SIZE) == MPU_REGION_SIZE_4MB) || \
((SIZE) == MPU_REGION_SIZE_8MB) || \
((SIZE) == MPU_REGION_SIZE_16MB) || \
((SIZE) == MPU_REGION_SIZE_32MB) || \
((SIZE) == MPU_REGION_SIZE_64MB) || \
((SIZE) == MPU_REGION_SIZE_128MB) || \
((SIZE) == MPU_REGION_SIZE_256MB) || \
((SIZE) == MPU_REGION_SIZE_512MB) || \
((SIZE) == MPU_REGION_SIZE_1GB) || \
((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB))
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32G4xx_HAL_CORTEX_H */

209
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h
View File

@ -1,209 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_def.h
* @author MCD Application Team
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32G4xx_HAL_DEF
#define __STM32G4xx_HAL_DEF
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
#include <stddef.h>
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
HAL_BUSY = 0x02U,
HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef;
/**
* @brief HAL Lock structures definition
*/
typedef enum
{
HAL_UNLOCKED = 0x00U,
HAL_LOCKED = 0x01U
} HAL_LockTypeDef;
/* Exported macros -----------------------------------------------------------*/
#define HAL_MAX_DELAY 0xFFFFFFFFU
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
(__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0)
#define UNUSED(X) (void)X
/** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field.
* Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
* @retval None
*/
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
#if (USE_RTOS == 1U)
/* Reserved for future use */
#error " USE_RTOS should be 0 in the current HAL release "
#else
#define __HAL_LOCK(__HANDLE__) \
do{ \
if((__HANDLE__)->Lock == HAL_LOCKED) \
{ \
return HAL_BUSY; \
} \
else \
{ \
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
}while (0U)
#define __HAL_UNLOCK(__HANDLE__) \
do{ \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0U)
#endif /* USE_RTOS */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __weak
#define __weak __attribute__((weak))
#endif
#ifndef __packed
#define __packed __attribute__((packed))
#endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4U)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler V5*/
#define __ALIGN_BEGIN __align(4U)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/**
* @brief __RAM_FUNC definition
*/
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
/* ARM Compiler V4/V5 and V6
--------------------------
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
dialog.
*/
#define __RAM_FUNC
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/
#define __RAM_FUNC __ramfunc
#elif defined ( __GNUC__ )
/* GNU Compiler
------------
RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
*/
#define __RAM_FUNC __attribute__((section(".RamFunc")))
#endif /* __CC_ARM */
/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
/* ARM V4/V5 and V6 & GNU Compiler
-------------------------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
*/
#define __NOINLINE _Pragma("optimize = no_inline")
#endif /* __CC_ARM || __GNUC__ */
#ifdef __cplusplus
}
#endif
#endif /* ___STM32G4xx_HAL_DEF */

852
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h
View File

@ -1,852 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_dma.h
* @author MCD Application Team
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32G4xx_HAL_DMA_H
#define __STM32G4xx_HAL_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DMA_Exported_Types DMA Exported Types
* @{
*/
/**
* @brief DMA Configuration Structure definition
*/
typedef struct
{
uint32_t Request; /*!< Specifies the request selected for the specified channel.
This parameter can be a value of @ref DMA_request */
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
from memory to memory or from peripheral to memory.
This parameter can be a value of @ref DMA_Data_transfer_direction */
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
This parameter can be a value of @ref DMA_Memory_incremented_mode */
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_Peripheral_data_size */
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
This parameter can be a value of @ref DMA_Memory_data_size */
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_mode
@note The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Channel */
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_Priority_level */
} DMA_InitTypeDef;
/**
* @brief HAL DMA State structures definition
*/
typedef enum
{
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
} HAL_DMA_StateTypeDef;
/**
* @brief HAL DMA Error Code structure definition
*/
typedef enum
{
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
} HAL_DMA_LevelCompleteTypeDef;
/**
* @brief HAL DMA Callback ID structure definition
*/
typedef enum
{
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
} HAL_DMA_CallbackIDTypeDef;
/**
* @brief DMA handle Structure definition
*/
typedef struct __DMA_HandleTypeDef
{
DMA_Channel_TypeDef *Instance; /*!< Register base address */
DMA_InitTypeDef Init; /*!< DMA communication parameters */
HAL_LockTypeDef Lock; /*!< DMA locking object */
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
void *Parent; /*!< Parent object state */
void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */
void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
uint32_t ChannelIndex; /*!< DMA Channel Index */
DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */
DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */
uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */
DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */
DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */
uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */
} DMA_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA_Exported_Constants DMA Exported Constants
* @{
*/
/** @defgroup DMA_Error_Code DMA Error Code
* @{
*/
#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */
#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
#define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */
#define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */
/**
* @}
*/
/** @defgroup DMA_request DMA request
* @{
*/
#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */
#define DMA_REQUEST_GENERATOR0 1U
#define DMA_REQUEST_GENERATOR1 2U
#define DMA_REQUEST_GENERATOR2 3U
#define DMA_REQUEST_GENERATOR3 4U
#define DMA_REQUEST_ADC1 5U
#define DMA_REQUEST_DAC1_CHANNEL1 6U
#define DMA_REQUEST_DAC1_CHANNEL2 7U
#define DMA_REQUEST_TIM6_UP 8U
#define DMA_REQUEST_TIM7_UP 9U
#define DMA_REQUEST_SPI1_RX 10U
#define DMA_REQUEST_SPI1_TX 11U
#define DMA_REQUEST_SPI2_RX 12U
#define DMA_REQUEST_SPI2_TX 13U
#define DMA_REQUEST_SPI3_RX 14U
#define DMA_REQUEST_SPI3_TX 15U
#define DMA_REQUEST_I2C1_RX 16U
#define DMA_REQUEST_I2C1_TX 17U
#define DMA_REQUEST_I2C2_RX 18U
#define DMA_REQUEST_I2C2_TX 19U
#define DMA_REQUEST_I2C3_RX 20U
#define DMA_REQUEST_I2C3_TX 21U
#if defined (I2C4)
#define DMA_REQUEST_I2C4_RX 22U
#define DMA_REQUEST_I2C4_TX 23U
#endif /* I2C4 */
#define DMA_REQUEST_USART1_RX 24U
#define DMA_REQUEST_USART1_TX 25U
#define DMA_REQUEST_USART2_RX 26U
#define DMA_REQUEST_USART2_TX 27U
#define DMA_REQUEST_USART3_RX 28U
#define DMA_REQUEST_USART3_TX 29U
#define DMA_REQUEST_UART4_RX 30U
#define DMA_REQUEST_UART4_TX 31U
#if defined (UART5)
#define DMA_REQUEST_UART5_RX 32U
#define DMA_REQUEST_UART5_TX 33U
#endif /* UART5 */
#define DMA_REQUEST_LPUART1_RX 34U
#define DMA_REQUEST_LPUART1_TX 35U
#define DMA_REQUEST_ADC2 36U
#if defined (ADC3)
#define DMA_REQUEST_ADC3 37U
#endif /* ADC3 */
#if defined (ADC4)
#define DMA_REQUEST_ADC4 38U
#endif /* ADC4 */
#if defined (ADC5)
#define DMA_REQUEST_ADC5 39U
#endif /* ADC5 */
#if defined (QUADSPI)
#define DMA_REQUEST_QUADSPI 40U
#endif /* QUADSPI */
#if defined (DAC2)
#define DMA_REQUEST_DAC2_CHANNEL1 41U
#endif /* DAC2 */
#define DMA_REQUEST_TIM1_CH1 42U
#define DMA_REQUEST_TIM1_CH2 43U
#define DMA_REQUEST_TIM1_CH3 44U
#define DMA_REQUEST_TIM1_CH4 45U
#define DMA_REQUEST_TIM1_UP 46U
#define DMA_REQUEST_TIM1_TRIG 47U
#define DMA_REQUEST_TIM1_COM 48U
#define DMA_REQUEST_TIM8_CH1 49U
#define DMA_REQUEST_TIM8_CH2 50U
#define DMA_REQUEST_TIM8_CH3 51U
#define DMA_REQUEST_TIM8_CH4 52U
#define DMA_REQUEST_TIM8_UP 53U
#define DMA_REQUEST_TIM8_TRIG 54U
#define DMA_REQUEST_TIM8_COM 55U
#define DMA_REQUEST_TIM2_CH1 56U
#define DMA_REQUEST_TIM2_CH2 57U
#define DMA_REQUEST_TIM2_CH3 58U
#define DMA_REQUEST_TIM2_CH4 59U
#define DMA_REQUEST_TIM2_UP 60U
#define DMA_REQUEST_TIM3_CH1 61U
#define DMA_REQUEST_TIM3_CH2 62U
#define DMA_REQUEST_TIM3_CH3 63U
#define DMA_REQUEST_TIM3_CH4 64U
#define DMA_REQUEST_TIM3_UP 65U
#define DMA_REQUEST_TIM3_TRIG 66U
#define DMA_REQUEST_TIM4_CH1 67U
#define DMA_REQUEST_TIM4_CH2 68U
#define DMA_REQUEST_TIM4_CH3 69U
#define DMA_REQUEST_TIM4_CH4 70U
#define DMA_REQUEST_TIM4_UP 71U
#if defined (TIM5)
#define DMA_REQUEST_TIM5_CH1 72U
#define DMA_REQUEST_TIM5_CH2 73U
#define DMA_REQUEST_TIM5_CH3 74U
#define DMA_REQUEST_TIM5_CH4 75U
#define DMA_REQUEST_TIM5_UP 76U
#define DMA_REQUEST_TIM5_TRIG 77U
#endif /* TIM5 */
#define DMA_REQUEST_TIM15_CH1 78U
#define DMA_REQUEST_TIM15_UP 79U
#define DMA_REQUEST_TIM15_TRIG 80U
#define DMA_REQUEST_TIM15_COM 81U
#define DMA_REQUEST_TIM16_CH1 82U
#define DMA_REQUEST_TIM16_UP 83U
#define DMA_REQUEST_TIM17_CH1 84U
#define DMA_REQUEST_TIM17_UP 85U
#if defined (TIM20)
#define DMA_REQUEST_TIM20_CH1 86U
#define DMA_REQUEST_TIM20_CH2 87U
#define DMA_REQUEST_TIM20_CH3 88U
#define DMA_REQUEST_TIM20_CH4 89U
#define DMA_REQUEST_TIM20_UP 90U
#endif /* TIM20 */
#define DMA_REQUEST_AES_IN 91U
#define DMA_REQUEST_AES_OUT 92U
#if defined (TIM20)
#define DMA_REQUEST_TIM20_TRIG 93U
#define DMA_REQUEST_TIM20_COM 94U
#endif /* TIM20 */
#if defined (HRTIM1)
#define DMA_REQUEST_HRTIM1_M 95U
#define DMA_REQUEST_HRTIM1_A 96U
#define DMA_REQUEST_HRTIM1_B 97U
#define DMA_REQUEST_HRTIM1_C 98U
#define DMA_REQUEST_HRTIM1_D 99U
#define DMA_REQUEST_HRTIM1_E 100U
#define DMA_REQUEST_HRTIM1_F 101U
#endif /* HRTIM1 */
#define DMA_REQUEST_DAC3_CHANNEL1 102U
#define DMA_REQUEST_DAC3_CHANNEL2 103U
#if defined (DAC4)
#define DMA_REQUEST_DAC4_CHANNEL1 104U
#define DMA_REQUEST_DAC4_CHANNEL2 105U
#endif /* DAC4 */
#if defined (SPI4)
#define DMA_REQUEST_SPI4_RX 106U
#define DMA_REQUEST_SPI4_TX 107U
#endif /* SPI4 */
#define DMA_REQUEST_SAI1_A 108U
#define DMA_REQUEST_SAI1_B 109U
#define DMA_REQUEST_FMAC_READ 110U
#define DMA_REQUEST_FMAC_WRITE 111U
#define DMA_REQUEST_CORDIC_READ 112U
#define DMA_REQUEST_CORDIC_WRITE 113U
#define DMA_REQUEST_UCPD1_RX 114U
#define DMA_REQUEST_UCPD1_TX 115U
/**
* @}
*/
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
* @{
*/
#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
/**
* @}
*/
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
* @{
*/
#define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */
#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */
/**
* @}
*/
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
* @{
*/
#define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */
#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */
/**
* @}
*/
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
* @{
*/
#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
#define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
#define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
/**
* @}
*/
/** @defgroup DMA_Memory_data_size DMA Memory data size
* @{
*/
#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
#define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
#define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
/**
* @}
*/
/** @defgroup DMA_mode DMA mode
* @{
*/
#define DMA_NORMAL 0x00000000U /*!< Normal mode */
#define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */
/**
* @}
*/
/** @defgroup DMA_Priority_level DMA Priority level
* @{
*/
#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
#define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
#define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
#define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */
/**
* @}
*/
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
* @{
*/
#define DMA_IT_TC DMA_CCR_TCIE
#define DMA_IT_HT DMA_CCR_HTIE
#define DMA_IT_TE DMA_CCR_TEIE
/**
* @}
*/
/** @defgroup DMA_flag_definitions DMA flag definitions
* @{
*/
#define DMA_FLAG_GL1 0x00000001U
#define DMA_FLAG_TC1 0x00000002U
#define DMA_FLAG_HT1 0x00000004U
#define DMA_FLAG_TE1 0x00000008U
#define DMA_FLAG_GL2 0x00000010U
#define DMA_FLAG_TC2 0x00000020U
#define DMA_FLAG_HT2 0x00000040U
#define DMA_FLAG_TE2 0x00000080U
#define DMA_FLAG_GL3 0x00000100U
#define DMA_FLAG_TC3 0x00000200U
#define DMA_FLAG_HT3 0x00000400U
#define DMA_FLAG_TE3 0x00000800U
#define DMA_FLAG_GL4 0x00001000U
#define DMA_FLAG_TC4 0x00002000U
#define DMA_FLAG_HT4 0x00004000U
#define DMA_FLAG_TE4 0x00008000U
#define DMA_FLAG_GL5 0x00010000U
#define DMA_FLAG_TC5 0x00020000U
#define DMA_FLAG_HT5 0x00040000U
#define DMA_FLAG_TE5 0x00080000U
#define DMA_FLAG_GL6 0x00100000U
#define DMA_FLAG_TC6 0x00200000U
#define DMA_FLAG_HT6 0x00400000U
#define DMA_FLAG_TE6 0x00800000U
#if defined (DMA1_Channel7)
#define DMA_FLAG_GL7 0x01000000U
#define DMA_FLAG_TC7 0x02000000U
#define DMA_FLAG_HT7 0x04000000U
#define DMA_FLAG_TE7 0x08000000U
#endif /* DMA1_Channel7 */
#if defined (DMA1_Channel8)
#define DMA_FLAG_GL8 0x10000000U
#define DMA_FLAG_TC8 0x20000000U
#define DMA_FLAG_HT8 0x40000000U
#define DMA_FLAG_TE8 0x80000000U
#endif /* DMA1_Channel8 */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup DMA_Exported_Macros DMA Exported Macros
* @{
*/
/** @brief Reset DMA handle state.
* @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
/**
* @brief Enable the specified DMA Channel.
* @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
/**
* @brief Disable the specified DMA Channel.
* @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
/* Interrupt & Flag management */
/**
* @brief Return the current DMA Channel transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index.
*/
#if defined (DMA1_Channel8)
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TC7 :\
DMA_FLAG_TC8)
#elif defined (DMA1_Channel6)
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
DMA_FLAG_TC6)
#endif /* DMA1_Channel8 */
/**
* @brief Return the current DMA Channel half transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index.
*/
#if defined (DMA1_Channel8)
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_HT7 :\
DMA_FLAG_HT8)
#elif defined (DMA1_Channel6)
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
DMA_FLAG_HT6)
#endif /* DMA1_Channel8 */
/**
* @brief Return the current DMA Channel transfer error flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#if defined (DMA1_Channel8)
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TE7 :\
DMA_FLAG_TE8)
#elif defined (DMA1_Channel6)
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
DMA_FLAG_TE6)
#endif /* DMA1_Channel8 */
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#if defined (DMA1_Channel8)
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_ISR_GIF7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_ISR_GIF7 :\
DMA_ISR_GIF8)
#elif defined (DMA1_Channel6)
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
DMA_ISR_GIF6)
#endif /* DMA1_Channel8 */
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx Transfer complete flag
* @arg DMA_FLAG_HTx Half transfer complete flag
* @arg DMA_FLAG_TEx Transfer error flag
* @arg DMA_FLAG_GLx Global interrupt flag
* Where x can be from 1 to 8 to select the DMA Channel x flag.
* @retval The state of FLAG (SET or RESET).
*/
#if defined (DMA1_Channel8)
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \
(DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
#elif defined (DMA1_Channel6)
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \
(DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
#endif /* DMA1_Channel8 */
/**
* @brief Clear the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx Transfer complete flag
* @arg DMA_FLAG_HTx Half transfer complete flag
* @arg DMA_FLAG_TEx Transfer error flag
* @arg DMA_FLAG_GLx Global interrupt flag
* Where x can be from 1 to 8 to select the DMA Channel x flag.
* @retval None
*/
#if defined (DMA1_Channel8)
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \
(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
#else
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \
(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
#endif /* DMA1_Channel8 */
/**
* @brief Enable the specified DMA Channel interrupts.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC Transfer complete interrupt mask
* @arg DMA_IT_HT Half transfer complete interrupt mask
* @arg DMA_IT_TE Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
/**
* @brief Disable the specified DMA Channel interrupts.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC Transfer complete interrupt mask
* @arg DMA_IT_HT Half transfer complete interrupt mask
* @arg DMA_IT_TE Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
/**
* @brief Check whether the specified DMA Channel interrupt is enabled or not.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA_IT_TC Transfer complete interrupt mask
* @arg DMA_IT_HT Half transfer complete interrupt mask
* @arg DMA_IT_TE Transfer error interrupt mask
* @retval The state of DMA_IT (SET or RESET).
*/
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
/**
* @brief Return the number of remaining data units in the current DMA Channel transfer.
* @param __HANDLE__ DMA handle
* @retval The number of remaining data units in the current DMA Channel transfer.
*/
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
/**
* @}
*/
/* Include DMA HAL Extension module */
#include "stm32g4xx_hal_dma_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA_Exported_Functions
* @{
*/
/** @addtogroup DMA_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/** @addtogroup DMA_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel,
uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
/**
* @}
*/
/** @addtogroup DMA_Exported_Functions_Group3
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMA_Private_Macros DMA Private Macros
* @{
*/
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x40000U))
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
((STATE) == DMA_PINC_DISABLE))
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
((STATE) == DMA_MINC_DISABLE))
#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_UCPD1_TX)
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
((SIZE) == DMA_PDATAALIGN_WORD))
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
((SIZE) == DMA_MDATAALIGN_WORD ))
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
((MODE) == DMA_CIRCULAR))
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
((PRIORITY) == DMA_PRIORITY_HIGH) || \
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32G4xx_HAL_DMA_H */

264
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h
View File

@ -1,264 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_dma_ex.h
* @author MCD Application Team
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32G4xx_HAL_DMA_EX_H
#define __STM32G4xx_HAL_DMA_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup DMAEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
* @{
*/
/**
* @brief HAL DMA Synchro definition
*/
/**
* @brief HAL DMAMUX Synchronization configuration structure definition
*/
typedef struct
{
uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */
uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */
FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled
This parameter can take the value ENABLE or DISABLE*/
FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached.
This parameter can take the value ENABLE or DISABLE */
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
} HAL_DMA_MuxSyncConfigTypeDef;
/**
* @brief HAL DMAMUX request generator parameters structure definition
*/
typedef struct
{
uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator
This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */
uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated.
This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
} HAL_DMA_MuxRequestGeneratorConfigTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
* @{
*/
/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection
* @{
*/
#define HAL_DMAMUX1_SYNC_EXTI0 0U /*!< Synchronization Signal is EXTI0 IT */
#define HAL_DMAMUX1_SYNC_EXTI1 1U /*!< Synchronization Signal is EXTI1 IT */
#define HAL_DMAMUX1_SYNC_EXTI2 2U /*!< Synchronization Signal is EXTI2 IT */
#define HAL_DMAMUX1_SYNC_EXTI3 3U /*!< Synchronization Signal is EXTI3 IT */
#define HAL_DMAMUX1_SYNC_EXTI4 4U /*!< Synchronization Signal is EXTI4 IT */
#define HAL_DMAMUX1_SYNC_EXTI5 5U /*!< Synchronization Signal is EXTI5 IT */
#define HAL_DMAMUX1_SYNC_EXTI6 6U /*!< Synchronization Signal is EXTI6 IT */
#define HAL_DMAMUX1_SYNC_EXTI7 7U /*!< Synchronization Signal is EXTI7 IT */
#define HAL_DMAMUX1_SYNC_EXTI8 8U /*!< Synchronization Signal is EXTI8 IT */
#define HAL_DMAMUX1_SYNC_EXTI9 9U /*!< Synchronization Signal is EXTI9 IT */
#define HAL_DMAMUX1_SYNC_EXTI10 10U /*!< Synchronization Signal is EXTI10 IT */
#define HAL_DMAMUX1_SYNC_EXTI11 11U /*!< Synchronization Signal is EXTI11 IT */
#define HAL_DMAMUX1_SYNC_EXTI12 12U /*!< Synchronization Signal is EXTI12 IT */
#define HAL_DMAMUX1_SYNC_EXTI13 13U /*!< Synchronization Signal is EXTI13 IT */
#define HAL_DMAMUX1_SYNC_EXTI14 14U /*!< Synchronization Signal is EXTI14 IT */
#define HAL_DMAMUX1_SYNC_EXTI15 15U /*!< Synchronization Signal is EXTI15 IT */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U /*!< Synchronization Signal is DMAMUX1 Channel0 Event */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U /*!< Synchronization Signal is DMAMUX1 Channel1 Event */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U /*!< Synchronization Signal is DMAMUX1 Channel2 Event */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U /*!< Synchronization Signal is DMAMUX1 Channel3 Event */
#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 20U /*!< Synchronization Signal is LPTIM1 OUT */
/**
* @}
*/
/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection
* @{
*/
#define HAL_DMAMUX_SYNC_NO_EVENT 0U /*!< block synchronization events */
#define HAL_DMAMUX_SYNC_RISING ((uint32_t)DMAMUX_CxCR_SPOL_0) /*!< synchronize with rising edge events */
#define HAL_DMAMUX_SYNC_FALLING ((uint32_t)DMAMUX_CxCR_SPOL_1) /*!< synchronize with falling edge events */
#define HAL_DMAMUX_SYNC_RISING_FALLING ((uint32_t)DMAMUX_CxCR_SPOL) /*!< synchronize with rising and falling edge events */
/**
* @}
*/
/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection
* @{
*/
#define HAL_DMAMUX1_REQ_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */
#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */
/**
* @}
*/
/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection
* @{
*/
#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< block request generator events */
#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */
#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */
#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMAEx_Exported_Functions
* @{
*/
/* IO operation functions *****************************************************/
/** @addtogroup DMAEx_Exported_Functions_Group1
* @{
*/
/* ------------------------- REQUEST -----------------------------------------*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
/* -------------------------------------------------------------------------- */
/* ------------------------- SYNCHRO -----------------------------------------*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
/* -------------------------------------------------------------------------- */
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
* @brief DMAEx private macros
* @{
*/
#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LPTIM1_OUT)
#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \
((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \
((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \
((EVENT) == ENABLE))
#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT)
#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \
((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32G4xx_HAL_DMA_EX_H */

315
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h
View File

@ -1,315 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_exti.h
* @author MCD Application Team
* @brief Header file of EXTI HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_EXTI_H
#define STM32G4xx_HAL_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @defgroup EXTI EXTI
* @brief EXTI HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Types EXTI Exported Types
* @{
*/
typedef enum
{
HAL_EXTI_COMMON_CB_ID = 0x00UL
} EXTI_CallbackIDTypeDef;
/**
* @brief EXTI Handle structure definition
*/
typedef struct
{
uint32_t Line; /*!< Exti line number */
void (* PendingCallback)(void); /*!< Exti pending callback */
} EXTI_HandleTypeDef;
/**
* @brief EXTI Configuration structure definition
*/
typedef struct
{
uint32_t Line; /*!< The Exti line to be configured. This parameter
can be a value of @ref EXTI_Line */
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
This parameter can be a combination of @ref EXTI_Mode */
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
can be a value of @ref EXTI_Trigger */
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
This parameter is only possible for line 0 to 15. It
can be a value of @ref EXTI_GPIOSel */
} EXTI_ConfigTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
* @{
*/
/** @defgroup EXTI_Line EXTI Line
* @{
*/
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u)
#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u)
#define EXTI_LINE_18 (EXTI_DIRECT | EXTI_REG1 | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)
#define EXTI_LINE_29 (EXTI_CONFIG | EXTI_REG1 | 0x1Du)
#define EXTI_LINE_30 (EXTI_CONFIG | EXTI_REG1 | 0x1Eu)
#define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu)
#define EXTI_LINE_32 (EXTI_CONFIG | EXTI_REG2 | 0x00u)
#define EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u)
#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | 0x02u)
#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u)
#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u)
#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | 0x06u)
#define EXTI_LINE_39 (EXTI_CONFIG | EXTI_REG2 | 0x07u)
#define EXTI_LINE_40 (EXTI_CONFIG | EXTI_REG2 | 0x08u)
#define EXTI_LINE_41 (EXTI_CONFIG | EXTI_REG2 | 0x09u)
#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au)
#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu)
/**
* @}
*/
/** @defgroup EXTI_Mode EXTI Mode
* @{
*/
#define EXTI_MODE_NONE 0x00000000U
#define EXTI_MODE_INTERRUPT 0x00000001U
#define EXTI_MODE_EVENT 0x00000002U
/**
* @}
*/
/** @defgroup EXTI_Trigger EXTI Trigger
* @{
*/
#define EXTI_TRIGGER_NONE 0x00000000U
#define EXTI_TRIGGER_RISING 0x00000001U
#define EXTI_TRIGGER_FALLING 0x00000002U
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @}
*/
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
* @brief
* @{
*/
#define EXTI_GPIOA 0x00000000U
#define EXTI_GPIOB 0x00000001U
#define EXTI_GPIOC 0x00000002U
#define EXTI_GPIOD 0x00000003U
#define EXTI_GPIOE 0x00000004U
#define EXTI_GPIOF 0x00000005U
#define EXTI_GPIOG 0x00000006U
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
* @{
*/
/**
* @}
*/
/* Private constants --------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
/**
* @brief EXTI Line property definition
*/
#define EXTI_PROPERTY_SHIFT 24U
#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
/**
* @brief EXTI Register and bit usage
*/
#define EXTI_REG_SHIFT 16U
#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
#define EXTI_PIN_MASK 0x0000001FU
/**
* @brief EXTI Mask for interrupt & event mode
*/
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
/**
* @brief EXTI Mask for trigger possibilities
*/
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @brief EXTI Line number
*/
#define EXTI_LINE_NB 44UL
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \
((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
(((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
(((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \
(((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U))
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG))
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
#define IS_EXTI_PENDING_EDGE(__EDGE__) (((__EDGE__) == EXTI_TRIGGER_RISING) || \
((__EDGE__) == EXTI_TRIGGER_FALLING)|| \
((__EDGE__) == EXTI_TRIGGER_RISING_FALLING))
#define IS_EXTI_CB(__CB__) ((__CB__) == HAL_EXTI_COMMON_CB_ID)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
* @brief EXTI Exported Functions
* @{
*/
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
* @brief Configuration functions
* @{
*/
/* Configuration functions ****************************************************/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_EXTI_H */

1429
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h
View File

File diff suppressed because it is too large Load Diff

1017
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h
View File

File diff suppressed because it is too large Load Diff

89
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h
View File

@ -1,89 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_flash_ex.h
* @author MCD Application Team
* @brief Header file of FLASH HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_FLASH_EX_H
#define STM32G4xx_HAL_FLASH_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup FLASHEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASHEx_Exported_Functions
* @{
*/
/* Extended Program operation functions *************************************/
/** @addtogroup FLASHEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank);
void HAL_FLASHEx_EnableDebugger(void);
void HAL_FLASHEx_DisableDebugger(void);
/**
* @}
*/
/**
* @}
*/
/** @addtogroup FLASHEx_Private_Functions
* @{
*/
void FLASH_PageErase(uint32_t Page, uint32_t Banks);
void FLASH_FlushCaches(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_FLASH_EX_H */

74
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h
View File

@ -1,74 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_flash_ramfunc.h
* @author MCD Application Team
* @brief Header file of FLASH RAMFUNC driver.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_FLASH_RAMFUNC_H
#define STM32G4xx_FLASH_RAMFUNC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup FLASH_RAMFUNC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASH_RAMFUNC_Exported_Functions
* @{
*/
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
* @{
*/
/* Peripheral Control functions ************************************************/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void);
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void);
#if defined (FLASH_OPTR_DBANK)
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig);
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_FLASH_RAMFUNC_H */

326
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h
View File

@ -1,326 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_gpio.h
* @author MCD Application Team
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_GPIO_H
#define STM32G4xx_HAL_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @defgroup GPIO GPIO
* @brief GPIO HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Types GPIO Exported Types
* @{
*/
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_mode */
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
This parameter can be a value of @ref GPIO_pull */
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed */
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
} GPIO_InitTypeDef;
/**
* @brief GPIO Bit SET and Bit RESET enumeration
*/
typedef enum
{
GPIO_PIN_RESET = 0U,
GPIO_PIN_SET
} GPIO_PinState;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_pins GPIO pins
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
/**
* @}
*/
/** @defgroup GPIO_mode GPIO mode
* @brief GPIO Configuration Mode
* Elements values convention: 0x00WX00YZ
* - W : EXTI trigger detection on 3 bits
* - X : EXTI mode (IT or Event) on 2 bits
* - Y : Output type (Push Pull or Open Drain) on 1 bit
* - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
* @{
*/
#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup GPIO_speed GPIO speed
* @brief GPIO Output Maximum frequency
* @{
*/
#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< range up to 5 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< range 5 MHz to 25 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< range 50 MHz to 120 MHz, please refer to the product datasheet */
/**
* @}
*/
/** @defgroup GPIO_pull GPIO pull
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */
#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
* @{
*/
/**
* @brief Check whether the specified EXTI line flag is set or not.
* @param __EXTI_LINE__ specifies the EXTI line flag to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
/**
* @brief Clear the EXTI's line pending flags.
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
/**
* @brief Check whether the specified EXTI line is asserted or not.
* @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
/**
* @brief Clear the EXTI's line pending bits.
* @param __EXTI_LINE__ specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
#define GPIO_MODE_Pos 0U
#define GPIO_MODE (0x3UL << GPIO_MODE_Pos)
#define MODE_INPUT (0x0UL << GPIO_MODE_Pos)
#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos)
#define MODE_AF (0x2UL << GPIO_MODE_Pos)
#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos)
#define OUTPUT_TYPE_Pos 4U
#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos)
#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos)
#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos)
#define EXTI_MODE_Pos 16U
#define EXTI_MODE (0x3UL << EXTI_MODE_Pos)
#define EXTI_IT (0x1UL << EXTI_MODE_Pos)
#define EXTI_EVT (0x2UL << EXTI_MODE_Pos)
#define TRIGGER_MODE_Pos 20U
#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos)
#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos)
#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos)
/**
* @}
*/
/** @defgroup GPIO_Private_Macros GPIO Private Macros
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
((__MODE__) == GPIO_MODE_AF_PP) ||\
((__MODE__) == GPIO_MODE_AF_OD) ||\
((__MODE__) == GPIO_MODE_IT_RISING) ||\
((__MODE__) == GPIO_MODE_IT_FALLING) ||\
((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
((__MODE__) == GPIO_MODE_EVT_RISING) ||\
((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
((__MODE__) == GPIO_MODE_ANALOG))
#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\
((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
((__PULL__) == GPIO_PULLUP) || \
((__PULL__) == GPIO_PULLDOWN))
/**
* @}
*/
/* Include GPIO HAL Extended module */
#include "stm32g4xx_hal_gpio_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
* @brief GPIO Exported Functions
* @{
*/
/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
/**
* @}
*/
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_GPIO_H */

340
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h
View File

@ -1,340 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_gpio_ex.h
* @author MCD Application Team
* @brief Header file of GPIO HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_GPIO_EX_H
#define STM32G4xx_HAL_GPIO_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @defgroup GPIOEx GPIOEx
* @brief GPIO Extended HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
* @{
*/
/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
* @{
*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#if defined(TIM5)
#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */
#endif /* TIM5 */
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
#define GPIO_AF1_TIM17_COMP1 ((uint8_t)0x01) /* TIM17/COMP1 Break in Alternate Function mapping */
#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
/**
* @brief AF 2 selection
*/
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#if defined(TIM5)
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#endif /* TIM5 */
#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
#define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */
#if defined(TIM20)
#define GPIO_AF2_TIM20 ((uint8_t)0x02) /* TIM20 Alternate Function mapping */
#endif /* TIM20 */
#define GPIO_AF2_TIM1_COMP1 ((uint8_t)0x02) /* TIM1/COMP1 Break in Alternate Function mapping */
#define GPIO_AF2_TIM15_COMP1 ((uint8_t)0x02) /* TIM15/COMP1 Break in Alternate Function mapping */
#define GPIO_AF2_TIM16_COMP1 ((uint8_t)0x02) /* TIM16/COMP1 Break in Alternate Function mapping */
#if defined(TIM20)
#define GPIO_AF2_TIM20_COMP1 ((uint8_t)0x02) /* TIM20/COMP1 Break in Alternate Function mapping */
#define GPIO_AF2_TIM20_COMP2 ((uint8_t)0x02) /* TIM20/COMP2 Break in Alternate Function mapping */
#endif /* TIM20 */
#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
#if defined(TIM20)
#define GPIO_AF3_TIM20 ((uint8_t)0x03) /* TIM20 Alternate Function mapping */
#endif /* TIM20 */
#define GPIO_AF3_UCPD1 ((uint8_t)0x03) /* UCPD1 Alternate Function mapping */
#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
#if defined(I2C4)
#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */
#endif /* I2C4 */
#if defined(HRTIM1)
#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM1 Alternate Function mapping */
#endif /* HRTIM1 */
#if defined(QUADSPI)
#define GPIO_AF3_QUADSPI ((uint8_t)0x03) /* QUADSPI Alternate Function mapping */
#endif /* QUADSPI */
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */
#define GPIO_AF3_COMP3 ((uint8_t)0x03) /* COMP3 Alternate Function mapping */
/**
* @brief AF 4 selection
*/
#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
#define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */
#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
#define GPIO_AF4_TIM8_COMP1 ((uint8_t)0x04) /* TIM8/COMP1 Break in Alternate Function mapping */
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#if defined(I2C4)
#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
#endif /* I2C4 */
/**
* @brief AF 5 selection
*/
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#if defined(SPI4)
#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
#endif /* SPI4 */
#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
#define GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */
#define GPIO_AF5_TIM8_COMP1 ((uint8_t)0x05) /* TIM8/COMP1 Break in Alternate Function mapping */
#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
#if defined(UART5)
#define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */
#endif /* UART5 */
#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext_SD Alternate Function mapping */
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
#if defined(TIM5)
#define GPIO_AF6_TIM5 ((uint8_t)0x06) /* TIM5 Alternate Function mapping */
#endif /* TIM5 */
#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
#if defined(TIM20)
#define GPIO_AF6_TIM20 ((uint8_t)0x06) /* TIM20 Alternate Function mapping */
#endif /* TIM20 */
#define GPIO_AF6_TIM1_COMP1 ((uint8_t)0x06) /* TIM1/COMP1 Break in Alternate Function mapping */
#define GPIO_AF6_TIM1_COMP2 ((uint8_t)0x06) /* TIM1/COMP2 Break in Alternate Function mapping */
#define GPIO_AF6_TIM8_COMP2 ((uint8_t)0x06) /* TIM8/COMP2 Break in Alternate Function mapping */
#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext_SD Alternate Function mapping */
/**
* @brief AF 7 selection
*/
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#if defined(COMP5)
#define GPIO_AF7_COMP5 ((uint8_t)0x07) /* COMP5 Alternate Function mapping */
#endif /* COMP5 */
#if defined(COMP6)
#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
#endif /* COMP6 */
#if defined(COMP7)
#define GPIO_AF7_COMP7 ((uint8_t)0x07) /* COMP7 Alternate Function mapping */
#endif /* COMP7 */
/**
* @brief AF 8 selection
*/
#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
#define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */
#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
#if defined(COMP5)
#define GPIO_AF8_COMP5 ((uint8_t)0x08) /* COMP5 Alternate Function mapping */
#endif /* COMP5 */
#if defined(COMP6)
#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
#endif /* COMP6 */
#if defined(COMP7)
#define GPIO_AF8_COMP7 ((uint8_t)0x08) /* COMP7 Alternate Function mapping */
#endif /* COMP7 */
#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
#if defined(I2C4)
#define GPIO_AF8_I2C4 ((uint8_t)0x08) /* I2C4 Alternate Function mapping */
#endif /* I2C4 */
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#if defined(UART5)
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#endif /* UART5 */
/**
* @brief AF 9 selection
*/
#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
#define GPIO_AF9_TIM1_COMP1 ((uint8_t)0x09) /* TIM1/COMP1 Break in Alternate Function mapping */
#define GPIO_AF9_TIM8_COMP1 ((uint8_t)0x09) /* TIM8/COMP1 Break in Alternate Function mapping */
#define GPIO_AF9_TIM15_COMP1 ((uint8_t)0x09) /* TIM15/COMP1 Break in Alternate Function mapping */
#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
#if defined(FDCAN2)
#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */
#endif /* FDCAN2 */
/**
* @brief AF 10 selection
*/
#define GPIO_AF10_TIM2 ((uint8_t)0x0A) /* TIM2 Alternate Function mapping */
#define GPIO_AF10_TIM3 ((uint8_t)0x0A) /* TIM3 Alternate Function mapping */
#define GPIO_AF10_TIM4 ((uint8_t)0x0A) /* TIM4 Alternate Function mapping */
#define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */
#define GPIO_AF10_TIM17 ((uint8_t)0x0A) /* TIM17 Alternate Function mapping */
#define GPIO_AF10_TIM8_COMP2 ((uint8_t)0x0A) /* TIM8/COMP2 Break in Alternate Function mapping */
#define GPIO_AF10_TIM17_COMP1 ((uint8_t)0x0A) /* TIM17/COMP1 Break in Alternate Function mapping */
#if defined(QUADSPI)
#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* OctoSPI Manager Port 1 Alternate Function mapping */
#endif /* QUADSPI */
/**
* @brief AF 11 selection
*/
#define GPIO_AF11_FDCAN1 ((uint8_t)0x0B) /* FDCAN1 Alternate Function mapping */
#if defined(FDCAN3)
#define GPIO_AF11_FDCAN3 ((uint8_t)0x0B) /* FDCAN3 Alternate Function mapping */
#endif /* FDCAN3 */
#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
#define GPIO_AF11_TIM8_COMP1 ((uint8_t)0x0B) /* TIM8/COMP1 Break in Alternate Function mapping */
#define GPIO_AF11_LPTIM1 ((uint8_t)0x0B) /* LPTIM1 Alternate Function mapping */
/**
* @brief AF 12 selection
*/
#define GPIO_AF12_LPUART1 ((uint8_t)0x0C) /* LPUART1 Alternate Function mapping */
#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */
#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */
#if defined(HRTIM1)
#define GPIO_AF12_HRTIM1 ((uint8_t)0x0C) /* HRTIM1 Alternate Function mapping */
#endif /* HRTIM1 */
#if defined(FMC_BANK1)
#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
#endif /* FMC_BANK1 */
#define GPIO_AF12_SAI1 ((uint8_t)0x0C) /* SAI1 Alternate Function mapping */
/**
* @brief AF 13 selection
*/
#if defined(HRTIM1)
#define GPIO_AF13_HRTIM1 ((uint8_t)0x0D) /* HRTIM1 Alternate Function mapping */
#endif /* HRTIM1 */
#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
/**
* @brief AF 14 selection
*/
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
#define GPIO_AF14_UCPD1 ((uint8_t)0x0E) /* UCPD1 Alternate Function mapping */
#define GPIO_AF14_SAI1 ((uint8_t)0x0E) /* SAI1 Alternate Function mapping */
#define GPIO_AF14_UART4 ((uint8_t)0x0E) /* UART4 Alternate Function mapping */
#if defined(UART5)
#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
#endif /* UART5 */
/**
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
* @{
*/
/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
* @{
*/
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\
((__GPIOx__) == (GPIOB))? 1UL :\
((__GPIOx__) == (GPIOC))? 2UL :\
((__GPIOx__) == (GPIOD))? 3UL :\
((__GPIOx__) == (GPIOE))? 4UL :\
((__GPIOx__) == (GPIOF))? 5UL : 6UL)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_GPIO_EX_H */

835
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h
View File

@ -1,835 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_i2c.h
* @author MCD Application Team
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_I2C_H
#define STM32G4xx_HAL_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Types I2C Exported Types
* @{
*/
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
* @brief I2C Configuration Structure definition
* @{
*/
typedef struct
{
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
This parameter calculated by referring to I2C initialization section
in Reference manual */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
mode is selected.
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
} I2C_InitTypeDef;
/**
* @}
*/
/** @defgroup HAL_state_structure_definition HAL state structure definition
* @brief HAL State structure definition
* @note HAL I2C State value coding follow below described bitmap :\n
* b7-b6 Error information\n
* 00 : No Error\n
* 01 : Abort (Abort user request on going)\n
* 10 : Timeout\n
* 11 : Error\n
* b5 Peripheral initialization status\n
* 0 : Reset (peripheral not initialized)\n
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
* b4 (not used)\n
* x : Should be set to 0\n
* b3\n
* 0 : Ready or Busy (No Listen mode ongoing)\n
* 1 : Listen (peripheral in Address Listen Mode)\n
* b2 Intrinsic process state\n
* 0 : Ready\n
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
* b1 Rx state\n
* 0 : Ready (no Rx operation ongoing)\n
* 1 : Busy (Rx operation ongoing)\n
* b0 Tx state\n
* 0 : Ready (no Tx operation ongoing)\n
* 1 : Busy (Tx operation ongoing)
* @{
*/
typedef enum
{
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
process is ongoing */
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
} HAL_I2C_StateTypeDef;
/**
* @}
*/
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
* @brief HAL Mode structure definition
* @note HAL I2C Mode value coding follow below described bitmap :\n
* b7 (not used)\n
* x : Should be set to 0\n
* b6\n
* 0 : None\n
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
* b5\n
* 0 : None\n
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
* b4\n
* 0 : None\n
* 1 : Master (HAL I2C communication is in Master Mode)\n
* b3-b2-b1-b0 (not used)\n
* xxxx : Should be set to 0000
* @{
*/
typedef enum
{
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
} HAL_I2C_ModeTypeDef;
/**
* @}
*/
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
* @brief I2C Error Code definition
* @{
*/
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/**
* @}
*/
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
* @brief I2C handle Structure definition
* @{
*/
typedef struct __I2C_HandleTypeDef
{
I2C_TypeDef *Instance; /*!< I2C registers base address */
I2C_InitTypeDef Init; /*!< I2C communication parameters */
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
uint16_t XferSize; /*!< I2C transfer size */
__IO uint16_t XferCount; /*!< I2C transfer counter */
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
be a value of @ref I2C_XFEROPTIONS */
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
/*!< I2C transfer IRQ handler function pointer */
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
__IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Master Tx Transfer completed callback */
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Master Rx Transfer completed callback */
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Slave Tx Transfer completed callback */
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Slave Rx Transfer completed callback */
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Listen Complete callback */
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Memory Tx Transfer completed callback */
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Memory Rx Transfer completed callback */
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Error callback */
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Abort callback */
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
/*!< I2C Slave Address Match callback */
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Msp Init callback */
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Msp DeInit callback */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
} I2C_HandleTypeDef;
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
/**
* @brief HAL I2C Callback ID enumeration definition
*/
typedef enum
{
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
} HAL_I2C_CallbackIDTypeDef;
/**
* @brief HAL I2C Callback pointer definition
*/
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
/*!< pointer to an I2C callback function */
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
uint16_t AddrMatchCode);
/*!< pointer to an I2C Address Match callback function */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_Exported_Constants I2C Exported Constants
* @{
*/
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
* @{
*/
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
/* List of XferOptions in usage of :
* 1- Restart condition in all use cases (direction change or not)
*/
#define I2C_OTHER_FRAME (0x000000AAU)
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
/**
* @}
*/
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
* @{
*/
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
* @{
*/
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
*/
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
* @{
*/
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
/**
* @}
*/
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
* @{
*/
#define I2C_GENERALCALL_DISABLE (0x00000000U)
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
*/
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
* @{
*/
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
* @{
*/
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
* @{
*/
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
#define I2C_DIRECTION_RECEIVE (0x00000001U)
/**
* @}
*/
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
* @{
*/
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE (0x00000000U)
/**
* @}
*/
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
* @{
*/
#define I2C_NO_STARTSTOP (0x00000000U)
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
* @brief I2C Interrupt definition
* Elements values convention: 0xXXXXXXXX
* - XXXXXXXX : Interrupt control mask
* @{
*/
#define I2C_IT_ERRI I2C_CR1_ERRIE
#define I2C_IT_TCI I2C_CR1_TCIE
#define I2C_IT_STOPI I2C_CR1_STOPIE
#define I2C_IT_NACKI I2C_CR1_NACKIE
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
#define I2C_IT_RXI I2C_CR1_RXIE
#define I2C_IT_TXI I2C_CR1_TXIE
/**
* @}
*/
/** @defgroup I2C_Flag_definition I2C Flag definition
* @{
*/
#define I2C_FLAG_TXE I2C_ISR_TXE
#define I2C_FLAG_TXIS I2C_ISR_TXIS
#define I2C_FLAG_RXNE I2C_ISR_RXNE
#define I2C_FLAG_ADDR I2C_ISR_ADDR
#define I2C_FLAG_AF I2C_ISR_NACKF
#define I2C_FLAG_STOPF I2C_ISR_STOPF
#define I2C_FLAG_TC I2C_ISR_TC
#define I2C_FLAG_TCR I2C_ISR_TCR
#define I2C_FLAG_BERR I2C_ISR_BERR
#define I2C_FLAG_ARLO I2C_ISR_ARLO
#define I2C_FLAG_OVR I2C_ISR_OVR
#define I2C_FLAG_PECERR I2C_ISR_PECERR
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define I2C_FLAG_ALERT I2C_ISR_ALERT
#define I2C_FLAG_BUSY I2C_ISR_BUSY
#define I2C_FLAG_DIR I2C_ISR_DIR
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2C_Exported_Macros I2C Exported Macros
* @{
*/
/** @brief Reset I2C handle state.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/** @brief Enable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
/** @brief Disable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
/** @brief Check whether the specified I2C interrupt source is enabled or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified I2C flag is set or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
* @arg @ref I2C_FLAG_TCR Transfer complete reload
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
* @arg @ref I2C_FLAG_BUSY Bus busy
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
*
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define I2C_FLAG_MASK (0x0001FFFFU)
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
*
* @retval None
*/
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Disable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
/**
* @}
*/
/* Include I2C HAL Extended module */
#include "stm32g4xx_hal_i2c_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2C_Exported_Functions
* @{
*/
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions******************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
pI2C_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
uint32_t Timeout);
/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
/**
* @}
*/
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
* @{
*/
/* Peripheral State, Mode and Error functions *********************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_Private_Constants I2C Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2C_Private_Macro I2C Private Macros
* @{
*/
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
((MODE) == I2C_ADDRESSINGMODE_10BIT))
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
((MASK) == I2C_OA2_MASK01) || \
((MASK) == I2C_OA2_MASK02) || \
((MASK) == I2C_OA2_MASK03) || \
((MASK) == I2C_OA2_MASK04) || \
((MASK) == I2C_OA2_MASK05) || \
((MASK) == I2C_OA2_MASK06) || \
((MASK) == I2C_OA2_MASK07))
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
((CALL) == I2C_GENERALCALL_ENABLE))
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
((STRETCH) == I2C_NOSTRETCH_ENABLE))
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
((MODE) == I2C_AUTOEND_MODE) || \
((MODE) == I2C_SOFTEND_MODE))
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
((REQUEST) == I2C_GENERATE_START_READ) || \
((REQUEST) == I2C_GENERATE_START_WRITE) || \
((REQUEST) == I2C_NO_STARTSTOP))
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
I2C_CR2_RD_WRN)))
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
>> 16U))
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
>> 16U))
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
(uint16_t)(0xFF00U))) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
(~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_ADD10) | (I2C_CR2_START)) & \
(~I2C_CR2_RD_WRN)))
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2C_Private_Functions I2C Private Functions
* @{
*/
/* Private functions are defined in stm32g4xx_hal_i2c.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_I2C_H */

175
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h
View File

@ -1,175 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_i2c_ex.h
* @author MCD Application Team
* @brief Header file of I2C HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_I2C_EX_H
#define STM32G4xx_HAL_I2C_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup I2CEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
* @{
*/
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
* @{
*/
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
*/
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
* @{
*/
#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
#if defined(SYSCFG_CFGR1_I2C4_FMP)
#define I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
#else
#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */
#endif /* SYSCFG_CFGR1_I2C4_FMP */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
* @{
*/
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
/**
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
* @{
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @{
*/
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
* @{
*/
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
((FILTER) == I2C_ANALOGFILTER_DISABLE))
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4)))
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
* @{
*/
/* Private functions are defined in stm32g4xx_hal_i2c_ex.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_I2C_EX_H */

411
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h
View File

@ -1,411 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_pwr.h
* @author MCD Application Team
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_PWR_H
#define STM32G4xx_HAL_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup PWR
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Types PWR Exported Types
* @{
*/
/**
* @brief PWR PVD configuration structure definition
*/
typedef struct
{
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
This parameter can be a value of @ref PWR_PVD_detection_level. */
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWR_PVD_Mode. */
}PWR_PVDTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_Exported_Constants PWR Exported Constants
* @{
*/
/** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels
* @{
*/
#define PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0 /*!< PVD threshold around 2.0 V */
#define PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1 /*!< PVD threshold around 2.2 V */
#define PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2 /*!< PVD threshold around 2.4 V */
#define PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3 /*!< PVD threshold around 2.5 V */
#define PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4 /*!< PVD threshold around 2.6 V */
#define PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5 /*!< PVD threshold around 2.8 V */
#define PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6 /*!< PVD threshold around 2.9 V */
#define PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7 /*!< External input analog voltage (compared internally to VREFINT) */
/**
* @}
*/
/** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode
* @{
*/
#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */
#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode
* @{
*/
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) /*!< Regulator in main mode */
#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR /*!< Regulator in low-power mode */
/**
* @}
*/
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
* @{
*/
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode */
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */
/**
* @}
*/
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
* @{
*/
#define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */
#define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */
/**
* @}
*/
/** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line
* @{
*/
#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
/**
* @}
*/
/** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line
* @{
*/
#define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000) /*!< Event line 16 Connected to the PVD Event Line */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PWR_Exported_Macros PWR Exported Macros
* @{
*/
/** @brief Check whether or not a specific PWR flag is set.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
* was received from the WKUP pin 1.
* @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
* was received from the WKUP pin 2.
* @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
* was received from the WKUP pin 3.
* @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
* was received from the WKUP pin 4.
* @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
* was received from the WKUP pin 5.
* @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system
* entered StandBy mode.
* @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on
* the internal wakeup line.
* @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the
* low-power regulator is ready.
* @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the
* regulator is ready in main mode or is in low-power mode.
* @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready
* in the selected voltage range or is still changing to the required voltage level.
* @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is
* below or above the selected PVD threshold.
@if PWR_CR2_PVME1
* @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is
* is below or above PVM1 threshold (applicable when USB feature is supported).
@endif
@if PWR_CR2_PVME2
* @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is
* is below or above PVM2 threshold (applicable when VDDIO2 is present on device).
@endif
* @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
* is below or above PVM3 threshold.
* @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is
* is below or above PVM4 threshold.
*
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1) ?\
(PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
(PWR->SR2 & (1U << ((__FLAG__) & 31U))) )
/** @brief Clear a specific PWR flag.
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
* was received from the WKUP pin 1.
* @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
* was received from the WKUP pin 2.
* @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
* was received from the WKUP pin 3.
* @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
* was received from the WKUP pin 4.
* @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
* was received from the WKUP pin 5.
* @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.
* @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system
* entered Standby mode.
* @retval None
*/
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
(PWR->SCR = (__FLAG__)) :\
(PWR->SCR = (1U << ((__FLAG__) & 31U))) )
/**
* @brief Enable the PVD Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Event Line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
/**
* @brief Disable the PVD Event Line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
/**
* @brief Check whether or not the PVD EXTI interrupt flag is set.
* @retval EXTI PVD Line Status.
*/
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD)
/**
* @brief Clear the PVD EXTI interrupt flag.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @addtogroup PWR_Private_Macros PWR Private Macros
* @{
*/
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\
((MODE) == PWR_PVD_MODE_IT_RISING) ||\
((MODE) == PWR_PVD_MODE_IT_FALLING) ||\
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\
((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\
((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\
((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
/**
* @}
*/
/* Include PWR HAL Extended module */
#include "stm32g4xx_hal_pwr_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *******************************/
void HAL_PWR_DeInit(void);
void HAL_PWR_EnableBkUpAccess(void);
void HAL_PWR_DisableBkUpAccess(void);
/**
* @}
*/
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
void HAL_PWR_EnablePVD(void);
void HAL_PWR_DisablePVD(void);
/* WakeUp pins configuration functions ****************************************/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
/* Low Power modes configuration functions ************************************/
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
void HAL_PWR_EnterSTANDBYMode(void);
void HAL_PWR_EnableSleepOnExit(void);
void HAL_PWR_DisableSleepOnExit(void);
void HAL_PWR_EnableSEVOnPend(void);
void HAL_PWR_DisableSEVOnPend(void);
void HAL_PWR_PVDCallback(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_PWR_H */

817
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h
View File

@ -1,817 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_pwr_ex.h
* @author MCD Application Team
* @brief Header file of PWR HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_PWR_EX_H
#define STM32G4xx_HAL_PWR_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup PWREx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
* @{
*/
/**
* @brief PWR PVM configuration structure definition
*/
typedef struct
{
uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold.
This parameter can be a value of @ref PWREx_PVM_Type. */
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWREx_PVM_Mode. */
}PWR_PVMTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
* @{
*/
/** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
* @{
*/
#define PWR_WUP_POLARITY_SHIFT 0x05U /*!< Internal constant used to retrieve wakeup pin polariry */
/**
* @}
*/
/** @defgroup PWREx_WakeUp_Pins PWR wake-up pins
* @{
*/
#define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
#define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
#define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
#define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
#define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
#define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
#define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
#define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
#define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
/**
* @}
*/
/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
* @{
*/
#if defined(PWR_CR2_PVME1)
#define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
#define PWR_PVM_2 PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */
#endif /* PWR_CR2_PVME2 */
#define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
#define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V */
/**
* @}
*/
/** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode
* @{
*/
#define PWR_PVM_MODE_NORMAL 0x00000000U /*!< basic mode is used */
#define PWR_PVM_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVM_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVM_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVM_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVM_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVM_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale
* @{
*/
#if defined(PWR_CR5_R1MODE)
#define PWR_REGULATOR_VOLTAGE_SCALE1_BOOST ((uint32_t)0x00000000) /*!< Voltage scaling range 1 boost mode */
#endif /*PWR_CR5_R1MODE */
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 normal mode */
#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */
/**
* @}
*/
/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
* @{
*/
#define PWR_BATTERY_CHARGING_RESISTOR_5 0x00000000U /*!< VBAT charging through a 5 kOhms resistor */
#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
/**
* @}
*/
/** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
* @{
*/
#define PWR_BATTERY_CHARGING_DISABLE 0x00000000U
#define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE
/**
* @}
*/
/** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
* @{
*/
#define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /*!< GPIO port I/O pin 0 */
#define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /*!< GPIO port I/O pin 1 */
#define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /*!< GPIO port I/O pin 2 */
#define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /*!< GPIO port I/O pin 3 */
#define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /*!< GPIO port I/O pin 4 */
#define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /*!< GPIO port I/O pin 5 */
#define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /*!< GPIO port I/O pin 6 */
#define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /*!< GPIO port I/O pin 7 */
#define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /*!< GPIO port I/O pin 8 */
#define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /*!< GPIO port I/O pin 9 */
#define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /*!< GPIO port I/O pin 10 */
#define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /*!< GPIO port I/O pin 11 */
#define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /*!< GPIO port I/O pin 12 */
#define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /*!< GPIO port I/O pin 13 */
#define PWR_GPIO_BIT_14 PWR_PDCRA_PA14 /*!< GPIO port I/O pin 14 */
#define PWR_GPIO_BIT_15 PWR_PUCRA_PA15 /*!< GPIO port I/O pin 15 */
/**
* @}
*/
/** @defgroup PWREx_GPIO GPIO port
* @{
*/
#define PWR_GPIO_A 0x00000000U /*!< GPIO port A */
#define PWR_GPIO_B 0x00000001U /*!< GPIO port B */
#define PWR_GPIO_C 0x00000002U /*!< GPIO port C */
#define PWR_GPIO_D 0x00000003U /*!< GPIO port D */
#define PWR_GPIO_E 0x00000004U /*!< GPIO port E */
#define PWR_GPIO_F 0x00000005U /*!< GPIO port F */
#define PWR_GPIO_G 0x00000006U /*!< GPIO port G */
/**
* @}
*/
/** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
* @{
*/
#if defined(PWR_CR2_PVME1)
#define PWR_EXTI_LINE_PVM1 0x00000008U /*!< External interrupt line 35 Connected to the PVM1 EXTI Line */
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
#define PWR_EXTI_LINE_PVM2 0x00000010U /*!< External interrupt line 36 Connected to the PVM2 EXTI Line */
#endif /* PWR_CR2_PVME2 */
#define PWR_EXTI_LINE_PVM3 0x00000020U /*!< External interrupt line 37 Connected to the PVM3 EXTI Line */
#define PWR_EXTI_LINE_PVM4 0x00000040U /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */
/**
* @}
*/
/** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines
* @{
*/
#if defined(PWR_CR2_PVME1)
#define PWR_EVENT_LINE_PVM1 0x00000008U /*!< Event line 35 Connected to the PVM1 EXTI Line */
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
#define PWR_EVENT_LINE_PVM2 0x00000010U /*!< Event line 36 Connected to the PVM2 EXTI Line */
#endif /* PWR_CR2_PVME2 */
#define PWR_EVENT_LINE_PVM3 0x00000020U /*!< Event line 37 Connected to the PVM3 EXTI Line */
#define PWR_EVENT_LINE_PVM4 0x00000040U /*!< Event line 38 Connected to the PVM4 EXTI Line */
/**
* @}
*/
/** @defgroup PWREx_Flag PWR Status Flags
* Elements values convention: 0000 0000 0XXY YYYYb
* - Y YYYY : Flag position in the XX register (5 bits)
* - XX : Status register (2 bits)
* - 01: SR1 register
* - 10: SR2 register
* The only exception is PWR_FLAG_WU, encompassing all
* wake-up flags and set to PWR_SR1_WUF.
* @{
*/
#define PWR_FLAG_WUF1 0x0020U /*!< Wakeup event on wakeup pin 1 */
#define PWR_FLAG_WUF2 0x0021U /*!< Wakeup event on wakeup pin 2 */
#define PWR_FLAG_WUF3 0x0022U /*!< Wakeup event on wakeup pin 3 */
#define PWR_FLAG_WUF4 0x0023U /*!< Wakeup event on wakeup pin 4 */
#define PWR_FLAG_WUF5 0x0024U /*!< Wakeup event on wakeup pin 5 */
#define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */
#define PWR_FLAG_SB 0x0028U /*!< Standby flag */
#define PWR_FLAG_WUFI 0x002FU /*!< Wakeup on internal wakeup line */
#define PWR_FLAG_REGLPS 0x0048U /*!< Low-power regulator start flag */
#define PWR_FLAG_REGLPF 0x0049U /*!< Low-power regulator flag */
#define PWR_FLAG_VOSF 0x004AU /*!< Voltage scaling flag */
#define PWR_FLAG_PVDO 0x004BU /*!< Power Voltage Detector output flag */
#if defined(PWR_CR2_PVME1)
#define PWR_FLAG_PVMO1 0x004CU /*!< Power Voltage Monitoring 1 output flag */
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
#define PWR_FLAG_PVMO2 0x004DU /*!< Power Voltage Monitoring 2 output flag */
#endif /* PWR_CR2_PVME2 */
#define PWR_FLAG_PVMO3 0x004EU /*!< Power Voltage Monitoring 3 output flag */
#define PWR_FLAG_PVMO4 0x004FU /*!< Power Voltage Monitoring 4 output flag */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
* @{
*/
#if defined(PWR_CR2_PVME1)
/**
* @brief Enable the PVM1 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
/**
* @brief Disable the PVM1 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
/**
* @brief Enable the PVM1 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
/**
* @brief Disable the PVM1 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
/**
* @brief Enable the PVM1 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
/**
* @brief Disable the PVM1 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
/**
* @brief Enable the PVM1 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
/**
* @brief Disable the PVM1 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
/**
* @brief PVM1 EXTI line configuration: set rising & falling edge trigger.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
/**
* @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
* @retval EXTI PVM1 Line Status.
*/
#define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
/**
* @brief Clear the PVM1 EXTI flag.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
/**
* @brief Enable the PVM2 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
/**
* @brief Disable the PVM2 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
/**
* @brief Enable the PVM2 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
/**
* @brief Disable the PVM2 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
/**
* @brief Enable the PVM2 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
/**
* @brief Disable the PVM2 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
/**
* @brief Enable the PVM2 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
/**
* @brief Disable the PVM2 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
/**
* @brief PVM2 EXTI line configuration: set rising & falling edge trigger.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
/**
* @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.
* @retval EXTI PVM2 Line Status.
*/
#define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
/**
* @brief Clear the PVM2 EXTI flag.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
#endif /* PWR_CR2_PVME2 */
/**
* @brief Enable the PVM3 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
/**
* @brief Disable the PVM3 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
/**
* @brief Enable the PVM3 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
/**
* @brief Disable the PVM3 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
/**
* @brief Enable the PVM3 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
/**
* @brief Disable the PVM3 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
/**
* @brief Enable the PVM3 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
/**
* @brief Disable the PVM3 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
/**
* @brief PVM3 EXTI line configuration: set rising & falling edge trigger.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
/**
* @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
* @retval EXTI PVM3 Line Status.
*/
#define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
/**
* @brief Clear the PVM3 EXTI flag.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
/**
* @brief Enable the PVM4 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
/**
* @brief Disable the PVM4 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
/**
* @brief Enable the PVM4 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
/**
* @brief Disable the PVM4 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
/**
* @brief Enable the PVM4 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
/**
* @brief Disable the PVM4 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
/**
* @brief Enable the PVM4 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
/**
* @brief Disable the PVM4 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
/**
* @brief PVM4 EXTI line configuration: set rising & falling edge trigger.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
/**
* @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.
* @retval EXTI PVM4 Line Status.
*/
#define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
/**
* @brief Clear the PVM4 EXTI flag.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
/**
* @brief Configure the main internal regulator output voltage.
* @param __REGULATOR__: specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption.
* This parameter can be one of the following values:
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST Regulator voltage output range 1 mode,
* typical output voltage at 1.28 V,
* system frequency up to 170 MHz.
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
* typical output voltage at 1.2 V,
* system frequency up to 150 MHz.
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
* typical output voltage at 1.0 V,
* system frequency up to 26 MHz.
* @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
* whether or not VOSF flag is cleared when moving from range 2 to range 1. User
* may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
* @retval None
*/
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
__IO uint32_t tmpreg; \
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
UNUSED(tmpreg); \
} while(0)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
* @{
*/
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
((PIN) == PWR_WAKEUP_PIN2) || \
((PIN) == PWR_WAKEUP_PIN3) || \
((PIN) == PWR_WAKEUP_PIN4) || \
((PIN) == PWR_WAKEUP_PIN5) || \
((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
((PIN) == PWR_WAKEUP_PIN1_LOW) || \
((PIN) == PWR_WAKEUP_PIN2_LOW) || \
((PIN) == PWR_WAKEUP_PIN3_LOW) || \
((PIN) == PWR_WAKEUP_PIN4_LOW) || \
((PIN) == PWR_WAKEUP_PIN5_LOW))
#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
((TYPE) == PWR_PVM_2) ||\
((TYPE) == PWR_PVM_3) ||\
((TYPE) == PWR_PVM_4))
#define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\
((MODE) == PWR_PVM_MODE_IT_RISING) ||\
((MODE) == PWR_PVM_MODE_IT_FALLING) ||\
((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\
((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\
((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\
((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
#if defined(PWR_CR5_R1MODE)
#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
#else
#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
#endif
#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
#define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00U)
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
((GPIO) == PWR_GPIO_B) ||\
((GPIO) == PWR_GPIO_C) ||\
((GPIO) == PWR_GPIO_D) ||\
((GPIO) == PWR_GPIO_E) ||\
((GPIO) == PWR_GPIO_F) ||\
((GPIO) == PWR_GPIO_G))
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
* @{
*/
/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
* @{
*/
/* Peripheral Control functions **********************************************/
uint32_t HAL_PWREx_GetVoltageRange(void);
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
void HAL_PWREx_DisableBatteryCharging(void);
void HAL_PWREx_EnableInternalWakeUpLine(void);
void HAL_PWREx_DisableInternalWakeUpLine(void);
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
void HAL_PWREx_EnablePullUpPullDownConfig(void);
void HAL_PWREx_DisablePullUpPullDownConfig(void);
void HAL_PWREx_EnableSRAM2ContentRetention(void);
void HAL_PWREx_DisableSRAM2ContentRetention(void);
#if defined(PWR_CR2_PVME1)
void HAL_PWREx_EnablePVM1(void);
void HAL_PWREx_DisablePVM1(void);
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
void HAL_PWREx_EnablePVM2(void);
void HAL_PWREx_DisablePVM2(void);
#endif /* PWR_CR2_PVME2 */
void HAL_PWREx_EnablePVM3(void);
void HAL_PWREx_DisablePVM3(void);
void HAL_PWREx_EnablePVM4(void);
void HAL_PWREx_DisablePVM4(void);
HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
/* Low Power modes configuration functions ************************************/
void HAL_PWREx_EnableLowPowerRunMode(void);
HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
void HAL_PWREx_EnterSHUTDOWNMode(void);
void HAL_PWREx_PVD_PVM_IRQHandler(void);
#if defined(PWR_CR2_PVME1)
void HAL_PWREx_PVM1Callback(void);
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
void HAL_PWREx_PVM2Callback(void);
#endif /* PWR_CR2_PVME2 */
void HAL_PWREx_PVM3Callback(void);
void HAL_PWREx_PVM4Callback(void);
#if defined(PWR_CR3_UCPD_STDBY)
void HAL_PWREx_EnableUCPDStandbyMode(void);
void HAL_PWREx_DisableUCPDStandbyMode(void);
#endif /* PWR_CR3_UCPD_STDBY */
#if defined(PWR_CR3_UCPD_DBDIS)
void HAL_PWREx_EnableUCPDDeadBattery(void);
void HAL_PWREx_DisableUCPDDeadBattery(void);
#endif /* PWR_CR3_UCPD_DBDIS */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_PWR_EX_H */

3406
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h
View File

File diff suppressed because it is too large Load Diff

1606
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h
View File

File diff suppressed because it is too large Load Diff

2631
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h
View File

File diff suppressed because it is too large Load Diff

2138
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h
View File

File diff suppressed because it is too large Load Diff

8183
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h
View File

File diff suppressed because it is too large Load Diff

1680
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h
View File

File diff suppressed because it is too large Load Diff

637
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h
View File

@ -1,637 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_ll_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL CORTEX driver contains a set of generic APIs that can be
used by user:
(+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
functions
(+) Low power mode configuration (SCB register of Cortex-MCU)
(+) MPU API to configure and enable regions
(+) API to access to MCU info (CPUID register)
(+) API to enable fault handler (SHCSR accesses)
@endverbatim
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32G4xx_LL_CORTEX_H
#define __STM32G4xx_LL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
/** @defgroup CORTEX_LL CORTEX
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
* @{
*/
/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
* @{
*/
#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
* @{
*/
#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
/**
* @}
*/
#if __MPU_PRESENT
/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
* @{
*/
#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
* @{
*/
#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
* @{
*/
#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
* @{
*/
#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
* @{
*/
#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
* @{
*/
#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
* @{
*/
#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
* @{
*/
#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
* @{
*/
#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
* @{
*/
/**
* @brief This function checks if the Systick counter flag is active or not.
* @note It can be used in timeout function on application side.
* @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
{
return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
}
/**
* @brief Configures the SysTick clock source
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
{
if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
{
SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
else
{
CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
}
/**
* @brief Get the SysTick clock source
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
*/
__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
{
return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
/**
* @brief Enable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
{
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Disable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
{
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Checks if the SYSTICK interrupt is enabled or disabled.
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
{
return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
* @{
*/
/**
* @brief Processor uses sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleep(void)
{
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Processor uses deep sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
{
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
* @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
* empty main application.
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
{
/* Set SLEEPONEXIT bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Do not sleep when returning to Thread mode.
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
* @retval None
*/
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
{
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
* processor.
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
{
/* Set SEVEONPEND bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
* excluded
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
* @retval None
*/
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
{
/* Clear SEVEONPEND bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
* @{
*/
/**
* @brief Enable a fault in System handler control register (SHCSR)
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
* @param Fault This parameter can be a combination of the following values:
* @arg @ref LL_HANDLER_FAULT_USG
* @arg @ref LL_HANDLER_FAULT_BUS
* @arg @ref LL_HANDLER_FAULT_MEM
* @retval None
*/
__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
{
/* Enable the system handler fault */
SET_BIT(SCB->SHCSR, Fault);
}
/**
* @brief Disable a fault in System handler control register (SHCSR)
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
* @param Fault This parameter can be a combination of the following values:
* @arg @ref LL_HANDLER_FAULT_USG
* @arg @ref LL_HANDLER_FAULT_BUS
* @arg @ref LL_HANDLER_FAULT_MEM
* @retval None
*/
__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
{
/* Disable the system handler fault */
CLEAR_BIT(SCB->SHCSR, Fault);
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
* @{
*/
/**
* @brief Get Implementer code
* @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
* @retval Value should be equal to 0x41 for ARM
*/
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
}
/**
* @brief Get Variant number (The r value in the rnpn product revision identifier)
* @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
* @retval Value between 0 and 255 (0x0: revision 0)
*/
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
}
/**
* @brief Get Architecture number
* @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
* @retval Value should be equal to 0xF for Cortex-M4 devices
*/
__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
}
/**
* @brief Get Part number
* @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
* @retval Value should be equal to 0xC24 for Cortex-M4
*/
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
}
/**
* @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
* @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
* @retval Value between 0 and 255 (0x1: patch 1)
*/
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
}
/**
* @}
*/
#if __MPU_PRESENT
/** @defgroup CORTEX_LL_EF_MPU MPU
* @{
*/
/**
* @brief Enable MPU with input options
* @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
* @param Options This parameter can be one of the following values:
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
* @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
* @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
* @retval None
*/
__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
{
/* Enable the MPU*/
WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
/* Ensure MPU settings take effects */
__DSB();
/* Sequence instruction fetches using update settings */
__ISB();
}
/**
* @brief Disable MPU
* @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
* @retval None
*/
__STATIC_INLINE void LL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable MPU*/
WRITE_REG(MPU->CTRL, 0U);
}
/**
* @brief Check if MPU is enabled or not
* @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
{
return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
}
/**
* @brief Enable a MPU region
* @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Enable the MPU region */
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Configure and enable a region
* @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
* MPU_RBAR REGION LL_MPU_ConfigRegion\n
* MPU_RBAR ADDR LL_MPU_ConfigRegion\n
* MPU_RASR XN LL_MPU_ConfigRegion\n
* MPU_RASR AP LL_MPU_ConfigRegion\n
* MPU_RASR S LL_MPU_ConfigRegion\n
* MPU_RASR C LL_MPU_ConfigRegion\n
* MPU_RASR B LL_MPU_ConfigRegion\n
* MPU_RASR SIZE LL_MPU_ConfigRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @param Address Value of region base address
* @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
* @param Attributes This parameter can be a combination of the following values:
* @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
* or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
* or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
* or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
* or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
* or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
* @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
* or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
* @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
* @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
* @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
* @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
* @retval None
*/
__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Set base address */
WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
/* Configure MPU */
WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
}
/**
* @brief Disable a region
* @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
* MPU_RASR ENABLE LL_MPU_DisableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Disable the MPU region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32G4xx_LL_CORTEX_H */

781
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h
View File

@ -1,781 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_ll_crs.h
* @author MCD Application Team
* @brief Header file of CRS LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2018 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32G4xx_LL_CRS_H
#define __STM32G4xx_LL_CRS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined(CRS)
/** @defgroup CRS_LL CRS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
* @{
*/
/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_CRS_ReadReg function
* @{
*/
#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
#define LL_CRS_ISR_ERRF CRS_ISR_ERRF
#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
/**
* @}
*/
/** @defgroup CRS_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
* @{
*/
#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
#define LL_CRS_CR_ERRIE CRS_CR_ERRIE
#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
* @{
*/
#define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
* @{
*/
#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal source GPIO */
#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
* @{
*/
#define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
/**
* @}
*/
/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
* @{
*/
#define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */
#define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
/**
* @}
*/
/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
* @{
*/
/**
* @brief Reset value of the RELOAD field
* @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
* and a synchronization signal frequency of 1 kHz (SOF signal from USB)
*/
#define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
/**
* @brief Reset value of Frequency error limit.
*/
#define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
/**
* @brief Reset value of the HSI48 Calibration field
* @note The default value is 64, which corresponds to the middle of the trimming interval.
* The trimming step is specified in the product datasheet.
* A higher TRIM value corresponds to a higher output frequency
*/
#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x40U)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
* @{
*/
/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in CRS register
* @param __INSTANCE__ CRS Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in CRS register
* @param __INSTANCE__ CRS Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
* @{
*/
/**
* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
* @note The RELOAD value should be selected according to the ratio between
* the target frequency and the frequency of the synchronization source after
* prescaling. It is then decreased by one in order to reach the expected
* synchronization on the zero value. The formula is the following:
* RELOAD = (fTARGET / fSYNC) -1
* @param __FTARGET__ Target frequency (value in Hz)
* @param __FSYNC__ Synchronization signal frequency (value in Hz)
* @retval Reload value (in Hz)
*/
#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
* @{
*/
/** @defgroup CRS_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable Frequency error counter
* @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
* @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
{
SET_BIT(CRS->CR, CRS_CR_CEN);
}
/**
* @brief Disable Frequency error counter
* @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_CEN);
}
/**
* @brief Check if Frequency error counter is enabled or not
* @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
}
/**
* @brief Enable Automatic trimming counter
* @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
{
SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
}
/**
* @brief Disable Automatic trimming counter
* @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
}
/**
* @brief Check if Automatic trimming is enabled or not
* @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
}
/**
* @brief Set HSI48 oscillator smooth trimming
* @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
* @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
* @param Value a number between Min_Data = 0 and Max_Data = 63
* @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
{
MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
}
/**
* @brief Get HSI48 oscillator smooth trimming
* @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
* @retval a number between Min_Data = 0 and Max_Data = 63
*/
__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
{
return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
}
/**
* @brief Set counter reload value
* @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
* @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
* @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
* Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
}
/**
* @brief Get counter reload value
* @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
* @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
*/
__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
}
/**
* @brief Set frequency error limit
* @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
* @param Value a number between Min_Data = 0 and Max_Data = 255
* @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
}
/**
* @brief Get frequency error limit
* @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
* @retval A number between Min_Data = 0 and Max_Data = 255
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
}
/**
* @brief Set division factor for SYNC signal
* @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
* @param Divider This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1
* @arg @ref LL_CRS_SYNC_DIV_2
* @arg @ref LL_CRS_SYNC_DIV_4
* @arg @ref LL_CRS_SYNC_DIV_8
* @arg @ref LL_CRS_SYNC_DIV_16
* @arg @ref LL_CRS_SYNC_DIV_32
* @arg @ref LL_CRS_SYNC_DIV_64
* @arg @ref LL_CRS_SYNC_DIV_128
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
}
/**
* @brief Get division factor for SYNC signal
* @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1
* @arg @ref LL_CRS_SYNC_DIV_2
* @arg @ref LL_CRS_SYNC_DIV_4
* @arg @ref LL_CRS_SYNC_DIV_8
* @arg @ref LL_CRS_SYNC_DIV_16
* @arg @ref LL_CRS_SYNC_DIV_32
* @arg @ref LL_CRS_SYNC_DIV_64
* @arg @ref LL_CRS_SYNC_DIV_128
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
}
/**
* @brief Set SYNC signal source
* @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
* @arg @ref LL_CRS_SYNC_SOURCE_USB
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
}
/**
* @brief Get SYNC signal source
* @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
* @arg @ref LL_CRS_SYNC_SOURCE_USB
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
}
/**
* @brief Set input polarity for the SYNC signal source
* @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
}
/**
* @brief Get input polarity for the SYNC signal source
* @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
}
/**
* @brief Configure CRS for the synchronization
* @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
* CFGR RELOAD LL_CRS_ConfigSynchronization\n
* CFGR FELIM LL_CRS_ConfigSynchronization\n
* CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
* CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
* CFGR SYNCPOL LL_CRS_ConfigSynchronization
* @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
* @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
* @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
* @param Settings This parameter can be a combination of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
* or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
* @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
* @retval None
*/
__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue,
uint32_t ReloadValue, uint32_t Settings)
{
MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
MODIFY_REG(CRS->CFGR,
CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
* @{
*/
/**
* @brief Generate software SYNC event
* @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
{
SET_BIT(CRS->CR, CRS_CR_SWSYNC);
}
/**
* @brief Get the frequency error direction latched in the time of the last
* SYNC event
* @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
* @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
{
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
}
/**
* @brief Get the frequency error counter value latched in the time of the last SYNC event
* @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
* @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
{
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check if SYNC event OK signal occurred or not
* @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
}
/**
* @brief Check if SYNC warning signal occurred or not
* @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
}
/**
* @brief Check if Synchronization or trimming error signal occurred or not
* @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
}
/**
* @brief Check if Expected SYNC signal occurred or not
* @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
}
/**
* @brief Check if SYNC error signal occurred or not
* @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
}
/**
* @brief Check if SYNC missed error signal occurred or not
* @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
}
/**
* @brief Check if Trimming overflow or underflow occurred or not
* @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
}
/**
* @brief Clear the SYNC event OK flag
* @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
}
/**
* @brief Clear the SYNC warning flag
* @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
}
/**
* @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
* the ERR flag
* @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
}
/**
* @brief Clear Expected SYNC flag
* @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable SYNC event OK interrupt
* @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
{
SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
}
/**
* @brief Disable SYNC event OK interrupt
* @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
}
/**
* @brief Check if SYNC event OK interrupt is enabled or not
* @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
}
/**
* @brief Enable SYNC warning interrupt
* @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
{
SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
}
/**
* @brief Disable SYNC warning interrupt
* @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
}
/**
* @brief Check if SYNC warning interrupt is enabled or not
* @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Synchronization or trimming error interrupt
* @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
{
SET_BIT(CRS->CR, CRS_CR_ERRIE);
}
/**
* @brief Disable Synchronization or trimming error interrupt
* @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
}
/**
* @brief Check if Synchronization or trimming error interrupt is enabled or not
* @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Expected SYNC interrupt
* @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
{
SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
}
/**
* @brief Disable Expected SYNC interrupt
* @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
}
/**
* @brief Check if Expected SYNC interrupt is enabled or not
* @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_CRS_DeInit(void);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(CRS) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32G4xx_LL_CRS_H */

2578
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h
View File

File diff suppressed because it is too large Load Diff

2006
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h
View File

File diff suppressed because it is too large Load Diff

1422
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h
View File

File diff suppressed because it is too large Load Diff

994
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h
View File

@ -1,994 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_ll_gpio.h
* @author MCD Application Team
* @brief Header file of GPIO LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_GPIO_H
#define STM32G4xx_LL_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
/** @defgroup GPIO_LL GPIO
* @{
*/
/** MISRA C:2012 deviation rule has been granted for following rules:
* Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..]
* which may be out of array bounds [..,UNKNOWN] in following APIs:
* LL_GPIO_GetAFPin_0_7
* LL_GPIO_SetAFPin_0_7
* LL_GPIO_SetAFPin_8_15
* LL_GPIO_GetAFPin_8_15
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
* @{
*/
/**
* @brief LL GPIO Init Structure definition
*/
typedef struct
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_LL_EC_PIN */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_MODE.
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_SPEED.
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_PULL.
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_AF.
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
} LL_GPIO_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_LL_EC_PIN PIN
* @{
*/
#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */
#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */
#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */
#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */
#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */
#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */
#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */
#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */
#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */
#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */
#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */
#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */
#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */
#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */
#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */
#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */
#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | \
GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | \
GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 | \
GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
GPIO_BSRR_BS15) /*!< Select all pins */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_MODE Mode
* @{
*/
#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */
#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */
#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */
#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_OUTPUT Output Type
* @{
*/
#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */
#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_SPEED Output Speed
* @{
*/
#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */
#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */
#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */
/**
* @}
*/
#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW
#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM
#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH
#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH
/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
* @{
*/
#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */
#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_AF Alternate Function
* @{
*/
#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */
#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */
#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */
#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */
#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */
#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */
#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */
#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */
#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */
#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */
#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */
#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */
#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */
#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */
#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */
#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
* @{
*/
/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in GPIO register
* @param __INSTANCE__ GPIO Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in GPIO register
* @param __INSTANCE__ GPIO Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
* @{
*/
/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
* @{
*/
/**
* @brief Configure gpio mode for a dedicated pin on dedicated port.
* @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll MODER MODEy LL_GPIO_SetPinMode
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_GPIO_MODE_INPUT
* @arg @ref LL_GPIO_MODE_OUTPUT
* @arg @ref LL_GPIO_MODE_ALTERNATE
* @arg @ref LL_GPIO_MODE_ANALOG
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
{
MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
}
/**
* @brief Return gpio mode for a dedicated pin on dedicated port.
* @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll MODER MODEy LL_GPIO_GetPinMode
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_MODE_INPUT
* @arg @ref LL_GPIO_MODE_OUTPUT
* @arg @ref LL_GPIO_MODE_ALTERNATE
* @arg @ref LL_GPIO_MODE_ANALOG
*/
__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->MODER,
(GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
}
/**
* @brief Configure gpio output type for several pins on dedicated port.
* @note Output type as to be set when gpio pin is in output or
* alternate modes. Possible type are Push-pull or Open-drain.
* @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @param OutputType This parameter can be one of the following values:
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
{
MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
}
/**
* @brief Return gpio output type for several pins on dedicated port.
* @note Output type as to be set when gpio pin is in output or
* alternate modes. Possible type are Push-pull or Open-drain.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
*/
__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
}
/**
* @brief Configure gpio speed for a dedicated pin on dedicated port.
* @note I/O speed can be Low, Medium, Fast or High speed.
* @note Warning: only one pin can be passed as parameter.
* @note Refer to datasheet for frequency specifications and the power
* supply and load conditions for each speed.
* @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @param Speed This parameter can be one of the following values:
* @arg @ref LL_GPIO_SPEED_FREQ_LOW
* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
* @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
{
MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U)),
(Speed << (POSITION_VAL(Pin) * 2U)));
}
/**
* @brief Return gpio speed for a dedicated pin on dedicated port.
* @note I/O speed can be Low, Medium, Fast or High speed.
* @note Warning: only one pin can be passed as parameter.
* @note Refer to datasheet for frequency specifications and the power
* supply and load conditions for each speed.
* @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_SPEED_FREQ_LOW
* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
* @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
*/
__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
(GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
}
/**
* @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @param Pull This parameter can be one of the following values:
* @arg @ref LL_GPIO_PULL_NO
* @arg @ref LL_GPIO_PULL_UP
* @arg @ref LL_GPIO_PULL_DOWN
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
{
MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
}
/**
* @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
* @note Warning: only one pin can be passed as parameter.
* @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_PULL_NO
* @arg @ref LL_GPIO_PULL_UP
* @arg @ref LL_GPIO_PULL_DOWN
*/
__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->PUPDR,
(GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
}
/**
* @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
* @note Possible values are from AF0 to AF15 depending on target.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @param Alternate This parameter can be one of the following values:
* @arg @ref LL_GPIO_AF_0
* @arg @ref LL_GPIO_AF_1
* @arg @ref LL_GPIO_AF_2
* @arg @ref LL_GPIO_AF_3
* @arg @ref LL_GPIO_AF_4
* @arg @ref LL_GPIO_AF_5
* @arg @ref LL_GPIO_AF_6
* @arg @ref LL_GPIO_AF_7
* @arg @ref LL_GPIO_AF_8
* @arg @ref LL_GPIO_AF_9
* @arg @ref LL_GPIO_AF_10
* @arg @ref LL_GPIO_AF_11
* @arg @ref LL_GPIO_AF_12
* @arg @ref LL_GPIO_AF_13
* @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
{
MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
(Alternate << (POSITION_VAL(Pin) * 4U)));
}
/**
* @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
* @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_AF_0
* @arg @ref LL_GPIO_AF_1
* @arg @ref LL_GPIO_AF_2
* @arg @ref LL_GPIO_AF_3
* @arg @ref LL_GPIO_AF_4
* @arg @ref LL_GPIO_AF_5
* @arg @ref LL_GPIO_AF_6
* @arg @ref LL_GPIO_AF_7
* @arg @ref LL_GPIO_AF_8
* @arg @ref LL_GPIO_AF_9
* @arg @ref LL_GPIO_AF_10
* @arg @ref LL_GPIO_AF_11
* @arg @ref LL_GPIO_AF_12
* @arg @ref LL_GPIO_AF_13
* @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15
*/
__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->AFR[0],
(GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
}
/**
* @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
* @note Possible values are from AF0 to AF15 depending on target.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @param Alternate This parameter can be one of the following values:
* @arg @ref LL_GPIO_AF_0
* @arg @ref LL_GPIO_AF_1
* @arg @ref LL_GPIO_AF_2
* @arg @ref LL_GPIO_AF_3
* @arg @ref LL_GPIO_AF_4
* @arg @ref LL_GPIO_AF_5
* @arg @ref LL_GPIO_AF_6
* @arg @ref LL_GPIO_AF_7
* @arg @ref LL_GPIO_AF_8
* @arg @ref LL_GPIO_AF_9
* @arg @ref LL_GPIO_AF_10
* @arg @ref LL_GPIO_AF_11
* @arg @ref LL_GPIO_AF_12
* @arg @ref LL_GPIO_AF_13
* @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
{
MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
(Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
}
/**
* @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
* @note Possible values are from AF0 to AF15 depending on target.
* @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_AF_0
* @arg @ref LL_GPIO_AF_1
* @arg @ref LL_GPIO_AF_2
* @arg @ref LL_GPIO_AF_3
* @arg @ref LL_GPIO_AF_4
* @arg @ref LL_GPIO_AF_5
* @arg @ref LL_GPIO_AF_6
* @arg @ref LL_GPIO_AF_7
* @arg @ref LL_GPIO_AF_8
* @arg @ref LL_GPIO_AF_9
* @arg @ref LL_GPIO_AF_10
* @arg @ref LL_GPIO_AF_11
* @arg @ref LL_GPIO_AF_12
* @arg @ref LL_GPIO_AF_13
* @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15
*/
__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->AFR[1],
(GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
}
/**
* @brief Lock configuration of several pins for a dedicated port.
* @note When the lock sequence has been applied on a port bit, the
* value of this port bit can no longer be modified until the
* next reset.
* @note Each lock bit freezes a specific configuration register
* (control and alternate function registers).
* @rmtoll LCKR LCKK LL_GPIO_LockPin
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
__IO uint32_t temp;
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
WRITE_REG(GPIOx->LCKR, PinMask);
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
/* Read LCKR register. This read is mandatory to complete key lock sequence */
temp = READ_REG(GPIOx->LCKR);
(void) temp;
}
/**
* @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
* @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
}
/**
* @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
* @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
* @param GPIOx GPIO Port
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
{
return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup GPIO_LL_EF_Data_Access Data Access
* @{
*/
/**
* @brief Return full input data register value for a dedicated port.
* @rmtoll IDR IDy LL_GPIO_ReadInputPort
* @param GPIOx GPIO Port
* @retval Input data register value of port
*/
__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
{
return (uint32_t)(READ_REG(GPIOx->IDR));
}
/**
* @brief Return if input data level for several pins of dedicated port is high or low.
* @rmtoll IDR IDy LL_GPIO_IsInputPinSet
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
}
/**
* @brief Write output data register for the port.
* @rmtoll ODR ODy LL_GPIO_WriteOutputPort
* @param GPIOx GPIO Port
* @param PortValue Level value for each pin of the port
* @retval None
*/
__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
{
WRITE_REG(GPIOx->ODR, PortValue);
}
/**
* @brief Return full output data register value for a dedicated port.
* @rmtoll ODR ODy LL_GPIO_ReadOutputPort
* @param GPIOx GPIO Port
* @retval Output data register value of port
*/
__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
{
return (uint32_t)(READ_REG(GPIOx->ODR));
}
/**
* @brief Return if input data level for several pins of dedicated port is high or low.
* @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
}
/**
* @brief Set several pins to high level on dedicated gpio port.
* @rmtoll BSRR BSy LL_GPIO_SetOutputPin
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
WRITE_REG(GPIOx->BSRR, PinMask);
}
/**
* @brief Set several pins to low level on dedicated gpio port.
* @rmtoll BRR BRy LL_GPIO_ResetOutputPin
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
WRITE_REG(GPIOx->BRR, PinMask);
}
/**
* @brief Toggle data value for several pin of dedicated port.
* @rmtoll ODR ODy LL_GPIO_TogglePin
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
uint32_t odr = READ_REG(GPIOx->ODR);
WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_GPIO_H */

2272
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_i2c.h
View File

File diff suppressed because it is too large Load Diff

1602
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h
View File

File diff suppressed because it is too large Load Diff

2998
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h
View File

File diff suppressed because it is too large Load Diff

1516
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h
View File

File diff suppressed because it is too large Load Diff

6716
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h
View File

File diff suppressed because it is too large Load Diff

317
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h
View File

@ -1,317 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_ll_utils.h
* @author MCD Application Team
* @brief Header file of UTILS LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL UTILS driver contains a set of generic APIs that can be
used by user:
(+) Device electronic signature
(+) Timing functions
(+) PLL configuration functions
@endverbatim
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_UTILS_H
#define STM32G4xx_LL_UTILS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
/** @defgroup UTILS_LL UTILS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
* @{
*/
/* Max delay can be used in LL_mDelay */
#define LL_MAX_DELAY 0xFFFFFFFFU
/**
* @brief Unique device ID register base address
*/
#define UID_BASE_ADDRESS UID_BASE
/**
* @brief Flash size data register base address
*/
#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
/**
* @brief Package data register base address
*/
#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
* @{
*/
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
* @{
*/
/**
* @brief UTILS PLL structure definition
*/
typedef struct
{
uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
This parameter must be a number between Min_Data = 8 and Max_Data = 86
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
uint32_t PLLR; /*!< Division for the main system clock.
This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
} LL_UTILS_PLLInitTypeDef;
/**
* @brief UTILS System, AHB and APB buses clock configuration structure definition
*/
typedef struct
{
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAHBPrescaler(). */
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB1Prescaler(). */
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB2Prescaler(). */
} LL_UTILS_ClkInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
* @{
*/
/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
* @{
*/
#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
/**
* @}
*/
/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
* @{
*/
#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */
#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */
#define LL_UTILS_PACKAGETYPE_WLCSP81 0x00000005U /*!< WLCSP81 package type */
#define LL_UTILS_PACKAGETYPE_LQFP128 0x00000007U /*!< LQFP128 package type */
#define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000008U /*!< UFQFPN32 package type */
#define LL_UTILS_PACKAGETYPE_LQFP32 0x00000009U /*!< LQFP32 package type */
#define LL_UTILS_PACKAGETYPE_UFQFPN48 0x0000000AU /*!< UFQFPN48 package type */
#define LL_UTILS_PACKAGETYPE_LQFP48 0x0000000BU /*!< LQFP48 package type */
#define LL_UTILS_PACKAGETYPE_WLCSP49 0x0000000CU /*!< WLCSP49 package type */
#define LL_UTILS_PACKAGETYPE_UFBGA64 0x0000000DU /*!< UFBGA64 package type */
#define LL_UTILS_PACKAGETYPE_UFBGA100 0x0000000EU /*!< UFBGA100 package type */
#define LL_UTILS_PACKAGETYPE_LQFP48_EBIKE 0x00000010U /*!< LQFP48 EBIKE package type */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
* @{
*/
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
* @{
*/
/**
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
* @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
*/
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
}
/**
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
* @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
*/
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
}
/**
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
* @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
}
/**
* @brief Get Flash memory size
* @note This bitfield indicates the size of the device Flash memory expressed in
* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
* @retval FLASH_SIZE[15:0]: Flash memory size
*/
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0x0000FFFFUL);
}
/**
* @brief Get Package type
* @retval Returned value can be one of the following values:
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP64
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP81
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP128
* @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP32
* @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP48
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP49
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA64
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP48_EBIKE
*
*/
__STATIC_INLINE uint32_t LL_GetPackageType(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
}
/**
* @}
*/
/** @defgroup UTILS_LL_EF_DELAY DELAY
* @{
*/
/**
* @brief This function configures the Cortex-M SysTick source of the time base.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Number of ticks
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
/* Configure the SysTick to have interrupt in 1ms time base */
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
}
void LL_Init1msTick(uint32_t HCLKFrequency);
void LL_mDelay(uint32_t Delay);
/**
* @}
*/
/** @defgroup UTILS_EF_SYSTEM SYSTEM
* @{
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_UTILS_H */

6
Drivers/STM32G4xx_HAL_Driver/LICENSE.txt
View File

@ -1,6 +0,0 @@
This software component is provided to you as part of a software package and
applicable license terms are in the Package_license file. If you received this
software component outside of a package or without applicable license terms,
the terms of the BSD-3-Clause license shall apply.
You may obtain a copy of the BSD-3-Clause at:
https://opensource.org/licenses/BSD-3-Clause

772
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c
View File

@ -1,772 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal.c
* @author MCD Application Team
* @brief HAL module driver.
* This is the common part of the HAL initialization
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The common HAL driver contains a set of generic and common APIs that can be
used by the PPP peripheral drivers and the user to start using the HAL.
[..]
The HAL contains two APIs' categories:
(+) Common HAL APIs
(+) Services HAL APIs
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @defgroup HAL HAL
* @brief HAL module driver
* @{
*/
#ifdef HAL_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
* @brief STM32G4xx HAL Driver version number V1.2.2
*/
#define __STM32G4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32G4xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
#define __STM32G4xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32G4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32G4xx_HAL_VERSION ((__STM32G4xx_HAL_VERSION_MAIN << 24U)\
|(__STM32G4xx_HAL_VERSION_SUB1 << 16U)\
|(__STM32G4xx_HAL_VERSION_SUB2 << 8U )\
|(__STM32G4xx_HAL_VERSION_RC))
#if defined(VREFBUF)
#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */
#endif /* VREFBUF */
/* ------------ SYSCFG registers bit address in the alias region ------------ */
#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
/* --- MEMRMP Register ---*/
/* Alias word address of FB_MODE bit */
#define MEMRMP_OFFSET SYSCFG_OFFSET
#define FB_MODE_BitNumber ((uint8_t)0x8)
#define FB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4))
/* --- GPC Register ---*/
/* Alias word address of CCMER bit */
#define SCSR_OFFSET (SYSCFG_OFFSET + 0x18)
#define CCMER_BitNumber ((uint8_t)0x0)
#define SCSR_CCMER_BB (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (CCMER_BitNumber * 4))
/* Private macro -------------------------------------------------------------*/
/* Exported variables ---------------------------------------------------------*/
/** @defgroup HAL_Exported_Variables HAL Exported Variables
* @{
*/
__IO uint32_t uwTick;
uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup HAL_Exported_Functions HAL Exported Functions
* @{
*/
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
* @brief HAL Initialization and de-initialization functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the Flash interface the NVIC allocation and initial time base
clock configuration.
(+) De-Initialize common part of the HAL.
(+) Configure the time base source to have 1ms time base with a dedicated
Tick interrupt priority.
(++) SysTick timer is used by default as source of time base, but user
can eventually implement his proper time base source (a general purpose
timer for example or other time source), keeping in mind that Time base
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
handled in milliseconds basis.
(++) Time base configuration function (HAL_InitTick ()) is called automatically
at the beginning of the program after reset by HAL_Init() or at any time
when clock is configured, by HAL_RCC_ClockConfig().
(++) Source of time base is configured to generate interrupts at regular
time intervals. Care must be taken if HAL_Delay() is called from a
peripheral ISR process, the Tick interrupt line must have higher priority
(numerically lower) than the peripheral interrupt. Otherwise the caller
ISR process will be blocked.
(++) functions affecting time base configurations are declared as __weak
to make override possible in case of other implementations in user file.
@endverbatim
* @{
*/
/**
* @brief This function is used to configure the Flash prefetch, the Instruction and Data caches,
* the time base source, NVIC and any required global low level hardware
* by calling the HAL_MspInit() callback function to be optionally defined in user file
* stm32g4xx_hal_msp.c.
*
* @note HAL_Init() function is called at the beginning of program after reset and before
* the clock configuration.
*
* @note In the default implementation the System Timer (Systick) is used as source of time base.
* The Systick configuration is based on HSI clock, as HSI is the clock
* used after a system Reset and the NVIC configuration is set to Priority group 4.
* Once done, time base tick starts incrementing: the tick variable counter is incremented
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
HAL_StatusTypeDef status = HAL_OK;
/* Configure Flash prefetch, Instruction cache, Data cache */
/* Default configuration at reset is: */
/* - Prefetch disabled */
/* - Instruction cache enabled */
/* - Data cache enabled */
#if (INSTRUCTION_CACHE_ENABLE == 0U)
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (DATA_CACHE_ENABLE == 0U)
__HAL_FLASH_DATA_CACHE_DISABLE();
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
{
status = HAL_ERROR;
}
else
{
/* Init the low level hardware */
HAL_MspInit();
}
/* Return function status */
return status;
}
/**
* @brief This function de-initializes common part of the HAL and stops the source of time base.
* @note This function is optional.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DeInit(void)
{
/* Reset of all peripherals */
__HAL_RCC_APB1_FORCE_RESET();
__HAL_RCC_APB1_RELEASE_RESET();
__HAL_RCC_APB2_FORCE_RESET();
__HAL_RCC_APB2_RELEASE_RESET();
__HAL_RCC_AHB1_FORCE_RESET();
__HAL_RCC_AHB1_RELEASE_RESET();
__HAL_RCC_AHB2_FORCE_RESET();
__HAL_RCC_AHB2_RELEASE_RESET();
__HAL_RCC_AHB3_FORCE_RESET();
__HAL_RCC_AHB3_RELEASE_RESET();
/* De-Init the low level hardware */
HAL_MspDeInit();
/* Return function status */
return HAL_OK;
}
/**
* @brief Initialize the MSP.
* @retval None
*/
__weak void HAL_MspInit(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes the MSP.
* @retval None
*/
__weak void HAL_MspDeInit(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspDeInit could be implemented in the user file
*/
}
/**
* @brief This function configures the source of the time base:
* The time source is configured to have 1ms time base with a dedicated
* Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
* @note In the default implementation, SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals.
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
* The SysTick interrupt must have higher priority (numerically lower)
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
* The function is declared as __weak to be overwritten in case of other
* implementation in user file.
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
HAL_StatusTypeDef status = HAL_OK;
if (uwTickFreq != 0U)
{
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
uwTickPrio = TickPriority;
}
else
{
status = HAL_ERROR;
}
}
else
{
status = HAL_ERROR;
}
}
else
{
status = HAL_ERROR;
}
/* Return function status */
return status;
}
/**
* @}
*/
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
* @brief HAL Control functions
*
@verbatim
===============================================================================
##### HAL Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Provide a tick value in millisecond
(+) Provide a blocking delay in millisecond
(+) Suspend the time base source interrupt
(+) Resume the time base source interrupt
(+) Get the HAL API driver version
(+) Get the device identifier
(+) Get the device revision identifier
@endverbatim
* @{
*/
/**
* @brief This function is called to increment a global variable "uwTick"
* used as application time base.
* @note In the default implementation, this variable is incremented each 1ms
* in SysTick ISR.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
uwTick += uwTickFreq;
}
/**
* @brief Provides a tick value in millisecond.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
return uwTick;
}
/**
* @brief This function returns a tick priority.
* @retval tick priority
*/
uint32_t HAL_GetTickPrio(void)
{
return uwTickPrio;
}
/**
* @brief Set new tick Freq.
* @retval status
*/
HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t prevTickFreq;
assert_param(IS_TICKFREQ(Freq));
if (uwTickFreq != Freq)
{
/* Back up uwTickFreq frequency */
prevTickFreq = uwTickFreq;
/* Update uwTickFreq global variable used by HAL_InitTick() */
uwTickFreq = Freq;
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
if (status != HAL_OK)
{
/* Restore previous tick frequency */
uwTickFreq = prevTickFreq;
}
}
return status;
}
/**
* @brief Returns tick frequency.
* @retval tick period in Hz
*/
uint32_t HAL_GetTickFreq(void)
{
return uwTickFreq;
}
/**
* @brief This function provides minimum delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
* is incremented.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
uint32_t tickstart = HAL_GetTick();
uint32_t wait = Delay;
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
{
wait += (uint32_t)(uwTickFreq);
}
while ((HAL_GetTick() - tickstart) < wait)
{
}
}
/**
* @brief Suspends Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
* is called, the SysTick interrupt will be disabled and so Tick increment
* is suspended.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_SuspendTick(void)
{
/* Disable SysTick Interrupt */
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Resume Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
* is called, the SysTick interrupt will be enabled and so Tick increment
* is resumed.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_ResumeTick(void)
{
/* Enable SysTick Interrupt */
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Returns the HAL revision.
* @retval version : 0xXYZR (8bits for each decimal, R for RC)
*/
uint32_t HAL_GetHalVersion(void)
{
return __STM32G4xx_HAL_VERSION;
}
/**
* @brief Returns the device revision identifier.
* @retval Device revision identifier
*/
uint32_t HAL_GetREVID(void)
{
return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16U);
}
/**
* @brief Returns the device identifier.
* @retval Device identifier
*/
uint32_t HAL_GetDEVID(void)
{
return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
}
/**
* @}
*/
/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
* @brief HAL Debug functions
*
@verbatim
===============================================================================
##### HAL Debug functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Enable/Disable Debug module during SLEEP mode
(+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes
(+) Enable/Disable Debug module during STANDBY mode
@endverbatim
* @{
*/
/**
* @brief Enable the Debug Module during SLEEP mode.
* @retval None
*/
void HAL_DBGMCU_EnableDBGSleepMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Disable the Debug Module during SLEEP mode.
* @retval None
*/
void HAL_DBGMCU_DisableDBGSleepMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Enable the Debug Module during STOP0/STOP1/STOP2 modes.
* @retval None
*/
void HAL_DBGMCU_EnableDBGStopMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Disable the Debug Module during STOP0/STOP1/STOP2 modes.
* @retval None
*/
void HAL_DBGMCU_DisableDBGStopMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Enable the Debug Module during STANDBY mode.
* @retval None
*/
void HAL_DBGMCU_EnableDBGStandbyMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Disable the Debug Module during STANDBY mode.
* @retval None
*/
void HAL_DBGMCU_DisableDBGStandbyMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @}
*/
/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions
* @brief HAL SYSCFG configuration functions
*
@verbatim
===============================================================================
##### HAL SYSCFG configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Start a hardware CCMSRAM erase operation
(+) Enable/Disable the Internal FLASH Bank Swapping
(+) Configure the Voltage reference buffer
(+) Enable/Disable the Voltage reference buffer
(+) Enable/Disable the I/O analog switch voltage booster
@endverbatim
* @{
*/
/**
* @brief Start a hardware CCMSRAM erase operation.
* @note As long as CCMSRAM is not erased the CCMER bit will be set.
* This bit is automatically reset at the end of the CCMSRAM erase operation.
* @retval None
*/
void HAL_SYSCFG_CCMSRAMErase(void)
{
/* unlock the write protection of the CCMER bit */
SYSCFG->SKR = 0xCA;
SYSCFG->SKR = 0x53;
/* Starts a hardware CCMSRAM erase operation*/
SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER);
}
/**
* @brief Enable the Internal FLASH Bank Swapping.
*
* @note This function can be used only for STM32G4xx devices.
*
* @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
* and Flash Bank1 mapped at 0x08040000 (and aliased at 0x00040000)
*
* @retval None
*/
void HAL_SYSCFG_EnableMemorySwappingBank(void)
{
SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE);
}
/**
* @brief Disable the Internal FLASH Bank Swapping.
*
* @note This function can be used only for STM32G4xx devices.
*
* @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000)
* and Flash Bank2 mapped at 0x08040000 (and aliased at 0x00040000)
*
* @retval None
*/
void HAL_SYSCFG_DisableMemorySwappingBank(void)
{
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE);
}
#if defined(VREFBUF)
/**
* @brief Configure the internal voltage reference buffer voltage scale.
* @param VoltageScaling: specifies the output voltage to achieve
* This parameter can be one of the following values:
* @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREFBUF_OUT around 2.048 V.
* This requires VDDA equal to or higher than 2.4 V.
* @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREFBUF_OUT around 2.5 V.
* This requires VDDA equal to or higher than 2.8 V.
* @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREFBUF_OUT around 2.9 V.
* This requires VDDA equal to or higher than 3.15 V.
* @retval None
*/
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
{
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
}
/**
* @brief Configure the internal voltage reference buffer high impedance mode.
* @param Mode: specifies the high impedance mode
* This parameter can be one of the following values:
* @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
* @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
* @retval None
*/
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
{
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
}
/**
* @brief Tune the Internal Voltage Reference buffer (VREFBUF).
* @param TrimmingValue specifies trimming code for VREFBUF calibration
* This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x3F
* @retval None
*/
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
{
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
}
/**
* @brief Enable the Internal Voltage Reference buffer (VREFBUF).
* @retval HAL_OK/HAL_TIMEOUT
*/
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
{
uint32_t tickstart;
SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait for VRR bit */
while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0x00U)
{
if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
return HAL_OK;
}
/**
* @brief Disable the Internal Voltage Reference buffer (VREFBUF).
*
* @retval None
*/
void HAL_SYSCFG_DisableVREFBUF(void)
{
CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
}
#endif /* VREFBUF */
/**
* @brief Enable the I/O analog switch voltage booster
*
* @retval None
*/
void HAL_SYSCFG_EnableIOSwitchBooster(void)
{
SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
}
/**
* @brief Disable the I/O analog switch voltage booster
*
* @retval None
*/
void HAL_SYSCFG_DisableIOSwitchBooster(void)
{
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
}
/**
* @brief Enable the I/O analog switch voltage by VDD
*
* @retval None
*/
void HAL_SYSCFG_EnableIOSwitchVDD(void)
{
SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
}
/**
* @brief Disable the I/O analog switch voltage by VDD
*
* @retval None
*/
void HAL_SYSCFG_DisableIOSwitchVDD(void)
{
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
}
/** @brief CCMSRAM page write protection enable
* @param Page: This parameter is a long 32bit value and can be a value of @ref SYSCFG_CCMSRAMWRP
* @note write protection can only be disabled by a system reset
* @retval None
*/
void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page)
{
assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE(Page));
SET_BIT(SYSCFG->SWPR, (uint32_t)(Page));
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

3682
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c
View File

File diff suppressed because it is too large Load Diff

2373
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c
View File

File diff suppressed because it is too large Load Diff

517
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c
View File

@ -1,517 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_cortex.c
* @author MCD Application Team
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
* + Initialization and Configuration functions
* + Peripheral Control functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** How to configure Interrupts using CORTEX HAL driver ***
===========================================================
[..]
This section provides functions allowing to configure the NVIC interrupts (IRQ).
The Cortex-M4 exceptions are managed by CMSIS functions.
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
-@- IRQ priority order (sorted by highest to lowest priority):
(+@) Lowest pre-emption priority
(+@) Lowest sub priority
(+@) Lowest hardware priority (IRQ number)
[..]
*** How to configure SysTick using CORTEX HAL driver ***
========================================================
[..]
Setup SysTick Timer for time base.
(+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
is a CMSIS function that:
(++) Configures the SysTick Reload register with value passed as function parameter.
(++) Configures the SysTick IRQ priority to the lowest value (0x0F).
(++) Resets the SysTick Counter register.
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
(++) Enables the SysTick Interrupt.
(++) Starts the SysTick Counter.
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
__HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
inside the stm32g4xx_hal_cortex.h file.
(+) You can change the SysTick IRQ priority by calling the
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
(+) To adjust the SysTick time base, use the following formula:
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
(++) Reload Value should not exceed 0xFFFFFF
@endverbatim
******************************************************************************
The table below gives the allowed values of the pre-emption priority and subpriority according
to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
==========================================================================================================================
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
==========================================================================================================================
NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority
| | | 4 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority
| | | 3 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
| | | 2 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
| | | 1 bit for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
| | | 0 bit for subpriority
==========================================================================================================================
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup CORTEX
* @{
*/
#ifdef HAL_CORTEX_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CORTEX_Exported_Functions
* @{
*/
/** @addtogroup CORTEX_Exported_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and Configuration functions #####
==============================================================================
[..]
This section provides the CORTEX HAL driver functions allowing to configure Interrupts
SysTick functionalities
@endverbatim
* @{
*/
/**
* @brief Set the priority grouping field (pre-emption priority and subpriority)
* using the required unlock sequence.
* @param PriorityGroup: The priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
* 1 bit for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
* 0 bit for subpriority
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
}
/**
* @brief Set the priority of an interrupt.
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
* @param PreemptPriority: The pre-emption priority for the IRQn channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority
* @param SubPriority: the subpriority level for the IRQ channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t prioritygroup;
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
}
/**
* @brief Enable a device specific interrupt in the NVIC interrupt controller.
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
* function should be called before.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
}
/**
* @brief Disable a device specific interrupt in the NVIC interrupt controller.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
* @retval None
*/
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Disable interrupt */
NVIC_DisableIRQ(IRQn);
}
/**
* @brief Initiate a system reset request to reset the MCU.
* @retval None
*/
void HAL_NVIC_SystemReset(void)
{
/* System Reset */
NVIC_SystemReset();
}
/**
* @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
* Counter is in free running mode to generate periodic interrupts.
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
return SysTick_Config(TicksNumb);
}
/**
* @}
*/
/** @addtogroup CORTEX_Exported_Functions_Group2
* @brief Cortex control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control the CORTEX
(NVIC, SYSTICK, MPU) functionalities.
@endverbatim
* @{
*/
/**
* @brief Get the priority grouping field from the NVIC Interrupt Controller.
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
*/
uint32_t HAL_NVIC_GetPriorityGrouping(void)
{
/* Get the PRIGROUP[10:8] field value */
return NVIC_GetPriorityGrouping();
}
/**
* @brief Get the priority of an interrupt.
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
* @param PriorityGroup: the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
* 1 bit for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
* 0 bit for subpriority
* @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
* @param pSubPriority: Pointer on the Subpriority value (starting from 0).
* @retval None
*/
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Get priority for Cortex-M system or device specific interrupts */
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
}
/**
* @brief Set Pending bit of an external interrupt.
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
* @retval None
*/
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn);
}
/**
* @brief Get Pending Interrupt (read the pending register in the NVIC
* and return the pending bit for the specified interrupt).
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Return 1 if pending else 0 */
return NVIC_GetPendingIRQ(IRQn);
}
/**
* @brief Clear the pending bit of an external interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
* @retval None
*/
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Clear pending interrupt */
NVIC_ClearPendingIRQ(IRQn);
}
/**
* @brief Get active interrupt (read the active register in NVIC and return the active bit).
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
{
/* Return 1 if active else 0 */
return NVIC_GetActive(IRQn);
}
/**
* @brief Configure the SysTick clock source.
* @param CLKSource: specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
* @retval None
*/
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
{
/* Check the parameters */
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
{
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
}
else
{
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
}
}
/**
* @brief Handle SYSTICK interrupt request.
* @retval None
*/
void HAL_SYSTICK_IRQHandler(void)
{
HAL_SYSTICK_Callback();
}
/**
* @brief SYSTICK callback.
* @retval None
*/
__weak void HAL_SYSTICK_Callback(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SYSTICK_Callback could be implemented in the user file
*/
}
#if (__MPU_PRESENT == 1)
/**
* @brief Enable the MPU.
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged accessto the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Enable the MPU */
MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
/* Ensure MPU setting take effects */
__DSB();
__ISB();
}
/**
* @brief Disable the MPU.
* @retval None
*/
void HAL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable the MPU and clear the control register*/
MPU->CTRL = 0;
}
/**
* @brief Initialize and configure the Region and the memory to be protected.
* @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
* @retval None
*/
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
if ((MPU_Init->Enable) != 0U)
{
/* Check the parameters */
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
MPU->RBAR = MPU_Init->BaseAddress;
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
else
{
MPU->RBAR = 0x00;
MPU->RASR = 0x00;
}
}
#endif /* __MPU_PRESENT */
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CORTEX_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

1110
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c
View File

File diff suppressed because it is too large Load Diff

298
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c
View File

@ -1,298 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_dma_ex.c
* @author MCD Application Team
* @brief DMA Extension HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the DMA Extension peripheral:
* + Extended features functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The DMA Extension HAL driver can be used as follows:
(+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
(+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
to respectively enable/disable the request generator.
(+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from
the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler.
As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be
called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
(exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @defgroup DMAEx DMAEx
* @brief DMA Extended HAL module driver
* @{
*/
#ifdef HAL_DMA_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private Constants ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
* @{
*/
/** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions
* @brief Extended features functions
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
(+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
to respectively enable/disable the request generator.
@endverbatim
* @{
*/
/**
* @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA channel.
* @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity));
assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
/*Check if the DMA state is ready */
if (hdma->State == HAL_DMA_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hdma);
/* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
MODIFY_REG(hdma->DMAmuxChannel->CCR, \
(~DMAMUX_CxCR_DMAREQ_ID), \
((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \
((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
/* Process UnLocked */
__HAL_UNLOCK(hdma);
return HAL_OK;
}
else
{
/*DMA State not Ready*/
return HAL_ERROR;
}
}
/**
* @brief Configure the DMAMUX request generator block used by the given DMA channel (instance).
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA channel.
* @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
* contains the request generator parameters.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block
*/
if ((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))
{
/* Process Locked */
__HAL_LOCK(hdma);
/* Set the request generator new parameters */
hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
((pRequestGeneratorConfig->RequestNumber - 1U) << (POSITION_VAL(DMAMUX_RGxCR_GNBREQ) & 0x1FU)) | \
pRequestGeneratorConfig->Polarity;
/* Process UnLocked */
__HAL_UNLOCK(hdma);
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Enable the DMAMUX request generator block used by the given DMA channel (instance).
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block
*/
if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
{
/* Enable the request generator*/
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Disable the DMAMUX request generator block used by the given DMA channel (instance).
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block
*/
if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
{
/* Disable the request generator*/
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Handles DMAMUX interrupt request.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA channel.
* @retval None
*/
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
{
/* Check for DMAMUX Synchronization overrun */
if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
{
/* Disable the synchro overrun interrupt */
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
if (hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
}
}
if (hdma->DMAmuxRequestGen != 0)
{
/* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
{
/* Disable the request gen overrun interrupt */
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
if (hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
}
}
}
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

639
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c
View File

@ -1,639 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_exti.c
* @author MCD Application Team
* @brief EXTI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
* functionalities of the General Purpose Input/Output (EXTI) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### EXTI Peripheral features #####
==============================================================================
[..]
(+) Each Exti line can be configured within this driver.
(+) Exti line can be configured in 3 different modes
(++) Interrupt
(++) Event
(++) Both of them
(+) Configurable Exti lines can be configured with 3 different triggers
(++) Rising
(++) Falling
(++) Both of them
(+) When set in interrupt mode, configurable Exti lines have two different
interrupt pending registers which allow to distinguish which transition
occurs:
(++) Rising edge pending interrupt
(++) Falling
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
be selected through multiplexer.
##### How to use this driver #####
==============================================================================
[..]
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
(++) Choose the interrupt line number by setting "Line" member from
EXTI_ConfigTypeDef structure.
(++) Configure the interrupt and/or event mode using "Mode" member from
EXTI_ConfigTypeDef structure.
(++) For configurable lines, configure rising and/or falling trigger
"Trigger" member from EXTI_ConfigTypeDef structure.
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
member from GPIO_InitTypeDef structure.
(#) Get current Exti configuration of a dedicated line using
HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
(++) Provide exiting handle as first parameter.
(++) Provide which callback will be registered using one value from
EXTI_CallbackIDTypeDef.
(++) Provide callback function pointer.
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
/** MISRA C:2012 deviation rule has been granted for following rule:
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
* of bounds [0,3] in following API :
* HAL_EXTI_SetConfigLine
* HAL_EXTI_GetConfigLine
* HAL_EXTI_ClearConfigLine
*/
#ifdef HAL_EXTI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
#define EXTI_MODE_OFFSET 0x08U /* 0x20: offset between MCU IMR/EMR registers */
#define EXTI_CONFIG_OFFSET 0x08U /* 0x20: offset between MCU Rising/Falling configuration registers */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup EXTI_Exported_Functions
* @{
*/
/** @addtogroup EXTI_Exported_Functions_Group1
* @brief Configuration functions
*
@verbatim
===============================================================================
##### Configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Set configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on EXTI configuration to be set.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check parameters */
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
/* Assign line number to handle */
hexti->Line = pExtiConfig->Line;
/* Compute line register offset */
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
/* Compute line position */
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
/* Compute line mask */
maskline = (1uL << linepos);
/* Configure triggers for configurable lines */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
/* Configure rising trigger */
regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store rising trigger mode */
*regaddr = regval;
/* Configure falling trigger */
regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store falling trigger mode */
*regaddr = regval;
/* Configure gpio port selection in case of gpio exti line */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
SYSCFG->EXTICR[linepos >> 2u] = regval;
}
}
/* Configure interrupt mode : read current mode */
regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store interrupt mode */
*regaddr = regval;
/* Configure event mode : read current mode */
regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store event mode */
*regaddr = regval;
return HAL_OK;
}
/**
* @brief Get configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on structure to store Exti configuration.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* Store handle line number to configuration structure */
pExtiConfig->Line = hexti->Line;
/* Compute line register offset and line mask */
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
/* Compute line position */
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
/* Compute mask */
maskline = (1uL << linepos);
/* 1] Get core mode : interrupt */
regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
}
else
{
pExtiConfig->Mode = EXTI_MODE_NONE;
}
/* Get event mode */
regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Mode |= EXTI_MODE_EVENT;
}
/* Get default Trigger and GPIOSel configuration */
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
pExtiConfig->GPIOSel = 0x00u;
/* 2] Get trigger for configurable lines : rising */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Check if configuration of selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
}
/* Get falling configuration */
regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Check if configuration of selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
}
/* Get Gpio port selection for gpio lines */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
pExtiConfig->GPIOSel = ((regval >> (SYSCFG_EXTICR1_EXTI1_Pos * ((linepos & 0x03u)))));
}
}
return HAL_OK;
}
/**
* @brief Clear whole configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
/* compute line position */
linepos = (hexti->Line & EXTI_PIN_MASK);
/* compute line mask */
maskline = (1uL << linepos);
/* 1] Clear interrupt mode */
regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* 2] Clear event mode */
regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* 3] Clear triggers in case of configurable lines */
if ((hexti->Line & EXTI_CONFIG) != 0x00u)
{
regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* Get Gpio port selection for gpio lines */
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
SYSCFG->EXTICR[linepos >> 2u] = regval;
}
}
return HAL_OK;
}
/**
* @brief Register callback for a dedicated Exti line.
* @param hexti Exti handle.
* @param CallbackID User callback identifier.
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
* @param pPendingCbfn function pointer to be stored as callback.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_EXTI_CB(CallbackID));
switch (CallbackID)
{
/* set common callback */
case HAL_EXTI_COMMON_CB_ID:
hexti->PendingCallback = pPendingCbfn;
break;
default:
hexti->PendingCallback = NULL;
status = HAL_ERROR;
break;
}
return status;
}
/**
* @brief Store line number as handle private field.
* @param hexti Exti handle.
* @param ExtiLine Exti line number.
* This parameter can be from 0 to @ref EXTI_LINE_NB.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(ExtiLine));
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
else
{
/* Store line number as handle private field */
hexti->Line = ExtiLine;
return HAL_OK;
}
}
/**
* @}
*/
/** @addtogroup EXTI_Exported_Functions_Group2
* @brief EXTI IO functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Handle EXTI interrupt request.
* @param hexti Exti handle.
* @retval none.
*/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t maskline;
uint32_t offset;
/* Compute line register offset */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
/* compute line mask */
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Get pending bit */
regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & maskline);
if (regval != 0x00u)
{
/* Clear pending bit */
*regaddr = maskline;
/* Call pending callback */
if (hexti->PendingCallback != NULL)
{
hexti->PendingCallback();
}
}
}
/**
* @brief Get interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge unused
* @retval 1 if interrupt is pending else 0.
*/
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
UNUSED(Edge);
/* Compute line register offset */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
/* Compute line position */
linepos = (hexti->Line & EXTI_PIN_MASK);
/* Compute line mask */
maskline = (1uL << linepos);
/* Get pending bit */
regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
/* return 1 if bit is set else 0 */
regval = ((*regaddr & maskline) >> linepos);
return regval;
}
/**
* @brief Clear interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge unused
* @retval None.
*/
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t maskline;
uint32_t offset;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
UNUSED(Edge);
/* Compute line register offset */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
/* Compute line mask */
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Get pending register address */
regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
/* Clear Pending bit */
*regaddr = maskline;
}
/**
* @brief Generate a software interrupt for a dedicated line.
* @param hexti Exti handle.
* @retval None.
*/
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t maskline;
uint32_t offset;
/* Check parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
/* compute line register offset */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
/* compute line mask */
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
*regaddr = maskline;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_EXTI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

3516
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.c
View File

File diff suppressed because it is too large Load Diff

768
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c
View File

@ -1,768 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_flash.c
* @author MCD Application Team
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
* + Program operations functions
* + Memory Control functions
* + Peripheral Errors functions
*
@verbatim
==============================================================================
##### FLASH peripheral features #####
==============================================================================
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
to the Flash memory. It implements the erase and program Flash memory operations
and the read and write protection mechanisms.
[..] The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.
[..] The FLASH main features are:
(+) Flash memory read operations
(+) Flash memory program/erase operations
(+) Read / write protections
(+) Option bytes programming
(+) Prefetch on I-Code
(+) 32 cache lines of 4*64 or 2*128 bits on I-Code
(+) 8 cache lines of 4*64 or 2*128 bits on D-Code
(+) Error code correction (ECC) : Data in flash are 72-bits word
(8 bits added per double word)
##### How to use this driver #####
==============================================================================
[..]
This driver provides functions and macros to configure and program the FLASH
memory of all STM32G4xx devices.
(#) Flash Memory IO Programming functions:
(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
HAL_FLASH_Lock() functions
(++) Program functions: double word and fast program (full row programming)
(++) There are two modes of programming :
(+++) Polling mode using HAL_FLASH_Program() function
(+++) Interrupt mode using HAL_FLASH_Program_IT() function
(#) Interrupts and flags management functions:
(++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
(++) Callback functions are called when the flash operations are finished :
HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
HAL_FLASH_OperationErrorCallback()
(++) Get error flag status by calling HAL_GetError()
(#) Option bytes management functions:
(++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
HAL_FLASH_OB_Lock() functions
(++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.
In this case, a reset is generated
[..]
In addition to these functions, this driver includes a set of macros allowing
to handle the following operations:
(+) Set the latency
(+) Enable/Disable the prefetch buffer
(+) Enable/Disable the Instruction cache and the Data cache
(+) Reset the Instruction cache and the Data cache
(+) Enable/Disable the Flash power-down during low-power run and sleep modes
(+) Enable/Disable the Flash interrupts
(+) Monitor the Flash flags status
@endverbatim
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @defgroup FLASH FLASH
* @brief FLASH HAL module driver
* @{
*/
#ifdef HAL_FLASH_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup FLASH_Private_Constants FLASH Private Constants
* @{
*/
#define FLASH_NB_DOUBLE_WORDS_IN_ROW 32
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Variables FLASH Private Variables
* @{
*/
/**
* @brief Variable used for Program/Erase sectors under interruption
*/
FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED,
.ErrorCode = HAL_FLASH_ERROR_NONE,
.ProcedureOnGoing = FLASH_PROC_NONE,
.Address = 0U,
.Bank = FLASH_BANK_1,
.Page = 0U,
.NbPagesToErase = 0U,
.CacheToReactivate = FLASH_CACHE_DISABLED};
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup FLASH_Private_Functions FLASH Private Functions
* @{
*/
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
* @{
*/
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
* @brief Programming operation functions
*
@verbatim
===============================================================================
##### Programming operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the FLASH
program operations.
@endverbatim
* @{
*/
/**
* @brief Program double word or fast program of a row at a specified address.
* @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program.
* @param Address specifies the address to be programmed.
* @param Data specifies the data to be programmed.
* This parameter is the data for the double word program and the address where
* are stored the data for the row fast program.
*
* @retval HAL_Status
*/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
HAL_StatusTypeDef status;
uint32_t prog_bit = 0;
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if (status == HAL_OK)
{
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
{
/* Program double-word (64-bit) at a specified address */
FLASH_Program_DoubleWord(Address, Data);
prog_bit = FLASH_CR_PG;
}
else if ((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
{
/* Fast program a 32 row double-word (64-bit) at a specified address */
FLASH_Program_Fast(Address, (uint32_t)Data);
/* If it is the last row, the bit will be cleared at the end of the operation */
if (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
{
prog_bit = FLASH_CR_FSTPG;
}
}
else
{
/* Nothing to do */
}
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* If the program operation is completed, disable the PG or FSTPG Bit */
if (prog_bit != 0U)
{
CLEAR_BIT(FLASH->CR, prog_bit);
}
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
/* return status */
return status;
}
/**
* @brief Program double word or fast program of a row at a specified address with interrupt enabled.
* @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program.
* @param Address specifies the address to be programmed.
* @param Data specifies the data to be programmed.
* This parameter is the data for the double word program and the address where
* are stored the data for the row fast program.
*
* @retval HAL_Status
*/
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
HAL_StatusTypeDef status;
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Reset error code */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if (status != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
}
else
{
/* Set internal variables used by the IRQ handler */
if (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
{
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_LAST;
}
else
{
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
}
pFlash.Address = Address;
/* Enable End of Operation and Error interrupts */
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
{
/* Program double-word (64-bit) at a specified address */
FLASH_Program_DoubleWord(Address, Data);
}
else if ((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
{
/* Fast program a 32 row double-word (64-bit) at a specified address */
FLASH_Program_Fast(Address, (uint32_t)Data);
}
else
{
/* Nothing to do */
}
}
return status;
}
/**
* @brief Handle FLASH interrupt request.
* @retval None
*/
void HAL_FLASH_IRQHandler(void)
{
uint32_t tmp_page;
uint32_t error;
FLASH_ProcedureTypeDef procedure;
/* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */
CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB));
#if defined (FLASH_OPTR_DBANK)
CLEAR_BIT(FLASH->CR, FLASH_CR_MER2);
#endif
/* Disable the FSTPG Bit only if it is the last row programmed */
if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)
{
CLEAR_BIT(FLASH->CR, FLASH_CR_FSTPG);
}
/* Check FLASH operation error flags */
error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
if (error != 0U)
{
/* Save the error code */
pFlash.ErrorCode |= error;
/* Clear error programming flags */
__HAL_FLASH_CLEAR_FLAG(error);
/* Flush the caches to be sure of the data consistency */
FLASH_FlushCaches() ;
/* FLASH error interrupt user callback */
procedure = pFlash.ProcedureOnGoing;
if (procedure == FLASH_PROC_PAGE_ERASE)
{
HAL_FLASH_OperationErrorCallback(pFlash.Page);
}
else if (procedure == FLASH_PROC_MASS_ERASE)
{
HAL_FLASH_OperationErrorCallback(pFlash.Bank);
}
else if ((procedure == FLASH_PROC_PROGRAM) ||
(procedure == FLASH_PROC_PROGRAM_LAST))
{
HAL_FLASH_OperationErrorCallback(pFlash.Address);
}
else
{
/* Nothing to do */
}
/*Stop the procedure ongoing*/
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
/* Check FLASH End of Operation flag */
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
if (pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE)
{
/* Nb of pages to erased can be decreased */
pFlash.NbPagesToErase--;
/* Check if there are still pages to erase*/
if (pFlash.NbPagesToErase != 0U)
{
/* Indicate user which page has been erased*/
HAL_FLASH_EndOfOperationCallback(pFlash.Page);
/* Increment page number */
pFlash.Page++;
tmp_page = pFlash.Page;
FLASH_PageErase(tmp_page, pFlash.Bank);
}
else
{
/* No more pages to Erase */
/* Reset Address and stop Erase pages procedure */
pFlash.Page = 0xFFFFFFFFU;
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
/* Flush the caches to be sure of the data consistency */
FLASH_FlushCaches() ;
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(pFlash.Page);
}
}
else
{
/* Flush the caches to be sure of the data consistency */
FLASH_FlushCaches() ;
procedure = pFlash.ProcedureOnGoing;
if (procedure == FLASH_PROC_MASS_ERASE)
{
/* MassErase ended. Return the selected bank */
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
}
else if ((procedure == FLASH_PROC_PROGRAM) ||
(procedure == FLASH_PROC_PROGRAM_LAST))
{
/* Program ended. Return the selected address */
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
}
else
{
/* Nothing to do */
}
/*Clear the procedure ongoing*/
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
}
if (pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
{
/* Disable End of Operation and Error interrupts */
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
}
}
/**
* @brief FLASH end of operation interrupt callback.
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure:
* @arg Mass Erase: Bank number which has been requested to erase
* @arg Page Erase: Page which has been erased
* (if 0xFFFFFFFF, it means that all the selected pages have been erased)
* @arg Program: Address which was selected for data program
* @retval None
*/
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
*/
}
/**
* @brief FLASH operation error interrupt callback.
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure:
* @arg Mass Erase: Bank number which has been requested to erase
* @arg Page Erase: Page number which returned an error
* @arg Program: Address which was selected for data program
* @retval None
*/
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
* @brief Management functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the FLASH
memory operations.
@endverbatim
* @{
*/
/**
* @brief Unlock the FLASH control register access.
* @retval HAL_Status
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
HAL_StatusTypeDef status = HAL_OK;
if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
{
/* Authorize the FLASH Registers access */
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
/* verify Flash is unlocked */
if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
{
status = HAL_ERROR;
}
}
return status;
}
/**
* @brief Lock the FLASH control register access.
* @retval HAL_Status
*/
HAL_StatusTypeDef HAL_FLASH_Lock(void)
{
HAL_StatusTypeDef status = HAL_ERROR;
/* Set the LOCK Bit to lock the FLASH Registers access */
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
/* verify Flash is locked */
if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
{
status = HAL_OK;
}
return status;
}
/**
* @brief Unlock the FLASH Option Bytes Registers access.
* @retval HAL_Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
{
HAL_StatusTypeDef status = HAL_OK;
if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)
{
/* Authorizes the Option Byte register programming */
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
/* verify option bytes are unlocked */
if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)
{
status = HAL_ERROR;
}
}
return status;
}
/**
* @brief Lock the FLASH Option Bytes Registers access.
* @retval HAL_Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
{
HAL_StatusTypeDef status = HAL_ERROR;
/* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
/* Verify option bytes are locked */
if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)
{
status = HAL_OK;
}
return status;
}
/**
* @brief Launch the option byte loading.
* @retval HAL_Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
{
/* Set the bit to force the option byte reloading */
SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
/* Wait for last operation to be completed */
return (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief Peripheral Errors functions
*
@verbatim
===============================================================================
##### Peripheral Errors functions #####
===============================================================================
[..]
This subsection permits to get in run-time Errors of the FLASH peripheral.
@endverbatim
* @{
*/
/**
* @brief Get the specific FLASH error flag.
* @retval FLASH_ErrorCode. The returned value can be:
* @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
* @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag
* @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
* @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
* @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
* @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag
* @arg HAL_FLASH_ERROR_NONE: No error set
* @arg HAL_FLASH_ERROR_OP: FLASH Operation error
* @arg HAL_FLASH_ERROR_PROG: FLASH Programming error
* @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error
* @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error
* @arg HAL_FLASH_ERROR_SIZ: FLASH Size error
* @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error
* @arg HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error
* @arg HAL_FLASH_ERROR_FAST: FLASH Fast programming error
* @arg HAL_FLASH_ERROR_RD: FLASH PCROP read error
* @arg HAL_FLASH_ERROR_OPTV: FLASH Option validity error
*/
uint32_t HAL_FLASH_GetError(void)
{
return pFlash.ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup FLASH_Private_Functions
* @{
*/
/**
* @brief Wait for a FLASH operation to complete.
* @param Timeout maximum flash operation timeout.
* @retval HAL_Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
uint32_t tickstart = HAL_GetTick();
uint32_t error;
while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
{
if ((HAL_GetTick() - tickstart) > Timeout)
{
return HAL_TIMEOUT;
}
}
/* Check FLASH operation error flags */
error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
if (error != 0u)
{
/* Save the error code */
pFlash.ErrorCode |= error;
/* Clear error programming flags */
__HAL_FLASH_CLEAR_FLAG(error);
return HAL_ERROR;
}
/* Check FLASH End of Operation flag */
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
}
/* If there is an error flag set */
return HAL_OK;
}
/**
* @brief Program double-word (64-bit) at a specified address.
* @param Address specifies the address to be programmed.
* @param Data specifies the data to be programmed.
* @retval None
*/
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
{
/* Check the parameters */
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
/* Set PG bit */
SET_BIT(FLASH->CR, FLASH_CR_PG);
/* Program first word */
*(uint32_t *)Address = (uint32_t)Data;
/* Barrier to ensure programming is performed in 2 steps, in right order
(independently of compiler optimization behavior) */
__ISB();
/* Program second word */
*(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U);
}
/**
* @brief Fast program a row double-word (64-bit) at a specified address.
* @param Address specifies the address to be programmed.
* @param DataAddress specifies the address where the data are stored.
* @retval None
*/
static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)
{
uint8_t row_index = (2 * FLASH_NB_DOUBLE_WORDS_IN_ROW);
uint32_t *dest_addr = (uint32_t *)Address;
uint32_t *src_addr = (uint32_t *)DataAddress;
uint32_t primask_bit;
/* Check the parameters */
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
/* Set FSTPG bit */
SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
/* Enter critical section: Disable interrupts to avoid any interruption during the loop */
primask_bit = __get_PRIMASK();
__disable_irq();
/* Program the double words of the row */
do
{
*dest_addr = *src_addr;
dest_addr++;
src_addr++;
row_index--;
}
while (row_index != 0U);
/* Exit critical section: restore previous priority mask */
__set_PRIMASK(primask_bit);
}
/**
* @}
*/
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

1414
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c
View File

File diff suppressed because it is too large Load Diff

253
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c
View File

@ -1,253 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_flash_ramfunc.c
* @author MCD Application Team
* @brief FLASH RAMFUNC driver.
* This file provides a Flash firmware functions which should be
* executed from internal SRAM
* + FLASH Power Down in Run mode
* + FLASH DBANK User Option Byte
*
*
@verbatim
==============================================================================
##### Flash RAM functions #####
==============================================================================
*** ARM Compiler ***
--------------------
[..] RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate
source module. Using the 'Options for File' dialog you can simply change
the 'Code / Const' area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the
Options for Target' dialog.
*** ICCARM Compiler ***
-----------------------
[..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
*** GNU Compiler ***
--------------------
[..] RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
@endverbatim
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
* @brief FLASH functions executed from RAM
* @{
*/
#ifdef HAL_FLASH_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions -------------------------------------------------------*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH_RAMFUNC Exported Functions
* @{
*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions
* @brief Data transfers functions
*
@verbatim
===============================================================================
##### ramfunc functions #####
===============================================================================
[..]
This subsection provides a set of functions that should be executed from RAM.
@endverbatim
* @{
*/
/**
* @brief Enable the Power down in Run Mode
* @note This function should be called and executed from SRAM memory.
* @retval None
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void)
{
/* Enable the Power Down in Run mode*/
__HAL_FLASH_POWER_DOWN_ENABLE();
return HAL_OK;
}
/**
* @brief Disable the Power down in Run Mode
* @note This function should be called and executed from SRAM memory.
* @retval None
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void)
{
/* Disable the Power Down in Run mode*/
__HAL_FLASH_POWER_DOWN_DISABLE();
return HAL_OK;
}
#if defined (FLASH_OPTR_DBANK)
/**
* @brief Program the FLASH DBANK User Option Byte.
*
* @note To configure the user option bytes, the option lock bit OPTLOCK must
* be cleared with the call of the HAL_FLASH_OB_Unlock() function.
* @note To modify the DBANK option byte, no PCROP region should be defined.
* To deactivate PCROP, user should perform RDP changing.
*
* @param DBankConfig The FLASH DBANK User Option Byte value.
* This parameter can be one of the following values:
* @arg OB_DBANK_128_BITS: Single-bank with 128-bits data
* @arg OB_DBANK_64_BITS: Dual-bank with 64-bits data
*
* @retval HAL_Status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig)
{
uint32_t count, reg;
HAL_StatusTypeDef status = HAL_ERROR;
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Check if the PCROP is disabled */
reg = FLASH->PCROP1SR;
if (reg > FLASH->PCROP1ER)
{
reg = FLASH->PCROP2SR;
if (reg > FLASH->PCROP2ER)
{
/* Disable Flash prefetch */
__HAL_FLASH_PREFETCH_BUFFER_DISABLE();
if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
{
/* Disable Flash instruction cache */
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
/* Flush Flash instruction cache */
__HAL_FLASH_INSTRUCTION_CACHE_RESET();
}
if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
{
/* Disable Flash data cache */
__HAL_FLASH_DATA_CACHE_DISABLE();
/* Flush Flash data cache */
__HAL_FLASH_DATA_CACHE_RESET();
}
/* Disable WRP zone A of 1st bank if needed */
reg = FLASH->WRP1AR;
if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> FLASH_WRP1AR_WRP1A_STRT_Pos) <=
((reg & FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos))
{
MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), FLASH_WRP1AR_WRP1A_STRT);
}
/* Disable WRP zone B of 1st bank if needed */
reg = FLASH->WRP1BR;
if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> FLASH_WRP1BR_WRP1B_STRT_Pos) <=
((reg & FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos))
{
MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), FLASH_WRP1BR_WRP1B_STRT);
}
/* Disable WRP zone A of 2nd bank if needed */
reg = FLASH->WRP2AR;
if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> FLASH_WRP2AR_WRP2A_STRT_Pos) <=
((reg & FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos))
{
MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), FLASH_WRP2AR_WRP2A_STRT);
}
/* Disable WRP zone B of 2nd bank if needed */
reg = FLASH->WRP2BR;
if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> FLASH_WRP2BR_WRP2B_STRT_Pos) <=
((reg & FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos))
{
MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), FLASH_WRP2BR_WRP2B_STRT);
}
/* Modify the DBANK user option byte */
MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig);
/* Set OPTSTRT Bit */
SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
/* Wait for last operation to be completed */
/* 8 is the number of required instruction cycles for the below loop statement (timeout expressed in ms) */
count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8U / 1000U);
do
{
if (count == 0U)
{
break;
}
count--;
}
while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET);
/* If the option byte program operation is completed, disable the OPTSTRT Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
/* Set the bit to force the option byte reloading */
SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
}
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
return status;
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

532
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c
View File

@ -1,532 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_gpio.c
* @author MCD Application Team
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### GPIO Peripheral features #####
==============================================================================
[..]
(+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
configured by software in several modes:
(++) Input mode
(++) Analog mode
(++) Output mode
(++) Alternate function mode
(++) External interrupt/event lines
(+) During and just after reset, the alternate functions and external interrupt
lines are not active and the I/O ports are configured in input floating mode.
(+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
activated or not.
(+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
type and the IO speed can be selected depending on the VDD value.
(+) The microcontroller IO pins are connected to onboard peripherals/modules through a
multiplexer that allows only one peripheral alternate function (AF) connected
to an IO pin at a time. In this way, there can be no conflict between peripherals
sharing the same IO pin.
(+) All ports have external interrupt/event capability. To use external interrupt
lines, the port must be configured in input mode. All available GPIO pins are
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
(+) The external interrupt/event controller consists of up to 44 edge detectors
(16 lines are connected to GPIO) for generating event/interrupt requests (each
input line can be independently configured to select the type (interrupt or event)
and the corresponding trigger event (rising or falling or both). Each line can
also be masked independently.
##### How to use this driver #####
==============================================================================
[..]
(#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
structure.
(++) In case of Output or alternate function mode selection: the speed is
configured through "Speed" member from GPIO_InitTypeDef structure.
(++) In alternate mode is selection, the alternate function connected to the IO
is configured through "Alternate" member from GPIO_InitTypeDef structure.
(++) Analog mode is required when a pin is to be used as ADC channel
or DAC output.
(++) In case of external interrupt/event selection the "Mode" member from
GPIO_InitTypeDef structure select the type (interrupt or event) and
the corresponding trigger event (rising or falling or both).
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
HAL_NVIC_EnableIRQ().
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
(#) To set/reset the level of a pin configured in output mode use
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
(#) During and just after reset, the alternate functions are not
active and the GPIO pins are configured in input floating mode (except JTAG
pins).
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
priority over the GPIO function.
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
general purpose PF0 and PF1, respectively, when the HSE oscillator is off.
The HSE has priority over the GPIO function.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/** MISRA C:2012 deviation rule has been granted for following rules:
* Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
* range of the shift operator in following API :
* HAL_GPIO_Init
* HAL_GPIO_DeInit
*/
#ifdef HAL_GPIO_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
#define GPIO_NUMBER (16U)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_Exported_Functions
* @{
*/
/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
* @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
uint32_t position = 0x00U;
uint32_t iocurrent;
uint32_t temp;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0U)
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1UL << position);
if (iocurrent != 0x00u)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
temp |= (GPIO_Init->Speed << (position * 2U));
GPIOx->OSPEEDR = temp;
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
temp &= ~(GPIO_OTYPER_OT0 << position) ;
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
GPIOx->OTYPER = temp;
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
temp |= ((GPIO_Init->Pull) << (position * 2U));
GPIOx->PUPDR = temp;
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
temp &= ~(0xFU << ((position & 0x07U) * 4U));
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
GPIOx->AFR[position >> 3U] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
GPIOx->MODER = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
temp = SYSCFG->EXTICR[position >> 2U];
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
SYSCFG->EXTICR[position >> 2U] = temp;
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
{
temp |= iocurrent;
}
EXTI->RTSR1 = temp;
temp = EXTI->FTSR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
{
temp |= iocurrent;
}
EXTI->FTSR1 = temp;
temp = EXTI->EMR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
{
temp |= iocurrent;
}
EXTI->EMR1 = temp;
/* Clear EXTI line configuration */
temp = EXTI->IMR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
{
temp |= iocurrent;
}
EXTI->IMR1 = temp;
}
}
position++;
}
}
/**
* @brief De-initialize the GPIOx peripheral registers to their default reset values.
* @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
* @param GPIO_Pin specifies the port bit to be written.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{
uint32_t position = 0x00U;
uint32_t iocurrent;
uint32_t tmp;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Configure the port pins */
while ((GPIO_Pin >> position) != 0U)
{
/* Get current io position */
iocurrent = (GPIO_Pin) & (1UL << position);
if (iocurrent != 0x00u)
{
/*------------------------- EXTI Mode Configuration --------------------*/
/* Clear the External Interrupt or Event for the current IO */
tmp = SYSCFG->EXTICR[position >> 2U];
tmp &= (0x0FUL << (4U * (position & 0x03U)));
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
{
/* Clear EXTI line configuration */
EXTI->IMR1 &= ~(iocurrent);
EXTI->EMR1 &= ~(iocurrent);
/* Clear Rising Falling edge configuration */
EXTI->FTSR1 &= ~(iocurrent);
EXTI->RTSR1 &= ~(iocurrent);
tmp = 0x0FUL << (4U * (position & 0x03U));
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
}
/*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO in Analog Mode */
GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u));
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position);
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
}
position++;
}
}
/**
* @}
*/
/** @addtogroup GPIO_Exported_Functions_Group2
* @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Read the specified input port pin.
* @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != 0x00U)
{
bitstatus = GPIO_PIN_SET;
}
else
{
bitstatus = GPIO_PIN_RESET;
}
return bitstatus;
}
/**
* @brief Set or clear the selected data port bit.
*
* @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
*
* @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
* @param GPIO_Pin specifies the port bit to be written.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @param PinState specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
/**
* @brief Toggle the specified GPIO pin.
* @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
* @param GPIO_Pin specifies the pin to be toggled.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
uint32_t odr;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
}
/**
* @brief Lock GPIO Pins configuration registers.
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset.
* @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family
* @param GPIO_Pin specifies the port bits to be locked.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
__IO uint32_t tmp = GPIO_LCKR_LCKK;
/* Check the parameters */
assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Apply lock key write sequence */
tmp |= GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
GPIOx->LCKR = GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Read LCKK register. This read is mandatory to complete key lock sequence */
tmp = GPIOx->LCKR;
/* read again in order to confirm lock is active */
if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
{
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Handle EXTI interrupt request.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
/* EXTI line interrupt detected */
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
HAL_GPIO_EXTI_Callback(GPIO_Pin);
}
}
/**
* @brief EXTI line detection callback.
* @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(GPIO_Pin);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_GPIO_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

6884
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c
View File

File diff suppressed because it is too large Load Diff

368
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c_ex.c
View File

@ -1,368 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_i2c_ex.c
* @author MCD Application Team
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
* + Filter Mode Functions
* + WakeUp Mode Functions
* + FastModePlus Functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### I2C peripheral Extended features #####
==============================================================================
[..] Comparing to other previous devices, the I2C interface for STM32G4xx
devices contains the following additional features
(+) Possibility to disable or enable Analog Noise Filter
(+) Use of a configured Digital Noise Filter
(+) Disable or enable wakeup from Stop mode(s)
(+) Disable or enable Fast Mode Plus
##### How to use this driver #####
==============================================================================
[..] This driver provides functions to configure Noise Filter and Wake Up Feature
(#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
(#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
(#) Configure the enable or disable of I2C Wake Up Mode using the functions :
(++) HAL_I2CEx_EnableWakeUp()
(++) HAL_I2CEx_DisableWakeUp()
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
(++) HAL_I2CEx_EnableFastModePlus()
(++) HAL_I2CEx_DisableFastModePlus()
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @defgroup I2CEx I2CEx
* @brief I2C Extended HAL module driver
* @{
*/
#ifdef HAL_I2C_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
* @brief Filter Mode Functions
*
@verbatim
===============================================================================
##### Filter Mode Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Noise Filters
@endverbatim
* @{
*/
/**
* @brief Configure I2C Analog noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Configure I2C Digital noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
* @brief WakeUp Mode Functions
*
@verbatim
===============================================================================
##### WakeUp Mode Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Wake Up Feature
@endverbatim
* @{
*/
/**
* @brief Enable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Enable wakeup from stop mode */
hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Disable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Enable wakeup from stop mode */
hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @brief Fast Mode Plus Functions
*
@verbatim
===============================================================================
##### Fast Mode Plus Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Fast Mode Plus
@endverbatim
* @{
*/
/**
* @brief Enable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref I2CEx_FastModePlus values
* @note For I2C1, fast mode plus driving capability can be enabled on all selected
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
* on each one of the following pins PB6, PB7, PB8 and PB9.
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
* can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
* @note For all I2C2 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
* @note For all I2C3 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
* @retval None
*/
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
{
/* Check the parameter */
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
/* Enable SYSCFG clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Enable fast mode plus driving capability for selected pin */
SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
}
/**
* @brief Disable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref I2CEx_FastModePlus values
* @note For I2C1, fast mode plus driving capability can be disabled on all selected
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
* on each one of the following pins PB6, PB7, PB8 and PB9.
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
* can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
* @note For all I2C2 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
* @note For all I2C3 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
* @retval None
*/
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
{
/* Check the parameter */
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
/* Enable SYSCFG clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Disable fast mode plus driving capability for selected pin */
CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_I2C_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

652
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c
View File

@ -1,652 +0,0 @@
/**
******************************************************************************
* @file stm32g4xx_hal_pwr.c
* @author MCD Application Team
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
* + Initialization/de-initialization functions
* + Peripheral Control functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @defgroup PWR PWR
* @brief PWR HAL module driver
* @{
*/
#ifdef HAL_PWR_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup PWR_Private_Defines PWR Private Defines
* @{
*/
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
* @{
*/
#define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold crossing */
#define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing */
#define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */
#define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..]
@endverbatim
* @{
*/
/**
* @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
* @retval None
*/
void HAL_PWR_DeInit(void)
{
__HAL_RCC_PWR_FORCE_RESET();
__HAL_RCC_PWR_RELEASE_RESET();
}
/**
* @brief Enable access to the backup domain
* (RTC registers, RTC backup data registers).
* @note After reset, the backup domain is protected against
* possible unwanted write accesses.
* @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
* In order to set or modify the RTC clock, the backup domain access must be
* disabled.
* @note LSEON bit that switches on and off the LSE crystal belongs as well to the
* back-up domain.
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
{
SET_BIT(PWR->CR1, PWR_CR1_DBP);
}
/**
* @brief Disable access to the backup domain
* (RTC registers, RTC backup data registers).
* @retval None
*/
void HAL_PWR_DisableBkUpAccess(void)
{
CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
}
/**
* @}
*/
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
* @brief Low Power modes configuration functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
*** PVD configuration ***
=========================
[..]
(+) The PVD is used to monitor the VDD power supply by comparing it to a
threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
(+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
than the PVD threshold. This event is internally connected to the EXTI
line16 and can generate an interrupt if enabled. This is done through
__HAL_PVD_EXTI_ENABLE_IT() macro.
(+) The PVD is stopped in Standby mode.
*** WakeUp pin configuration ***
================================
[..]
(+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
The polarity of these pins can be set to configure event detection on high
level (rising edge) or low level (falling edge).
*** Low Power modes configuration ***
=====================================
[..]
The devices feature 8 low-power modes:
(+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
(+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
(+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
(+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
(+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
(+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
(+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
(+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
*** Low-power run mode ***
==========================
[..]
(+) Entry: (from main run mode)
(++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
(+) Exit:
(++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
then can the system clock frequency be increased above 2 MHz.
*** Sleep mode / Low-power sleep mode ***
=========================================
[..]
(+) Entry:
The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API
in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
(++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
(++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
(+) WFI Exit:
(++) Any peripheral interrupt acknowledged by the nested vectored interrupt
controller (NVIC) or any wake-up event.
(+) WFE Exit:
(++) Any wake-up event such as an EXTI line configured in event mode.
[..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
the MCU is in Low-power Run mode.
*** Stop 0, Stop 1 modes ***
===============================
[..]
(+) Entry:
The Stop 0, Stop 1 modes are entered through the following API's:
(++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
(+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
(++) PWR_MAINREGULATOR_ON
(++) PWR_LOWPOWERREGULATOR_ON
(+) Exit (interrupt or event-triggered, specified when entering STOP mode):
(++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
(++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
(+) WFI Exit:
(++) Any EXTI Line (Internal or External) configured in Interrupt mode.
(++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
when programmed in wakeup mode.
(+) WFE Exit:
(++) Any EXTI Line (Internal or External) configured in Event mode.
[..]
When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
depending on the LPR bit setting.
*** Standby mode ***
====================
[..]
The Standby mode offers two options:
(+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
and Standby circuitry.
(+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
SRAM and register contents are lost except for the RTC registers, RTC backup registers
and Standby circuitry.
(++) Entry:
(+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API.
SRAM1 and register contents are lost except for registers in the Backup domain and
Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
to set RRS bit.
(++) Exit:
(+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
external reset in NRST pin, IWDG reset.
[..] After waking up from Standby mode, program execution restarts in the same way as after a Reset.
*** Shutdown mode ***
======================
[..]
In Shutdown mode,
voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
SRAM and registers contents are lost except for backup domain registers.
(+) Entry:
The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API.
(+) Exit:
(++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
external reset in NRST pin.
[..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
*** Auto-wakeup (AWU) from low-power mode ***
=============================================
[..]
The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
Wakeup event, a tamper event or a time-stamp event, without depending on
an external interrupt (Auto-wakeup mode).
(+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
is necessary to configure the RTC to detect the tamper or time stamp event using the
HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
(++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
@endverbatim
* @{
*/
/**
* @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
* @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD
* configuration information.
* @note Refer to the electrical characteristics of your device datasheet for
* more details about the voltage thresholds corresponding to each
* detection level.
* @retval None
*/
HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
{
/* Check the parameters */
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
/* Set PLS bits according to PVDLevel value */
MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
/* Clear any previous config. Keep it clear if no event or IT mode is selected */
__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
__HAL_PWR_PVD_EXTI_DISABLE_IT();
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
/* Configure interrupt mode */
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
{
__HAL_PWR_PVD_EXTI_ENABLE_IT();
}
/* Configure event mode */
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
{
__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
}
/* Configure the edge */
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
{
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
}
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
{
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
}
return HAL_OK;
}
/**
* @brief Enable the Power Voltage Detector (PVD).
* @retval None
*/
void HAL_PWR_EnablePVD(void)
{
SET_BIT(PWR->CR2, PWR_CR2_PVDE);
}
/**
* @brief Disable the Power Voltage Detector (PVD).
* @retval None
*/
void HAL_PWR_DisablePVD(void)
{
CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
}
/**
* @brief Enable the WakeUp PINx functionality.
* @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
* This parameter can be one of the following legacy values which set the default polarity
* i.e. detection on high level (rising edge):
* @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
*
* or one of the following value where the user can explicitly specify the enabled pin and
* the chosen polarity:
* @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
* @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
* @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
* @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
* @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
* @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
* @retval None
*/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
{
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
/* Specifies the Wake-Up pin polarity for the event detection
(rising or falling edge) */
MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
/* Enable wake-up pin */
SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
}
/**
* @brief Disable the WakeUp PINx functionality.
* @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
* This parameter can be one of the following values:
* @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
* @retval None
*/
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
{
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
}
/**
* @brief Enter Sleep or Low-power Sleep mode.
* @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
* @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
* This parameter can be one of the following values:
* @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
* @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
* @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
* in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
* to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
* Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
* Additionally, the clock frequency must be reduced below 2 MHz.
* Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
* be done before calling HAL_PWR_EnterSLEEPMode() API.
* @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
* Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
* @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
* @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
* @note When WFI entry is used, tick interrupt have to be disabled if not desired as
* the interrupt wake up source.
* @retval None
*/
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
{
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
/* Set Regulator parameter */
if (Regulator == PWR_MAINREGULATOR_ON)
{
/* If in low-power run mode at this point, exit it */
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
{
(void)HAL_PWREx_DisableLowPowerRunMode();
}
/* Regulator now in main mode. */
}
else
{
/* If in run mode, first move to low-power run mode.
The system clock frequency must be below 2 MHz at this point. */
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == 0U)
{
HAL_PWREx_EnableLowPowerRunMode();
}
}
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* Select SLEEP mode entry -------------------------------------------------*/
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__SEV();
__WFE();
__WFE();
}
}
/**
* @brief Enter Stop mode
* @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
* on devices where only "Stop mode" is mentioned with main or low power regulator ON.
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
* @note All clocks in the VCORE domain are stopped; the PLL,
* the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
* (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
* after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
* only to the peripheral requesting it.
* SRAM1, SRAM2 and register contents are preserved.
* The BOR is available.
* The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
* @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
* the HSI RC oscillator is selected as system clock.
* @note When the voltage regulator operates in low power mode (Stop 1), an additional
* startup delay is incurred when waking up.
* By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
* is higher although the startup time is reduced.
* @param Regulator: Specifies the regulator state in Stop mode.
* This parameter can be one of the following values:
* @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
* @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
* @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
* @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
* @retval None
*/
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
{
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
if(Regulator == PWR_LOWPOWERREGULATOR_ON)
{
HAL_PWREx_EnterSTOP1Mode(STOPEntry);
}
else
{
HAL_PWREx_EnterSTOP0Mode(STOPEntry);
}
}
/**
* @brief Enter Standby mode.
* @note In Standby mode, the PLL, the HSI and the HSE oscillators are switched
* off. The voltage regulator is disabled, except when SRAM2 content is preserved
* in which case the regulator is in low-power mode.
* SRAM1 and register contents are lost except for registers in the Backup domain and
* Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
* To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
* to set RRS bit.
* The BOR is available.
* @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
* HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
* Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
* same.
* These states are effective in Standby mode only if APC bit is set through
* HAL_PWREx_EnablePullUpPullDownConfig() API.
* @retval None
*/
void HAL_PWR_EnterSTANDBYMode(void)
{
/* Set Stand-by mode */
MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM)
__force_stores();
#endif
/* Request Wait For Interrupt */
__WFI();
}
/**
* @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
* re-enters SLEEP mode when an interruption handling is over.
* Setting this bit is useful when the processor is expected to run only on
* interruptions handling.
* @retval None
*/
void HAL_PWR_EnableSleepOnExit(void)
{
/* Set SLEEPONEXIT bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
* @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
* re-enters SLEEP mode when an interruption handling is over.
* @retval None
*/
void HAL_PWR_DisableSleepOnExit(void)
{
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Enable CORTEX M4 SEVONPEND bit.
* @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
* WFE to wake up when an interrupt moves from inactive to pended.
* @retval None
*/
void HAL_PWR_EnableSEVOnPend(void)
{
/* Set SEVONPEND bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @brief Disable CORTEX M4 SEVONPEND bit.
* @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
* WFE to wake up when an interrupt moves from inactive to pended.
* @retval None
*/
void HAL_PWR_DisableSEVOnPend(void)
{
/* Clear SEVONPEND bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @brief PWR PVD interrupt callback
* @retval None
*/
__weak void HAL_PWR_PVDCallback(void)
{
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_PWR_PVDCallback can be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_PWR_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

1182
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c
View File

File diff suppressed because it is too large Load Diff

1401
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c
View File

File diff suppressed because it is too large Load Diff

1825
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c
View File

File diff suppressed because it is too large Load Diff

8108
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c
View File

File diff suppressed because it is too large Load Diff

3701
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c
View File

File diff suppressed because it is too large Load Diff

1425
Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c
View File

File diff suppressed because it is too large Load Diff

3
PDU FT24 MCU.ioc
View File

@ -331,7 +331,8 @@ SH.S_TIM3_CH1.ConfNb=1
SH.S_TIM3_CH4.0=TIM3_CH4,PWM Generation4 CH4
SH.S_TIM3_CH4.ConfNb=1
TIM2.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2
TIM2.IPParameters=Channel-PWM Generation2 CH2
TIM2.IPParameters=Channel-PWM Generation2 CH2,Pulse-PWM Generation2 CH2
TIM2.Pulse-PWM\ Generation2\ CH2=0
TIM3.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
TIM3.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4
TIM3.IPParameters=Channel-PWM Generation4 CH4,Channel-PWM Generation1 CH1

BIN
PDU_FT23.pdf
View File

Binary file not shown.

6
STM32-for-VSCode.config.yaml
View File

@ -6,18 +6,18 @@
# - entry_2
# The project name
target: PDU_FT23
target: PDU_FT24_Code
# Can be C or C++
language: C
optimization: Og
# MCU settings
targetMCU: stm32g4x
targetMCU: stm32f3x
cpu: cortex-m4 # type of cpu e.g. cortex-m4
fpu: fpv4-sp-d16 # Defines how floating points are defined. Can be left empty.
floatAbi: -mfloat-abi=hard
ldscript: STM32G431CBTx_FLASH.ld # linker script
ldscript: STM32F302RBTx_FLASH.ld # linker script
# Compiler definitions. The -D prefix for the compiler will be automatically added.
cDefinitions: []

19460
STM32G031.svd
View File

File diff suppressed because it is too large Load Diff

189
STM32G431CBTx_FLASH.ld
View File

@ -1,189 +0,0 @@
/*
******************************************************************************
**
** File : LinkerScript.ld
**
** Author : STM32CubeMX
**
** Abstract : Linker script for STM32G431CBTx series
** 128Kbytes FLASH and 32Kbytes RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
** Target : STMicroelectronics STM32
**
** Distribution: The file is distributed “as is,” without any warranty
** of any kind.
**
*****************************************************************************
** @attention
**
** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** 1. Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** 2. Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** 3. Neither the name of STMicroelectronics nor the names of its contributors
** may be used to endorse or promote products derived from this software
** without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

6
STM32Make.make
View File

@ -13,7 +13,7 @@
######################################
# target
######################################
TARGET = PDU_FT23
TARGET = PDU_FT24_Code
######################################
@ -169,7 +169,7 @@ CXXFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
# LDFLAGS
#######################################
# link script
LDSCRIPT = STM32G431CBTx_FLASH.ld
LDSCRIPT = STM32F302RBTx_FLASH.ld
# libraries
LIBS = -lc -lm -lnosys
@ -242,7 +242,7 @@ flash: $(BUILD_DIR)/$(TARGET).elf
# erase
#######################################
erase: $(BUILD_DIR)/$(TARGET).elf
"C:/USERS/NIVED/APPDATA/ROAMING/CODE/USER/GLOBALSTORAGE/BMD.STM32-FOR-VSCODE/@XPACK-DEV-TOOLS/OPENOCD/0.12.0-2.1/.CONTENT/BIN/OPENOCD.EXE" -f ./openocd.cfg -c "init; reset halt; stm32g4x mass_erase 0; exit"
"C:/USERS/NIVED/APPDATA/ROAMING/CODE/USER/GLOBALSTORAGE/BMD.STM32-FOR-VSCODE/@XPACK-DEV-TOOLS/OPENOCD/0.12.0-2.1/.CONTENT/BIN/OPENOCD.EXE" -f ./openocd.cfg -c "init; reset halt; stm32f3x mass_erase 0; exit"
#######################################
# clean up

40
build/CAN_Communication.lst
View File

@ -1,4 +1,4 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s page 1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccbLt2aK.s page 1
1 .cpu cortex-m4
@ -58,7 +58,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s page 1
39 .loc 1 17 3 is_stmt 1 view .LVU2
40 0002 FFF7FEFF bl ftcan_init
41 .LVL1:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s page 2
ARM GAS C:\Users\nived\AppData\Local\Temp\ccbLt2aK.s page 2
18:Core/Src/CAN_Communication.c **** ftcan_add_filter(0x00, 0x00); // No Filter
@ -118,7 +118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s page 1
88 0016 8DF80220 strb r2, [sp, #2]
28:Core/Src/CAN_Communication.c **** status_data[3] = rxstate.radiatorfans;
89 .loc 1 28 3 is_stmt 1 view .LVU17
ARM GAS C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s page 3
ARM GAS C:\Users\nived\AppData\Local\Temp\ccbLt2aK.s page 3
90 .loc 1 28 27 is_stmt 0 view .LVU18
@ -178,7 +178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s page 1
55:Core/Src/CAN_Communication.c **** data[2] = current_measurements_adc_val.cooling_pump >> 8;
56:Core/Src/CAN_Communication.c **** data[3] = current_measurements_adc_val.cooling_pump & 0xFF;
57:Core/Src/CAN_Communication.c **** data[4] = current_measurements_adc_val.aggregat >> 8;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s page 4
ARM GAS C:\Users\nived\AppData\Local\Temp\ccbLt2aK.s page 4
58:Core/Src/CAN_Communication.c **** data[5] = current_measurements_adc_val.aggregat & 0xFF;
@ -238,7 +238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s page 1
133 .global ftcan_msg_received_cb
134 .syntax unified
135 .thumb
ARM GAS C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s page 5
ARM GAS C:\Users\nived\AppData\Local\Temp\ccbLt2aK.s page 5
136 .thumb_func
@ -298,7 +298,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s page 1
172 .loc 1 103 40 is_stmt 0 view .LVU44
173 001a 5178 ldrb r1, [r2, #1] @ zero_extendqisi2
103:Core/Src/CAN_Communication.c **** rxstate.radiatorfans = data[2];
ARM GAS C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s page 6
ARM GAS C:\Users\nived\AppData\Local\Temp\ccbLt2aK.s page 6
174 .loc 1 103 34 view .LVU45
@ -358,7 +358,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s page 1
216 canmsg_received:
217 0000 00 .space 1
218 .global rxstate
ARM GAS C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s page 7
ARM GAS C:\Users\nived\AppData\Local\Temp\ccbLt2aK.s page 7
219 .section .bss.rxstate,"aw",%nobits
@ -378,23 +378,23 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s page 1
234 .file 9 "Core/Inc/Channel_Control.h"
235 .file 10 "Core/Inc/CAN_Communication.h"
236 .file 11 "Core/Inc/can-halal.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s page 8
ARM GAS C:\Users\nived\AppData\Local\Temp\ccbLt2aK.s page 8
DEFINED SYMBOLS
*ABS*:00000000 CAN_Communication.c
C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s:21 .text.can_init:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s:27 .text.can_init:00000000 can_init
C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s:53 .text.can_sendloop:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s:59 .text.can_sendloop:00000000 can_sendloop
C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s:126 .text.can_sendloop:00000044 $d
C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s:223 .bss.rxstate:00000000 rxstate
C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s:132 .text.ftcan_msg_received_cb:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s:138 .text.ftcan_msg_received_cb:00000000 ftcan_msg_received_cb
C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s:207 .text.ftcan_msg_received_cb:00000034 $d
C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s:216 .bss.canmsg_received:00000000 canmsg_received
C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s:217 .bss.canmsg_received:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccWrmAuI.s:220 .bss.rxstate:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccbLt2aK.s:21 .text.can_init:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccbLt2aK.s:27 .text.can_init:00000000 can_init
C:\Users\nived\AppData\Local\Temp\ccbLt2aK.s:53 .text.can_sendloop:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccbLt2aK.s:59 .text.can_sendloop:00000000 can_sendloop
C:\Users\nived\AppData\Local\Temp\ccbLt2aK.s:126 .text.can_sendloop:00000044 $d
C:\Users\nived\AppData\Local\Temp\ccbLt2aK.s:223 .bss.rxstate:00000000 rxstate
C:\Users\nived\AppData\Local\Temp\ccbLt2aK.s:132 .text.ftcan_msg_received_cb:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccbLt2aK.s:138 .text.ftcan_msg_received_cb:00000000 ftcan_msg_received_cb
C:\Users\nived\AppData\Local\Temp\ccbLt2aK.s:207 .text.ftcan_msg_received_cb:00000034 $d
C:\Users\nived\AppData\Local\Temp\ccbLt2aK.s:216 .bss.canmsg_received:00000000 canmsg_received
C:\Users\nived\AppData\Local\Temp\ccbLt2aK.s:217 .bss.canmsg_received:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccbLt2aK.s:220 .bss.rxstate:00000000 $d
UNDEFINED SYMBOLS
ftcan_init

139
build/Channel_Control.lst
View File

@ -1,4 +1,4 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s page 1
ARM GAS C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s page 1
1 .cpu cortex-m4
@ -58,7 +58,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s page 1
27:Core/Src/Channel_Control.c **** PCA9535_setGPIOPortDirection(PC9535_PORTB, 0x00);
28:Core/Src/Channel_Control.c ****
29:Core/Src/Channel_Control.c **** EN_Ports.porta.porta = 0;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s page 2
ARM GAS C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s page 2
30:Core/Src/Channel_Control.c **** EN_Ports.portb.portb = 0;
@ -82,7 +82,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s page 1
40 .loc 1 37 12 is_stmt 0 view .LVU3
41 0002 0B4B ldr r3, .L3
42 0004 1880 strh r0, [r3] @ movhi
38:Core/Src/Channel_Control.c **** UpdatePorts.porta.alwayson = 1; // Always on stays always on
38:Core/Src/Channel_Control.c **** UpdatePorts.porta.alwayson = 1;// Always on stays always on
43 .loc 1 38 3 is_stmt 1 view .LVU4
44 .loc 1 38 30 is_stmt 0 view .LVU5
45 0006 40F08004 orr r4, r0, #128
@ -102,23 +102,23 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s page 1
57 .LVL3:
41:Core/Src/Channel_Control.c **** gpio_port_b testb={};
58 .loc 1 41 2 view .LVU9
42:Core/Src/Channel_Control.c **** testb.en14=1;
42:Core/Src/Channel_Control.c **** testb.en16=1;
59 .loc 1 42 2 view .LVU10
43:Core/Src/Channel_Control.c **** PCA9535_setGPIOPortOutput(PC9535_PORTB, testb.portb);
60 .loc 1 43 3 view .LVU11
61 001c 4021 movs r1, #64
43:Core/Src/Channel_Control.c **** PCA9535_setGPIOPortOutput(PC9535_PORTB, testb.portb);
60 .loc 1 43 2 view .LVU11
61 001c 8021 movs r1, #128
62 001e 0120 movs r0, #1
63 0020 FFF7FEFF bl PCA9535_setGPIOPortOutput
64 .LVL4:
44:Core/Src/Channel_Control.c **** gpio_port_a testa={};
65 .loc 1 44 3 view .LVU12
45:Core/Src/Channel_Control.c **** testa.en13=1;
45:Core/Src/Channel_Control.c **** testa.en1=1;
66 .loc 1 45 3 view .LVU13
46:Core/Src/Channel_Control.c **** PCA9535_setGPIOPortOutput(PC9535_PORTA, testa.porta);
67 .loc 1 46 3 view .LVU14
68 0024 0221 movs r1, #2
68 0024 0821 movs r1, #8
69 0026 0020 movs r0, #0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s page 3
ARM GAS C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s page 3
70 0028 FFF7FEFF bl PCA9535_setGPIOPortOutput
@ -178,7 +178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s page 1
114 .loc 1 24 3 is_stmt 1 view .LVU24
115 0010 0021 movs r1, #0
116 0012 0846 mov r0, r1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s page 4
ARM GAS C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s page 4
117 0014 FFF7FEFF bl PCA9535_setGPIOPortOutput
@ -238,7 +238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s page 1
159 .cfi_endproc
160 .LFE130:
162 .section .text.ChannelControl_UpdatePWMs,"ax",%progbits
ARM GAS C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s page 5
ARM GAS C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s page 5
163 .align 1
@ -257,50 +257,51 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s page 1
174 @ args = 0, pretend = 0, frame = 0
175 @ frame_needed = 0, uses_anonymous_args = 0
176 @ link register save eliminated.
53:Core/Src/Channel_Control.c **** return;
177 .loc 1 53 3 view .LVU38
54:Core/Src/Channel_Control.c ****
55:Core/Src/Channel_Control.c **** pwmtimer3->Instance->CCR4 = pwmpumps << 8;
56:Core/Src/Channel_Control.c **** pwmtimer3->Instance->CCR1 = radiatorfans << 8;
57:Core/Src/Channel_Control.c **** pwmtimer2->Instance->CCR2 = tsacfans << 8;
58:Core/Src/Channel_Control.c ****
59:Core/Src/Channel_Control.c **** if (timer3_running) {
60:Core/Src/Channel_Control.c **** if ((pwmpumps == 0) && (radiatorfans == 0)) {
61:Core/Src/Channel_Control.c **** timer3_running = 0;
62:Core/Src/Channel_Control.c **** HAL_TIM_PWM_Stop(pwmtimer3, TIM_CHANNEL_4);
63:Core/Src/Channel_Control.c **** HAL_TIM_PWM_Stop(pwmtimer3, TIM_CHANNEL_1);
64:Core/Src/Channel_Control.c **** }
65:Core/Src/Channel_Control.c **** } else {
66:Core/Src/Channel_Control.c **** if ( (pwmpumps != 0) || (radiatorfans != 0)) {
67:Core/Src/Channel_Control.c **** timer3_running = 1;
68:Core/Src/Channel_Control.c **** HAL_TIM_PWM_Start(pwmtimer3, TIM_CHANNEL_4);
69:Core/Src/Channel_Control.c **** HAL_TIM_PWM_Start(pwmtimer3, TIM_CHANNEL_1);
70:Core/Src/Channel_Control.c **** }
71:Core/Src/Channel_Control.c **** }
72:Core/Src/Channel_Control.c ****
73:Core/Src/Channel_Control.c **** if (timer2_running) {
74:Core/Src/Channel_Control.c **** if (tsacfans == 0) {
75:Core/Src/Channel_Control.c **** timer2_running = 0;
76:Core/Src/Channel_Control.c **** HAL_TIM_PWM_Stop(pwmtimer2, TIM_CHANNEL_2);
77:Core/Src/Channel_Control.c **** }
78:Core/Src/Channel_Control.c **** } else {
79:Core/Src/Channel_Control.c **** if (tsacfans != 0) {
80:Core/Src/Channel_Control.c **** timer2_running = 1;
81:Core/Src/Channel_Control.c **** HAL_TIM_PWM_Start(pwmtimer2, TIM_CHANNEL_2);
82:Core/Src/Channel_Control.c **** }
83:Core/Src/Channel_Control.c **** }
84:Core/Src/Channel_Control.c ****
53:Core/Src/Channel_Control.c ****
54:Core/Src/Channel_Control.c **** return;
177 .loc 1 54 3 view .LVU38
55:Core/Src/Channel_Control.c ****
56:Core/Src/Channel_Control.c **** pwmtimer3->Instance->CCR4 = pwmpumps << 8;
57:Core/Src/Channel_Control.c **** pwmtimer3->Instance->CCR1 = radiatorfans << 8;
58:Core/Src/Channel_Control.c **** pwmtimer2->Instance->CCR2 = tsacfans << 8;
59:Core/Src/Channel_Control.c ****
60:Core/Src/Channel_Control.c **** if (timer3_running) {
61:Core/Src/Channel_Control.c **** if ((pwmpumps == 0) && (radiatorfans == 0)) {
62:Core/Src/Channel_Control.c **** timer3_running = 0;
63:Core/Src/Channel_Control.c **** HAL_TIM_PWM_Stop(pwmtimer3, TIM_CHANNEL_4);
64:Core/Src/Channel_Control.c **** HAL_TIM_PWM_Stop(pwmtimer3, TIM_CHANNEL_1);
65:Core/Src/Channel_Control.c **** }
66:Core/Src/Channel_Control.c **** } else {
67:Core/Src/Channel_Control.c **** if ( (pwmpumps != 0) || (radiatorfans != 0)) {
68:Core/Src/Channel_Control.c **** timer3_running = 1;
69:Core/Src/Channel_Control.c **** HAL_TIM_PWM_Start(pwmtimer3, TIM_CHANNEL_4);
70:Core/Src/Channel_Control.c **** HAL_TIM_PWM_Start(pwmtimer3, TIM_CHANNEL_1);
71:Core/Src/Channel_Control.c **** }
72:Core/Src/Channel_Control.c **** }
73:Core/Src/Channel_Control.c ****
74:Core/Src/Channel_Control.c **** if (timer2_running) {
75:Core/Src/Channel_Control.c **** if (tsacfans == 0) {
76:Core/Src/Channel_Control.c **** timer2_running = 0;
77:Core/Src/Channel_Control.c **** HAL_TIM_PWM_Stop(pwmtimer2, TIM_CHANNEL_2);
78:Core/Src/Channel_Control.c **** }
79:Core/Src/Channel_Control.c **** } else {
80:Core/Src/Channel_Control.c **** if (tsacfans != 0) {
81:Core/Src/Channel_Control.c **** timer2_running = 1;
82:Core/Src/Channel_Control.c **** HAL_TIM_PWM_Start(pwmtimer2, TIM_CHANNEL_2);
83:Core/Src/Channel_Control.c **** }
84:Core/Src/Channel_Control.c **** }
85:Core/Src/Channel_Control.c ****
86:Core/Src/Channel_Control.c **** }
178 .loc 1 86 1 is_stmt 0 view .LVU39
86:Core/Src/Channel_Control.c ****
87:Core/Src/Channel_Control.c **** }
178 .loc 1 87 1 is_stmt 0 view .LVU39
179 0000 7047 bx lr
180 .cfi_endproc
181 .LFE132:
183 .global pwmtimer2
ARM GAS C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s page 6
184 .section .bss.pwmtimer2,"aw",%nobits
ARM GAS C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s page 6
185 .align 2
188 pwmtimer2:
189 0000 00000000 .space 4
@ -333,29 +334,29 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s page 1
224 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h"
225 .file 9 "Core/Inc/Channel_Control.h"
226 .file 10 "Core/Inc/PCA9535D_Driver.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s page 7
ARM GAS C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s page 7
DEFINED SYMBOLS
*ABS*:00000000 Channel_Control.c
C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s:21 .text.ChannelControl_UpdateGPIOs:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s:27 .text.ChannelControl_UpdateGPIOs:00000000 ChannelControl_UpdateGPIOs
C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s:77 .text.ChannelControl_UpdateGPIOs:00000030 $d
C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s:214 .bss.EN_Ports:00000000 EN_Ports
C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s:82 .text.ChannelControl_init:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s:88 .text.ChannelControl_init:00000000 ChannelControl_init
C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s:156 .text.ChannelControl_init:00000044 $d
C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s:195 .bss.pwmtimer3:00000000 pwmtimer3
C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s:188 .bss.pwmtimer2:00000000 pwmtimer2
C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s:163 .text.ChannelControl_UpdatePWMs:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s:169 .text.ChannelControl_UpdatePWMs:00000000 ChannelControl_UpdatePWMs
C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s:185 .bss.pwmtimer2:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s:192 .bss.pwmtimer3:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s:201 .bss.timer2_running:00000000 timer2_running
C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s:202 .bss.timer2_running:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s:207 .bss.timer3_running:00000000 timer3_running
C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s:208 .bss.timer3_running:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccG5EOIc.s:211 .bss.EN_Ports:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s:21 .text.ChannelControl_UpdateGPIOs:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s:27 .text.ChannelControl_UpdateGPIOs:00000000 ChannelControl_UpdateGPIOs
C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s:77 .text.ChannelControl_UpdateGPIOs:00000030 $d
C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s:214 .bss.EN_Ports:00000000 EN_Ports
C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s:82 .text.ChannelControl_init:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s:88 .text.ChannelControl_init:00000000 ChannelControl_init
C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s:156 .text.ChannelControl_init:00000044 $d
C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s:195 .bss.pwmtimer3:00000000 pwmtimer3
C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s:188 .bss.pwmtimer2:00000000 pwmtimer2
C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s:163 .text.ChannelControl_UpdatePWMs:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s:169 .text.ChannelControl_UpdatePWMs:00000000 ChannelControl_UpdatePWMs
C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s:185 .bss.pwmtimer2:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s:192 .bss.pwmtimer3:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s:201 .bss.timer2_running:00000000 timer2_running
C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s:202 .bss.timer2_running:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s:207 .bss.timer3_running:00000000 timer3_running
C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s:208 .bss.timer3_running:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc8T0p9d.s:211 .bss.EN_Ports:00000000 $d
UNDEFINED SYMBOLS
PCA9535_setGPIOPortOutput

78
build/Current_Monitoring.lst
View File

@ -1,4 +1,4 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 1
ARM GAS C:\Users\nived\AppData\Local\Temp\cc968GSL.s page 1
1 .cpu cortex-m4
@ -58,7 +58,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 1
27:Core/Src/Current_Monitoring.c **** struct {
28:Core/Src/Current_Monitoring.c **** uint16_t isense2; // ebs valve a and ebs valve b
29:Core/Src/Current_Monitoring.c **** uint16_t isense1; // ebs cs valve
ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 2
ARM GAS C:\Users\nived\AppData\Local\Temp\cc968GSL.s page 2
30:Core/Src/Current_Monitoring.c **** uint16_t isense10; // hyr aggregat
@ -118,7 +118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 1
63 001e 98F80020 ldrb r2, [r8] @ zero_extendqisi2
64 0022 4FF40051 mov r1, #8192
65 0026 3046 mov r0, r6
ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 3
ARM GAS C:\Users\nived\AppData\Local\Temp\cc968GSL.s page 3
66 0028 FFF7FEFF bl HAL_GPIO_WritePin
@ -167,9 +167,9 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 1
102 006c 2846 mov r0, r5
103 006e FFF7FEFF bl HAL_ADC_Start_DMA
104 .LVL10:
58:Core/Src/Current_Monitoring.c **** HAL_ADC_Start_DMA(hadc2, (uint32_t*)adc_channels2.adcbuffer, 4); // wie adc mit dma geht , red mi
58:Core/Src/Current_Monitoring.c **** HAL_ADC_Start_DMA(hadc2, (uint32_t*)adc_channels2.adcbuffer, 7); // wie adc mit dma geht , red mi
105 .loc 1 58 3 view .LVU16
106 0072 0422 movs r2, #4
106 0072 0722 movs r2, #7
107 0074 0649 ldr r1, .L3+16
108 0076 2046 mov r0, r4
109 0078 FFF7FEFF bl HAL_ADC_Start_DMA
@ -178,7 +178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 1
111 .loc 1 59 1 is_stmt 0 view .LVU17
112 007c BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc}
113 .LVL12:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 4
ARM GAS C:\Users\nived\AppData\Local\Temp\cc968GSL.s page 4
114 .L4:
@ -238,7 +238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 1
168 .cfi_offset 5, -8
169 .cfi_offset 14, -4
170 0002 0446 mov r4, r0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 5
ARM GAS C:\Users\nived\AppData\Local\Temp\cc968GSL.s page 5
64:Core/Src/Current_Monitoring.c **** if (hadc == adc2) {
@ -298,7 +298,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 1
100:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.always_on =
101:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense3 * CURR_SENSE_FACTOR_5A;
102:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.inverters =
ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 6
ARM GAS C:\Users\nived\AppData\Local\Temp\cc968GSL.s page 6
103:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense7 * CURR_SENSE_FACTOR_7_5A;
@ -358,7 +358,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 1
214 003e 9383 strh r3, [r2, #28] @ movhi
68:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense4 * CURR_SENSE_FACTOR_7_5A;
215 .loc 1 68 7 is_stmt 1 view .LVU38
ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 7
ARM GAS C:\Users\nived\AppData\Local\Temp\cc968GSL.s page 7
69:Core/Src/Current_Monitoring.c **** adcbank2 = GPIO_PIN_SET;
@ -418,7 +418,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 1
80:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense10 * CURR_SENSE_FACTOR_21A;
258 .loc 1 80 43 view .LVU51
259 009a FCEEE77A vcvt.u32.f32 s15, s15
ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 8
ARM GAS C:\Users\nived\AppData\Local\Temp\cc968GSL.s page 8
260 009e 17EE903A vmov r3, s15 @ int
@ -478,7 +478,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 1
74:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense4 * CURR_SENSE_FACTOR_7_5A;
304 .loc 1 74 45 view .LVU62
305 00f6 FCEEE77A vcvt.u32.f32 s15, s15
ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 9
ARM GAS C:\Users\nived\AppData\Local\Temp\cc968GSL.s page 9
306 00fa 17EE903A vmov r3, s15 @ int
@ -538,7 +538,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 1
347 .loc 1 93 40 view .LVU75
348 0146 FCEEE77A vcvt.u32.f32 s15, s15
349 014a 17EE903A vmov r3, s15 @ int
ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 10
ARM GAS C:\Users\nived\AppData\Local\Temp\cc968GSL.s page 10
350 014e 9382 strh r3, [r2, #20] @ movhi
@ -598,7 +598,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 1
391 019e 9FED3B7A vldr.32 s14, .L16+28
392 01a2 67EE877A vmul.f32 s15, s15, s14
110:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_21A;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 11
ARM GAS C:\Users\nived\AppData\Local\Temp\cc968GSL.s page 11
393 .loc 1 110 39 view .LVU89
@ -658,7 +658,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 1
436 .LVL24:
121:Core/Src/Current_Monitoring.c **** adcbank1);
437 .loc 1 121 5 view .LVU101
ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 12
ARM GAS C:\Users\nived\AppData\Local\Temp\cc968GSL.s page 12
438 0200 2A78 ldrb r2, [r5] @ zero_extendqisi2
@ -718,7 +718,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 1
481 0256 F8EEE77A vcvt.f32.s32 s15, s15
482 025a 67EE877A vmul.f32 s15, s15, s14
104:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense5 * CURR_SENSE_FACTOR_7_5A;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 13
ARM GAS C:\Users\nived\AppData\Local\Temp\cc968GSL.s page 13
483 .loc 1 104 41 view .LVU114
@ -778,7 +778,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 1
543 00000000
543 00000000
544 .global adc_channels2
ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 14
ARM GAS C:\Users\nived\AppData\Local\Temp\cc968GSL.s page 14
545 .section .bss.adc_channels2,"aw",%nobits
@ -807,33 +807,33 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 1
568 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h"
569 .file 11 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h"
570 .file 12 "Core/Inc/Current_Monitoring.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s page 15
ARM GAS C:\Users\nived\AppData\Local\Temp\cc968GSL.s page 15
DEFINED SYMBOLS
*ABS*:00000000 Current_Monitoring.c
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:21 .text.currentMonitor_init:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:27 .text.currentMonitor_init:00000000 currentMonitor_init
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:118 .text.currentMonitor_init:00000080 $d
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:523 .bss.adc1:00000000 adc1
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:516 .bss.adc2:00000000 adc2
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:556 .bss.adc_channels1:00000000 adc_channels1
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:549 .bss.adc_channels2:00000000 adc_channels2
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:529 .bss.adcbank2:00000000 adcbank2
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:535 .bss.adcbank1:00000000 adcbank1
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:129 .text.currentMonitor_checklimits:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:135 .text.currentMonitor_checklimits:00000000 currentMonitor_checklimits
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:150 .text.HAL_ADC_ConvCpltCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:156 .text.HAL_ADC_ConvCpltCallback:00000000 HAL_ADC_ConvCpltCallback
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:496 .text.HAL_ADC_ConvCpltCallback:00000270 $d
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:542 .bss.current_measurements_adc_val:00000000 current_measurements_adc_val
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:513 .bss.adc2:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:520 .bss.adc1:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:530 .bss.adcbank2:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:536 .bss.adcbank1:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:539 .bss.current_measurements_adc_val:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:546 .bss.adc_channels2:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccaFPxrf.s:553 .bss.adc_channels1:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:21 .text.currentMonitor_init:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:27 .text.currentMonitor_init:00000000 currentMonitor_init
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:118 .text.currentMonitor_init:00000080 $d
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:523 .bss.adc1:00000000 adc1
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:516 .bss.adc2:00000000 adc2
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:556 .bss.adc_channels1:00000000 adc_channels1
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:549 .bss.adc_channels2:00000000 adc_channels2
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:529 .bss.adcbank2:00000000 adcbank2
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:535 .bss.adcbank1:00000000 adcbank1
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:129 .text.currentMonitor_checklimits:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:135 .text.currentMonitor_checklimits:00000000 currentMonitor_checklimits
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:150 .text.HAL_ADC_ConvCpltCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:156 .text.HAL_ADC_ConvCpltCallback:00000000 HAL_ADC_ConvCpltCallback
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:496 .text.HAL_ADC_ConvCpltCallback:00000270 $d
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:542 .bss.current_measurements_adc_val:00000000 current_measurements_adc_val
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:513 .bss.adc2:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:520 .bss.adc1:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:530 .bss.adcbank2:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:536 .bss.adcbank1:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:539 .bss.current_measurements_adc_val:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:546 .bss.adc_channels2:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc968GSL.s:553 .bss.adc_channels1:00000000 $d
UNDEFINED SYMBOLS
HAL_GPIO_WritePin

134
build/PCA9535D_Driver.lst
View File

@ -1,4 +1,4 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 1
1 .cpu cortex-m4
@ -58,7 +58,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
27:Core/Src/PCA9535D_Driver.c **** * @retval none
28:Core/Src/PCA9535D_Driver.c **** */
29:Core/Src/PCA9535D_Driver.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 2
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 2
30:Core/Src/PCA9535D_Driver.c **** void PCA9535_init(I2C_HandleTypeDef* hi2c, uint8_t subadr) {
@ -118,7 +118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
77 @ sp needed
78 0042 10BD pop {r4, pc}
79 .LVL3:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 3
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 3
80 .L4:
@ -178,7 +178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
42:Core/Src/PCA9535D_Driver.c **** else
43:Core/Src/PCA9535D_Driver.c **** gpioa_shadow_reg_dir &= ~(1 << pin);
44:Core/Src/PCA9535D_Driver.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 4
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 4
45:Core/Src/PCA9535D_Driver.c **** uint8_t data[2] = {CONFIGURATION_REG_BASE_ADDRESS, gpioa_shadow_reg_dir};
@ -238,7 +238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
169 0044 5BB2 sxtb r3, r3
170 0046 1549 ldr r1, .L13
171 .LVL10:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 5
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 5
43:Core/Src/PCA9535D_Driver.c ****
@ -298,7 +298,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
55:Core/Src/PCA9535D_Driver.c **** }
212 .loc 1 55 5 is_stmt 1 view .LVU47
213 0070 4FF47A73 mov r3, #1000
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 6
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 6
214 0074 0093 str r3, [sp]
@ -358,7 +358,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
263 .thumb_func
265 PCA9535_setGPIOPinOutput:
266 .LVL20:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 7
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 7
267 .LFB132:
@ -418,7 +418,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
311 002c 0978 ldrb r1, [r1] @ zero_extendqisi2
312 002e 1C48 ldr r0, .L23+8
313 .LVL23:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 8
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 8
314 .loc 1 67 5 is_stmt 0 view .LVU69
@ -478,7 +478,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
68:Core/Src/PCA9535D_Driver.c **** } else if (Port == PC9535_PORTB) {
351 .loc 1 68 13 is_stmt 0 view .LVU78
352 004e 0128 cmp r0, #1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 9
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 9
353 0050 F1D1 bne .L15
@ -538,7 +538,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
396 .L20:
397 .LBB9:
72:Core/Src/PCA9535D_Driver.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 10
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 10
398 .loc 1 72 7 is_stmt 1 view .LVU91
@ -598,7 +598,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
447 0004 20BB cbnz r0, .L26
448 .LBB10:
81:Core/Src/PCA9535D_Driver.c **** if (state)
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 11
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 11
449 .loc 1 81 5 is_stmt 1 view .LVU100
@ -658,7 +658,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
97:Core/Src/PCA9535D_Driver.c **** HAL_I2C_Master_Transmit(pcai2c, deviceadr, data, 2, 1000);
98:Core/Src/PCA9535D_Driver.c **** }
99:Core/Src/PCA9535D_Driver.c **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 12
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 12
488 .loc 1 99 1 view .LVU111
@ -718,7 +718,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
91:Core/Src/PCA9535D_Driver.c **** else
530 .loc 1 91 34 view .LVU124
531 0058 8A40 lsls r2, r2, r1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 13
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 13
91:Core/Src/PCA9535D_Driver.c **** else
@ -778,7 +778,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
576 0092 0A78 ldrb r2, [r1] @ zero_extendqisi2
577 .LVL51:
93:Core/Src/PCA9535D_Driver.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 14
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 14
578 .loc 1 93 28 view .LVU136
@ -838,7 +838,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
109:Core/Src/PCA9535D_Driver.c ****
110:Core/Src/PCA9535D_Driver.c **** uint8_t reval = 0;
625 .loc 1 110 3 is_stmt 1 view .LVU143
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 15
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 15
626 .loc 1 110 11 is_stmt 0 view .LVU144
@ -898,7 +898,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
671 0050 0093 str r3, [sp]
672 0052 0123 movs r3, #1
673 0054 0DF10E02 add r2, sp, #14
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 16
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 16
674 0058 0A49 ldr r1, .L41
@ -958,7 +958,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
721 .thumb
722 .thumb_func
724 PCA9535_setGPIOPortDirection:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 17
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 17
725 .LVL63:
@ -1018,7 +1018,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
768 .LVL66:
128:Core/Src/PCA9535D_Driver.c **** }
769 .loc 1 128 1 view .LVU178
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 18
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 18
770 0030 05B0 add sp, sp, #20
@ -1078,7 +1078,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
818 .cfi_offset 14, -4
819 0002 85B0 sub sp, sp, #20
820 .cfi_def_cfa_offset 24
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 19
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 19
131:Core/Src/PCA9535D_Driver.c **** uint8_t command[2] = {0x00, bitmask};
@ -1138,7 +1138,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
863 .loc 1 135 13 is_stmt 0 view .LVU200
864 0036 0128 cmp r0, #1
865 0038 EFD1 bne .L51
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 20
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 20
136:Core/Src/PCA9535D_Driver.c **** command[0] = OUTPUT_REG_BASE_ADDRESS | 1;
@ -1198,7 +1198,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
913 .loc 1 145 5 is_stmt 1 view .LVU211
914 .loc 1 145 26 is_stmt 0 view .LVU212
915 0010 0D4B ldr r3, .L59
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 21
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 21
916 0012 1970 strb r1, [r3]
@ -1258,7 +1258,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
957 0040 8DF80C30 strb r3, [sp, #12]
958 0044 E9E7 b .L57
959 .L60:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 22
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 22
960 0046 00BF .align 2
@ -1318,7 +1318,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
161:Core/Src/PCA9535D_Driver.c ****
162:Core/Src/PCA9535D_Driver.c **** HAL_I2C_Master_Transmit(pcai2c, deviceadr, &command, 1, 1000);
1008 .loc 1 162 3 is_stmt 1 view .LVU235
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 23
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 23
1009 0016 0D4D ldr r5, .L64
@ -1378,7 +1378,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
1067 0000 FF .byte -1
1068 .section .bss.gpiob_shadow_reg_out,"aw",%nobits
1071 gpiob_shadow_reg_out:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 24
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 24
1072 0000 00 .space 1
@ -1406,53 +1406,53 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 1
1099 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h"
1100 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h"
1101 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s page 25
ARM GAS C:\Users\nived\AppData\Local\Temp\cc91uOuO.s page 25
DEFINED SYMBOLS
*ABS*:00000000 PCA9535D_Driver.c
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:21 .text.PCA9535_init:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:27 .text.PCA9535_init:00000000 PCA9535_init
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:84 .text.PCA9535_init:00000044 $d
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:1087 .bss.pcai2c:00000000 pcai2c
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:1081 .bss.deviceadr:00000000 deviceadr
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:91 .text.PCA9535_setGPIOPinDirection:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:97 .text.PCA9535_setGPIOPinDirection:00000000 PCA9535_setGPIOPinDirection
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:250 .text.PCA9535_setGPIOPinDirection:0000009c $d
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:1066 .data.gpioa_shadow_reg_dir:00000000 gpioa_shadow_reg_dir
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:1061 .data.gpiob_shadow_reg_dir:00000000 gpiob_shadow_reg_dir
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:259 .text.PCA9535_setGPIOPinOutput:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:265 .text.PCA9535_setGPIOPinOutput:00000000 PCA9535_setGPIOPinOutput
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:417 .text.PCA9535_setGPIOPinOutput:00000098 $d
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:1076 .bss.gpioa_shadow_reg_out:00000000 gpioa_shadow_reg_out
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:1071 .bss.gpiob_shadow_reg_out:00000000 gpiob_shadow_reg_out
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:426 .text.PCA9535_invertGPIOPinPolarity:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:432 .text.PCA9535_invertGPIOPinPolarity:00000000 PCA9535_invertGPIOPinPolarity
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:585 .text.PCA9535_invertGPIOPinPolarity:0000009c $d
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:1056 .bss.gpioa_shadow_reg_inv:00000000 gpioa_shadow_reg_inv
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:1051 .bss.gpiob_shadow_reg_inv:00000000 gpiob_shadow_reg_inv
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:594 .text.PCA9535_readGPIOPinInput:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:600 .text.PCA9535_readGPIOPinInput:00000000 PCA9535_readGPIOPinInput
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:711 .text.PCA9535_readGPIOPinInput:00000084 $d
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:718 .text.PCA9535_setGPIOPortDirection:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:724 .text.PCA9535_setGPIOPortDirection:00000000 PCA9535_setGPIOPortDirection
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:794 .text.PCA9535_setGPIOPortDirection:00000048 $d
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:802 .text.PCA9535_setGPIOPortOutput:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:808 .text.PCA9535_setGPIOPortOutput:00000000 PCA9535_setGPIOPortOutput
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:878 .text.PCA9535_setGPIOPortOutput:00000048 $d
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:886 .text.PCA9535_invertGPIOPortPolarity:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:892 .text.PCA9535_invertGPIOPortPolarity:00000000 PCA9535_invertGPIOPortPolarity
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:962 .text.PCA9535_invertGPIOPortPolarity:00000048 $d
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:970 .text.PCA9535_readGPIOPortInput:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:976 .text.PCA9535_readGPIOPortInput:00000000 PCA9535_readGPIOPortInput
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:1043 .text.PCA9535_readGPIOPortInput:0000004c $d
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:1052 .bss.gpiob_shadow_reg_inv:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:1057 .bss.gpioa_shadow_reg_inv:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:1072 .bss.gpiob_shadow_reg_out:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:1077 .bss.gpioa_shadow_reg_out:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:1082 .bss.deviceadr:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:1084 .bss.pcai2c:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccYA9Eni.s:1090 .rodata:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:21 .text.PCA9535_init:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:27 .text.PCA9535_init:00000000 PCA9535_init
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:84 .text.PCA9535_init:00000044 $d
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:1087 .bss.pcai2c:00000000 pcai2c
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:1081 .bss.deviceadr:00000000 deviceadr
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:91 .text.PCA9535_setGPIOPinDirection:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:97 .text.PCA9535_setGPIOPinDirection:00000000 PCA9535_setGPIOPinDirection
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:250 .text.PCA9535_setGPIOPinDirection:0000009c $d
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:1066 .data.gpioa_shadow_reg_dir:00000000 gpioa_shadow_reg_dir
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:1061 .data.gpiob_shadow_reg_dir:00000000 gpiob_shadow_reg_dir
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:259 .text.PCA9535_setGPIOPinOutput:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:265 .text.PCA9535_setGPIOPinOutput:00000000 PCA9535_setGPIOPinOutput
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:417 .text.PCA9535_setGPIOPinOutput:00000098 $d
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:1076 .bss.gpioa_shadow_reg_out:00000000 gpioa_shadow_reg_out
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:1071 .bss.gpiob_shadow_reg_out:00000000 gpiob_shadow_reg_out
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:426 .text.PCA9535_invertGPIOPinPolarity:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:432 .text.PCA9535_invertGPIOPinPolarity:00000000 PCA9535_invertGPIOPinPolarity
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:585 .text.PCA9535_invertGPIOPinPolarity:0000009c $d
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:1056 .bss.gpioa_shadow_reg_inv:00000000 gpioa_shadow_reg_inv
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:1051 .bss.gpiob_shadow_reg_inv:00000000 gpiob_shadow_reg_inv
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:594 .text.PCA9535_readGPIOPinInput:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:600 .text.PCA9535_readGPIOPinInput:00000000 PCA9535_readGPIOPinInput
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:711 .text.PCA9535_readGPIOPinInput:00000084 $d
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:718 .text.PCA9535_setGPIOPortDirection:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:724 .text.PCA9535_setGPIOPortDirection:00000000 PCA9535_setGPIOPortDirection
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:794 .text.PCA9535_setGPIOPortDirection:00000048 $d
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:802 .text.PCA9535_setGPIOPortOutput:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:808 .text.PCA9535_setGPIOPortOutput:00000000 PCA9535_setGPIOPortOutput
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:878 .text.PCA9535_setGPIOPortOutput:00000048 $d
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:886 .text.PCA9535_invertGPIOPortPolarity:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:892 .text.PCA9535_invertGPIOPortPolarity:00000000 PCA9535_invertGPIOPortPolarity
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:962 .text.PCA9535_invertGPIOPortPolarity:00000048 $d
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:970 .text.PCA9535_readGPIOPortInput:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:976 .text.PCA9535_readGPIOPortInput:00000000 PCA9535_readGPIOPortInput
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:1043 .text.PCA9535_readGPIOPortInput:0000004c $d
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:1052 .bss.gpiob_shadow_reg_inv:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:1057 .bss.gpioa_shadow_reg_inv:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:1072 .bss.gpiob_shadow_reg_out:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:1077 .bss.gpioa_shadow_reg_out:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:1082 .bss.deviceadr:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:1084 .bss.pcai2c:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc91uOuO.s:1090 .rodata:00000000 $d
UNDEFINED SYMBOLS
HAL_I2C_Master_Transmit

BIN
build/PDU_FT23.bin
View File

Binary file not shown.

BIN
build/PDU_FT24_Code.bin Normal file
View File

Binary file not shown.

96
build/can-halal.lst
View File

@ -1,4 +1,4 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLn44vU.s page 1
1 .cpu cortex-m4
@ -58,7 +58,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 1
44 .loc 1 12 7 is_stmt 0 view .LVU5
45 0006 0221 movs r1, #2
46 0008 FFF7FEFF bl HAL_CAN_ActivateNotification
ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 2
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLn44vU.s page 2
47 .LVL1:
@ -118,7 +118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 1
90 0002 83B0 sub sp, sp, #12
91 .cfi_def_cfa_offset 16
92 0004 8C46 mov ip, r1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 3
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLn44vU.s page 3
22:Core/Src/can-halal.c **** static CAN_TxHeaderTypeDef header;
@ -178,7 +178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 1
140 .thumb
141 .thumb_func
143 ftcan_add_filter:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 4
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLn44vU.s page 4
144 .LVL9:
@ -238,7 +238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 1
44:Core/Src/can-halal.c **** filter.FilterFIFOAssignment = CAN_FILTER_FIFO0;
184 .loc 1 44 3 is_stmt 1 view .LVU48
185 .loc 1 44 31 is_stmt 0 view .LVU49
ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 5
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLn44vU.s page 5
186 001a 124A ldr r2, .L18+4
@ -298,7 +298,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 1
42:Core/Src/can-halal.c **** }
216 .loc 1 42 28 view .LVU62
217 0034 D160 str r1, [r2, #12]
ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 6
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLn44vU.s page 6
218 0036 F0E7 b .L13
@ -358,7 +358,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 1
258 0068 00000000 .word hcan
259 .cfi_endproc
260 .LFE132:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 7
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLn44vU.s page 7
262 .section .text.ftcan_msg_received_cb,"ax",%progbits
@ -418,7 +418,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 1
109:Core/Src/can-halal.c **** switch (datalen) {
110:Core/Src/can-halal.c **** case 0:
111:Core/Src/can-halal.c **** header.DataLength = FDCAN_DLC_BYTES_0;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 8
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLn44vU.s page 8
112:Core/Src/can-halal.c **** break;
@ -478,7 +478,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 1
166:Core/Src/can-halal.c **** }
167:Core/Src/can-halal.c **** return status;
168:Core/Src/can-halal.c **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 9
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLn44vU.s page 9
169:Core/Src/can-halal.c ****
@ -538,7 +538,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 1
223:Core/Src/can-halal.c **** #endif
224:Core/Src/can-halal.c ****
225:Core/Src/can-halal.c **** __weak void ftcan_msg_received_cb(uint16_t id, size_t datalen,
ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 10
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLn44vU.s page 10
226:Core/Src/can-halal.c **** const uint8_t *data) {}
@ -598,7 +598,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 1
69:Core/Src/can-halal.c **** uint8_t data[8];
321 .loc 1 69 3 is_stmt 1 view .LVU85
70:Core/Src/can-halal.c **** if (HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &header, data) != HAL_OK) {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 11
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLn44vU.s page 11
322 .loc 1 70 3 view .LVU86
@ -658,7 +658,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 1
368 @ args = 0, pretend = 0, frame = 0
369 @ frame_needed = 0, uses_anonymous_args = 0
370 .loc 1 228 79 is_stmt 0 view .LVU96
ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 12
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLn44vU.s page 12
371 0000 10B5 push {r4, lr}
@ -718,7 +718,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 1
414 .loc 1 237 19 is_stmt 0 discriminator 3 view .LVU113
415 0020 E25C ldrb r2, [r4, r3] @ zero_extendqisi2
416 .loc 1 237 12 discriminator 3 view .LVU114
ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 13
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLn44vU.s page 13
417 0022 42EA0020 orr r0, r2, r0, lsl #8
@ -778,7 +778,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 1
245:Core/Src/can-halal.c **** num_bytes = 8;
464 .loc 1 245 15 view .LVU126
465 0008 0824 movs r4, #8
ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 14
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLn44vU.s page 14
466 .L35:
@ -838,7 +838,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 1
509 .loc 1 256 1 view .LVU140
510 0052 1941 asrs r1, r1, r3
511 0054 10BD pop {r4, pc}
ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 15
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLn44vU.s page 15
512 .cfi_endproc
@ -898,7 +898,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 1
559 .LVL46:
560 .loc 1 265 9 discriminator 3 view .LVU154
561 0012 42EA0362 orr r2, r2, r3, lsl #24
ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 16
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLn44vU.s page 16
562 0016 1B0A lsrs r3, r3, #8
@ -958,7 +958,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 1
608 .loc 1 272 10 is_stmt 0 view .LVU165
609 0004 0499 ldr r1, [sp, #16]
610 0006 0091 str r1, [sp]
ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 17
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLn44vU.s page 17
611 0008 FFF7FEFF bl ftcan_marshal_unsigned
@ -1005,41 +1005,41 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 1
652 .file 6 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
653 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h"
654 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s page 18
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLn44vU.s page 18
DEFINED SYMBOLS
*ABS*:00000000 can-halal.c
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:21 .text.ftcan_init:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:27 .text.ftcan_init:00000000 ftcan_init
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:68 .text.ftcan_init:0000001c $d
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:644 .bss.hcan:00000000 hcan
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:73 .text.ftcan_transmit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:79 .text.ftcan_transmit:00000000 ftcan_transmit
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:131 .text.ftcan_transmit:00000024 $d
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:638 .bss.header.2:00000000 header.2
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:137 .text.ftcan_add_filter:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:143 .text.ftcan_add_filter:00000000 ftcan_add_filter
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:256 .text.ftcan_add_filter:00000060 $d
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:632 .bss.next_filter_no.1:00000000 next_filter_no.1
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:626 .bss.filter.0:00000000 filter.0
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:263 .text.ftcan_msg_received_cb:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:269 .text.ftcan_msg_received_cb:00000000 ftcan_msg_received_cb
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:283 .text.HAL_CAN_RxFifo0MsgPendingCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:289 .text.HAL_CAN_RxFifo0MsgPendingCallback:00000000 HAL_CAN_RxFifo0MsgPendingCallback
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:352 .text.HAL_CAN_RxFifo0MsgPendingCallback:00000034 $d
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:357 .text.ftcan_unmarshal_unsigned:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:363 .text.ftcan_unmarshal_unsigned:00000000 ftcan_unmarshal_unsigned
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:441 .text.ftcan_unmarshal_signed:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:447 .text.ftcan_unmarshal_signed:00000000 ftcan_unmarshal_signed
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:516 .text.ftcan_marshal_unsigned:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:522 .text.ftcan_marshal_unsigned:00000000 ftcan_marshal_unsigned
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:588 .text.ftcan_marshal_signed:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:594 .text.ftcan_marshal_signed:00000000 ftcan_marshal_signed
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:623 .bss.filter.0:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:629 .bss.next_filter_no.1:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:635 .bss.header.2:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccs4JhW6.s:641 .bss.hcan:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:21 .text.ftcan_init:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:27 .text.ftcan_init:00000000 ftcan_init
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:68 .text.ftcan_init:0000001c $d
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:644 .bss.hcan:00000000 hcan
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:73 .text.ftcan_transmit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:79 .text.ftcan_transmit:00000000 ftcan_transmit
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:131 .text.ftcan_transmit:00000024 $d
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:638 .bss.header.2:00000000 header.2
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:137 .text.ftcan_add_filter:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:143 .text.ftcan_add_filter:00000000 ftcan_add_filter
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:256 .text.ftcan_add_filter:00000060 $d
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:632 .bss.next_filter_no.1:00000000 next_filter_no.1
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:626 .bss.filter.0:00000000 filter.0
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:263 .text.ftcan_msg_received_cb:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:269 .text.ftcan_msg_received_cb:00000000 ftcan_msg_received_cb
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:283 .text.HAL_CAN_RxFifo0MsgPendingCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:289 .text.HAL_CAN_RxFifo0MsgPendingCallback:00000000 HAL_CAN_RxFifo0MsgPendingCallback
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:352 .text.HAL_CAN_RxFifo0MsgPendingCallback:00000034 $d
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:357 .text.ftcan_unmarshal_unsigned:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:363 .text.ftcan_unmarshal_unsigned:00000000 ftcan_unmarshal_unsigned
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:441 .text.ftcan_unmarshal_signed:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:447 .text.ftcan_unmarshal_signed:00000000 ftcan_unmarshal_signed
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:516 .text.ftcan_marshal_unsigned:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:522 .text.ftcan_marshal_unsigned:00000000 ftcan_marshal_unsigned
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:588 .text.ftcan_marshal_signed:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:594 .text.ftcan_marshal_signed:00000000 ftcan_marshal_signed
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:623 .bss.filter.0:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:629 .bss.next_filter_no.1:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:635 .bss.header.2:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccLn44vU.s:641 .bss.hcan:00000000 $d
UNDEFINED SYMBOLS
HAL_CAN_ActivateNotification

3793
build/main.lst
View File

File diff suppressed because it is too large Load Diff

202
build/stm32f3xx_hal.lst
View File

@ -1,4 +1,4 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 1
1 .cpu cortex-m4
@ -58,7 +58,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) HAL Initialization and de-initialization functions
29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) HAL Control functions
30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 2
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 2
31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** @endverbatim
@ -118,7 +118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** @defgroup HAL_Exported_Functions HAL Exported Functions
86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @{
87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 3
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 3
88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c ****
@ -178,7 +178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #endif /* PREFETCH_ENABLE */
144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 4
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 4
145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Set Interrupt Group Priority */
@ -238,7 +238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
36 .cfi_endproc
37 .LFE132:
39 .section .text.HAL_MspDeInit,"ax",%progbits
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 5
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 5
40 .align 1
@ -298,7 +298,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
82 .loc 1 169 3 view .LVU7
83 000e DA60 str r2, [r3, #12]
170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 6
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 6
84 .loc 1 170 3 view .LVU8
@ -358,7 +358,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
116 @ args = 0, pretend = 0, frame = 0
117 @ frame_needed = 0, uses_anonymous_args = 0
118 .loc 1 221 1 is_stmt 0 view .LVU15
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 7
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 7
119 0000 10B5 push {r4, lr}
@ -418,7 +418,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
155 .loc 1 232 16 is_stmt 0 view .LVU26
156 0032 054B ldr r3, .L13+8
157 0034 1C60 str r4, [r3]
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 8
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 8
237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** }
@ -478,7 +478,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
205 000e FFF7FEFF bl HAL_MspInit
206 .LVL8:
155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 9
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 9
207 .loc 1 155 3 view .LVU36
@ -538,7 +538,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
223 .loc 1 279 1 is_stmt 1 view -0
224 .cfi_startproc
225 @ args = 0, pretend = 0, frame = 0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 10
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 10
226 @ frame_needed = 0, uses_anonymous_args = 0
@ -598,7 +598,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
269 0008 00000000 .word uwTick
270 .cfi_endproc
271 .LFE136:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 11
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 11
273 .section .text.HAL_GetTickPrio,"ax",%progbits
@ -658,7 +658,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
314 0000 10B5 push {r4, lr}
315 .cfi_def_cfa_offset 8
316 .cfi_offset 4, -8
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 12
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 12
317 .cfi_offset 14, -4
@ -718,7 +718,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c ****
342 .loc 1 323 5 is_stmt 1 view .LVU63
323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 13
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 13
343 .loc 1 323 14 is_stmt 0 view .LVU64
@ -778,7 +778,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
384 0002 1878 ldrb r0, [r3] @ zero_extendqisi2
385 0004 7047 bx lr
386 .L35:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 14
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 14
387 0006 00BF .align 2
@ -838,7 +838,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
424 .loc 1 362 6 is_stmt 0 view .LVU80
425 000a B4F1FF3F cmp r4, #-1
426 000e 02D0 beq .L38
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 15
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 15
363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** {
@ -898,7 +898,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * is suspended.
378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other
379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * implementations in user file.
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 16
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 16
380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None
@ -958,7 +958,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
497 .loc 1 403 10 is_stmt 0 view .LVU98
498 0000 4FF0E022 mov r2, #-536813568
499 0004 1369 ldr r3, [r2, #16]
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 17
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 17
500 .loc 1 403 18 view .LVU99
@ -1018,7 +1018,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t HAL_GetREVID(void)
421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** {
542 .loc 1 421 1 is_stmt 1 view -0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 18
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 18
543 .cfi_startproc
@ -1078,7 +1078,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
589 .section .text.HAL_GetUIDw0,"ax",%progbits
590 .align 1
591 .global HAL_GetUIDw0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 19
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 19
592 .syntax unified
@ -1138,7 +1138,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
631 0000 014B ldr r3, .L57
632 0002 D3F8B007 ldr r0, [r3, #1968]
633 0006 7047 bx lr
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 20
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 20
634 .L58:
@ -1198,7 +1198,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
676 .loc 1 466 1 is_stmt 1 view -0
677 .cfi_startproc
678 @ args = 0, pretend = 0, frame = 0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 21
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 21
679 @ frame_needed = 0, uses_anonymous_args = 0
@ -1258,7 +1258,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
725 .global HAL_DBGMCU_EnableDBGStopMode
726 .syntax unified
727 .thumb
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 22
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 22
728 .thumb_func
@ -1318,7 +1318,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
768 0004 23F00203 bic r3, r3, #2
769 0008 5360 str r3, [r2, #4]
495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 23
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 23
770 .loc 1 495 1 is_stmt 0 view .LVU132
@ -1378,7 +1378,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None
509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */
510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** void HAL_DBGMCU_DisableDBGStandbyMode(void)
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 24
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 24
511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** {
@ -1426,89 +1426,89 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 1
862 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h"
863 .file 8 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h"
864 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 25
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 25
DEFINED SYMBOLS
*ABS*:00000000 stm32f3xx_hal.c
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:21 .text.HAL_MspInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:27 .text.HAL_MspInit:00000000 HAL_MspInit
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:40 .text.HAL_MspDeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:46 .text.HAL_MspDeInit:00000000 HAL_MspDeInit
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:59 .text.HAL_DeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:65 .text.HAL_DeInit:00000000 HAL_DeInit
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:100 .text.HAL_DeInit:00000020 $d
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:105 .text.HAL_InitTick:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:111 .text.HAL_InitTick:00000000 HAL_InitTick
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:173 .text.HAL_InitTick:00000040 $d
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:839 .data.uwTickFreq:00000000 uwTickFreq
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:846 .data.uwTickPrio:00000000 uwTickPrio
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:180 .text.HAL_Init:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:186 .text.HAL_Init:00000000 HAL_Init
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:215 .text.HAL_IncTick:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:221 .text.HAL_IncTick:00000000 HAL_IncTick
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:241 .text.HAL_IncTick:00000010 $d
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:853 .bss.uwTick:00000000 uwTick
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:247 .text.HAL_GetTick:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:253 .text.HAL_GetTick:00000000 HAL_GetTick
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:269 .text.HAL_GetTick:00000008 $d
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:274 .text.HAL_GetTickPrio:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:280 .text.HAL_GetTickPrio:00000000 HAL_GetTickPrio
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:295 .text.HAL_GetTickPrio:00000008 $d
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:300 .text.HAL_SetTickFreq:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:306 .text.HAL_SetTickFreq:00000000 HAL_SetTickFreq
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:362 .text.HAL_SetTickFreq:00000024 $d
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:368 .text.HAL_GetTickFreq:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:374 .text.HAL_GetTickFreq:00000000 HAL_GetTickFreq
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:389 .text.HAL_GetTickFreq:00000008 $d
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:394 .text.HAL_Delay:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:400 .text.HAL_Delay:00000000 HAL_Delay
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:452 .text.HAL_Delay:00000024 $d
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:457 .text.HAL_SuspendTick:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:463 .text.HAL_SuspendTick:00000000 HAL_SuspendTick
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:483 .text.HAL_ResumeTick:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:489 .text.HAL_ResumeTick:00000000 HAL_ResumeTick
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:509 .text.HAL_GetHalVersion:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:515 .text.HAL_GetHalVersion:00000000 HAL_GetHalVersion
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:529 .text.HAL_GetHalVersion:00000004 $d
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:534 .text.HAL_GetREVID:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:540 .text.HAL_GetREVID:00000000 HAL_GetREVID
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:557 .text.HAL_GetREVID:00000008 $d
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:562 .text.HAL_GetDEVID:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:568 .text.HAL_GetDEVID:00000000 HAL_GetDEVID
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:585 .text.HAL_GetDEVID:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:590 .text.HAL_GetUIDw0:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:596 .text.HAL_GetUIDw0:00000000 HAL_GetUIDw0
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:611 .text.HAL_GetUIDw0:00000008 $d
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:616 .text.HAL_GetUIDw1:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:622 .text.HAL_GetUIDw1:00000000 HAL_GetUIDw1
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:637 .text.HAL_GetUIDw1:00000008 $d
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:642 .text.HAL_GetUIDw2:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:648 .text.HAL_GetUIDw2:00000000 HAL_GetUIDw2
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:663 .text.HAL_GetUIDw2:00000008 $d
ARM GAS C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s page 26
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:21 .text.HAL_MspInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:27 .text.HAL_MspInit:00000000 HAL_MspInit
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:40 .text.HAL_MspDeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:46 .text.HAL_MspDeInit:00000000 HAL_MspDeInit
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:59 .text.HAL_DeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:65 .text.HAL_DeInit:00000000 HAL_DeInit
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:100 .text.HAL_DeInit:00000020 $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:105 .text.HAL_InitTick:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:111 .text.HAL_InitTick:00000000 HAL_InitTick
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:173 .text.HAL_InitTick:00000040 $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:839 .data.uwTickFreq:00000000 uwTickFreq
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:846 .data.uwTickPrio:00000000 uwTickPrio
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:180 .text.HAL_Init:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:186 .text.HAL_Init:00000000 HAL_Init
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:215 .text.HAL_IncTick:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:221 .text.HAL_IncTick:00000000 HAL_IncTick
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:241 .text.HAL_IncTick:00000010 $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:853 .bss.uwTick:00000000 uwTick
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:247 .text.HAL_GetTick:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:253 .text.HAL_GetTick:00000000 HAL_GetTick
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:269 .text.HAL_GetTick:00000008 $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:274 .text.HAL_GetTickPrio:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:280 .text.HAL_GetTickPrio:00000000 HAL_GetTickPrio
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:295 .text.HAL_GetTickPrio:00000008 $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:300 .text.HAL_SetTickFreq:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:306 .text.HAL_SetTickFreq:00000000 HAL_SetTickFreq
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:362 .text.HAL_SetTickFreq:00000024 $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:368 .text.HAL_GetTickFreq:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:374 .text.HAL_GetTickFreq:00000000 HAL_GetTickFreq
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:389 .text.HAL_GetTickFreq:00000008 $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:394 .text.HAL_Delay:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:400 .text.HAL_Delay:00000000 HAL_Delay
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:452 .text.HAL_Delay:00000024 $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:457 .text.HAL_SuspendTick:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:463 .text.HAL_SuspendTick:00000000 HAL_SuspendTick
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:483 .text.HAL_ResumeTick:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:489 .text.HAL_ResumeTick:00000000 HAL_ResumeTick
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:509 .text.HAL_GetHalVersion:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:515 .text.HAL_GetHalVersion:00000000 HAL_GetHalVersion
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:529 .text.HAL_GetHalVersion:00000004 $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:534 .text.HAL_GetREVID:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:540 .text.HAL_GetREVID:00000000 HAL_GetREVID
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:557 .text.HAL_GetREVID:00000008 $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:562 .text.HAL_GetDEVID:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:568 .text.HAL_GetDEVID:00000000 HAL_GetDEVID
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:585 .text.HAL_GetDEVID:0000000c $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:590 .text.HAL_GetUIDw0:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:596 .text.HAL_GetUIDw0:00000000 HAL_GetUIDw0
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:611 .text.HAL_GetUIDw0:00000008 $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:616 .text.HAL_GetUIDw1:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:622 .text.HAL_GetUIDw1:00000000 HAL_GetUIDw1
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:637 .text.HAL_GetUIDw1:00000008 $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:642 .text.HAL_GetUIDw2:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:648 .text.HAL_GetUIDw2:00000000 HAL_GetUIDw2
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:663 .text.HAL_GetUIDw2:00000008 $d
ARM GAS C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s page 26
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:668 .text.HAL_DBGMCU_EnableDBGSleepMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:674 .text.HAL_DBGMCU_EnableDBGSleepMode:00000000 HAL_DBGMCU_EnableDBGSleepMode
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:691 .text.HAL_DBGMCU_EnableDBGSleepMode:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:696 .text.HAL_DBGMCU_DisableDBGSleepMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:702 .text.HAL_DBGMCU_DisableDBGSleepMode:00000000 HAL_DBGMCU_DisableDBGSleepMode
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:719 .text.HAL_DBGMCU_DisableDBGSleepMode:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:724 .text.HAL_DBGMCU_EnableDBGStopMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:730 .text.HAL_DBGMCU_EnableDBGStopMode:00000000 HAL_DBGMCU_EnableDBGStopMode
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:747 .text.HAL_DBGMCU_EnableDBGStopMode:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:752 .text.HAL_DBGMCU_DisableDBGStopMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:758 .text.HAL_DBGMCU_DisableDBGStopMode:00000000 HAL_DBGMCU_DisableDBGStopMode
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:775 .text.HAL_DBGMCU_DisableDBGStopMode:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:780 .text.HAL_DBGMCU_EnableDBGStandbyMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:786 .text.HAL_DBGMCU_EnableDBGStandbyMode:00000000 HAL_DBGMCU_EnableDBGStandbyMode
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:803 .text.HAL_DBGMCU_EnableDBGStandbyMode:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:808 .text.HAL_DBGMCU_DisableDBGStandbyMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:814 .text.HAL_DBGMCU_DisableDBGStandbyMode:00000000 HAL_DBGMCU_DisableDBGStandbyMode
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:831 .text.HAL_DBGMCU_DisableDBGStandbyMode:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:843 .data.uwTickPrio:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccxtPP8d.s:850 .bss.uwTick:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:668 .text.HAL_DBGMCU_EnableDBGSleepMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:674 .text.HAL_DBGMCU_EnableDBGSleepMode:00000000 HAL_DBGMCU_EnableDBGSleepMode
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:691 .text.HAL_DBGMCU_EnableDBGSleepMode:0000000c $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:696 .text.HAL_DBGMCU_DisableDBGSleepMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:702 .text.HAL_DBGMCU_DisableDBGSleepMode:00000000 HAL_DBGMCU_DisableDBGSleepMode
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:719 .text.HAL_DBGMCU_DisableDBGSleepMode:0000000c $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:724 .text.HAL_DBGMCU_EnableDBGStopMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:730 .text.HAL_DBGMCU_EnableDBGStopMode:00000000 HAL_DBGMCU_EnableDBGStopMode
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:747 .text.HAL_DBGMCU_EnableDBGStopMode:0000000c $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:752 .text.HAL_DBGMCU_DisableDBGStopMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:758 .text.HAL_DBGMCU_DisableDBGStopMode:00000000 HAL_DBGMCU_DisableDBGStopMode
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:775 .text.HAL_DBGMCU_DisableDBGStopMode:0000000c $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:780 .text.HAL_DBGMCU_EnableDBGStandbyMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:786 .text.HAL_DBGMCU_EnableDBGStandbyMode:00000000 HAL_DBGMCU_EnableDBGStandbyMode
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:803 .text.HAL_DBGMCU_EnableDBGStandbyMode:0000000c $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:808 .text.HAL_DBGMCU_DisableDBGStandbyMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:814 .text.HAL_DBGMCU_DisableDBGStandbyMode:00000000 HAL_DBGMCU_DisableDBGStandbyMode
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:831 .text.HAL_DBGMCU_DisableDBGStandbyMode:0000000c $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:843 .data.uwTickPrio:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc9VxNQg.s:850 .bss.uwTick:00000000 $d
UNDEFINED SYMBOLS
HAL_SYSTICK_Config

150
build/stm32f3xx_hal_adc.lst
View File

@ -1,4 +1,4 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 1
1 .cpu cortex-m4
@ -58,7 +58,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** ##### ADC peripheral features #####
28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** ==============================================================================
29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** [..]
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 2
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 2
30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution (available only on
@ -118,7 +118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c ****
85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** (#) Enable the ADC interface
86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** (++) As prerequisite, ADC clock must be configured at RCC top level.
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 3
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 3
87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c ****
@ -178,7 +178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** ADCx_IRQHandler().
142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c ****
143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** (#) Optionally, in case of usage of DMA:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 4
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 4
144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** (++) Configure the DMA (DMA channel, mode normal or circular, ...)
@ -238,7 +238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** (+++) Stop conversion and disable the ADC peripheral
199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** using function HAL_ADC_Stop()
200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 5
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 5
201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** (++) ADC conversion by interruption:
@ -298,7 +298,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c ****
256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** (#) Disable the ADC interface
257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** (++) ADC clock can be hard reset and disabled at RCC top level.
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 6
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 6
258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** (++) Hard reset of ADC peripherals
@ -358,7 +358,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c ****
313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** (#) Optionally, in case of usage of DMA:
314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** (++) Deinitialize the DMA
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 7
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 7
315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** using function HAL_DMA_DeInit().
@ -418,7 +418,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** [..]
370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c ****
371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 8
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 8
372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** Exception done MspInit/MspDeInit functions that can be registered/unregistered
@ -478,7 +478,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** * @{
427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** */
428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 9
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 9
429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** /**
@ -538,7 +538,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
43 .LFE130:
45 .section .text.HAL_ADC_DeInit,"ax",%progbits
46 .align 1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 10
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 10
47 .weak HAL_ADC_DeInit
@ -598,7 +598,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
72 .weak HAL_ADC_MspInit
73 .syntax unified
74 .thumb
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 11
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 11
75 .thumb_func
@ -658,7 +658,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c ****
527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** /* NOTE : This function should not be modified. When the callback is needed,
528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** function HAL_ADC_MspDeInit must be implemented in the user file.
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 12
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 12
529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** */
@ -718,7 +718,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** break;
571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c ****
572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** case HAL_ADC_CONVERSION_HALF_CB_ID :
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 13
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 13
573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** hadc->ConvHalfCpltCallback = pCallback;
@ -778,7 +778,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** {
628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** /* Update the error code */
629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 14
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 14
630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c ****
@ -838,7 +838,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** case HAL_ADC_MSPINIT_CB_ID :
685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** break;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 15
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 15
687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c ****
@ -898,7 +898,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** * @brief IO operation functions
742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** *
743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** @verbatim
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 16
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 16
744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** ===============================================================================
@ -958,7 +958,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
141 .thumb
142 .thumb_func
144 HAL_ADC_Stop:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 17
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 17
145 .LVL8:
@ -1018,7 +1018,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** * @param hadc ADC handle
810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** * @param Timeout Timeout value in millisecond.
811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** * @retval HAL status
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 18
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 18
812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** */
@ -1078,7 +1078,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
199 .cfi_startproc
200 @ args = 0, pretend = 0, frame = 0
201 @ frame_needed = 0, uses_anonymous_args = 0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 19
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 19
202 @ link register save eliminated.
@ -1138,7 +1138,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
229 @ link register save eliminated.
870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */
871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** UNUSED(hadc);
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 20
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 20
230 .loc 1 871 3 view .LVU40
@ -1198,7 +1198,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c ****
903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** /* Return function status */
904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** return HAL_ERROR;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 21
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 21
256 .loc 1 904 3 view .LVU46
@ -1258,7 +1258,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** return HAL_ERROR;
283 .loc 1 934 3 view .LVU53
935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 22
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 22
284 .loc 1 935 1 is_stmt 0 view .LVU54
@ -1318,7 +1318,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
315 .LFE141:
317 .section .text.HAL_ADC_GetValue,"ax",%progbits
318 .align 1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 23
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 23
319 .weak HAL_ADC_GetValue
@ -1378,7 +1378,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** */
985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** __weak void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 24
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 24
353 .loc 1 986 1 is_stmt 1 view -0
@ -1438,7 +1438,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
389 .thumb
390 .thumb_func
392 HAL_ADC_ConvHalfCpltCallback:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 25
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 25
393 .LVL26:
@ -1498,7 +1498,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
1035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file.
1036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** */
1037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 26
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 26
422 .loc 1 1037 1 is_stmt 0 view .LVU77
@ -1558,7 +1558,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
1060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** * @brief Peripheral Control functions
1061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** *
1062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** @verbatim
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 27
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 27
1063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** ===============================================================================
@ -1618,7 +1618,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
466 .loc 1 1108 1 is_stmt 0 view .LVU85
467 0000 0120 movs r0, #1
468 .LVL30:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 28
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 28
469 .loc 1 1108 1 view .LVU86
@ -1678,7 +1678,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
498 .LFE149:
500 .section .text.HAL_ADC_GetState,"ax",%progbits
501 .align 1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 29
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 29
502 .global HAL_ADC_GetState
@ -1738,7 +1738,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
518 0000 006C ldr r0, [r0, #64]
519 .LVL34:
1175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 30
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 30
520 .loc 1 1175 1 view .LVU97
@ -1787,54 +1787,54 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 1
556 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h"
557 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h"
558 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s page 31
ARM GAS C:\Users\nived\AppData\Local\Temp\ccgltKQe.s page 31
DEFINED SYMBOLS
*ABS*:00000000 stm32f3xx_hal_adc.c
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:21 .text.HAL_ADC_Init:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:27 .text.HAL_ADC_Init:00000000 HAL_ADC_Init
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:46 .text.HAL_ADC_DeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:52 .text.HAL_ADC_DeInit:00000000 HAL_ADC_DeInit
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:71 .text.HAL_ADC_MspInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:77 .text.HAL_ADC_MspInit:00000000 HAL_ADC_MspInit
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:92 .text.HAL_ADC_MspDeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:98 .text.HAL_ADC_MspDeInit:00000000 HAL_ADC_MspDeInit
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:113 .text.HAL_ADC_Start:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:119 .text.HAL_ADC_Start:00000000 HAL_ADC_Start
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:138 .text.HAL_ADC_Stop:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:144 .text.HAL_ADC_Stop:00000000 HAL_ADC_Stop
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:163 .text.HAL_ADC_PollForConversion:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:169 .text.HAL_ADC_PollForConversion:00000000 HAL_ADC_PollForConversion
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:189 .text.HAL_ADC_PollForEvent:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:195 .text.HAL_ADC_PollForEvent:00000000 HAL_ADC_PollForEvent
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:216 .text.HAL_ADC_Start_IT:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:222 .text.HAL_ADC_Start_IT:00000000 HAL_ADC_Start_IT
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:241 .text.HAL_ADC_Stop_IT:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:247 .text.HAL_ADC_Stop_IT:00000000 HAL_ADC_Stop_IT
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:266 .text.HAL_ADC_Start_DMA:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:272 .text.HAL_ADC_Start_DMA:00000000 HAL_ADC_Start_DMA
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:293 .text.HAL_ADC_Stop_DMA:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:299 .text.HAL_ADC_Stop_DMA:00000000 HAL_ADC_Stop_DMA
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:318 .text.HAL_ADC_GetValue:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:324 .text.HAL_ADC_GetValue:00000000 HAL_ADC_GetValue
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:344 .text.HAL_ADC_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:350 .text.HAL_ADC_IRQHandler:00000000 HAL_ADC_IRQHandler
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:365 .text.HAL_ADC_ConvCpltCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:371 .text.HAL_ADC_ConvCpltCallback:00000000 HAL_ADC_ConvCpltCallback
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:386 .text.HAL_ADC_ConvHalfCpltCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:392 .text.HAL_ADC_ConvHalfCpltCallback:00000000 HAL_ADC_ConvHalfCpltCallback
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:407 .text.HAL_ADC_LevelOutOfWindowCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:413 .text.HAL_ADC_LevelOutOfWindowCallback:00000000 HAL_ADC_LevelOutOfWindowCallback
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:428 .text.HAL_ADC_ErrorCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:434 .text.HAL_ADC_ErrorCallback:00000000 HAL_ADC_ErrorCallback
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:449 .text.HAL_ADC_ConfigChannel:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:455 .text.HAL_ADC_ConfigChannel:00000000 HAL_ADC_ConfigChannel
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:475 .text.HAL_ADC_AnalogWDGConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:481 .text.HAL_ADC_AnalogWDGConfig:00000000 HAL_ADC_AnalogWDGConfig
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:501 .text.HAL_ADC_GetState:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:507 .text.HAL_ADC_GetState:00000000 HAL_ADC_GetState
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:526 .text.HAL_ADC_GetError:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccLW8e6e.s:532 .text.HAL_ADC_GetError:00000000 HAL_ADC_GetError
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:21 .text.HAL_ADC_Init:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:27 .text.HAL_ADC_Init:00000000 HAL_ADC_Init
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:46 .text.HAL_ADC_DeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:52 .text.HAL_ADC_DeInit:00000000 HAL_ADC_DeInit
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:71 .text.HAL_ADC_MspInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:77 .text.HAL_ADC_MspInit:00000000 HAL_ADC_MspInit
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:92 .text.HAL_ADC_MspDeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:98 .text.HAL_ADC_MspDeInit:00000000 HAL_ADC_MspDeInit
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:113 .text.HAL_ADC_Start:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:119 .text.HAL_ADC_Start:00000000 HAL_ADC_Start
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:138 .text.HAL_ADC_Stop:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:144 .text.HAL_ADC_Stop:00000000 HAL_ADC_Stop
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:163 .text.HAL_ADC_PollForConversion:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:169 .text.HAL_ADC_PollForConversion:00000000 HAL_ADC_PollForConversion
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:189 .text.HAL_ADC_PollForEvent:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:195 .text.HAL_ADC_PollForEvent:00000000 HAL_ADC_PollForEvent
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:216 .text.HAL_ADC_Start_IT:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:222 .text.HAL_ADC_Start_IT:00000000 HAL_ADC_Start_IT
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:241 .text.HAL_ADC_Stop_IT:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:247 .text.HAL_ADC_Stop_IT:00000000 HAL_ADC_Stop_IT
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:266 .text.HAL_ADC_Start_DMA:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:272 .text.HAL_ADC_Start_DMA:00000000 HAL_ADC_Start_DMA
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:293 .text.HAL_ADC_Stop_DMA:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:299 .text.HAL_ADC_Stop_DMA:00000000 HAL_ADC_Stop_DMA
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:318 .text.HAL_ADC_GetValue:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:324 .text.HAL_ADC_GetValue:00000000 HAL_ADC_GetValue
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:344 .text.HAL_ADC_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:350 .text.HAL_ADC_IRQHandler:00000000 HAL_ADC_IRQHandler
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:365 .text.HAL_ADC_ConvCpltCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:371 .text.HAL_ADC_ConvCpltCallback:00000000 HAL_ADC_ConvCpltCallback
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:386 .text.HAL_ADC_ConvHalfCpltCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:392 .text.HAL_ADC_ConvHalfCpltCallback:00000000 HAL_ADC_ConvHalfCpltCallback
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:407 .text.HAL_ADC_LevelOutOfWindowCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:413 .text.HAL_ADC_LevelOutOfWindowCallback:00000000 HAL_ADC_LevelOutOfWindowCallback
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:428 .text.HAL_ADC_ErrorCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:434 .text.HAL_ADC_ErrorCallback:00000000 HAL_ADC_ErrorCallback
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:449 .text.HAL_ADC_ConfigChannel:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:455 .text.HAL_ADC_ConfigChannel:00000000 HAL_ADC_ConfigChannel
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:475 .text.HAL_ADC_AnalogWDGConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:481 .text.HAL_ADC_AnalogWDGConfig:00000000 HAL_ADC_AnalogWDGConfig
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:501 .text.HAL_ADC_GetState:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:507 .text.HAL_ADC_GetState:00000000 HAL_ADC_GetState
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:526 .text.HAL_ADC_GetError:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccgltKQe.s:532 .text.HAL_ADC_GetError:00000000 HAL_ADC_GetError
NO UNDEFINED SYMBOLS

820
build/stm32f3xx_hal_adc_ex.lst
View File

File diff suppressed because it is too large Load Diff

390
build/stm32f3xx_hal_can.lst
View File

File diff suppressed because it is too large Load Diff

298
build/stm32f3xx_hal_cortex.lst
View File

@ -1,4 +1,4 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 1
1 .cpu cortex-m4
@ -58,7 +58,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
27:Drivers/CMSIS/Include/core_cm4.h **** #elif defined (__clang__)
28:Drivers/CMSIS/Include/core_cm4.h **** #pragma clang system_header /* treat file as system include file */
29:Drivers/CMSIS/Include/core_cm4.h **** #endif
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 2
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 2
30:Drivers/CMSIS/Include/core_cm4.h ****
@ -118,7 +118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
84:Drivers/CMSIS/Include/core_cm4.h **** #else
85:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U
86:Drivers/CMSIS/Include/core_cm4.h **** #endif
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 3
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 3
87:Drivers/CMSIS/Include/core_cm4.h ****
@ -178,7 +178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
141:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
142:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U
143:Drivers/CMSIS/Include/core_cm4.h **** #endif
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 4
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 4
144:Drivers/CMSIS/Include/core_cm4.h **** #else
@ -238,7 +238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
198:Drivers/CMSIS/Include/core_cm4.h **** #define __NVIC_PRIO_BITS 3U
199:Drivers/CMSIS/Include/core_cm4.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
200:Drivers/CMSIS/Include/core_cm4.h **** #endif
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 5
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 5
201:Drivers/CMSIS/Include/core_cm4.h ****
@ -298,7 +298,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
255:Drivers/CMSIS/Include/core_cm4.h ****
256:Drivers/CMSIS/Include/core_cm4.h **** /**
257:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Application Program Status Register (APSR).
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 6
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 6
258:Drivers/CMSIS/Include/core_cm4.h **** */
@ -358,7 +358,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
312:Drivers/CMSIS/Include/core_cm4.h ****
313:Drivers/CMSIS/Include/core_cm4.h **** /**
314:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 7
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 7
315:Drivers/CMSIS/Include/core_cm4.h **** */
@ -418,7 +418,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
369:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Control Registers (CONTROL).
370:Drivers/CMSIS/Include/core_cm4.h **** */
371:Drivers/CMSIS/Include/core_cm4.h **** typedef union
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 8
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 8
372:Drivers/CMSIS/Include/core_cm4.h **** {
@ -478,7 +478,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
426:Drivers/CMSIS/Include/core_cm4.h ****
427:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_NVIC */
428:Drivers/CMSIS/Include/core_cm4.h ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 9
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 9
429:Drivers/CMSIS/Include/core_cm4.h ****
@ -538,7 +538,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
483:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB
484:Drivers/CMSIS/Include/core_cm4.h ****
485:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 10
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 10
486:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB
@ -598,7 +598,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
540:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB
541:Drivers/CMSIS/Include/core_cm4.h ****
542:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 11
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 11
543:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB
@ -658,7 +658,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
597:Drivers/CMSIS/Include/core_cm4.h ****
598:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB
599:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 12
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 12
600:Drivers/CMSIS/Include/core_cm4.h ****
@ -718,7 +718,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
654:Drivers/CMSIS/Include/core_cm4.h ****
655:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB
656:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 13
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 13
657:Drivers/CMSIS/Include/core_cm4.h ****
@ -778,7 +778,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
711:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
712:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the System Control and ID Register not in the SCB
713:Drivers/CMSIS/Include/core_cm4.h **** @{
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 14
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 14
714:Drivers/CMSIS/Include/core_cm4.h **** */
@ -838,7 +838,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
768:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT
769:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT
770:Drivers/CMSIS/Include/core_cm4.h ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 15
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 15
771:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT
@ -898,7 +898,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
825:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED3[29U];
826:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register *
827:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 16
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 16
828:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Reg
@ -958,7 +958,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
882:Drivers/CMSIS/Include/core_cm4.h ****
883:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Integration Read Register Definitions */
884:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 17
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 17
885:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM
@ -1018,7 +1018,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
939:Drivers/CMSIS/Include/core_cm4.h **** } DWT_Type;
940:Drivers/CMSIS/Include/core_cm4.h ****
941:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Control Register Definitions */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 18
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 18
942:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTR
@ -1078,7 +1078,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
996:Drivers/CMSIS/Include/core_cm4.h **** /* DWT CPI Count Register Definitions */
997:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPI
998:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPI
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 19
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 19
999:Drivers/CMSIS/Include/core_cm4.h ****
@ -1138,7 +1138,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1053:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_TPI Trace Port Interface (TPI)
1054:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Trace Port Interface (TPI)
1055:Drivers/CMSIS/Include/core_cm4.h **** @{
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 20
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 20
1056:Drivers/CMSIS/Include/core_cm4.h **** */
@ -1198,7 +1198,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1110:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Formatter and Flush Control Register Definitions */
1111:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFC
1112:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFC
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 21
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 21
1113:Drivers/CMSIS/Include/core_cm4.h ****
@ -1258,7 +1258,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1167:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIF
1168:Drivers/CMSIS/Include/core_cm4.h ****
1169:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIF
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 22
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 22
1170:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIF
@ -1318,7 +1318,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1224:Drivers/CMSIS/Include/core_cm4.h **** {
1225:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1226:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 23
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 23
1227:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
@ -1378,7 +1378,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1281:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU
1282:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU
1283:Drivers/CMSIS/Include/core_cm4.h ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 24
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 24
1284:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU
@ -1438,7 +1438,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1338:Drivers/CMSIS/Include/core_cm4.h ****
1339:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCC
1340:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCC
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 25
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 25
1341:Drivers/CMSIS/Include/core_cm4.h ****
@ -1498,7 +1498,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1395:Drivers/CMSIS/Include/core_cm4.h ****
1396:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR
1397:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 26
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 26
1398:Drivers/CMSIS/Include/core_cm4.h ****
@ -1558,7 +1558,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1452:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< Core
1453:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< Core
1454:Drivers/CMSIS/Include/core_cm4.h ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 27
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 27
1455:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< Core
@ -1618,7 +1618,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1509:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< Core
1510:Drivers/CMSIS/Include/core_cm4.h ****
1511:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< Core
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 28
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 28
1512:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< Core
@ -1678,7 +1678,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1566:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc
1567:Drivers/CMSIS/Include/core_cm4.h **** #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct
1568:Drivers/CMSIS/Include/core_cm4.h **** #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 29
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 29
1569:Drivers/CMSIS/Include/core_cm4.h **** #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct
@ -1738,7 +1738,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1623:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SystemReset __NVIC_SystemReset
1624:Drivers/CMSIS/Include/core_cm4.h **** #endif /* CMSIS_NVIC_VIRTUAL */
1625:Drivers/CMSIS/Include/core_cm4.h ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 30
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 30
1626:Drivers/CMSIS/Include/core_cm4.h **** #ifdef CMSIS_VECTAB_VIRTUAL
@ -1798,7 +1798,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1680:Drivers/CMSIS/Include/core_cm4.h ****
1681:Drivers/CMSIS/Include/core_cm4.h ****
1682:Drivers/CMSIS/Include/core_cm4.h **** /**
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 31
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 31
1683:Drivers/CMSIS/Include/core_cm4.h **** \brief Enable Interrupt
@ -1858,7 +1858,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
40 0002 0CDB blt .L1
1727:Drivers/CMSIS/Include/core_cm4.h **** {
1728:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 32
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 32
41 .loc 2 1728 5 is_stmt 1 view .LVU4
@ -1918,7 +1918,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
38:Drivers/CMSIS/Include/cmsis_gcc.h ****
39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 33
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 33
41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm
@ -1978,7 +1978,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 34
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 34
98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
@ -2038,7 +2038,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
152:Drivers/CMSIS/Include/cmsis_gcc.h **** {
153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
154:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 35
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 35
155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) );
@ -2098,7 +2098,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
211:Drivers/CMSIS/Include/cmsis_gcc.h **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 36
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 36
212:Drivers/CMSIS/Include/cmsis_gcc.h ****
@ -2158,7 +2158,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
268:Drivers/CMSIS/Include/cmsis_gcc.h **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 37
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 37
269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
@ -2218,7 +2218,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
324:Drivers/CMSIS/Include/cmsis_gcc.h ****
325:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 38
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 38
326:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
@ -2278,7 +2278,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value
381:Drivers/CMSIS/Include/cmsis_gcc.h **** */
382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 39
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 39
383:Drivers/CMSIS/Include/cmsis_gcc.h **** {
@ -2338,7 +2338,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
438:Drivers/CMSIS/Include/cmsis_gcc.h **** */
439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 40
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 40
440:Drivers/CMSIS/Include/cmsis_gcc.h **** {
@ -2398,7 +2398,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
495:Drivers/CMSIS/Include/cmsis_gcc.h ****
496:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 41
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 41
497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
@ -2458,7 +2458,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
551:Drivers/CMSIS/Include/cmsis_gcc.h ****
552:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 42
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 42
554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register.
@ -2518,7 +2518,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always.
610:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 43
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 43
611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
@ -2578,7 +2578,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
666:Drivers/CMSIS/Include/cmsis_gcc.h **** }
667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 44
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 44
668:Drivers/CMSIS/Include/cmsis_gcc.h ****
@ -2638,7 +2638,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
724:Drivers/CMSIS/Include/cmsis_gcc.h **** */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 45
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 45
725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
@ -2698,7 +2698,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 46
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 46
782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U);
@ -2758,7 +2758,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop")
837:Drivers/CMSIS/Include/cmsis_gcc.h ****
838:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 47
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 47
839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt
@ -2818,7 +2818,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
69 .LBB34:
70 .LBI34:
866:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 48
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 48
71 .loc 3 866 27 view .LVU13
@ -2878,7 +2878,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1756:Drivers/CMSIS/Include/core_cm4.h **** /**
1757:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Pending Interrupt
1758:Drivers/CMSIS/Include/core_cm4.h **** \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 49
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 49
1759:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number.
@ -2938,7 +2938,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1813:Drivers/CMSIS/Include/core_cm4.h **** \param [in] priority Priority to set.
1814:Drivers/CMSIS/Include/core_cm4.h **** \note The priority cannot be set for every processor exception.
1815:Drivers/CMSIS/Include/core_cm4.h **** */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 50
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 50
1816:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
@ -2998,7 +2998,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
145 .section .text.__NVIC_GetPriority,"ax",%progbits
146 .align 1
147 .syntax unified
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 51
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 51
148 .thumb
@ -3058,7 +3058,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1848:Drivers/CMSIS/Include/core_cm4.h **** }
1849:Drivers/CMSIS/Include/core_cm4.h **** }
182 .loc 2 1849 1 view .LVU41
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 52
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 52
183 001e 7047 bx lr
@ -3118,7 +3118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
219 000e 28BF it cs
220 0010 4FF0040C movcs ip, #4
221 .LVL11:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 53
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 53
1870:Drivers/CMSIS/Include/core_cm4.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
@ -3178,7 +3178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1881:Drivers/CMSIS/Include/core_cm4.h **** \details Decodes an interrupt priority value with a given priority group to
1882:Drivers/CMSIS/Include/core_cm4.h **** preemptive priority value and subpriority value.
1883:Drivers/CMSIS/Include/core_cm4.h **** In case of a conflict between priority grouping and available
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 54
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 54
1884:Drivers/CMSIS/Include/core_cm4.h **** priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
@ -3238,7 +3238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
304 0020 4FF0FF3E mov lr, #-1
305 0024 0EFA0CFC lsl ip, lr, ip
306 .LVL22:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 55
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 55
307 .loc 2 1899 53 discriminator 4 view .LVU78
@ -3298,7 +3298,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1923:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt,
1924:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception.
1925:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number.
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 56
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 56
1926:Drivers/CMSIS/Include/core_cm4.h **** \return Address of interrupt handler function
@ -3358,7 +3358,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1946:Drivers/CMSIS/Include/core_cm4.h **** __DSB(); /* Ensure completion of memory
369 .loc 2 1946 3 is_stmt 1 view .LVU95
370 .LBB38:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 57
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 57
371 .LBI38:
@ -3418,7 +3418,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** *
11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @verbatim
12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ==============================================================================
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 58
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 58
13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ##### How to use this driver #####
@ -3478,7 +3478,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** @endverbatim
69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ******************************************************************************
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 59
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 59
70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @attention
@ -3538,7 +3538,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Private variables ---------------------------------------------------------*/
125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Private function prototypes -----------------------------------------------*/
126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Exported functions ---------------------------------------------------------*/
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 60
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 60
127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
@ -3598,7 +3598,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
418 .loc 1 174 3 view .LVU103
419 .LBB40:
420 .LBI40:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 61
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 61
1657:Drivers/CMSIS/Include/core_cm4.h **** {
@ -3658,7 +3658,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
458 .loc 1 175 1 view .LVU120
459 001e 7047 bx lr
460 .L29:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 62
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 62
461 .align 2
@ -3718,7 +3718,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1676:Drivers/CMSIS/Include/core_cm4.h **** {
494 .loc 2 1676 26 view .LVU127
495 .LBB43:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 63
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 63
1678:Drivers/CMSIS/Include/core_cm4.h **** }
@ -3778,7 +3778,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
534 .loc 1 213 1 is_stmt 1 view -0
535 .cfi_startproc
536 @ args = 0, pretend = 0, frame = 0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 64
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 64
537 @ frame_needed = 0, uses_anonymous_args = 0
@ -3838,7 +3838,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
576 .section .text.HAL_NVIC_DisableIRQ,"ax",%progbits
577 .align 1
578 .global HAL_NVIC_DisableIRQ
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 65
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 65
579 .syntax unified
@ -3898,7 +3898,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
613 .loc 1 242 1 is_stmt 1 view -0
614 .cfi_startproc
615 @ Volatile: function does not return.
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 66
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 66
616 @ args = 0, pretend = 0, frame = 0
@ -3958,7 +3958,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1963:Drivers/CMSIS/Include/core_cm4.h ****
1964:Drivers/CMSIS/Include/core_cm4.h ****
1965:Drivers/CMSIS/Include/core_cm4.h **** /* ########################## FPU functions #################################### */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 67
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 67
1966:Drivers/CMSIS/Include/core_cm4.h **** /**
@ -4018,7 +4018,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
2020:Drivers/CMSIS/Include/core_cm4.h **** must contain a vendor-specific implementation of this function.
2021:Drivers/CMSIS/Include/core_cm4.h **** */
2022:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 68
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 68
646 .loc 2 2022 26 view .LVU158
@ -4078,7 +4078,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
2033:Drivers/CMSIS/Include/core_cm4.h **** SysTick_CTRL_TICKINT_Msk |
2034:Drivers/CMSIS/Include/core_cm4.h **** SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTi
2035:Drivers/CMSIS/Include/core_cm4.h **** return (0UL); /* Function successful */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 69
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 69
685 .loc 2 2035 3 is_stmt 1 view .LVU175
@ -4138,7 +4138,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */
284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_MPU_Disable(void)
285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 70
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 70
713 .loc 1 285 1 is_stmt 1 view -0
@ -4198,7 +4198,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
749 .cfi_startproc
750 @ args = 0, pretend = 0, frame = 0
751 @ frame_needed = 0, uses_anonymous_args = 0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 71
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 71
752 @ link register save eliminated.
@ -4258,7 +4258,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
791 .loc 1 323 3 view .LVU197
324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 72
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 72
325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Set the Region number */
@ -4318,7 +4318,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
826 .loc 1 343 36 view .LVU220
827 001e 817A ldrb r1, [r0, #10] @ zero_extendqisi2
342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 73
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 73
828 .loc 1 342 84 view .LVU221
@ -4378,7 +4378,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
864 .loc 1 354 15 is_stmt 0 view .LVU238
865 0054 C3F8A020 str r2, [r3, #160]
355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 74
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 74
356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
@ -4438,7 +4438,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
907 .cfi_endproc
908 .LFE139:
910 .section .text.HAL_NVIC_GetPriority,"ax",%progbits
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 75
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 75
911 .align 1
@ -4498,7 +4498,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
938 .loc 1 395 3 is_stmt 0 view .LVU250
939 000c 3346 mov r3, r6
940 000e 2A46 mov r2, r5
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 76
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 76
941 0010 2146 mov r1, r4
@ -4558,7 +4558,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
978 0004 00F01F02 and r2, r0, #31
1766:Drivers/CMSIS/Include/core_cm4.h **** }
979 .loc 2 1766 34 view .LVU261
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 77
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 77
980 0008 4009 lsrs r0, r0, #5
@ -4618,7 +4618,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1018 .LBB54:
1019 .LBI54:
1743:Drivers/CMSIS/Include/core_cm4.h **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 78
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 78
1020 .loc 2 1743 26 view .LVU268
@ -4678,7 +4678,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1063 .thumb_func
1065 HAL_NVIC_ClearPendingIRQ:
1066 .LVL64:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 79
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 79
1067 .LFB143:
@ -4738,7 +4738,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1099 .LBE57:
1100 .LBE56:
437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 80
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 80
1101 .loc 1 437 1 view .LVU293
@ -4798,7 +4798,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1138 0004 4309 lsrs r3, r0, #5
1798:Drivers/CMSIS/Include/core_cm4.h **** }
1139 .loc 2 1798 35 view .LVU302
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 81
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 81
1140 0006 8033 adds r3, r3, #128
@ -4858,7 +4858,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1179 @ frame_needed = 0, uses_anonymous_args = 0
1180 @ link register save eliminated.
463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 82
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 82
464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
@ -4918,7 +4918,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** }
483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ****
484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /**
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 83
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 83
485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief SYSTICK callback.
@ -4972,77 +4972,77 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 1
1255 .file 6 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
1256 .file 7 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h"
1257 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 84
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 84
DEFINED SYMBOLS
*ABS*:00000000 stm32f3xx_hal_cortex.c
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:21 .text.__NVIC_DisableIRQ:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:26 .text.__NVIC_DisableIRQ:00000000 __NVIC_DisableIRQ
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:88 .text.__NVIC_DisableIRQ:00000020 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:93 .text.__NVIC_SetPriority:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:98 .text.__NVIC_SetPriority:00000000 __NVIC_SetPriority
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:141 .text.__NVIC_SetPriority:00000024 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:146 .text.__NVIC_GetPriority:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:151 .text.__NVIC_GetPriority:00000000 __NVIC_GetPriority
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:187 .text.__NVIC_GetPriority:00000020 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:192 .text.NVIC_EncodePriority:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:197 .text.NVIC_EncodePriority:00000000 NVIC_EncodePriority
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:258 .text.NVIC_DecodePriority:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:263 .text.NVIC_DecodePriority:00000000 NVIC_DecodePriority
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:331 .text.__NVIC_SystemReset:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:336 .text.__NVIC_SystemReset:00000000 __NVIC_SystemReset
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:397 .text.__NVIC_SystemReset:0000001c $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:403 .text.HAL_NVIC_SetPriorityGrouping:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:409 .text.HAL_NVIC_SetPriorityGrouping:00000000 HAL_NVIC_SetPriorityGrouping
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:463 .text.HAL_NVIC_SetPriorityGrouping:00000020 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:468 .text.HAL_NVIC_SetPriority:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:474 .text.HAL_NVIC_SetPriority:00000000 HAL_NVIC_SetPriority
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:520 .text.HAL_NVIC_SetPriority:0000001c $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:525 .text.HAL_NVIC_EnableIRQ:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:531 .text.HAL_NVIC_EnableIRQ:00000000 HAL_NVIC_EnableIRQ
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:572 .text.HAL_NVIC_EnableIRQ:00000018 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:577 .text.HAL_NVIC_DisableIRQ:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:583 .text.HAL_NVIC_DisableIRQ:00000000 HAL_NVIC_DisableIRQ
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:605 .text.HAL_NVIC_SystemReset:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:611 .text.HAL_NVIC_SystemReset:00000000 HAL_NVIC_SystemReset
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:629 .text.HAL_SYSTICK_Config:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:635 .text.HAL_SYSTICK_Config:00000000 HAL_SYSTICK_Config
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:700 .text.HAL_SYSTICK_Config:00000024 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:705 .text.HAL_MPU_Disable:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:711 .text.HAL_MPU_Disable:00000000 HAL_MPU_Disable
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:734 .text.HAL_MPU_Disable:00000014 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:739 .text.HAL_MPU_Enable:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:745 .text.HAL_MPU_Enable:00000000 HAL_MPU_Enable
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:771 .text.HAL_MPU_Enable:00000014 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:776 .text.HAL_MPU_ConfigRegion:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:782 .text.HAL_MPU_ConfigRegion:00000000 HAL_MPU_ConfigRegion
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:871 .text.HAL_MPU_ConfigRegion:0000005c $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:876 .text.HAL_NVIC_GetPriorityGrouping:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:882 .text.HAL_NVIC_GetPriorityGrouping:00000000 HAL_NVIC_GetPriorityGrouping
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:906 .text.HAL_NVIC_GetPriorityGrouping:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:911 .text.HAL_NVIC_GetPriority:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:917 .text.HAL_NVIC_GetPriority:00000000 HAL_NVIC_GetPriority
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:951 .text.HAL_NVIC_SetPendingIRQ:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:957 .text.HAL_NVIC_SetPendingIRQ:00000000 HAL_NVIC_SetPendingIRQ
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:998 .text.HAL_NVIC_SetPendingIRQ:00000018 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1003 .text.HAL_NVIC_GetPendingIRQ:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1009 .text.HAL_NVIC_GetPendingIRQ:00000000 HAL_NVIC_GetPendingIRQ
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1054 .text.HAL_NVIC_GetPendingIRQ:00000020 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1059 .text.HAL_NVIC_ClearPendingIRQ:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1065 .text.HAL_NVIC_ClearPendingIRQ:00000000 HAL_NVIC_ClearPendingIRQ
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1106 .text.HAL_NVIC_ClearPendingIRQ:00000018 $d
ARM GAS C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s page 85
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:21 .text.__NVIC_DisableIRQ:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:26 .text.__NVIC_DisableIRQ:00000000 __NVIC_DisableIRQ
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:88 .text.__NVIC_DisableIRQ:00000020 $d
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:93 .text.__NVIC_SetPriority:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:98 .text.__NVIC_SetPriority:00000000 __NVIC_SetPriority
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:141 .text.__NVIC_SetPriority:00000024 $d
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:146 .text.__NVIC_GetPriority:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:151 .text.__NVIC_GetPriority:00000000 __NVIC_GetPriority
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:187 .text.__NVIC_GetPriority:00000020 $d
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:192 .text.NVIC_EncodePriority:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:197 .text.NVIC_EncodePriority:00000000 NVIC_EncodePriority
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:258 .text.NVIC_DecodePriority:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:263 .text.NVIC_DecodePriority:00000000 NVIC_DecodePriority
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:331 .text.__NVIC_SystemReset:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:336 .text.__NVIC_SystemReset:00000000 __NVIC_SystemReset
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:397 .text.__NVIC_SystemReset:0000001c $d
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:403 .text.HAL_NVIC_SetPriorityGrouping:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:409 .text.HAL_NVIC_SetPriorityGrouping:00000000 HAL_NVIC_SetPriorityGrouping
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:463 .text.HAL_NVIC_SetPriorityGrouping:00000020 $d
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:468 .text.HAL_NVIC_SetPriority:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:474 .text.HAL_NVIC_SetPriority:00000000 HAL_NVIC_SetPriority
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:520 .text.HAL_NVIC_SetPriority:0000001c $d
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:525 .text.HAL_NVIC_EnableIRQ:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:531 .text.HAL_NVIC_EnableIRQ:00000000 HAL_NVIC_EnableIRQ
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:572 .text.HAL_NVIC_EnableIRQ:00000018 $d
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:577 .text.HAL_NVIC_DisableIRQ:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:583 .text.HAL_NVIC_DisableIRQ:00000000 HAL_NVIC_DisableIRQ
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:605 .text.HAL_NVIC_SystemReset:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:611 .text.HAL_NVIC_SystemReset:00000000 HAL_NVIC_SystemReset
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:629 .text.HAL_SYSTICK_Config:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:635 .text.HAL_SYSTICK_Config:00000000 HAL_SYSTICK_Config
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:700 .text.HAL_SYSTICK_Config:00000024 $d
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:705 .text.HAL_MPU_Disable:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:711 .text.HAL_MPU_Disable:00000000 HAL_MPU_Disable
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:734 .text.HAL_MPU_Disable:00000014 $d
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:739 .text.HAL_MPU_Enable:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:745 .text.HAL_MPU_Enable:00000000 HAL_MPU_Enable
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:771 .text.HAL_MPU_Enable:00000014 $d
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:776 .text.HAL_MPU_ConfigRegion:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:782 .text.HAL_MPU_ConfigRegion:00000000 HAL_MPU_ConfigRegion
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:871 .text.HAL_MPU_ConfigRegion:0000005c $d
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:876 .text.HAL_NVIC_GetPriorityGrouping:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:882 .text.HAL_NVIC_GetPriorityGrouping:00000000 HAL_NVIC_GetPriorityGrouping
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:906 .text.HAL_NVIC_GetPriorityGrouping:0000000c $d
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:911 .text.HAL_NVIC_GetPriority:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:917 .text.HAL_NVIC_GetPriority:00000000 HAL_NVIC_GetPriority
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:951 .text.HAL_NVIC_SetPendingIRQ:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:957 .text.HAL_NVIC_SetPendingIRQ:00000000 HAL_NVIC_SetPendingIRQ
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:998 .text.HAL_NVIC_SetPendingIRQ:00000018 $d
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:1003 .text.HAL_NVIC_GetPendingIRQ:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:1009 .text.HAL_NVIC_GetPendingIRQ:00000000 HAL_NVIC_GetPendingIRQ
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:1054 .text.HAL_NVIC_GetPendingIRQ:00000020 $d
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:1059 .text.HAL_NVIC_ClearPendingIRQ:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:1065 .text.HAL_NVIC_ClearPendingIRQ:00000000 HAL_NVIC_ClearPendingIRQ
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:1106 .text.HAL_NVIC_ClearPendingIRQ:00000018 $d
ARM GAS C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s page 85
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1111 .text.HAL_NVIC_GetActive:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1117 .text.HAL_NVIC_GetActive:00000000 HAL_NVIC_GetActive
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1162 .text.HAL_NVIC_GetActive:00000020 $d
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1167 .text.HAL_SYSTICK_CLKSourceConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1173 .text.HAL_SYSTICK_CLKSourceConfig:00000000 HAL_SYSTICK_CLKSourceConfig
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1208 .text.HAL_SYSTICK_Callback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1214 .text.HAL_SYSTICK_Callback:00000000 HAL_SYSTICK_Callback
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1227 .text.HAL_SYSTICK_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccFCsp5u.s:1233 .text.HAL_SYSTICK_IRQHandler:00000000 HAL_SYSTICK_IRQHandler
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:1111 .text.HAL_NVIC_GetActive:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:1117 .text.HAL_NVIC_GetActive:00000000 HAL_NVIC_GetActive
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:1162 .text.HAL_NVIC_GetActive:00000020 $d
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:1167 .text.HAL_SYSTICK_CLKSourceConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:1173 .text.HAL_SYSTICK_CLKSourceConfig:00000000 HAL_SYSTICK_CLKSourceConfig
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:1208 .text.HAL_SYSTICK_Callback:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:1214 .text.HAL_SYSTICK_Callback:00000000 HAL_SYSTICK_Callback
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:1227 .text.HAL_SYSTICK_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc63Ynqu.s:1233 .text.HAL_SYSTICK_IRQHandler:00000000 HAL_SYSTICK_IRQHandler
NO UNDEFINED SYMBOLS

172
build/stm32f3xx_hal_dma.lst
View File

@ -1,4 +1,4 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 1
1 .cpu cortex-m4
@ -58,7 +58,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** detection.
29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (#) Use HAL_DMA_Abort() function to abort the current transfer
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 2
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 2
31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
@ -118,7 +118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @{
86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */
87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 3
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 3
88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** #ifdef HAL_DMA_MODULE_ENABLED
@ -178,7 +178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** {
143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR;
144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 4
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 4
145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
@ -238,7 +238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** {
200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Check the DMA handle allocation */
201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(NULL == hdma)
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 5
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 5
202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** {
@ -298,7 +298,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ===============================================================================
257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ##### IO operation functions #####
258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ===============================================================================
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 6
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 6
259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** [..] This section provides functions allowing to:
@ -358,7 +358,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** }
314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return status;
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 7
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 7
316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** }
@ -418,7 +418,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Remain BUSY */
371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** status = HAL_BUSY;
372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 8
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 8
373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
@ -478,7 +478,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* no transfer ongoing */
428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 9
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 9
430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** status = HAL_ERROR;
@ -538,7 +538,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR;
485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** }
486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 10
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 10
487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Get the level transfer complete flag */
@ -598,7 +598,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** {
543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear the transfer complete flag */
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 11
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 11
544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
@ -658,7 +658,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** {
599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 12
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 12
601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable the transfer complete & transfer error interrupts */
@ -718,7 +718,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param pCallback pointer to private callback function which has pointer to
657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * a DMA_HandleTypeDef structure as parameter.
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 13
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 13
658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status
@ -778,7 +778,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** {
713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK;
714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 14
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 14
715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process locked */
@ -838,7 +838,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ===============================================================================
770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ##### State and Errors functions #####
771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ===============================================================================
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 15
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 15
772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** [..]
@ -898,7 +898,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
29 .loc 1 825 1 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 0
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 16
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 16
32 @ frame_needed = 0, uses_anonymous_args = 0
@ -958,7 +958,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Configure DMA Channel destination address */
848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CMAR = DstAddress;
65 .loc 1 848 5 is_stmt 1 view .LVU14
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 17
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 17
66 .loc 1 848 9 is_stmt 0 view .LVU15
@ -1018,7 +1018,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
105 .loc 1 859 1 is_stmt 1 view -0
106 .cfi_startproc
107 @ args = 0, pretend = 0, frame = 0
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 18
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 18
108 @ frame_needed = 0, uses_anonymous_args = 0
@ -1078,7 +1078,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
149 002e 064B ldr r3, .L9+20
150 0030 C363 str r3, [r0, #60]
873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 19
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 19
874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** #else
@ -1138,7 +1138,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
192 .loc 1 150 3 view .LVU51
151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 20
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 20
193 .loc 1 151 3 view .LVU52
@ -1198,7 +1198,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
228 .loc 1 169 72 view .LVU71
229 0024 0343 orrs r3, r3, r0
170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.Mode | hdma->Init.Priority;
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 21
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 21
230 .loc 1 170 54 view .LVU72
@ -1258,7 +1258,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
267 .L13:
268 .cfi_def_cfa_offset 0
269 .cfi_restore 4
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 22
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 22
270 .cfi_restore 14
@ -1318,7 +1318,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
314 .loc 1 213 7 is_stmt 0 view .LVU102
315 0010 0368 ldr r3, [r0]
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 23
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 23
213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
@ -1378,7 +1378,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferErrorCallback = NULL;
351 .loc 1 232 30 is_stmt 0 view .LVU122
352 0032 E562 str r5, [r4, #44]
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 24
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 24
233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferAbortCallback = NULL;
@ -1438,7 +1438,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
392 .syntax unified
393 .thumb
394 .thumb_func
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 25
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 25
396 HAL_DMA_Start:
@ -1498,7 +1498,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
435 .loc 1 309 4 is_stmt 0 view .LVU153
436 001c 84F82030 strb r3, [r4, #32]
309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 26
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 26
437 .loc 1 309 4 is_stmt 1 view .LVU154
@ -1558,7 +1558,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
475 0046 1360 str r3, [r2]
282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
476 .loc 1 282 20 view .LVU171
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 27
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 27
477 0048 2846 mov r0, r5
@ -1618,7 +1618,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** {
523 .loc 1 337 3 discriminator 2 view .LVU182
337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 28
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 28
524 .loc 1 337 33 is_stmt 0 discriminator 2 view .LVU183
@ -1678,7 +1678,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
562 .loc 1 348 4 is_stmt 1 view .LVU200
563 0038 2046 mov r0, r4
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 29
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 29
564 003a FFF7FEFF bl DMA_SetConfig
@ -1738,7 +1738,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** }
601 .loc 1 359 9 is_stmt 0 view .LVU218
602 0064 2268 ldr r2, [r4]
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 30
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 30
359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** }
@ -1798,7 +1798,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
647 0010 80F82020 strb r2, [r0, #32]
391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
648 .loc 1 391 5 view .LVU231
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 31
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 31
393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** }
@ -1858,7 +1858,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
685 .loc 1 407 15 is_stmt 0 view .LVU249
686 0038 83F82110 strb r1, [r3, #33]
410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 32
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 32
687 .loc 1 410 3 is_stmt 1 view .LVU250
@ -1918,7 +1918,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
730 .LVL43:
430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** }
731 .loc 1 430 12 is_stmt 0 view .LVU264
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 33
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 33
732 000e 0120 movs r0, #1
@ -1978,7 +1978,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
769 .loc 1 448 5 is_stmt 1 view .LVU282
448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 34
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 34
770 .loc 1 448 5 view .LVU283
@ -2038,7 +2038,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
816 .cfi_offset 7, -16
817 .cfi_offset 8, -12
818 .cfi_offset 9, -8
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 35
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 35
819 .cfi_offset 14, -4
@ -2098,7 +2098,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** {
856 .loc 1 481 6 view .LVU311
857 0026 13F0200F tst r3, #32
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 36
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 36
858 002a 23D1 bne .L61
@ -2158,7 +2158,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** {
895 .loc 1 504 7 view .LVU329
896 004a 1942 tst r1, r3
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 37
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 37
897 004c 1BD1 bne .L63
@ -2218,7 +2218,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
933 .loc 1 483 21 is_stmt 0 view .LVU347
934 0074 4FF48073 mov r3, #256
935 0078 8363 str r3, [r0, #56]
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 38
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 38
484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** }
@ -2278,7 +2278,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
972 .loc 1 520 7 view .LVU365
520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** }
973 .loc 1 520 14 is_stmt 0 view .LVU366
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 39
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 39
974 009a BEE7 b .L49
@ -2338,7 +2338,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
1011 .cfi_endproc
1012 .LFE136:
1014 .section .text.HAL_DMA_IRQHandler,"ax",%progbits
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 40
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 40
1015 .align 1
@ -2398,7 +2398,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
1057 0014 15F0040F tst r5, #4
1058 0018 10D0 beq .L65
577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 41
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 41
1059 .loc 1 577 4 is_stmt 1 view .LVU397
@ -2458,7 +2458,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** {
1097 .loc 1 597 47 is_stmt 0 view .LVU414
1098 003c 0223 movs r3, #2
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 42
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 42
1099 003e 8B40 lsls r3, r3, r1
@ -2518,7 +2518,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
1136 006a 0023 movs r3, #0
1137 006c 80F82030 strb r3, [r0, #32]
613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 43
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 43
1138 .loc 1 613 4 view .LVU432
@ -2578,7 +2578,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
1176 0096 03FA02F2 lsl r2, r3, r2
631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
1177 .loc 1 631 32 view .LVU449
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 44
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 44
1178 009a 4A60 str r2, [r1, #4]
@ -2638,7 +2638,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
1220 0000 0346 mov r3, r0
662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
1221 .loc 1 662 3 is_stmt 1 view .LVU464
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 45
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 45
1222 .LVL74:
@ -2698,7 +2698,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
1260 .L75:
1261 002a 02 .byte (.L78-.L75)/2
1262 002b 05 .byte (.L77-.L75)/2
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 46
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 46
1263 002c 08 .byte (.L76-.L75)/2
@ -2758,7 +2758,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
1298 .loc 1 662 21 is_stmt 0 view .LVU499
1299 0042 0020 movs r0, #0
685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 47
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 47
1300 .loc 1 685 12 view .LVU500
@ -2818,7 +2818,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
1344 0016 04D0 beq .L95
752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** }
1345 .loc 1 752 12 view .LVU513
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 48
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 48
1346 0018 0120 movs r0, #1
@ -2878,7 +2878,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
1386 003c EDE7 b .L85
1387 .L89:
731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break;
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 49
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 49
1388 .loc 1 731 12 view .LVU528
@ -2938,7 +2938,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
1427 .section .text.HAL_DMA_GetState,"ax",%progbits
1428 .align 1
1429 .global HAL_DMA_GetState
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 50
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 50
1430 .syntax unified
@ -2998,49 +2998,49 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 1
1480 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h"
1481 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h"
1482 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 51
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 51
1483 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\cctOjN0y.s page 52
ARM GAS C:\Users\nived\AppData\Local\Temp\cc84oSSz.s page 52
DEFINED SYMBOLS
*ABS*:00000000 stm32f3xx_hal_dma.c
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:21 .text.DMA_SetConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:26 .text.DMA_SetConfig:00000000 DMA_SetConfig
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:97 .text.DMA_CalcBaseAndBitshift:00000000 $t
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:102 .text.DMA_CalcBaseAndBitshift:00000000 DMA_CalcBaseAndBitshift
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:156 .text.DMA_CalcBaseAndBitshift:00000034 $d
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:166 .text.HAL_DMA_Init:00000000 $t
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:172 .text.HAL_DMA_Init:00000000 HAL_DMA_Init
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:280 .text.HAL_DMA_DeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:286 .text.HAL_DMA_DeInit:00000000 HAL_DMA_DeInit
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:390 .text.HAL_DMA_Start:00000000 $t
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:396 .text.HAL_DMA_Start:00000000 HAL_DMA_Start
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:488 .text.HAL_DMA_Start_IT:00000000 $t
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:494 .text.HAL_DMA_Start_IT:00000000 HAL_DMA_Start_IT
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:618 .text.HAL_DMA_Abort:00000000 $t
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:624 .text.HAL_DMA_Abort:00000000 HAL_DMA_Abort
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:699 .text.HAL_DMA_Abort_IT:00000000 $t
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:705 .text.HAL_DMA_Abort_IT:00000000 HAL_DMA_Abort_IT
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:796 .text.HAL_DMA_PollForTransfer:00000000 $t
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:802 .text.HAL_DMA_PollForTransfer:00000000 HAL_DMA_PollForTransfer
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:1015 .text.HAL_DMA_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:1021 .text.HAL_DMA_IRQHandler:00000000 HAL_DMA_IRQHandler
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:1205 .text.HAL_DMA_RegisterCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:1211 .text.HAL_DMA_RegisterCallback:00000000 HAL_DMA_RegisterCallback
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:1261 .text.HAL_DMA_RegisterCallback:0000002a $d
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:1265 .text.HAL_DMA_RegisterCallback:0000002e $t
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:1311 .text.HAL_DMA_UnRegisterCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:1317 .text.HAL_DMA_UnRegisterCallback:00000000 HAL_DMA_UnRegisterCallback
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:1364 .text.HAL_DMA_UnRegisterCallback:0000002a $d
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:1428 .text.HAL_DMA_GetState:00000000 $t
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:1434 .text.HAL_DMA_GetState:00000000 HAL_DMA_GetState
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:1452 .text.HAL_DMA_GetError:00000000 $t
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:1458 .text.HAL_DMA_GetError:00000000 HAL_DMA_GetError
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:1369 .text.HAL_DMA_UnRegisterCallback:0000002f $d
C:\Users\nived\AppData\Local\Temp\cctOjN0y.s:1369 .text.HAL_DMA_UnRegisterCallback:00000030 $t
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:21 .text.DMA_SetConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:26 .text.DMA_SetConfig:00000000 DMA_SetConfig
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:97 .text.DMA_CalcBaseAndBitshift:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:102 .text.DMA_CalcBaseAndBitshift:00000000 DMA_CalcBaseAndBitshift
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:156 .text.DMA_CalcBaseAndBitshift:00000034 $d
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:166 .text.HAL_DMA_Init:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:172 .text.HAL_DMA_Init:00000000 HAL_DMA_Init
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:280 .text.HAL_DMA_DeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:286 .text.HAL_DMA_DeInit:00000000 HAL_DMA_DeInit
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:390 .text.HAL_DMA_Start:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:396 .text.HAL_DMA_Start:00000000 HAL_DMA_Start
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:488 .text.HAL_DMA_Start_IT:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:494 .text.HAL_DMA_Start_IT:00000000 HAL_DMA_Start_IT
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:618 .text.HAL_DMA_Abort:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:624 .text.HAL_DMA_Abort:00000000 HAL_DMA_Abort
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:699 .text.HAL_DMA_Abort_IT:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:705 .text.HAL_DMA_Abort_IT:00000000 HAL_DMA_Abort_IT
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:796 .text.HAL_DMA_PollForTransfer:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:802 .text.HAL_DMA_PollForTransfer:00000000 HAL_DMA_PollForTransfer
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:1015 .text.HAL_DMA_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:1021 .text.HAL_DMA_IRQHandler:00000000 HAL_DMA_IRQHandler
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:1205 .text.HAL_DMA_RegisterCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:1211 .text.HAL_DMA_RegisterCallback:00000000 HAL_DMA_RegisterCallback
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:1261 .text.HAL_DMA_RegisterCallback:0000002a $d
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:1265 .text.HAL_DMA_RegisterCallback:0000002e $t
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:1311 .text.HAL_DMA_UnRegisterCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:1317 .text.HAL_DMA_UnRegisterCallback:00000000 HAL_DMA_UnRegisterCallback
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:1364 .text.HAL_DMA_UnRegisterCallback:0000002a $d
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:1428 .text.HAL_DMA_GetState:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:1434 .text.HAL_DMA_GetState:00000000 HAL_DMA_GetState
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:1452 .text.HAL_DMA_GetError:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:1458 .text.HAL_DMA_GetError:00000000 HAL_DMA_GetError
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:1369 .text.HAL_DMA_UnRegisterCallback:0000002f $d
C:\Users\nived\AppData\Local\Temp\cc84oSSz.s:1369 .text.HAL_DMA_UnRegisterCallback:00000030 $t
UNDEFINED SYMBOLS
HAL_GetTick

112
build/stm32f3xx_hal_exti.lst
View File

@ -1,4 +1,4 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 1
1 .cpu cortex-m4
@ -58,7 +58,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (+) Each Exti line can be configured within this driver.
28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c ****
29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (+) Exti line can be configured in 3 different modes
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 2
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 2
30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Interrupt
@ -118,7 +118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c ****
85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Includes ------------------------------------------------------------------*/
86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** #include "stm32f3xx_hal.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 3
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 3
87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c ****
@ -178,7 +178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @retval HAL Status.
142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */
143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 4
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 4
144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** {
@ -238,7 +238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
61 .loc 1 165 3 is_stmt 1 view .LVU15
62 .loc 1 165 10 is_stmt 0 view .LVU16
63 000e C2F30043 ubfx r3, r2, #16, #1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 5
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 5
64 .LVL1:
@ -298,7 +298,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** }
183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** else
184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 6
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 6
185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval &= ~maskline;
@ -358,7 +358,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
131 004e 05F0C06C and ip, r5, #100663296
132 .LVL12:
133 .loc 1 209 8 view .LVU50
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 7
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 7
134 0052 BCF1C06F cmp ip, #100663296
@ -418,7 +418,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
161 .loc 1 236 12 is_stmt 0 view .LVU61
162 006e 1460 str r4, [r2]
237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 8
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 8
238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Configure event mode : read current mode */
@ -478,7 +478,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
198 .LVL23:
199 .loc 1 256 1 view .LVU76
200 0084 7047 bx lr
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 9
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 9
201 .LVL24:
@ -538,7 +538,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
240 .loc 1 215 14 view .LVU92
241 00a6 26EA0506 bic r6, r6, r5
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 10
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 10
242 .LVL32:
@ -598,7 +598,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
282 00c4 7047 bx lr
283 .LVL40:
284 .L13:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 11
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 11
154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** }
@ -658,7 +658,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
323 .loc 1 273 23 discriminator 1 view .LVU117
324 0004 0029 cmp r1, #0
325 0006 4CD0 beq .L29
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 12
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 12
265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** __IO uint32_t *regaddr;
@ -718,7 +718,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
361 .LVL48:
292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c ****
293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check if selected line is enable */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 13
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 13
294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((regval & maskline) != 0x00u)
@ -778,7 +778,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
395 0042 0024 movs r4, #0
396 0044 8C60 str r4, [r1, #8]
315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->GPIOSel = 0x00u;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 14
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 14
397 .loc 1 315 3 is_stmt 1 view .LVU150
@ -838,7 +838,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
432 .loc 1 334 8 is_stmt 0 view .LVU168
433 005e 0242 tst r2, r0
434 0060 03D0 beq .L27
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 15
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 15
335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** {
@ -898,7 +898,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
468 007e 4FEA9E02 lsr r2, lr, #2
344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EX
469 .loc 1 344 14 view .LVU183
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 16
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 16
470 0082 0232 adds r2, r2, #2
@ -958,7 +958,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** }
513 .loc 1 349 10 view .LVU196
514 00a6 0020 movs r0, #0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 17
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 17
515 .LVL71:
@ -1018,7 +1018,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
554 .cfi_def_cfa_offset 12
555 .cfi_offset 4, -12
556 .cfi_offset 5, -8
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 18
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 18
557 .cfi_offset 14, -4
@ -1078,7 +1078,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c ****
384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* 2] Clear event mode */
385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->EMR + (EXTI_MODE_OFFSET * offset));
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 19
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 19
595 .loc 1 385 3 is_stmt 1 view .LVU224
@ -1138,7 +1138,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
637 .loc 1 397 12 view .LVU245
638 004c 0D40 ands r5, r5, r1
639 .LVL88:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 20
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 20
398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = regval;
@ -1198,7 +1198,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
672 .loc 1 406 40 view .LVU260
673 0076 0F22 movs r2, #15
674 0078 A240 lsls r2, r2, r4
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 21
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 21
406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval;
@ -1258,7 +1258,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
725 .LVL98:
726 .LFB133:
413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 22
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 22
414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /**
@ -1318,7 +1318,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
757 .align 1
758 .global HAL_EXTI_GetHandle
759 .syntax unified
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 23
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 23
760 .thumb
@ -1378,7 +1378,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** }
789 .loc 1 464 1 view .LVU290
790 000a 7047 bx lr
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 24
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 24
791 .cfi_endproc
@ -1438,7 +1438,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
817 .loc 1 495 3 view .LVU297
818 .loc 1 495 19 is_stmt 0 view .LVU298
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 25
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 25
819 0002 0368 ldr r3, [r0]
@ -1498,7 +1498,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
858 0024 9847 blx r3
859 .LVL114:
860 .L57:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 26
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 26
511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** }
@ -1558,7 +1558,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_PENDING_EDGE(Edge));
893 .loc 1 535 3 view .LVU326
536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 27
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 27
537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* compute line register offset and line mask */
@ -1618,7 +1618,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
938 .global HAL_EXTI_ClearPending
939 .syntax unified
940 .thumb
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 28
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 28
941 .thumb_func
@ -1678,7 +1678,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c ****
573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Get pending bit */
574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->PR + (EXTI_CONFIG_OFFSET * offset));
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 29
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 29
972 .loc 1 574 3 is_stmt 1 view .LVU357
@ -1738,7 +1738,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
1010 .loc 1 593 3 view .LVU368
594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 30
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 30
595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* compute line register offset and line mask */
@ -1786,35 +1786,35 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 1
1047 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
1048 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h"
1049 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccT69dI2.s page 31
ARM GAS C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s page 31
DEFINED SYMBOLS
*ABS*:00000000 stm32f3xx_hal_exti.c
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:21 .text.HAL_EXTI_SetConfigLine:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:27 .text.HAL_EXTI_SetConfigLine:00000000 HAL_EXTI_SetConfigLine
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:293 .text.HAL_EXTI_SetConfigLine:000000cc $d
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:301 .text.HAL_EXTI_GetConfigLine:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:307 .text.HAL_EXTI_GetConfigLine:00000000 HAL_EXTI_GetConfigLine
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:522 .text.HAL_EXTI_GetConfigLine:000000ac $d
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:530 .text.HAL_EXTI_ClearConfigLine:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:536 .text.HAL_EXTI_ClearConfigLine:00000000 HAL_EXTI_ClearConfigLine
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:710 .text.HAL_EXTI_ClearConfigLine:00000090 $d
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:718 .text.HAL_EXTI_RegisterCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:724 .text.HAL_EXTI_RegisterCallback:00000000 HAL_EXTI_RegisterCallback
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:757 .text.HAL_EXTI_GetHandle:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:763 .text.HAL_EXTI_GetHandle:00000000 HAL_EXTI_GetHandle
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:795 .text.HAL_EXTI_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:801 .text.HAL_EXTI_IRQHandler:00000000 HAL_EXTI_IRQHandler
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:866 .text.HAL_EXTI_IRQHandler:00000028 $d
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:872 .text.HAL_EXTI_GetPending:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:878 .text.HAL_EXTI_GetPending:00000000 HAL_EXTI_GetPending
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:932 .text.HAL_EXTI_GetPending:0000001c $d
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:937 .text.HAL_EXTI_ClearPending:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:943 .text.HAL_EXTI_ClearPending:00000000 HAL_EXTI_ClearPending
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:987 .text.HAL_EXTI_ClearPending:00000018 $d
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:992 .text.HAL_EXTI_GenerateSWI:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:998 .text.HAL_EXTI_GenerateSWI:00000000 HAL_EXTI_GenerateSWI
C:\Users\nived\AppData\Local\Temp\ccT69dI2.s:1039 .text.HAL_EXTI_GenerateSWI:00000018 $d
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:21 .text.HAL_EXTI_SetConfigLine:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:27 .text.HAL_EXTI_SetConfigLine:00000000 HAL_EXTI_SetConfigLine
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:293 .text.HAL_EXTI_SetConfigLine:000000cc $d
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:301 .text.HAL_EXTI_GetConfigLine:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:307 .text.HAL_EXTI_GetConfigLine:00000000 HAL_EXTI_GetConfigLine
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:522 .text.HAL_EXTI_GetConfigLine:000000ac $d
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:530 .text.HAL_EXTI_ClearConfigLine:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:536 .text.HAL_EXTI_ClearConfigLine:00000000 HAL_EXTI_ClearConfigLine
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:710 .text.HAL_EXTI_ClearConfigLine:00000090 $d
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:718 .text.HAL_EXTI_RegisterCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:724 .text.HAL_EXTI_RegisterCallback:00000000 HAL_EXTI_RegisterCallback
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:757 .text.HAL_EXTI_GetHandle:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:763 .text.HAL_EXTI_GetHandle:00000000 HAL_EXTI_GetHandle
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:795 .text.HAL_EXTI_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:801 .text.HAL_EXTI_IRQHandler:00000000 HAL_EXTI_IRQHandler
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:866 .text.HAL_EXTI_IRQHandler:00000028 $d
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:872 .text.HAL_EXTI_GetPending:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:878 .text.HAL_EXTI_GetPending:00000000 HAL_EXTI_GetPending
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:932 .text.HAL_EXTI_GetPending:0000001c $d
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:937 .text.HAL_EXTI_ClearPending:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:943 .text.HAL_EXTI_ClearPending:00000000 HAL_EXTI_ClearPending
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:987 .text.HAL_EXTI_ClearPending:00000018 $d
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:992 .text.HAL_EXTI_GenerateSWI:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:998 .text.HAL_EXTI_GenerateSWI:00000000 HAL_EXTI_GenerateSWI
C:\Users\nived\AppData\Local\Temp\cc2FUR2z.s:1039 .text.HAL_EXTI_GenerateSWI:00000018 $d
NO UNDEFINED SYMBOLS

158
build/stm32f3xx_hal_flash.lst
View File

@ -1,4 +1,4 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 1
1 .cpu cortex-m4
@ -58,7 +58,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Option Bytes programming
29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c ****
30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 2
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 2
31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ##### How to use this driver #####
@ -118,7 +118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @addtogroup STM32F3xx_HAL_Driver
86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{
87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 3
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 3
88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c ****
@ -178,7 +178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** *
143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** @verbatim
144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** @endverbatim
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 4
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 4
145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{
@ -238,7 +238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c ****
200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** for (index = 0U; index < nbiterations; index++)
201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 5
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 5
202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
@ -298,7 +298,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** {
257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program halfword (16-bit) at a specified address. */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 6
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 6
259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.DataRemaining = 1U;
@ -358,7 +358,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** {
315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 7
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 7
316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** {
@ -418,7 +418,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Shift to have next 16-bit data */
371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Data = (pFlash.Data >> 16U);
372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 8
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 8
373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Operation is completed, disable the PG Bit */
@ -478,7 +478,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** {
429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 9
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 9
430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** UNUSED(ReturnValue);
@ -538,7 +538,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Authorize the FLASH Registers access */
485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** WRITE_REG(FLASH->KEYR, FLASH_KEY1);
486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** WRITE_REG(FLASH->KEYR, FLASH_KEY2);
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 10
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 10
487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c ****
@ -598,7 +598,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c ****
542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /**
543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Launch the option byte loading.
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 11
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 11
544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @note This function will reset automatically the MCU.
@ -658,7 +658,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param Address specify the address to be programmed.
599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param Data specify the data to be programmed.
600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval None
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 12
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 12
601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */
@ -718,7 +718,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** Even if the FLASH operation fails, the BUSY flag will be reset and an error
623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** flag will be set */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 13
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 13
624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c ****
@ -778,7 +778,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
76 .loc 1 666 5 view .LVU11
77 0004 13F01003 ands r3, r3, #16
78 0008 05D0 beq .L5
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 14
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 14
667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** {
@ -838,7 +838,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
121 .cfi_endproc
122 .LFE143:
124 .section .text.HAL_FLASH_Program_IT,"ax",%progbits
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 15
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 15
125 .align 1
@ -898,7 +898,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
168 .loc 1 250 3 discriminator 2 view .LVU38
169 0018 1349 ldr r1, .L18+4
170 .LVL9:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 16
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 16
250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c ****
@ -958,7 +958,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
208 0046 38BD pop {r3, r4, r5, pc}
209 .LVL11:
210 .L16:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 17
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 17
257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program halfword (16-bit) at a specified address. */
@ -1018,7 +1018,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
256 .loc 1 428 1 is_stmt 1 view -0
257 .cfi_startproc
258 @ args = 0, pretend = 0, frame = 0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 18
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 18
259 @ frame_needed = 0, uses_anonymous_args = 0
@ -1078,7 +1078,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
310 .LVL16:
289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** {
311 .loc 1 289 3 view .LVU74
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 19
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 19
289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** {
@ -1138,7 +1138,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
351 .loc 1 307 5 view .LVU89
352 0032 13F0200F tst r3, #32
353 0036 2BD0 beq .L25
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 20
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 20
310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c ****
@ -1198,7 +1198,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
392 0064 4FD1 bne .L37
383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** {
393 .loc 1 383 11 is_stmt 1 view .LVU106
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 21
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 21
383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** {
@ -1258,7 +1258,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
433 0094 5BB9 cbnz r3, .L22
408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c ****
434 .loc 1 408 5 is_stmt 1 view .LVU122
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 22
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 22
435 0096 2D4B ldr r3, .L40
@ -1318,7 +1318,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Address = addresstmp;
474 .loc 1 328 30 is_stmt 0 view .LVU138
475 00c4 A068 ldr r0, [r4, #8]
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 23
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 23
328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Address = addresstmp;
@ -1378,7 +1378,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
517 .LVL29:
356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** }
518 .loc 1 356 11 view .LVU152
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 24
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 24
356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** }
@ -1438,7 +1438,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
558 0134 ACE7 b .L25
559 .LVL32:
560 .L38:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 25
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 25
385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** }
@ -1498,7 +1498,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** {
607 .loc 1 482 5 view .LVU178
608 0004 13F0800F tst r3, #128
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 26
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 26
609 0008 0BD0 beq .L44
@ -1558,7 +1558,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
655 @ args = 0, pretend = 0, frame = 0
656 @ frame_needed = 0, uses_anonymous_args = 0
657 @ link register save eliminated.
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 27
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 27
505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c ****
@ -1618,7 +1618,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
703 .loc 1 527 10 is_stmt 0 view .LVU199
704 0016 0020 movs r0, #0
705 0018 7047 bx lr
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 28
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 28
706 .L53:
@ -1678,7 +1678,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return pFlash.ErrorCode;
758 .loc 1 580 1 is_stmt 1 view -0
759 .cfi_startproc
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 29
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 29
760 @ args = 0, pretend = 0, frame = 0
@ -1738,7 +1738,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** {
807 .loc 1 627 9 view .LVU216
808 000a 144B ldr r3, .L73
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 30
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 30
809 000c DB68 ldr r3, [r3, #12]
@ -1798,7 +1798,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
848 003c DB68 ldr r3, [r3, #12]
645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
849 .loc 1 645 5 view .LVU232
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 31
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 31
850 003e 13F0100F tst r3, #16
@ -1858,7 +1858,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
897 .cfi_offset 4, -28
898 .cfi_offset 5, -24
899 .cfi_offset 6, -20
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 32
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 32
900 .cfi_offset 7, -16
@ -1918,7 +1918,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
938 .loc 1 184 5 is_stmt 1 view .LVU257
184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** {
939 .loc 1 184 7 is_stmt 0 view .LVU258
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 33
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 33
940 0026 012C cmp r4, #1
@ -1978,7 +1978,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
980 .loc 1 202 70 view .LVU272
981 004c C1F12002 rsb r2, r1, #32
982 0050 A1F12003 sub r3, r1, #32
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 34
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 34
983 .LVL54:
@ -2038,7 +2038,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
1025 .L81:
173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c ****
1026 .loc 1 173 3 view .LVU285
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 35
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 35
1027 0092 0223 movs r3, #2
@ -2098,7 +2098,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
1079 00000000
1079 00000000
1079 00000000
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 36
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 36
1080 .text
@ -2110,53 +2110,53 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 1
1086 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h"
1087 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h"
1088 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccvSeb44.s page 37
ARM GAS C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s page 37
DEFINED SYMBOLS
*ABS*:00000000 stm32f3xx_hal_flash.c
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:21 .text.FLASH_Program_HalfWord:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:26 .text.FLASH_Program_HalfWord:00000000 FLASH_Program_HalfWord
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:52 .text.FLASH_Program_HalfWord:00000014 $d
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:1078 .bss.pFlash:00000000 pFlash
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:58 .text.FLASH_SetErrorCode:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:63 .text.FLASH_SetErrorCode:00000000 FLASH_SetErrorCode
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:119 .text.FLASH_SetErrorCode:00000034 $d
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:125 .text.HAL_FLASH_Program_IT:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:131 .text.HAL_FLASH_Program_IT:00000000 HAL_FLASH_Program_IT
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:241 .text.HAL_FLASH_Program_IT:00000064 $d
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:247 .text.HAL_FLASH_EndOfOperationCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:253 .text.HAL_FLASH_EndOfOperationCallback:00000000 HAL_FLASH_EndOfOperationCallback
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:268 .text.HAL_FLASH_OperationErrorCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:274 .text.HAL_FLASH_OperationErrorCallback:00000000 HAL_FLASH_OperationErrorCallback
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:289 .text.HAL_FLASH_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:295 .text.HAL_FLASH_IRQHandler:00000000 HAL_FLASH_IRQHandler
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:582 .text.HAL_FLASH_IRQHandler:0000014c $d
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:588 .text.HAL_FLASH_Unlock:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:594 .text.HAL_FLASH_Unlock:00000000 HAL_FLASH_Unlock
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:639 .text.HAL_FLASH_Unlock:0000002c $d
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:645 .text.HAL_FLASH_Lock:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:651 .text.HAL_FLASH_Lock:00000000 HAL_FLASH_Lock
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:670 .text.HAL_FLASH_Lock:00000010 $d
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:675 .text.HAL_FLASH_OB_Unlock:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:681 .text.HAL_FLASH_OB_Unlock:00000000 HAL_FLASH_OB_Unlock
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:714 .text.HAL_FLASH_OB_Unlock:00000020 $d
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:720 .text.HAL_FLASH_OB_Lock:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:726 .text.HAL_FLASH_OB_Lock:00000000 HAL_FLASH_OB_Lock
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:745 .text.HAL_FLASH_OB_Lock:00000010 $d
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:750 .text.HAL_FLASH_GetError:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:756 .text.HAL_FLASH_GetError:00000000 HAL_FLASH_GetError
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:772 .text.HAL_FLASH_GetError:00000008 $d
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:777 .text.FLASH_WaitForLastOperation:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:783 .text.FLASH_WaitForLastOperation:00000000 FLASH_WaitForLastOperation
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:875 .text.FLASH_WaitForLastOperation:0000005c $d
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:880 .text.HAL_FLASH_Program:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:886 .text.HAL_FLASH_Program:00000000 HAL_FLASH_Program
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:1032 .text.HAL_FLASH_Program:00000098 $d
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:1038 .text.HAL_FLASH_OB_Launch:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:1044 .text.HAL_FLASH_OB_Launch:00000000 HAL_FLASH_OB_Launch
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:1069 .text.HAL_FLASH_OB_Launch:00000018 $d
C:\Users\nived\AppData\Local\Temp\ccvSeb44.s:1075 .bss.pFlash:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:21 .text.FLASH_Program_HalfWord:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:26 .text.FLASH_Program_HalfWord:00000000 FLASH_Program_HalfWord
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:52 .text.FLASH_Program_HalfWord:00000014 $d
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:1078 .bss.pFlash:00000000 pFlash
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:58 .text.FLASH_SetErrorCode:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:63 .text.FLASH_SetErrorCode:00000000 FLASH_SetErrorCode
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:119 .text.FLASH_SetErrorCode:00000034 $d
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:125 .text.HAL_FLASH_Program_IT:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:131 .text.HAL_FLASH_Program_IT:00000000 HAL_FLASH_Program_IT
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:241 .text.HAL_FLASH_Program_IT:00000064 $d
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:247 .text.HAL_FLASH_EndOfOperationCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:253 .text.HAL_FLASH_EndOfOperationCallback:00000000 HAL_FLASH_EndOfOperationCallback
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:268 .text.HAL_FLASH_OperationErrorCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:274 .text.HAL_FLASH_OperationErrorCallback:00000000 HAL_FLASH_OperationErrorCallback
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:289 .text.HAL_FLASH_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:295 .text.HAL_FLASH_IRQHandler:00000000 HAL_FLASH_IRQHandler
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:582 .text.HAL_FLASH_IRQHandler:0000014c $d
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:588 .text.HAL_FLASH_Unlock:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:594 .text.HAL_FLASH_Unlock:00000000 HAL_FLASH_Unlock
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:639 .text.HAL_FLASH_Unlock:0000002c $d
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:645 .text.HAL_FLASH_Lock:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:651 .text.HAL_FLASH_Lock:00000000 HAL_FLASH_Lock
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:670 .text.HAL_FLASH_Lock:00000010 $d
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:675 .text.HAL_FLASH_OB_Unlock:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:681 .text.HAL_FLASH_OB_Unlock:00000000 HAL_FLASH_OB_Unlock
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:714 .text.HAL_FLASH_OB_Unlock:00000020 $d
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:720 .text.HAL_FLASH_OB_Lock:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:726 .text.HAL_FLASH_OB_Lock:00000000 HAL_FLASH_OB_Lock
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:745 .text.HAL_FLASH_OB_Lock:00000010 $d
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:750 .text.HAL_FLASH_GetError:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:756 .text.HAL_FLASH_GetError:00000000 HAL_FLASH_GetError
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:772 .text.HAL_FLASH_GetError:00000008 $d
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:777 .text.FLASH_WaitForLastOperation:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:783 .text.FLASH_WaitForLastOperation:00000000 FLASH_WaitForLastOperation
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:875 .text.FLASH_WaitForLastOperation:0000005c $d
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:880 .text.HAL_FLASH_Program:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:886 .text.HAL_FLASH_Program:00000000 HAL_FLASH_Program
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:1032 .text.HAL_FLASH_Program:00000098 $d
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:1038 .text.HAL_FLASH_OB_Launch:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:1044 .text.HAL_FLASH_OB_Launch:00000000 HAL_FLASH_OB_Launch
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:1069 .text.HAL_FLASH_OB_Launch:00000018 $d
C:\Users\nived\AppData\Local\Temp\ccQ5UPcF.s:1075 .bss.pFlash:00000000 $d
UNDEFINED SYMBOLS
FLASH_PageErase

238
build/stm32f3xx_hal_flash_ex.lst
View File

@ -1,4 +1,4 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 1
1 .cpu cortex-m4
@ -58,7 +58,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @attention
30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** *
31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * Copyright (c) 2016 STMicroelectronics.
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 2
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 2
32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * All rights reserved.
@ -118,7 +118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @}
87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */
88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 3
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 3
89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Private variables ---------------------------------------------------------*/
@ -178,7 +178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Perform a mass erase or erase the specified FLASH memory pages
144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * must be called before.
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 4
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 4
146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * Call the @ref HAL_FLASH_Lock() to disable the flash memory access
@ -238,7 +238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** address += FLASH_PAGE_SIZE)
202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 5
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 5
203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** FLASH_PageErase(address);
@ -298,7 +298,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** {
259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /*Mass erase to be done*/
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 6
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 6
260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
@ -358,7 +358,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR;
315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Get the actual read protection Option Byte value */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 7
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 7
317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** rdptmp = FLASH_OB_GetRDP();
@ -418,7 +418,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** {
373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_WRPSTATE(pOBInit->WRPState));
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 8
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 8
374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)
@ -478,7 +478,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Process Unlocked */
429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash);
430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 9
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 9
431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status;
@ -538,7 +538,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /**
486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @}
487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 10
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 10
488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
@ -598,7 +598,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /**
509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Enable the write protection of the desired pages
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 11
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 11
510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note An option byte erase is done automatically in this function.
@ -658,7 +658,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* To be able to write again option byte, need to perform a option byte erase */
566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = HAL_FLASHEx_OBErase();
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 12
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 12
567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status == HAL_OK)
@ -718,7 +718,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Disable the write protection of the desired pages
622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note An option byte erase is done automatically in this function.
623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note When the memory read protection level is selected (RDP level = 1),
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 13
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 13
624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * it is not possible to program or erase the flash page i if
@ -778,7 +778,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* To be able to write again option byte, need to perform a option byte erase */
679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = HAL_FLASHEx_OBErase();
680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status == HAL_OK)
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 14
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 14
681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** {
@ -838,7 +838,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_0 No protection
736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_2 Full chip protection
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 15
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 15
738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
@ -898,7 +898,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** {
794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 16
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 16
795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
@ -958,7 +958,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */
851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_DATA_ADDRESS(Address));
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 17
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 17
852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
@ -1018,7 +1018,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
89 FLASH_OB_GetRDP:
90 .LFB143:
884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 18
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 18
885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /**
@ -1078,7 +1078,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
115 .L9:
910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** }
116 .loc 1 910 12 view .LVU20
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 19
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 19
117 0012 CC20 movs r0, #204
@ -1138,7 +1138,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
160 0008 FFF7FEFF bl FLASH_WaitForLastOperation
161 .LVL5:
751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 20
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 20
162 .loc 1 751 3 is_stmt 1 view .LVU30
@ -1198,7 +1198,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
203 .loc 1 771 7 view .LVU44
204 0044 074B ldr r3, .L17+8
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 21
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 21
205 0046 1D80 strh r5, [r3] @ movhi
@ -1258,7 +1258,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET)));
252 .loc 1 799 3 view .LVU54
800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON)));
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 22
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 22
253 .loc 1 800 3 view .LVU55
@ -1318,7 +1318,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
291 002c FFF7FEFF bl FLASH_WaitForLastOperation
292 .LVL17:
828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 23
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 23
293 .loc 1 828 5 is_stmt 1 view .LVU72
@ -1378,7 +1378,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
340 .loc 1 856 5 is_stmt 0 view .LVU81
341 000e 00B1 cbz r0, .L28
342 .L26:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 24
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 24
343 .LVL22:
@ -1438,7 +1438,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /**
923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Return the FLASH User Option Byte value.
924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nB
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 25
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 25
925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
@ -1498,7 +1498,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
33:Drivers/CMSIS/Include/cmsis_gcc.h ****
34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 26
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 26
36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0)
@ -1558,7 +1558,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 27
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 27
93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
@ -1618,7 +1618,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register
148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register.
149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 28
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 28
150:Drivers/CMSIS/Include/cmsis_gcc.h **** */
@ -1678,7 +1678,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
204:Drivers/CMSIS/Include/cmsis_gcc.h **** */
205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
206:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 29
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 29
207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
@ -1738,7 +1738,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
261:Drivers/CMSIS/Include/cmsis_gcc.h **** */
262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
263:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 30
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 30
264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
@ -1798,7 +1798,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
319:Drivers/CMSIS/Include/cmsis_gcc.h ****
320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 31
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 31
321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
@ -1858,7 +1858,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
375:Drivers/CMSIS/Include/cmsis_gcc.h ****
376:Drivers/CMSIS/Include/cmsis_gcc.h ****
377:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 32
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 32
378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask
@ -1918,7 +1918,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
434:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 33
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 33
435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ
@ -1978,7 +1978,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
490:Drivers/CMSIS/Include/cmsis_gcc.h **** */
491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 34
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 34
492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
@ -2038,7 +2038,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
548:Drivers/CMSIS/Include/cmsis_gcc.h **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 35
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 35
549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
@ -2098,7 +2098,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
603:Drivers/CMSIS/Include/cmsis_gcc.h **** }
604:Drivers/CMSIS/Include/cmsis_gcc.h ****
605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 36
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 36
606:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
@ -2158,7 +2158,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 37
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 37
663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
@ -2218,7 +2218,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit
718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 38
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 38
720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
@ -2278,7 +2278,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr();
775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 39
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 39
777:Drivers/CMSIS/Include/cmsis_gcc.h ****
@ -2338,7 +2338,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
831:Drivers/CMSIS/Include/cmsis_gcc.h ****
832:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 40
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 40
834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes.
@ -2398,7 +2398,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
889:Drivers/CMSIS/Include/cmsis_gcc.h **** {
890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory");
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 41
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 41
891:Drivers/CMSIS/Include/cmsis_gcc.h **** }
@ -2458,7 +2458,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
945:Drivers/CMSIS/Include/cmsis_gcc.h ****
946:Drivers/CMSIS/Include/cmsis_gcc.h ****
947:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 42
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 42
948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit)
@ -2518,7 +2518,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */
993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U)
994:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 43
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 43
995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U;
@ -2578,7 +2578,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
456 .loc 1 317 12 is_stmt 0 view .LVU108
457 0002 FFF7FEFF bl FLASH_OB_GetRDP
458 .LVL28:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 44
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 44
317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
@ -2638,7 +2638,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
499 003a 2361 str r3, [r4, #16]
337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** {
500 .loc 1 337 5 view .LVU123
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 45
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 45
337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** {
@ -2698,7 +2698,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
547 .loc 1 524 3 view .LVU133
527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP2_WRP2 */
548 .loc 1 527 3 view .LVU134
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 46
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 46
530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP3_WRP3 */
@ -2758,7 +2758,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
585 .LVL46:
586 .L41:
617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 47
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 47
587 .loc 1 617 3 is_stmt 1 view .LVU153
@ -2818,7 +2818,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** {
627 .loc 1 593 9 is_stmt 0 view .LVU168
628 004c 23B9 cbnz r3, .L45
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 48
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 48
593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** {
@ -2878,7 +2878,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
670 .loc 1 585 9 is_stmt 1 view .LVU182
585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 49
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 49
671 .loc 1 585 11 is_stmt 0 view .LVU183
@ -2938,7 +2938,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
711 .L51:
605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
712 .loc 1 605 9 is_stmt 1 view .LVU198
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 50
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 50
605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
@ -2998,7 +2998,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
761 0002 0446 mov r4, r0
633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint16_t WRP0_Data = 0xFFFFU;
762 .loc 1 633 3 is_stmt 1 view .LVU207
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 51
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 51
763 .LVL69:
@ -3058,7 +3058,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
798 .LVL77:
673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** {
799 .loc 1 673 3 is_stmt 1 view .LVU227
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 52
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 52
673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** {
@ -3118,7 +3118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
839 .loc 1 695 29 discriminator 1 view .LVU242
840 0046 FF2F cmp r7, #255
841 0048 16D1 bne .L63
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 53
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 53
842 .L58:
@ -3178,7 +3178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
882 .loc 1 690 18 view .LVU256
883 0076 E5E7 b .L56
884 .L63:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 54
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 54
697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
@ -3238,7 +3238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
925 .loc 1 717 9 is_stmt 1 view .LVU271
717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 55
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 55
926 .loc 1 717 11 is_stmt 0 view .LVU272
@ -3298,7 +3298,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
973 0006 44D0 beq .L76
361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR;
974 .loc 1 361 1 is_stmt 0 discriminator 2 view .LVU282
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 56
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 56
975 0008 10B5 push {r4, lr}
@ -3358,7 +3358,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
1012 0028 1B4B ldr r3, .L86
1013 002a 0022 movs r2, #0
1014 002c 1A76 strb r2, [r3, #24]
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 57
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 57
387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status;
@ -3418,7 +3418,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** {
1053 .loc 1 417 5 view .LVU316
1054 004c 13F0080F tst r3, #8
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 58
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 58
1055 0050 15D1 bne .L85
@ -3478,7 +3478,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
1092 006c 607B ldrb r0, [r4, #13] @ zero_extendqisi2
1093 .LVL106:
407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status != HAL_OK)
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 59
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 59
1094 .loc 1 407 14 view .LVU334
@ -3538,7 +3538,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
1131 0090 E2E7 b .L69
1132 .LVL110:
1133 .L76:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 60
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 60
1134 .cfi_def_cfa_offset 0
@ -3598,7 +3598,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
1180 .loc 1 449 23 is_stmt 0 view .LVU362
1181 000e FFF7FEFF bl FLASH_OB_GetRDP
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 61
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 61
1182 .LVL114:
@ -3658,7 +3658,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
1225 .LVL118:
1226 .LBB10:
1227 .LBI10:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 62
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 62
981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
@ -3718,7 +3718,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
1269 .syntax unified
1270 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1271 002a 93FAA3F3 rbit r3, r3
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 63
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 63
1272 @ 0 "" 2
@ -3778,7 +3778,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The value of this parameter depend on device used within the same series
954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** *
955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval None
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 64
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 64
956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */
@ -3838,7 +3838,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
1349 @ frame_needed = 0, uses_anonymous_args = 0
159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint32_t address = 0U;
1350 .loc 1 159 3 view .LVU404
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 65
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 65
160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
@ -3898,7 +3898,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
1389 0022 88BB cbnz r0, .L108
196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
1390 .loc 1 196 9 is_stmt 1 view .LVU421
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 66
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 66
196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ****
@ -3958,7 +3958,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** {
1430 .loc 1 201 21 is_stmt 1 view .LVU437
1431 0056 04F50064 add r4, r4, #2048
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 67
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 67
1432 .LVL134:
@ -4018,7 +4018,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
1473 .LVL142:
1474 .L108:
159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint32_t address = 0U;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 68
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 68
1475 .loc 1 159 21 is_stmt 0 view .LVU451
@ -4078,7 +4078,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
1522 .loc 1 239 1 is_stmt 1 view -0
1523 .cfi_startproc
1524 @ args = 0, pretend = 0, frame = 0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 69
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 69
1525 @ frame_needed = 0, uses_anonymous_args = 0
@ -4138,7 +4138,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
1563 .loc 1 269 5 view .LVU476
271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.DataRemaining = pEraseInit->NbPages;
1564 .loc 1 271 5 view .LVU477
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 70
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 70
271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.DataRemaining = pEraseInit->NbPages;
@ -4198,7 +4198,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** }
1605 .loc 1 248 12 view .LVU492
1606 004e 0124 movs r4, #1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 71
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 71
1607 0050 F3E7 b .L119
@ -4217,58 +4217,58 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 1
1621 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h"
1622 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h"
1623 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s page 72
ARM GAS C:\Users\nived\AppData\Local\Temp\cci6gvs3.s page 72
DEFINED SYMBOLS
*ABS*:00000000 stm32f3xx_hal_flash_ex.c
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:21 .text.FLASH_MassErase:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:26 .text.FLASH_MassErase:00000000 FLASH_MassErase
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:52 .text.FLASH_MassErase:0000001c $d
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:58 .text.FLASH_OB_GetWRP:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:63 .text.FLASH_OB_GetWRP:00000000 FLASH_OB_GetWRP
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:79 .text.FLASH_OB_GetWRP:00000008 $d
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:84 .text.FLASH_OB_GetRDP:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:89 .text.FLASH_OB_GetRDP:00000000 FLASH_OB_GetRDP
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:127 .text.FLASH_OB_GetRDP:0000001c $d
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:132 .text.FLASH_OB_RDP_LevelConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:137 .text.FLASH_OB_RDP_LevelConfig:00000000 FLASH_OB_RDP_LevelConfig
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:221 .text.FLASH_OB_RDP_LevelConfig:0000005c $d
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:228 .text.FLASH_OB_UserConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:233 .text.FLASH_OB_UserConfig:00000000 FLASH_OB_UserConfig
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:301 .text.FLASH_OB_UserConfig:0000003c $d
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:308 .text.FLASH_OB_ProgramData:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:313 .text.FLASH_OB_ProgramData:00000000 FLASH_OB_ProgramData
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:375 .text.FLASH_OB_ProgramData:00000038 $d
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:381 .text.FLASH_OB_GetUser:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:386 .text.FLASH_OB_GetUser:00000000 FLASH_OB_GetUser
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:429 .text.FLASH_OB_GetUser:0000001c $d
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:434 .text.HAL_FLASHEx_OBErase:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:440 .text.HAL_FLASHEx_OBErase:00000000 HAL_FLASHEx_OBErase
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:516 .text.HAL_FLASHEx_OBErase:00000048 $d
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:522 .text.FLASH_OB_EnableWRP:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:527 .text.FLASH_OB_EnableWRP:00000000 FLASH_OB_EnableWRP
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:733 .text.FLASH_OB_EnableWRP:000000b8 $d
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:740 .text.FLASH_OB_DisableWRP:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:745 .text.FLASH_OB_DisableWRP:00000000 FLASH_OB_DisableWRP
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:947 .text.FLASH_OB_DisableWRP:000000bc $d
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:954 .text.HAL_FLASHEx_OBProgram:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:960 .text.HAL_FLASHEx_OBProgram:00000000 HAL_FLASHEx_OBProgram
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:1145 .text.HAL_FLASHEx_OBProgram:00000098 $d
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:1150 .text.HAL_FLASHEx_OBGetConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:1156 .text.HAL_FLASHEx_OBGetConfig:00000000 HAL_FLASHEx_OBGetConfig
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:1198 .text.HAL_FLASHEx_OBGetUserData:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:1204 .text.HAL_FLASHEx_OBGetUserData:00000000 HAL_FLASHEx_OBGetUserData
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:1290 .text.HAL_FLASHEx_OBGetUserData:00000038 $d
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:1296 .text.FLASH_PageErase:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:1302 .text.FLASH_PageErase:00000000 FLASH_PageErase
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:1331 .text.FLASH_PageErase:0000001c $d
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:1337 .text.HAL_FLASHEx_Erase:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:1343 .text.HAL_FLASHEx_Erase:00000000 HAL_FLASHEx_Erase
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:1507 .text.HAL_FLASHEx_Erase:0000009c $d
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:1513 .text.HAL_FLASHEx_Erase_IT:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:1519 .text.HAL_FLASHEx_Erase_IT:00000000 HAL_FLASHEx_Erase_IT
C:\Users\nived\AppData\Local\Temp\ccB9ovYa.s:1611 .text.HAL_FLASHEx_Erase_IT:00000054 $d
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:21 .text.FLASH_MassErase:00000000 $t
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:26 .text.FLASH_MassErase:00000000 FLASH_MassErase
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:52 .text.FLASH_MassErase:0000001c $d
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:58 .text.FLASH_OB_GetWRP:00000000 $t
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:63 .text.FLASH_OB_GetWRP:00000000 FLASH_OB_GetWRP
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:79 .text.FLASH_OB_GetWRP:00000008 $d
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:84 .text.FLASH_OB_GetRDP:00000000 $t
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:89 .text.FLASH_OB_GetRDP:00000000 FLASH_OB_GetRDP
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:127 .text.FLASH_OB_GetRDP:0000001c $d
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:132 .text.FLASH_OB_RDP_LevelConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:137 .text.FLASH_OB_RDP_LevelConfig:00000000 FLASH_OB_RDP_LevelConfig
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:221 .text.FLASH_OB_RDP_LevelConfig:0000005c $d
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:228 .text.FLASH_OB_UserConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:233 .text.FLASH_OB_UserConfig:00000000 FLASH_OB_UserConfig
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:301 .text.FLASH_OB_UserConfig:0000003c $d
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:308 .text.FLASH_OB_ProgramData:00000000 $t
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:313 .text.FLASH_OB_ProgramData:00000000 FLASH_OB_ProgramData
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:375 .text.FLASH_OB_ProgramData:00000038 $d
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:381 .text.FLASH_OB_GetUser:00000000 $t
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:386 .text.FLASH_OB_GetUser:00000000 FLASH_OB_GetUser
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:429 .text.FLASH_OB_GetUser:0000001c $d
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:434 .text.HAL_FLASHEx_OBErase:00000000 $t
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:440 .text.HAL_FLASHEx_OBErase:00000000 HAL_FLASHEx_OBErase
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:516 .text.HAL_FLASHEx_OBErase:00000048 $d
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:522 .text.FLASH_OB_EnableWRP:00000000 $t
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:527 .text.FLASH_OB_EnableWRP:00000000 FLASH_OB_EnableWRP
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:733 .text.FLASH_OB_EnableWRP:000000b8 $d
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:740 .text.FLASH_OB_DisableWRP:00000000 $t
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:745 .text.FLASH_OB_DisableWRP:00000000 FLASH_OB_DisableWRP
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:947 .text.FLASH_OB_DisableWRP:000000bc $d
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:954 .text.HAL_FLASHEx_OBProgram:00000000 $t
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:960 .text.HAL_FLASHEx_OBProgram:00000000 HAL_FLASHEx_OBProgram
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:1145 .text.HAL_FLASHEx_OBProgram:00000098 $d
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:1150 .text.HAL_FLASHEx_OBGetConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:1156 .text.HAL_FLASHEx_OBGetConfig:00000000 HAL_FLASHEx_OBGetConfig
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:1198 .text.HAL_FLASHEx_OBGetUserData:00000000 $t
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:1204 .text.HAL_FLASHEx_OBGetUserData:00000000 HAL_FLASHEx_OBGetUserData
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:1290 .text.HAL_FLASHEx_OBGetUserData:00000038 $d
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:1296 .text.FLASH_PageErase:00000000 $t
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:1302 .text.FLASH_PageErase:00000000 FLASH_PageErase
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:1331 .text.FLASH_PageErase:0000001c $d
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:1337 .text.HAL_FLASHEx_Erase:00000000 $t
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:1343 .text.HAL_FLASHEx_Erase:00000000 HAL_FLASHEx_Erase
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:1507 .text.HAL_FLASHEx_Erase:0000009c $d
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:1513 .text.HAL_FLASHEx_Erase_IT:00000000 $t
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:1519 .text.HAL_FLASHEx_Erase_IT:00000000 HAL_FLASHEx_Erase_IT
C:\Users\nived\AppData\Local\Temp\cci6gvs3.s:1611 .text.HAL_FLASHEx_Erase_IT:00000054 $d
UNDEFINED SYMBOLS
pFlash

96
build/stm32f3xx_hal_gpio.lst
View File

@ -1,4 +1,4 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 1
1 .cpu cortex-m4
@ -58,7 +58,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** configured by software in several modes:
29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (++) Input mode
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 2
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 2
30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (++) Analog mode
@ -118,7 +118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (#) To set/reset the level of a pin configured in output mode use
85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 3
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 3
87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
@ -178,7 +178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /**
142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @}
143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 4
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 4
144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Private variables ---------------------------------------------------------*/
@ -238,7 +238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
49 .loc 1 179 3 view .LVU6
180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 5
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 5
50 .loc 1 180 3 view .LVU7
@ -298,7 +298,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c ****
202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure the IO Output Type */
203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = GPIOx->OTYPER;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 6
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 6
83 .loc 1 203 9 is_stmt 1 view .LVU24
@ -358,7 +358,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
110 .loc 1 230 36 is_stmt 0 view .LVU38
111 0030 DD08 lsrs r5, r3, #3
112 .loc 1 230 14 view .LVU39
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 7
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 7
113 0032 0835 adds r5, r5, #8
@ -418,7 +418,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
146 .L7:
147 .loc 1 251 40 discriminator 20 view .LVU52
148 0062 04FA0EF4 lsl r4, r4, lr
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 8
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 8
149 .loc 1 251 14 discriminator 20 view .LVU53
@ -478,7 +478,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
190 008e 04EA0506 and r6, r4, r5
191 .LVL20:
265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 9
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 9
192 .loc 1 265 9 is_stmt 1 view .LVU72
@ -538,7 +538,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
231 .LVL25:
281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(iocurrent);
232 .loc 1 281 9 is_stmt 1 view .LVU90
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 10
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 10
233 .loc 1 281 14 is_stmt 0 view .LVU91
@ -598,7 +598,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** {
272 .loc 1 188 8 is_stmt 0 view .LVU108
273 00de 1CEA0202 ands r2, ip, r2
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 11
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 11
274 .LVL32:
@ -658,7 +658,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
310 .loc 1 217 9 is_stmt 1 view .LVU126
217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->PUPDR = temp;
311 .loc 1 217 28 is_stmt 0 view .LVU127
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 12
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 12
312 010a 8C68 ldr r4, [r1, #8]
@ -718,7 +718,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
349 0132 04F00304 and r4, r4, #3
239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->MODER = temp;
350 .loc 1 239 46 view .LVU145
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 13
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 13
351 0136 04FA0EF4 lsl r4, r4, lr
@ -778,7 +778,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
390 .loc 1 250 9 is_stmt 1 view .LVU161
250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 14
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 14
391 .loc 1 250 45 is_stmt 0 view .LVU162
@ -838,7 +838,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** }
292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** }
435 .loc 1 292 1 view .LVU173
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 15
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 15
436 01b4 03B0 add sp, sp, #12
@ -898,7 +898,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
471 0000 0023 movs r3, #0
472 .LVL46:
473 .loc 1 312 33 is_stmt 1 view .LVU182
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 16
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 16
474 0002 31FA03F2 lsrs r2, r1, r3
@ -958,7 +958,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure IO Direction in Input Floating Mode */
341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2u));
500 .loc 1 341 7 is_stmt 1 view .LVU187
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 17
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 17
501 .loc 1 341 12 is_stmt 0 view .LVU188
@ -1018,7 +1018,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
543 .loc 1 353 22 view .LVU207
544 005c 22EA0C02 bic r2, r2, ip
545 0060 8260 str r2, [r0, #8]
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 18
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 18
546 .L27:
@ -1078,7 +1078,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
583 .loc 1 323 11 view .LVU223
584 0090 3440 ands r4, r4, r6
585 .LVL55:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 19
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 19
324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** {
@ -1138,7 +1138,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
628 .loc 1 328 9 is_stmt 1 view .LVU235
328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c ****
629 .loc 1 328 13 is_stmt 0 view .LVU236
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 20
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 20
630 00d0 6568 ldr r5, [r4, #4]
@ -1198,7 +1198,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
670 .cfi_restore 14
671 .loc 1 358 1 view .LVU250
672 00fe 7047 bx lr
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 21
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 21
673 .L44:
@ -1258,7 +1258,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c ****
390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
699 .loc 1 390 3 view .LVU254
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 22
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 22
700 .loc 1 390 12 is_stmt 0 view .LVU255
@ -1318,7 +1318,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */
417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 23
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 23
731 .loc 1 418 1 is_stmt 1 view -0
@ -1378,7 +1378,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
765 .cfi_startproc
766 @ args = 0, pretend = 0, frame = 0
767 @ frame_needed = 0, uses_anonymous_args = 0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 24
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 24
768 @ link register save eliminated.
@ -1438,7 +1438,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** {
800 .loc 1 465 1 is_stmt 1 view -0
801 .cfi_startproc
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 25
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 25
802 @ args = 0, pretend = 0, frame = 8
@ -1498,7 +1498,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
837 001c C369 ldr r3, [r0, #28]
838 .loc 1 484 4 view .LVU302
839 001e 13F4803F tst r3, #65536
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 26
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 26
840 0022 02D0 beq .L54
@ -1558,7 +1558,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** }
508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c ****
509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /**
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 27
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 27
510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief EXTI line detection callback.
@ -1618,7 +1618,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
910 .L57:
507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c ****
911 .loc 1 507 1 view .LVU315
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 28
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 28
912 000a 08BD pop {r3, pc}
@ -1648,29 +1648,29 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 1
934 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
935 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h"
936 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s page 29
ARM GAS C:\Users\nived\AppData\Local\Temp\ccqanTW6.s page 29
DEFINED SYMBOLS
*ABS*:00000000 stm32f3xx_hal_gpio.c
C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s:21 .text.HAL_GPIO_Init:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s:27 .text.HAL_GPIO_Init:00000000 HAL_GPIO_Init
C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s:443 .text.HAL_GPIO_Init:000001b8 $d
C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s:451 .text.HAL_GPIO_DeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s:457 .text.HAL_GPIO_DeInit:00000000 HAL_GPIO_DeInit
C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s:676 .text.HAL_GPIO_DeInit:00000100 $d
C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s:683 .text.HAL_GPIO_ReadPin:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s:689 .text.HAL_GPIO_ReadPin:00000000 HAL_GPIO_ReadPin
C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s:722 .text.HAL_GPIO_WritePin:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s:728 .text.HAL_GPIO_WritePin:00000000 HAL_GPIO_WritePin
C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s:755 .text.HAL_GPIO_TogglePin:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s:761 .text.HAL_GPIO_TogglePin:00000000 HAL_GPIO_TogglePin
C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s:791 .text.HAL_GPIO_LockPin:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s:797 .text.HAL_GPIO_LockPin:00000000 HAL_GPIO_LockPin
C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s:863 .text.HAL_GPIO_EXTI_Callback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s:869 .text.HAL_GPIO_EXTI_Callback:00000000 HAL_GPIO_EXTI_Callback
C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s:884 .text.HAL_GPIO_EXTI_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s:890 .text.HAL_GPIO_EXTI_IRQHandler:00000000 HAL_GPIO_EXTI_IRQHandler
C:\Users\nived\AppData\Local\Temp\ccnWxPPc.s:926 .text.HAL_GPIO_EXTI_IRQHandler:00000018 $d
C:\Users\nived\AppData\Local\Temp\ccqanTW6.s:21 .text.HAL_GPIO_Init:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccqanTW6.s:27 .text.HAL_GPIO_Init:00000000 HAL_GPIO_Init
C:\Users\nived\AppData\Local\Temp\ccqanTW6.s:443 .text.HAL_GPIO_Init:000001b8 $d
C:\Users\nived\AppData\Local\Temp\ccqanTW6.s:451 .text.HAL_GPIO_DeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccqanTW6.s:457 .text.HAL_GPIO_DeInit:00000000 HAL_GPIO_DeInit
C:\Users\nived\AppData\Local\Temp\ccqanTW6.s:676 .text.HAL_GPIO_DeInit:00000100 $d
C:\Users\nived\AppData\Local\Temp\ccqanTW6.s:683 .text.HAL_GPIO_ReadPin:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccqanTW6.s:689 .text.HAL_GPIO_ReadPin:00000000 HAL_GPIO_ReadPin
C:\Users\nived\AppData\Local\Temp\ccqanTW6.s:722 .text.HAL_GPIO_WritePin:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccqanTW6.s:728 .text.HAL_GPIO_WritePin:00000000 HAL_GPIO_WritePin
C:\Users\nived\AppData\Local\Temp\ccqanTW6.s:755 .text.HAL_GPIO_TogglePin:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccqanTW6.s:761 .text.HAL_GPIO_TogglePin:00000000 HAL_GPIO_TogglePin
C:\Users\nived\AppData\Local\Temp\ccqanTW6.s:791 .text.HAL_GPIO_LockPin:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccqanTW6.s:797 .text.HAL_GPIO_LockPin:00000000 HAL_GPIO_LockPin
C:\Users\nived\AppData\Local\Temp\ccqanTW6.s:863 .text.HAL_GPIO_EXTI_Callback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccqanTW6.s:869 .text.HAL_GPIO_EXTI_Callback:00000000 HAL_GPIO_EXTI_Callback
C:\Users\nived\AppData\Local\Temp\ccqanTW6.s:884 .text.HAL_GPIO_EXTI_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccqanTW6.s:890 .text.HAL_GPIO_EXTI_IRQHandler:00000000 HAL_GPIO_EXTI_IRQHandler
C:\Users\nived\AppData\Local\Temp\ccqanTW6.s:926 .text.HAL_GPIO_EXTI_IRQHandler:00000018 $d
NO UNDEFINED SYMBOLS

1310
build/stm32f3xx_hal_i2c.lst
View File

File diff suppressed because it is too large Load Diff

60
build/stm32f3xx_hal_i2c_ex.lst
View File

@ -1,4 +1,4 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 1
ARM GAS C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s page 1
1 .cpu cortex-m4
@ -58,7 +58,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 1
27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** [..] Comparing to other previous devices, the I2C interface for STM32F3xx
29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** devices contains the following additional features
ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 2
ARM GAS C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s page 2
30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
@ -118,7 +118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 1
84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @endverbatim
86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @{
ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 3
ARM GAS C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s page 3
87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */
@ -178,7 +178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 1
60 0020 0068 ldr r0, [r0]
61 .LVL1:
62 .loc 1 110 5 is_stmt 0 discriminator 2 view .LVU14
ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 4
ARM GAS C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s page 4
63 0022 0268 ldr r2, [r0]
@ -238,7 +238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 1
102 .L3:
126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** }
127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** else
ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 5
ARM GAS C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s page 5
128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** {
@ -298,7 +298,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 1
148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY)
138 .loc 1 148 3 view .LVU41
139 .loc 1 148 11 is_stmt 0 view .LVU42
ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 6
ARM GAS C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s page 6
140 0002 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2
@ -358,7 +358,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 1
177 0032 42EA0122 orr r2, r2, r1, lsl #8
178 .LVL11:
166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 7
ARM GAS C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s page 7
167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Store the new register value */
@ -418,7 +418,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 1
183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** }
216 .loc 1 183 1 view .LVU74
217 0056 7047 bx lr
ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 8
ARM GAS C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s page 8
218 .cfi_endproc
@ -478,7 +478,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 1
244 0008 202A cmp r2, #32
245 000a 1FD1 bne .L11
214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 9
ARM GAS C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s page 9
215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Locked */
@ -538,7 +538,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 1
283 0044 0020 movs r0, #0
284 .LVL20:
285 .loc 1 231 5 is_stmt 0 discriminator 2 view .LVU97
ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 10
ARM GAS C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s page 10
286 0046 83F84000 strb r0, [r3, #64]
@ -598,7 +598,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 1
324 0000 0346 mov r3, r0
249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Check the parameters */
250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 11
ARM GAS C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s page 11
325 .loc 1 250 3 is_stmt 1 view .LVU107
@ -658,7 +658,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 1
266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY;
364 .loc 1 267 5 discriminator 2 view .LVU123
ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 12
ARM GAS C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s page 12
365 .loc 1 267 17 is_stmt 0 discriminator 2 view .LVU124
@ -718,7 +718,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 1
283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Fast Mode Plus Functions
285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** *
ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 13
ARM GAS C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s page 13
286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @verbatim
@ -778,7 +778,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 1
426 .loc 1 318 3 view .LVU142
427 0014 019B ldr r3, [sp, #4]
428 .LBE2:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 14
ARM GAS C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s page 14
429 .loc 1 318 3 view .LVU143
@ -838,7 +838,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 1
463 .loc 1 340 1 is_stmt 0 view .LVU147
464 0000 82B0 sub sp, sp, #8
465 .cfi_def_cfa_offset 8
ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 15
ARM GAS C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s page 15
341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Check the parameter */
@ -892,24 +892,24 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 1
506 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h"
507 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h"
508 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s page 16
ARM GAS C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s page 16
DEFINED SYMBOLS
*ABS*:00000000 stm32f3xx_hal_i2c_ex.c
C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s:21 .text.HAL_I2CEx_ConfigAnalogFilter:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s:27 .text.HAL_I2CEx_ConfigAnalogFilter:00000000 HAL_I2CEx_ConfigAnalogFilter
C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s:119 .text.HAL_I2CEx_ConfigDigitalFilter:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s:125 .text.HAL_I2CEx_ConfigDigitalFilter:00000000 HAL_I2CEx_ConfigDigitalFilter
C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s:222 .text.HAL_I2CEx_EnableWakeUp:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s:228 .text.HAL_I2CEx_EnableWakeUp:00000000 HAL_I2CEx_EnableWakeUp
C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s:309 .text.HAL_I2CEx_DisableWakeUp:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s:315 .text.HAL_I2CEx_DisableWakeUp:00000000 HAL_I2CEx_DisableWakeUp
C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s:396 .text.HAL_I2CEx_EnableFastModePlus:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s:402 .text.HAL_I2CEx_EnableFastModePlus:00000000 HAL_I2CEx_EnableFastModePlus
C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s:443 .text.HAL_I2CEx_EnableFastModePlus:00000024 $d
C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s:449 .text.HAL_I2CEx_DisableFastModePlus:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s:455 .text.HAL_I2CEx_DisableFastModePlus:00000000 HAL_I2CEx_DisableFastModePlus
C:\Users\nived\AppData\Local\Temp\ccAZOhw4.s:496 .text.HAL_I2CEx_DisableFastModePlus:00000024 $d
C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s:21 .text.HAL_I2CEx_ConfigAnalogFilter:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s:27 .text.HAL_I2CEx_ConfigAnalogFilter:00000000 HAL_I2CEx_ConfigAnalogFilter
C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s:119 .text.HAL_I2CEx_ConfigDigitalFilter:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s:125 .text.HAL_I2CEx_ConfigDigitalFilter:00000000 HAL_I2CEx_ConfigDigitalFilter
C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s:222 .text.HAL_I2CEx_EnableWakeUp:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s:228 .text.HAL_I2CEx_EnableWakeUp:00000000 HAL_I2CEx_EnableWakeUp
C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s:309 .text.HAL_I2CEx_DisableWakeUp:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s:315 .text.HAL_I2CEx_DisableWakeUp:00000000 HAL_I2CEx_DisableWakeUp
C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s:396 .text.HAL_I2CEx_EnableFastModePlus:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s:402 .text.HAL_I2CEx_EnableFastModePlus:00000000 HAL_I2CEx_EnableFastModePlus
C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s:443 .text.HAL_I2CEx_EnableFastModePlus:00000024 $d
C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s:449 .text.HAL_I2CEx_DisableFastModePlus:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s:455 .text.HAL_I2CEx_DisableFastModePlus:00000000 HAL_I2CEx_DisableFastModePlus
C:\Users\nived\AppData\Local\Temp\cc3Bnvzc.s:496 .text.HAL_I2CEx_DisableFastModePlus:00000024 $d
NO UNDEFINED SYMBOLS

170
build/stm32f3xx_hal_msp.lst
View File

@ -1,4 +1,4 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 1
1 .cpu cortex-m4
@ -58,7 +58,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
28:Core/Src/stm32f3xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/
29:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TD */
30:Core/Src/stm32f3xx_hal_msp.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 2
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 2
31:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TD */
@ -118,7 +118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
41 0004 9A69 ldr r2, [r3, #24]
42 0006 42F00102 orr r2, r2, #1
43 000a 9A61 str r2, [r3, #24]
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 3
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 3
44 .loc 1 72 3 view .LVU4
@ -178,7 +178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
84:Core/Src/stm32f3xx_hal_msp.c **** /**
85:Core/Src/stm32f3xx_hal_msp.c **** * @brief ADC MSP Initialization
86:Core/Src/stm32f3xx_hal_msp.c **** * This function configures the hardware resources used in this example
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 4
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 4
87:Core/Src/stm32f3xx_hal_msp.c **** * @param hadc: ADC handle pointer
@ -238,7 +238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
115:Core/Src/stm32f3xx_hal_msp.c **** */
116:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = isense12_Pin|isense11_Pin|isense6_Pin|isense13_Pin;
117:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 5
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 5
118:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
@ -298,7 +298,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
165:Core/Src/stm32f3xx_hal_msp.c **** }
122 .loc 1 165 1 view .LVU23
123 001e 0DB0 add sp, sp, #52
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 6
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 6
124 .cfi_remember_state
@ -358,7 +358,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
164 0044 42F40032 orr r2, r2, #131072
165 0048 5A61 str r2, [r3, #20]
105:Core/Src/stm32f3xx_hal_msp.c **** /**ADC1 GPIO Configuration
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 7
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 7
166 .loc 1 105 5 discriminator 1 view .LVU38
@ -418,7 +418,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
204 .LVL5:
205 0076 D2E7 b .L5
206 .LVL6:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 8
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 8
207 .L13:
@ -478,7 +478,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
247 00a6 02F40032 and r2, r2, #131072
248 00aa 0592 str r2, [sp, #20]
141:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOC_CLK_ENABLE();
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 9
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 9
249 .loc 1 141 5 discriminator 1 view .LVU69
@ -538,7 +538,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
287 00d4 0793 str r3, [sp, #28]
156:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
288 .loc 1 156 5 is_stmt 1 discriminator 1 view .LVU86
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 10
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 10
156:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
@ -598,7 +598,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
335 .thumb_func
337 HAL_ADC_MspDeInit:
338 .LVL11:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 11
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 11
339 .LFB132:
@ -658,7 +658,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
204:Core/Src/stm32f3xx_hal_msp.c **** else if(hadc->Instance==ADC2)
355 .loc 1 204 8 is_stmt 1 view .LVU102
356 .loc 1 204 10 is_stmt 0 view .LVU103
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 12
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 12
357 000a 164A ldr r2, .L25
@ -718,7 +718,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
379 0024 5361 str r3, [r2, #20]
380 .L19:
196:Core/Src/stm32f3xx_hal_msp.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 13
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 13
381 .loc 1 196 5 view .LVU110
@ -778,7 +778,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
425 .L26:
426 0062 00BF .align 2
427 .L25:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 14
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 14
428 0064 00010050 .word 1342177536
@ -838,7 +838,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
473 .LVL22:
474 .L27:
243:Core/Src/stm32f3xx_hal_msp.c **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 15
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 15
244:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN CAN_MspInit 0 */
@ -898,7 +898,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
488 001c 03F5D633 add r3, r3, #109568
489 0020 DA69 ldr r2, [r3, #28]
490 0022 42F00072 orr r2, r2, #33554432
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 16
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 16
491 0026 DA61 str r2, [r3, #28]
@ -958,7 +958,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
528 0050 0326 movs r6, #3
529 0052 0696 str r6, [sp, #24]
259:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 17
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 17
530 .loc 1 259 5 is_stmt 1 view .LVU150
@ -1018,7 +1018,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
271:Core/Src/stm32f3xx_hal_msp.c **** HAL_NVIC_SetPriority(CAN_RX1_IRQn, 0, 0);
569 .loc 1 271 5 view .LVU166
570 0086 1420 movs r0, #20
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 18
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 18
571 0088 FFF7FEFF bl HAL_NVIC_EnableIRQ
@ -1078,7 +1078,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
614 @ args = 0, pretend = 0, frame = 0
615 @ frame_needed = 0, uses_anonymous_args = 0
616 .loc 1 290 1 is_stmt 0 view .LVU173
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 19
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 19
617 0000 08B5 push {r3, lr}
@ -1138,7 +1138,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
644 001e FFF7FEFF bl HAL_GPIO_DeInit
645 .LVL37:
306:Core/Src/stm32f3xx_hal_msp.c **** HAL_NVIC_DisableIRQ(CAN_RX1_IRQn);
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 20
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 20
646 .loc 1 306 5 is_stmt 1 view .LVU181
@ -1198,7 +1198,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
691 .cfi_def_cfa_offset 56
324:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
692 .loc 1 324 3 is_stmt 1 view .LVU187
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 21
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 21
693 .loc 1 324 20 is_stmt 0 view .LVU188
@ -1258,7 +1258,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
713 @ sp needed
714 001a F0BD pop {r4, r5, r6, r7, pc}
715 .LVL43:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 22
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 22
716 .L42:
@ -1318,7 +1318,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
754 .loc 1 338 26 is_stmt 0 view .LVU208
755 0048 1227 movs r7, #18
756 004a 0497 str r7, [sp, #16]
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 23
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 23
339:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
@ -1378,7 +1378,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
793 0070 FFF7FEFF bl HAL_GPIO_Init
794 .LVL46:
352:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C1_MspInit 1 */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 24
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 24
795 .loc 1 352 5 view .LVU227
@ -1438,7 +1438,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
837 .cfi_def_cfa_offset 8
838 .cfi_offset 3, -8
839 .cfi_offset 14, -4
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 25
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 25
368:Core/Src/stm32f3xx_hal_msp.c **** if(hi2c->Instance==I2C1)
@ -1498,7 +1498,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
868 0026 FFF7FEFF bl HAL_GPIO_DeInit
869 .LVL52:
870 .loc 1 389 1 is_stmt 0 view .LVU244
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 26
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 26
871 002a EEE7 b .L45
@ -1558,7 +1558,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
906 .loc 1 410 10 is_stmt 0 view .LVU251
907 000a 0E4A ldr r2, .L57
908 000c 9342 cmp r3, r2
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 27
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 27
909 000e 0DD0 beq .L56
@ -1618,7 +1618,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
942 002e DA69 ldr r2, [r3, #28]
943 0030 42F00202 orr r2, r2, #2
944 0034 DA61 str r2, [r3, #28]
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 28
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 28
416:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspInit 1 */
@ -1678,7 +1678,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
987 .loc 1 431 1 view .LVU270
988 000a 82B0 sub sp, sp, #8
989 .cfi_def_cfa_offset 8
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 29
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 29
433:Core/Src/stm32f3xx_hal_msp.c **** {
@ -1738,7 +1738,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
1031 @ frame_needed = 0, uses_anonymous_args = 0
1032 .loc 1 447 1 is_stmt 0 view .LVU279
1033 0000 00B5 push {lr}
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 30
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 30
1034 .cfi_def_cfa_offset 4
@ -1798,7 +1798,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
477:Core/Src/stm32f3xx_hal_msp.c **** PB1 ------> TIM3_CH4
478:Core/Src/stm32f3xx_hal_msp.c **** PB4 ------> TIM3_CH1
479:Core/Src/stm32f3xx_hal_msp.c **** */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 31
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 31
480:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4;
@ -1858,7 +1858,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
1090 003e 0223 movs r3, #2
1091 0040 0493 str r3, [sp, #16]
460:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 32
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 32
1092 .loc 1 460 5 is_stmt 1 view .LVU298
@ -1918,7 +1918,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
1131 006a 0493 str r3, [sp, #16]
482:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
1132 .loc 1 482 5 is_stmt 1 view .LVU314
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 33
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 33
483:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
@ -1978,7 +1978,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
1175 0006 03D0 beq .L79
502:Core/Src/stm32f3xx_hal_msp.c **** {
503:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspDeInit 0 */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 34
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 34
504:Core/Src/stm32f3xx_hal_msp.c ****
@ -2038,7 +2038,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
1208 .align 1
1209 .global HAL_TIM_Base_MspDeInit
1210 .syntax unified
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 35
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 35
1211 .thumb
@ -2098,7 +2098,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
1243 0018 00100040 .word 1073745920
1244 001c 00100240 .word 1073876992
1245 .cfi_endproc
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 36
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 36
1246 .LFE141:
@ -2158,7 +2158,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
564:Core/Src/stm32f3xx_hal_msp.c ****
565:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
566:Core/Src/stm32f3xx_hal_msp.c **** /**USART1 GPIO Configuration
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 37
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 37
567:Core/Src/stm32f3xx_hal_msp.c **** PA9 ------> USART1_TX
@ -2218,7 +2218,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
1314 0034 5A69 ldr r2, [r3, #20]
1315 0036 42F40032 orr r2, r2, #131072
1316 003a 5A61 str r2, [r3, #20]
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 38
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 38
565:Core/Src/stm32f3xx_hal_msp.c **** /**USART1 GPIO Configuration
@ -2278,7 +2278,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
1358 .section .text.HAL_UART_MspDeInit,"ax",%progbits
1359 .align 1
1360 .global HAL_UART_MspDeInit
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 39
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 39
1361 .syntax unified
@ -2338,7 +2338,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
1387 000a 08BD pop {r3, pc}
1388 .LVL72:
1389 .L97:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 40
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 40
598:Core/Src/stm32f3xx_hal_msp.c ****
@ -2385,55 +2385,55 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 1
1431 .file 13 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h"
1432 .file 14 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h"
1433 .file 15 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s page 41
ARM GAS C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s page 41
DEFINED SYMBOLS
*ABS*:00000000 stm32f3xx_hal_msp.c
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:21 .text.HAL_MspInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:27 .text.HAL_MspInit:00000000 HAL_MspInit
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:75 .text.HAL_MspInit:0000002c $d
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:80 .text.HAL_ADC_MspInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:86 .text.HAL_ADC_MspInit:00000000 HAL_ADC_MspInit
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:322 .text.HAL_ADC_MspInit:000000fc $d
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:1416 .bss.HAL_RCC_ADC12_CLK_ENABLED:00000000 HAL_RCC_ADC12_CLK_ENABLED
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:331 .text.HAL_ADC_MspDeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:337 .text.HAL_ADC_MspDeInit:00000000 HAL_ADC_MspDeInit
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:428 .text.HAL_ADC_MspDeInit:00000064 $d
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:436 .text.HAL_CAN_MspInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:442 .text.HAL_CAN_MspInit:00000000 HAL_CAN_MspInit
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:598 .text.HAL_CAN_MspInit:000000b0 $d
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:603 .text.HAL_CAN_MspDeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:609 .text.HAL_CAN_MspDeInit:00000000 HAL_CAN_MspDeInit
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:663 .text.HAL_CAN_MspDeInit:00000038 $d
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:669 .text.HAL_I2C_MspInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:675 .text.HAL_I2C_MspInit:00000000 HAL_I2C_MspInit
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:815 .text.HAL_I2C_MspInit:00000088 $d
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:822 .text.HAL_I2C_MspDeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:828 .text.HAL_I2C_MspDeInit:00000000 HAL_I2C_MspDeInit
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:875 .text.HAL_I2C_MspDeInit:0000002c $d
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:882 .text.HAL_TIM_PWM_MspInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:888 .text.HAL_TIM_PWM_MspInit:00000000 HAL_TIM_PWM_MspInit
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:958 .text.HAL_TIM_PWM_MspInit:00000044 $d
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:964 .text.HAL_TIM_Base_MspInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:970 .text.HAL_TIM_Base_MspInit:00000000 HAL_TIM_Base_MspInit
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:1014 .text.HAL_TIM_Base_MspInit:00000028 $d
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:1019 .text.HAL_TIM_MspPostInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:1025 .text.HAL_TIM_MspPostInit:00000000 HAL_TIM_MspPostInit
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:1149 .text.HAL_TIM_MspPostInit:00000078 $d
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:1156 .text.HAL_TIM_PWM_MspDeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:1162 .text.HAL_TIM_PWM_MspDeInit:00000000 HAL_TIM_PWM_MspDeInit
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:1202 .text.HAL_TIM_PWM_MspDeInit:0000002c $d
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:1208 .text.HAL_TIM_Base_MspDeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:1214 .text.HAL_TIM_Base_MspDeInit:00000000 HAL_TIM_Base_MspDeInit
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:1243 .text.HAL_TIM_Base_MspDeInit:00000018 $d
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:1249 .text.HAL_UART_MspInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:1255 .text.HAL_UART_MspInit:00000000 HAL_UART_MspInit
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:1354 .text.HAL_UART_MspInit:00000064 $d
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:1359 .text.HAL_UART_MspDeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:1365 .text.HAL_UART_MspDeInit:00000000 HAL_UART_MspDeInit
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:1407 .text.HAL_UART_MspDeInit:00000024 $d
C:\Users\nived\AppData\Local\Temp\ccEKjK7m.s:1413 .bss.HAL_RCC_ADC12_CLK_ENABLED:00000000 $d
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:21 .text.HAL_MspInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:27 .text.HAL_MspInit:00000000 HAL_MspInit
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:75 .text.HAL_MspInit:0000002c $d
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:80 .text.HAL_ADC_MspInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:86 .text.HAL_ADC_MspInit:00000000 HAL_ADC_MspInit
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:322 .text.HAL_ADC_MspInit:000000fc $d
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:1416 .bss.HAL_RCC_ADC12_CLK_ENABLED:00000000 HAL_RCC_ADC12_CLK_ENABLED
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:331 .text.HAL_ADC_MspDeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:337 .text.HAL_ADC_MspDeInit:00000000 HAL_ADC_MspDeInit
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:428 .text.HAL_ADC_MspDeInit:00000064 $d
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:436 .text.HAL_CAN_MspInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:442 .text.HAL_CAN_MspInit:00000000 HAL_CAN_MspInit
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:598 .text.HAL_CAN_MspInit:000000b0 $d
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:603 .text.HAL_CAN_MspDeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:609 .text.HAL_CAN_MspDeInit:00000000 HAL_CAN_MspDeInit
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:663 .text.HAL_CAN_MspDeInit:00000038 $d
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:669 .text.HAL_I2C_MspInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:675 .text.HAL_I2C_MspInit:00000000 HAL_I2C_MspInit
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:815 .text.HAL_I2C_MspInit:00000088 $d
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:822 .text.HAL_I2C_MspDeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:828 .text.HAL_I2C_MspDeInit:00000000 HAL_I2C_MspDeInit
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:875 .text.HAL_I2C_MspDeInit:0000002c $d
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:882 .text.HAL_TIM_PWM_MspInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:888 .text.HAL_TIM_PWM_MspInit:00000000 HAL_TIM_PWM_MspInit
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:958 .text.HAL_TIM_PWM_MspInit:00000044 $d
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:964 .text.HAL_TIM_Base_MspInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:970 .text.HAL_TIM_Base_MspInit:00000000 HAL_TIM_Base_MspInit
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:1014 .text.HAL_TIM_Base_MspInit:00000028 $d
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:1019 .text.HAL_TIM_MspPostInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:1025 .text.HAL_TIM_MspPostInit:00000000 HAL_TIM_MspPostInit
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:1149 .text.HAL_TIM_MspPostInit:00000078 $d
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:1156 .text.HAL_TIM_PWM_MspDeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:1162 .text.HAL_TIM_PWM_MspDeInit:00000000 HAL_TIM_PWM_MspDeInit
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:1202 .text.HAL_TIM_PWM_MspDeInit:0000002c $d
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:1208 .text.HAL_TIM_Base_MspDeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:1214 .text.HAL_TIM_Base_MspDeInit:00000000 HAL_TIM_Base_MspDeInit
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:1243 .text.HAL_TIM_Base_MspDeInit:00000018 $d
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:1249 .text.HAL_UART_MspInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:1255 .text.HAL_UART_MspInit:00000000 HAL_UART_MspInit
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:1354 .text.HAL_UART_MspInit:00000064 $d
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:1359 .text.HAL_UART_MspDeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:1365 .text.HAL_UART_MspDeInit:00000000 HAL_UART_MspDeInit
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:1407 .text.HAL_UART_MspDeInit:00000024 $d
C:\Users\nived\AppData\Local\Temp\cc5Dvw05.s:1413 .bss.HAL_RCC_ADC12_CLK_ENABLED:00000000 $d
UNDEFINED SYMBOLS
HAL_GPIO_Init

106
build/stm32f3xx_hal_pwr.lst
View File

@ -1,4 +1,4 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s page 1
1 .cpu cortex-m4
@ -58,7 +58,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 1
28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 2
ARM GAS C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s page 2
31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR PWR
@ -118,7 +118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 1
38 0008 1A61 str r2, [r3, #16]
76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET();
39 .loc 1 76 3 view .LVU2
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 3
ARM GAS C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s page 3
40 000a 1A69 ldr r2, [r3, #16]
@ -178,7 +178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 1
84 .thumb
85 .thumb_func
87 HAL_PWR_DisableBkUpAccess:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 4
ARM GAS C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s page 4
88 .LFB132:
@ -238,7 +238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 1
116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** WakeUp pin configuration ***
117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ================================
118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 5
ARM GAS C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s page 5
119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
@ -298,7 +298,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 1
173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry:
174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPEN
175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** function with:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 6
ARM GAS C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s page 6
176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Main regulator ON or
@ -358,7 +358,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 1
230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @endverbatim
231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 7
ARM GAS C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s page 7
233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
@ -418,7 +418,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 1
149 .cfi_startproc
150 @ args = 0, pretend = 0, frame = 0
151 @ frame_needed = 0, uses_anonymous_args = 0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 8
ARM GAS C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s page 8
152 @ link register save eliminated.
@ -478,7 +478,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 1
283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
183 .loc 1 284 3 view .LVU19
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 9
ARM GAS C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s page 9
285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
@ -538,7 +538,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 1
219 .syntax unified
220 0018 7047 bx lr
221 .L21:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 10
ARM GAS C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s page 10
222 001a 00BF .align 2
@ -598,7 +598,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 1
248 0000 0B4A ldr r2, .L26
249 0002 1368 ldr r3, [r2]
250 .LVL4:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 11
ARM GAS C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s page 11
333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
@ -658,7 +658,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 1
281 @ 356 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
282 001c 20BF wfe
283 @ 0 "" 2
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 12
ARM GAS C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s page 12
357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
@ -718,7 +718,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 1
370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - WKUP pins if enabled.
371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 13
ARM GAS C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s page 13
373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void)
@ -778,7 +778,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 1
366 .thumb
367 .thumb_func
369 HAL_PWR_EnableSleepOnExit:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 14
ARM GAS C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s page 14
370 .LFB138:
@ -838,7 +838,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 1
402 @ frame_needed = 0, uses_anonymous_args = 0
403 @ link register save eliminated.
412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 15
ARM GAS C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s page 15
413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
@ -898,7 +898,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 1
444 .LFE140:
446 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits
447 .align 1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 16
ARM GAS C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s page 16
448 .global HAL_PWR_DisableSEVOnPend
@ -944,46 +944,46 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 1
477 .file 3 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
478 .file 4 "Drivers/CMSIS/Include/core_cm4.h"
479 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s page 17
ARM GAS C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s page 17
DEFINED SYMBOLS
*ABS*:00000000 stm32f3xx_hal_pwr.c
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:21 .text.HAL_PWR_DeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:27 .text.HAL_PWR_DeInit:00000000 HAL_PWR_DeInit
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:48 .text.HAL_PWR_DeInit:00000014 $d
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:53 .text.HAL_PWR_EnableBkUpAccess:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:59 .text.HAL_PWR_EnableBkUpAccess:00000000 HAL_PWR_EnableBkUpAccess
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:76 .text.HAL_PWR_EnableBkUpAccess:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:81 .text.HAL_PWR_DisableBkUpAccess:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:87 .text.HAL_PWR_DisableBkUpAccess:00000000 HAL_PWR_DisableBkUpAccess
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:104 .text.HAL_PWR_DisableBkUpAccess:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:109 .text.HAL_PWR_EnableWakeUpPin:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:115 .text.HAL_PWR_EnableWakeUpPin:00000000 HAL_PWR_EnableWakeUpPin
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:134 .text.HAL_PWR_EnableWakeUpPin:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:139 .text.HAL_PWR_DisableWakeUpPin:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:145 .text.HAL_PWR_DisableWakeUpPin:00000000 HAL_PWR_DisableWakeUpPin
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:164 .text.HAL_PWR_DisableWakeUpPin:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:169 .text.HAL_PWR_EnterSLEEPMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:175 .text.HAL_PWR_EnterSLEEPMode:00000000 HAL_PWR_EnterSLEEPMode
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:224 .text.HAL_PWR_EnterSLEEPMode:0000001c $d
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:229 .text.HAL_PWR_EnterSTOPMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:235 .text.HAL_PWR_EnterSTOPMode:00000000 HAL_PWR_EnterSTOPMode
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:312 .text.HAL_PWR_EnterSTOPMode:00000030 $d
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:318 .text.HAL_PWR_EnterSTANDBYMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:324 .text.HAL_PWR_EnterSTANDBYMode:00000000 HAL_PWR_EnterSTANDBYMode
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:357 .text.HAL_PWR_EnterSTANDBYMode:00000018 $d
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:363 .text.HAL_PWR_EnableSleepOnExit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:369 .text.HAL_PWR_EnableSleepOnExit:00000000 HAL_PWR_EnableSleepOnExit
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:386 .text.HAL_PWR_EnableSleepOnExit:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:391 .text.HAL_PWR_DisableSleepOnExit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:397 .text.HAL_PWR_DisableSleepOnExit:00000000 HAL_PWR_DisableSleepOnExit
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:414 .text.HAL_PWR_DisableSleepOnExit:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:419 .text.HAL_PWR_EnableSEVOnPend:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:425 .text.HAL_PWR_EnableSEVOnPend:00000000 HAL_PWR_EnableSEVOnPend
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:442 .text.HAL_PWR_EnableSEVOnPend:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:447 .text.HAL_PWR_DisableSEVOnPend:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:453 .text.HAL_PWR_DisableSEVOnPend:00000000 HAL_PWR_DisableSEVOnPend
C:\Users\nived\AppData\Local\Temp\ccYHNbL7.s:470 .text.HAL_PWR_DisableSEVOnPend:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:21 .text.HAL_PWR_DeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:27 .text.HAL_PWR_DeInit:00000000 HAL_PWR_DeInit
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:48 .text.HAL_PWR_DeInit:00000014 $d
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:53 .text.HAL_PWR_EnableBkUpAccess:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:59 .text.HAL_PWR_EnableBkUpAccess:00000000 HAL_PWR_EnableBkUpAccess
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:76 .text.HAL_PWR_EnableBkUpAccess:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:81 .text.HAL_PWR_DisableBkUpAccess:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:87 .text.HAL_PWR_DisableBkUpAccess:00000000 HAL_PWR_DisableBkUpAccess
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:104 .text.HAL_PWR_DisableBkUpAccess:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:109 .text.HAL_PWR_EnableWakeUpPin:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:115 .text.HAL_PWR_EnableWakeUpPin:00000000 HAL_PWR_EnableWakeUpPin
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:134 .text.HAL_PWR_EnableWakeUpPin:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:139 .text.HAL_PWR_DisableWakeUpPin:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:145 .text.HAL_PWR_DisableWakeUpPin:00000000 HAL_PWR_DisableWakeUpPin
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:164 .text.HAL_PWR_DisableWakeUpPin:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:169 .text.HAL_PWR_EnterSLEEPMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:175 .text.HAL_PWR_EnterSLEEPMode:00000000 HAL_PWR_EnterSLEEPMode
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:224 .text.HAL_PWR_EnterSLEEPMode:0000001c $d
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:229 .text.HAL_PWR_EnterSTOPMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:235 .text.HAL_PWR_EnterSTOPMode:00000000 HAL_PWR_EnterSTOPMode
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:312 .text.HAL_PWR_EnterSTOPMode:00000030 $d
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:318 .text.HAL_PWR_EnterSTANDBYMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:324 .text.HAL_PWR_EnterSTANDBYMode:00000000 HAL_PWR_EnterSTANDBYMode
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:357 .text.HAL_PWR_EnterSTANDBYMode:00000018 $d
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:363 .text.HAL_PWR_EnableSleepOnExit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:369 .text.HAL_PWR_EnableSleepOnExit:00000000 HAL_PWR_EnableSleepOnExit
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:386 .text.HAL_PWR_EnableSleepOnExit:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:391 .text.HAL_PWR_DisableSleepOnExit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:397 .text.HAL_PWR_DisableSleepOnExit:00000000 HAL_PWR_DisableSleepOnExit
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:414 .text.HAL_PWR_DisableSleepOnExit:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:419 .text.HAL_PWR_EnableSEVOnPend:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:425 .text.HAL_PWR_EnableSEVOnPend:00000000 HAL_PWR_EnableSEVOnPend
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:442 .text.HAL_PWR_EnableSEVOnPend:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:447 .text.HAL_PWR_DisableSEVOnPend:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:453 .text.HAL_PWR_DisableSEVOnPend:00000000 HAL_PWR_DisableSEVOnPend
C:\Users\nived\AppData\Local\Temp\ccv8xoUp.s:470 .text.HAL_PWR_DisableSEVOnPend:0000000c $d
NO UNDEFINED SYMBOLS

46
build/stm32f3xx_hal_pwr_ex.lst
View File

@ -1,4 +1,4 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccea5p49.s page 1
ARM GAS C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s page 1
1 .cpu cortex-m4
@ -58,7 +58,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccea5p49.s page 1
27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** @addtogroup STM32F3xx_HAL_Driver
28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @{
29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccea5p49.s page 2
ARM GAS C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s page 2
30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
@ -118,7 +118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccea5p49.s page 1
84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) The voltage regulator is always enabled after Reset. It works in three different
85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** modes.
86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** In Run mode, the regulator supplies full power to the 1.8V domain (core, memories
ARM GAS C:\Users\nived\AppData\Local\Temp\ccea5p49.s page 3
ARM GAS C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s page 3
87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** and digital peripherals).
@ -178,7 +178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccea5p49.s page 1
134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Set PLS[7:5] bits according to PVDLevel value */
135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
37 .loc 1 135 3 view .LVU3
ARM GAS C:\Users\nived\AppData\Local\Temp\ccea5p49.s page 4
ARM GAS C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s page 4
38 0000 1E4A ldr r2, .L6
@ -238,7 +238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccea5p49.s page 1
78 0048 04D0 beq .L3
150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** {
151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
ARM GAS C:\Users\nived\AppData\Local\Temp\ccea5p49.s page 5
ARM GAS C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s page 5
79 .loc 1 151 5 is_stmt 1 view .LVU15
@ -298,7 +298,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccea5p49.s page 1
121 .global HAL_PWR_EnablePVD
122 .syntax unified
123 .thumb
ARM GAS C:\Users\nived\AppData\Local\Temp\ccea5p49.s page 6
ARM GAS C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s page 6
124 .thumb_func
@ -358,7 +358,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccea5p49.s page 1
164 0004 23F01003 bic r3, r3, #16
165 0008 1360 str r3, [r2]
182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccea5p49.s page 7
ARM GAS C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s page 7
166 .loc 1 182 1 is_stmt 0 view .LVU30
@ -418,7 +418,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccea5p49.s page 1
194 .section .text.HAL_PWR_PVD_IRQHandler,"ax",%progbits
195 .align 1
196 .global HAL_PWR_PVD_IRQHandler
ARM GAS C:\Users\nived\AppData\Local\Temp\ccea5p49.s page 8
ARM GAS C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s page 8
197 .syntax unified
@ -475,24 +475,24 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccea5p49.s page 1
242 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
243 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h"
244 .file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccea5p49.s page 9
ARM GAS C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s page 9
DEFINED SYMBOLS
*ABS*:00000000 stm32f3xx_hal_pwr_ex.c
C:\Users\nived\AppData\Local\Temp\ccea5p49.s:21 .text.HAL_PWR_ConfigPVD:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccea5p49.s:27 .text.HAL_PWR_ConfigPVD:00000000 HAL_PWR_ConfigPVD
C:\Users\nived\AppData\Local\Temp\ccea5p49.s:114 .text.HAL_PWR_ConfigPVD:0000007c $d
C:\Users\nived\AppData\Local\Temp\ccea5p49.s:120 .text.HAL_PWR_EnablePVD:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccea5p49.s:126 .text.HAL_PWR_EnablePVD:00000000 HAL_PWR_EnablePVD
C:\Users\nived\AppData\Local\Temp\ccea5p49.s:143 .text.HAL_PWR_EnablePVD:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccea5p49.s:148 .text.HAL_PWR_DisablePVD:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccea5p49.s:154 .text.HAL_PWR_DisablePVD:00000000 HAL_PWR_DisablePVD
C:\Users\nived\AppData\Local\Temp\ccea5p49.s:171 .text.HAL_PWR_DisablePVD:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccea5p49.s:176 .text.HAL_PWR_PVDCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccea5p49.s:182 .text.HAL_PWR_PVDCallback:00000000 HAL_PWR_PVDCallback
C:\Users\nived\AppData\Local\Temp\ccea5p49.s:195 .text.HAL_PWR_PVD_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccea5p49.s:201 .text.HAL_PWR_PVD_IRQHandler:00000000 HAL_PWR_PVD_IRQHandler
C:\Users\nived\AppData\Local\Temp\ccea5p49.s:234 .text.HAL_PWR_PVD_IRQHandler:0000001c $d
C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s:21 .text.HAL_PWR_ConfigPVD:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s:27 .text.HAL_PWR_ConfigPVD:00000000 HAL_PWR_ConfigPVD
C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s:114 .text.HAL_PWR_ConfigPVD:0000007c $d
C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s:120 .text.HAL_PWR_EnablePVD:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s:126 .text.HAL_PWR_EnablePVD:00000000 HAL_PWR_EnablePVD
C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s:143 .text.HAL_PWR_EnablePVD:0000000c $d
C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s:148 .text.HAL_PWR_DisablePVD:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s:154 .text.HAL_PWR_DisablePVD:00000000 HAL_PWR_DisablePVD
C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s:171 .text.HAL_PWR_DisablePVD:0000000c $d
C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s:176 .text.HAL_PWR_PVDCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s:182 .text.HAL_PWR_PVDCallback:00000000 HAL_PWR_PVDCallback
C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s:195 .text.HAL_PWR_PVD_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s:201 .text.HAL_PWR_PVD_IRQHandler:00000000 HAL_PWR_PVD_IRQHandler
C:\Users\nived\AppData\Local\Temp\cc1OBeWt.s:234 .text.HAL_PWR_PVD_IRQHandler:0000001c $d
NO UNDEFINED SYMBOLS

308
build/stm32f3xx_hal_rcc.lst
View File

@ -1,4 +1,4 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 1
1 .cpu cortex-m4
@ -58,7 +58,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) Configure the AHB and APB buses prescalers
29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) Enable the clock for the peripheral(s) to be used
30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) Configure the clock source(s) for peripherals whose clocks are not
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 2
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 2
31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** derived from the System clock (RTC, ADC, I2C, I2S, TIM, USB FS)
@ -118,7 +118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */
86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Private macro -------------------------------------------------------------*/
87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC_Private_Macros RCC Private Macros
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 3
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 3
88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{
@ -178,7 +178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c ****
143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) PLL (clocked by HSI or HSE), featuring different output clocks:
144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The first output is used to generate the high speed system clock (up to 72 MHz)
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 4
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 4
145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The second output is used to generate the clock for the USB FS (48 MHz)
@ -238,7 +238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */
200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c ****
201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /**
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 5
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 5
202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Resets the RCC clock configuration to the default reset state.
@ -298,7 +298,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
58 .loc 1 226 42 view .LVU8
59 0016 13F0020F tst r3, #2
60 001a 07D1 bne .L14
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 6
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 6
227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
@ -358,7 +358,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Insure PLLRDY is reset */
269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get start tick */
270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick();
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 7
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 7
271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
@ -418,7 +418,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
96 .loc 1 245 3 is_stmt 1 view .LVU19
97 .L5:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 8
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 8
245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
@ -478,7 +478,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
137 0074 08B1 cbz r0, .L16
259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** }
138 .loc 1 259 12 view .LVU35
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 9
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 9
139 0076 0124 movs r4, #1
@ -538,7 +538,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c ****
180 .loc 1 280 3 is_stmt 1 view .LVU49
181 00ae 0B4B ldr r3, .L18
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 10
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 10
182 00b0 0022 movs r2, #0
@ -598,7 +598,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
33:Drivers/CMSIS/Include/cmsis_gcc.h ****
34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 11
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 11
36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0)
@ -658,7 +658,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 12
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 12
93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
@ -718,7 +718,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register
148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register.
149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 13
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 13
150:Drivers/CMSIS/Include/cmsis_gcc.h **** */
@ -778,7 +778,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
204:Drivers/CMSIS/Include/cmsis_gcc.h **** */
205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
206:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 14
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 14
207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
@ -838,7 +838,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
261:Drivers/CMSIS/Include/cmsis_gcc.h **** */
262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
263:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 15
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 15
264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
@ -898,7 +898,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
319:Drivers/CMSIS/Include/cmsis_gcc.h ****
320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 16
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 16
321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
@ -958,7 +958,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
375:Drivers/CMSIS/Include/cmsis_gcc.h ****
376:Drivers/CMSIS/Include/cmsis_gcc.h ****
377:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 17
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 17
378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask
@ -1018,7 +1018,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
434:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 18
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 18
435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ
@ -1078,7 +1078,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
490:Drivers/CMSIS/Include/cmsis_gcc.h **** */
491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 19
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 19
492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
@ -1138,7 +1138,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
548:Drivers/CMSIS/Include/cmsis_gcc.h **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 20
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 20
549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
@ -1198,7 +1198,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
603:Drivers/CMSIS/Include/cmsis_gcc.h **** }
604:Drivers/CMSIS/Include/cmsis_gcc.h ****
605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 21
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 21
606:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
@ -1258,7 +1258,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 22
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 22
663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
@ -1318,7 +1318,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit
718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 23
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 23
720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
@ -1378,7 +1378,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr();
775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 24
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 24
777:Drivers/CMSIS/Include/cmsis_gcc.h ****
@ -1438,7 +1438,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
831:Drivers/CMSIS/Include/cmsis_gcc.h ****
832:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 25
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 25
834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes.
@ -1498,7 +1498,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
889:Drivers/CMSIS/Include/cmsis_gcc.h **** {
890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory");
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 26
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 26
891:Drivers/CMSIS/Include/cmsis_gcc.h **** }
@ -1558,7 +1558,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
945:Drivers/CMSIS/Include/cmsis_gcc.h ****
946:Drivers/CMSIS/Include/cmsis_gcc.h ****
947:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 27
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 27
948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit)
@ -1618,7 +1618,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */
993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U)
994:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 28
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 28
995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U;
@ -1678,7 +1678,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * supported by this macro. User should request a transition to LSE Off
308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * first and then LSE On or LSE Bypass.
309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 29
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 29
310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * supported by this macro. User should request a transition to HSE Off
@ -1738,7 +1738,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
274 .loc 1 335 5 is_stmt 1 view .LVU73
336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c ****
337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowe
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 30
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 30
338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
@ -1798,7 +1798,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
315 0058 13F4803F tst r3, #65536
316 005c E6D0 beq .L24
317 .L23:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 31
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 31
341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
@ -1858,7 +1858,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
363 007a 0122 movs r2, #1
364 007c 02FA03F3 lsl r3, r2, r3
341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 32
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 32
365 .loc 1 341 9 view .LVU99
@ -1918,7 +1918,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
378 .loc 1 388 5 view .LVU104
379 008e 13F0020F tst r3, #2
380 0092 00F0C480 beq .L40
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 33
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 33
389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
@ -1978,7 +1978,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
407 .LBI174:
981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
408 .loc 2 981 31 view .LVU116
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 34
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 34
409 .LBB175:
@ -2038,7 +2038,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
452 .loc 2 1001 3 is_stmt 0 view .LVU130
453 .thumb
454 .syntax unified
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 35
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 35
455 .LBE177:
@ -2098,7 +2098,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
501 .loc 1 349 7 is_stmt 1 discriminator 1 view .LVU144
502 0106 784A ldr r2, .L132
503 0108 1368 ldr r3, [r2]
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 36
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 36
504 010a 43F48033 orr r3, r3, #65536
@ -2158,7 +2158,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
545 .thumb
546 .syntax unified
547 .LBE181:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 37
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 37
548 .LBE180:
@ -2218,7 +2218,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
591 .LVL39:
592 .L29:
349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 38
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 38
593 .loc 1 349 7 is_stmt 1 discriminator 5 view .LVU173
@ -2278,7 +2278,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
635 0198 4FF40033 mov r3, #131072
636 .syntax unified
637 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 39
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 39
638 019c 93FAA3F3 rbit r3, r3
@ -2338,7 +2338,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
683 .loc 1 379 14 view .LVU199
684 01c6 6428 cmp r0, #100
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 40
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 40
685 01c8 E6D9 bls .L36
@ -2398,7 +2398,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
728 01e4 0223 movs r3, #2
729 .syntax unified
730 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 41
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 41
731 01e6 93FAA3F3 rbit r3, r3
@ -2458,7 +2458,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
777 .LBE192:
407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** }
778 .loc 1 407 9 view .LVU225
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 42
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 42
779 0214 B2FA82F2 clz r2, r2
@ -2518,7 +2518,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
797 .loc 1 462 7 is_stmt 1 view .LVU233
798 .LVL53:
799 .LBB194:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 43
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 43
800 .LBI194:
@ -2578,7 +2578,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
842 @ 0 "" 2
843 .LVL57:
844 .loc 2 1001 3 view .LVU247
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 44
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 44
845 .loc 2 1001 3 is_stmt 0 view .LVU248
@ -2638,7 +2638,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
983:Drivers/CMSIS/Include/cmsis_gcc.h ****
892 .loc 2 983 3 view .LVU261
988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 45
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 45
893 .loc 2 988 4 view .LVU262
@ -2698,7 +2698,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
939 .syntax unified
940 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
941 0288 92FAA2F2 rbit r2, r2
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 46
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 46
942 @ 0 "" 2
@ -2758,7 +2758,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
988 02b4 0546 mov r5, r0
989 .LVL68:
442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 47
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 47
990 .loc 1 442 9 is_stmt 1 view .LVU288
@ -2818,7 +2818,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1035 02ca 03F01F03 and r3, r3, #31
1036 02ce 0122 movs r2, #1
1037 02d0 02FA03F3 lsl r3, r2, r3
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 48
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 48
442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
@ -2878,7 +2878,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1076 .syntax unified
1077 .LBE213:
1078 .LBE212:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 49
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 49
1079 .loc 1 479 7 view .LVU314
@ -2938,7 +2938,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1121 0310 93FAA3F2 rbit r2, r3
1122 @ 0 "" 2
1123 .LVL78:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 50
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 50
1124 .loc 2 1001 3 view .LVU327
@ -2998,7 +2998,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1172 032a 02FA03F3 lsl r3, r2, r3
1173 .loc 1 485 49 view .LVU341
1174 032e 0B42 tst r3, r1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 51
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 51
1175 0330 06D0 beq .L55
@ -3058,7 +3058,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1208 .LBB223:
1209 .loc 1 506 7 view .LVU356
1210 .loc 1 506 7 view .LVU357
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 52
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 52
1211 0354 A14B ldr r3, .L134+4
@ -3118,7 +3118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1243 037a 73BB cbnz r3, .L68
1244 .loc 1 528 5 discriminator 4 view .LVU369
1245 037c 03F18043 add r3, r3, #1073741824
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 53
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 53
1246 0380 03F50433 add r3, r3, #135168
@ -3178,7 +3178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1289 .loc 1 522 18 view .LVU381
1290 03be 0320 movs r0, #3
1291 03c0 2BE1 b .L21
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 54
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 54
1292 .LVL92:
@ -3238,7 +3238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1334 03f4 1A6A ldr r2, [r3, #32]
1335 03f6 42F00402 orr r2, r2, #4
1336 03fa 1A62 str r2, [r3, #32]
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 55
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 55
528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the LSE State */
@ -3298,7 +3298,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1384 .LBE226:
1385 .loc 1 536 13 discriminator 11 view .LVU407
1386 0416 B3FA83F3 clz r3, r3
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 56
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 56
1387 041a 03F01F03 and r3, r3, #31
@ -3358,7 +3358,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1432 043e 93FAA3F3 rbit r3, r3
1433 @ 0 "" 2
1434 .LVL103:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 57
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 57
1435 .loc 2 1001 3 view .LVU422
@ -3418,7 +3418,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1472 .LVL108:
1473 .loc 2 1001 3 view .LVU433
1474 .loc 2 1001 3 is_stmt 0 view .LVU434
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 58
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 58
1475 .thumb
@ -3478,7 +3478,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1523 .LBB236:
1524 .LBI236:
981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 59
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 59
1525 .loc 2 981 31 view .LVU448
@ -3538,7 +3538,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Require to disable power clock if necessary */
560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(pwrclkchanged == SET)
1566 .loc 1 560 5 is_stmt 1 view .LVU460
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 60
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 60
1567 .loc 1 560 7 is_stmt 0 view .LVU461
@ -3598,7 +3598,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 61
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 61
593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
@ -3658,7 +3658,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1609 .syntax unified
1610 .LBE241:
1611 .LBE240:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 62
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 62
1612 .loc 1 626 9 view .LVU478
@ -3718,7 +3718,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
1655 .loc 2 988 4 view .LVU491
1656 04e2 4FF00073 mov r3, #33554432
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 63
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 63
1657 .syntax unified
@ -3778,7 +3778,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c ****
1703 .loc 1 584 9 view .LVU505
1704 .LBB247:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 64
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 64
1705 .LBI247:
@ -3838,7 +3838,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1748 @ 0 "" 2
1749 .loc 2 1001 3 view .LVU519
1750 .LVL129:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 65
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 65
1751 .loc 2 1001 3 is_stmt 0 view .LVU520
@ -3898,7 +3898,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** }
1795 .loc 1 594 20 view .LVU533
1796 0566 0320 movs r0, #3
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 66
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 66
1797 0568 57E0 b .L21
@ -3958,7 +3958,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1842 .L86:
615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
1843 .loc 1 615 52 view .LVU545
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 67
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 67
1844 .LBB255:
@ -4018,7 +4018,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1889 .loc 1 615 52 view .LVU558
1890 05be 1942 tst r1, r3
1891 05c0 06D1 bne .L131
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 68
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 68
617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
@ -4078,7 +4078,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1909 .loc 1 668 10 view .LVU565
1910 05d4 0020 movs r0, #0
1911 05d6 20E0 b .L21
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 69
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 69
1912 .L135:
@ -4138,7 +4138,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** }
1955 .loc 1 325 12 view .LVU578
1956 0604 0120 movs r0, #1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 70
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 70
1957 .LVL145:
@ -4198,7 +4198,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** }
2003 .loc 1 646 16 view .LVU588
2004 061e 0120 movs r0, #1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 71
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 71
2005 0620 FBE7 b .L21
@ -4258,7 +4258,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t tickstart = 0U;
697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c ****
698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check Null pointer */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 72
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 72
699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_ClkInitStruct == NULL)
@ -4318,7 +4318,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR;
754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** }
755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 73
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 73
756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* HSI is selected as System Clock Source */
@ -4378,7 +4378,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the source of time base considering new system clocks settings*/
811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HAL_InitTick (uwTickPrio);
812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 74
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 74
813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_OK;
@ -4438,7 +4438,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note MCO pin should be configured in alternate function mode.
868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_MCOx specifies the output direction for the clock source.
869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This parameter can be one of the following values:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 75
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 75
870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
@ -4498,7 +4498,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
2058 .loc 1 898 3 is_stmt 1 view .LVU601
2059 .loc 1 898 18 is_stmt 0 view .LVU602
2060 000e 0023 movs r3, #0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 76
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 76
2061 0010 0393 str r3, [sp, #12]
@ -4558,7 +4558,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
2104 @ sp needed
2105 0044 30BD pop {r4, r5, pc}
2106 .LVL159:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 77
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 77
2107 .L141:
@ -4618,7 +4618,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
2147 .LBE262:
2148 .LBE261:
2149 .loc 1 922 22 view .LVU627
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 78
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 78
2150 0008 B3FA83F3 clz r3, r3
@ -4678,7 +4678,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
2194 .LBE264:
2195 .LBE263:
2196 .loc 1 931 22 view .LVU637
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 79
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 79
2197 0008 B3FA83F3 clz r3, r3
@ -4738,7 +4738,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
2220 @ args = 0, pretend = 0, frame = 0
2221 @ frame_needed = 0, uses_anonymous_args = 0
2222 @ link register save eliminated.
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 80
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 80
965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
@ -4798,7 +4798,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
2258 .syntax unified
2259 .LBE266:
2260 .LBE265:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 81
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 81
2261 .loc 1 980 72 view .LVU655
@ -4858,7 +4858,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
2306 0046 0A4B ldr r3, .L149+12
2307 0048 B3FBF1F3 udiv r3, r3, r1
2308 .loc 1 986 16 view .LVU671
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 82
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 82
2309 004c 03FB00F0 mul r0, r3, r0
@ -4918,7 +4918,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
2332 .loc 1 1016 1 is_stmt 0 view .LVU679
2333 0060 7047 bx lr
2334 .L150:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 83
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 83
2335 0062 00BF .align 2
@ -4978,7 +4978,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
2381 .loc 1 713 5 view .LVU689
2382 0014 8B42 cmp r3, r1
2383 0016 0BD2 bcs .L153
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 84
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 84
716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c ****
@ -5038,7 +5038,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
2423 .loc 1 739 25 is_stmt 0 view .LVU705
2424 004e 6368 ldr r3, [r4, #4]
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 85
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 85
739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
@ -5098,7 +5098,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
2468 .loc 2 1001 3 view .LVU719
2469 .loc 2 1001 3 is_stmt 0 view .LVU720
2470 .thumb
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 86
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 86
2471 .syntax unified
@ -5158,7 +5158,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
2512 00a2 801B subs r0, r0, r6
773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
2513 .loc 1 773 10 view .LVU734
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 87
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 87
2514 00a4 41F28833 movw r3, #5000
@ -5218,7 +5218,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
2559 .thumb
2560 .syntax unified
2561 .LBE276:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 88
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 88
2562 .LBE275:
@ -5278,7 +5278,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
2605 00e6 4FF00072 mov r2, #33554432
2606 .syntax unified
2607 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 89
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 89
2608 00ea 92FAA2F2 rbit r2, r2
@ -5338,7 +5338,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
2652 .loc 1 794 3 is_stmt 1 view .LVU773
794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 90
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 90
2653 .loc 1 794 25 is_stmt 0 view .LVU774
@ -5398,7 +5398,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
2694 .loc 2 981 31 is_stmt 1 view .LVU787
2695 .LBB282:
983:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 91
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 91
2696 .loc 2 983 3 view .LVU788
@ -5458,7 +5458,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
2740 0182 0120 movs r0, #1
2741 .LVL200:
814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 92
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 92
2742 .loc 1 814 1 view .LVU801
@ -5518,7 +5518,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval HCLK frequency
1026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */
1027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t HAL_RCC_GetHCLKFreq(void)
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 93
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 93
1028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
@ -5578,7 +5578,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
2828 000a 03F4E063 and r3, r3, #1792
2829 .LVL206:
2830 .LBB283:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 94
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 94
2831 .LBI283:
@ -5638,7 +5638,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
2874 .loc 1 1051 1 is_stmt 1 view -0
2875 .cfi_startproc
2876 @ args = 0, pretend = 0, frame = 0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 95
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 95
2877 @ frame_needed = 0, uses_anonymous_args = 0
@ -5698,7 +5698,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
2925 .LFE139:
2927 .section .text.HAL_RCC_GetOscConfig,"ax",%progbits
2928 .align 1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 96
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 96
2929 .global HAL_RCC_GetOscConfig
@ -5758,7 +5758,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_ON;
1081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** }
1082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 97
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 97
1083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
@ -5818,7 +5818,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
2992 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
2993 0034 92FAA2F2 rbit r2, r2
2994 @ 0 "" 2
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 98
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 98
2995 .LVL213:
@ -5878,7 +5878,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** }
1121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else
1122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 99
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 99
1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
@ -5938,7 +5938,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
3063 007e 1B68 ldr r3, [r3]
1078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** {
3064 .loc 1 1078 10 view .LVU888
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 100
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 100
3065 0080 13F4803F tst r3, #65536
@ -5998,7 +5998,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** }
3105 .loc 1 1123 33 is_stmt 0 view .LVU903
3106 00b0 0023 movs r3, #0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 101
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 101
3107 00b2 8361 str r3, [r0, #24]
@ -6058,7 +6058,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the SYSCLK configuration --------------------------------------------*/
1161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
3143 .loc 1 1161 3 is_stmt 1 view .LVU911
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 102
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 102
3144 .loc 1 1161 51 is_stmt 0 view .LVU912
@ -6118,7 +6118,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
3185 .L212:
3186 0034 00100240 .word 1073876992
3187 0038 00200240 .word 1073881088
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 103
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 103
3188 .cfi_endproc
@ -6178,7 +6178,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
3217 HAL_RCC_NMI_IRQHandler:
3218 .LFB142:
1182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check RCC CSSF flag */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 104
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 104
3219 .loc 1 1182 1 view -0
@ -6238,7 +6238,7 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
3266 0A0B0C0D
3266 0E
3267 000d 0F1010 .ascii "\017\020\020"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 105
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 105
3268 .text
@ -6252,58 +6252,58 @@ ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 1
3276 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h"
3277 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h"
3278 .file 11 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 106
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 106
DEFINED SYMBOLS
*ABS*:00000000 stm32f3xx_hal_rcc.c
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:21 .text.HAL_RCC_DeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:27 .text.HAL_RCC_DeInit:00000000 HAL_RCC_DeInit
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:228 .text.HAL_RCC_DeInit:000000dc $d
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:238 .text.HAL_RCC_OscConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:244 .text.HAL_RCC_OscConfig:00000000 HAL_RCC_OscConfig
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:1056 .text.HAL_RCC_OscConfig:000002e8 $d
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:1067 .text.HAL_RCC_OscConfig:000002f0 $t
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:1915 .text.HAL_RCC_OscConfig:000005d8 $d
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:1922 .text.HAL_RCC_OscConfig:000005e4 $t
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2019 .text.HAL_RCC_OscConfig:0000062c $d
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2024 .text.HAL_RCC_MCOConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2030 .text.HAL_RCC_MCOConfig:00000000 HAL_RCC_MCOConfig
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2111 .text.HAL_RCC_MCOConfig:00000048 $d
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2116 .text.HAL_RCC_EnableCSS:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2122 .text.HAL_RCC_EnableCSS:00000000 HAL_RCC_EnableCSS
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2163 .text.HAL_RCC_DisableCSS:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2169 .text.HAL_RCC_DisableCSS:00000000 HAL_RCC_DisableCSS
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2210 .text.HAL_RCC_GetSysClockFreq:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2216 .text.HAL_RCC_GetSysClockFreq:00000000 HAL_RCC_GetSysClockFreq
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2337 .text.HAL_RCC_GetSysClockFreq:00000064 $d
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:3265 .rodata.aPLLMULFactorTable:00000000 aPLLMULFactorTable
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:3258 .rodata.aPredivFactorTable:00000000 aPredivFactorTable
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2347 .text.HAL_RCC_ClockConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2353 .text.HAL_RCC_ClockConfig:00000000 HAL_RCC_ClockConfig
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2769 .text.HAL_RCC_ClockConfig:00000194 $d
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2778 .text.HAL_RCC_GetHCLKFreq:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2784 .text.HAL_RCC_GetHCLKFreq:00000000 HAL_RCC_GetHCLKFreq
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2799 .text.HAL_RCC_GetHCLKFreq:00000008 $d
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2804 .text.HAL_RCC_GetPCLK1Freq:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2810 .text.HAL_RCC_GetPCLK1Freq:00000000 HAL_RCC_GetPCLK1Freq
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2860 .text.HAL_RCC_GetPCLK1Freq:00000024 $d
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2866 .text.HAL_RCC_GetPCLK2Freq:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2872 .text.HAL_RCC_GetPCLK2Freq:00000000 HAL_RCC_GetPCLK2Freq
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2922 .text.HAL_RCC_GetPCLK2Freq:00000024 $d
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2928 .text.HAL_RCC_GetOscConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:2934 .text.HAL_RCC_GetOscConfig:00000000 HAL_RCC_GetOscConfig
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:3118 .text.HAL_RCC_GetOscConfig:000000bc $d
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:3123 .text.HAL_RCC_GetClockConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:3129 .text.HAL_RCC_GetClockConfig:00000000 HAL_RCC_GetClockConfig
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:3186 .text.HAL_RCC_GetClockConfig:00000034 $d
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:3192 .text.HAL_RCC_CSSCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:3198 .text.HAL_RCC_CSSCallback:00000000 HAL_RCC_CSSCallback
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:3211 .text.HAL_RCC_NMI_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:3217 .text.HAL_RCC_NMI_IRQHandler:00000000 HAL_RCC_NMI_IRQHandler
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:3250 .text.HAL_RCC_NMI_IRQHandler:0000001c $d
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:3255 .rodata.aPredivFactorTable:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccleyZTU.s:3262 .rodata.aPLLMULFactorTable:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:21 .text.HAL_RCC_DeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:27 .text.HAL_RCC_DeInit:00000000 HAL_RCC_DeInit
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:228 .text.HAL_RCC_DeInit:000000dc $d
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:238 .text.HAL_RCC_OscConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:244 .text.HAL_RCC_OscConfig:00000000 HAL_RCC_OscConfig
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:1056 .text.HAL_RCC_OscConfig:000002e8 $d
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:1067 .text.HAL_RCC_OscConfig:000002f0 $t
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:1915 .text.HAL_RCC_OscConfig:000005d8 $d
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:1922 .text.HAL_RCC_OscConfig:000005e4 $t
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2019 .text.HAL_RCC_OscConfig:0000062c $d
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2024 .text.HAL_RCC_MCOConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2030 .text.HAL_RCC_MCOConfig:00000000 HAL_RCC_MCOConfig
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2111 .text.HAL_RCC_MCOConfig:00000048 $d
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2116 .text.HAL_RCC_EnableCSS:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2122 .text.HAL_RCC_EnableCSS:00000000 HAL_RCC_EnableCSS
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2163 .text.HAL_RCC_DisableCSS:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2169 .text.HAL_RCC_DisableCSS:00000000 HAL_RCC_DisableCSS
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2210 .text.HAL_RCC_GetSysClockFreq:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2216 .text.HAL_RCC_GetSysClockFreq:00000000 HAL_RCC_GetSysClockFreq
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2337 .text.HAL_RCC_GetSysClockFreq:00000064 $d
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:3265 .rodata.aPLLMULFactorTable:00000000 aPLLMULFactorTable
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:3258 .rodata.aPredivFactorTable:00000000 aPredivFactorTable
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2347 .text.HAL_RCC_ClockConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2353 .text.HAL_RCC_ClockConfig:00000000 HAL_RCC_ClockConfig
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2769 .text.HAL_RCC_ClockConfig:00000194 $d
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2778 .text.HAL_RCC_GetHCLKFreq:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2784 .text.HAL_RCC_GetHCLKFreq:00000000 HAL_RCC_GetHCLKFreq
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2799 .text.HAL_RCC_GetHCLKFreq:00000008 $d
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2804 .text.HAL_RCC_GetPCLK1Freq:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2810 .text.HAL_RCC_GetPCLK1Freq:00000000 HAL_RCC_GetPCLK1Freq
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2860 .text.HAL_RCC_GetPCLK1Freq:00000024 $d
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2866 .text.HAL_RCC_GetPCLK2Freq:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2872 .text.HAL_RCC_GetPCLK2Freq:00000000 HAL_RCC_GetPCLK2Freq
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2922 .text.HAL_RCC_GetPCLK2Freq:00000024 $d
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2928 .text.HAL_RCC_GetOscConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:2934 .text.HAL_RCC_GetOscConfig:00000000 HAL_RCC_GetOscConfig
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:3118 .text.HAL_RCC_GetOscConfig:000000bc $d
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:3123 .text.HAL_RCC_GetClockConfig:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:3129 .text.HAL_RCC_GetClockConfig:00000000 HAL_RCC_GetClockConfig
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:3186 .text.HAL_RCC_GetClockConfig:00000034 $d
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:3192 .text.HAL_RCC_CSSCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:3198 .text.HAL_RCC_CSSCallback:00000000 HAL_RCC_CSSCallback
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:3211 .text.HAL_RCC_NMI_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:3217 .text.HAL_RCC_NMI_IRQHandler:00000000 HAL_RCC_NMI_IRQHandler
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:3250 .text.HAL_RCC_NMI_IRQHandler:0000001c $d
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:3255 .rodata.aPredivFactorTable:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s:3262 .rodata.aPLLMULFactorTable:00000000 $d
UNDEFINED SYMBOLS
HAL_GetTick
@ -6312,7 +6312,7 @@ SystemCoreClock
uwTickPrio
HAL_GPIO_Init
AHBPrescTable
ARM GAS C:\Users\nived\AppData\Local\Temp\ccleyZTU.s page 107
ARM GAS C:\Users\nived\AppData\Local\Temp\ccV7K3yz.s page 107
APBPrescTable

Some files were not shown because too many files have changed in this diff Show More