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update IOC & regenerate

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2024-06-11 17:57:43 +02:00
parent 60ddc046d0
commit 9aca436798
85 changed files with 2152 additions and 1390 deletions
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6
Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xc.h
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@ -1996,9 +1996,9 @@ typedef struct
#define ADC34_CSR_ADRDY_EOS_SLV_Pos (19U)
#define ADC34_CSR_ADRDY_EOS_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */
#define ADC34_CSR_ADRDY_EOS_SLV ADC34_CSR_ADRDY_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
#define ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)
#define ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
#define ADC34_CSR_ADRDY_OVR_SLV_Pos (20U)
#define ADC34_CSR_ADRDY_OVR_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC34_CSR_ADRDY_OVR_SLV ADC34_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
#define ADC34_CSR_ADRDY_JEOC_SLV_Pos (21U)
#define ADC34_CSR_ADRDY_JEOC_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */
#define ADC34_CSR_ADRDY_JEOC_SLV ADC34_CSR_ADRDY_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */

6
Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xe.h
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@ -2107,9 +2107,9 @@ typedef struct
#define ADC34_CSR_ADRDY_EOS_SLV_Pos (19U)
#define ADC34_CSR_ADRDY_EOS_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */
#define ADC34_CSR_ADRDY_EOS_SLV ADC34_CSR_ADRDY_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
#define ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)
#define ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
#define ADC34_CSR_ADRDY_OVR_SLV_Pos (20U)
#define ADC34_CSR_ADRDY_OVR_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC34_CSR_ADRDY_OVR_SLV ADC34_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
#define ADC34_CSR_ADRDY_JEOC_SLV_Pos (21U)
#define ADC34_CSR_ADRDY_JEOC_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */
#define ADC34_CSR_ADRDY_JEOC_SLV ADC34_CSR_ADRDY_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */

6
Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h
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@ -1998,9 +1998,9 @@ typedef struct
#define ADC34_CSR_ADRDY_EOS_SLV_Pos (19U)
#define ADC34_CSR_ADRDY_EOS_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */
#define ADC34_CSR_ADRDY_EOS_SLV ADC34_CSR_ADRDY_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
#define ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)
#define ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
#define ADC34_CSR_ADRDY_OVR_SLV_Pos (20U)
#define ADC34_CSR_ADRDY_OVR_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC34_CSR_ADRDY_OVR_SLV ADC34_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
#define ADC34_CSR_ADRDY_JEOC_SLV_Pos (21U)
#define ADC34_CSR_ADRDY_JEOC_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */
#define ADC34_CSR_ADRDY_JEOC_SLV ADC34_CSR_ADRDY_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */

6
Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f358xx.h
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@ -1954,9 +1954,9 @@ typedef struct
#define ADC34_CSR_ADRDY_EOS_SLV_Pos (19U)
#define ADC34_CSR_ADRDY_EOS_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */
#define ADC34_CSR_ADRDY_EOS_SLV ADC34_CSR_ADRDY_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
#define ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)
#define ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
#define ADC34_CSR_ADRDY_OVR_SLV_Pos (20U)
#define ADC34_CSR_ADRDY_OVR_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC34_CSR_ADRDY_OVR_SLV ADC34_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
#define ADC34_CSR_ADRDY_JEOC_SLV_Pos (21U)
#define ADC34_CSR_ADRDY_JEOC_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */
#define ADC34_CSR_ADRDY_JEOC_SLV ADC34_CSR_ADRDY_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */

10
Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f373xc.h
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@ -7363,9 +7363,13 @@ typedef struct
#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
/******************* Bit definition for CEC_RXDR register *******************/
#define CEC_TXDR_RXD_Pos (0U)
#define CEC_TXDR_RXD_Msk (0xFFUL << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */
#define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */
#define CEC_RXDR_RXD_Pos (0U)
#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */
#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */
/* Legacy aliases */
#define CEC_TXDR_RXD_Pos CEC_RXDR_RXD_Pos
#define CEC_TXDR_RXD_Msk CEC_RXDR_RXD_Msk
#define CEC_TXDR_RXD CEC_RXDR_RXD
/******************* Bit definition for CEC_ISR register ********************/
#define CEC_ISR_RXBR_Pos (0U)

10
Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f378xx.h
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@ -7304,9 +7304,13 @@ typedef struct
#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
/******************* Bit definition for CEC_RXDR register *******************/
#define CEC_TXDR_RXD_Pos (0U)
#define CEC_TXDR_RXD_Msk (0xFFUL << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */
#define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */
#define CEC_RXDR_RXD_Pos (0U)
#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */
#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */
/* Legacy aliases */
#define CEC_TXDR_RXD_Pos CEC_RXDR_RXD_Pos
#define CEC_TXDR_RXD_Msk CEC_RXDR_RXD_Msk
#define CEC_TXDR_RXD CEC_RXDR_RXD
/******************* Bit definition for CEC_ISR register ********************/
#define CEC_ISR_RXBR_Pos (0U)

6
Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f398xx.h
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@ -2063,9 +2063,9 @@ typedef struct
#define ADC34_CSR_ADRDY_EOS_SLV_Pos (19U)
#define ADC34_CSR_ADRDY_EOS_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */
#define ADC34_CSR_ADRDY_EOS_SLV ADC34_CSR_ADRDY_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
#define ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)
#define ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
#define ADC34_CSR_ADRDY_OVR_SLV_Pos (20U)
#define ADC34_CSR_ADRDY_OVR_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC34_CSR_ADRDY_OVR_SLV ADC34_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
#define ADC34_CSR_ADRDY_JEOC_SLV_Pos (21U)
#define ADC34_CSR_ADRDY_JEOC_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */
#define ADC34_CSR_ADRDY_JEOC_SLV ADC34_CSR_ADRDY_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */

4
Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h
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@ -102,11 +102,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.7
* @brief CMSIS Device version number V2.3.8
*/
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x07) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x08) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\