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Master_Control/stm32g441xx.svd
jazzpi 7795a7cd7d Working version
2022-07-18 16:54:42 +02:00

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<?xml version="1.0" encoding="UTF-8"?>
<!--
Copyright (c) 2022 STMicroelectronics.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
-->
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32G441xx</name>
<version>1.9</version>
<description>STM32G441xx</description>
<cpu>
<name>CM4</name>
<revision>r0p1</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<fpuPresent>true</fpuPresent>
<nvicPrioBits>4</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<size>0x20</size>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<peripherals>
<peripheral>
<name>CRC</name>
<description>Cyclic redundancy check calculation unit</description>
<groupName>CRC</groupName>
<baseAddress>0x40023000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>Data register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>DR</name>
<description>Data register bits</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<displayName>IDR</displayName>
<description>Independent data register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDR</name>
<description>General-purpose 8-bit data register bits</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REV_OUT</name>
<description>Reverse output data</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>REV_IN</name>
<description>Reverse input data</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>POLYSIZE</name>
<description>Polynomial size</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RESET</name>
<description>RESET bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>INIT</name>
<displayName>INIT</displayName>
<description>Initial CRC value</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>CRC_INIT</name>
<description>Programmable initial CRC value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>POL</name>
<displayName>POL</displayName>
<description>polynomial</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x04C11DB7</resetValue>
<fields>
<field>
<name>POL</name>
<description>Programmable polynomial</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>IWDG</name>
<description>WinWATCHDOG</description>
<groupName>IWDG</groupName>
<baseAddress>0x40003000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>KR</name>
<displayName>KR</displayName>
<description>Key register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEY</name>
<description>Key value (write only, read 0x0000)</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PR</name>
<displayName>PR</displayName>
<description>Prescaler register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PR</name>
<description>Prescaler divider</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR</name>
<displayName>RLR</displayName>
<description>Reload register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000FFF</resetValue>
<fields>
<field>
<name>RL</name>
<description>Watchdog counter reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>Status register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WVU</name>
<description>Watchdog counter window value update</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RVU</name>
<description>Watchdog counter reload value update</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVU</name>
<description>Watchdog prescaler value update</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WINR</name>
<displayName>WINR</displayName>
<description>Window register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000FFF</resetValue>
<fields>
<field>
<name>WIN</name>
<description>Watchdog counter window value</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>WWDG</name>
<description>System window watchdog</description>
<groupName>WWDG</groupName>
<baseAddress>0x40002C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000007F</resetValue>
<fields>
<field>
<name>WDGA</name>
<description>Activation bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T</name>
<description>7-bit counter (MSB to LSB)</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFR</name>
<displayName>CFR</displayName>
<description>Configuration register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000007F</resetValue>
<fields>
<field>
<name>WDGTB</name>
<description>Timer base</description>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>EWI</name>
<description>Early wakeup interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>W</name>
<description>7-bit window value</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>Status register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EWIF</name>
<description>Early wakeup interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>I2C1</name>
<description>Inter-integrated circuit</description>
<groupName>I2C</groupName>
<baseAddress>0x40005400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C1_EV</name>
<description>I2C1_EV</description>
<value>31</value>
</interrupt>
<interrupt>
<name>I2C1_ER</name>
<description>I2C1_ER</description>
<value>32</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>Control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PE</name>
<description>Peripheral enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXIE</name>
<description>TX Interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXIE</name>
<description>RX Interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDRIE</name>
<description>Address match interrupt enable (slave only)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACKIE</name>
<description>Not acknowledge received interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOPIE</name>
<description>STOP detection Interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer Complete interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRIE</name>
<description>Error interrupts enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DNF</name>
<description>Digital noise filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ANFOFF</name>
<description>Analog noise filter OFF</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXDMAEN</name>
<description>DMA transmission requests enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXDMAEN</name>
<description>DMA reception requests enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBC</name>
<description>Slave byte control</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOSTRETCH</name>
<description>Clock stretching disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUPEN</name>
<description>Wakeup from STOP enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GCEN</name>
<description>General call enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBHEN</name>
<description>SMBus Host address enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBDEN</name>
<description>SMBus Device Default address enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALERTEN</name>
<description>SMBUS alert enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECEN</name>
<description>PEC enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>Control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PECBYTE</name>
<description>Packet error checking byte</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AUTOEND</name>
<description>Automatic end mode (master mode)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RELOAD</name>
<description>NBYTES reload mode</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBYTES</name>
<description>Number of bytes</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>NACK</name>
<description>NACK generation (slave mode)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOP</name>
<description>Stop generation (master mode)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>START</name>
<description>Start generation</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HEAD10R</name>
<description>10-bit address header only read direction (master receiver mode)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADD10</name>
<description>10-bit addressing mode (master mode)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_WRN</name>
<description>Transfer direction (master mode)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADD</name>
<description>Slave address bit (master mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>OAR1</name>
<displayName>OAR1</displayName>
<description>Own address register 1</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OA1</name>
<description>Interface address</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>OA1MODE</name>
<description>Own Address 1 10-bit mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OA1EN</name>
<description>Own Address 1 enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OAR2</name>
<displayName>OAR2</displayName>
<description>Own address register 2</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OA2</name>
<description>Interface address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>OA2MSK</name>
<description>Own Address 2 masks</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OA2EN</name>
<description>Own Address 2 enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMINGR</name>
<displayName>TIMINGR</displayName>
<description>Timing register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCLL</name>
<description>SCL low period (master mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SCLH</name>
<description>SCL high period (master mode)</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SDADEL</name>
<description>Data hold time</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SCLDEL</name>
<description>Data setup time</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PRESC</name>
<description>Timing prescaler</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMEOUTR</name>
<displayName>TIMEOUTR</displayName>
<description>Status register 1</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMEOUTA</name>
<description>Bus timeout A</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>TIDLE</name>
<description>Idle clock timeout detection</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMOUTEN</name>
<description>Clock timeout enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEOUTB</name>
<description>Bus timeout B</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>TEXTEN</name>
<description>Extended clock timeout enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Interrupt and Status register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>ADDCODE</name>
<description>Address match code (Slave mode)</description>
<bitOffset>17</bitOffset>
<bitWidth>7</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DIR</name>
<description>Transfer direction (Slave mode)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BUSY</name>
<description>Bus busy</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ALERT</name>
<description>SMBus alert</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TIMEOUT</name>
<description>Timeout or t_low detection flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PECERR</name>
<description>PEC Error in reception</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVR</name>
<description>Overrun/Underrun (slave mode)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ARLO</name>
<description>Arbitration lost</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BERR</name>
<description>Bus error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TCR</name>
<description>Transfer Complete Reload</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TC</name>
<description>Transfer Complete (master mode)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>STOPF</name>
<description>Stop detection flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NACKF</name>
<description>Not acknowledge received flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ADDR</name>
<description>Address matched (slave mode)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RXNE</name>
<description>Receive data register not empty (receivers)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXIS</name>
<description>Transmit interrupt status (transmitters)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXE</name>
<description>Transmit data register empty (transmitters)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>Interrupt clear register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ALERTCF</name>
<description>Alert flag clear</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMOUTCF</name>
<description>Timeout detection flag clear</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECCF</name>
<description>PEC Error flag clear</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRCF</name>
<description>Overrun/Underrun flag clear</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARLOCF</name>
<description>Arbitration lost flag clear</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BERRCF</name>
<description>Bus error flag clear</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOPCF</name>
<description>Stop detection flag clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACKCF</name>
<description>Not Acknowledge flag clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDRCF</name>
<description>Address Matched flag clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PECR</name>
<displayName>PECR</displayName>
<description>PEC register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PEC</name>
<description>Packet error checking register</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXDR</name>
<displayName>RXDR</displayName>
<description>Receive data register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXDATA</name>
<description>8-bit receive data</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXDR</name>
<displayName>TXDR</displayName>
<description>Transmit data register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXDATA</name>
<description>8-bit transmit data</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="I2C1">
<name>I2C2</name>
<baseAddress>0x40005800</baseAddress>
<interrupt>
<name>WWDG</name>
<description>Window Watchdog interrupt</description>
<value>0</value>
</interrupt>
<interrupt>
<name>I2C2_EV</name>
<description>I2C2_EV</description>
<value>33</value>
</interrupt>
<interrupt>
<name>I2C2_ER</name>
<description>I2C2_ER</description>
<value>34</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="I2C1">
<name>I2C3</name>
<baseAddress>0x40007800</baseAddress>
<interrupt>
<name>I2C3_EV</name>
<description>I2C3_EV</description>
<value>92</value>
</interrupt>
<interrupt>
<name>I2C3_ER</name>
<description>I2C3_ER</description>
<value>93</value>
</interrupt>
</peripheral>
<peripheral>
<name>FLASH</name>
<description>Flash</description>
<groupName>Flash</groupName>
<baseAddress>0x40022000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FLASH</name>
<description>FLASH</description>
<value>4</value>
</interrupt>
<registers>
<register>
<name>ACR</name>
<displayName>ACR</displayName>
<description>Access control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000600</resetValue>
<fields>
<field>
<name>LATENCY</name>
<description>Latency</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PRFTEN</name>
<description>Prefetch enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ICEN</name>
<description>Instruction cache enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DCEN</name>
<description>Data cache enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ICRST</name>
<description>Instruction cache reset</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DCRST</name>
<description>Data cache reset</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RUN_PD</name>
<description>Flash Power-down mode during Low-power run mode</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLEEP_PD</name>
<description>Flash Power-down mode during Low-power sleep mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_SWEN</name>
<description>Debug software enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PDKEYR</name>
<displayName>PDKEYR</displayName>
<description>Power down key register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PDKEYR</name>
<description>RUN_PD in FLASH_ACR key</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR</name>
<displayName>KEYR</displayName>
<description>Flash key register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEYR</name>
<description>KEYR</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPTKEYR</name>
<displayName>OPTKEYR</displayName>
<description>Option byte key register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OPTKEYR</name>
<description>Option byte key</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>Status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EOP</name>
<description>End of operation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OPERR</name>
<description>Operation error</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PROGERR</name>
<description>Programming error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WRPERR</name>
<description>Write protected error</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PGAERR</name>
<description>Programming alignment error</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SIZERR</name>
<description>Size error</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PGSERR</name>
<description>Programming sequence error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MISERR</name>
<description>Fast programming data miss error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FASTERR</name>
<description>Fast programming error</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RDERR</name>
<description>PCROP read error</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OPTVERR</name>
<description>Option validity error</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BSY</name>
<description>Busy</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Flash control register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xC0000000</resetValue>
<fields>
<field>
<name>PG</name>
<description>Programming</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>Page erase</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MER1</name>
<description>Bank 1 Mass erase</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PNB</name>
<description>Page number</description>
<bitOffset>3</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>STRT</name>
<description>Start</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPTSTRT</name>
<description>Options modification start</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTPG</name>
<description>Fast programming</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOPIE</name>
<description>End of operation interrupt enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRIE</name>
<description>Error interrupt enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDERRIE</name>
<description>PCROP read error interrupt enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OBL_LAUNCH</name>
<description>Force the option byte loading</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SEC_PROT1</name>
<description>SEC_PROT1</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPTLOCK</name>
<description>Options Lock</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>FLASH_CR Lock</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ECCR</name>
<displayName>ECCR</displayName>
<description>Flash ECC register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDR_ECC</name>
<description>ECC fail address</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BK_ECC</name>
<description>BK_ECC</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SYSF_ECC</name>
<description>SYSF_ECC</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ECCIE</name>
<description>ECCIE</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ECCC2</name>
<description>ECC correction</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ECCD2</name>
<description>ECC2 detection</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ECCC</name>
<description>ECC correction</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ECCD</name>
<description>ECC detection</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OPTR</name>
<displayName>OPTR</displayName>
<description>Flash option register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xF0000000</resetValue>
<fields>
<field>
<name>RDP</name>
<description>Read protection level</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BOR_LEV</name>
<description>BOR reset Level</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>nRST_STOP</name>
<description>nRST_STOP</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nRST_STDBY</name>
<description>nRST_STDBY</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nRST_SHDW</name>
<description>nRST_SHDW</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDWG_SW</name>
<description>Independent watchdog selection</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IWDG_STOP</name>
<description>Independent watchdog counter freeze in Stop mode</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IWDG_STDBY</name>
<description>Independent watchdog counter freeze in Standby mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WWDG_SW</name>
<description>Window watchdog selection</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nBOOT1</name>
<description>Boot configuration</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRAM2_PE</name>
<description>SRAM2 parity check enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRAM2_RST</name>
<description>SRAM2 Erase when system reset</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nSWBOOT0</name>
<description>nSWBOOT0</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nBOOT0</name>
<description>nBOOT0</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NRST_MODE</name>
<description>NRST_MODE</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IRHEN</name>
<description>IRHEN</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCROP1SR</name>
<displayName>PCROP1SR</displayName>
<description>Flash Bank 1 PCROP Start address register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFF0000</resetValue>
<fields>
<field>
<name>PCROP1_STRT</name>
<description>Bank 1 PCROP area start offset</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCROP1ER</name>
<displayName>PCROP1ER</displayName>
<description>Flash Bank 1 PCROP End address register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFF0000</resetValue>
<fields>
<field>
<name>PCROP1_END</name>
<description>Bank 1 PCROP area end offset</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
</field>
<field>
<name>PCROP_RDP</name>
<description>PCROP area preserved when RDP level decreased</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WRP1AR</name>
<displayName>WRP1AR</displayName>
<description>Flash Bank 1 WRP area A address register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WRP1A_STRT</name>
<description>Bank 1 WRP first area start offset</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>WRP1A_END</name>
<description>Bank 1 WRP first area A end offset</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>WRP1BR</name>
<displayName>WRP1BR</displayName>
<description>Flash Bank 1 WRP area B address register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WRP1B_STRT</name>
<description>Bank 1 WRP second area B end offset</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>WRP1B_END</name>
<description>Bank 1 WRP second area B start offset</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>SEC1R</name>
<displayName>SEC1R</displayName>
<description>securable area bank1 register</description>
<addressOffset>0x70</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFF00FF00</resetValue>
<fields>
<field>
<name>BOOT_LOCK</name>
<description>BOOT_LOCK</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SEC_SIZE1</name>
<description>SEC_SIZE1</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DBGMCU</name>
<description>Debug support</description>
<groupName>DBGMCU</groupName>
<baseAddress>0xE0042000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>IDCODE</name>
<displayName>IDCODE</displayName>
<description>MCU Device ID Code Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DEV_ID</name>
<description>Device Identifier</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>REV_ID</name>
<description>Revision Identifier</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Debug MCU Configuration Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DBG_SLEEP</name>
<description>Debug Sleep Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_STOP</name>
<description>Debug Stop Mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_STANDBY</name>
<description>Debug Standby Mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRACE_IOEN</name>
<description>Trace pin assignment control</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRACE_MODE</name>
<description>Trace pin assignment control</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB1L_FZ</name>
<displayName>APB1L_FZ</displayName>
<description>APB Low Freeze Register 1</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DBG_TIMER2_STOP</name>
<description>Debug Timer 2 stopped when Core is halted</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM3_STOP</name>
<description>TIM3 counter stopped when core is halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM4_STOP</name>
<description>TIM4 counter stopped when core is halted</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM5_STOP</name>
<description>TIM5 counter stopped when core is halted</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIMER6_STOP</name>
<description>Debug Timer 6 stopped when Core is halted</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM7_STOP</name>
<description>TIM7 counter stopped when core is halted</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_RTC_STOP</name>
<description>Debug RTC stopped when Core is halted</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_WWDG_STOP</name>
<description>Debug Window Wachdog stopped when Core is halted</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_IWDG_STOP</name>
<description>Debug Independent Wachdog stopped when Core is halted</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_I2C1_STOP</name>
<description>I2C1 SMBUS timeout mode stopped when core is halted</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_I2C2_STOP</name>
<description>I2C2 SMBUS timeout mode stopped when core is halted</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_I2C3_STOP</name>
<description>I2C3 SMBUS timeout mode stopped when core is halted</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_LPTIMER_STOP</name>
<description>LPTIM1 counter stopped when core is halted</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB1H_FZ</name>
<displayName>APB1H_FZ</displayName>
<description>APB Low Freeze Register 2</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DBG_I2C4_STOP</name>
<description>DBG_I2C4_STOP</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB2_FZ</name>
<displayName>APB2_FZ</displayName>
<description>APB High Freeze Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DBG_TIM1_STOP</name>
<description>TIM1 counter stopped when core is halted</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM8_STOP</name>
<description>TIM8 counter stopped when core is halted</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM15_STOP</name>
<description>TIM15 counter stopped when core is halted</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM16_STOP</name>
<description>TIM16 counter stopped when core is halted</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM17_STOP</name>
<description>TIM17 counter stopped when core is halted</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM20_STOP</name>
<description>TIM20counter stopped when core is halted</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_HRTIM0_STOP</name>
<description>DBG_HRTIM0_STOP</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_HRTIM1_STOP</name>
<description>DBG_HRTIM0_STOP</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_HRTIM2_STOP</name>
<description>DBG_HRTIM0_STOP</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_HRTIM3_STOP</name>
<description>DBG_HRTIM0_STOP</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RCC</name>
<description>Reset and clock control</description>
<groupName>RCC</groupName>
<baseAddress>0x40021000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RCC</name>
<description>RCC global interrupt</description>
<value>5</value>
</interrupt>
<registers>
<register>
<name>RCC_CR</name>
<displayName>RCC_CR</displayName>
<description>Clock control register</description>
<addressOffset>0x00</addressOffset>
<size>0x20</size>
<resetValue>0x00000063</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HSION</name>
<description>HSI16 clock enable
Set and cleared by software.
Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown mode.
Set by hardware to force the HSI16 oscillator ON when STOPWUCK=1 or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator.
This bit is set by hardware if the HSI16 is used directly or indirectly as system clock.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSI16 oscillator OFF</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSI16 oscillator ON</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSIKERON</name>
<description>HSI16 always enable for peripheral kernels.
Set and cleared by software to force HSI16 ON even in Stop modes. The HSI16 can only feed USARTs and I&lt;sup&gt;2&lt;/sup&gt;Cs peripherals configured with HSI16 as kernel clock. Keeping the HSI16 ON in Stop mode allows to avoid slowing down the communication speed because of the HSI16 startup time. This bit has no effect on HSION value.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect on HSI16 oscillator.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSI16 oscillator is forced ON even in Stop mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSIRDY</name>
<description>HSI16 clock ready flag
Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION.
Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI16 clock cycles.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSI16 oscillator not ready</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSI16 oscillator ready</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSEON</name>
<description>HSE clock enable
Set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSE oscillator OFF</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSE oscillator ON</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSERDY</name>
<description>HSE clock ready flag
Set by hardware to indicate that the HSE oscillator is stable.
Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSE oscillator not ready</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSE oscillator ready</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSEBYP</name>
<description>HSE crystal oscillator bypass
Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSE crystal oscillator not bypassed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSE crystal oscillator bypassed with external clock</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSSON</name>
<description>Clock security system enable
Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Clock security system OFF (clock detector OFF)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLON</name>
<description>Main PLL enable
Set and cleared by software to enable the main PLL.
Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL clock is used as the system clock.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL OFF</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL ON</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLRDY</name>
<description>Main PLL clock ready flag
Set by hardware to indicate that the main PLL is locked.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL unlocked</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL locked</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_ICSCR</name>
<displayName>RCC_ICSCR</displayName>
<description>Internal clock sources calibration register</description>
<addressOffset>0x04</addressOffset>
<size>0x20</size>
<resetValue>0x40000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HSICAL</name>
<description>HSI16 clock calibration
These bits are initialized at startup with the factory-programmed HSI16 calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value.</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HSITRIM</name>
<description>HSI16 clock trimming
These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI16.
The default value is 16, which, when added to the HSICAL value, should trim the HSI16 to 16 MHz <20> 1 %.</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RCC_CFGR</name>
<displayName>RCC_CFGR</displayName>
<description>Clock configuration register</description>
<addressOffset>0x08</addressOffset>
<size>0x20</size>
<resetValue>0x00000005</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SW</name>
<description>System clock switch
Set and cleared by software to select system clock source (SYSCLK).
Configured by hardware to force HSI16 oscillator selection when exiting stop and standby modes or in case of failure of the HSE oscillator.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Reserved, must be kept at reset value</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSI16 selected as system clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>HSE selected as system clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>PLL selected as system clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWS</name>
<description>System clock switch status
Set and cleared by hardware to indicate which clock source is used as system clock.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Reserved, must be kept at reset value</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSI16 oscillator used as system clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>HSE used as system clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>PLL used as system clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HPRE</name>
<description>AHB prescaler
Set and cleared by software to control the division factor of the AHB clock.
Note: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details please refer to Section 6.1.5: Dynamic voltage scaling management). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account.
0xxx: SYSCLK not divided</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x8</name>
<description>SYSCLK divided by 2</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x9</name>
<description>SYSCLK divided by 4</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xA</name>
<description>SYSCLK divided by 8</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xB</name>
<description>SYSCLK divided by 16</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xC</name>
<description>SYSCLK divided by 64</description>
<value>0xC</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xD</name>
<description>SYSCLK divided by 128</description>
<value>0xD</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xE</name>
<description>SYSCLK divided by 256</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xF</name>
<description>SYSCLK divided by 512</description>
<value>0xF</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PPRE1</name>
<description>APB1 prescaler
Set and cleared by software to control the division factor of the APB1 clock (PCLK1).
0xx: HCLK not divided</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x4</name>
<description>HCLK divided by 2</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x5</name>
<description>HCLK divided by 4</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x6</name>
<description>HCLK divided by 8</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7</name>
<description>HCLK divided by 16</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PPRE2</name>
<description>APB2 prescaler
Set and cleared by software to control the division factor of the APB2 clock (PCLK2).
0xx: HCLK not divided</description>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x4</name>
<description>HCLK divided by 2</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x5</name>
<description>HCLK divided by 4</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x6</name>
<description>HCLK divided by 8</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7</name>
<description>HCLK divided by 16</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MCOSEL</name>
<description>Microcontroller clock output
Set and cleared by software.
Others: Reserved
Note: This clock output may have some truncated cycles at startup or during MCO clock source switching.</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>MCO output disabled, no clock on MCO</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SYSCLK system clock selected</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Reserved, must be kept at reset value</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>HSI16 clock selected</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>HSE clock selected</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x5</name>
<description>Main PLL clock selected</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x6</name>
<description>LSI clock selected</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7</name>
<description>LSE clock selected</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x8</name>
<description>Internal HSI48 clock selected</description>
<value>0x8</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MCOPRE</name>
<description>Microcontroller clock output prescaler
These bits are set and cleared by software.
It is highly recommended to change this prescaler before MCO output is enabled.
Others: not allowed</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>MCO is divided by 1</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>MCO is divided by 2</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>MCO is divided by 4</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>MCO is divided by 8</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>MCO is divided by 16</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_PLLCFGR</name>
<displayName>RCC_PLLCFGR</displayName>
<description>PLL configuration register</description>
<addressOffset>0x0C</addressOffset>
<size>0x20</size>
<resetValue>0x00001000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PLLSRC</name>
<description>Main PLL entry clock source
Set and cleared by software to select PLL clock source. These bits can be written only when PLL is disabled.
In order to save power, when no PLL is used, the value of PLLSRC should be 00.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No clock sent to PLL</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>No clock sent to PLL</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>HSI16 clock selected as PLL clock entry</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>HSE clock selected as PLL clock entry</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLM</name>
<description>Division factor for the main PLL input clock
Set and cleared by software to divide the PLL input clock before the VCO. These bits can be written only when all PLLs are disabled.
VCO input frequency = PLL input clock frequency / PLLM with 1 &lt;= PLLM &lt;= 16
...
Note: The software has to set these bits correctly to ensure that the VCO input frequency is within the range defined in the device datasheet.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLLM = 1</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLLM = 2</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>PLLM = 3</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>PLLM = 4</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>PLLM = 5</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x5</name>
<description>PLLM = 6</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x6</name>
<description>PLLM = 7</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7</name>
<description>PLLM = 8</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x8</name>
<description>PLLSYSM = 9</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xF</name>
<description>PLLSYSM= 16</description>
<value>0xF</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLN</name>
<description>Main PLL multiplication factor for VCO
Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled.
VCO output frequency = VCO input frequency x PLLN with 8 =&lt; PLLN =&lt; 127
...
...
Note: The software has to set correctly these bits to assure that the VCO output frequency is within the range defined in the device datasheet.</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLLN = 0 wrong configuration</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLLN = 1 wrong configuration</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7</name>
<description>PLLN = 7 wrong configuration</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x8</name>
<description>PLLN = 8</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x9</name>
<description>PLLN = 9</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7F</name>
<description>PLLN = 127</description>
<value>0x7F</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLPEN</name>
<description>Main PLL PLL “P” clock output enable
Set and reset by software to enable the PLL “P” clock output of the PLL.
In order to save power, when the PLL “P” clock output of the PLL is not used, the value of PLLPEN should be 0.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL “P” clock output disable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL “P” clock output enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLP</name>
<description>Main PLL division factor for PLL “P” clock.
Set and cleared by software to control the frequency of the main PLL output clock PLL “P” clock. These bits can be written only if PLL is disabled.
When the PLLPDIV[4:0] is set to “00000”PLL “P” output clock frequency = VCO frequency / PLLP with PLLP =7, or 17
Note: The software has to set these bits correctly not to exceed 170 MHz on this domain.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLLP = 7</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLLP = 17</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLQEN</name>
<description>Main PLL “Q” clock output enable
Set and reset by software to enable the PLL “Q” clock output of the PLL.
In order to save power, when the PLL “Q” clock output of the PLL is not used, the value of PLLQEN should be 0.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL “Q” clock output disable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL “Q” clock output enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLQ</name>
<description>Main PLL division factor for PLL “Q” clock.
Set and cleared by software to control the frequency of the main PLL output clock PLL “Q” clock. This output can be selected for USB, RNG, SAI (48 MHz clock). These bits can be written only if PLL is disabled.
PLL “Q” output clock frequency = VCO frequency / PLLQ with PLLQ = 2, 4, 6, or 8
Note: The software has to set these bits correctly not to exceed 170 MHz on this domain.</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLLQ = 2</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLLQ = 4</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>PLLQ = 6</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>PLLQ = 8</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLREN</name>
<description>PLL “R” clock output enable
Set and reset by software to enable the PLL “R” clock output of the PLL (used as system clock).
This bit cannot be written when PLL “R” clock output of the PLL is used as System Clock.
In order to save power, when the PLL “R” clock output of the PLL is not used, the value of PLLREN should be 0.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL “R” clock output disable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL “R” clock output enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLR</name>
<description>Main PLL division factor for PLL “R” clock (system clock)
Set and cleared by software to control the frequency of the main PLL output clock PLLCLK. This output can be selected as system clock. These bits can be written only if PLL is disabled.
PLL “R” output clock frequency = VCO frequency / PLLR with PLLR = 2, 4, 6, or 8
Note: The software has to set these bits correctly not to exceed 170 MHz on this domain.</description>
<bitOffset>25</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLLR = 2</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLLR = 4</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>PLLR = 6</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>PLLR = 8</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLPDIV</name>
<description>Main PLLP division factor
Set and cleared by software to control the PLL “P” frequency. PLL “P” output clock frequency = VCO frequency / PLLPDIV.
....</description>
<bitOffset>27</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL “P” clock is controlled by the bit PLLP</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reserved.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>PLL “P” clock = VCO / 2</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1F</name>
<description>PLL “P” clock = VCO / 31</description>
<value>0x1F</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_CIER</name>
<displayName>RCC_CIER</displayName>
<description>Clock interrupt enable register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LSIRDYIE</name>
<description>LSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LSI ready interrupt disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSI ready interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSERDYIE</name>
<description>LSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LSE ready interrupt disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSE ready interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSIRDYIE</name>
<description>HSI16 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSI16 ready interrupt disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSI16 ready interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSERDYIE</name>
<description>HSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSE ready interrupt disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSE ready interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLRDYIE</name>
<description>PLL ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLL lock.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL lock interrupt disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL lock interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSECSSIE</name>
<description>LSE clock security system interrupt enable
Set and cleared by software to enable/disable interrupt caused by the clock security system on LSE.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Clock security interrupt caused by LSE clock failure disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clock security interrupt caused by LSE clock failure enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSI48RDYIE</name>
<description>HSI48 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the internal HSI48 oscillator.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSI48 ready interrupt disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSI48 ready interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_CIFR</name>
<displayName>RCC_CIFR</displayName>
<description>Clock interrupt flag register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LSIRDYF</name>
<description>LSI ready interrupt flag
Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No clock ready interrupt caused by the LSI oscillator</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clock ready interrupt caused by the LSI oscillator</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSERDYF</name>
<description>LSE ready interrupt flag
Set by hardware when the LSE clock becomes stable and LSERDYDIE is set.
Cleared by software setting the LSERDYC bit.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No clock ready interrupt caused by the LSE oscillator</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clock ready interrupt caused by the LSE oscillator</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSIRDYF</name>
<description>HSI16 ready interrupt flag
Set by hardware when the HSI16 clock becomes stable and HSIRDYDIE is set in a response to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.
Cleared by software setting the HSIRDYC bit.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No clock ready interrupt caused by the HSI16 oscillator</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clock ready interrupt caused by the HSI16 oscillator</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSERDYF</name>
<description>HSE ready interrupt flag
Set by hardware when the HSE clock becomes stable and HSERDYDIE is set.
Cleared by software setting the HSERDYC bit.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No clock ready interrupt caused by the HSE oscillator</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clock ready interrupt caused by the HSE oscillator</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLRDYF</name>
<description>PLL ready interrupt flag
Set by hardware when the PLL locks and PLLRDYDIE is set.
Cleared by software setting the PLLRDYC bit.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No clock ready interrupt caused by PLL lock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clock ready interrupt caused by PLL lock</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSSF</name>
<description>Clock security system interrupt flag
Set by hardware when a failure is detected in the HSE oscillator.
Cleared by software setting the CSSC bit.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No clock security interrupt caused by HSE clock failure</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clock security interrupt caused by HSE clock failure</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSECSSF</name>
<description>LSE Clock security system interrupt flag
Set by hardware when a failure is detected in the LSE oscillator.
Cleared by software setting the LSECSSC bit.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No clock security interrupt caused by LSE clock failure</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clock security interrupt caused by LSE clock failure</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSI48RDYF</name>
<description>HSI48 ready interrupt flag
Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a response to setting the HSI48ON (refer to Clock recovery RC register (RCC_CRRCR)).
Cleared by software setting the HSI48RDYC bit.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No clock ready interrupt caused by the HSI48 oscillator</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clock ready interrupt caused by the HSI48 oscillator</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_CICR</name>
<displayName>RCC_CICR</displayName>
<description>Clock interrupt clear register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LSIRDYC</name>
<description>LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSIRDYF cleared</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSERDYC</name>
<description>LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSERDYF cleared</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSIRDYC</name>
<description>HSI16 ready interrupt clear
This bit is set software to clear the HSIRDYF flag.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clear HSIRDYF flag</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSERDYC</name>
<description>HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clear HSERDYF flag</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLRDYC</name>
<description>PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clear PLLRDYF flag</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSSC</name>
<description>Clock security system interrupt clear
This bit is set by software to clear the CSSF flag.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clear CSSF flag</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSECSSC</name>
<description>LSE Clock security system interrupt clear
This bit is set by software to clear the LSECSSF flag.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clear LSECSSF flag</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSI48RDYC</name>
<description>HSI48 oscillator ready interrupt clear
This bit is set by software to clear the HSI48RDYF flag.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clear the HSI48RDYC flag</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB1RSTR</name>
<displayName>RCC_AHB1RSTR</displayName>
<description>AHB1 peripheral reset register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMA1RST</name>
<description>DMA1 reset
Set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset DMA1</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMA2RST</name>
<description>DMA2 reset
Set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset DMA2</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAMUX1RST</name>
<description>Set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset DMAMUX1</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CORDICRST</name>
<description>Set and cleared by software</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset CORDIC</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FMACRST</name>
<description>Set and cleared by software</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset FMAC</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLASHRST</name>
<description>Flash memory interface reset
Set and cleared by software. This bit can be activated only when the Flash memory is in power down mode.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset Flash memory interface</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRCRST</name>
<description>CRC reset
Set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset CRC</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB2RSTR</name>
<displayName>RCC_AHB2RSTR</displayName>
<description>AHB2 peripheral reset register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPIOARST</name>
<description>IO port A reset
Set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset IO port A</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOBRST</name>
<description>IO port B reset
Set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset IO port B</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOCRST</name>
<description>IO port C reset
Set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset IO port C</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIODRST</name>
<description>IO port D reset
Set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset IO port D</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOERST</name>
<description>IO port E reset
Set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset IO port E</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOFRST</name>
<description>IO port F reset
Set and cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset IO port F</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOGRST</name>
<description>IO port G reset
Set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset IO port G</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC12RST</name>
<description>ADC12 reset
Set and cleared by software.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset ADC12 interface</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC345RST</name>
<description>ADC345 reset
Set and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset ADC345</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC1RST</name>
<description>DAC1 reset
Set and cleared by software.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset DAC1</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC2RST</name>
<description>DAC2 reset
Set and cleared by software.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset DAC2</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC3RST</name>
<description>DAC3 reset
Set and cleared by software.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset DAC3</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC4RST</name>
<description>DAC4 reset
Set and cleared by software.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset DAC4</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AESRST</name>
<description>AESRST reset
Set and cleared by software.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset AES</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RNGRST</name>
<description>RNG reset
Set and cleared by software.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset RNG</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB3RSTR</name>
<displayName>RCC_AHB3RSTR</displayName>
<description>AHB3 peripheral reset register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FMCRST</name>
<description>Flexible static memory controller reset
Set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset FSMC</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>QSPIRST</name>
<description>QUADSPI reset
Set and cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset QUADSPI</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB1RSTR1</name>
<displayName>RCC_APB1RSTR1</displayName>
<description>APB1 peripheral reset register 1</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TIM2RST</name>
<description>TIM2 timer reset
Set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset TIM2</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM3RST</name>
<description>TIM3 timer reset
Set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset TIM3</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM4RST</name>
<description>TIM3 timer reset
Set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset TIM3</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM5RST</name>
<description>TIM5 timer reset
Set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset TIM5</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM6RST</name>
<description>TIM6 timer reset
Set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset TIM7</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM7RST</name>
<description>TIM7 timer reset
Set and cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset TIM7</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRSRST</name>
<description>CRS reset
Set and cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset CRS</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI2RST</name>
<description>SPI2 reset
Set and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset SPI2</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI3RST</name>
<description>SPI3 reset
Set and cleared by software.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset SPI3</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART2RST</name>
<description>USART2 reset
Set and cleared by software.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset USART2</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART3RST</name>
<description>USART3 reset
Set and cleared by software.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset USART3</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART4RST</name>
<description>UART4 reset
Set and cleared by software.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset UART4</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART5RST</name>
<description>UART5 reset
Set and cleared by software.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset UART5</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C1RST</name>
<description>I2C1 reset
Set and cleared by software.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset I2C1</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C2RST</name>
<description>I2C2 reset
Set and cleared by software.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset I2C2</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USBRST</name>
<description>USB device reset
Set and reset by software.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset USB device</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FDCANRST</name>
<description>FDCAN reset
Set and reset by software.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset the FDCAN</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWRRST</name>
<description>Power interface reset
Set and cleared by software.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset PWR</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C3RST</name>
<description>I2C3 reset
Set and cleared by software.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset I2C3 interface</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTIM1RST</name>
<description>Low Power Timer 1 reset
Set and cleared by software.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset LPTIM1</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB1RSTR2</name>
<displayName>RCC_APB1RSTR2</displayName>
<description>APB1 peripheral reset register 2</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LPUART1RST</name>
<description>Low-power UART 1 reset
Set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset LPUART1</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C4RST</name>
<description>I2C4 reset
Set and cleared by software</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset I2C4</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UCPD1RST</name>
<description>UCPD1 reset
Set and cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset UCPD1</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB2RSTR</name>
<displayName>RCC_APB2RSTR</displayName>
<description>APB2 peripheral reset register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SYSCFGRST</name>
<description>SYSCFG + COMP + OPAMP + VREFBUF reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset SYSCFG + COMP + OPAMP + VREFBUF</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM1RST</name>
<description>TIM1 timer reset
Set and cleared by software.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset TIM1 timer</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI1RST</name>
<description>SPI1 reset
Set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset SPI1</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM8RST</name>
<description>TIM8 timer reset
Set and cleared by software.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset TIM8 timer</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART1RST</name>
<description>USART1 reset
Set and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset USART1</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI4RST</name>
<description>SPI4 reset
Set and cleared by software.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset SPI4</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM15RST</name>
<description>TIM15 timer reset
Set and cleared by software.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset TIM15 timer</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM16RST</name>
<description>TIM16 timer reset
Set and cleared by software.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset TIM16 timer</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM17RST</name>
<description>TIM17 timer reset
Set and cleared by software.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset TIM17 timer</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM20RST</name>
<description>TIM20 reset
Set and cleared by software.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset TIM20</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SAI1RST</name>
<description>Serial audio interface 1 (SAI1) reset
Set and cleared by software.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset SAI1</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HRTIM1RST</name>
<description>HRTIM1 reset
Set and cleared by software.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset HRTIM1</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB1ENR</name>
<displayName>RCC_AHB1ENR</displayName>
<description>AHB1 peripheral clock enable register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<resetValue>0x00000100</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMA1EN</name>
<description>DMA1 clock enable
Set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DMA1 clock disable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DMA1 clock enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMA2EN</name>
<description>DMA2 clock enable
Set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DMA2 clock disable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DMA2 clock enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAMUX1EN</name>
<description>DMAMUX1 clock enable
Set and reset by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DMAMUX1 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DMAMUX1 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CORDICEN</name>
<description>CORDIC clock enable
Set and reset by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>CORDIC clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CORDIC clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FMACEN</name>
<description>FMAC enable
Set and reset by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FMAC clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>FMAC clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLASHEN</name>
<description>Flash memory interface clock enable
Set and cleared by software. This bit can be disabled only when the Flash is in power down mode.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Flash memory interface clock disable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Flash memory interface clock enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRCEN</name>
<description>CRC clock enable
Set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>CRC clock disable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CRC clock enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB2ENR</name>
<displayName>RCC_AHB2ENR</displayName>
<description>AHB2 peripheral clock enable register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPIOAEN</name>
<description>IO port A clock enable
Set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>IO port A clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>IO port A clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOBEN</name>
<description>IO port B clock enable
Set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>IO port B clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>IO port B clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOCEN</name>
<description>IO port C clock enable
Set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>IO port C clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>IO port C clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIODEN</name>
<description>IO port D clock enable
Set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>IO port D clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>IO port D clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOEEN</name>
<description>IO port E clock enable
Set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>IO port E clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>IO port E clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOFEN</name>
<description>IO port F clock enable
Set and cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>IO port F clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>IO port F clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOGEN</name>
<description>IO port G clock enable
Set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>IO port G clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>IO port G clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC12EN</name>
<description>ADC12 clock enable
Set and cleared by software.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>ADC12 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>ADC12 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC345EN</name>
<description>ADC345 clock enable
Set and cleared by software</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>ADC345 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>ADC345 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC1EN</name>
<description>DAC1 clock enable
Set and cleared by software.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DAC1 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DAC1 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC2EN</name>
<description>DAC2 clock enable
Set and cleared by software.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DAC2 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DAC2 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC3EN</name>
<description>DAC3 clock enable
Set and cleared by software.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DAC3 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DAC3 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC4EN</name>
<description>DAC4 clock enable
Set and cleared by software.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DAC4 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DAC4 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AESEN</name>
<description>AES clock enable
Set and cleared by software.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>AES clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>AES clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RNGEN</name>
<description>RNG enable
Set and cleared by software.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>RNG disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>RNG enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB3ENR</name>
<displayName>RCC_AHB3ENR</displayName>
<description>AHB3 peripheral clock enable register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FMCEN</name>
<description>Flexible static memory controller clock enable
Set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FSMC clock disable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>FSMC clock enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>QSPIEN</name>
<description>QUADSPI memory interface clock enable
Set and cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>QUADSPI clock disable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>QUADSPI clock enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB1ENR1</name>
<displayName>RCC_APB1ENR1</displayName>
<description>APB1 peripheral clock enable register 1</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<resetValue>0x00000400</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TIM2EN</name>
<description>TIM2 timer clock enable
Set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM2 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM2 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM3EN</name>
<description>TIM3 timer clock enable
Set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM3 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM3 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM4EN</name>
<description>TIM4 timer clock enable
Set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM4 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM4 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM5EN</name>
<description>TIM5 timer clock enable
Set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM5 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM5 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM6EN</name>
<description>TIM6 timer clock enable
Set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM6 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM6 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM7EN</name>
<description>TIM7 timer clock enable
Set and cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM7 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM7 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRSEN</name>
<description>CRS Recovery System clock enable
Set and cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>CRS clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CRS clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTCAPBEN</name>
<description>RTC APB clock enable
Set and cleared by software</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>RTC APB clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>RTC APB clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WWDGEN</name>
<description>Window watchdog clock enable
Set by software to enable the window watchdog clock. Reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Window watchdog clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Window watchdog clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI2EN</name>
<description>SPI2 clock enable
Set and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI2 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI2 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI3EN</name>
<description>SPI3 clock enable
Set and cleared by software.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI3 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI3 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART2EN</name>
<description>USART2 clock enable
Set and cleared by software.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USART2 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USART2 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART3EN</name>
<description>USART3 clock enable
Set and cleared by software.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USART3 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USART3 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART4EN</name>
<description>UART4 clock enable
Set and cleared by software.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>UART4 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>UART4 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART5EN</name>
<description>UART5 clock enable
Set and cleared by software.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>UART5 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>UART5 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C1EN</name>
<description>I2C1 clock enable
Set and cleared by software.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>I2C1 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>I2C1 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C2EN</name>
<description>I2C2 clock enable
Set and cleared by software.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>I2C2 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>I2C2 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USBEN</name>
<description>USB device clock enable
Set and cleared by software.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USB device clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USB device clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FDCANEN</name>
<description>FDCAN clock enable
Set and cleared by software.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FDCAN clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>FDCAN clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWREN</name>
<description>Power interface clock enable
Set and cleared by software.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Power interface clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Power interface clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C3EN</name>
<description>I2C3 clock enable
Set and cleared by software.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>I2C3 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>I2C3 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTIM1EN</name>
<description>Low power timer 1 clock enable
Set and cleared by software.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LPTIM1 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LPTIM1 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB1ENR2</name>
<displayName>RCC_APB1ENR2</displayName>
<description>APB1 peripheral clock enable register 2</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LPUART1EN</name>
<description>Low power UART 1 clock enable
Set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LPUART1 clock disable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LPUART1 clock enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C4EN</name>
<description>I2C4 clock enable
Set and cleared by software</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>I2C4 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>I2C4 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UCPD1EN</name>
<description>UCPD1 clock enable
Set and cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>UCPD1 clock disable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>UCPD1 clock enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB2ENR</name>
<displayName>RCC_APB2ENR</displayName>
<description>APB2 peripheral clock enable register</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SYSCFGEN</name>
<description>SYSCFG + COMP + VREFBUF + OPAMP clock enable
Set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SYSCFG + COMP + VREFBUF + OPAMP clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SYSCFG + COMP + VREFBUF + OPAMP clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM1EN</name>
<description>TIM1 timer clock enable
Set and cleared by software.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM1 timer clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM1P timer clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI1EN</name>
<description>SPI1 clock enable
Set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI1 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI1 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM8EN</name>
<description>TIM8 timer clock enable
Set and cleared by software.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM8 timer clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM8 timer clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART1EN</name>
<description>USART1clock enable
Set and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USART1clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USART1clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI4EN</name>
<description>SPI4 clock enable
Set and cleared by software.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI4 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI4 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM15EN</name>
<description>TIM15 timer clock enable
Set and cleared by software.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM15 timer clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM15 timer clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM16EN</name>
<description>TIM16 timer clock enable
Set and cleared by software.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM16 timer clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM16 timer clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM17EN</name>
<description>TIM17 timer clock enable
Set and cleared by software.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM17 timer clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM17 timer clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM20EN</name>
<description>TIM20 timer clock enable
Set and cleared by software.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM20 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM20 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SAI1EN</name>
<description>SAI1 clock enable
Set and cleared by software.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SAI1 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SAI1 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HRTIM1EN</name>
<description>HRTIM1 clock enable
Set and cleared by software.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HRTIM1 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HRTIM1 clock enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB1SMENR</name>
<displayName>RCC_AHB1SMENR</displayName>
<description>AHB1 peripheral clocks enable in Sleep and Stop modes register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<resetValue>0x0000130F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMA1SMEN</name>
<description>DMA1 clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DMA1 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DMA1 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMA2SMEN</name>
<description>DMA2 clocks enable during Sleep and Stop modes
Set and cleared by software during Sleep mode.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DMA2 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DMA2 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAMUX1SMEN</name>
<description>DMAMUX1 clock enable during Sleep and Stop modes.
Set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DMAMUX1 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DMAMUX1 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CORDICSMEN</name>
<description>CORDICSM clock enable.
Set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>CORDICSM clocks disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CORDICSM clocks enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FMACSMEN</name>
<description>FMACSM clock enable.
Set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FMACSM clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>FMACSM clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLASHSMEN</name>
<description>Flash memory interface clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Flash memory interface clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Flash memory interface clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRAM1SMEN</name>
<description>SRAM1 interface clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SRAM1 interface clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SRAM1 interface clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRCSMEN</name>
<description>CRC clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>CRC clocks disabled by the clock gating during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CRC clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB2SMENR</name>
<displayName>RCC_AHB2SMENR</displayName>
<description>AHB2 peripheral clocks enable in Sleep and Stop modes register</description>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<resetValue>0x050F667F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPIOASMEN</name>
<description>IO port A clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>IO port A clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>IO port A clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOBSMEN</name>
<description>IO port B clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>IO port B clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>IO port B clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOCSMEN</name>
<description>IO port C clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>IO port C clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>IO port C clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIODSMEN</name>
<description>IO port D clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>IO port D clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>IO port D clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOESMEN</name>
<description>IO port E clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>IO port E clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>IO port E clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOFSMEN</name>
<description>IO port F clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>IO port F clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>IO port F clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOGSMEN</name>
<description>IO port G clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>IO port G clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>IO port G clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCMSRAMSMEN</name>
<description>CCM SRAM interface clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>CCM SRAM interface clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CCM SRAM interface clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRAM2SMEN</name>
<description>SRAM2 interface clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SRAM2 interface clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SRAM2 interface clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC12SMEN</name>
<description>ADC12 clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>ADC12 clocks disabled by the clock gating during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>ADC12 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC345SMEN</name>
<description>ADC345 clock enable
Set and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>ADC345 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>ADC345 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC1SMEN</name>
<description>DAC1 clock enable
Set and cleared by software.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DAC1 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DAC1 clock enabled during sleep and stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC2SMEN</name>
<description>DAC2 clock enable
Set and cleared by software.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DAC2 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DAC2 clock enabled during sleep and stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC3SMEN</name>
<description>DAC3 clock enable
Set and cleared by software.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DAC3 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DAC3 clock enabled during sleep and stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC4SMEN</name>
<description>DAC4 clock enable
Set and cleared by software.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DAC4 clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DAC4 clock enabled during sleep and stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AESSMEN</name>
<description>AESM clocks enable
Set and cleared by software.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>AESM clocks disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>AESM clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RNGEN</name>
<description>RNG enable
Set and cleared by software.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>RNG disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>RNG enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB3SMENR</name>
<displayName>RCC_AHB3SMENR</displayName>
<description>AHB3 peripheral clocks enable in Sleep and Stop modes register</description>
<addressOffset>0x70</addressOffset>
<size>0x20</size>
<resetValue>0x00000101</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FMCSMEN</name>
<description>Flexible static memory controller clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FSMC clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>FSMC clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>QSPISMEN</name>
<description>QUADSPI memory interface clock enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>QUADSPI clock disabled by the clock gating during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>QUADSPI clock enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB1SMENR1</name>
<displayName>RCC_APB1SMENR1</displayName>
<description>APB1 peripheral clocks enable in Sleep and Stop modes register 1</description>
<addressOffset>0x78</addressOffset>
<size>0x20</size>
<resetValue>0xD2FECD3F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TIM2SMEN</name>
<description>TIM2 timer clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM2 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM2 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM3SMEN</name>
<description>TIM3 timer clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM3 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM3 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM4SMEN</name>
<description>TIM4 timer clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM4 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM4 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM5SMEN</name>
<description>TIM5 timer clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM5 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM5 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM6SMEN</name>
<description>TIM6 timer clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM6 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM6 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM7SMEN</name>
<description>TIM7 timer clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM7 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM7 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRSSMEN</name>
<description>CRS timer clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>CRS clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CRS clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTCAPBSMEN</name>
<description>RTC APB clock enable during Sleep and Stop modes
Set and cleared by software</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>RTC APB clock disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>RTC APB clock enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WWDGSMEN</name>
<description>Window watchdog clocks enable during Sleep and Stop modes
Set and cleared by software. This bit is forced to ‘1’ by hardware when the hardware WWDG option is activated.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Window watchdog clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Window watchdog clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI2SMEN</name>
<description>SPI2 clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI2 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI2 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI3SMEN</name>
<description>SPI3 clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI3 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI3 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART2SMEN</name>
<description>USART2 clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USART2 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USART2 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART3SMEN</name>
<description>USART3 clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USART3 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USART3 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART4SMEN</name>
<description>UART4 clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>UART4 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>UART4 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART5SMEN</name>
<description>UART5 clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>UART5 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>UART5 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C1SMEN</name>
<description>I2C1 clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>I2C1 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>I2C1 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C2SMEN</name>
<description>I2C2 clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>I2C2 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>I2C2 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USBSMEN</name>
<description>USB device clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USB device clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USB device clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FDCANSMEN</name>
<description>FDCAN clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FDCAN clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>FDCAN clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWRSMEN</name>
<description>Power interface clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Power interface clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Power interface clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C3SMEN</name>
<description>I2C3 clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>I2C3 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>I2C3 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTIM1SMEN</name>
<description>Low power timer 1 clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LPTIM1 clocks disabled by the clock gating during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LPTIM1 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB1SMENR2</name>
<displayName>RCC_APB1SMENR2</displayName>
<description>APB1 peripheral clocks enable in Sleep and Stop modes register 2</description>
<addressOffset>0x7C</addressOffset>
<size>0x20</size>
<resetValue>0x00000103</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LPUART1SMEN</name>
<description>Low power UART 1 clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LPUART1 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LPUART1 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C4SMEN</name>
<description>I2C4 clocks enable during Sleep and Stop modes
Set and cleared by software</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>I2C4 clocks disabled by the clock gating during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>I2C4 clock enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UCPD1SMEN</name>
<description>UCPD1 clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>UCPD1 clocks disabled by the clock gating during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>UCPD1 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB2SMENR</name>
<displayName>RCC_APB2SMENR</displayName>
<description>APB2 peripheral clocks enable in Sleep and Stop modes register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<resetValue>0x0437F801</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SYSCFGSMEN</name>
<description>SYSCFG + COMP + VREFBUF + OPAMP clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SYSCFG + COMP + VREFBUF + OPAMP clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SYSCFG + COMP + VREFBUF + OPAMP clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM1SMEN</name>
<description>TIM1 timer clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM1 timer clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM1P timer clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI1SMEN</name>
<description>SPI1 clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI1 clocks disabled by the clock gating during&lt;sup&gt;(1)&lt;/sup&gt; Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI1 clocks enabled by the clock gating during&lt;sup&gt;(1)&lt;/sup&gt; Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM8SMEN</name>
<description>TIM8 timer clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM8 timer clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM8 timer clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART1SMEN</name>
<description>USART1clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USART1clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USART1clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI4SMEN</name>
<description>SPI4 timer clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI4 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI4 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop mode</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM15SMEN</name>
<description>TIM15 timer clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM15 timer clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM15 timer clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop mode</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM16SMEN</name>
<description>TIM16 timer clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM16 timer clocks disabled by the clock gating during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM16 timer clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM17SMEN</name>
<description>TIM17 timer clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM17 timer clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM17 timer clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM20SMEN</name>
<description>TIM20 timer clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM20 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM20 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SAI1SMEN</name>
<description>SAI1 clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SAI1 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SAI1 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HRTIM1SMEN</name>
<description>HRTIM1 timer clocks enable during Sleep and Stop modes
Set and cleared by software.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HRTIM1 clocks disabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HRTIM1 clocks enabled by the clock gating&lt;sup&gt;(1)&lt;/sup&gt; during Sleep and Stop modes</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_CCIPR</name>
<displayName>RCC_CCIPR</displayName>
<description>Peripherals independent clock configuration register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>USART1SEL</name>
<description>USART1 clock source selection
This bit is set and cleared by software to select the USART1 clock source.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PCLK selected as USART1 clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>System clock (SYSCLK) selected as USART1 clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>HSI16 clock selected as USART1 clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>LSE clock selected as USART1 clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART2SEL</name>
<description>USART2 clock source selection
This bit is set and cleared by software to select the USART2 clock source.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PCLK selected as USART2 clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>System clock (SYSCLK) selected as USART2 clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>HSI16 clock selected as USART2 clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>LSE clock selected as USART2 clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART3SEL</name>
<description>USART3 clock source selection
This bit is set and cleared by software to select the USART3 clock source.</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PCLK selected as USART3 clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>System clock (SYSCLK) selected as USART3 clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>HSI16 clock selected as USART3 clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>LSE clock selected as USART3 clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART4SEL</name>
<description>UART4 clock source selection
This bit is set and cleared by software to select the UART4 clock source.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PCLK selected as UART4 clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>System clock (SYSCLK) selected as UART4 clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>HSI16 clock selected as UART4 clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>LSE clock selected as UART4 clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART5SEL</name>
<description>UART5 clock source selection
These bits are set and cleared by software to select the UART5 clock source.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PCLK selected as UART5 clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>System clock (SYSCLK) selected as UART5 clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>HSI16 clock selected as UART5 clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>LSE clock selected as UART5 clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPUART1SEL</name>
<description>LPUART1 clock source selection
These bits are set and cleared by software to select the LPUART1 clock source.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PCLK selected as LPUART1 clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>System clock (SYSCLK) selected as LPUART1 clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>HSI16 clock selected as LPUART1 clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>LSE clock selected as LPUART1 clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C1SEL</name>
<description>I2C1 clock source selection
These bits are set and cleared by software to select the I2C1 clock source.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PCLK selected as I2C1 clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>System clock (SYSCLK) selected as I2C1 clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>HSI16 clock selected as I2C1 clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C2SEL</name>
<description>I2C2 clock source selection
These bits are set and cleared by software to select the I2C2 clock source.</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PCLK selected as I2C2 clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>System clock (SYSCLK) selected as I2C2 clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>HSI16 clock selected as I2C2 clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C3SEL</name>
<description>I2C3 clock source selection
These bits are set and cleared by software to select the I2C3 clock source.</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PCLK selected as I2C3 clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>System clock (SYSCLK) selected as I2C3 clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>HSI16 clock selected as I2C3 clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTIM1SEL</name>
<description>Low power timer 1 clock source selection
These bits are set and cleared by software to select the LPTIM1 clock source.</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PCLK selected as LPTIM1 clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSI clock selected as LPTIM1 clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>HSI16 clock selected as LPTIM1 clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>LSE clock selected as LPTIM1 clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SAI1SEL</name>
<description>clock source selection
These bits are set and cleared by software to select the SAI clock source.</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>System clock selected as SAI clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL “Q” clock selected as SAI clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Clock provided on I2S_CKIN pin selected as SAI clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>HSI16 clock selected as SAI clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2S23SEL</name>
<description>clock source selection
These bits are set and cleared by software to select the I2S23 clock source.</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>System clock selected as I2S23 clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL “Q” clock selected as I2S23 clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Clock provided on I2S_CKIN pin is selected as I2S23 clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>HSI16 clock selected as I2S23 clock.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FDCANSEL</name>
<description>None</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLK48SEL</name>
<description>48 MHz clock source selection
These bits are set and cleared by software to select the 48 MHz clock source used by USB device FS and RNG.</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSI48 clock selected as 48 MHz clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reserved</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>PLL “Q” clock (PLL48M1CLK) selected as 48 MHz clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Reserved, must be kept at reset value</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC12SEL</name>
<description>ADC1/2 clock source selection
These bits are set and cleared by software to select the clock source used by the ADC interface.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No clock selected</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL “P” clock selected as ADC1/2 clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>System clock selected as ADC1/2 clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC345SEL</name>
<description>ADC3/4/5 clock source selection
These bits are set and cleared by software to select the clock source used by the ADC345 interface.</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No clock selected</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL “P” clock selected as ADC345 clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>System clock selected as ADC3/4/5 clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Reserved.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_BDCR</name>
<displayName>RCC_BDCR</displayName>
<description>RTC domain control register</description>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LSEON</name>
<description>LSE oscillator enable
Set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LSE oscillator OFF</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSE oscillator ON</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSERDY</name>
<description>LSE oscillator ready
Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LSE oscillator not ready</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSE oscillator ready</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSEBYP</name>
<description>LSE oscillator bypass
Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0).</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LSE oscillator not bypassed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSE oscillator bypassed</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSEDRV</name>
<description>LSE oscillator drive capability
Set by software to modulate the LSE oscillator’s drive capability.
The oscillator is in Xtal mode when it is not in bypass mode.</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>‘Xtal mode’ lower driving capability</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>‘Xtal mode’ medium low driving capability</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>‘Xtal mode’ medium high driving capability</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>‘Xtal mode’ higher driving capability</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSECSSON</name>
<description>CSS on LSE enable
Set by software to enable the Clock Security System on LSE (32 kHz oscillator).
LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected.
Once enabled this bit cannot be disabled, except after a LSE failure detection (LSECSSD
=1). In that case the software MUST disable the LSECSSON bit.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>CSS on LSE (32 kHz external oscillator) OFF</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CSS on LSE (32 kHz external oscillator) ON</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSECSSD</name>
<description>CSS on LSE failure Detection
Set by hardware to indicate when a failure has been detected by the Clock Security System
on the external 32 kHz oscillator (LSE).</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No failure detected on LSE (32 kHz oscillator)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Failure detected on LSE (32 kHz oscillator)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTCSEL</name>
<description>RTC clock source selection
Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSE oscillator clock used as RTC clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>LSI oscillator clock used as RTC clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>HSE oscillator clock divided by 32 used as RTC clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTCEN</name>
<description>RTC clock enable
Set and cleared by software.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>RTC clock disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>RTC clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BDRST</name>
<description>RTC domain software reset
Set and cleared by software.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Reset not activated</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset the entire RTC domain</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSCOEN</name>
<description>Low speed clock output enable
Set and cleared by software.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Low speed clock output (LSCO) disable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Low speed clock output (LSCO) enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSCOSEL</name>
<description>Low speed clock output selection
Set and cleared by software.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LSI clock selected</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSE clock selected</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_CSR</name>
<displayName>RCC_CSR</displayName>
<description>Control/status register</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<resetValue>0x0C000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LSION</name>
<description>LSI oscillator enable
Set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LSI oscillator OFF</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSI oscillator ON</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSIRDY</name>
<description>LSI oscillator ready
Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LSI oscillator not ready</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSI oscillator ready</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RMVF</name>
<description>Remove reset flag
Set by software to clear the reset flags.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clear the reset flags</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OBLRSTF</name>
<description>Option byte loader reset flag
Set by hardware when a reset from the Option Byte loading occurs.
Cleared by writing to the RMVF bit.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No reset from Option Byte loading occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset from Option Byte loading occurred</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PINRSTF</name>
<description>Pin reset flag
Set by hardware when a reset from the NRST pin occurs.
Cleared by writing to the RMVF bit.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No reset from NRST pin occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Reset from NRST pin occurred</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BORRSTF</name>
<description>BOR flag
Set by hardware when a BOR occurs.
Cleared by writing to the RMVF bit.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No BOR occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>BOR occurred</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SFTRSTF</name>
<description>Software reset flag
Set by hardware when a software reset occurs.
Cleared by writing to the RMVF bit.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No software reset occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Software reset occurred</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IWDGRSTF</name>
<description>Independent window watchdog reset flag
Set by hardware when an independent watchdog reset domain occurs.
Cleared by writing to the RMVF bit.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No independent watchdog reset occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Independent watchdog reset occurred</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WWDGRSTF</name>
<description>Window watchdog reset flag
Set by hardware when a window watchdog reset occurs.
Cleared by writing to the RMVF bit.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No window watchdog reset occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Window watchdog reset occurred</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPWRRSTF</name>
<description>Low-power reset flag
Set by hardware when a reset occurs due to illegal Stop, Standby or Shutdown mode entry.
Cleared by writing to the RMVF bit.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No illegal mode reset occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Illegal mode reset occurred</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_CRRCR</name>
<displayName>RCC_CRRCR</displayName>
<description>Clock recovery RC register</description>
<addressOffset>0x98</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HSI48ON</name>
<description>HSI48 clock enable
Set and cleared by software.
Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSI48 oscillator OFF</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSI48 oscillator ON</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSI48RDY</name>
<description>HSI48 clock ready flag
Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSI48 oscillator not ready</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSI48 oscillator ready</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSI48CAL</name>
<description>HSI48 clock calibration
These bits are initialized at startup with the factory-programmed HSI48 calibration trim value.
They are ready only.</description>
<bitOffset>7</bitOffset>
<bitWidth>9</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RCC_CCIPR2</name>
<displayName>RCC_CCIPR2</displayName>
<description>Peripherals independent clock configuration register</description>
<addressOffset>0x9C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>I2C4SEL</name>
<description>I2C4 clock source selection
These bits are set and cleared by software to select the I2C4 clock source.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PCLK selected as I2C4 clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>System clock (SYSCLK) selected as I2C4 clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>HSI16 clock selected as I2C4 clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>QSPISEL</name>
<description>QUADSPI clock source selection
Set and reset by software.</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>system clock selected as QUADSPI kernel clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSI16 clock selected as QUADSPI kernel clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>PLL “Q” clock selected as QUADSPI kernel clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PWR</name>
<description>Power control</description>
<groupName>PWR</groupName>
<baseAddress>0x40007000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PWR_CR1</name>
<displayName>PWR_CR1</displayName>
<description>Power control register 1</description>
<addressOffset>0x00</addressOffset>
<size>0x20</size>
<resetValue>0x00000200</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LPMS</name>
<description>Low-power mode selection
These bits select the low-power mode entered when CPU enters the deepsleep mode.
1xx: Shutdown mode
Note: In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Stop 0 mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Stop 1 mode</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Reserved</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Standby mode</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FPD_STOP</name>
<description>FPD_STOP</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DBP</name>
<description>Disable backup domain write protection
In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Access to RTC and Backup registers disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Access to RTC and Backup registers enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VOS</name>
<description>Voltage scaling range selection</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Cannot be written (forbidden by hardware)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Range 1</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Range 2</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Cannot be written (forbidden by hardware)</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPR</name>
<description>Low-power run
When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR).</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_CR2</name>
<displayName>PWR_CR2</displayName>
<description>Power control register 2</description>
<addressOffset>0x04</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PVDE</name>
<description>Programmable voltage detector enable
Note: This bit is write-protected when the PVDL bit is set in the SYSCFG_CFGR2 register. The protection can be reset only by a system reset.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Programmable voltage detector disable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Programmable voltage detector enable.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PVDLS</name>
<description>Programmable voltage detector level selection.
These bits select the PVD falling threshold:
Note: These bits are write-protected when the PVDL bit is set in the SYSCFG_CFGR2 register. The protection can be reset only by a system reset.</description>
<bitOffset>1</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>V&lt;sub&gt;PVD0&lt;/sub&gt; PVD threshold 0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>V&lt;sub&gt;PVD1&lt;/sub&gt; PVD threshold 1</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>V&lt;sub&gt;PVD2&lt;/sub&gt; PVD threshold 2</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>V&lt;sub&gt;PVD3&lt;/sub&gt; PVD threshold 3</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>V&lt;sub&gt;PVD4&lt;/sub&gt; PVD threshold 4</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x5</name>
<description>V&lt;sub&gt;PVD5&lt;/sub&gt; PVD threshold 5</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x6</name>
<description>V&lt;sub&gt;PVD6&lt;/sub&gt; PVD threshold 6</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7</name>
<description>External input analog voltage PVD_IN (compared internally to V&lt;sub&gt;REFINT&lt;/sub&gt;)</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PVMEN1</name>
<description>Peripheral voltage monitoring 3 enable: V&lt;sub&gt;DDA&lt;/sub&gt; vs. ADC/COMP min voltage 1.62V</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PVM1 (V&lt;sub&gt;DDA&lt;/sub&gt; monitoring vs. 1.62V threshold) disable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PVM1 (V&lt;sub&gt;DDA&lt;/sub&gt; monitoring vs. 1.62V threshold) enable.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PVMEN2</name>
<description>Peripheral voltage monitoring 4 enable: V&lt;sub&gt;DDA&lt;/sub&gt; vs. DAC 1MSPS /DAC 15MSPS min voltage.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PVM2 (V&lt;sub&gt;DDA&lt;/sub&gt; monitoring vs. 1.8 V threshold) disable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PVM2 (V&lt;sub&gt;DDA&lt;/sub&gt; monitoring vs. 1.8 V threshold) enable.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PWR_CR3</name>
<displayName>PWR_CR3</displayName>
<description>Power control register 3</description>
<addressOffset>0x08</addressOffset>
<size>0x20</size>
<resetValue>0x00008000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EWUP1</name>
<description>Enable Wakeup pin WKUP1
When this bit is set, the external wakeup pin WKUP1 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit in the PWR_CR4 register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EWUP2</name>
<description>Enable Wakeup pin WKUP2
When this bit is set, the external wakeup pin WKUP2 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit in the PWR_CR4 register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EWUP3</name>
<description>Enable Wakeup pin WKUP3
When this bit is set, the external wakeup pin WKUP3 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit in the PWR_CR4 register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EWUP4</name>
<description>Enable Wakeup pin WKUP4
When this bit is set, the external wakeup pin WKUP4 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EWUP5</name>
<description>Enable Wakeup pin WKUP5
When this bit is set, the external wakeup pin WKUP5 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP5 bit in the PWR_CR4 register.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RRS</name>
<description>SRAM2 retention in Standby mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SRAM2 is powered off in Standby mode (SRAM2 content is lost).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 content is kept).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>APC</name>
<description>Apply pull-up and pull-down configuration
When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx
and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and
PWR_PDCRx registers are not applied to the I/Os.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UCPD1_STDBY</name>
<description>UCPD1_STDBY USB Type-C and Power Delivery standby mode.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Write ‘0’ immediately after standby exit when using UCPD1, (and before writing any UCPD1 registers).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Write ‘1’ just before entering standby when using UCPD1.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UCPD1_DBDIS</name>
<description>USB Type-C and Power Delivery Dead Battery disable.
After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have
a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either
to stop this pull-down or to hand over control to the UCPD1 (which should therefore be
initialized before doing the disable).</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Enable USB Type-C dead battery pull-down behavior on UCPD1_CC1 and UCPD1_CC2 pins.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Disable USB Type-C dead battery pull-down behavior on UCPD1_CC1 and UCPD1_CC2 pins.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EIWUL</name>
<description>Enable internal wakeup line</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Internal wakeup line disable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Internal wakeup line enable.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PWR_CR4</name>
<displayName>PWR_CR4</displayName>
<description>Power control register 4</description>
<addressOffset>0x0C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WP1</name>
<description>Wakeup pin WKUP1 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP1</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Detection on high level (rising edge)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Detection on low level (falling edge)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WP2</name>
<description>Wakeup pin WKUP2 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Detection on high level (rising edge)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Detection on low level (falling edge)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WP3</name>
<description>Wakeup pin WKUP3 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP3</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Detection on high level (rising edge)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Detection on low level (falling edge)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WP4</name>
<description>Wakeup pin WKUP4 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP4</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Detection on high level (rising edge)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Detection on low level (falling edge)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WP5</name>
<description>Wakeup pin WKUP5 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP5</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Detection on high level (rising edge)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Detection on low level (falling edge)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VBE</name>
<description>V&lt;sub&gt;BAT&lt;/sub&gt; battery charging enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>V&lt;sub&gt;BAT&lt;/sub&gt; battery charging disable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>V&lt;sub&gt;BAT&lt;/sub&gt; battery charging enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VBRS</name>
<description>V&lt;sub&gt;BAT&lt;/sub&gt; battery charging resistor selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Charge V&lt;sub&gt;BAT&lt;/sub&gt; through a 5 kOhms resistor</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Charge V&lt;sub&gt;BAT&lt;/sub&gt; through a 1.5 kOhms resistor</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PWR_SR1</name>
<displayName>PWR_SR1</displayName>
<description>Power status register 1</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WUF1</name>
<description>Wakeup flag 1
This bit is set when a wakeup event is detected on wakeup pin, WKUP1. It is cleared by writing ‘1’ in the CWUF1 bit of the PWR_SCR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>WUF2</name>
<description>Wakeup flag 2
This bit is set when a wakeup event is detected on wakeup pin, WKUP2. It is cleared by writing ‘1’ in the CWUF2 bit of the PWR_SCR register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>WUF3</name>
<description>Wakeup flag 3
This bit is set when a wakeup event is detected on wakeup pin, WKUP3. It is cleared by writing ‘1’ in the CWUF3 bit of the PWR_SCR register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>WUF4</name>
<description>Wakeup flag 4
This bit is set when a wakeup event is detected on wakeup pin,WKUP4. It is cleared by writing ‘1’ in the CWUF4 bit of the PWR_SCR register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>WUF5</name>
<description>Wakeup flag 5
This bit is set when a wakeup event is detected on wakeup pin, WKUP5. It is cleared by writing ‘1’ in the CWUF5 bit of the PWR_SCR register.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SBF</name>
<description>Standby flag
This bit is set by hardware when the device enters the Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The device did not enter the Standby mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The device entered the Standby mode</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUFI</name>
<description>Wakeup flag internal
This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PWR_SR2</name>
<displayName>PWR_SR2</displayName>
<description>Power status register 2</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>REGLPS</name>
<description>Low-power regulator started
This bit provides the information whether the low-power regulator is ready after a power-on
reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wakeup from Standby mode time may be increased.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The low-power regulator is not ready</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The low-power regulator is ready</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REGLPF</name>
<description>Low-power regulator flag
This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits
the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency.
This bit is cleared by hardware when the regulator is ready.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The regulator is ready in main mode (MR)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The regulator is in low-power mode (LPR)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VOSF</name>
<description>Voltage scaling flag
A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The regulator is ready in the selected voltage range</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The regulator output voltage is changing to the required voltage level</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PVDO</name>
<description>Programmable voltage detector output</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>V&lt;sub&gt;DD&lt;/sub&gt; is above the selected PVD threshold</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>V&lt;sub&gt;DD&lt;/sub&gt; is below the selected PVD threshold</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PVMO1</name>
<description>Peripheral voltage monitoring output: V&lt;sub&gt;DDA&lt;/sub&gt; vs. 1.62 V
Note: PVMO1 is cleared when PVM1 is disabled (PVME = 0). After enabling PVM1, the PVM1 output is valid after the PVM1 wakeup time.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>V&lt;sub&gt;DDA&lt;/sub&gt; voltage is above PVM1 threshold (around 1.62 V).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>V&lt;sub&gt;DDA&lt;/sub&gt; voltage is below PVM1 threshold (around 1.62 V).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PVMO2</name>
<description>Peripheral voltage monitoring output: V&lt;sub&gt;DDA&lt;/sub&gt; vs. 1.8 V
Note: PVMO2 is cleared when PVM2 is disabled (PVME = 0). After enabling PVM2, the PVM2 output is valid after the PVM2 wakeup time.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>V&lt;sub&gt;DDA&lt;/sub&gt; voltage is above PVM2 threshold (around 1.8 V).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>V&lt;sub&gt;DDA&lt;/sub&gt; voltage is below PVM2 threshold (around 1.8 V).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PWR_SCR</name>
<displayName>PWR_SCR</displayName>
<description>Power status clear register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CWUF1</name>
<description>Clear wakeup flag 1
Setting this bit clears the WUF1 flag in the PWR_SR1 register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CWUF2</name>
<description>Clear wakeup flag 2
Setting this bit clears the WUF2 flag in the PWR_SR1 register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CWUF3</name>
<description>Clear wakeup flag 3
Setting this bit clears the WUF3 flag in the PWR_SR1 register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CWUF4</name>
<description>Clear wakeup flag 4
Setting this bit clears the WUF4 flag in the PWR_SR1 register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CWUF5</name>
<description>Clear wakeup flag 5
Setting this bit clears the WUF5 flag in the PWR_SR1 register.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CSBF</name>
<description>Clear standby flag
Setting this bit clears the SBF flag in the PWR_SR1 register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>PWR_PUCRA</name>
<displayName>PWR_PUCRA</displayName>
<description>Power Port A pull-up control register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PU0</name>
<description>Port A pull-up bit y (y=0..13)
When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU1</name>
<description>Port A pull-up bit y (y=0..13)
When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU2</name>
<description>Port A pull-up bit y (y=0..13)
When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU3</name>
<description>Port A pull-up bit y (y=0..13)
When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU4</name>
<description>Port A pull-up bit y (y=0..13)
When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU5</name>
<description>Port A pull-up bit y (y=0..13)
When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU6</name>
<description>Port A pull-up bit y (y=0..13)
When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU7</name>
<description>Port A pull-up bit y (y=0..13)
When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU8</name>
<description>Port A pull-up bit y (y=0..13)
When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU9</name>
<description>Port A pull-up bit y (y=0..13)
When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU10</name>
<description>Port A pull-up bit y (y=0..13)
When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU11</name>
<description>Port A pull-up bit y (y=0..13)
When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU12</name>
<description>Port A pull-up bit y (y=0..13)
When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU13</name>
<description>Port A pull-up bit y (y=0..13)
When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU15</name>
<description>Port A pull-up bit 15
When set, this bit activates the pull-up on PA[15] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PD15 bit is also set.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_PDCRA</name>
<displayName>PWR_PDCRA</displayName>
<description>Power Port A pull-down control register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PD0</name>
<description>Port A pull-down bit y (y=0..12)
When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD1</name>
<description>Port A pull-down bit y (y=0..12)
When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD2</name>
<description>Port A pull-down bit y (y=0..12)
When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD3</name>
<description>Port A pull-down bit y (y=0..12)
When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD4</name>
<description>Port A pull-down bit y (y=0..12)
When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD5</name>
<description>Port A pull-down bit y (y=0..12)
When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD6</name>
<description>Port A pull-down bit y (y=0..12)
When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD7</name>
<description>Port A pull-down bit y (y=0..12)
When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD8</name>
<description>Port A pull-down bit y (y=0..12)
When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD9</name>
<description>Port A pull-down bit y (y=0..12)
When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD10</name>
<description>Port A pull-down bit y (y=0..12)
When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD11</name>
<description>Port A pull-down bit y (y=0..12)
When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD12</name>
<description>Port A pull-down bit y (y=0..12)
When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD14</name>
<description>Port A pull-down bit 14
When set, this bit activates the pull-down on PA[14] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_PUCRB</name>
<displayName>PWR_PUCRB</displayName>
<description>Power Port B pull-up control register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PU0</name>
<description>Port B pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU1</name>
<description>Port B pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU2</name>
<description>Port B pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU3</name>
<description>Port B pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU4</name>
<description>Port B pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU5</name>
<description>Port B pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU6</name>
<description>Port B pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU7</name>
<description>Port B pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU8</name>
<description>Port B pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU9</name>
<description>Port B pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU10</name>
<description>Port B pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU11</name>
<description>Port B pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU12</name>
<description>Port B pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU13</name>
<description>Port B pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU14</name>
<description>Port B pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU15</name>
<description>Port B pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_PDCRB</name>
<displayName>PWR_PDCRB</displayName>
<description>Power Port B pull-down control register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PD0</name>
<description>Port B pull-down bit y (y=0..3)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD1</name>
<description>Port B pull-down bit y (y=0..3)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD2</name>
<description>Port B pull-down bit y (y=0..3)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD3</name>
<description>Port B pull-down bit y (y=0..3)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD5</name>
<description>Port B pull-down bit y (y=5..15)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD6</name>
<description>Port B pull-down bit y (y=5..15)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD7</name>
<description>Port B pull-down bit y (y=5..15)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD8</name>
<description>Port B pull-down bit y (y=5..15)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD9</name>
<description>Port B pull-down bit y (y=5..15)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD10</name>
<description>Port B pull-down bit y (y=5..15)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD11</name>
<description>Port B pull-down bit y (y=5..15)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD12</name>
<description>Port B pull-down bit y (y=5..15)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD13</name>
<description>Port B pull-down bit y (y=5..15)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD14</name>
<description>Port B pull-down bit y (y=5..15)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD15</name>
<description>Port B pull-down bit y (y=5..15)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_PUCRC</name>
<displayName>PWR_PUCRC</displayName>
<description>Power Port C pull-up control register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PU0</name>
<description>Port C pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU1</name>
<description>Port C pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU2</name>
<description>Port C pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU3</name>
<description>Port C pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU4</name>
<description>Port C pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU5</name>
<description>Port C pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU6</name>
<description>Port C pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU7</name>
<description>Port C pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU8</name>
<description>Port C pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU9</name>
<description>Port C pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU10</name>
<description>Port C pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU11</name>
<description>Port C pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU12</name>
<description>Port C pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU13</name>
<description>Port C pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU14</name>
<description>Port C pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU15</name>
<description>Port C pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_PDCRC</name>
<displayName>PWR_PDCRC</displayName>
<description>Power Port C pull-down control register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PD0</name>
<description>Port C pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD1</name>
<description>Port C pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD2</name>
<description>Port C pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD3</name>
<description>Port C pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD4</name>
<description>Port C pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD5</name>
<description>Port C pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD6</name>
<description>Port C pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD7</name>
<description>Port C pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD8</name>
<description>Port C pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD9</name>
<description>Port C pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD10</name>
<description>Port C pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD11</name>
<description>Port C pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD12</name>
<description>Port C pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD13</name>
<description>Port C pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD14</name>
<description>Port C pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD15</name>
<description>Port C pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_PUCRD</name>
<displayName>PWR_PUCRD</displayName>
<description>Power Port D pull-up control register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PU0</name>
<description>Port D pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU1</name>
<description>Port D pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU2</name>
<description>Port D pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU3</name>
<description>Port D pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU4</name>
<description>Port D pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU5</name>
<description>Port D pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU6</name>
<description>Port D pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU7</name>
<description>Port D pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU8</name>
<description>Port D pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU9</name>
<description>Port D pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU10</name>
<description>Port D pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU11</name>
<description>Port D pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU12</name>
<description>Port D pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU13</name>
<description>Port D pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU14</name>
<description>Port D pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU15</name>
<description>Port D pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_PDCRD</name>
<displayName>PWR_PDCRD</displayName>
<description>Power Port D pull-down control register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PD0</name>
<description>Port D pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD1</name>
<description>Port D pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD2</name>
<description>Port D pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD3</name>
<description>Port D pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD4</name>
<description>Port D pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD5</name>
<description>Port D pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD6</name>
<description>Port D pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD7</name>
<description>Port D pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD8</name>
<description>Port D pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD9</name>
<description>Port D pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD10</name>
<description>Port D pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD11</name>
<description>Port D pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD12</name>
<description>Port D pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD13</name>
<description>Port D pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD14</name>
<description>Port D pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD15</name>
<description>Port D pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_PUCRE</name>
<displayName>PWR_PUCRE</displayName>
<description>Power Port E pull-up control register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PU0</name>
<description>Port E pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU1</name>
<description>Port E pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU2</name>
<description>Port E pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU3</name>
<description>Port E pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU4</name>
<description>Port E pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU5</name>
<description>Port E pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU6</name>
<description>Port E pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU7</name>
<description>Port E pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU8</name>
<description>Port E pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU9</name>
<description>Port E pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU10</name>
<description>Port E pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU11</name>
<description>Port E pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU12</name>
<description>Port E pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU13</name>
<description>Port E pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU14</name>
<description>Port E pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU15</name>
<description>Port E pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_PDCRE</name>
<displayName>PWR_PDCRE</displayName>
<description>Power Port E pull-down control register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PD0</name>
<description>Port E pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD1</name>
<description>Port E pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD2</name>
<description>Port E pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD3</name>
<description>Port E pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD4</name>
<description>Port E pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD5</name>
<description>Port E pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD6</name>
<description>Port E pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD7</name>
<description>Port E pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD8</name>
<description>Port E pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD9</name>
<description>Port E pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD10</name>
<description>Port E pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD11</name>
<description>Port E pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD12</name>
<description>Port E pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD13</name>
<description>Port E pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD14</name>
<description>Port E pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD15</name>
<description>Port E pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_PUCRF</name>
<displayName>PWR_PUCRF</displayName>
<description>Power Port F pull-up control register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PU0</name>
<description>Port F pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU1</name>
<description>Port F pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU2</name>
<description>Port F pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU3</name>
<description>Port F pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU4</name>
<description>Port F pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU5</name>
<description>Port F pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU6</name>
<description>Port F pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU7</name>
<description>Port F pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU8</name>
<description>Port F pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU9</name>
<description>Port F pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU10</name>
<description>Port F pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU11</name>
<description>Port F pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU12</name>
<description>Port F pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU13</name>
<description>Port F pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU14</name>
<description>Port F pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU15</name>
<description>Port F pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_PDCRF</name>
<displayName>PWR_PDCRF</displayName>
<description>Power Port F pull-down control register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PD0</name>
<description>Port F pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD1</name>
<description>Port F pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD2</name>
<description>Port F pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD3</name>
<description>Port F pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD4</name>
<description>Port F pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD5</name>
<description>Port F pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD6</name>
<description>Port F pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD7</name>
<description>Port F pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD8</name>
<description>Port F pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD9</name>
<description>Port F pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD10</name>
<description>Port F pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD11</name>
<description>Port F pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD12</name>
<description>Port F pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD13</name>
<description>Port F pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD14</name>
<description>Port F pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD15</name>
<description>Port F pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_PUCRG</name>
<displayName>PWR_PUCRG</displayName>
<description>Power Port G pull-up control register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PU0</name>
<description>Port G pull-up bit y (y=0..10)
When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU1</name>
<description>Port G pull-up bit y (y=0..10)
When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU2</name>
<description>Port G pull-up bit y (y=0..10)
When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU3</name>
<description>Port G pull-up bit y (y=0..10)
When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU4</name>
<description>Port G pull-up bit y (y=0..10)
When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU5</name>
<description>Port G pull-up bit y (y=0..10)
When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU6</name>
<description>Port G pull-up bit y (y=0..10)
When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU7</name>
<description>Port G pull-up bit y (y=0..10)
When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU8</name>
<description>Port G pull-up bit y (y=0..10)
When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU9</name>
<description>Port G pull-up bit y (y=0..10)
When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PU10</name>
<description>Port G pull-up bit y (y=0..10)
When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_PDCRG</name>
<displayName>PWR_PDCRG</displayName>
<description>Power Port G pull-down control register</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PD0</name>
<description>Port G pull-down bit y (y=0..10)
When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD1</name>
<description>Port G pull-down bit y (y=0..10)
When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD2</name>
<description>Port G pull-down bit y (y=0..10)
When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD3</name>
<description>Port G pull-down bit y (y=0..10)
When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD4</name>
<description>Port G pull-down bit y (y=0..10)
When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD5</name>
<description>Port G pull-down bit y (y=0..10)
When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD6</name>
<description>Port G pull-down bit y (y=0..10)
When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD7</name>
<description>Port G pull-down bit y (y=0..10)
When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD8</name>
<description>Port G pull-down bit y (y=0..10)
When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD9</name>
<description>Port G pull-down bit y (y=0..10)
When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD10</name>
<description>Port G pull-down bit y (y=0..10)
When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_CR5</name>
<displayName>PWR_CR5</displayName>
<description>Power control register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<resetValue>0x00000100</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>R1MODE</name>
<description>Main regular range 1 mode
This bit is only valid for the main regulator in range 1 and has no effect on range 2. It is recommended to reset this bit when the system frequency is greater than 150 MHz. Refer to</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Main regulator in range 1 boost mode.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Main regulator in range 1 normal mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RNG</name>
<description>Random number generator</description>
<groupName>RNG</groupName>
<baseAddress>0x50060800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RNG</name>
<description>RNG</description>
<value>90</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CED</name>
<description>Clock error detection</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE</name>
<description>Interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RNGEN</name>
<description>Random number generator enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEIS</name>
<description>Seed error interrupt status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CEIS</name>
<description>Clock error interrupt status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SECS</name>
<description>Seed error current status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CECS</name>
<description>Clock error current status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DRDY</name>
<description>Data ready</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>data register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RNDATA</name>
<description>Random data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>AES</name>
<description>Advanced encryption standard hardware accelerator</description>
<groupName>AES</groupName>
<baseAddress>0x50060000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>AES</name>
<description>AES</description>
<value>85</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NPBLB</name>
<description>NPBLB</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>KEYSIZE</name>
<description>KEYSIZE</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHMOD_2</name>
<description>CHMOD_2</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GCMPH</name>
<description>GCMPH</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DMAOUTEN</name>
<description>Enable DMA management of data output phase</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAINEN</name>
<description>Enable DMA management of data input phase</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRIE</name>
<description>Error interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCFIE</name>
<description>CCF flag interrupt enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRC</name>
<description>Error clear</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCFC</name>
<description>Computation Complete Flag Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHMOD</name>
<description>AES chaining mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE</name>
<description>AES operating mode</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DATATYPE</name>
<description>Data type selection (for data in and data out to/from the cryptographic block)</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EN</name>
<description>AES enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BUSY</name>
<description>BUSY</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRERR</name>
<description>Write error flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDERR</name>
<description>Read error flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCF</name>
<description>Computation complete flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DINR</name>
<displayName>DINR</displayName>
<description>data input register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_DINR</name>
<description>Data Input Register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOUTR</name>
<displayName>DOUTR</displayName>
<description>data output register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_DOUTR</name>
<description>Data output register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR0</name>
<displayName>KEYR0</displayName>
<description>key register 0</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_KEYR0</name>
<description>Data Output Register (LSB key [31:0])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR1</name>
<displayName>KEYR1</displayName>
<description>key register 1</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_KEYR1</name>
<description>AES key register (key [63:32])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR2</name>
<displayName>KEYR2</displayName>
<description>key register 2</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_KEYR2</name>
<description>AES key register (key [95:64])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR3</name>
<displayName>KEYR3</displayName>
<description>key register 3</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_KEYR3</name>
<description>AES key register (MSB key [127:96])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IVR0</name>
<displayName>IVR0</displayName>
<description>initialization vector register 0</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_IVR0</name>
<description>initialization vector register (LSB IVR [31:0])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IVR1</name>
<displayName>IVR1</displayName>
<description>initialization vector register 1</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_IVR1</name>
<description>Initialization Vector Register (IVR [63:32])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IVR2</name>
<displayName>IVR2</displayName>
<description>initialization vector register 2</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_IVR2</name>
<description>Initialization Vector Register (IVR [95:64])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IVR3</name>
<displayName>IVR3</displayName>
<description>initialization vector register 3</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_IVR3</name>
<description>Initialization Vector Register (MSB IVR [127:96])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR4</name>
<displayName>KEYR4</displayName>
<description>key register 4</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEY</name>
<description>AES key</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR5</name>
<displayName>KEYR5</displayName>
<description>key register 5</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEY</name>
<description>AES key</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR6</name>
<displayName>KEYR6</displayName>
<description>key register 6</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEY</name>
<description>AES key</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR7</name>
<displayName>KEYR7</displayName>
<description>key register 7</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEY</name>
<description>AES key</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP0R</name>
<displayName>SUSP0R</displayName>
<description>suspend registers</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUSP</name>
<description>AES suspend</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP1R</name>
<displayName>SUSP1R</displayName>
<description>suspend registers</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUSP</name>
<description>AES suspend</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP2R</name>
<displayName>SUSP2R</displayName>
<description>suspend registers</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUSP</name>
<description>AES suspend</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP3R</name>
<displayName>SUSP3R</displayName>
<description>suspend registers</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUSP</name>
<description>AES suspend</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP4R</name>
<displayName>SUSP4R</displayName>
<description>suspend registers</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUSP</name>
<description>AES suspend</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP5R</name>
<displayName>SUSP5R</displayName>
<description>suspend registers</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUSP</name>
<description>AES suspend</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP6R</name>
<displayName>SUSP6R</displayName>
<description>suspend registers</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUSP</name>
<description>AES suspend</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP7R</name>
<displayName>SUSP7R</displayName>
<description>suspend registers</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUSP</name>
<description>AES suspend</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOA</name>
<description>General-purpose I/Os</description>
<groupName>GPIO</groupName>
<baseAddress>0x48000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MODER</name>
<displayName>MODER</displayName>
<description>GPIO port mode register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xABFFFFFF</resetValue>
<fields>
<field>
<name>MODER15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTYPER</name>
<displayName>OTYPER</displayName>
<description>GPIO port output type register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OT15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OSPEEDR</name>
<displayName>OSPEEDR</displayName>
<description>GPIO port output speed register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0C000000</resetValue>
<fields>
<field>
<name>OSPEEDR15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>PUPDR</name>
<displayName>PUPDR</displayName>
<description>GPIO port pull-up/pull-down register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x64000000</resetValue>
<fields>
<field>
<name>PUPDR15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<displayName>IDR</displayName>
<description>GPIO port input data register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDR15</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR14</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR13</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR12</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR11</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR10</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR9</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR8</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR7</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR6</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR5</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR4</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR3</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR2</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR1</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR0</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ODR</name>
<displayName>ODR</displayName>
<description>GPIO port output data register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ODR15</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR14</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR13</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR12</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR11</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR10</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR9</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR8</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR7</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR6</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR5</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR4</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR3</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR2</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR1</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR0</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BSRR</name>
<displayName>BSRR</displayName>
<description>GPIO port bit set/reset register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR15</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR14</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR13</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR12</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR11</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR10</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR9</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR8</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR7</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR6</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR5</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR4</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR3</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR2</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR1</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR0</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS15</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS14</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS13</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS12</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS11</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS10</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS9</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS8</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS7</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS6</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS5</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS4</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS3</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS2</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS1</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS0</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>LCKR</name>
<displayName>LCKR</displayName>
<description>GPIO port configuration lock register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LCKK</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK15</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK14</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK13</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK12</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK11</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK10</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK9</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK8</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK7</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK6</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK5</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK4</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK3</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK2</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK1</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK0</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFRL</name>
<displayName>AFRL</displayName>
<description>GPIO alternate function low register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFRL7</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL6</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL5</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL4</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL3</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL2</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL1</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL0</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFRH</name>
<displayName>AFRH</displayName>
<description>GPIO alternate function high register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFRH15</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH14</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH13</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH12</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH11</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH10</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH9</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH8</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>GPIO port bit reset register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR0</name>
<description>Port Reset bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR1</name>
<description>Port Reset bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR2</name>
<description>Port Reset bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR3</name>
<description>Port Reset bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR4</name>
<description>Port Reset bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR5</name>
<description>Port Reset bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR6</name>
<description>Port Reset bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR7</name>
<description>Port Reset bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR8</name>
<description>Port Reset bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR9</name>
<description>Port Reset bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR10</name>
<description>Port Reset bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR11</name>
<description>Port Reset bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR12</name>
<description>Port Reset bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR13</name>
<description>Port Reset bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR14</name>
<description>Port Reset bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR15</name>
<description>Port Reset bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOB</name>
<description>General-purpose I/Os</description>
<groupName>GPIO</groupName>
<baseAddress>0x48000400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MODER</name>
<displayName>MODER</displayName>
<description>GPIO port mode register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFEBF</resetValue>
<fields>
<field>
<name>MODER15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTYPER</name>
<displayName>OTYPER</displayName>
<description>GPIO port output type register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OT15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OSPEEDR</name>
<displayName>OSPEEDR</displayName>
<description>GPIO port output speed register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000000C0</resetValue>
<fields>
<field>
<name>OSPEEDR15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>PUPDR</name>
<displayName>PUPDR</displayName>
<description>GPIO port pull-up/pull-down register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000100</resetValue>
<fields>
<field>
<name>PUPDR15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<displayName>IDR</displayName>
<description>GPIO port input data register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDR15</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR14</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR13</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR12</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR11</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR10</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR9</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR8</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR7</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR6</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR5</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR4</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR3</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR2</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR1</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR0</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ODR</name>
<displayName>ODR</displayName>
<description>GPIO port output data register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ODR15</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR14</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR13</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR12</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR11</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR10</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR9</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR8</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR7</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR6</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR5</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR4</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR3</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR2</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR1</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR0</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BSRR</name>
<displayName>BSRR</displayName>
<description>GPIO port bit set/reset register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR15</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR14</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR13</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR12</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR11</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR10</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR9</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR8</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR7</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR6</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR5</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR4</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR3</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR2</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR1</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR0</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS15</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS14</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS13</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS12</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS11</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS10</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS9</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS8</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS7</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS6</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS5</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS4</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS3</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS2</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS1</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS0</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>LCKR</name>
<displayName>LCKR</displayName>
<description>GPIO port configuration lock register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LCKK</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK15</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK14</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK13</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK12</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK11</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK10</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK9</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK8</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK7</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK6</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK5</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK4</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK3</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK2</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK1</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK0</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFRL</name>
<displayName>AFRL</displayName>
<description>GPIO alternate function low register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFRL7</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL6</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL5</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL4</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL3</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL2</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL1</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL0</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFRH</name>
<displayName>AFRH</displayName>
<description>GPIO alternate function high register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFRH15</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH14</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH13</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH12</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH11</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH10</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH9</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH8</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>GPIO port bit reset register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR0</name>
<description>Port Reset bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR1</name>
<description>Port Reset bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR2</name>
<description>Port Reset bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR3</name>
<description>Port Reset bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR4</name>
<description>Port Reset bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR5</name>
<description>Port Reset bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR6</name>
<description>Port Reset bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR7</name>
<description>Port Reset bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR8</name>
<description>Port Reset bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR9</name>
<description>Port Reset bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR10</name>
<description>Port Reset bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR11</name>
<description>Port Reset bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR12</name>
<description>Port Reset bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR13</name>
<description>Port Reset bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR14</name>
<description>Port Reset bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR15</name>
<description>Port Reset bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOC</name>
<description>General-purpose I/Os</description>
<groupName>GPIO</groupName>
<baseAddress>0x48000800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MODER</name>
<displayName>MODER</displayName>
<description>GPIO port mode register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>MODER15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTYPER</name>
<displayName>OTYPER</displayName>
<description>GPIO port output type register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OT15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OSPEEDR</name>
<displayName>OSPEEDR</displayName>
<description>GPIO port output speed register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OSPEEDR15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>PUPDR</name>
<displayName>PUPDR</displayName>
<description>GPIO port pull-up/pull-down register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PUPDR15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<displayName>IDR</displayName>
<description>GPIO port input data register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDR15</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR14</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR13</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR12</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR11</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR10</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR9</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR8</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR7</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR6</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR5</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR4</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR3</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR2</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR1</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR0</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ODR</name>
<displayName>ODR</displayName>
<description>GPIO port output data register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ODR15</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR14</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR13</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR12</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR11</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR10</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR9</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR8</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR7</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR6</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR5</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR4</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR3</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR2</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR1</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR0</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BSRR</name>
<displayName>BSRR</displayName>
<description>GPIO port bit set/reset register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR15</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR14</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR13</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR12</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR11</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR10</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR9</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR8</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR7</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR6</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR5</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR4</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR3</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR2</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR1</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR0</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS15</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS14</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS13</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS12</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS11</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS10</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS9</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS8</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS7</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS6</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS5</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS4</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS3</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS2</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS1</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS0</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>LCKR</name>
<displayName>LCKR</displayName>
<description>GPIO port configuration lock register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LCKK</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK15</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK14</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK13</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK12</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK11</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK10</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK9</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK8</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK7</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK6</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK5</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK4</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK3</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK2</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK1</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK0</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFRL</name>
<displayName>AFRL</displayName>
<description>GPIO alternate function low register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFRL7</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL6</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL5</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL4</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL3</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL2</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL1</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRL0</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFRH</name>
<displayName>AFRH</displayName>
<description>GPIO alternate function high register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFRH15</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH14</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH13</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH12</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH11</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH10</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH9</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFRH8</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>GPIO port bit reset register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR0</name>
<description>Port Reset bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR1</name>
<description>Port Reset bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR2</name>
<description>Port Reset bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR3</name>
<description>Port Reset bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR4</name>
<description>Port Reset bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR5</name>
<description>Port Reset bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR6</name>
<description>Port Reset bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR7</name>
<description>Port Reset bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR8</name>
<description>Port Reset bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR9</name>
<description>Port Reset bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR10</name>
<description>Port Reset bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR11</name>
<description>Port Reset bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR12</name>
<description>Port Reset bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR13</name>
<description>Port Reset bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR14</name>
<description>Port Reset bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR15</name>
<description>Port Reset bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="GPIOC">
<name>GPIOD</name>
<baseAddress>0x48000C00</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOC">
<name>GPIOE</name>
<baseAddress>0x48001000</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOC">
<name>GPIOF</name>
<baseAddress>0x48001400</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOC">
<name>GPIOG</name>
<baseAddress>0x48001800</baseAddress>
</peripheral>
<peripheral>
<name>TIM15</name>
<description>General purpose timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40014000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>UIFREMAP</name>
<description>UIF status bit remapping</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DITHEN</name>
<description>Dithering Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OIS2</name>
<description>Output idle state 2 (OC2 output)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1N</name>
<description>Output Idle state 1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1</name>
<description>Output Idle state 1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TI1S</name>
<description>TI1 selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMS</name>
<description>Master mode selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CCDS</name>
<description>Capture/compare DMA selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCUS</name>
<description>Capture/compare control update selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCPC</name>
<description>Capture/compare preloaded control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMCR</name>
<displayName>SMCR</displayName>
<description>slave mode control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TS_4_3</name>
<description>Trigger selection - bit 4:3</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SMS_3</name>
<description>Slave mode selection - bit 3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSM</name>
<description>Master/Slave mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TS</name>
<description>Trigger selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMS</name>
<description>Slave mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TDE</name>
<description>Trigger DMA request enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMDE</name>
<description>COM DMA request enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2DE</name>
<description>Capture/Compare 2 DMA request enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1DE</name>
<description>Capture/Compare 1 DMA request enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIE</name>
<description>Break interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE</name>
<description>Trigger interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIE</name>
<description>COM interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IE</name>
<description>Capture/Compare 2 interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC2OF</name>
<description>Capture/Compare 2 overcapture flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIF</name>
<description>Break interrupt flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIF</name>
<description>Trigger interrupt flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIF</name>
<description>COM interrupt flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IF</name>
<description>Capture/compare 2 interrupt flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BG</name>
<description>Break generation</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TG</name>
<description>Trigger generation</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMG</name>
<description>Capture/Compare control update generation</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2G</name>
<description>Capture/compare 2 generation</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1G</name>
<description>Capture/compare 1 generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register (output mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC2M_3</name>
<description>Output Compare 2 mode - bit 3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M_3</name>
<description>Output Compare 1 mode</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2M</name>
<description>OC2M</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC2PE</name>
<description>OC2PE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2FE</name>
<description>OC2FE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>CC2S</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC1CE</name>
<description>OC1CE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>Output Compare 1 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC1PE</name>
<description>Output Compare 1 preload enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1FE</name>
<description>Output Compare 1 fast enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (input mode)</description>
<alternateRegister>CCMR1_Output</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC2F</name>
<description>IC2F</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC2PSC</name>
<description>IC2PSC</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>CC2S</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC1PSC</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC2NP</name>
<description>Capture/Compare 2 complementary output polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2P</name>
<description>Capture/Compare 2 output polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2E</name>
<description>Capture/Compare 2 output enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NE</name>
<description>Capture/Compare 1 complementary output enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UIFCPY</name>
<description>UIF Copy</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RCR</name>
<displayName>RCR</displayName>
<description>repetition counter register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REP</name>
<description>Repetition counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR1</name>
<displayName>CCR1</displayName>
<description>capture/compare register 1</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR1</name>
<description>Capture/Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR2</name>
<displayName>CCR2</displayName>
<description>capture/compare register 2</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR2</name>
<description>Capture/Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>BDTR</name>
<displayName>BDTR</displayName>
<description>break and dead-time register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DTG</name>
<description>Dead-time generator setup</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock configuration</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSSI</name>
<description>Off-state selection for Idle mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSR</name>
<description>Off-state selection for Run mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKE</name>
<description>Break enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKP</name>
<description>Break polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AOE</name>
<description>Automatic output enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MOE</name>
<description>Main output enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKF</name>
<description>Break filter</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BKDSRM</name>
<description>BKDSRM</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKBID</name>
<description>BKBID</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DTR2</name>
<displayName>DTR2</displayName>
<description>timer Deadtime Register 2</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DTGF</name>
<description>Dead-time generator setup</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DTAE</name>
<description>Deadtime Asymmetric Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTPE</name>
<description>Deadtime Preload Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TISEL</name>
<displayName>TISEL</displayName>
<description>TIM timer input selection register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TI1SEL</name>
<description>TI1[0] to TI1[15] input selection</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TI2SEL</name>
<description>TI2[0] to TI2[15] input selection</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AF1</name>
<displayName>AF1</displayName>
<description>TIM alternate function option register 1</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKCMP4P</name>
<description>BRK COMP4 input polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP3P</name>
<description>BRK COMP3 input polarity</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2P</name>
<description>BRK COMP2 input polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1P</name>
<description>BRK COMP1 input polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKINP</name>
<description>BRK BKIN input polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP7E</name>
<description>BRK COMP7 enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP6E</name>
<description>BRK COMP6 enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP5E</name>
<description>BRK COMP5 enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP4E</name>
<description>BRK COMP4 enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP3E</name>
<description>BRK COMP3 enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2E</name>
<description>BRK COMP2 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1E</name>
<description>BRK COMP1 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKINE</name>
<description>BRK BKIN input enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AF2</name>
<displayName>AF2</displayName>
<description>TIM alternate function option register 2</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OCRSEL</name>
<description>OCREF_CLR source selection</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCR</name>
<displayName>DCR</displayName>
<description>DMA control register</description>
<addressOffset>0x3DC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DBL</name>
<description>DMA burst length</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DBA</name>
<description>DMA base address</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAR</name>
<displayName>DMAR</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x3E0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAB</name>
<description>DMA register for burst accesses</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TIM16</name>
<description>General purpose timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40014400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>UIFREMAP</name>
<description>UIF status bit remapping</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DITHEN</name>
<description>Dithering Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OIS1N</name>
<description>Output Idle state 1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1</name>
<description>Output Idle state 1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCDS</name>
<description>Capture/compare DMA selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCUS</name>
<description>Capture/compare control update selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCPC</name>
<description>Capture/compare preloaded control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMDE</name>
<description>COM DMA request enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1DE</name>
<description>Capture/Compare 1 DMA request enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIE</name>
<description>Break interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIE</name>
<description>COM interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIF</name>
<description>Break interrupt flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIF</name>
<description>COM interrupt flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BG</name>
<description>Break generation</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMG</name>
<description>Capture/Compare control update generation</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1G</name>
<description>Capture/compare 1 generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register (output mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC1M_3</name>
<description>Output Compare 1 mode</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>Output Compare 1 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC1PE</name>
<description>Output Compare 1 preload enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1FE</name>
<description>Output Compare 1 fast enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (input mode)</description>
<alternateRegister>CCMR1_Output</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC1PSC</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NE</name>
<description>Capture/Compare 1 complementary output enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UIFCPY</name>
<description>UIF Copy</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RCR</name>
<displayName>RCR</displayName>
<description>repetition counter register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REP</name>
<description>Repetition counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR1</name>
<displayName>CCR1</displayName>
<description>capture/compare register 1</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR1</name>
<description>Capture/Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>BDTR</name>
<displayName>BDTR</displayName>
<description>break and dead-time register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DTG</name>
<description>Dead-time generator setup</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock configuration</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSSI</name>
<description>Off-state selection for Idle mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSR</name>
<description>Off-state selection for Run mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKE</name>
<description>Break enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKP</name>
<description>Break polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AOE</name>
<description>Automatic output enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MOE</name>
<description>Main output enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKF</name>
<description>Break filter</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BKDSRM</name>
<description>BKDSRM</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKBID</name>
<description>BKBID</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DTR2</name>
<displayName>DTR2</displayName>
<description>timer Deadtime Register 2</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DTGF</name>
<description>Dead-time generator setup</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DTAE</name>
<description>Deadtime Asymmetric Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTPE</name>
<description>Deadtime Preload Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TISEL</name>
<displayName>TISEL</displayName>
<description>TIM timer input selection register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TI1SEL</name>
<description>TI1[0] to TI1[15] input selection</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AF1</name>
<displayName>AF1</displayName>
<description>TIM alternate function option register 1</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKCMP4P</name>
<description>BRK COMP4 input polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP3P</name>
<description>BRK COMP3 input polarity</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2P</name>
<description>BRK COMP2 input polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1P</name>
<description>BRK COMP1 input polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKINP</name>
<description>BRK BKIN input polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP7E</name>
<description>BRK COMP7 enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP6E</name>
<description>BRK COMP6 enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP5E</name>
<description>BRK COMP5 enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP4E</name>
<description>BRK COMP4 enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP3E</name>
<description>BRK COMP3 enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2E</name>
<description>BRK COMP2 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1E</name>
<description>BRK COMP1 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKINE</name>
<description>BRK BKIN input enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AF2</name>
<displayName>AF2</displayName>
<description>TIM alternate function option register 2</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OCRSEL</name>
<description>OCREF_CLR source selection</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>OR1</name>
<displayName>OR1</displayName>
<description>TIM option register 1</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HSE32EN</name>
<description>HSE Divided by 32 enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCR</name>
<displayName>DCR</displayName>
<description>DMA control register</description>
<addressOffset>0x3DC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DBL</name>
<description>DMA burst length</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DBA</name>
<description>DMA base address</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAR</name>
<displayName>DMAR</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x3E0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAB</name>
<description>DMA register for burst accesses</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="TIM16">
<name>TIM17</name>
<baseAddress>0x40014800</baseAddress>
</peripheral>
<peripheral>
<name>TIM1</name>
<description>Advanced-timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40012C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIM1_BRK_TIM15</name>
<description>TIM1_BRK_TIM15</description>
<value>24</value>
</interrupt>
<interrupt>
<name>TIM1_UP_TIM16</name>
<description>TIM1_UP_TIM16</description>
<value>25</value>
</interrupt>
<interrupt>
<name>TIM1_TRG_COM</name>
<description>TIM1_TRG_COM/</description>
<value>26</value>
</interrupt>
<interrupt>
<name>TIM1_CC</name>
<description>TIM1 capture compare interrupt</description>
<value>27</value>
</interrupt>
<interrupt>
<name>TIM8_CC</name>
<description>TIM8_CC</description>
<value>46</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DITHEN</name>
<description>Dithering Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIFREMAP</name>
<description>UIF status bit remapping</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMS</name>
<description>Center-aligned mode selection</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MMS_3</name>
<description>Master mode selection - bit 3</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMS2</name>
<description>Master mode selection 2</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>OIS6</name>
<description>Output Idle state 6 (OC6 output)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS5</name>
<description>Output Idle state 5 (OC5 output)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS4N</name>
<description>Output Idle state 4 (OC4N output)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS4</name>
<description>Output Idle state 4</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS3N</name>
<description>Output Idle state 3</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS3</name>
<description>Output Idle state 3</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS2N</name>
<description>Output Idle state 2</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS2</name>
<description>Output Idle state 2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1N</name>
<description>Output Idle state 1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1</name>
<description>Output Idle state 1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TI1S</name>
<description>TI1 selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMS</name>
<description>Master mode selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CCDS</name>
<description>Capture/compare DMA selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCUS</name>
<description>Capture/compare control update selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCPC</name>
<description>Capture/compare preloaded control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMCR</name>
<displayName>SMCR</displayName>
<description>slave mode control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SMSPS</name>
<description>SMS Preload Source</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMSPE</name>
<description>SMS Preload Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TS_4_3</name>
<description>Trigger selection - bit 4:3</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SMS_3</name>
<description>Slave mode selection - bit 3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETP</name>
<description>External trigger polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECE</name>
<description>External clock enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETPS</name>
<description>External trigger prescaler</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ETF</name>
<description>External trigger filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MSM</name>
<description>Master/Slave mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TS</name>
<description>Trigger selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OCCS</name>
<description>OCREF clear selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMS</name>
<description>Slave mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TERRIE</name>
<description>Transition Error interrupt enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IERRIE</name>
<description>Index Error interrupt enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIRIE</name>
<description>Direction Change interrupt enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDXIE</name>
<description>Index interrupt enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDE</name>
<description>Trigger DMA request enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMDE</name>
<description>COM DMA request enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4DE</name>
<description>Capture/Compare 4 DMA request enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3DE</name>
<description>Capture/Compare 3 DMA request enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2DE</name>
<description>Capture/Compare 2 DMA request enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1DE</name>
<description>Capture/Compare 1 DMA request enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE</name>
<description>Trigger interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4IE</name>
<description>Capture/Compare 4 interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3IE</name>
<description>Capture/Compare 3 interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IE</name>
<description>Capture/Compare 2 interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIE</name>
<description>Break interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIE</name>
<description>COM interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TERRF</name>
<description>Transition Error interrupt flag</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IERRF</name>
<description>Index Error interrupt flag</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIRF</name>
<description>Direction Change interrupt flag</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDXF</name>
<description>Index interrupt flag</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC6IF</name>
<description>Compare 6 interrupt flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC5IF</name>
<description>Compare 5 interrupt flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBIF</name>
<description>System Break interrupt flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4OF</name>
<description>Capture/Compare 4 overcapture flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3OF</name>
<description>Capture/Compare 3 overcapture flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2OF</name>
<description>Capture/compare 2 overcapture flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>B2IF</name>
<description>Break 2 interrupt flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIF</name>
<description>Break interrupt flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIF</name>
<description>Trigger interrupt flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIF</name>
<description>COM interrupt flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4IF</name>
<description>Capture/Compare 4 interrupt flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3IF</name>
<description>Capture/Compare 3 interrupt flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IF</name>
<description>Capture/Compare 2 interrupt flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>B2G</name>
<description>Break 2 generation</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BG</name>
<description>Break generation</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TG</name>
<description>Trigger generation</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMG</name>
<description>Capture/Compare control update generation</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4G</name>
<description>Capture/compare 4 generation</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3G</name>
<description>Capture/compare 3 generation</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2G</name>
<description>Capture/compare 2 generation</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1G</name>
<description>Capture/compare 1 generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register 1 (output mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC2M_3</name>
<description>Output Compare 2 mode - bit 3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M_3</name>
<description>Output Compare 1 mode - bit 3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2CE</name>
<description>Output Compare 2 clear enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2M</name>
<description>Output Compare 2 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC2PE</name>
<description>Output Compare 2 preload enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2FE</name>
<description>Output Compare 2 fast enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/Compare 2 selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC1CE</name>
<description>Output Compare 1 clear enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>Output Compare 1 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC1PE</name>
<description>Output Compare 1 preload enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1FE</name>
<description>Output Compare 1 fast enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (input mode)</description>
<alternateRegister>CCMR1_Output</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC2F</name>
<description>Input capture 2 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC2PSC</name>
<description>Input capture 2 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/Compare 2 selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ICPCS</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR2_Output</name>
<displayName>CCMR2_Output</displayName>
<description>capture/compare mode register 2 (output mode)</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC4M_3</name>
<description>Output Compare 4 mode - bit 3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3M_3</name>
<description>Output Compare 3 mode - bit 3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4CE</name>
<description>Output compare 4 clear enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4M</name>
<description>Output compare 4 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC4PE</name>
<description>Output compare 4 preload enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4FE</name>
<description>Output compare 4 fast enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>Capture/Compare 4 selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC3CE</name>
<description>Output compare 3 clear enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3M</name>
<description>Output compare 3 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC3PE</name>
<description>Output compare 3 preload enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3FE</name>
<description>Output compare 3 fast enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3S</name>
<description>Capture/Compare 3 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR2_Input</name>
<displayName>CCMR2_Input</displayName>
<description>capture/compare mode register 2 (input mode)</description>
<alternateRegister>CCMR2_Output</alternateRegister>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC4F</name>
<description>Input capture 4 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC4PSC</name>
<description>Input capture 4 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>Capture/Compare 4 selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC3F</name>
<description>Input capture 3 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC3PSC</name>
<description>Input capture 3 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC3S</name>
<description>Capture/compare 3 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC6P</name>
<description>Capture/Compare 6 output polarity</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC6E</name>
<description>Capture/Compare 6 output enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC5P</name>
<description>Capture/Compare 5 output polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC5E</name>
<description>Capture/Compare 5 output enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4NP</name>
<description>Capture/Compare 4 complementary output polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4NE</name>
<description>Capture/Compare 4 complementary output enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4P</name>
<description>Capture/Compare 3 output Polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4E</name>
<description>Capture/Compare 4 output enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3NP</name>
<description>Capture/Compare 3 output Polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3NE</name>
<description>Capture/Compare 3 complementary output enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3P</name>
<description>Capture/Compare 3 output Polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3E</name>
<description>Capture/Compare 3 output enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2NP</name>
<description>Capture/Compare 2 output Polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2NE</name>
<description>Capture/Compare 2 complementary output enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2P</name>
<description>Capture/Compare 2 output Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2E</name>
<description>Capture/Compare 2 output enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NE</name>
<description>Capture/Compare 1 complementary output enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UIFCPY</name>
<description>UIFCPY</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CNT</name>
<description>counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RCR</name>
<displayName>RCR</displayName>
<description>repetition counter register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REP</name>
<description>Repetition counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR1</name>
<displayName>CCR1</displayName>
<description>capture/compare register 1</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR1</name>
<description>Capture/Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR2</name>
<displayName>CCR2</displayName>
<description>capture/compare register 2</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR2</name>
<description>Capture/Compare 2 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR3</name>
<displayName>CCR3</displayName>
<description>capture/compare register 3</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR3</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR4</name>
<displayName>CCR4</displayName>
<description>capture/compare register 4</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR4</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>BDTR</name>
<displayName>BDTR</displayName>
<description>break and dead-time register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BK2ID</name>
<description>BK2ID</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKBID</name>
<description>BKBID</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2DSRM</name>
<description>BK2DSRM</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKDSRM</name>
<description>BKDSRM</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2P</name>
<description>Break 2 polarity</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2E</name>
<description>Break 2 Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2F</name>
<description>Break 2 filter</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BKF</name>
<description>Break filter</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MOE</name>
<description>Main output enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AOE</name>
<description>Automatic output enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKP</name>
<description>Break polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKE</name>
<description>Break enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSR</name>
<description>Off-state selection for Run mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSI</name>
<description>Off-state selection for Idle mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock configuration</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTG</name>
<description>Dead-time generator setup</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR5</name>
<displayName>CCR5</displayName>
<description>capture/compare register 4</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR5</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>GC5C1</name>
<description>Group Channel 5 and Channel 1</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GC5C2</name>
<description>Group Channel 5 and Channel 2</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GC5C3</name>
<description>Group Channel 5 and Channel 3</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR6</name>
<displayName>CCR6</displayName>
<description>capture/compare register 4</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR6</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR3_Output</name>
<displayName>CCMR3_Output</displayName>
<description>capture/compare mode register 2 (output mode)</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC6M_bit3</name>
<description>Output Compare 6 mode bit 3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC5M_bit3</name>
<description>Output Compare 5 mode bit 3</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC6CE</name>
<description>Output compare 6 clear enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC6M</name>
<description>Output compare 6 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC6PE</name>
<description>Output compare 6 preload enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC6FE</name>
<description>Output compare 6 fast enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC5CE</name>
<description>Output compare 5 clear enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC5M</name>
<description>Output compare 5 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC5PE</name>
<description>Output compare 5 preload enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC5FE</name>
<description>Output compare 5 fast enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DTR2</name>
<displayName>DTR2</displayName>
<description>timer Deadtime Register 2</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DTPE</name>
<description>Deadtime Preload Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTAE</name>
<description>Deadtime Asymmetric Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTGF</name>
<description>Dead-time falling edge generator setup</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ECR</name>
<displayName>ECR</displayName>
<description>DMA control register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IE</name>
<description>Index Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDIR</name>
<description>Index Direction</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IBLK</name>
<description>Index Blanking</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FIDX</name>
<description>First Index</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IPOS</name>
<description>Index Positioning</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PW</name>
<description>Pulse width</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PWPRSC</name>
<description>Pulse Width prescaler</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TISEL</name>
<displayName>TISEL</displayName>
<description>TIM timer input selection register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TI1SEL</name>
<description>TI1[0] to TI1[15] input selection</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TI2SEL</name>
<description>TI2[0] to TI2[15] input selection</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TI3SEL</name>
<description>TI3[0] to TI3[15] input selection</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TI4SEL</name>
<description>TI4[0] to TI4[15] input selection</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AF1</name>
<displayName>AF1</displayName>
<description>TIM alternate function option register 1</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ETRSEL</name>
<description>ETR source selection</description>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BKCMP4P</name>
<description>BRK COMP4 input polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP3P</name>
<description>BRK COMP3 input polarity</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2P</name>
<description>BRK COMP2 input polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1P</name>
<description>BRK COMP1 input polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKINP</name>
<description>BRK BKIN input polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP7E</name>
<description>BRK COMP7 enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP6E</name>
<description>BRK COMP6 enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP5E</name>
<description>BRK COMP5 enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP4E</name>
<description>BRK COMP4 enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP3E</name>
<description>BRK COMP3 enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2E</name>
<description>BRK COMP2 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1E</name>
<description>BRK COMP1 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKINE</name>
<description>BRK BKIN input enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AF2</name>
<displayName>AF2</displayName>
<description>TIM alternate function option register 2</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OCRSEL</name>
<description>OCREF_CLR source selection</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>BK2CMP4P</name>
<description>BRK2 COMP4 input polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP3P</name>
<description>BRK2 COMP3 input polarity</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP2P</name>
<description>BRK2 COMP2 input polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP1P</name>
<description>BRK2 COMP1 input polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2INP</name>
<description>BRK2 BKIN input polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP7E</name>
<description>BRK2 COMP7 enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP6E</name>
<description>BRK2 COMP6 enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP5E</name>
<description>BRK2 COMP5 enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP4E</name>
<description>BRK2 COMP4 enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP3E</name>
<description>BRK2 COMP3 enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP2E</name>
<description>BRK2 COMP2 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP1E</name>
<description>BRK2 COMP1 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKINE</name>
<description>BRK BKIN input enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCR</name>
<displayName>DCR</displayName>
<description>control register</description>
<addressOffset>0x3DC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DBL</name>
<description>DMA burst length</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DBA</name>
<description>DMA base address</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAR</name>
<displayName>DMAR</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x3E0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAB</name>
<description>DMA register for burst accesses</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="TIM1">
<name>TIM8</name>
<baseAddress>0x40013400</baseAddress>
<interrupt>
<name>TIM8_BRK</name>
<description>TIM8_BRK</description>
<value>43</value>
</interrupt>
<interrupt>
<name>TIM8_UP</name>
<description>TIM8_UP</description>
<value>44</value>
</interrupt>
<interrupt>
<name>TIM8_TRG_COM</name>
<description>TIM8_TRG_COM</description>
<value>45</value>
</interrupt>
</peripheral>
<peripheral>
<name>TIM2</name>
<description>Advanced-timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIM2</name>
<description>TIM2</description>
<value>28</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DITHEN</name>
<description>Dithering Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIFREMAP</name>
<description>UIF status bit remapping</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMS</name>
<description>Center-aligned mode selection</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MMS_3</name>
<description>Master mode selection - bit 3</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMS2</name>
<description>Master mode selection 2</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>OIS6</name>
<description>Output Idle state 6 (OC6 output)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS5</name>
<description>Output Idle state 5 (OC5 output)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS4N</name>
<description>Output Idle state 4 (OC4N output)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS4</name>
<description>Output Idle state 4</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS3N</name>
<description>Output Idle state 3</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS3</name>
<description>Output Idle state 3</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS2N</name>
<description>Output Idle state 2</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS2</name>
<description>Output Idle state 2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1N</name>
<description>Output Idle state 1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1</name>
<description>Output Idle state 1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TI1S</name>
<description>TI1 selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMS</name>
<description>Master mode selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CCDS</name>
<description>Capture/compare DMA selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCUS</name>
<description>Capture/compare control update selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCPC</name>
<description>Capture/compare preloaded control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMCR</name>
<displayName>SMCR</displayName>
<description>slave mode control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SMSPS</name>
<description>SMS Preload Source</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMSPE</name>
<description>SMS Preload Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TS_4_3</name>
<description>Trigger selection - bit 4:3</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SMS_3</name>
<description>Slave mode selection - bit 3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETP</name>
<description>External trigger polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECE</name>
<description>External clock enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETPS</name>
<description>External trigger prescaler</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ETF</name>
<description>External trigger filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MSM</name>
<description>Master/Slave mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TS</name>
<description>Trigger selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OCCS</name>
<description>OCREF clear selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMS</name>
<description>Slave mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TERRIE</name>
<description>Transition Error interrupt enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IERRIE</name>
<description>Index Error interrupt enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIRIE</name>
<description>Direction Change interrupt enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDXIE</name>
<description>Index interrupt enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDE</name>
<description>Trigger DMA request enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMDE</name>
<description>COM DMA request enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4DE</name>
<description>Capture/Compare 4 DMA request enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3DE</name>
<description>Capture/Compare 3 DMA request enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2DE</name>
<description>Capture/Compare 2 DMA request enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1DE</name>
<description>Capture/Compare 1 DMA request enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE</name>
<description>Trigger interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4IE</name>
<description>Capture/Compare 4 interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3IE</name>
<description>Capture/Compare 3 interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IE</name>
<description>Capture/Compare 2 interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIE</name>
<description>Break interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIE</name>
<description>COM interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TERRF</name>
<description>Transition Error interrupt flag</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IERRF</name>
<description>Index Error interrupt flag</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIRF</name>
<description>Direction Change interrupt flag</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDXF</name>
<description>Index interrupt flag</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC6IF</name>
<description>Compare 6 interrupt flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC5IF</name>
<description>Compare 5 interrupt flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBIF</name>
<description>System Break interrupt flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4OF</name>
<description>Capture/Compare 4 overcapture flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3OF</name>
<description>Capture/Compare 3 overcapture flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2OF</name>
<description>Capture/compare 2 overcapture flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>B2IF</name>
<description>Break 2 interrupt flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIF</name>
<description>Break interrupt flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIF</name>
<description>Trigger interrupt flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIF</name>
<description>COM interrupt flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4IF</name>
<description>Capture/Compare 4 interrupt flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3IF</name>
<description>Capture/Compare 3 interrupt flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IF</name>
<description>Capture/Compare 2 interrupt flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>B2G</name>
<description>Break 2 generation</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BG</name>
<description>Break generation</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TG</name>
<description>Trigger generation</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMG</name>
<description>Capture/Compare control update generation</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4G</name>
<description>Capture/compare 4 generation</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3G</name>
<description>Capture/compare 3 generation</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2G</name>
<description>Capture/compare 2 generation</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1G</name>
<description>Capture/compare 1 generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register 1 (output mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC2M_3</name>
<description>Output Compare 2 mode - bit 3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M_3</name>
<description>Output Compare 1 mode - bit 3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2CE</name>
<description>Output Compare 2 clear enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2M</name>
<description>Output Compare 2 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC2PE</name>
<description>Output Compare 2 preload enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2FE</name>
<description>Output Compare 2 fast enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/Compare 2 selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC1CE</name>
<description>Output Compare 1 clear enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>Output Compare 1 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC1PE</name>
<description>Output Compare 1 preload enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1FE</name>
<description>Output Compare 1 fast enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (input mode)</description>
<alternateRegister>CCMR1_Output</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC2F</name>
<description>Input capture 2 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC2PSC</name>
<description>Input capture 2 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/Compare 2 selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ICPCS</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR2_Output</name>
<displayName>CCMR2_Output</displayName>
<description>capture/compare mode register 2 (output mode)</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC4M_3</name>
<description>Output Compare 4 mode - bit 3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3M_3</name>
<description>Output Compare 3 mode - bit 3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4CE</name>
<description>Output compare 4 clear enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4M</name>
<description>Output compare 4 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC4PE</name>
<description>Output compare 4 preload enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4FE</name>
<description>Output compare 4 fast enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>Capture/Compare 4 selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC3CE</name>
<description>Output compare 3 clear enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3M</name>
<description>Output compare 3 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC3PE</name>
<description>Output compare 3 preload enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3FE</name>
<description>Output compare 3 fast enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3S</name>
<description>Capture/Compare 3 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR2_Input</name>
<displayName>CCMR2_Input</displayName>
<description>capture/compare mode register 2 (input mode)</description>
<alternateRegister>CCMR2_Output</alternateRegister>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC4F</name>
<description>Input capture 4 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC4PSC</name>
<description>Input capture 4 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>Capture/Compare 4 selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC3F</name>
<description>Input capture 3 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC3PSC</name>
<description>Input capture 3 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC3S</name>
<description>Capture/compare 3 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC6P</name>
<description>Capture/Compare 6 output polarity</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC6E</name>
<description>Capture/Compare 6 output enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC5P</name>
<description>Capture/Compare 5 output polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC5E</name>
<description>Capture/Compare 5 output enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4NP</name>
<description>Capture/Compare 4 complementary output polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4NE</name>
<description>Capture/Compare 4 complementary output enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4P</name>
<description>Capture/Compare 3 output Polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4E</name>
<description>Capture/Compare 4 output enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3NP</name>
<description>Capture/Compare 3 output Polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3NE</name>
<description>Capture/Compare 3 complementary output enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3P</name>
<description>Capture/Compare 3 output Polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3E</name>
<description>Capture/Compare 3 output enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2NP</name>
<description>Capture/Compare 2 output Polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2NE</name>
<description>Capture/Compare 2 complementary output enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2P</name>
<description>Capture/Compare 2 output Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2E</name>
<description>Capture/Compare 2 output enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NE</name>
<description>Capture/Compare 1 complementary output enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UIFCPY</name>
<description>UIFCPY</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT</name>
<description>counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RCR</name>
<displayName>RCR</displayName>
<description>repetition counter register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REP</name>
<description>Repetition counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR1</name>
<displayName>CCR1</displayName>
<description>capture/compare register 1</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR1</name>
<description>Capture/Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR2</name>
<displayName>CCR2</displayName>
<description>capture/compare register 2</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR2</name>
<description>Capture/Compare 2 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR3</name>
<displayName>CCR3</displayName>
<description>capture/compare register 3</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR3</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR4</name>
<displayName>CCR4</displayName>
<description>capture/compare register 4</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR4</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>BDTR</name>
<displayName>BDTR</displayName>
<description>break and dead-time register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BK2ID</name>
<description>BK2ID</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKBID</name>
<description>BKBID</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2DSRM</name>
<description>BK2DSRM</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKDSRM</name>
<description>BKDSRM</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2P</name>
<description>Break 2 polarity</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2E</name>
<description>Break 2 Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2F</name>
<description>Break 2 filter</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BKF</name>
<description>Break filter</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MOE</name>
<description>Main output enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AOE</name>
<description>Automatic output enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKP</name>
<description>Break polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKE</name>
<description>Break enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSR</name>
<description>Off-state selection for Run mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSI</name>
<description>Off-state selection for Idle mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock configuration</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTG</name>
<description>Dead-time generator setup</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR5</name>
<displayName>CCR5</displayName>
<description>capture/compare register 4</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR5</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>GC5C1</name>
<description>Group Channel 5 and Channel 1</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GC5C2</name>
<description>Group Channel 5 and Channel 2</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GC5C3</name>
<description>Group Channel 5 and Channel 3</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR6</name>
<displayName>CCR6</displayName>
<description>capture/compare register 4</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR6</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR3_Output</name>
<displayName>CCMR3_Output</displayName>
<description>capture/compare mode register 2 (output mode)</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC6M_bit3</name>
<description>Output Compare 6 mode bit 3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC5M_bit3</name>
<description>Output Compare 5 mode bit 3</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC6CE</name>
<description>Output compare 6 clear enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC6M</name>
<description>Output compare 6 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC6PE</name>
<description>Output compare 6 preload enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC6FE</name>
<description>Output compare 6 fast enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC5CE</name>
<description>Output compare 5 clear enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC5M</name>
<description>Output compare 5 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC5PE</name>
<description>Output compare 5 preload enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC5FE</name>
<description>Output compare 5 fast enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DTR2</name>
<displayName>DTR2</displayName>
<description>timer Deadtime Register 2</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DTPE</name>
<description>Deadtime Preload Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTAE</name>
<description>Deadtime Asymmetric Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTGF</name>
<description>Dead-time falling edge generator setup</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ECR</name>
<displayName>ECR</displayName>
<description>DMA control register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IE</name>
<description>Index Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDIR</name>
<description>Index Direction</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IBLK</name>
<description>Index Blanking</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FIDX</name>
<description>First Index</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IPOS</name>
<description>Index Positioning</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PW</name>
<description>Pulse width</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PWPRSC</name>
<description>Pulse Width prescaler</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TISEL</name>
<displayName>TISEL</displayName>
<description>TIM timer input selection register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TI1SEL</name>
<description>TI1[0] to TI1[15] input selection</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TI2SEL</name>
<description>TI2[0] to TI2[15] input selection</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TI3SEL</name>
<description>TI3[0] to TI3[15] input selection</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TI4SEL</name>
<description>TI4[0] to TI4[15] input selection</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AF1</name>
<displayName>AF1</displayName>
<description>TIM alternate function option register 1</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ETRSEL</name>
<description>ETR source selection</description>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BKCMP4P</name>
<description>BRK COMP4 input polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP3P</name>
<description>BRK COMP3 input polarity</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2P</name>
<description>BRK COMP2 input polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1P</name>
<description>BRK COMP1 input polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKINP</name>
<description>BRK BKIN input polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP7E</name>
<description>BRK COMP7 enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP6E</name>
<description>BRK COMP6 enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP5E</name>
<description>BRK COMP5 enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP4E</name>
<description>BRK COMP4 enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP3E</name>
<description>BRK COMP3 enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2E</name>
<description>BRK COMP2 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1E</name>
<description>BRK COMP1 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKINE</name>
<description>BRK BKIN input enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AF2</name>
<displayName>AF2</displayName>
<description>TIM alternate function option register 2</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OCRSEL</name>
<description>OCREF_CLR source selection</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>BK2CMP4P</name>
<description>BRK2 COMP4 input polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP3P</name>
<description>BRK2 COMP3 input polarity</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP2P</name>
<description>BRK2 COMP2 input polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP1P</name>
<description>BRK2 COMP1 input polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2INP</name>
<description>BRK2 BKIN input polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP7E</name>
<description>BRK2 COMP7 enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP6E</name>
<description>BRK2 COMP6 enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP5E</name>
<description>BRK2 COMP5 enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP4E</name>
<description>BRK2 COMP4 enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP3E</name>
<description>BRK2 COMP3 enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP2E</name>
<description>BRK2 COMP2 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP1E</name>
<description>BRK2 COMP1 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKINE</name>
<description>BRK BKIN input enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCR</name>
<displayName>DCR</displayName>
<description>control register</description>
<addressOffset>0x3DC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DBL</name>
<description>DMA burst length</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DBA</name>
<description>DMA base address</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAR</name>
<displayName>DMAR</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x3E0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAB</name>
<description>DMA register for burst accesses</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="TIM2">
<name>TIM3</name>
<baseAddress>0x40000400</baseAddress>
<interrupt>
<name>TIM3</name>
<description>TIM3</description>
<value>29</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="TIM2">
<name>TIM4</name>
<baseAddress>0x40000800</baseAddress>
<interrupt>
<name>TIM4</name>
<description>TIM4</description>
<value>30</value>
</interrupt>
</peripheral>
<peripheral>
<name>TIM6</name>
<description>Basic-timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40001000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIM6_DACUNDER</name>
<description>TIM6_DACUNDER</description>
<value>54</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DITHEN</name>
<description>Dithering Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIFREMAP</name>
<description>UIF status bit remapping</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MMS</name>
<description>Master mode selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UIFCPY</name>
<description>UIF Copy</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CNT</name>
<description>Low counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Low Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="TIM6">
<name>TIM7</name>
<baseAddress>0x40001400</baseAddress>
<interrupt>
<name>TIM7</name>
<description>TIM7</description>
<value>55</value>
</interrupt>
</peripheral>
<peripheral>
<name>LPTIMER1</name>
<description>Low power timer</description>
<groupName>LPTIM</groupName>
<baseAddress>0x40007C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Interrupt and Status Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOWN</name>
<description>Counter direction change up to down</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UP</name>
<description>Counter direction change down to up</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARROK</name>
<description>Autoreload register update OK</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPOK</name>
<description>Compare register update OK</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTTRIG</name>
<description>External trigger edge event</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARRM</name>
<description>Autoreload match</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM</name>
<description>Compare match</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>Interrupt Clear Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOWNCF</name>
<description>Direction change to down Clear Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPCF</name>
<description>Direction change to UP Clear Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARROKCF</name>
<description>Autoreload register update OK Clear Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPOKCF</name>
<description>Compare register update OK Clear Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTTRIGCF</name>
<description>External trigger valid edge Clear Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARRMCF</name>
<description>Autoreload match Clear Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPMCF</name>
<description>compare match Clear Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>Interrupt Enable Register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOWNIE</name>
<description>Direction change to down Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPIE</name>
<description>Direction change to UP Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARROKIE</name>
<description>Autoreload register update OK Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPOKIE</name>
<description>Compare register update OK Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTTRIGIE</name>
<description>External trigger valid edge Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARRMIE</name>
<description>Autoreload match Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPMIE</name>
<description>Compare match Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFGR</name>
<displayName>CFGR</displayName>
<description>Configuration Register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ENC</name>
<description>Encoder mode enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COUNTMODE</name>
<description>counter mode enabled</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRELOAD</name>
<description>Registers update mode</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAVPOL</name>
<description>Waveform shape polarity</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAVE</name>
<description>Waveform shape</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMOUT</name>
<description>Timeout enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRIGEN</name>
<description>Trigger enable and polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TRIGSEL</name>
<description>Trigger selector</description>
<bitOffset>13</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PRESC</name>
<description>Clock prescaler</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TRGFLT</name>
<description>Configurable digital filter for trigger</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKFLT</name>
<description>Configurable digital filter for external clock</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKPOL</name>
<description>Clock Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKSEL</name>
<description>Clock selector</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Control Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RSTARE</name>
<description>RSTARE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COUNTRST</name>
<description>COUNTRST</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNTSTRT</name>
<description>Timer start in continuous mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SNGSTRT</name>
<description>LPTIM start in single mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ENABLE</name>
<description>LPTIM Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP</name>
<displayName>CMP</displayName>
<description>Compare Register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP</name>
<description>Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>Autoreload Register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Auto reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>Counter Register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OR</name>
<displayName>OR</displayName>
<description>option register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IN1</name>
<description>IN1</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN2</name>
<description>IN2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN1_2_1</name>
<description>IN1_2_1</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IN2_2_1</name>
<description>IN2_2_1</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>USART1</name>
<description>Universal synchronous asynchronous receiver transmitter</description>
<groupName>USART</groupName>
<baseAddress>0x40013800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>USART1</name>
<description>USART1</description>
<value>37</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>Control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXFFIE</name>
<description>RXFFIE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFEIE</name>
<description>TXFEIE</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOEN</name>
<description>FIFOEN</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M1</name>
<description>M1</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBIE</name>
<description>End of Block interrupt enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOIE</name>
<description>Receiver timeout interrupt enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT4</name>
<description>Driver Enable assertion time</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT3</name>
<description>DEAT3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT2</name>
<description>DEAT2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT1</name>
<description>DEAT1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT0</name>
<description>DEAT0</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT4</name>
<description>Driver Enable de-assertion time</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT3</name>
<description>DEDT3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT2</name>
<description>DEDT2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT1</name>
<description>DEDT1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT0</name>
<description>DEDT0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVER8</name>
<description>Oversampling mode</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMIE</name>
<description>Character match interrupt enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MME</name>
<description>Mute mode enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M0</name>
<description>Word length</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAKE</name>
<description>Receiver wakeup method</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCE</name>
<description>Parity control enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PS</name>
<description>Parity selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEIE</name>
<description>PE interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEIE</name>
<description>interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transmission complete interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNEIE</name>
<description>RXNE interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEIE</name>
<description>IDLE interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE</name>
<description>Transmitter enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RE</name>
<description>Receiver enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UESM</name>
<description>USART enable in Stop mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UE</name>
<description>USART enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>Control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADD4_7</name>
<description>Address of the USART node</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADD0_3</name>
<description>Address of the USART node</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RTOEN</name>
<description>Receiver timeout enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRMOD1</name>
<description>Auto baud rate mode</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRMOD0</name>
<description>ABRMOD0</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABREN</name>
<description>Auto baud rate enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSBFIRST</name>
<description>Most significant bit first</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAINV</name>
<description>Binary data inversion</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXINV</name>
<description>TX pin active level inversion</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXINV</name>
<description>RX pin active level inversion</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWAP</name>
<description>Swap TX/RX pins</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINEN</name>
<description>LIN mode enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOP</name>
<description>STOP bits</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CLKEN</name>
<description>Clock enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPOL</name>
<description>Clock polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPHA</name>
<description>Clock phase</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBCL</name>
<description>Last bit clock pulse</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDIE</name>
<description>LIN break detection interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDL</name>
<description>LIN break detection length</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDM7</name>
<description>7-bit Address Detection/4-bit Address Detection</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIS_NSS</name>
<description>DIS_NSS</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLVEN</name>
<description>SLVEN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR3</name>
<displayName>CR3</displayName>
<description>Control register 3</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFTCFG</name>
<description>TXFTCFG</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RXFTIE</name>
<description>RXFTIE</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFTCFG</name>
<description>RXFTCFG</description>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TCBGTIE</name>
<description>TCBGTIE</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFTIE</name>
<description>TXFTIE</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUFIE</name>
<description>Wakeup from Stop mode interrupt enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUS</name>
<description>Wakeup from Stop mode interrupt flag selection</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SCARCNT</name>
<description>Smartcard auto-retry count</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DEP</name>
<description>Driver enable polarity selection</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEM</name>
<description>Driver enable mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DDRE</name>
<description>DMA Disable on Reception Error</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRDIS</name>
<description>Overrun Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ONEBIT</name>
<description>One sample bit method enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIE</name>
<description>CTS interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSE</name>
<description>CTS enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTSE</name>
<description>RTS enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAT</name>
<description>DMA enable transmitter</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAR</name>
<description>DMA enable receiver</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCEN</name>
<description>Smartcard mode enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>Smartcard NACK enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDSEL</name>
<description>Half-duplex selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRLP</name>
<description>Ir low-power</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IREN</name>
<description>Ir mode enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EIE</name>
<description>Error interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>Baud rate register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIV_Mantissa</name>
<description>DIV_Mantissa</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>DIV_Fraction</name>
<description>DIV_Fraction</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GTPR</name>
<displayName>GTPR</displayName>
<description>Guard time and prescaler register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GT</name>
<description>Guard time value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RTOR</name>
<displayName>RTOR</displayName>
<description>Receiver timeout register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLEN</name>
<description>Block Length</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RTO</name>
<description>Receiver timeout value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>RQR</name>
<displayName>RQR</displayName>
<description>Request register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFRQ</name>
<description>Transmit data flush request</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFRQ</name>
<description>Receive data flush request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMRQ</name>
<description>Mute mode request</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBKRQ</name>
<description>Send break request</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRRQ</name>
<description>Auto baud rate request</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Interrupt &amp; status register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFT</name>
<description>TXFT</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFT</name>
<description>RXFT</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCBGT</name>
<description>TCBGT</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFF</name>
<description>RXFF</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFE</name>
<description>TXFE</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REACK</name>
<description>REACK</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEACK</name>
<description>TEACK</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUF</name>
<description>WUF</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWU</name>
<description>RWU</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBKF</name>
<description>SBKF</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMF</name>
<description>CMF</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSY</name>
<description>BUSY</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRF</name>
<description>ABRF</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRE</name>
<description>ABRE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDR</name>
<description>UDR</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBF</name>
<description>EOBF</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOF</name>
<description>RTOF</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTS</name>
<description>CTS</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIF</name>
<description>CTSIF</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDF</name>
<description>LBDF</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXE</name>
<description>TXE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC</name>
<description>TC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNE</name>
<description>RXNE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE</name>
<description>IDLE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORE</name>
<description>ORE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NF</name>
<description>NF</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FE</name>
<description>FE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PE</name>
<description>PE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>Interrupt flag clear register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WUCF</name>
<description>Wakeup from Stop mode clear flag</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMCF</name>
<description>Character match clear flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDRCF</name>
<description>UDRCF</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBCF</name>
<description>End of block clear flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOCF</name>
<description>Receiver timeout clear flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSCF</name>
<description>CTS clear flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDCF</name>
<description>LIN break detection clear flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCBGTCF</name>
<description>TCBGTCF</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCF</name>
<description>Transmission complete clear flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFECF</name>
<description>TXFECF</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLECF</name>
<description>Idle line detected clear flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORECF</name>
<description>Overrun error clear flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NCF</name>
<description>Noise detected clear flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FECF</name>
<description>Framing error clear flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECF</name>
<description>Parity error clear flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RDR</name>
<displayName>RDR</displayName>
<description>Receive data register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RDR</name>
<description>Receive data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>TDR</name>
<displayName>TDR</displayName>
<description>Transmit data register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TDR</name>
<description>Transmit data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRESC</name>
<displayName>PRESC</displayName>
<description>USART prescaler register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRESCALER</name>
<description>PRESCALER</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="USART1">
<name>USART2</name>
<baseAddress>0x40004400</baseAddress>
<interrupt>
<name>USART2</name>
<description>USART2</description>
<value>38</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="USART1">
<name>USART3</name>
<baseAddress>0x40004800</baseAddress>
<interrupt>
<name>USART3</name>
<description>USART3</description>
<value>39</value>
</interrupt>
</peripheral>
<peripheral>
<name>UART4</name>
<description>Universal synchronous asynchronous receiver transmitter</description>
<groupName>USART</groupName>
<baseAddress>0x40004C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UART4</name>
<description>UART4</description>
<value>52</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>Control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXFFIE</name>
<description>RXFFIE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFEIE</name>
<description>TXFEIE</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOEN</name>
<description>FIFOEN</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M1</name>
<description>M1</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBIE</name>
<description>End of Block interrupt enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOIE</name>
<description>Receiver timeout interrupt enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT4</name>
<description>Driver Enable assertion time</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT3</name>
<description>DEAT3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT2</name>
<description>DEAT2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT1</name>
<description>DEAT1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT0</name>
<description>DEAT0</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT4</name>
<description>Driver Enable de-assertion time</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT3</name>
<description>DEDT3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT2</name>
<description>DEDT2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT1</name>
<description>DEDT1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT0</name>
<description>DEDT0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVER8</name>
<description>Oversampling mode</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMIE</name>
<description>Character match interrupt enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MME</name>
<description>Mute mode enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M0</name>
<description>Word length</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAKE</name>
<description>Receiver wakeup method</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCE</name>
<description>Parity control enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PS</name>
<description>Parity selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEIE</name>
<description>PE interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEIE</name>
<description>interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transmission complete interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNEIE</name>
<description>RXNE interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEIE</name>
<description>IDLE interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE</name>
<description>Transmitter enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RE</name>
<description>Receiver enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UESM</name>
<description>USART enable in Stop mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UE</name>
<description>USART enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>Control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADD4_7</name>
<description>Address of the USART node</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADD0_3</name>
<description>Address of the USART node</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RTOEN</name>
<description>Receiver timeout enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRMOD1</name>
<description>Auto baud rate mode</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRMOD0</name>
<description>ABRMOD0</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABREN</name>
<description>Auto baud rate enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSBFIRST</name>
<description>Most significant bit first</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAINV</name>
<description>Binary data inversion</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXINV</name>
<description>TX pin active level inversion</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXINV</name>
<description>RX pin active level inversion</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWAP</name>
<description>Swap TX/RX pins</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINEN</name>
<description>LIN mode enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOP</name>
<description>STOP bits</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CLKEN</name>
<description>Clock enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPOL</name>
<description>Clock polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPHA</name>
<description>Clock phase</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBCL</name>
<description>Last bit clock pulse</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDIE</name>
<description>LIN break detection interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDL</name>
<description>LIN break detection length</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDM7</name>
<description>7-bit Address Detection/4-bit Address Detection</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIS_NSS</name>
<description>DIS_NSS</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLVEN</name>
<description>SLVEN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR3</name>
<displayName>CR3</displayName>
<description>Control register 3</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFTCFG</name>
<description>TXFTCFG</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RXFTIE</name>
<description>RXFTIE</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFTCFG</name>
<description>RXFTCFG</description>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TCBGTIE</name>
<description>TCBGTIE</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFTIE</name>
<description>TXFTIE</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUFIE</name>
<description>Wakeup from Stop mode interrupt enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUS</name>
<description>Wakeup from Stop mode interrupt flag selection</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SCARCNT</name>
<description>Smartcard auto-retry count</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DEP</name>
<description>Driver enable polarity selection</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEM</name>
<description>Driver enable mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DDRE</name>
<description>DMA Disable on Reception Error</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRDIS</name>
<description>Overrun Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ONEBIT</name>
<description>One sample bit method enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIE</name>
<description>CTS interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSE</name>
<description>CTS enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTSE</name>
<description>RTS enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAT</name>
<description>DMA enable transmitter</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAR</name>
<description>DMA enable receiver</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCEN</name>
<description>Smartcard mode enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>Smartcard NACK enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDSEL</name>
<description>Half-duplex selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRLP</name>
<description>Ir low-power</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IREN</name>
<description>Ir mode enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EIE</name>
<description>Error interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>Baud rate register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIV_Mantissa</name>
<description>DIV_Mantissa</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>DIV_Fraction</name>
<description>DIV_Fraction</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GTPR</name>
<displayName>GTPR</displayName>
<description>Guard time and prescaler register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GT</name>
<description>Guard time value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RTOR</name>
<displayName>RTOR</displayName>
<description>Receiver timeout register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLEN</name>
<description>Block Length</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RTO</name>
<description>Receiver timeout value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>RQR</name>
<displayName>RQR</displayName>
<description>Request register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFRQ</name>
<description>Transmit data flush request</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFRQ</name>
<description>Receive data flush request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMRQ</name>
<description>Mute mode request</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBKRQ</name>
<description>Send break request</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRRQ</name>
<description>Auto baud rate request</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Interrupt &amp; status register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x000000C0</resetValue>
<fields>
<field>
<name>TXFT</name>
<description>TXFT</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFT</name>
<description>RXFT</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCBGT</name>
<description>TCBGT</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFF</name>
<description>RXFF</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFE</name>
<description>TXFE</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REACK</name>
<description>REACK</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEACK</name>
<description>TEACK</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUF</name>
<description>WUF</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWU</name>
<description>RWU</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBKF</name>
<description>SBKF</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMF</name>
<description>CMF</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSY</name>
<description>BUSY</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRF</name>
<description>ABRF</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRE</name>
<description>ABRE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDR</name>
<description>UDR</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBF</name>
<description>EOBF</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOF</name>
<description>RTOF</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTS</name>
<description>CTS</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIF</name>
<description>CTSIF</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDF</name>
<description>LBDF</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXE</name>
<description>TXE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC</name>
<description>TC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNE</name>
<description>RXNE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE</name>
<description>IDLE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORE</name>
<description>ORE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NF</name>
<description>NF</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FE</name>
<description>FE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PE</name>
<description>PE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>Interrupt flag clear register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WUCF</name>
<description>Wakeup from Stop mode clear flag</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMCF</name>
<description>Character match clear flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDRCF</name>
<description>UDRCF</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBCF</name>
<description>End of block clear flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOCF</name>
<description>Receiver timeout clear flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSCF</name>
<description>CTS clear flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDCF</name>
<description>LIN break detection clear flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCBGTCF</name>
<description>TCBGTCF</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCF</name>
<description>Transmission complete clear flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFECF</name>
<description>TXFECF</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLECF</name>
<description>Idle line detected clear flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORECF</name>
<description>Overrun error clear flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NCF</name>
<description>Noise detected clear flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FECF</name>
<description>Framing error clear flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECF</name>
<description>Parity error clear flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RDR</name>
<displayName>RDR</displayName>
<description>Receive data register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RDR</name>
<description>Receive data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>TDR</name>
<displayName>TDR</displayName>
<description>Transmit data register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TDR</name>
<description>Transmit data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRESC</name>
<displayName>PRESC</displayName>
<description>USART prescaler register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRESCALER</name>
<description>PRESCALER</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>LPUART1</name>
<description>Universal synchronous asynchronous receiver transmitter</description>
<groupName>USART</groupName>
<baseAddress>0x40008000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>LPTIM1</name>
<description>LPTIM1</description>
<value>49</value>
</interrupt>
<interrupt>
<name>LPUART</name>
<description>LPUART</description>
<value>91</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>Control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>RXFFIE</name>
<description>RXFFIE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFEIE</name>
<description>TXFEIE</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOEN</name>
<description>FIFOEN</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M1</name>
<description>Word length</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT4</name>
<description>Driver Enable assertion time</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT3</name>
<description>DEAT3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT2</name>
<description>DEAT2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT1</name>
<description>DEAT1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT0</name>
<description>DEAT0</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT4</name>
<description>Driver Enable de-assertion time</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT3</name>
<description>DEDT3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT2</name>
<description>DEDT2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT1</name>
<description>DEDT1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT0</name>
<description>DEDT0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMIE</name>
<description>Character match interrupt enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MME</name>
<description>Mute mode enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M0</name>
<description>Word length</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAKE</name>
<description>Receiver wakeup method</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCE</name>
<description>Parity control enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PS</name>
<description>Parity selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEIE</name>
<description>PE interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEIE</name>
<description>interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transmission complete interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNEIE</name>
<description>RXNE interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEIE</name>
<description>IDLE interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE</name>
<description>Transmitter enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RE</name>
<description>Receiver enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UESM</name>
<description>USART enable in Stop mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UE</name>
<description>USART enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>Control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ADD4_7</name>
<description>Address of the USART node</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADD0_3</name>
<description>Address of the USART node</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MSBFIRST</name>
<description>Most significant bit first</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAINV</name>
<description>Binary data inversion</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXINV</name>
<description>TX pin active level inversion</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXINV</name>
<description>RX pin active level inversion</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWAP</name>
<description>Swap TX/RX pins</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOP</name>
<description>STOP bits</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ADDM7</name>
<description>7-bit Address Detection/4-bit Address Detection</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR3</name>
<displayName>CR3</displayName>
<description>Control register 3</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TXFTCFG</name>
<description>TXFTCFG</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RXFTIE</name>
<description>RXFTIE</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFTCFG</name>
<description>RXFTCFG</description>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TXFTIE</name>
<description>TXFTIE</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUFIE</name>
<description>Wakeup from Stop mode interrupt enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUS</name>
<description>Wakeup from Stop mode interrupt flag selection</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DEP</name>
<description>Driver enable polarity selection</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEM</name>
<description>Driver enable mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DDRE</name>
<description>DMA Disable on Reception Error</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRDIS</name>
<description>Overrun Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIE</name>
<description>CTS interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSE</name>
<description>CTS enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTSE</name>
<description>RTS enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAT</name>
<description>DMA enable transmitter</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAR</name>
<description>DMA enable receiver</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDSEL</name>
<description>Half-duplex selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EIE</name>
<description>Error interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>Baud rate register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BRR</name>
<description>BRR</description>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>RQR</name>
<displayName>RQR</displayName>
<description>Request register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TXFRQ</name>
<description>TXFRQ</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFRQ</name>
<description>Receive data flush request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMRQ</name>
<description>Mute mode request</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBKRQ</name>
<description>Send break request</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Interrupt &amp; status register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00C0</resetValue>
<fields>
<field>
<name>TXFT</name>
<description>TXFT</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFT</name>
<description>RXFT</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFF</name>
<description>RXFF</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFE</name>
<description>TXFE</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REACK</name>
<description>REACK</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEACK</name>
<description>TEACK</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUF</name>
<description>WUF</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWU</name>
<description>RWU</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBKF</name>
<description>SBKF</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMF</name>
<description>CMF</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSY</name>
<description>BUSY</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTS</name>
<description>CTS</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIF</name>
<description>CTSIF</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXE</name>
<description>TXE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC</name>
<description>TC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNE</name>
<description>RXNE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE</name>
<description>IDLE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORE</name>
<description>ORE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NF</name>
<description>NF</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FE</name>
<description>FE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PE</name>
<description>PE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>Interrupt flag clear register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>WUCF</name>
<description>Wakeup from Stop mode clear flag</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMCF</name>
<description>Character match clear flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSCF</name>
<description>CTS clear flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCF</name>
<description>Transmission complete clear flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLECF</name>
<description>Idle line detected clear flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORECF</name>
<description>Overrun error clear flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NCF</name>
<description>Noise detected clear flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FECF</name>
<description>Framing error clear flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECF</name>
<description>Parity error clear flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RDR</name>
<displayName>RDR</displayName>
<description>Receive data register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>RDR</name>
<description>Receive data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>TDR</name>
<displayName>TDR</displayName>
<description>Transmit data register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TDR</name>
<description>Transmit data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRESC</name>
<displayName>PRESC</displayName>
<description>Prescaler register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PRESCALER</name>
<description>PRESCALER</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SPI1</name>
<description>Serial peripheral interface/Inter-IC sound</description>
<groupName>SPI</groupName>
<baseAddress>0x40013000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SPI1</name>
<description>SPI1</description>
<value>35</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BIDIMODE</name>
<description>Bidirectional data mode enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIDIOE</name>
<description>Output enable in bidirectional mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCEN</name>
<description>Hardware CRC calculation enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCNEXT</name>
<description>CRC transfer next</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DFF</name>
<description>Data frame format</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXONLY</name>
<description>Receive only</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SSM</name>
<description>Software slave management</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SSI</name>
<description>Internal slave select</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSBFIRST</name>
<description>Frame format</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPE</name>
<description>SPI enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR</name>
<description>Baud rate control</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MSTR</name>
<description>Master selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPOL</name>
<description>Clock polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPHA</name>
<description>Clock phase</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000700</resetValue>
<fields>
<field>
<name>RXDMAEN</name>
<description>Rx buffer DMA enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXDMAEN</name>
<description>Tx buffer DMA enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SSOE</name>
<description>SS output enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NSSP</name>
<description>NSS pulse management</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRF</name>
<description>Frame format</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRIE</name>
<description>Error interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNEIE</name>
<description>RX buffer not empty interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEIE</name>
<description>Tx buffer empty interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DS</name>
<description>Data size</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FRXTH</name>
<description>FIFO reception threshold</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LDMA_RX</name>
<description>Last DMA transfer for reception</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LDMA_TX</name>
<description>Last DMA transfer for transmission</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x00000002</resetValue>
<fields>
<field>
<name>RXNE</name>
<description>Receive buffer not empty</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXE</name>
<description>Transmit buffer empty</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CRCERR</name>
<description>CRC error flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MODF</name>
<description>Mode fault</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVR</name>
<description>Overrun flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BSY</name>
<description>Busy flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TIFRFE</name>
<description>TI frame format error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FRLVL</name>
<description>FIFO reception level</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FTLVL</name>
<description>FIFO transmission level</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>data register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DR</name>
<description>Data register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CRCPR</name>
<displayName>CRCPR</displayName>
<description>CRC polynomial register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000007</resetValue>
<fields>
<field>
<name>CRCPOLY</name>
<description>CRC polynomial register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXCRCR</name>
<displayName>RXCRCR</displayName>
<description>RX CRC register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RxCRC</name>
<description>Rx CRC register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXCRCR</name>
<displayName>TXCRCR</displayName>
<description>TX CRC register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TxCRC</name>
<description>Tx CRC register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>I2SCFGR</name>
<displayName>I2SCFGR</displayName>
<description>configuration register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CHLEN</name>
<description>CHLEN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DATLEN</name>
<description>DATLEN</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKPOL</name>
<description>CKPOL</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2SSTD</name>
<description>I2SSTD</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCMSYNC</name>
<description>PCMSYNC</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2SCFG</name>
<description>I2SCFG</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>I2SE</name>
<description>I2SE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2SMOD</name>
<description>I2SMOD</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>I2SPR</name>
<displayName>I2SPR</displayName>
<description>prescaler register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000002</resetValue>
<fields>
<field>
<name>I2SDIV</name>
<description>I2SDIV</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ODD</name>
<description>ODD</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCKOE</name>
<description>MCKOE</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="SPI1">
<name>SPI3</name>
<baseAddress>0x40003C00</baseAddress>
<interrupt>
<name>SPI3</name>
<description>SPI3</description>
<value>51</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="SPI1">
<name>SPI2</name>
<baseAddress>0x40003800</baseAddress>
<interrupt>
<name>SPI2</name>
<description>SPI2</description>
<value>36</value>
</interrupt>
</peripheral>
<peripheral>
<name>EXTI</name>
<description>External interrupt/event controller</description>
<groupName>EXTI</groupName>
<baseAddress>0x40010400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PVD_PVM</name>
<description>PVD through EXTI line detection</description>
<value>1</value>
</interrupt>
<interrupt>
<name>EXTI0</name>
<description>EXTI Line0 interrupt</description>
<value>6</value>
</interrupt>
<interrupt>
<name>EXTI1</name>
<description>EXTI Line1 interrupt</description>
<value>7</value>
</interrupt>
<interrupt>
<name>EXTI2</name>
<description>EXTI Line2 interrupt</description>
<value>8</value>
</interrupt>
<interrupt>
<name>EXTI3</name>
<description>EXTI Line3 interrupt</description>
<value>9</value>
</interrupt>
<interrupt>
<name>EXTI4</name>
<description>EXTI Line4 interrupt</description>
<value>10</value>
</interrupt>
<interrupt>
<name>USB_HP</name>
<description>USB_HP</description>
<value>19</value>
</interrupt>
<interrupt>
<name>USB_LP</name>
<description>USB_LP</description>
<value>20</value>
</interrupt>
<interrupt>
<name>EXTI9_5</name>
<description>EXTI9_5</description>
<value>23</value>
</interrupt>
<interrupt>
<name>EXTI15_10</name>
<description>EXTI15_10</description>
<value>40</value>
</interrupt>
<interrupt>
<name>USBWakeUP</name>
<description>USBWakeUP</description>
<value>42</value>
</interrupt>
<interrupt>
<name>CRS</name>
<description>CRS</description>
<value>75</value>
</interrupt>
<registers>
<register>
<name>IMR1</name>
<displayName>IMR1</displayName>
<description>Interrupt mask register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFF820000</resetValue>
<fields>
<field>
<name>IM0</name>
<description>Interrupt Mask on line 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM1</name>
<description>Interrupt Mask on line 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM2</name>
<description>Interrupt Mask on line 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM3</name>
<description>Interrupt Mask on line 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM4</name>
<description>Interrupt Mask on line 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM5</name>
<description>Interrupt Mask on line 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM6</name>
<description>Interrupt Mask on line 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM7</name>
<description>Interrupt Mask on line 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM8</name>
<description>Interrupt Mask on line 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM9</name>
<description>Interrupt Mask on line 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM10</name>
<description>Interrupt Mask on line 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM11</name>
<description>Interrupt Mask on line 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM12</name>
<description>Interrupt Mask on line 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM13</name>
<description>Interrupt Mask on line 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM14</name>
<description>Interrupt Mask on line 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM15</name>
<description>Interrupt Mask on line 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM16</name>
<description>Interrupt Mask on line 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM17</name>
<description>Interrupt Mask on line 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM18</name>
<description>Interrupt Mask on line 18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM19</name>
<description>Interrupt Mask on line 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM20</name>
<description>Interrupt Mask on line 20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM21</name>
<description>Interrupt Mask on line 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM22</name>
<description>Interrupt Mask on line 22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM23</name>
<description>Interrupt Mask on line 23</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM24</name>
<description>Interrupt Mask on line 24</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM25</name>
<description>Interrupt Mask on line 25</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM26</name>
<description>Interrupt Mask on line 26</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM27</name>
<description>Interrupt Mask on line 27</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM28</name>
<description>Interrupt Mask on line 28</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM29</name>
<description>Interrupt Mask on line 29</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM30</name>
<description>Interrupt Mask on line 30</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM31</name>
<description>Interrupt Mask on line 31</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EMR1</name>
<displayName>EMR1</displayName>
<description>Event mask register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EM0</name>
<description>Event Mask on line 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM1</name>
<description>Event Mask on line 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM2</name>
<description>Event Mask on line 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM3</name>
<description>Event Mask on line 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM4</name>
<description>Event Mask on line 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM5</name>
<description>Event Mask on line 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM6</name>
<description>Event Mask on line 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM7</name>
<description>Event Mask on line 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM8</name>
<description>Event Mask on line 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM9</name>
<description>Event Mask on line 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM10</name>
<description>Event Mask on line 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM11</name>
<description>Event Mask on line 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM12</name>
<description>Event Mask on line 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM13</name>
<description>Event Mask on line 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM14</name>
<description>Event Mask on line 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM15</name>
<description>Event Mask on line 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM16</name>
<description>Event Mask on line 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM17</name>
<description>Event Mask on line 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM18</name>
<description>Event Mask on line 18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM19</name>
<description>Event Mask on line 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM20</name>
<description>Event Mask on line 20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM21</name>
<description>Event Mask on line 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM22</name>
<description>Event Mask on line 22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM23</name>
<description>Event Mask on line 23</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM24</name>
<description>Event Mask on line 24</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM25</name>
<description>Event Mask on line 25</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM26</name>
<description>Event Mask on line 26</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM27</name>
<description>Event Mask on line 27</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM28</name>
<description>Event Mask on line 28</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM29</name>
<description>Event Mask on line 29</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM30</name>
<description>Event Mask on line 30</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM31</name>
<description>Event Mask on line 31</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RTSR1</name>
<displayName>RTSR1</displayName>
<description>Rising Trigger selection register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RT0</name>
<description>Rising trigger event configuration of line 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT1</name>
<description>Rising trigger event configuration of line 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT2</name>
<description>Rising trigger event configuration of line 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT3</name>
<description>Rising trigger event configuration of line 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT4</name>
<description>Rising trigger event configuration of line 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT5</name>
<description>Rising trigger event configuration of line 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT6</name>
<description>Rising trigger event configuration of line 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT7</name>
<description>Rising trigger event configuration of line 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT8</name>
<description>Rising trigger event configuration of line 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT9</name>
<description>Rising trigger event configuration of line 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT10</name>
<description>Rising trigger event configuration of line 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT11</name>
<description>Rising trigger event configuration of line 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT12</name>
<description>Rising trigger event configuration of line 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT13</name>
<description>Rising trigger event configuration of line 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT14</name>
<description>Rising trigger event configuration of line 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT15</name>
<description>Rising trigger event configuration of line 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT16</name>
<description>Rising trigger event configuration of line 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT18</name>
<description>Rising trigger event configuration of line 18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT19</name>
<description>Rising trigger event configuration of line 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT20</name>
<description>Rising trigger event configuration of line 20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT21</name>
<description>Rising trigger event configuration of line 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT22</name>
<description>Rising trigger event configuration of line 22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT</name>
<description>RT</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>FTSR1</name>
<displayName>FTSR1</displayName>
<description>Falling Trigger selection register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FT0</name>
<description>Falling trigger event configuration of line 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT1</name>
<description>Falling trigger event configuration of line 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT2</name>
<description>Falling trigger event configuration of line 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT3</name>
<description>Falling trigger event configuration of line 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT4</name>
<description>Falling trigger event configuration of line 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT5</name>
<description>Falling trigger event configuration of line 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT6</name>
<description>Falling trigger event configuration of line 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT7</name>
<description>Falling trigger event configuration of line 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT8</name>
<description>Falling trigger event configuration of line 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT9</name>
<description>Falling trigger event configuration of line 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT10</name>
<description>Falling trigger event configuration of line 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT11</name>
<description>Falling trigger event configuration of line 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT12</name>
<description>Falling trigger event configuration of line 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT13</name>
<description>Falling trigger event configuration of line 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT14</name>
<description>Falling trigger event configuration of line 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT15</name>
<description>Falling trigger event configuration of line 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT16</name>
<description>Falling trigger event configuration of line 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT18</name>
<description>Falling trigger event configuration of line 18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT19</name>
<description>Falling trigger event configuration of line 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT20</name>
<description>Falling trigger event configuration of line 20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT21</name>
<description>Falling trigger event configuration of line 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT22</name>
<description>Falling trigger event configuration of line 22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SWIER1</name>
<displayName>SWIER1</displayName>
<description>Software interrupt event register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWI0</name>
<description>Software Interrupt on line 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI1</name>
<description>Software Interrupt on line 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI2</name>
<description>Software Interrupt on line 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI3</name>
<description>Software Interrupt on line 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI4</name>
<description>Software Interrupt on line 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI5</name>
<description>Software Interrupt on line 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI6</name>
<description>Software Interrupt on line 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI7</name>
<description>Software Interrupt on line 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI8</name>
<description>Software Interrupt on line 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI9</name>
<description>Software Interrupt on line 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI10</name>
<description>Software Interrupt on line 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI11</name>
<description>Software Interrupt on line 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI12</name>
<description>Software Interrupt on line 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI13</name>
<description>Software Interrupt on line 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI14</name>
<description>Software Interrupt on line 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI15</name>
<description>Software Interrupt on line 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI16</name>
<description>Software Interrupt on line 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI18</name>
<description>Software Interrupt on line 18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI19</name>
<description>Software Interrupt on line 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI20</name>
<description>Software Interrupt on line 20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI21</name>
<description>Software Interrupt on line 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI22</name>
<description>Software Interrupt on line 22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PR1</name>
<displayName>PR1</displayName>
<description>Pending register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PIF0</name>
<description>Pending bit 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF1</name>
<description>Pending bit 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF2</name>
<description>Pending bit 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF3</name>
<description>Pending bit 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF4</name>
<description>Pending bit 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF5</name>
<description>Pending bit 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF6</name>
<description>Pending bit 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF7</name>
<description>Pending bit 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF8</name>
<description>Pending bit 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF9</name>
<description>Pending bit 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF10</name>
<description>Pending bit 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF11</name>
<description>Pending bit 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF12</name>
<description>Pending bit 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF13</name>
<description>Pending bit 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF14</name>
<description>Pending bit 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF15</name>
<description>Pending bit 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF16</name>
<description>Pending bit 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF18</name>
<description>Pending bit 18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF19</name>
<description>Pending bit 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF20</name>
<description>Pending bit 20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF21</name>
<description>Pending bit 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF22</name>
<description>Pending bit 22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR2</name>
<displayName>IMR2</displayName>
<description>Interrupt mask register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFF87</resetValue>
<fields>
<field>
<name>IM32</name>
<description>Interrupt Mask on external/internal line 32</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM33</name>
<description>Interrupt Mask on external/internal line 33</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM34</name>
<description>Interrupt Mask on external/internal line 34</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM35</name>
<description>Interrupt Mask on external/internal line 35</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM36</name>
<description>Interrupt Mask on external/internal line 36</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM37</name>
<description>Interrupt Mask on external/internal line 37</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM38</name>
<description>Interrupt Mask on external/internal line 38</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM39</name>
<description>Interrupt Mask on external/internal line 39</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM40</name>
<description>Interrupt Mask on external/internal line 40</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM41</name>
<description>Interrupt Mask on external/internal line 41</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM42</name>
<description>Interrupt Mask on external/internal line 42</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IM43</name>
<description>Interrupt Mask on external/internal line 43</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EMR2</name>
<displayName>EMR2</displayName>
<description>Event mask register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EM32</name>
<description>Event mask on external/internal line 32</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM33</name>
<description>Event mask on external/internal line 33</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM34</name>
<description>Event mask on external/internal line 34</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM35</name>
<description>Event mask on external/internal line 35</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM36</name>
<description>Event mask on external/internal line 36</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM37</name>
<description>Event mask on external/internal line 37</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM38</name>
<description>Event mask on external/internal line 38</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM39</name>
<description>Event mask on external/internal line 39</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EM40</name>
<description>Event mask on external/internal line 40</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RTSR2</name>
<displayName>RTSR2</displayName>
<description>Rising Trigger selection register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RT32</name>
<description>Rising trigger event configuration bit of line 32</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT33</name>
<description>Rising trigger event configuration bit of line 32</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT38</name>
<description>Rising trigger event configuration bit of line 38</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT39</name>
<description>Rising trigger event configuration bit of line 39</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT40</name>
<description>Rising trigger event configuration bit of line 40</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT41</name>
<description>Rising trigger event configuration bit of line 41</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FTSR2</name>
<displayName>FTSR2</displayName>
<description>Falling Trigger selection register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FT35</name>
<description>Falling trigger event configuration bit of line 35</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT36</name>
<description>Falling trigger event configuration bit of line 36</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT37</name>
<description>Falling trigger event configuration bit of line 37</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT38</name>
<description>Falling trigger event configuration bit of line 38</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SWIER2</name>
<displayName>SWIER2</displayName>
<description>Software interrupt event register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWI35</name>
<description>Software interrupt on line 35</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI36</name>
<description>Software interrupt on line 36</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI37</name>
<description>Software interrupt on line 37</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI38</name>
<description>Software interrupt on line 38</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PR2</name>
<displayName>PR2</displayName>
<description>Pending register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PIF35</name>
<description>Pending interrupt flag on line 35</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF36</name>
<description>Pending interrupt flag on line 36</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF37</name>
<description>Pending interrupt flag on line 37</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF38</name>
<description>Pending interrupt flag on line 38</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RTC</name>
<description>Real-time clock</description>
<groupName>RTC</groupName>
<baseAddress>0x40002800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RTC_TAMP_CSS_LSE</name>
<description>RTC_TAMP_CSS_LSE</description>
<value>2</value>
</interrupt>
<interrupt>
<name>RTC_WKUP</name>
<description>RTC Wakeup timer</description>
<value>3</value>
</interrupt>
<interrupt>
<name>RTC_ALARM</name>
<description>RTC_ALARM</description>
<value>41</value>
</interrupt>
<registers>
<register>
<name>TR</name>
<displayName>TR</displayName>
<description>time register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PM</name>
<description>AM/PM notation</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HT</name>
<description>Hour tens in BCD format</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>HU</name>
<description>Hour units in BCD format</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MNT</name>
<description>Minute tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MNU</name>
<description>Minute units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ST</name>
<description>Second tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SU</name>
<description>Second units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>date register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00002101</resetValue>
<fields>
<field>
<name>YT</name>
<description>Year tens in BCD format</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>YU</name>
<description>Year units in BCD format</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>WDU</name>
<description>Week day units</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MT</name>
<description>Month tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MU</name>
<description>Month units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DT</name>
<description>Date tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DU</name>
<description>Date units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>SSR</name>
<displayName>SSR</displayName>
<description>sub second register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SS</name>
<description>Sub second value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICSR</name>
<displayName>ICSR</displayName>
<description>initialization and status register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<resetValue>0x00000007</resetValue>
<fields>
<field>
<name>ALRAWF</name>
<description>Alarm A write flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ALRBWF</name>
<description>Alarm B write flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>WUTWF</name>
<description>Wakeup timer write flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SHPF</name>
<description>Shift operation pending</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INITS</name>
<description>Initialization status flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RSF</name>
<description>Registers synchronization flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INITF</name>
<description>Initialization flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>INIT</name>
<description>Initialization mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RECALPF</name>
<description>Recalibration pending Flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PRER</name>
<displayName>PRER</displayName>
<description>prescaler register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x007F00FF</resetValue>
<fields>
<field>
<name>PREDIV_A</name>
<description>Asynchronous prescaler factor</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PREDIV_S</name>
<description>Synchronous prescaler factor</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>WUTR</name>
<displayName>WUTR</displayName>
<description>wakeup timer register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>WUT</name>
<description>Wakeup auto-reload value bits</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>control register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WCKSEL</name>
<description>Wakeup clock selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TSEDGE</name>
<description>Time-stamp event active edge</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REFCKON</name>
<description>Reference clock detection enable (50 or 60 Hz)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BYPSHAD</name>
<description>Bypass the shadow registers</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FMT</name>
<description>Hour format</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALRAE</name>
<description>Alarm A enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALRBE</name>
<description>Alarm B enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUTE</name>
<description>Wakeup timer enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSE</name>
<description>Time stamp enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALRAIE</name>
<description>Alarm A interrupt enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALRBIE</name>
<description>Alarm B interrupt enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUTIE</name>
<description>Wakeup timer interrupt enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSIE</name>
<description>Time-stamp interrupt enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADD1H</name>
<description>Add 1 hour (summer time change)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SUB1H</name>
<description>Subtract 1 hour (winter time change)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKP</name>
<description>Backup</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COSEL</name>
<description>Calibration output selection</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>POL</name>
<description>Output polarity</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSEL</name>
<description>Output selection</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COE</name>
<description>Calibration output enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITSE</name>
<description>timestamp on internal event enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMPTS</name>
<description>TAMPTS</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMPOE</name>
<description>TAMPOE</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMPALRM_PU</name>
<description>TAMPALRM_PU</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMPALRM_TYPE</name>
<description>TAMPALRM_TYPE</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT2EN</name>
<description>OUT2EN</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPR</name>
<displayName>WPR</displayName>
<description>write protection register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEY</name>
<description>Write protection key</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CALR</name>
<displayName>CALR</displayName>
<description>calibration register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CALP</name>
<description>Increase frequency of RTC by 488.5 ppm</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALW8</name>
<description>Use an 8-second calibration cycle period</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALW16</name>
<description>Use a 16-second calibration cycle period</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALM</name>
<description>Calibration minus</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHIFTR</name>
<displayName>SHIFTR</displayName>
<description>shift control register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADD1S</name>
<description>Add one second</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SUBFS</name>
<description>Subtract a fraction of a second</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>TSTR</name>
<displayName>TSTR</displayName>
<description>time stamp time register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SU</name>
<description>Second units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ST</name>
<description>Second tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MNU</name>
<description>Minute units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MNT</name>
<description>Minute tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>HU</name>
<description>Hour units in BCD format</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>HT</name>
<description>Hour tens in BCD format</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PM</name>
<description>AM/PM notation</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TSDR</name>
<displayName>TSDR</displayName>
<description>time stamp date register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDU</name>
<description>Week day units</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MT</name>
<description>Month tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MU</name>
<description>Month units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DT</name>
<description>Date tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DU</name>
<description>Date units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>TSSSR</name>
<displayName>TSSSR</displayName>
<description>timestamp sub second register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SS</name>
<description>Sub second value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ALRMAR</name>
<displayName>ALRMAR</displayName>
<description>alarm A register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MSK4</name>
<description>Alarm A date mask</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDSEL</name>
<description>Week day selection</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT</name>
<description>Date tens in BCD format</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DU</name>
<description>Date units or day in BCD format</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MSK3</name>
<description>Alarm A hours mask</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PM</name>
<description>AM/PM notation</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HT</name>
<description>Hour tens in BCD format</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>HU</name>
<description>Hour units in BCD format</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MSK2</name>
<description>Alarm A minutes mask</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MNT</name>
<description>Minute tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MNU</name>
<description>Minute units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MSK1</name>
<description>Alarm A seconds mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST</name>
<description>Second tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SU</name>
<description>Second units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>ALRMASSR</name>
<displayName>ALRMASSR</displayName>
<description>alarm A sub second register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MASKSS</name>
<description>Mask the most-significant bits starting at this bit</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SS</name>
<description>Sub seconds value</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>ALRMBR</name>
<displayName>ALRMBR</displayName>
<description>alarm B register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MSK4</name>
<description>Alarm B date mask</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDSEL</name>
<description>Week day selection</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT</name>
<description>Date tens in BCD format</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DU</name>
<description>Date units or day in BCD format</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MSK3</name>
<description>Alarm B hours mask</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PM</name>
<description>AM/PM notation</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HT</name>
<description>Hour tens in BCD format</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>HU</name>
<description>Hour units in BCD format</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MSK2</name>
<description>Alarm B minutes mask</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MNT</name>
<description>Minute tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MNU</name>
<description>Minute units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MSK1</name>
<description>Alarm B seconds mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST</name>
<description>Second tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SU</name>
<description>Second units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>ALRMBSSR</name>
<displayName>ALRMBSSR</displayName>
<description>alarm B sub second register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MASKSS</name>
<description>Mask the most-significant bits starting at this bit</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SS</name>
<description>Sub seconds value</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ALRAF</name>
<description>ALRAF</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALRBF</name>
<description>ALRBF</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUTF</name>
<description>WUTF</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSF</name>
<description>TSF</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSOVF</name>
<description>TSOVF</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITSF</name>
<description>ITSF</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MISR</name>
<displayName>MISR</displayName>
<description>status register</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ALRAMF</name>
<description>ALRAMF</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALRBMF</name>
<description>ALRBMF</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUTMF</name>
<description>WUTMF</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSMF</name>
<description>TSMF</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSOVMF</name>
<description>TSOVMF</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITSMF</name>
<description>ITSMF</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCR</name>
<displayName>SCR</displayName>
<description>status register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CALRAF</name>
<description>CALRAF</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALRBF</name>
<description>CALRBF</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CWUTF</name>
<description>CWUTF</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSF</name>
<description>CTSF</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSOVF</name>
<description>CTSOVF</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CITSF</name>
<description>CITSF</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMA1</name>
<description>DMA controller</description>
<groupName>DMA</groupName>
<baseAddress>0x40020000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMA1_CH1</name>
<description>DMA1 channel 1 interrupt</description>
<value>11</value>
</interrupt>
<interrupt>
<name>DMA1_CH2</name>
<description>DMA1 channel 2 interrupt</description>
<value>12</value>
</interrupt>
<interrupt>
<name>DMA1_CH3</name>
<description>DMA1 channel 3 interrupt</description>
<value>13</value>
</interrupt>
<interrupt>
<name>DMA1_CH4</name>
<description>DMA1 channel 4 interrupt</description>
<value>14</value>
</interrupt>
<interrupt>
<name>DMA1_CH5</name>
<description>DMA1 channel 5 interrupt</description>
<value>15</value>
</interrupt>
<interrupt>
<name>DMA1_CH6</name>
<description>DMA1 channel 6 interrupt</description>
<value>16</value>
</interrupt>
<registers>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>interrupt status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF8</name>
<description>TEIF8</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF8</name>
<description>HTIF8</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF8</name>
<description>TCIF8</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF8</name>
<description>GIF8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF7</name>
<description>TEIF7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF7</name>
<description>HTIF7</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF7</name>
<description>TCIF7</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF7</name>
<description>GIF7</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF6</name>
<description>TEIF6</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF6</name>
<description>HTIF6</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF6</name>
<description>TCIF6</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF6</name>
<description>GIF6</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF5</name>
<description>TEIF5</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF5</name>
<description>HTIF5</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF5</name>
<description>TCIF5</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF5</name>
<description>GIF5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF4</name>
<description>TEIF4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF4</name>
<description>HTIF4</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF4</name>
<description>TCIF4</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF4</name>
<description>GIF4</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF3</name>
<description>TEIF3</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF3</name>
<description>HTIF3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF3</name>
<description>TCIF3</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF3</name>
<description>GIF3</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF2</name>
<description>TEIF2</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF2</name>
<description>HTIF2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF2</name>
<description>TCIF2</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF2</name>
<description>GIF2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF1</name>
<description>TEIF1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF1</name>
<description>HTIF1</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF1</name>
<description>TCIF1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF1</name>
<description>GIF1</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IFCR</name>
<displayName>IFCR</displayName>
<description>DMA interrupt flag clear register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF8</name>
<description>TEIF8</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF8</name>
<description>HTIF8</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF8</name>
<description>TCIF8</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF8</name>
<description>GIF8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF7</name>
<description>TEIF7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF7</name>
<description>HTIF7</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF7</name>
<description>TCIF7</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF7</name>
<description>GIF7</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF6</name>
<description>TEIF6</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF6</name>
<description>HTIF6</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF6</name>
<description>TCIF6</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF6</name>
<description>GIF6</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF5</name>
<description>TEIF5</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF5</name>
<description>HTIF5</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF5</name>
<description>TCIF5</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF5</name>
<description>GIF5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF4</name>
<description>TEIF4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF4</name>
<description>HTIF4</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF4</name>
<description>TCIF4</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF4</name>
<description>GIF4</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF3</name>
<description>TEIF3</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF3</name>
<description>HTIF3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF3</name>
<description>TCIF3</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF3</name>
<description>GIF3</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF2</name>
<description>TEIF2</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF2</name>
<description>HTIF2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF2</name>
<description>TCIF2</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF2</name>
<description>GIF2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF1</name>
<description>TEIF1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF1</name>
<description>HTIF1</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF1</name>
<description>TCIF1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF1</name>
<description>GIF1</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR1</name>
<displayName>CCR1</displayName>
<description>DMA channel 1 configuration register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>TCIE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>HTIE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>TEIE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>DIR</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>CIRC</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>PINC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>MINC</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>PSIZE</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>MSIZE</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>PL</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>MEM2MEM</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR2</name>
<displayName>CCR2</displayName>
<description>DMA channel 2 configuration register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>TCIE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>HTIE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>TEIE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>DIR</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>CIRC</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>PINC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>MINC</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>PSIZE</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>MSIZE</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>PL</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>MEM2MEM</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR3</name>
<displayName>CCR3</displayName>
<description>DMA channel 3 configuration register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>TCIE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>HTIE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>TEIE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>DIR</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>CIRC</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>PINC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>MINC</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>PSIZE</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>MSIZE</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>PL</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>MEM2MEM</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR4</name>
<displayName>CCR4</displayName>
<description>DMA channel 3 configuration register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>TCIE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>HTIE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>TEIE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>DIR</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>CIRC</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>PINC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>MINC</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>PSIZE</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>MSIZE</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>PL</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>MEM2MEM</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR5</name>
<displayName>CCR5</displayName>
<description>DMA channel 4 configuration register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>TCIE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>HTIE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>TEIE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>DIR</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>CIRC</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>PINC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>MINC</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>PSIZE</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>MSIZE</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>PL</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>MEM2MEM</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR6</name>
<displayName>CCR6</displayName>
<description>DMA channel 5 configuration register</description>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>TCIE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>HTIE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>TEIE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>DIR</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>CIRC</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>PINC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>MINC</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>PSIZE</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>MSIZE</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>PL</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>MEM2MEM</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR7</name>
<displayName>CCR7</displayName>
<description>DMA channel 6 configuration register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>TCIE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>HTIE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>TEIE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>DIR</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>CIRC</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>PINC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>MINC</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>PSIZE</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>MSIZE</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>PL</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>MEM2MEM</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR8</name>
<displayName>CCR8</displayName>
<description>DMA channel 7 configuration register</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>TCIE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>HTIE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>TEIE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>DIR</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>CIRC</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>PINC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>MINC</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>PSIZE</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>MSIZE</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>PL</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>MEM2MEM</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR1</name>
<displayName>CNDTR1</displayName>
<description>channel x number of data to transfer register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data items to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR2</name>
<displayName>CNDTR2</displayName>
<description>channel x number of data to transfer register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data items to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR3</name>
<displayName>CNDTR3</displayName>
<description>channel x number of data to transfer register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data items to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR4</name>
<displayName>CNDTR4</displayName>
<description>channel x number of data to transfer register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data items to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR5</name>
<displayName>CNDTR5</displayName>
<description>channel x number of data to transfer register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data items to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR6</name>
<displayName>CNDTR6</displayName>
<description>channel x number of data to transfer register</description>
<addressOffset>0x70</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data items to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR7</name>
<displayName>CNDTR7</displayName>
<description>channel x number of data to transfer register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data items to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR8</name>
<displayName>CNDTR8</displayName>
<description>channel x number of data to transfer register</description>
<addressOffset>0x98</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data items to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR1</name>
<displayName>CPAR1</displayName>
<description>DMA channel x peripheral address register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR2</name>
<displayName>CPAR2</displayName>
<description>DMA channel x peripheral address register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR3</name>
<displayName>CPAR3</displayName>
<description>DMA channel x peripheral address register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR4</name>
<displayName>CPAR4</displayName>
<description>DMA channel x peripheral address register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR5</name>
<displayName>CPAR5</displayName>
<description>DMA channel x peripheral address register</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR6</name>
<displayName>CPAR6</displayName>
<description>DMA channel x peripheral address register</description>
<addressOffset>0x74</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR7</name>
<displayName>CPAR7</displayName>
<description>DMA channel x peripheral address register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR8</name>
<displayName>CPAR8</displayName>
<description>DMA channel x peripheral address register</description>
<addressOffset>0x9C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR1</name>
<displayName>CMAR1</displayName>
<description>DMA channel x memory address register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory 1 address (used in case of Double buffer mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR2</name>
<displayName>CMAR2</displayName>
<description>DMA channel x memory address register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory 1 address (used in case of Double buffer mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR3</name>
<displayName>CMAR3</displayName>
<description>DMA channel x memory address register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory 1 address (used in case of Double buffer mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR4</name>
<displayName>CMAR4</displayName>
<description>DMA channel x memory address register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory 1 address (used in case of Double buffer mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR5</name>
<displayName>CMAR5</displayName>
<description>DMA channel x memory address register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory 1 address (used in case of Double buffer mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR6</name>
<displayName>CMAR6</displayName>
<description>DMA channel x memory address register</description>
<addressOffset>0x78</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory 1 address (used in case of Double buffer mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR7</name>
<displayName>CMAR7</displayName>
<description>DMA channel x memory address register</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory 1 address (used in case of Double buffer mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR8</name>
<displayName>CMAR8</displayName>
<description>DMA channel x memory address register</description>
<addressOffset>0xA0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory 1 address (used in case of Double buffer mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="DMA1">
<name>DMA2</name>
<baseAddress>0x40020400</baseAddress>
<interrupt>
<name>DMA2_CH1</name>
<description>DMA2_CH1</description>
<value>56</value>
</interrupt>
<interrupt>
<name>DMA2_CH2</name>
<description>DMA2_CH2</description>
<value>57</value>
</interrupt>
<interrupt>
<name>DMA2_CH3</name>
<description>DMA2_CH3</description>
<value>58</value>
</interrupt>
<interrupt>
<name>DMA2_CH4</name>
<description>DMA2_CH4</description>
<value>59</value>
</interrupt>
<interrupt>
<name>DMA2_CH5</name>
<description>DMA2_CH5</description>
<value>60</value>
</interrupt>
<interrupt>
<name>DMA2_CH6</name>
<description>DMA2_CH6</description>
<value>97</value>
</interrupt>
</peripheral>
<peripheral>
<name>DMAMUX</name>
<description>DMAMUX</description>
<groupName>DMAMUX</groupName>
<baseAddress>0x40020800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMAMUX_OVR</name>
<description>DMAMUX_OVR</description>
<value>94</value>
</interrupt>
<registers>
<register>
<name>C0CR</name>
<displayName>C0CR</displayName>
<description>DMAMux - DMA request line multiplexer channel x control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line selected</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1CR</name>
<displayName>C1CR</displayName>
<description>DMAMux - DMA request line multiplexer channel x control register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line selected</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2CR</name>
<displayName>C2CR</displayName>
<description>DMAMux - DMA request line multiplexer channel x control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line selected</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3CR</name>
<displayName>C3CR</displayName>
<description>DMAMux - DMA request line multiplexer channel x control register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line selected</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4CR</name>
<displayName>C4CR</displayName>
<description>DMAMux - DMA request line multiplexer channel x control register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line selected</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C5CR</name>
<displayName>C5CR</displayName>
<description>DMAMux - DMA request line multiplexer channel x control register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line selected</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C6CR</name>
<displayName>C6CR</displayName>
<description>DMAMux - DMA request line multiplexer channel x control register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line selected</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C7CR</name>
<displayName>C7CR</displayName>
<description>DMAMux - DMA request line multiplexer channel x control register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line selected</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C8CR</name>
<displayName>C8CR</displayName>
<description>DMAMux - DMA request line multiplexer channel x control register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line selected</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C9CR</name>
<displayName>C9CR</displayName>
<description>DMAMux - DMA request line multiplexer channel x control register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line selected</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C10CR</name>
<displayName>C10CR</displayName>
<description>DMAMux - DMA request line multiplexer channel x control register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line selected</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C11CR</name>
<displayName>C11CR</displayName>
<description>DMAMux - DMA request line multiplexer channel x control register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line selected</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C12CR</name>
<displayName>C12CR</displayName>
<description>DMAMux - DMA request line multiplexer channel x control register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line selected</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C13CR</name>
<displayName>C13CR</displayName>
<description>DMAMux - DMA request line multiplexer channel x control register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line selected</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C14CR</name>
<displayName>C14CR</displayName>
<description>DMAMux - DMA request line multiplexer channel x control register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line selected</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C15CR</name>
<displayName>C15CR</displayName>
<description>DMAMux - DMA request line multiplexer channel x control register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line selected</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>RG0CR</name>
<displayName>RG0CR</displayName>
<description>DMAMux - DMA request generator channel x control register</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_ID</name>
<description>DMA request trigger input selected</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Interrupt enable at trigger event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GE</name>
<description>DMA request generator channel enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GNBREQ</name>
<description>Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>RG1CR</name>
<displayName>RG1CR</displayName>
<description>DMAMux - DMA request generator channel x control register</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_ID</name>
<description>DMA request trigger input selected</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Interrupt enable at trigger event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GE</name>
<description>DMA request generator channel enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GNBREQ</name>
<description>Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>RG2CR</name>
<displayName>RG2CR</displayName>
<description>DMAMux - DMA request generator channel x control register</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_ID</name>
<description>DMA request trigger input selected</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Interrupt enable at trigger event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GE</name>
<description>DMA request generator channel enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GNBREQ</name>
<description>Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>RG3CR</name>
<displayName>RG3CR</displayName>
<description>DMAMux - DMA request generator channel x control register</description>
<addressOffset>0x10C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_ID</name>
<description>DMA request trigger input selected</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Interrupt enable at trigger event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GE</name>
<description>DMA request generator channel enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GNBREQ</name>
<description>Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>RGSR</name>
<displayName>RGSR</displayName>
<description>DMAMux - DMA request generator status register</description>
<addressOffset>0x140</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OF</name>
<description>Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>RGCFR</name>
<displayName>RGCFR</displayName>
<description>DMAMux - DMA request generator clear flag register</description>
<addressOffset>0x144</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COF</name>
<description>Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CSR</name>
<displayName>CSR</displayName>
<description>DMAMUX request line multiplexer interrupt channel status register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SOF</name>
<description>Synchronization overrun event flag</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFR</name>
<displayName>CFR</displayName>
<description>DMAMUX request line multiplexer interrupt clear flag register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CSOF</name>
<description>Clear synchronization overrun event flag</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SYSCFG</name>
<description>System configuration controller</description>
<groupName>SYSCFG</groupName>
<baseAddress>0x40010000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x2A</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MEMRMP</name>
<displayName>MEMRMP</displayName>
<description>Remap Memory register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM_MODE</name>
<description>Memory mapping selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>FB_mode</name>
<description>User Flash Bank mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFGR1</name>
<displayName>CFGR1</displayName>
<description>peripheral mode configuration register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x7C000001</resetValue>
<fields>
<field>
<name>BOOSTEN</name>
<description>BOOSTEN</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ANASWVDD</name>
<description>GPIO analog switch control voltage selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C_PB6_FMP</name>
<description>FM+ drive capability on PB6</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C_PB7_FMP</name>
<description>FM+ drive capability on PB6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C_PB8_FMP</name>
<description>FM+ drive capability on PB6</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C_PB9_FMP</name>
<description>FM+ drive capability on PB6</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C1_FMP</name>
<description>I2C1 FM+ drive capability enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C2_FMP</name>
<description>I2C1 FM+ drive capability enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C3_FMP</name>
<description>I2C1 FM+ drive capability enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C4_FMP</name>
<description>I2C1 FM+ drive capability enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPU_IE</name>
<description>FPU Interrupts Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXTICR1</name>
<displayName>EXTICR1</displayName>
<description>external interrupt configuration register 1</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>EXTI3</name>
<description>EXTI x configuration (x = 0 to 3)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI2</name>
<description>EXTI x configuration (x = 0 to 3)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI1</name>
<description>EXTI x configuration (x = 0 to 3)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI0</name>
<description>EXTI x configuration (x = 0 to 3)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXTICR2</name>
<displayName>EXTICR2</displayName>
<description>external interrupt configuration register 2</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>EXTI7</name>
<description>EXTI x configuration (x = 4 to 7)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI6</name>
<description>EXTI x configuration (x = 4 to 7)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI5</name>
<description>EXTI x configuration (x = 4 to 7)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI4</name>
<description>EXTI x configuration (x = 4 to 7)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXTICR3</name>
<displayName>EXTICR3</displayName>
<description>external interrupt configuration register 3</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>EXTI11</name>
<description>EXTI x configuration (x = 8 to 11)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI10</name>
<description>EXTI10</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI9</name>
<description>EXTI x configuration (x = 8 to 11)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI8</name>
<description>EXTI x configuration (x = 8 to 11)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXTICR4</name>
<displayName>EXTICR4</displayName>
<description>external interrupt configuration register 4</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>EXTI15</name>
<description>EXTI x configuration (x = 12 to 15)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI14</name>
<description>EXTI x configuration (x = 12 to 15)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI13</name>
<description>EXTI x configuration (x = 12 to 15)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI12</name>
<description>EXTI x configuration (x = 12 to 15)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCSR</name>
<displayName>SCSR</displayName>
<description>CCM SRAM control and status register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCMER</name>
<description>CCM SRAM Erase</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CCMBSY</name>
<description>CCM SRAM busy by erase operation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CFGR2</name>
<displayName>CFGR2</displayName>
<description>configuration register 2</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLL</name>
<description>Core Lockup Lock</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPL</name>
<description>SRAM Parity Lock</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVDL</name>
<description>PVD Lock</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECCL</name>
<description>ECC Lock</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPF</name>
<description>SRAM Parity Flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SWPR</name>
<displayName>SWPR</displayName>
<description>SRAM Write protection register 1</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>Page0_WP</name>
<description>Write protection</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page1_WP</name>
<description>Write protection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page2_WP</name>
<description>Write protection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page3_WP</name>
<description>Write protection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page4_WP</name>
<description>Write protection</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page5_WP</name>
<description>Write protection</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page6_WP</name>
<description>Write protection</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page7_WP</name>
<description>Write protection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page8_WP</name>
<description>Write protection</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page9_WP</name>
<description>Write protection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page10_WP</name>
<description>Write protection</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page11_WP</name>
<description>Write protection</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page12_WP</name>
<description>Write protection</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page13_WP</name>
<description>Write protection</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page14_WP</name>
<description>Write protection</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page15_WP</name>
<description>Write protection</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page16_WP</name>
<description>Write protection</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page17_WP</name>
<description>Write protection</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page18_WP</name>
<description>Write protection</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page19_WP</name>
<description>Write protection</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page20_WP</name>
<description>Write protection</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page21_WP</name>
<description>Write protection</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page22_WP</name>
<description>Write protection</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page23_WP</name>
<description>Write protection</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page24_WP</name>
<description>Write protection</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page25_WP</name>
<description>Write protection</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page26_WP</name>
<description>Write protection</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page27_WP</name>
<description>Write protection</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page28_WP</name>
<description>Write protection</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page29_WP</name>
<description>Write protection</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page30_WP</name>
<description>Write protection</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Page31_WP</name>
<description>Write protection</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SKR</name>
<displayName>SKR</displayName>
<description>SRAM2 Key Register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEY</name>
<description>SRAM2 Key for software erase</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>VREFBUF</name>
<description>Voltage reference buffer</description>
<groupName>VREFBUF</groupName>
<baseAddress>0x40010030</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1D0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>VREFBUF_CSR</name>
<displayName>VREFBUF_CSR</displayName>
<description>VREF_BUF Control and Status Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00000002</resetValue>
<fields>
<field>
<name>ENVR</name>
<description>Enable Voltage Reference</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HIZ</name>
<description>High impedence mode for the VREF_BUF</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>VRR</name>
<description>Voltage reference buffer ready</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>VRS</name>
<description>Voltage reference scale</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>VREFBUF_CCR</name>
<displayName>VREFBUF_CCR</displayName>
<description>VREF_BUF Calibration Control Register</description>
<addressOffset>0x04</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TRIM</name>
<description>Trimming code</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>COMP</name>
<description>Comparator control and status register</description>
<groupName>COMP</groupName>
<baseAddress>0x40010200</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x100</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>COMP1_2_3</name>
<description>COMP1_2_3</description>
<value>64</value>
</interrupt>
<interrupt>
<name>COMP4_5_6</name>
<description>COMP4_5_6</description>
<value>65</value>
</interrupt>
<interrupt>
<name>COMP7</name>
<description>COMP7</description>
<value>66</value>
</interrupt>
<registers>
<register>
<name>COMP_C1CSR</name>
<displayName>COMP_C1CSR</displayName>
<description>Comparator control/status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>EN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INMSEL</name>
<description>INMSEL</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INPSEL</name>
<description>INPSEL</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>POL</name>
<description>POL</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HYST</name>
<description>HYST</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BLANKSEL</name>
<description>BLANKSEL</description>
<bitOffset>19</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRGEN</name>
<description>BRGEN</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SCALEN</name>
<description>SCALEN</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>VALUE</name>
<description>VALUE</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>LOCK</name>
<description>LOCK</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>COMP_C2CSR</name>
<displayName>COMP_C2CSR</displayName>
<description>Comparator control/status register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>EN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INMSEL</name>
<description>INMSEL</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INPSEL</name>
<description>INPSEL</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>POL</name>
<description>POL</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HYST</name>
<description>HYST</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BLANKSEL</name>
<description>BLANKSEL</description>
<bitOffset>19</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRGEN</name>
<description>BRGEN</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SCALEN</name>
<description>SCALEN</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>VALUE</name>
<description>VALUE</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>LOCK</name>
<description>LOCK</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>COMP_C3CSR</name>
<displayName>COMP_C3CSR</displayName>
<description>Comparator control/status register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>EN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INMSEL</name>
<description>INMSEL</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INPSEL</name>
<description>INPSEL</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>POL</name>
<description>POL</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HYST</name>
<description>HYST</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BLANKSEL</name>
<description>BLANKSEL</description>
<bitOffset>19</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRGEN</name>
<description>BRGEN</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SCALEN</name>
<description>SCALEN</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>VALUE</name>
<description>VALUE</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>LOCK</name>
<description>LOCK</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>COMP_C4CSR</name>
<displayName>COMP_C4CSR</displayName>
<description>Comparator control/status register</description>
<addressOffset>0x0C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>EN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INMSEL</name>
<description>INMSEL</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INPSEL</name>
<description>INPSEL</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>POL</name>
<description>POL</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HYST</name>
<description>HYST</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BLANKSEL</name>
<description>BLANKSEL</description>
<bitOffset>19</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRGEN</name>
<description>BRGEN</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SCALEN</name>
<description>SCALEN</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>VALUE</name>
<description>VALUE</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>LOCK</name>
<description>LOCK</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>OPAMP</name>
<description>Operational amplifiers</description>
<groupName>OPAMP</groupName>
<baseAddress>0x40010300</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x100</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>OPAMP1_CSR</name>
<displayName>OPAMP1_CSR</displayName>
<description>OPAMP1 control/status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OPAEN</name>
<description>Operational amplifier Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCE_VP</name>
<description>FORCE_VP</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VP_SEL</name>
<description>VP_SEL</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>USERTRIM</name>
<description>USERTRIM</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VM_SEL</name>
<description>VM_SEL</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OPAHSM</name>
<description>OPAHSM</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPAINTOEN</name>
<description>OPAINTOEN</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALON</name>
<description>CALON</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALSEL</name>
<description>CALSEL</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PGA_GAIN</name>
<description>PGA_GAIN</description>
<bitOffset>14</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TRIMOFFSETP</name>
<description>TRIMOFFSETP</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TRIMOFFSETN</name>
<description>TRIMOFFSETN</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>CALOUT</name>
<description>CALOUT</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>LOCK</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPAMP2_CSR</name>
<displayName>OPAMP2_CSR</displayName>
<description>OPAMP2 control/status register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OPAEN</name>
<description>Operational amplifier Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCE_VP</name>
<description>FORCE_VP</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VP_SEL</name>
<description>VP_SEL</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>USERTRIM</name>
<description>USERTRIM</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VM_SEL</name>
<description>VM_SEL</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OPAHSM</name>
<description>OPAHSM</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPAINTOEN</name>
<description>OPAINTOEN</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALON</name>
<description>CALON</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALSEL</name>
<description>CALSEL</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PGA_GAIN</name>
<description>PGA_GAIN</description>
<bitOffset>14</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TRIMOFFSETP</name>
<description>TRIMOFFSETP</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TRIMOFFSETN</name>
<description>TRIMOFFSETN</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>CALOUT</name>
<description>CALOUT</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>LOCK</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPAMP3_CSR</name>
<displayName>OPAMP3_CSR</displayName>
<description>OPAMP3 control/status register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OPAEN</name>
<description>Operational amplifier Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCE_VP</name>
<description>FORCE_VP</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VP_SEL</name>
<description>VP_SEL</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>USERTRIM</name>
<description>USERTRIM</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VM_SEL</name>
<description>VM_SEL</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OPAHSM</name>
<description>OPAHSM</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPAINTOEN</name>
<description>OPAINTOEN</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALON</name>
<description>CALON</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALSEL</name>
<description>CALSEL</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PGA_GAIN</name>
<description>PGA_GAIN</description>
<bitOffset>14</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TRIMOFFSETP</name>
<description>TRIMOFFSETP</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TRIMOFFSETN</name>
<description>TRIMOFFSETN</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>CALOUT</name>
<description>CALOUT</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>LOCK</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPAMP1_TCMR</name>
<displayName>OPAMP1_TCMR</displayName>
<description>OPAMP1 control/status register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VMS_SEL</name>
<description>VMS_SEL</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VPS_SEL</name>
<description>VPS_SEL</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>T1CM_EN</name>
<description>T1CM_EN</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T8CM_EN</name>
<description>T8CM_EN</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T20CM_EN</name>
<description>T20CM_EN</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>LOCK</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPAMP2_TCMR</name>
<displayName>OPAMP2_TCMR</displayName>
<description>OPAMP2 control/status register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VMS_SEL</name>
<description>VMS_SEL</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VPS_SEL</name>
<description>VPS_SEL</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>T1CM_EN</name>
<description>T1CM_EN</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T8CM_EN</name>
<description>T8CM_EN</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T20CM_EN</name>
<description>T20CM_EN</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>LOCK</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPAMP3_TCMR</name>
<displayName>OPAMP3_TCMR</displayName>
<description>OPAMP3 control/status register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VMS_SEL</name>
<description>VMS_SEL</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VPS_SEL</name>
<description>VPS_SEL</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>T1CM_EN</name>
<description>T1CM_EN</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T8CM_EN</name>
<description>T8CM_EN</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T20CM_EN</name>
<description>T20CM_EN</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>LOCK</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DAC1</name>
<description>Digital-to-analog converter</description>
<groupName>DAC</groupName>
<baseAddress>0x50000800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DAC_CR</name>
<displayName>DAC_CR</displayName>
<description>DAC control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN1</name>
<description>DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEN1</name>
<description>DAC channel1 trigger enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSEL1</name>
<description>DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).</description>
<bitOffset>2</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>WAVE1</name>
<description>DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MAMP1</name>
<description>DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DMAEN1</name>
<description>DAC channel1 DMA enable This bit is set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAUDRIE1</name>
<description>DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEN1</name>
<description>DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN2</name>
<description>DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEN2</name>
<description>DAC channel2 trigger enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSEL2</name>
<description>DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).</description>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>WAVE2</name>
<description>DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MAMP2</name>
<description>DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DMAEN2</name>
<description>DAC channel2 DMA enable This bit is set and cleared by software.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAUDRIE2</name>
<description>DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEN2</name>
<description>DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_SWTRGR</name>
<displayName>DAC_SWTRGR</displayName>
<description>DAC software trigger register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWTRIG1</name>
<description>DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWTRIG2</name>
<description>DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWTRIGB1</name>
<description>DAC channel1 software trigger B</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWTRIGB2</name>
<description>DAC channel2 software trigger B</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_DHR12R1</name>
<displayName>DAC_DHR12R1</displayName>
<description>DAC channel1 12-bit right-aligned data holding register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>DACC1DHRB</name>
<description>DAC channel1 12-bit right-aligned data B</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_DHR12L1</name>
<displayName>DAC_DHR12L1</displayName>
<description>DAC channel1 12-bit left aligned data holding register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>DACC1DHRB</name>
<description>DAC channel1 12-bit left-aligned data B</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_DHR8R1</name>
<displayName>DAC_DHR8R1</displayName>
<description>DAC channel1 8-bit right aligned data holding register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DACC1DHRB</name>
<description>DAC channel1 8-bit right-aligned data</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_DHR12R2</name>
<displayName>DAC_DHR12R2</displayName>
<description>DAC channel2 12-bit right aligned data holding register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>DACC2DHRB</name>
<description>DAC channel2 12-bit right-aligned data</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_DHR12L2</name>
<displayName>DAC_DHR12L2</displayName>
<description>DAC channel2 12-bit left aligned data holding register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2.</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>DACC2DHRB</name>
<description>DAC channel2 12-bit left-aligned data B</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_DHR8R2</name>
<displayName>DAC_DHR8R2</displayName>
<description>DAC channel2 8-bit right-aligned data holding register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DACC2DHRB</name>
<description>DAC channel2 8-bit right-aligned data</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_DHR12RD</name>
<displayName>DAC_DHR12RD</displayName>
<description>Dual DAC 12-bit right-aligned data holding register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_DHR12LD</name>
<displayName>DAC_DHR12LD</displayName>
<description>DUAL DAC 12-bit left aligned data holding register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_DHR8RD</name>
<displayName>DAC_DHR8RD</displayName>
<description>DUAL DAC 8-bit right aligned data holding register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_DOR1</name>
<displayName>DAC_DOR1</displayName>
<description>DAC channel1 data output register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DOR</name>
<description>DAC channel1 data output These bits are read-only, they contain data output for DAC channel1.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>DACC1DORB</name>
<description>DAC channel1 data output</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_DOR2</name>
<displayName>DAC_DOR2</displayName>
<description>DAC channel2 data output register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC2DOR</name>
<description>DAC channel2 data output These bits are read-only, they contain data output for DAC channel2.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>DACC2DORB</name>
<description>DAC channel2 data output</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_SR</name>
<displayName>DAC_SR</displayName>
<description>DAC status register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAC1RDY</name>
<description>DAC channel1 ready status bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DORSTAT1</name>
<description>DAC channel1 output register status bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DMAUDR1</name>
<description>DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAL_FLAG1</name>
<description>DAC Channel 1 calibration offset status This bit is set and cleared by hardware</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BWST1</name>
<description>DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample &amp; Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization).</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DAC2RDY</name>
<description>DAC channel 2 ready status bit</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DORSTAT2</name>
<description>DAC channel 2 output register status bit</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DMAUDR2</name>
<description>DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAL_FLAG2</name>
<description>DAC Channel 2 calibration offset status This bit is set and cleared by hardware</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BWST2</name>
<description>DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample &amp; Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization).</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DAC_CCR</name>
<displayName>DAC_CCR</displayName>
<description>DAC calibration control register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OTRIM1</name>
<description>DAC Channel 1 offset trimming value</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OTRIM2</name>
<description>DAC Channel 2 offset trimming value</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_MCR</name>
<displayName>DAC_MCR</displayName>
<description>DAC mode control register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MODE1</name>
<description>DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample &amp;amp; hold mode</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DMADOUBLE1</name>
<description>DAC Channel1 DMA double data mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SINFORMAT1</name>
<description>Enable signed format for DAC channel1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HFSEL</name>
<description>High frequency interface mode selection</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE2</name>
<description>DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample &amp;amp; hold mode</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DMADOUBLE2</name>
<description>DAC Channel2 DMA double data mode</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SINFORMAT2</name>
<description>Enable signed format for DAC channel2</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_SHSR1</name>
<displayName>DAC_SHSR1</displayName>
<description>DAC Sample and Hold sample time register 1</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSAMPLE1</name>
<description>DAC Channel 1 sample Time (only valid in sample &amp;amp; hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored.</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_SHSR2</name>
<displayName>DAC_SHSR2</displayName>
<description>DAC Sample and Hold sample time register 2</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSAMPLE2</name>
<description>DAC Channel 2 sample Time (only valid in sample &amp;amp; hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored.</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_SHHR</name>
<displayName>DAC_SHHR</displayName>
<description>DAC Sample and Hold hold time register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00010001</resetValue>
<fields>
<field>
<name>THOLD1</name>
<description>DAC Channel 1 hold Time (only valid in sample &amp;amp; hold mode) Hold time= (THOLD[9:0]) x T LSI</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>THOLD2</name>
<description>DAC Channel 2 hold time (only valid in sample &amp;amp; hold mode). Hold time= (THOLD[9:0]) x T LSI</description>
<bitOffset>16</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_SHRR</name>
<displayName>DAC_SHRR</displayName>
<description>DAC Sample and Hold refresh time register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00010001</resetValue>
<fields>
<field>
<name>TREFRESH1</name>
<description>DAC Channel 1 refresh Time (only valid in sample &amp;amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>TREFRESH2</name>
<description>DAC Channel 2 refresh Time (only valid in sample &amp;amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_STR1</name>
<displayName>DAC_STR1</displayName>
<description>Sawtooth register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STRSTDATA1</name>
<description>DAC Channel 1 Sawtooth reset value</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>STDIR1</name>
<description>DAC Channel1 Sawtooth direction setting</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STINCDATA1</name>
<description>DAC CH1 Sawtooth increment value (12.4 bit format)</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_STR2</name>
<displayName>DAC_STR2</displayName>
<description>Sawtooth register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STRSTDATA2</name>
<description>DAC Channel 2 Sawtooth reset value</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>STDIR2</name>
<description>DAC Channel2 Sawtooth direction setting</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STINCDATA2</name>
<description>DAC CH2 Sawtooth increment value (12.4 bit format)</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_STMODR</name>
<displayName>DAC_STMODR</displayName>
<description>Sawtooth Mode register</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STRSTTRIGSEL1</name>
<description>DAC Channel 1 Sawtooth Reset trigger selection</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STINCTRIGSEL1</name>
<description>DAC Channel 1 Sawtooth Increment trigger selection</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STRSTTRIGSEL2</name>
<description>DAC Channel 1 Sawtooth Reset trigger selection</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STINCTRIGSEL2</name>
<description>DAC Channel 2 Sawtooth Increment trigger selection</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="DAC1">
<name>DAC2</name>
<baseAddress>0x50000C00</baseAddress>
</peripheral>
<peripheral derivedFrom="DAC1">
<name>DAC3</name>
<baseAddress>0x50001000</baseAddress>
</peripheral>
<peripheral derivedFrom="DAC1">
<name>DAC4</name>
<baseAddress>0x50001400</baseAddress>
</peripheral>
<peripheral>
<name>ADC1</name>
<description>Analog-to-Digital Converter</description>
<groupName>ADC</groupName>
<baseAddress>0x50000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xD0</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ADC1_2</name>
<description>ADC1 and ADC2 global interrupt</description>
<value>18</value>
</interrupt>
<registers>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>interrupt and status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JQOVF</name>
<description>JQOVF</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD3</name>
<description>AWD3</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD2</name>
<description>AWD2</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1</name>
<description>AWD1</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOS</name>
<description>JEOS</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOC</name>
<description>JEOC</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR</name>
<description>OVR</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOS</name>
<description>EOS</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC</name>
<description>EOC</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOSMP</name>
<description>EOSMP</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADRDY</name>
<description>ADRDY</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>interrupt enable register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JQOVFIE</name>
<description>JQOVFIE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD3IE</name>
<description>AWD3IE</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD2IE</name>
<description>AWD2IE</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1IE</name>
<description>AWD1IE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOSIE</name>
<description>JEOSIE</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOCIE</name>
<description>JEOCIE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRIE</name>
<description>OVRIE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOSIE</name>
<description>EOSIE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOCIE</name>
<description>EOCIE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOSMPIE</name>
<description>EOSMPIE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADRDYIE</name>
<description>ADRDYIE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>ADCAL</name>
<description>ADCAL</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADCALDIF</name>
<description>ADCALDIF</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEEPPWD</name>
<description>DEEPPWD</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADVREGEN</name>
<description>ADVREGEN</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JADSTP</name>
<description>JADSTP</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADSTP</name>
<description>ADSTP</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JADSTART</name>
<description>JADSTART</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADSTART</name>
<description>ADSTART</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDIS</name>
<description>ADDIS</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADEN</name>
<description>ADEN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFGR</name>
<displayName>CFGR</displayName>
<description>configuration register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x80000000</resetValue>
<fields>
<field>
<name>JQDIS</name>
<description>Injected Queue disable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1CH</name>
<description>Analog watchdog 1 channel selection</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JAUTO</name>
<description>JAUTO</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JAWD1EN</name>
<description>JAWD1EN</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1EN</name>
<description>AWD1EN</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1SGL</name>
<description>AWD1SGL</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JQM</name>
<description>JQM</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JDISCEN</name>
<description>JDISCEN</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISCNUM</name>
<description>DISCNUM</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DISCEN</name>
<description>DISCEN</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALIGN</name>
<description>ALIGN</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AUTDLY</name>
<description>AUTDLY</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CONT</name>
<description>CONT</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRMOD</name>
<description>OVRMOD</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEN</name>
<description>EXTEN</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EXTSEL</name>
<description>External trigger selection for regular group</description>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>RES</name>
<description>RES</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DMACFG</name>
<description>DMACFG</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAEN</name>
<description>DMAEN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFGR2</name>
<displayName>CFGR2</displayName>
<description>configuration register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SMPTRIG</name>
<description>SMPTRIG</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BULB</name>
<description>BULB</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWTRIG</name>
<description>SWTRIG</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GCOMP</name>
<description>GCOMP</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROVSM</name>
<description>EXTEN</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TROVS</name>
<description>Triggered Regular Oversampling</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVSS</name>
<description>ALIGN</description>
<bitOffset>5</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>OVSR</name>
<description>RES</description>
<bitOffset>2</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>JOVSE</name>
<description>DMACFG</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROVSE</name>
<description>DMAEN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMPR1</name>
<displayName>SMPR1</displayName>
<description>sample time register 1</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SMP9</name>
<description>SMP9</description>
<bitOffset>27</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP8</name>
<description>SMP8</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP7</name>
<description>SMP7</description>
<bitOffset>21</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP6</name>
<description>SMP6</description>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP5</name>
<description>SMP5</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP4</name>
<description>SMP4</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP3</name>
<description>SMP3</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP2</name>
<description>SMP2</description>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP1</name>
<description>SMP1</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMPPLUS</name>
<description>Addition of one clock cycle to the sampling time</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMP0</name>
<description>SMP0</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMPR2</name>
<displayName>SMPR2</displayName>
<description>sample time register 2</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SMP18</name>
<description>SMP18</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP17</name>
<description>SMP17</description>
<bitOffset>21</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP16</name>
<description>SMP16</description>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP15</name>
<description>SMP15</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP14</name>
<description>SMP14</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP13</name>
<description>SMP13</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP12</name>
<description>SMP12</description>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP11</name>
<description>SMP11</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP10</name>
<description>SMP10</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TR1</name>
<displayName>TR1</displayName>
<description>watchdog threshold register 1</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFF0000</resetValue>
<fields>
<field>
<name>HT1</name>
<description>HT1</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>AWDFILT</name>
<description>AWDFILT</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>LT1</name>
<description>LT1</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>TR2</name>
<displayName>TR2</displayName>
<description>watchdog threshold register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00FF0000</resetValue>
<fields>
<field>
<name>HT2</name>
<description>HT2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LT2</name>
<description>LT2</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>TR3</name>
<displayName>TR3</displayName>
<description>watchdog threshold register 3</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00FF0000</resetValue>
<fields>
<field>
<name>HT3</name>
<description>HT3</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LT3</name>
<description>LT3</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SQR1</name>
<displayName>SQR1</displayName>
<description>regular sequence register 1</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SQ4</name>
<description>SQ4</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ3</name>
<description>SQ3</description>
<bitOffset>18</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ2</name>
<description>SQ2</description>
<bitOffset>12</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ1</name>
<description>SQ1</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>L</name>
<description>Regular channel sequence length</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>SQR2</name>
<displayName>SQR2</displayName>
<description>regular sequence register 2</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SQ9</name>
<description>SQ9</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ8</name>
<description>SQ8</description>
<bitOffset>18</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ7</name>
<description>SQ7</description>
<bitOffset>12</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ6</name>
<description>SQ6</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ5</name>
<description>SQ5</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>SQR3</name>
<displayName>SQR3</displayName>
<description>regular sequence register 3</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SQ14</name>
<description>SQ14</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ13</name>
<description>SQ13</description>
<bitOffset>18</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ12</name>
<description>SQ12</description>
<bitOffset>12</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ11</name>
<description>SQ11</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ10</name>
<description>SQ10</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>SQR4</name>
<displayName>SQR4</displayName>
<description>regular sequence register 4</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SQ16</name>
<description>SQ16</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ15</name>
<description>SQ15</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>regular Data Register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RDATA</name>
<description>Regular Data converted</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>JSQR</name>
<displayName>JSQR</displayName>
<description>injected sequence register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JSQ4</name>
<description>JSQ4</description>
<bitOffset>27</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JSQ3</name>
<description>JSQ3</description>
<bitOffset>21</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JSQ2</name>
<description>JSQ2</description>
<bitOffset>15</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JSQ1</name>
<description>JSQ1</description>
<bitOffset>9</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JEXTEN</name>
<description>JEXTEN</description>
<bitOffset>7</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>JEXTSEL</name>
<description>JEXTSEL</description>
<bitOffset>2</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JL</name>
<description>JL</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OFR1</name>
<displayName>OFR1</displayName>
<description>offset register 1</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OFFSET1_EN</name>
<description>OFFSET1_EN</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSET1_CH</name>
<description>OFFSET1_CH</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SATEN</name>
<description>SATEN</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSETPOS</name>
<description>OFFSETPOS</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSET1</name>
<description>OFFSET1</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>OFR2</name>
<displayName>OFR2</displayName>
<description>offset register 2</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OFFSET1_EN</name>
<description>OFFSET1_EN</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSET1_CH</name>
<description>OFFSET1_CH</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SATEN</name>
<description>SATEN</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSETPOS</name>
<description>OFFSETPOS</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSET1</name>
<description>OFFSET1</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>OFR3</name>
<displayName>OFR3</displayName>
<description>offset register 3</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OFFSET1_EN</name>
<description>OFFSET1_EN</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSET1_CH</name>
<description>OFFSET1_CH</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SATEN</name>
<description>SATEN</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSETPOS</name>
<description>OFFSETPOS</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSET1</name>
<description>OFFSET1</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>OFR4</name>
<displayName>OFR4</displayName>
<description>offset register 4</description>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OFFSET1_EN</name>
<description>OFFSET1_EN</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSET1_CH</name>
<description>OFFSET1_CH</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SATEN</name>
<description>SATEN</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSETPOS</name>
<description>OFFSETPOS</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSET1</name>
<description>OFFSET1</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>JDR1</name>
<displayName>JDR1</displayName>
<description>injected data register 1</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA1</name>
<description>JDATA1</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>JDR2</name>
<displayName>JDR2</displayName>
<description>injected data register 2</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA2</name>
<description>JDATA2</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>JDR3</name>
<displayName>JDR3</displayName>
<description>injected data register 3</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA3</name>
<description>JDATA3</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>JDR4</name>
<displayName>JDR4</displayName>
<description>injected data register 4</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA4</name>
<description>JDATA4</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>AWD2CR</name>
<displayName>AWD2CR</displayName>
<description>Analog Watchdog 2 Configuration Register</description>
<addressOffset>0xA0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AWD2CH</name>
<description>AWD2CH</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
</fields>
</register>
<register>
<name>AWD3CR</name>
<displayName>AWD3CR</displayName>
<description>Analog Watchdog 3 Configuration Register</description>
<addressOffset>0xA4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AWD3CH</name>
<description>AWD3CH</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIFSEL</name>
<displayName>DIFSEL</displayName>
<description>Differential Mode Selection Register 2</description>
<addressOffset>0xB0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIFSEL_0</name>
<description>Differential mode for channels 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DIFSEL_1_18</name>
<description>Differential mode for channels 15 to 1</description>
<bitOffset>1</bitOffset>
<bitWidth>18</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CALFACT</name>
<displayName>CALFACT</displayName>
<description>Calibration Factors</description>
<addressOffset>0xB4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CALFACT_D</name>
<description>CALFACT_D</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>CALFACT_S</name>
<description>CALFACT_S</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>GCOMP</name>
<displayName>GCOMP</displayName>
<description>Gain compensation Register</description>
<addressOffset>0xC0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GCOMPCOEFF</name>
<description>GCOMPCOEFF</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="ADC1">
<name>ADC2</name>
<baseAddress>0x50000100</baseAddress>
</peripheral>
<peripheral>
<name>ADC12_Common</name>
<description>Analog-to-Digital Converter</description>
<groupName>ADC</groupName>
<baseAddress>0x50000300</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x11</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CSR</name>
<displayName>CSR</displayName>
<description>ADC Common status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDRDY_MST</name>
<description>ADDRDY_MST</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOSMP_MST</name>
<description>EOSMP_MST</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC_MST</name>
<description>EOC_MST</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOS_MST</name>
<description>EOS_MST</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR_MST</name>
<description>OVR_MST</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOC_MST</name>
<description>JEOC_MST</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOS_MST</name>
<description>JEOS_MST</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1_MST</name>
<description>AWD1_MST</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD2_MST</name>
<description>AWD2_MST</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD3_MST</name>
<description>AWD3_MST</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JQOVF_MST</name>
<description>JQOVF_MST</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADRDY_SLV</name>
<description>ADRDY_SLV</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOSMP_SLV</name>
<description>EOSMP_SLV</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC_SLV</name>
<description>End of regular conversion of the slave ADC</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOS_SLV</name>
<description>End of regular sequence flag of the slave ADC</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR_SLV</name>
<description>Overrun flag of the slave ADC</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOC_SLV</name>
<description>End of injected conversion flag of the slave ADC</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOS_SLV</name>
<description>End of injected sequence flag of the slave ADC</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1_SLV</name>
<description>Analog watchdog 1 flag of the slave ADC</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD2_SLV</name>
<description>Analog watchdog 2 flag of the slave ADC</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD3_SLV</name>
<description>Analog watchdog 3 flag of the slave ADC</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JQOVF_SLV</name>
<description>Injected Context Queue Overflow flag of the slave ADC</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<displayName>CCR</displayName>
<description>ADC common control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUAL</name>
<description>Dual ADC mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DELAY</name>
<description>Delay between 2 sampling phases</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DMACFG</name>
<description>DMA configuration (for multi-ADC mode)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MDMA</name>
<description>Direct memory access mode for multi ADC mode</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKMODE</name>
<description>ADC clock mode</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>VREFEN</name>
<description>VREFINT enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSENSESEL</name>
<description> VTS selection</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VBATSEL</name>
<description>VBAT selection</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRESC</name>
<description>ADC prescaler</description>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CDR</name>
<displayName>CDR</displayName>
<description>ADC common regular data register for dual and triple modes</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RDATA_SLV</name>
<description>Regular data of the slave ADC</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>RDATA_MST</name>
<description>Regular data of the master ADC</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="ADC12_Common">
<name>ADC345_Common</name>
<baseAddress>0x50000700</baseAddress>
</peripheral>
<peripheral>
<name>FMAC</name>
<description>Filter Math Accelerator</description>
<groupName>FMAC</groupName>
<baseAddress>0x40021400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xC00</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FMAC</name>
<description>FMAC</description>
<value>101</value>
</interrupt>
<registers>
<register>
<name>X1BUFCFG</name>
<displayName>X1BUFCFG</displayName>
<description>FMAC X1 Buffer Configuration register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>X1_BASE</name>
<description>X1_BASE</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>X1_BUF_SIZE</name>
<description>X1_BUF_SIZE</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>FULL_WM</name>
<description>FULL_WM</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>X2BUFCFG</name>
<displayName>X2BUFCFG</displayName>
<description>FMAC X2 Buffer Configuration register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>X2_BASE</name>
<description>X1_BASE</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>X2_BUF_SIZE</name>
<description>X1_BUF_SIZE</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>YBUFCFG</name>
<displayName>YBUFCFG</displayName>
<description>FMAC Y Buffer Configuration register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>Y_BASE</name>
<description>X1_BASE</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>Y_BUF_SIZE</name>
<description>X1_BUF_SIZE</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>EMPTY_WM</name>
<description>EMPTY_WM</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>PARAM</name>
<displayName>PARAM</displayName>
<description>FMAC Parameter register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>START</name>
<description>START</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUNC</name>
<description>FUNC</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>R</name>
<description>R</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>Q</name>
<description>Q</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>P</name>
<description>P</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>FMAC Control register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RESET</name>
<description>RESET</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLIPEN</name>
<description>CLIPEN</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAWEN</name>
<description>DMAWEN</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAREN</name>
<description>DMAREN</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SATIEN</name>
<description>SATIEN</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNFLIEN</name>
<description>UNFLIEN</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFLIEN</name>
<description>OVFLIEN</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WIEN</name>
<description>WIEN</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RIEN</name>
<description>RIEN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>FMAC Status register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>YEMPTY</name>
<description>YEMPTY</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>X1FULL</name>
<description>X1FULL</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVFL</name>
<description>OVFL</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNFL</name>
<description>UNFL</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAT</name>
<description>SAT</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WDATA</name>
<displayName>WDATA</displayName>
<description>FMAC Write Data register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDATA</name>
<description>WDATA</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RDATA</name>
<displayName>RDATA</displayName>
<description>FMAC Read Data register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RDATA</name>
<description>RDATA</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CORDIC</name>
<description>CORDIC Co-processor</description>
<groupName>CORDIC</groupName>
<baseAddress>0x40020C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>Cordic</name>
<description>Cordic</description>
<value>100</value>
</interrupt>
<registers>
<register>
<name>CSR</name>
<displayName>CSR</displayName>
<description>CORDIC Control Status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FUNC</name>
<description>FUNC</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PRECISION</name>
<description>PRECISION</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SCALE</name>
<description>SCALE</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>IEN</name>
<description>IEN</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAREN</name>
<description>DMAREN</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAWEN</name>
<description>DMAWEN</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NRES</name>
<description>NRES</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NARGS</name>
<description>NARGS</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESSIZE</name>
<description>RESSIZE</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARGSIZE</name>
<description>ARGSIZE</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RRDY</name>
<description>RRDY</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WDATA</name>
<displayName>WDATA</displayName>
<description>FMAC Write Data register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ARG</name>
<description>ARG</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>RDATA</name>
<displayName>RDATA</displayName>
<description>FMAC Read Data register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RES</name>
<description>RES</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SAI</name>
<description>Serial audio interface</description>
<groupName>SAI</groupName>
<baseAddress>0x40015400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SAI</name>
<description>SAI</description>
<value>76</value>
</interrupt>
<registers>
<register>
<name>BCR1</name>
<displayName>BCR1</displayName>
<description>BConfiguration register 1</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000040</resetValue>
<fields>
<field>
<name>MCKEN</name>
<description>MCKEN</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSR</name>
<description>OSR</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCJDIV</name>
<description>Master clock divider</description>
<bitOffset>20</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>NODIV</name>
<description>No divider</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAEN</name>
<description>DMA enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAIBEN</name>
<description>Audio block B enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OutDri</name>
<description>Output drive</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MONO</name>
<description>Mono mode</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCEN</name>
<description>Synchronization enable</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKSTR</name>
<description>Clock strobing edge</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSBFIRST</name>
<description>Least significant bit first</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DS</name>
<description>Data size</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PRTCFG</name>
<description>Protocol configuration</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE</name>
<description>Audio block mode</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>BCR2</name>
<displayName>BCR2</displayName>
<description>BConfiguration register 2</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMP</name>
<description>Companding mode</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CPL</name>
<description>Complement bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTECN</name>
<description>Mute counter</description>
<bitOffset>7</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>MUTEVAL</name>
<description>Mute value</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTE</name>
<description>Mute</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRIS</name>
<description>Tristate management on data line</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFLUS</name>
<description>FIFO flush</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FTH</name>
<description>FIFO threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>BFRCR</name>
<displayName>BFRCR</displayName>
<description>BFRCR</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000007</resetValue>
<fields>
<field>
<name>FSOFF</name>
<description>Frame synchronization offset</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSPOL</name>
<description>Frame synchronization polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSDEF</name>
<description>Frame synchronization definition</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSALL</name>
<description>Frame synchronization active level length</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>FRL</name>
<description>Frame length</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>BSLOTR</name>
<displayName>BSLOTR</displayName>
<description>BSlot register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLOTEN</name>
<description>Slot enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>NBSLOT</name>
<description>Number of slots in an audio frame</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SLOTSZ</name>
<description>Slot size</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FBOFF</name>
<description>First bit offset</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>BIM</name>
<displayName>BIM</displayName>
<description>BInterrupt mask register2</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LFSDETIE</name>
<description>Late frame synchronization detection interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AFSDETIE</name>
<description>Anticipated frame synchronization detection interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNRDYIE</name>
<description>Codec not ready interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FREQIE</name>
<description>FIFO request interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WCKCFG</name>
<description>Wrong clock configuration interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTEDET</name>
<description>Mute detection interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRUDRIE</name>
<description>Overrun/underrun interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BSR</name>
<displayName>BSR</displayName>
<description>BStatus register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLVL</name>
<description>FIFO level threshold</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>LFSDET</name>
<description>Late frame synchronization detection</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AFSDET</name>
<description>Anticipated frame synchronization detection</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNRDY</name>
<description>Codec not ready</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FREQ</name>
<description>FIFO request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WCKCFG</name>
<description>Wrong clock configuration flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTEDET</name>
<description>Mute detection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRUDR</name>
<description>Overrun / underrun</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BCLRFR</name>
<displayName>BCLRFR</displayName>
<description>BClear flag register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LFSDET</name>
<description>Clear late frame synchronization detection flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAFSDET</name>
<description>Clear anticipated frame synchronization detection flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNRDY</name>
<description>Clear codec not ready flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WCKCFG</name>
<description>Clear wrong clock configuration flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTEDET</name>
<description>Mute detection flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRUDR</name>
<description>Clear overrun / underrun</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BDR</name>
<displayName>BDR</displayName>
<description>BData register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATA</name>
<description>Data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ACR1</name>
<displayName>ACR1</displayName>
<description>AConfiguration register 1</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000040</resetValue>
<fields>
<field>
<name>MCKEN</name>
<description>MCKEN</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSR</name>
<description>OSR</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCJDIV</name>
<description>Master clock divider</description>
<bitOffset>20</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>NODIV</name>
<description>No divider</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAEN</name>
<description>DMA enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAIAEN</name>
<description>Audio block A enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OutDri</name>
<description>Output drive</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MONO</name>
<description>Mono mode</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCEN</name>
<description>Synchronization enable</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKSTR</name>
<description>Clock strobing edge</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSBFIRST</name>
<description>Least significant bit first</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DS</name>
<description>Data size</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PRTCFG</name>
<description>Protocol configuration</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE</name>
<description>Audio block mode</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>ACR2</name>
<displayName>ACR2</displayName>
<description>AConfiguration register 2</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMP</name>
<description>Companding mode</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CPL</name>
<description>Complement bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTECN</name>
<description>Mute counter</description>
<bitOffset>7</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>MUTEVAL</name>
<description>Mute value</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTE</name>
<description>Mute</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRIS</name>
<description>Tristate management on data line</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFLUS</name>
<description>FIFO flush</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FTH</name>
<description>FIFO threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFRCR</name>
<displayName>AFRCR</displayName>
<description>AFRCR</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000007</resetValue>
<fields>
<field>
<name>FSOFF</name>
<description>Frame synchronization offset</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSPOL</name>
<description>Frame synchronization polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSDEF</name>
<description>Frame synchronization definition</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSALL</name>
<description>Frame synchronization active level length</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>FRL</name>
<description>Frame length</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ASLOTR</name>
<displayName>ASLOTR</displayName>
<description>ASlot register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLOTEN</name>
<description>Slot enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>NBSLOT</name>
<description>Number of slots in an audio frame</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SLOTSZ</name>
<description>Slot size</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FBOFF</name>
<description>First bit offset</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>AIM</name>
<displayName>AIM</displayName>
<description>AInterrupt mask register2</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LFSDET</name>
<description>Late frame synchronization detection interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AFSDETIE</name>
<description>Anticipated frame synchronization detection interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNRDYIE</name>
<description>Codec not ready interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FREQIE</name>
<description>FIFO request interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WCKCFG</name>
<description>Wrong clock configuration interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTEDET</name>
<description>Mute detection interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRUDRIE</name>
<description>Overrun/underrun interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ASR</name>
<displayName>ASR</displayName>
<description>AStatus register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLVL</name>
<description>FIFO level threshold</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>LFSDET</name>
<description>Late frame synchronization detection</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AFSDET</name>
<description>Anticipated frame synchronization detection</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNRDY</name>
<description>Codec not ready</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FREQ</name>
<description>FIFO request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WCKCFG</name>
<description>Wrong clock configuration flag. This bit is read only</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTEDET</name>
<description>Mute detection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRUDR</name>
<description>Overrun / underrun</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ACLRFR</name>
<displayName>ACLRFR</displayName>
<description>AClear flag register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LFSDET</name>
<description>Clear late frame synchronization detection flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAFSDET</name>
<description>Clear anticipated frame synchronization detection flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNRDY</name>
<description>Clear codec not ready flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WCKCFG</name>
<description>Clear wrong clock configuration flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTEDET</name>
<description>Mute detection flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRUDR</name>
<description>Clear overrun / underrun</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADR</name>
<displayName>ADR</displayName>
<description>AData register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATA</name>
<description>Data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PDMCR</name>
<displayName>PDMCR</displayName>
<description>PDM control register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PDMEN</name>
<description>PDMEN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MICNBR</name>
<description>MICNBR</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKEN1</name>
<description>CKEN1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKEN2</name>
<description>CKEN2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKEN3</name>
<description>CKEN3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKEN4</name>
<description>CKEN4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PDMDLY</name>
<displayName>PDMDLY</displayName>
<description>PDM delay register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DLYM1L</name>
<description>DLYM1L</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM1R</name>
<description>DLYM1R</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM2L</name>
<description>DLYM2L</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM2R</name>
<description>DLYM2R</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM3L</name>
<description>DLYM3L</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM3R</name>
<description>DLYM3R</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM4L</name>
<description>DLYM4L</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM4R</name>
<description>DLYM4R</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TAMP</name>
<description>Tamper and backup registers</description>
<groupName>TAMP</groupName>
<baseAddress>0x40002400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFF0000</resetValue>
<fields>
<field>
<name>TAMP1E</name>
<description>TAMP1E</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP2E</name>
<description>TAMP2E</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP3E</name>
<description>TAMP2E</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITAMP3E</name>
<description>ITAMP3E</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITAMP4E</name>
<description>ITAMP4E</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITAMP5E</name>
<description>ITAMP5E</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITAMP6E</name>
<description>ITAMP6E</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TAMP1NOER</name>
<description>TAMP1NOER</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP2NOER</name>
<description>TAMP2NOER</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP3NOER</name>
<description>TAMP3NOER</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP1MSK</name>
<description>TAMP1MSK</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP2MSK</name>
<description>TAMP2MSK</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP3MSK</name>
<description>TAMP3MSK</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP1TRG</name>
<description>TAMP1TRG</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP2TRG</name>
<description>TAMP2TRG</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP3TRG</name>
<description>TAMP3TRG</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FLTCR</name>
<displayName>FLTCR</displayName>
<description>TAMP filter control register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TAMPFREQ</name>
<description>TAMPFREQ</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TAMPFLT</name>
<description>TAMPFLT</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TAMPPRCH</name>
<description>TAMPPRCH</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TAMPPUDIS</name>
<description>TAMPPUDIS</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>TAMP interrupt enable register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TAMP1IE</name>
<description>TAMP1IE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP2IE</name>
<description>TAMP2IE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP3IE</name>
<description>TAMP3IE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITAMP3IE</name>
<description>ITAMP3IE</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITAMP4IE</name>
<description>ITAMP4IE</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITAMP5IE</name>
<description>ITAMP5IE</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITAMP6IE</name>
<description>ITAMP6IE</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>TAMP status register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TAMP1F</name>
<description>TAMP1F</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP2F</name>
<description>TAMP2F</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP3F</name>
<description>TAMP3F</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITAMP3F</name>
<description>ITAMP3F</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITAMP4F</name>
<description>ITAMP4F</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITAMP5F</name>
<description>ITAMP5F</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITAMP6F</name>
<description>ITAMP6F</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MISR</name>
<displayName>MISR</displayName>
<description>TAMP masked interrupt status register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TAMP1MF</name>
<description>TAMP1MF:</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP2MF</name>
<description>TAMP2MF</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP3MF</name>
<description>TAMP3MF</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITAMP3MF</name>
<description>ITAMP3MF</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITAMP4MF</name>
<description>ITAMP4MF</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITAMP5MF</name>
<description>ITAMP5MF</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITAMP6MF</name>
<description>ITAMP6MF</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCR</name>
<displayName>SCR</displayName>
<description>TAMP status clear register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTAMP1F</name>
<description>CTAMP1F</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTAMP2F</name>
<description>CTAMP2F</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTAMP3F</name>
<description>CTAMP3F</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CITAMP3F</name>
<description>CITAMP3F</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CITAMP4F</name>
<description>CITAMP4F</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CITAMP5F</name>
<description>CITAMP5F</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CITAMP6F</name>
<description>CITAMP6F</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP0R</name>
<displayName>BKP0R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP1R</name>
<displayName>BKP1R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP2R</name>
<displayName>BKP2R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP3R</name>
<displayName>BKP3R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x10C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP4R</name>
<displayName>BKP4R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x110</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP5R</name>
<displayName>BKP5R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x114</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP6R</name>
<displayName>BKP6R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x118</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP7R</name>
<displayName>BKP7R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x11C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP8R</name>
<displayName>BKP8R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x120</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP9R</name>
<displayName>BKP9R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x124</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP10R</name>
<displayName>BKP10R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x128</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP11R</name>
<displayName>BKP11R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x12C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP12R</name>
<displayName>BKP12R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x130</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP13R</name>
<displayName>BKP13R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x134</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP14R</name>
<displayName>BKP14R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x138</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP15R</name>
<displayName>BKP15R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x13C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP16R</name>
<displayName>BKP16R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x140</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP17R</name>
<displayName>BKP17R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x144</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP18R</name>
<displayName>BKP18R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x148</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP19R</name>
<displayName>BKP19R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x14C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP20R</name>
<displayName>BKP20R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x150</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP21R</name>
<displayName>BKP21R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x154</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP22R</name>
<displayName>BKP22R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x158</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP23R</name>
<displayName>BKP23R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x15C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP24R</name>
<displayName>BKP24R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x160</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP25R</name>
<displayName>BKP25R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x164</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP26R</name>
<displayName>BKP26R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x168</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP27R</name>
<displayName>BKP27R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x16C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP28R</name>
<displayName>BKP28R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x170</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP29R</name>
<displayName>BKP29R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x174</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP30R</name>
<displayName>BKP30R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x178</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP31R</name>
<displayName>BKP31R</displayName>
<description>TAMP backup register</description>
<addressOffset>0x17C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FPU</name>
<description>Floting point unit</description>
<groupName>FPU</groupName>
<baseAddress>0xE000EF34</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xD</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FPU</name>
<description>Floating point unit interrupt</description>
<value>81</value>
</interrupt>
<registers>
<register>
<name>FPCCR</name>
<displayName>FPCCR</displayName>
<description>Floating-point context control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LSPACT</name>
<description>LSPACT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USER</name>
<description>USER</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THREAD</name>
<description>THREAD</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HFRDY</name>
<description>HFRDY</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMRDY</name>
<description>MMRDY</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BFRDY</name>
<description>BFRDY</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MONRDY</name>
<description>MONRDY</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSPEN</name>
<description>LSPEN</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASPEN</name>
<description>ASPEN</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FPCAR</name>
<displayName>FPCAR</displayName>
<description>Floating-point context address register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDRESS</name>
<description>Location of unpopulated floating-point</description>
<bitOffset>3</bitOffset>
<bitWidth>29</bitWidth>
</field>
</fields>
</register>
<register>
<name>FPSCR</name>
<displayName>FPSCR</displayName>
<description>Floating-point status control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IOC</name>
<description>Invalid operation cumulative exception bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DZC</name>
<description>Division by zero cumulative exception bit.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFC</name>
<description>Overflow cumulative exception bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UFC</name>
<description>Underflow cumulative exception bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IXC</name>
<description>Inexact cumulative exception bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDC</name>
<description>Input denormal cumulative exception bit.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RMode</name>
<description>Rounding Mode control field</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FZ</name>
<description>Flush-to-zero mode control bit:</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DN</name>
<description>Default NaN mode control bit</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHP</name>
<description>Alternative half-precision control bit</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>V</name>
<description>Overflow condition code flag</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C</name>
<description>Carry condition code flag</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Z</name>
<description>Zero condition code flag</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>N</name>
<description>Negative condition code flag</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MPU</name>
<description>Memory protection unit</description>
<groupName>MPU</groupName>
<baseAddress>0xE000E084</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x15</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>TYPER</name>
<displayName>TYPER</displayName>
<description>MPU type register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0X00000800</resetValue>
<fields>
<field>
<name>SEPARATE</name>
<description>Separate flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DREGION</name>
<description>Number of MPU data regions</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IREGION</name>
<description>Number of MPU instruction regions</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<displayName>CTRL</displayName>
<description>MPU control register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>ENABLE</name>
<description>Enables the MPU</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HFNMIENA</name>
<description>Enables the operation of MPU during hard fault</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRIVDEFENA</name>
<description>Enable priviliged software access to default memory map</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RNR</name>
<displayName>RNR</displayName>
<description>MPU region number register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>REGION</name>
<description>MPU region</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RBAR</name>
<displayName>RBAR</displayName>
<description>MPU region base address register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>REGION</name>
<description>MPU region field</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>VALID</name>
<description>MPU region number valid</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDR</name>
<description>Region base address field</description>
<bitOffset>5</bitOffset>
<bitWidth>27</bitWidth>
</field>
</fields>
</register>
<register>
<name>RASR</name>
<displayName>RASR</displayName>
<description>MPU region attribute and size register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>ENABLE</name>
<description>Region enable bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIZE</name>
<description>Size of the MPU protection region</description>
<bitOffset>1</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SRD</name>
<description>Subregion disable bits</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>B</name>
<description>memory attribute</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C</name>
<description>memory attribute</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S</name>
<description>Shareable memory attribute</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEX</name>
<description>memory attribute</description>
<bitOffset>19</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>AP</name>
<description>Access permission</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>XN</name>
<description>Instruction access disable bit</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>STK</name>
<description>SysTick timer</description>
<groupName>STK</groupName>
<baseAddress>0xE000E010</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x11</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTRL</name>
<displayName>CTRL</displayName>
<description>SysTick control and status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>ENABLE</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TICKINT</name>
<description>SysTick exception request enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKSOURCE</name>
<description>Clock source selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COUNTFLAG</name>
<description>COUNTFLAG</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>LOAD</name>
<displayName>LOAD</displayName>
<description>SysTick reload value register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>RELOAD</name>
<description>RELOAD value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>VAL</name>
<displayName>VAL</displayName>
<description>SysTick current value register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>CURRENT</name>
<description>Current counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>CALIB</name>
<displayName>CALIB</displayName>
<description>SysTick calibration value register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>TENMS</name>
<description>Calibration value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
<field>
<name>SKEW</name>
<description>SKEW flag: Indicates whether the TENMS value is exact</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOREF</name>
<description>NOREF flag. Reads as zero</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCB</name>
<description>System control block</description>
<groupName>SCB</groupName>
<baseAddress>0xE000ED00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x41</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CPUID</name>
<displayName>CPUID</displayName>
<description>CPUID base register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x410FC241</resetValue>
<fields>
<field>
<name>Revision</name>
<description>Revision number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PartNo</name>
<description>Part number of the processor</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>Constant</name>
<description>Reads as 0xF</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>Variant</name>
<description>Variant number</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>Implementer</name>
<description>Implementer code</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICSR</name>
<displayName>ICSR</displayName>
<description>Interrupt control and state register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VECTACTIVE</name>
<description>Active vector</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>RETTOBASE</name>
<description>Return to base level</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VECTPENDING</name>
<description>Pending vector</description>
<bitOffset>12</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ISRPENDING</name>
<description>Interrupt pending flag</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PENDSTCLR</name>
<description>SysTick exception clear-pending bit</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PENDSTSET</name>
<description>SysTick exception set-pending bit</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PENDSVCLR</name>
<description>PendSV clear-pending bit</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PENDSVSET</name>
<description>PendSV set-pending bit</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NMIPENDSET</name>
<description>NMI set-pending bit.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>VTOR</name>
<displayName>VTOR</displayName>
<description>Vector table offset register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TBLOFF</name>
<description>Vector table base offset field</description>
<bitOffset>9</bitOffset>
<bitWidth>21</bitWidth>
</field>
</fields>
</register>
<register>
<name>AIRCR</name>
<displayName>AIRCR</displayName>
<description>Application interrupt and reset control register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VECTRESET</name>
<description>VECTRESET</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VECTCLRACTIVE</name>
<description>VECTCLRACTIVE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYSRESETREQ</name>
<description>SYSRESETREQ</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRIGROUP</name>
<description>PRIGROUP</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ENDIANESS</name>
<description>ENDIANESS</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VECTKEYSTAT</name>
<description>Register key</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCR</name>
<displayName>SCR</displayName>
<description>System control register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLEEPONEXIT</name>
<description>SLEEPONEXIT</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLEEPDEEP</name>
<description>SLEEPDEEP</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SEVEONPEND</name>
<description>Send Event on Pending bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<displayName>CCR</displayName>
<description>Configuration and control register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NONBASETHRDENA</name>
<description>Configures how the processor enters Thread mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USERSETMPEND</name>
<description>USERSETMPEND</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNALIGN__TRP</name>
<description>UNALIGN_ TRP</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIV_0_TRP</name>
<description>DIV_0_TRP</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BFHFNMIGN</name>
<description>BFHFNMIGN</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STKALIGN</name>
<description>STKALIGN</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHPR1</name>
<displayName>SHPR1</displayName>
<description>System handler priority registers</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRI_4</name>
<description>Priority of system handler 4</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PRI_5</name>
<description>Priority of system handler 5</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PRI_6</name>
<description>Priority of system handler 6</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHPR2</name>
<displayName>SHPR2</displayName>
<description>System handler priority registers</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRI_11</name>
<description>Priority of system handler 11</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHPR3</name>
<displayName>SHPR3</displayName>
<description>System handler priority registers</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRI_14</name>
<description>Priority of system handler 14</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PRI_15</name>
<description>Priority of system handler 15</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHCSR</name>
<displayName>SHCSR</displayName>
<description>System handler control and state register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEMFAULTACT</name>
<description>Memory management fault exception active bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSFAULTACT</name>
<description>Bus fault exception active bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USGFAULTACT</name>
<description>Usage fault exception active bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SVCALLACT</name>
<description>SVC call active bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MONITORACT</name>
<description>Debug monitor active bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PENDSVACT</name>
<description>PendSV exception active bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYSTICKACT</name>
<description>SysTick exception active bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USGFAULTPENDED</name>
<description>Usage fault exception pending bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEMFAULTPENDED</name>
<description>Memory management fault exception pending bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSFAULTPENDED</name>
<description>Bus fault exception pending bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SVCALLPENDED</name>
<description>SVC call pending bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEMFAULTENA</name>
<description>Memory management fault enable bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSFAULTENA</name>
<description>Bus fault enable bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USGFAULTENA</name>
<description>Usage fault enable bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFSR_UFSR_BFSR_MMFSR</name>
<displayName>CFSR_UFSR_BFSR_MMFSR</displayName>
<description>Configurable fault status register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IACCVIOL</name>
<description>Instruction access violation flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUNSTKERR</name>
<description>Memory manager fault on unstacking for a return from exception</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTKERR</name>
<description>Memory manager fault on stacking for exception entry.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MLSPERR</name>
<description>MLSPERR</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMARVALID</name>
<description>Memory Management Fault Address Register (MMAR) valid flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IBUSERR</name>
<description>Instruction bus error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRECISERR</name>
<description>Precise data bus error</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IMPRECISERR</name>
<description>Imprecise data bus error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNSTKERR</name>
<description>Bus fault on unstacking for a return from exception</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STKERR</name>
<description>Bus fault on stacking for exception entry</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSPERR</name>
<description>Bus fault on floating-point lazy state preservation</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BFARVALID</name>
<description>Bus Fault Address Register (BFAR) valid flag</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDEFINSTR</name>
<description>Undefined instruction usage fault</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INVSTATE</name>
<description>Invalid state usage fault</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INVPC</name>
<description>Invalid PC load usage fault</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOCP</name>
<description>No coprocessor usage fault.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNALIGNED</name>
<description>Unaligned access usage fault</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIVBYZERO</name>
<description>Divide by zero usage fault</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HFSR</name>
<displayName>HFSR</displayName>
<description>Hard fault status register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VECTTBL</name>
<description>Vector table hard fault</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCED</name>
<description>Forced hard fault</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEBUG_VT</name>
<description>Reserved for Debug use</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MMFAR</name>
<displayName>MMFAR</displayName>
<description>Memory management fault address register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MMFAR</name>
<description>Memory management fault address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BFAR</name>
<displayName>BFAR</displayName>
<description>Bus fault address register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BFAR</name>
<description>Bus fault address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFSR</name>
<displayName>AFSR</displayName>
<description>Auxiliary fault status register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMPDEF</name>
<description>Implementation defined</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>NVIC</name>
<description>Nested Vectored Interrupt Controller</description>
<groupName>NVIC</groupName>
<baseAddress>0xE000E100</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>ISER0</name>
<displayName>ISER0</displayName>
<description>Interrupt Set-Enable Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETENA</name>
<description>SETENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISER1</name>
<displayName>ISER1</displayName>
<description>Interrupt Set-Enable Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETENA</name>
<description>SETENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISER2</name>
<displayName>ISER2</displayName>
<description>Interrupt Set-Enable Register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETENA</name>
<description>SETENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISER3</name>
<displayName>ISER3</displayName>
<description>Interrupt Set-Enable Register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETENA</name>
<description>SETENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICER0</name>
<displayName>ICER0</displayName>
<description>Interrupt Clear-Enable Register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRENA</name>
<description>CLRENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICER1</name>
<displayName>ICER1</displayName>
<description>Interrupt Clear-Enable Register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRENA</name>
<description>CLRENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICER2</name>
<displayName>ICER2</displayName>
<description>Interrupt Clear-Enable Register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRENA</name>
<description>CLRENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICER3</name>
<displayName>ICER3</displayName>
<description>Interrupt Clear-Enable Register</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRENA</name>
<description>CLRENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISPR0</name>
<displayName>ISPR0</displayName>
<description>Interrupt Set-Pending Register</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETPEND</name>
<description>SETPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISPR1</name>
<displayName>ISPR1</displayName>
<description>Interrupt Set-Pending Register</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETPEND</name>
<description>SETPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISPR2</name>
<displayName>ISPR2</displayName>
<description>Interrupt Set-Pending Register</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETPEND</name>
<description>SETPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISPR3</name>
<displayName>ISPR3</displayName>
<description>Interrupt Set-Pending Register</description>
<addressOffset>0x10C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETPEND</name>
<description>SETPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICPR0</name>
<displayName>ICPR0</displayName>
<description>Interrupt Clear-Pending Register</description>
<addressOffset>0x180</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRPEND</name>
<description>CLRPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICPR1</name>
<displayName>ICPR1</displayName>
<description>Interrupt Clear-Pending Register</description>
<addressOffset>0x184</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRPEND</name>
<description>CLRPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICPR2</name>
<displayName>ICPR2</displayName>
<description>Interrupt Clear-Pending Register</description>
<addressOffset>0x188</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRPEND</name>
<description>CLRPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICPR3</name>
<displayName>ICPR3</displayName>
<description>Interrupt Clear-Pending Register</description>
<addressOffset>0x18C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRPEND</name>
<description>CLRPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IABR0</name>
<displayName>IABR0</displayName>
<description>Interrupt Active Bit Register</description>
<addressOffset>0x200</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACTIVE</name>
<description>ACTIVE</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IABR1</name>
<displayName>IABR1</displayName>
<description>Interrupt Active Bit Register</description>
<addressOffset>0x204</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACTIVE</name>
<description>ACTIVE</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IABR2</name>
<displayName>IABR2</displayName>
<description>Interrupt Active Bit Register</description>
<addressOffset>0x208</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACTIVE</name>
<description>ACTIVE</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IABR3</name>
<displayName>IABR3</displayName>
<description>Interrupt Active Bit Register</description>
<addressOffset>0x20C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACTIVE</name>
<description>ACTIVE</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR0</name>
<displayName>IPR0</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x300</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR1</name>
<displayName>IPR1</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x304</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR2</name>
<displayName>IPR2</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x308</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR3</name>
<displayName>IPR3</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x30C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR4</name>
<displayName>IPR4</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x310</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR5</name>
<displayName>IPR5</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x314</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR6</name>
<displayName>IPR6</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x318</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR7</name>
<displayName>IPR7</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x31C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR8</name>
<displayName>IPR8</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x320</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR9</name>
<displayName>IPR9</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x324</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR10</name>
<displayName>IPR10</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x328</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR11</name>
<displayName>IPR11</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x32C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR12</name>
<displayName>IPR12</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x330</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR13</name>
<displayName>IPR13</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x334</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR14</name>
<displayName>IPR14</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x338</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR15</name>
<displayName>IPR15</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x33C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR16</name>
<displayName>IPR16</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x340</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR17</name>
<displayName>IPR17</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x344</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR18</name>
<displayName>IPR18</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x348</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR19</name>
<displayName>IPR19</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x34C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR20</name>
<displayName>IPR20</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x350</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR21</name>
<displayName>IPR21</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x354</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
</register>
<register>
<name>IPR22</name>
<displayName>IPR22</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x358</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
</register>
<register>
<name>IPR23</name>
<displayName>IPR23</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x35C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
</register>
<register>
<name>IPR24</name>
<displayName>IPR24</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x360</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
</register>
<register>
<name>IPR25</name>
<displayName>IPR25</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x364</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
</register>
</registers>
</peripheral>
<peripheral>
<name>NVIC_STIR</name>
<description>Nested vectored interrupt
controller</description>
<groupName>NVIC</groupName>
<baseAddress>0xE000EF00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x5</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>STIR</name>
<displayName>STIR</displayName>
<description>Software trigger interrupt
register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INTID</name>
<description>Software generated interrupt
ID</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FPU_CPACR</name>
<description>Floating point unit CPACR</description>
<groupName>FPU</groupName>
<baseAddress>0xE000ED88</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x5</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CPACR</name>
<displayName>CPACR</displayName>
<description>Coprocessor access control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000000</resetValue>
<fields>
<field>
<name>CP</name>
<description>CP</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCB_ACTLR</name>
<description>System control block ACTLR</description>
<groupName>SCB</groupName>
<baseAddress>0xE000E008</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x5</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>ACTRL</name>
<displayName>ACTRL</displayName>
<description>Auxiliary control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DISMCYCINT</name>
<description>DISMCYCINT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISDEFWBUF</name>
<description>DISDEFWBUF</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISFOLD</name>
<description>DISFOLD</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISFPCA</name>
<description>DISFPCA</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISOOFP</name>
<description>DISOOFP</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FDCAN</name>
<description>FDCAN</description>
<groupName>FDCAN</groupName>
<baseAddress>0x4000A400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CREL</name>
<displayName>CREL</displayName>
<description>FDCAN Core Release Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x32141218</resetValue>
<fields>
<field>
<name>DAY</name>
<description>DAY</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MON</name>
<description>MON</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>YEAR</name>
<description>YEAR</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SUBSTEP</name>
<description>SUBSTEP</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STEP</name>
<description>STEP</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>REL</name>
<description>REL</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>ENDN</name>
<displayName>ENDN</displayName>
<description>FDCAN Core Release Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x87654321</resetValue>
<fields>
<field>
<name>ETV</name>
<description>ETV</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DBTP</name>
<displayName>DBTP</displayName>
<description>This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<resetValue>0x00000A33</resetValue>
<fields>
<field>
<name>DSJW</name>
<description>DSJW</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DTSEG2</name>
<description>DTSEG2</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DTSEG1</name>
<description>DTSEG1</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DBRP</name>
<description>DBRP</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TDC</name>
<description>TDC</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TEST</name>
<displayName>TEST</displayName>
<description>Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus.</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LBCK</name>
<description>LBCK</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TX</name>
<description>TX</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RX</name>
<description>RX</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RWD</name>
<displayName>RWD</displayName>
<description>The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock.</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDC</name>
<description>WDC</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WDV</name>
<description>WDV</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CCCR</name>
<displayName>CCCR</displayName>
<description>For details about setting and resetting of single bits see Software initialization.</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>INIT</name>
<description>INIT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CCE</name>
<description>CCE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ASM</name>
<description>ASM</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CSA</name>
<description>CSA</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CSR</name>
<description>CSR</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MON</name>
<description>MON</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DAR</name>
<description>DAR</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TEST</name>
<description>TEST</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FDOE</name>
<description>FDOE</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRSE</name>
<description>BRSE</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PXHD</name>
<description>PXHD</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EFBI</name>
<description>EFBI</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXP</name>
<description>TXP</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NISO</name>
<description>NISO</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>NBTP</name>
<displayName>NBTP</displayName>
<description>FDCAN_NBTP</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x06000A03</resetValue>
<fields>
<field>
<name>NTSEG2</name>
<description>NTSEG2</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>NTSEG1</name>
<description>NTSEG1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>NBRP</name>
<description>NBRP</description>
<bitOffset>16</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>NSJW</name>
<description>NSJW</description>
<bitOffset>25</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>TSCC</name>
<displayName>TSCC</displayName>
<description>FDCAN Timestamp Counter Configuration Register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSS</name>
<description>TSS</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TCP</name>
<description>TCP</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>TSCV</name>
<displayName>TSCV</displayName>
<description>FDCAN Timestamp Counter Value Register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSC</name>
<description>TSC</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TOCC</name>
<displayName>TOCC</displayName>
<description>FDCAN Timeout Counter Configuration Register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<resetValue>0xFFFF0000</resetValue>
<fields>
<field>
<name>ETOC</name>
<description>ETOC</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOS</name>
<description>TOS</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOP</name>
<description>TOP</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TOCV</name>
<displayName>TOCV</displayName>
<description>FDCAN Timeout Counter Value Register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>TOC</name>
<description>TOC</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ECR</name>
<displayName>ECR</displayName>
<description>FDCAN Error Counter Register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEC</name>
<description>TEC</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>REC</name>
<description>TREC</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>RP</name>
<description>RP</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEL</name>
<description>CEL</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>PSR</name>
<displayName>PSR</displayName>
<description>FDCAN Protocol Status Register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<resetValue>0x00000707</resetValue>
<fields>
<field>
<name>LEC</name>
<description>LEC</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ACT</name>
<description>ACT</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EP</name>
<description>EP</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EW</name>
<description>EW</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BO</name>
<description>BO</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DLEC</name>
<description>DLEC</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RESI</name>
<description>RESI</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RBRS</name>
<description>RBRS</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>REDL</name>
<description>REDL</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PXE</name>
<description>PXE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TDCV</name>
<description>TDCV</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TDCR</name>
<displayName>TDCR</displayName>
<description>FDCAN Transmitter Delay Compensation Register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TDCF</name>
<description>TDCF</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TDCO</name>
<description>TDCO</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>IR</name>
<displayName>IR</displayName>
<description>The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled.</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RF0N</name>
<description>RF0N</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0F</name>
<description>RF0F</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0L</name>
<description>RF0L</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1N</name>
<description>RF1N</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1F</name>
<description>RF1F</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1L</name>
<description>RF1L</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HPM</name>
<description>HPM</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC</name>
<description>TC</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCF</name>
<description>TCF</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TFE</name>
<description>TFE</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFN</name>
<description>TEFN</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFF</name>
<description>TEFF</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFL</name>
<description>TEFL</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSW</name>
<description>TSW</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MRAF</name>
<description>MRAF</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOO</name>
<description>TOO</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELO</name>
<description>ELO</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP</name>
<description>EP</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EW</name>
<description>EW</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BO</name>
<description>BO</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDI</name>
<description>WDI</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEA</name>
<description>PEA</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PED</name>
<description>PED</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARA</name>
<description>ARA</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IE</name>
<displayName>IE</displayName>
<description>The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line.</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RF0NE</name>
<description>RF0NE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0FE</name>
<description>RF0FE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0LE</name>
<description>RF0LE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1NE</name>
<description>RF1NE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1FE</name>
<description>RF1FE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1LE</name>
<description>RF1LE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HPME</name>
<description>HPME</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCE</name>
<description>TCE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCFE</name>
<description>TCFE</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TFEE</name>
<description>TFEE</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFNE</name>
<description>TEFNE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFFE</name>
<description>TEFFE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFLE</name>
<description>TEFLE</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSWE</name>
<description>TSWE</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MRAFE</name>
<description>MRAFE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOOE</name>
<description>TOOE</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELOE</name>
<description>ELOE</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPE</name>
<description>EPE</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EWE</name>
<description>EWE</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOE</name>
<description>BOE</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDIE</name>
<description>WDIE</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEAE</name>
<description>PEAE</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEDE</name>
<description>PEDE</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARAE</name>
<description>ARAE</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ILS</name>
<displayName>ILS</displayName>
<description>The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1].</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RxFIFO0</name>
<description>RxFIFO0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RxFIFO1</name>
<description>RxFIFO1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMSG</name>
<description>SMSG</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TFERR</name>
<description>TFERR</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MISC</name>
<description>MISC</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BERR</name>
<description>BERR</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERR</name>
<description>PERR</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ILE</name>
<displayName>ILE</displayName>
<description>Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1.</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EINT0</name>
<description>EINT0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EINT1</name>
<description>EINT1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXGFC</name>
<displayName>RXGFC</displayName>
<description>Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path.</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RRFE</name>
<description>RRFE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RRFS</name>
<description>RRFS</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ANFE</name>
<description>ANFE</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ANFS</name>
<description>ANFS</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>F1OM</name>
<description>F1OM</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>F0OM</name>
<description>F0OM</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LSS</name>
<description>LSS</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LSE</name>
<description>LSE</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>XIDAM</name>
<displayName>XIDAM</displayName>
<description>FDCAN Extended ID and Mask Register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x1FFFFFFF</resetValue>
<fields>
<field>
<name>EIDM</name>
<description>EIDM</description>
<bitOffset>0</bitOffset>
<bitWidth>29</bitWidth>
</field>
</fields>
</register>
<register>
<name>HPMS</name>
<displayName>HPMS</displayName>
<description>This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BIDX</name>
<description>BIDX</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MSI</name>
<description>MSI</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FIDX</name>
<description>FIDX</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>FLST</name>
<description>FLST</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXF0S</name>
<displayName>RXF0S</displayName>
<description>FDCAN Rx FIFO 0 Status Register</description>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F0FL</name>
<description>F0FL</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>F0GI</name>
<description>F0GI</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>F0PI</name>
<description>F0PI</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>F0F</name>
<description>F0F</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0L</name>
<description>RF0L</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXF0A</name>
<displayName>RXF0A</displayName>
<description>CAN Rx FIFO 0 Acknowledge Register</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F0AI</name>
<description>F0AI</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXF1S</name>
<displayName>RXF1S</displayName>
<description>FDCAN Rx FIFO 1 Status Register</description>
<addressOffset>0x98</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F1FL</name>
<description>F1FL</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>F1GI</name>
<description>F1GI</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>F1PI</name>
<description>F1PI</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>F1F</name>
<description>F1F</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1L</name>
<description>RF1L</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXF1A</name>
<displayName>RXF1A</displayName>
<description>FDCAN Rx FIFO 1 Acknowledge Register</description>
<addressOffset>0x9C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F1AI</name>
<description>F1AI</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXBC</name>
<displayName>TXBC</displayName>
<description>FDCAN Tx Buffer Configuration Register</description>
<addressOffset>0xC0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TFQM</name>
<description>TFQM</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXFQS</name>
<displayName>TXFQS</displayName>
<description>The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated).</description>
<addressOffset>0xC4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000003</resetValue>
<fields>
<field>
<name>TFFL</name>
<description>TFFL</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TFGI</name>
<description>TFGI</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TFQPI</name>
<description>TFQPI</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TFQF</name>
<description>TFQF</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXBRP</name>
<displayName>TXBRP</displayName>
<description>FDCAN Tx Buffer Request Pending Register</description>
<addressOffset>0xC8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TRP</name>
<description>TRP</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXBAR</name>
<displayName>TXBAR</displayName>
<description>FDCAN Tx Buffer Add Request Register</description>
<addressOffset>0xCC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AR</name>
<description>AR</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXBCR</name>
<displayName>TXBCR</displayName>
<description>FDCAN Tx Buffer Cancellation Request Register</description>
<addressOffset>0xD0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CR</name>
<description>CR</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXBTO</name>
<displayName>TXBTO</displayName>
<description>FDCAN Tx Buffer Transmission Occurred Register</description>
<addressOffset>0xD4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TO</name>
<description>TO</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXBCF</name>
<displayName>TXBCF</displayName>
<description>FDCAN Tx Buffer Cancellation Finished Register</description>
<addressOffset>0xD8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CF</name>
<description>CF</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXBTIE</name>
<displayName>TXBTIE</displayName>
<description>FDCAN Tx Buffer Transmission Interrupt Enable Register</description>
<addressOffset>0xDC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIE</name>
<description>TIE</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXBCIE</name>
<displayName>TXBCIE</displayName>
<description>FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register</description>
<addressOffset>0xE0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CFIE</name>
<description>CFIE</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXEFS</name>
<displayName>TXEFS</displayName>
<description>FDCAN Tx Event FIFO Status Register</description>
<addressOffset>0xE4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EFFL</name>
<description>EFFL</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>EFGI</name>
<description>EFGI</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EFPI</name>
<description>EFPI</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EFF</name>
<description>EFF</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFL</name>
<description>TEFL</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXEFA</name>
<displayName>TXEFA</displayName>
<description>FDCAN Tx Event FIFO Acknowledge Register</description>
<addressOffset>0xE8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EFAI</name>
<description>EFAI</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CKDIV</name>
<displayName>CKDIV</displayName>
<description>FDCAN CFG clock divider register</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PDIV</name>
<description>input clock divider. the APB clock could be divided prior to be used by the CAN sub</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="FDCAN">
<name>FDCAN1</name>
<baseAddress>0x40006400</baseAddress>
<interrupt>
<name>FDCAN1_IT0</name>
<description>FDCAN1 interrupt 0</description>
<value>21</value>
</interrupt>
<interrupt>
<name>FDCAN1_IT1</name>
<description>FDCAN1 interrupt 1</description>
<value>22</value>
</interrupt>
</peripheral>
<peripheral>
<name>UCPD1</name>
<description>UCPD1</description>
<groupName>UCPD</groupName>
<baseAddress>0x4000A000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UCPD1</name>
<description>UCPD1</description>
<value>63</value>
</interrupt>
<registers>
<register>
<name>CFG1</name>
<displayName>CFG1</displayName>
<description>UCPD configuration register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HBITCLKDIV</name>
<description>HBITCLKDIV</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>IFRGAP</name>
<description>IFRGAP</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TRANSWIN</name>
<description>TRANSWIN</description>
<bitOffset>11</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>PSC_USBPDCLK</name>
<description>PSC_USBPDCLK</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RXORDSETEN</name>
<description>RXORDSETEN</description>
<bitOffset>20</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>TXDMAEN</name>
<description>TXDMAEN</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXDMAEN</name>
<description>RXDMAEN</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UCPDEN</name>
<description>UCPDEN</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFG2</name>
<displayName>CFG2</displayName>
<description>UCPD configuration register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXFILTDIS</name>
<description>RXFILTDIS</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFILT2N3</name>
<description>RXFILT2N3</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCECLK</name>
<description>FORCECLK</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUPEN</name>
<description>WUPEN</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>UCPD configuration register 2</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXMODE</name>
<description>TXMODE</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TXSEND</name>
<description>TXSEND</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXHRST</name>
<description>TXHRST</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXMODE</name>
<description>RXMODE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PHYRXEN</name>
<description>PHYRXEN</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PHYCCSEL</name>
<description>PHYCCSEL</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ANASUBMODE</name>
<description>ANASUBMODE</description>
<bitOffset>7</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ANAMODE</name>
<description>ANAMODE</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCENABLE</name>
<description>CCENABLE</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FRSRXEN</name>
<description>FRSRXEN</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRSTX</name>
<description>FRSTX</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDCH</name>
<description>RDCH</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1TCDIS</name>
<description>CC1TCDIS</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2TCDIS</name>
<description>CC2TCDIS</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<displayName>IMR</displayName>
<description>UCPD Interrupt Mask Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXISIE</name>
<description>TXISIE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXMSGDISCIE</name>
<description>TXMSGDISCIE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXMSGSENTIE</name>
<description>TXMSGSENTIE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXMSGABTIE</name>
<description>TXMSGABTIE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HRSTDISCIE</name>
<description>HRSTDISCIE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HRSTSENTIE</name>
<description>HRSTSENTIE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUNDIE</name>
<description>TXUNDIE</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNEIE</name>
<description>RXNEIE</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXORDDETIE</name>
<description>RXORDDETIE</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXHRSTDETIE</name>
<description>RXHRSTDETIE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOVRIE</name>
<description>RXOVRIE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXMSGENDIE</name>
<description>RXMSGENDIE</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TYPECEVT1IE</name>
<description>TYPECEVT1IE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TYPECEVT2IE</name>
<description>TYPECEVT2IE</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRSEVTIE</name>
<description>FRSEVTIE</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>UCPD Status Register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXIS</name>
<description>TXIS</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXMSGDISC</name>
<description>TXMSGDISC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXMSGSENT</name>
<description>TXMSGSENT</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXMSGABT</name>
<description>TXMSGABT</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HRSTDISC</name>
<description>HRSTDISC</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HRSTSENT</name>
<description>HRSTSENT</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUND</name>
<description>TXUND</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNE</name>
<description>RXNE</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXORDDET</name>
<description>RXORDDET</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXHRSTDET</name>
<description>RXHRSTDET</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOVR</name>
<description>RXOVR</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXMSGEND</name>
<description>RXMSGEND</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXERR</name>
<description>RXERR</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TYPECEVT1</name>
<description>TYPECEVT1</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TYPECEVT2</name>
<description>TYPECEVT2</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TYPEC_VSTATE_CC1</name>
<description>TYPEC_VSTATE_CC1</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TYPEC_VSTATE_CC2</name>
<description>TYPEC_VSTATE_CC2</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FRSEVT</name>
<description>FRSEVT</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>UCPD Interrupt Clear Register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXMSGDISCCF</name>
<description>TXMSGDISCCF</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXMSGSENTCF</name>
<description>TXMSGSENTCF</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXMSGABTCF</name>
<description>TXMSGABTCF</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HRSTDISCCF</name>
<description>HRSTDISCCF</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HRSTSENTCF</name>
<description>HRSTSENTCF</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUNDCF</name>
<description>TXUNDCF</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXORDDETCF</name>
<description>RXORDDETCF</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXHRSTDETCF</name>
<description>RXHRSTDETCF</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOVRCF</name>
<description>RXOVRCF</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXMSGENDCF</name>
<description>RXMSGENDCF</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TYPECEVT1CF</name>
<description>TYPECEVT1CF</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TYPECEVT2CF</name>
<description>TYPECEVT2CF</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRSEVTCF</name>
<description>FRSEVTCF</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TX_ORDSET</name>
<displayName>TX_ORDSET</displayName>
<description>UCPD Tx Ordered Set Type Register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXORDSET</name>
<description>TXORDSET</description>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>TX_PAYSZ</name>
<displayName>TX_PAYSZ</displayName>
<description>UCPD Tx Paysize Register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXPAYSZ</name>
<description>TXPAYSZ</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXDR</name>
<displayName>TXDR</displayName>
<description>UCPD Tx Data Register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXDATA</name>
<description>TXDATA</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RX_ORDSET</name>
<displayName>RX_ORDSET</displayName>
<description>UCPD Rx Ordered Set Register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXORDSET</name>
<description>RXORDSET</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RXSOP3OF4</name>
<description>RXSOP3OF4</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSOPKINVALID</name>
<description>RXSOPKINVALID</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>RX_PAYSZ</name>
<displayName>RX_PAYSZ</displayName>
<description>UCPD Rx Paysize Register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXPAYSZ</name>
<description>RXPAYSZ</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXDR</name>
<displayName>RXDR</displayName>
<description>UCPD Rx Data Register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXDATA</name>
<description>RXDATA</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RX_ORDEXT1</name>
<displayName>RX_ORDEXT1</displayName>
<description>UCPD Rx Ordered Set Extension Register 1</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXSOPX1</name>
<description>RXSOPX1</description>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>RX_ORDEXT2</name>
<displayName>RX_ORDEXT2</displayName>
<description>UCPD Rx Ordered Set Extension Register 2</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXSOPX2</name>
<description>RXSOPX2</description>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>USB_FS_device</name>
<description>USB_FS_device</description>
<groupName>USB</groupName>
<baseAddress>0x40005C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>EP0R</name>
<displayName>EP0R</displayName>
<description>USB endpoint n register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EA</name>
<description>EA</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STAT_TX</name>
<description>STAT_TX</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_TX</name>
<description>DTOG_TX</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_TX</name>
<description>CTR_TX</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_KIND</name>
<description>EP_KIND</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_TYPE</name>
<description>EP_TYPE</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SETUP</name>
<description>SETUP</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STAT_RX</name>
<description>STAT_RX</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_RX</name>
<description>DTOG_RX</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_RX</name>
<description>CTR_RX</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EP1R</name>
<displayName>EP1R</displayName>
<description>USB endpoint n register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EA</name>
<description>EA</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STAT_TX</name>
<description>STAT_TX</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_TX</name>
<description>DTOG_TX</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_TX</name>
<description>CTR_TX</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_KIND</name>
<description>EP_KIND</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_TYPE</name>
<description>EP_TYPE</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SETUP</name>
<description>SETUP</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STAT_RX</name>
<description>STAT_RX</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_RX</name>
<description>DTOG_RX</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_RX</name>
<description>CTR_RX</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EP2R</name>
<displayName>EP2R</displayName>
<description>USB endpoint n register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EA</name>
<description>EA</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STAT_TX</name>
<description>STAT_TX</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_TX</name>
<description>DTOG_TX</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_TX</name>
<description>CTR_TX</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_KIND</name>
<description>EP_KIND</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_TYPE</name>
<description>EP_TYPE</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SETUP</name>
<description>SETUP</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STAT_RX</name>
<description>STAT_RX</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_RX</name>
<description>DTOG_RX</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_RX</name>
<description>CTR_RX</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EP3R</name>
<displayName>EP3R</displayName>
<description>USB endpoint n register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EA</name>
<description>EA</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STAT_TX</name>
<description>STAT_TX</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_TX</name>
<description>DTOG_TX</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_TX</name>
<description>CTR_TX</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_KIND</name>
<description>EP_KIND</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_TYPE</name>
<description>EP_TYPE</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SETUP</name>
<description>SETUP</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STAT_RX</name>
<description>STAT_RX</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_RX</name>
<description>DTOG_RX</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_RX</name>
<description>CTR_RX</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EP4R</name>
<displayName>EP4R</displayName>
<description>USB endpoint n register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EA</name>
<description>EA</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STAT_TX</name>
<description>STAT_TX</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_TX</name>
<description>DTOG_TX</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_TX</name>
<description>CTR_TX</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_KIND</name>
<description>EP_KIND</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_TYPE</name>
<description>EP_TYPE</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SETUP</name>
<description>SETUP</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STAT_RX</name>
<description>STAT_RX</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_RX</name>
<description>DTOG_RX</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_RX</name>
<description>CTR_RX</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EP5R</name>
<displayName>EP5R</displayName>
<description>USB endpoint n register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EA</name>
<description>EA</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STAT_TX</name>
<description>STAT_TX</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_TX</name>
<description>DTOG_TX</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_TX</name>
<description>CTR_TX</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_KIND</name>
<description>EP_KIND</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_TYPE</name>
<description>EP_TYPE</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SETUP</name>
<description>SETUP</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STAT_RX</name>
<description>STAT_RX</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_RX</name>
<description>DTOG_RX</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_RX</name>
<description>CTR_RX</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EP6R</name>
<displayName>EP6R</displayName>
<description>USB endpoint n register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EA</name>
<description>EA</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STAT_TX</name>
<description>STAT_TX</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_TX</name>
<description>DTOG_TX</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_TX</name>
<description>CTR_TX</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_KIND</name>
<description>EP_KIND</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_TYPE</name>
<description>EP_TYPE</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SETUP</name>
<description>SETUP</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STAT_RX</name>
<description>STAT_RX</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_RX</name>
<description>DTOG_RX</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_RX</name>
<description>CTR_RX</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EP7R</name>
<displayName>EP7R</displayName>
<description>USB endpoint n register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EA</name>
<description>EA</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STAT_TX</name>
<description>STAT_TX</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_TX</name>
<description>DTOG_TX</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_TX</name>
<description>CTR_TX</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_KIND</name>
<description>EP_KIND</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_TYPE</name>
<description>EP_TYPE</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SETUP</name>
<description>SETUP</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STAT_RX</name>
<description>STAT_RX</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_RX</name>
<description>DTOG_RX</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_RX</name>
<description>CTR_RX</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNTR</name>
<displayName>CNTR</displayName>
<description>USB control register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FRES</name>
<description>FRES</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDWN</name>
<description>PDWN</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LP_MODE</name>
<description>LP_MODE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSUSP</name>
<description>FSUSP</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESUME</name>
<description>RESUME</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>L1RESUME</name>
<description>L1RESUME</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>L1REQM</name>
<description>L1REQM</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESOFM</name>
<description>ESOFM</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOFM</name>
<description>SOFM</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESETM</name>
<description>RESETM</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SUSPM</name>
<description>SUSPM</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPM</name>
<description>WKUPM</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRM</name>
<description>ERRM</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PMAOVRM</name>
<description>PMAOVRM</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTRM</name>
<description>CTRM</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISTR</name>
<displayName>ISTR</displayName>
<description>USB interrupt status register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EP_ID</name>
<description>EP_ID</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DIR</name>
<description>DIR</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>L1REQ</name>
<description>L1REQ</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESOF</name>
<description>ESOF</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOF</name>
<description>SOF</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESET</name>
<description>RESET</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SUSP</name>
<description>SUSP</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUP</name>
<description>WKUP</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERR</name>
<description>ERR</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PMAOVR</name>
<description>PMAOVR</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR</name>
<description>CTR</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FNR</name>
<displayName>FNR</displayName>
<description>USB frame number register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FN</name>
<description>FN</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>LSOF</name>
<description>LSOF</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>LCK</name>
<description>LCK</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXDM</name>
<description>RXDM</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXDP</name>
<description>RXDP</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DADDR</name>
<displayName>DADDR</displayName>
<description>USB device address</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>EF</name>
<description>EF</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BTABLE</name>
<displayName>BTABLE</displayName>
<description>Buffer table address</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BTABLE</name>
<description>BTABLE</description>
<bitOffset>3</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CRS</name>
<description>CRS</description>
<groupName>CRS</groupName>
<baseAddress>0x40002000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>CRS control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00004000</resetValue>
<fields>
<field>
<name>SYNCOKIE</name>
<description>SYNC event OK interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SYNCWARNIE</name>
<description>SYNC warning interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ERRIE</name>
<description>Synchronization or trimming error interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ESYNCIE</name>
<description>Expected SYNC interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CEN</name>
<description>Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set, the CRS_CFGR register is write-protected and cannot be modified.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AUTOTRIMEN</name>
<description>Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWSYNC</name>
<description>Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TRIM</name>
<description>HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only.</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CFGR</name>
<displayName>CFGR</displayName>
<description>This register can be written only when the frequency error counter is disabled (CEN bit is cleared in CRS_CR). When the counter is enabled, this register is write-protected.</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x2022BB7F</resetValue>
<fields>
<field>
<name>RELOAD</name>
<description>Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section7.3.3: Frequency error measurement for more details about counter behavior.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>FELIM</name>
<description>Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP evaluation.</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SYNCDIV</name>
<description>SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal.</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SYNCSRC</name>
<description>SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs should be used as SYNC signal.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SYNCPOL</name>
<description>SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>CRS interrupt and status register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNCOKF</name>
<description>SYNC event OK flag This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCWARNF</name>
<description>SYNC warning flag This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRF</name>
<description>Error flag This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESYNCF</name>
<description>Expected SYNC flag This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCERR</name>
<description>SYNC error This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action should be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCMISS</name>
<description>SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action should be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRIMOVF</name>
<description>Trimming overflow or underflow This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FEDIR</name>
<description>Frequency error direction FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FECAP</name>
<description>Frequency error capture FECAP is the frequency error counter value latched in the time ofthe last SYNC event. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP usage.</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>CRS interrupt flag clear register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNCOKC</name>
<description>SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCWARNC</name>
<description>SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRC</name>
<description>Error clear flag Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESYNCC</name>
<description>Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>
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