STM32G441xx 1.9 STM32G441xx CM4 r0p1 little true true 4 false 8 32 0x20 0x0 0xFFFFFFFF CRC Cyclic redundancy check calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data register bits 0 32 IDR IDR Independent data register 0x4 0x20 read-write 0x00000000 IDR General-purpose 8-bit data register bits 0 32 CR CR Control register 0x8 0x20 0x00000000 REV_OUT Reverse output data 7 1 read-write REV_IN Reverse input data 5 2 read-write POLYSIZE Polynomial size 3 2 read-write RESET RESET bit 0 1 write-only INIT INIT Initial CRC value 0x10 0x20 read-write 0xFFFFFFFF CRC_INIT Programmable initial CRC value 0 32 POL POL polynomial 0x14 0x20 read-write 0x04C11DB7 POL Programmable polynomial 0 32 IWDG WinWATCHDOG IWDG 0x40003000 0x0 0x400 registers KR KR Key register 0x0 0x20 write-only 0x00000000 KEY Key value (write only, read 0x0000) 0 16 PR PR Prescaler register 0x4 0x20 read-write 0x00000000 PR Prescaler divider 0 3 RLR RLR Reload register 0x8 0x20 read-write 0x00000FFF RL Watchdog counter reload value 0 12 SR SR Status register 0xC 0x20 read-only 0x00000000 WVU Watchdog counter window value update 2 1 RVU Watchdog counter reload value update 1 1 PVU Watchdog prescaler value update 0 1 WINR WINR Window register 0x10 0x20 read-write 0x00000FFF WIN Watchdog counter window value 0 12 WWDG System window watchdog WWDG 0x40002C00 0x0 0x400 registers CR CR Control register 0x0 0x20 read-write 0x0000007F WDGA Activation bit 7 1 T 7-bit counter (MSB to LSB) 0 7 CFR CFR Configuration register 0x4 0x20 read-write 0x0000007F WDGTB Timer base 11 3 EWI Early wakeup interrupt 9 1 W 7-bit window value 0 7 SR SR Status register 0x8 0x20 read-write 0x00000000 EWIF Early wakeup interrupt flag 0 1 I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1_EV 31 I2C1_ER I2C1_ER 32 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 PE Peripheral enable 0 1 TXIE TX Interrupt enable 1 1 RXIE RX Interrupt enable 2 1 ADDRIE Address match interrupt enable (slave only) 3 1 NACKIE Not acknowledge received interrupt enable 4 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 ERRIE Error interrupts enable 7 1 DNF Digital noise filter 8 4 ANFOFF Analog noise filter OFF 12 1 TXDMAEN DMA transmission requests enable 14 1 RXDMAEN DMA reception requests enable 15 1 SBC Slave byte control 16 1 NOSTRETCH Clock stretching disable 17 1 WUPEN Wakeup from STOP enable 18 1 GCEN General call enable 19 1 SMBHEN SMBus Host address enable 20 1 SMBDEN SMBus Device Default address enable 21 1 ALERTEN SMBUS alert enable 22 1 PECEN PEC enable 23 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 PECBYTE Packet error checking byte 26 1 AUTOEND Automatic end mode (master mode) 25 1 RELOAD NBYTES reload mode 24 1 NBYTES Number of bytes 16 8 NACK NACK generation (slave mode) 15 1 STOP Stop generation (master mode) 14 1 START Start generation 13 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 ADD10 10-bit addressing mode (master mode) 11 1 RD_WRN Transfer direction (master mode) 10 1 SADD Slave address bit (master mode) 0 10 OAR1 OAR1 Own address register 1 0x8 0x20 read-write 0x00000000 OA1 Interface address 0 10 OA1MODE Own Address 1 10-bit mode 10 1 OA1EN Own Address 1 enable 15 1 OAR2 OAR2 Own address register 2 0xC 0x20 read-write 0x00000000 OA2 Interface address 1 7 OA2MSK Own Address 2 masks 8 3 OA2EN Own Address 2 enable 15 1 TIMINGR TIMINGR Timing register 0x10 0x20 read-write 0x00000000 SCLL SCL low period (master mode) 0 8 SCLH SCL high period (master mode) 8 8 SDADEL Data hold time 16 4 SCLDEL Data setup time 20 4 PRESC Timing prescaler 28 4 TIMEOUTR TIMEOUTR Status register 1 0x14 0x20 read-write 0x00000000 TIMEOUTA Bus timeout A 0 12 TIDLE Idle clock timeout detection 12 1 TIMOUTEN Clock timeout enable 15 1 TIMEOUTB Bus timeout B 16 12 TEXTEN Extended clock timeout enable 31 1 ISR ISR Interrupt and Status register 0x18 0x20 0x00000001 ADDCODE Address match code (Slave mode) 17 7 read-only DIR Transfer direction (Slave mode) 16 1 read-only BUSY Bus busy 15 1 read-only ALERT SMBus alert 13 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only PECERR PEC Error in reception 11 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only TCR Transfer Complete Reload 7 1 read-only TC Transfer Complete (master mode) 6 1 read-only STOPF Stop detection flag 5 1 read-only NACKF Not acknowledge received flag 4 1 read-only ADDR Address matched (slave mode) 3 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only TXIS Transmit interrupt status (transmitters) 1 1 read-write TXE Transmit data register empty (transmitters) 0 1 read-write ICR ICR Interrupt clear register 0x1C 0x20 write-only 0x00000000 ALERTCF Alert flag clear 13 1 TIMOUTCF Timeout detection flag clear 12 1 PECCF PEC Error flag clear 11 1 OVRCF Overrun/Underrun flag clear 10 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 STOPCF Stop detection flag clear 5 1 NACKCF Not Acknowledge flag clear 4 1 ADDRCF Address Matched flag clear 3 1 PECR PECR PEC register 0x20 0x20 read-only 0x00000000 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 0x20 read-only 0x00000000 RXDATA 8-bit receive data 0 8 TXDR TXDR Transmit data register 0x28 0x20 read-write 0x00000000 TXDATA 8-bit transmit data 0 8 I2C2 0x40005800 WWDG Window Watchdog interrupt 0 I2C2_EV I2C2_EV 33 I2C2_ER I2C2_ER 34 I2C3 0x40007800 I2C3_EV I2C3_EV 92 I2C3_ER I2C3_ER 93 FLASH Flash Flash 0x40022000 0x0 0x400 registers FLASH FLASH 4 ACR ACR Access control register 0x0 0x20 read-write 0x00000600 LATENCY Latency 0 4 PRFTEN Prefetch enable 8 1 ICEN Instruction cache enable 9 1 DCEN Data cache enable 10 1 ICRST Instruction cache reset 11 1 DCRST Data cache reset 12 1 RUN_PD Flash Power-down mode during Low-power run mode 13 1 SLEEP_PD Flash Power-down mode during Low-power sleep mode 14 1 DBG_SWEN Debug software enable 18 1 PDKEYR PDKEYR Power down key register 0x4 0x20 write-only 0x00000000 PDKEYR RUN_PD in FLASH_ACR key 0 32 KEYR KEYR Flash key register 0x8 0x20 write-only 0x00000000 KEYR KEYR 0 32 OPTKEYR OPTKEYR Option byte key register 0xC 0x20 write-only 0x00000000 OPTKEYR Option byte key 0 32 SR SR Status register 0x10 0x20 0x00000000 EOP End of operation 0 1 read-write OPERR Operation error 1 1 read-write PROGERR Programming error 3 1 read-write WRPERR Write protected error 4 1 read-write PGAERR Programming alignment error 5 1 read-write SIZERR Size error 6 1 read-write PGSERR Programming sequence error 7 1 read-write MISERR Fast programming data miss error 8 1 read-write FASTERR Fast programming error 9 1 read-write RDERR PCROP read error 14 1 read-write OPTVERR Option validity error 15 1 read-write BSY Busy 16 1 read-only CR CR Flash control register 0x14 0x20 read-write 0xC0000000 PG Programming 0 1 PER Page erase 1 1 MER1 Bank 1 Mass erase 2 1 PNB Page number 3 7 STRT Start 16 1 OPTSTRT Options modification start 17 1 FSTPG Fast programming 18 1 EOPIE End of operation interrupt enable 24 1 ERRIE Error interrupt enable 25 1 RDERRIE PCROP read error interrupt enable 26 1 OBL_LAUNCH Force the option byte loading 27 1 SEC_PROT1 SEC_PROT1 28 1 OPTLOCK Options Lock 30 1 LOCK FLASH_CR Lock 31 1 ECCR ECCR Flash ECC register 0x18 0x20 0x00000000 ADDR_ECC ECC fail address 0 19 read-only BK_ECC BK_ECC 21 1 read-only SYSF_ECC SYSF_ECC 22 1 read-only ECCIE ECCIE 24 1 read-write ECCC2 ECC correction 28 1 read-write ECCD2 ECC2 detection 29 1 read-write ECCC ECC correction 30 1 read-write ECCD ECC detection 31 1 read-write OPTR OPTR Flash option register 0x20 0x20 read-write 0xF0000000 RDP Read protection level 0 8 BOR_LEV BOR reset Level 8 3 nRST_STOP nRST_STOP 12 1 nRST_STDBY nRST_STDBY 13 1 nRST_SHDW nRST_SHDW 14 1 IDWG_SW Independent watchdog selection 16 1 IWDG_STOP Independent watchdog counter freeze in Stop mode 17 1 IWDG_STDBY Independent watchdog counter freeze in Standby mode 18 1 WWDG_SW Window watchdog selection 19 1 nBOOT1 Boot configuration 23 1 SRAM2_PE SRAM2 parity check enable 24 1 SRAM2_RST SRAM2 Erase when system reset 25 1 nSWBOOT0 nSWBOOT0 26 1 nBOOT0 nBOOT0 27 1 NRST_MODE NRST_MODE 28 2 IRHEN IRHEN 30 1 PCROP1SR PCROP1SR Flash Bank 1 PCROP Start address register 0x24 0x20 read-write 0xFFFF0000 PCROP1_STRT Bank 1 PCROP area start offset 0 15 PCROP1ER PCROP1ER Flash Bank 1 PCROP End address register 0x28 0x20 read-write 0x0FFF0000 PCROP1_END Bank 1 PCROP area end offset 0 15 PCROP_RDP PCROP area preserved when RDP level decreased 31 1 WRP1AR WRP1AR Flash Bank 1 WRP area A address register 0x2C 0x20 read-write 0x00000000 WRP1A_STRT Bank 1 WRP first area start offset 0 7 WRP1A_END Bank 1 WRP first area A end offset 16 7 WRP1BR WRP1BR Flash Bank 1 WRP area B address register 0x30 0x20 read-write 0x00000000 WRP1B_STRT Bank 1 WRP second area B end offset 0 7 WRP1B_END Bank 1 WRP second area B start offset 16 7 SEC1R SEC1R securable area bank1 register 0x70 0x20 read-write 0xFF00FF00 BOOT_LOCK BOOT_LOCK 16 1 SEC_SIZE1 SEC_SIZE1 0 8 DBGMCU Debug support DBGMCU 0xE0042000 0x0 0x400 registers IDCODE IDCODE MCU Device ID Code Register 0x0 0x20 read-only 0x0 DEV_ID Device Identifier 0 16 REV_ID Revision Identifier 16 16 CR CR Debug MCU Configuration Register 0x4 0x20 read-write 0x0 DBG_SLEEP Debug Sleep Mode 0 1 DBG_STOP Debug Stop Mode 1 1 DBG_STANDBY Debug Standby Mode 2 1 TRACE_IOEN Trace pin assignment control 5 1 TRACE_MODE Trace pin assignment control 6 2 APB1L_FZ APB1L_FZ APB Low Freeze Register 1 0x8 0x20 read-write 0x0 DBG_TIMER2_STOP Debug Timer 2 stopped when Core is halted 0 1 DBG_TIM3_STOP TIM3 counter stopped when core is halted 1 1 DBG_TIM4_STOP TIM4 counter stopped when core is halted 2 1 DBG_TIM5_STOP TIM5 counter stopped when core is halted 3 1 DBG_TIMER6_STOP Debug Timer 6 stopped when Core is halted 4 1 DBG_TIM7_STOP TIM7 counter stopped when core is halted 5 1 DBG_RTC_STOP Debug RTC stopped when Core is halted 10 1 DBG_WWDG_STOP Debug Window Wachdog stopped when Core is halted 11 1 DBG_IWDG_STOP Debug Independent Wachdog stopped when Core is halted 12 1 DBG_I2C1_STOP I2C1 SMBUS timeout mode stopped when core is halted 21 1 DBG_I2C2_STOP I2C2 SMBUS timeout mode stopped when core is halted 22 1 DBG_I2C3_STOP I2C3 SMBUS timeout mode stopped when core is halted 30 1 DBG_LPTIMER_STOP LPTIM1 counter stopped when core is halted 31 1 APB1H_FZ APB1H_FZ APB Low Freeze Register 2 0xC 0x20 read-write 0x0 DBG_I2C4_STOP DBG_I2C4_STOP 1 1 APB2_FZ APB2_FZ APB High Freeze Register 0x10 0x20 read-write 0x0 DBG_TIM1_STOP TIM1 counter stopped when core is halted 11 1 DBG_TIM8_STOP TIM8 counter stopped when core is halted 13 1 DBG_TIM15_STOP TIM15 counter stopped when core is halted 16 1 DBG_TIM16_STOP TIM16 counter stopped when core is halted 17 1 DBG_TIM17_STOP TIM17 counter stopped when core is halted 18 1 DBG_TIM20_STOP TIM20counter stopped when core is halted 20 1 DBG_HRTIM0_STOP DBG_HRTIM0_STOP 26 1 DBG_HRTIM1_STOP DBG_HRTIM0_STOP 27 1 DBG_HRTIM2_STOP DBG_HRTIM0_STOP 28 1 DBG_HRTIM3_STOP DBG_HRTIM0_STOP 29 1 RCC Reset and clock control RCC 0x40021000 0x0 0x400 registers RCC RCC global interrupt 5 RCC_CR RCC_CR Clock control register 0x00 0x20 0x00000063 0xFFFFFFFF HSION HSI16 clock enable Set and cleared by software. Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the HSI16 oscillator ON when STOPWUCK=1 or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator. This bit is set by hardware if the HSI16 is used directly or indirectly as system clock. 8 1 read-write B_0x0 HSI16 oscillator OFF 0x0 B_0x1 HSI16 oscillator ON 0x1 HSIKERON HSI16 always enable for peripheral kernels. Set and cleared by software to force HSI16 ON even in Stop modes. The HSI16 can only feed USARTs and I²Cs peripherals configured with HSI16 as kernel clock. Keeping the HSI16 ON in Stop mode allows to avoid slowing down the communication speed because of the HSI16 startup time. This bit has no effect on HSION value. 9 1 read-write B_0x0 No effect on HSI16 oscillator. 0x0 B_0x1 HSI16 oscillator is forced ON even in Stop mode. 0x1 HSIRDY HSI16 clock ready flag Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION. Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI16 clock cycles. 10 1 read-only B_0x0 HSI16 oscillator not ready 0x0 B_0x1 HSI16 oscillator ready 0x1 HSEON HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 16 1 read-write B_0x0 HSE oscillator OFF 0x0 B_0x1 HSE oscillator ON 0x1 HSERDY HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles. 17 1 read-only B_0x0 HSE oscillator not ready 0x0 B_0x1 HSE oscillator ready 0x1 HSEBYP HSE crystal oscillator bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. 18 1 read-write B_0x0 HSE crystal oscillator not bypassed 0x0 B_0x1 HSE crystal oscillator bypassed with external clock 0x1 CSSON Clock security system enable Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. 19 1 read-write B_0x0 Clock security system OFF (clock detector OFF) 0x0 B_0x1 Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not). 0x1 PLLON Main PLL enable Set and cleared by software to enable the main PLL. Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL clock is used as the system clock. 24 1 read-write B_0x0 PLL OFF 0x0 B_0x1 PLL ON 0x1 PLLRDY Main PLL clock ready flag Set by hardware to indicate that the main PLL is locked. 25 1 read-only B_0x0 PLL unlocked 0x0 B_0x1 PLL locked 0x1 RCC_ICSCR RCC_ICSCR Internal clock sources calibration register 0x04 0x20 0x40000000 0xFFFFFFFF HSICAL HSI16 clock calibration These bits are initialized at startup with the factory-programmed HSI16 calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value. 16 8 read-only HSITRIM HSI16 clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI16. The default value is 16, which, when added to the HSICAL value, should trim the HSI16 to 16 MHz � 1 %. 24 7 read-write RCC_CFGR RCC_CFGR Clock configuration register 0x08 0x20 0x00000005 0xFFFFFFFF SW System clock switch Set and cleared by software to select system clock source (SYSCLK). Configured by hardware to force HSI16 oscillator selection when exiting stop and standby modes or in case of failure of the HSE oscillator. 0 2 read-write B_0x0 Reserved, must be kept at reset value 0x0 B_0x1 HSI16 selected as system clock 0x1 B_0x2 HSE selected as system clock 0x2 B_0x3 PLL selected as system clock 0x3 SWS System clock switch status Set and cleared by hardware to indicate which clock source is used as system clock. 2 2 read-only B_0x0 Reserved, must be kept at reset value 0x0 B_0x1 HSI16 oscillator used as system clock 0x1 B_0x2 HSE used as system clock 0x2 B_0x3 PLL used as system clock 0x3 HPRE AHB prescaler Set and cleared by software to control the division factor of the AHB clock. Note: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details please refer to Section 6.1.5: Dynamic voltage scaling management). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account. 0xxx: SYSCLK not divided 4 4 read-write B_0x8 SYSCLK divided by 2 0x8 B_0x9 SYSCLK divided by 4 0x9 B_0xA SYSCLK divided by 8 0xA B_0xB SYSCLK divided by 16 0xB B_0xC SYSCLK divided by 64 0xC B_0xD SYSCLK divided by 128 0xD B_0xE SYSCLK divided by 256 0xE B_0xF SYSCLK divided by 512 0xF PPRE1 APB1 prescaler Set and cleared by software to control the division factor of the APB1 clock (PCLK1). 0xx: HCLK not divided 8 3 read-write B_0x4 HCLK divided by 2 0x4 B_0x5 HCLK divided by 4 0x5 B_0x6 HCLK divided by 8 0x6 B_0x7 HCLK divided by 16 0x7 PPRE2 APB2 prescaler Set and cleared by software to control the division factor of the APB2 clock (PCLK2). 0xx: HCLK not divided 11 3 read-write B_0x4 HCLK divided by 2 0x4 B_0x5 HCLK divided by 4 0x5 B_0x6 HCLK divided by 8 0x6 B_0x7 HCLK divided by 16 0x7 MCOSEL Microcontroller clock output Set and cleared by software. Others: Reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. 24 4 read-write B_0x0 MCO output disabled, no clock on MCO 0x0 B_0x1 SYSCLK system clock selected 0x1 B_0x2 Reserved, must be kept at reset value 0x2 B_0x3 HSI16 clock selected 0x3 B_0x4 HSE clock selected 0x4 B_0x5 Main PLL clock selected 0x5 B_0x6 LSI clock selected 0x6 B_0x7 LSE clock selected 0x7 B_0x8 Internal HSI48 clock selected 0x8 MCOPRE Microcontroller clock output prescaler These bits are set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. Others: not allowed 28 3 read-write B_0x0 MCO is divided by 1 0x0 B_0x1 MCO is divided by 2 0x1 B_0x2 MCO is divided by 4 0x2 B_0x3 MCO is divided by 8 0x3 B_0x4 MCO is divided by 16 0x4 RCC_PLLCFGR RCC_PLLCFGR PLL configuration register 0x0C 0x20 0x00001000 0xFFFFFFFF PLLSRC Main PLL entry clock source Set and cleared by software to select PLL clock source. These bits can be written only when PLL is disabled. In order to save power, when no PLL is used, the value of PLLSRC should be 00. 0 2 read-write B_0x0 No clock sent to PLL 0x0 B_0x1 No clock sent to PLL 0x1 B_0x2 HSI16 clock selected as PLL clock entry 0x2 B_0x3 HSE clock selected as PLL clock entry 0x3 PLLM Division factor for the main PLL input clock Set and cleared by software to divide the PLL input clock before the VCO. These bits can be written only when all PLLs are disabled. VCO input frequency = PLL input clock frequency / PLLM with 1 <= PLLM <= 16 ... Note: The software has to set these bits correctly to ensure that the VCO input frequency is within the range defined in the device datasheet. 4 4 read-write B_0x0 PLLM = 1 0x0 B_0x1 PLLM = 2 0x1 B_0x2 PLLM = 3 0x2 B_0x3 PLLM = 4 0x3 B_0x4 PLLM = 5 0x4 B_0x5 PLLM = 6 0x5 B_0x6 PLLM = 7 0x6 B_0x7 PLLM = 8 0x7 B_0x8 PLLSYSM = 9 0x8 B_0xF PLLSYSM= 16 0xF PLLN Main PLL multiplication factor for VCO Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled. VCO output frequency = VCO input frequency x PLLN with 8 =< PLLN =< 127 ... ... Note: The software has to set correctly these bits to assure that the VCO output frequency is within the range defined in the device datasheet. 8 7 read-write B_0x0 PLLN = 0 wrong configuration 0x0 B_0x1 PLLN = 1 wrong configuration 0x1 B_0x7 PLLN = 7 wrong configuration 0x7 B_0x8 PLLN = 8 0x8 B_0x9 PLLN = 9 0x9 B_0x7F PLLN = 127 0x7F PLLPEN Main PLL PLL “P” clock output enable Set and reset by software to enable the PLL “P” clock output of the PLL. In order to save power, when the PLL “P” clock output of the PLL is not used, the value of PLLPEN should be 0. 16 1 read-write B_0x0 PLL “P” clock output disable 0x0 B_0x1 PLL “P” clock output enable 0x1 PLLP Main PLL division factor for PLL “P” clock. Set and cleared by software to control the frequency of the main PLL output clock PLL “P” clock. These bits can be written only if PLL is disabled. When the PLLPDIV[4:0] is set to “00000”PLL “P” output clock frequency = VCO frequency / PLLP with PLLP =7, or 17 Note: The software has to set these bits correctly not to exceed 170 MHz on this domain. 17 1 read-write B_0x0 PLLP = 7 0x0 B_0x1 PLLP = 17 0x1 PLLQEN Main PLL “Q” clock output enable Set and reset by software to enable the PLL “Q” clock output of the PLL. In order to save power, when the PLL “Q” clock output of the PLL is not used, the value of PLLQEN should be 0. 20 1 read-write B_0x0 PLL “Q” clock output disable 0x0 B_0x1 PLL “Q” clock output enable 0x1 PLLQ Main PLL division factor for PLL “Q” clock. Set and cleared by software to control the frequency of the main PLL output clock PLL “Q” clock. This output can be selected for USB, RNG, SAI (48 MHz clock). These bits can be written only if PLL is disabled. PLL “Q” output clock frequency = VCO frequency / PLLQ with PLLQ = 2, 4, 6, or 8 Note: The software has to set these bits correctly not to exceed 170 MHz on this domain. 21 2 read-write B_0x0 PLLQ = 2 0x0 B_0x1 PLLQ = 4 0x1 B_0x2 PLLQ = 6 0x2 B_0x3 PLLQ = 8 0x3 PLLREN PLL “R” clock output enable Set and reset by software to enable the PLL “R” clock output of the PLL (used as system clock). This bit cannot be written when PLL “R” clock output of the PLL is used as System Clock. In order to save power, when the PLL “R” clock output of the PLL is not used, the value of PLLREN should be 0. 24 1 read-write B_0x0 PLL “R” clock output disable 0x0 B_0x1 PLL “R” clock output enable 0x1 PLLR Main PLL division factor for PLL “R” clock (system clock) Set and cleared by software to control the frequency of the main PLL output clock PLLCLK. This output can be selected as system clock. These bits can be written only if PLL is disabled. PLL “R” output clock frequency = VCO frequency / PLLR with PLLR = 2, 4, 6, or 8 Note: The software has to set these bits correctly not to exceed 170 MHz on this domain. 25 2 read-write B_0x0 PLLR = 2 0x0 B_0x1 PLLR = 4 0x1 B_0x2 PLLR = 6 0x2 B_0x3 PLLR = 8 0x3 PLLPDIV Main PLLP division factor Set and cleared by software to control the PLL “P” frequency. PLL “P” output clock frequency = VCO frequency / PLLPDIV. .... 27 5 read-write B_0x0 PLL “P” clock is controlled by the bit PLLP 0x0 B_0x1 Reserved. 0x1 B_0x2 PLL “P” clock = VCO / 2 0x2 B_0x1F PLL “P” clock = VCO / 31 0x1F RCC_CIER RCC_CIER Clock interrupt enable register 0x18 0x20 0x00000000 0xFFFFFFFF LSIRDYIE LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization. 0 1 read-write B_0x0 LSI ready interrupt disabled 0x0 B_0x1 LSI ready interrupt enabled 0x1 LSERDYIE LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization. 1 1 read-write B_0x0 LSE ready interrupt disabled 0x0 B_0x1 LSE ready interrupt enabled 0x1 HSIRDYIE HSI16 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization. 3 1 read-write B_0x0 HSI16 ready interrupt disabled 0x0 B_0x1 HSI16 ready interrupt enabled 0x1 HSERDYIE HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization. 4 1 read-write B_0x0 HSE ready interrupt disabled 0x0 B_0x1 HSE ready interrupt enabled 0x1 PLLRDYIE PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock. 5 1 read-write B_0x0 PLL lock interrupt disabled 0x0 B_0x1 PLL lock interrupt enabled 0x1 LSECSSIE LSE clock security system interrupt enable Set and cleared by software to enable/disable interrupt caused by the clock security system on LSE. 9 1 read-write B_0x0 Clock security interrupt caused by LSE clock failure disabled 0x0 B_0x1 Clock security interrupt caused by LSE clock failure enabled 0x1 HSI48RDYIE HSI48 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the internal HSI48 oscillator. 10 1 read-write B_0x0 HSI48 ready interrupt disabled 0x0 B_0x1 HSI48 ready interrupt enabled 0x1 RCC_CIFR RCC_CIFR Clock interrupt flag register 0x1C 0x20 0x00000000 0xFFFFFFFF LSIRDYF LSI ready interrupt flag Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit. 0 1 read-only B_0x0 No clock ready interrupt caused by the LSI oscillator 0x0 B_0x1 Clock ready interrupt caused by the LSI oscillator 0x1 LSERDYF LSE ready interrupt flag Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit. 1 1 read-only B_0x0 No clock ready interrupt caused by the LSE oscillator 0x0 B_0x1 Clock ready interrupt caused by the LSE oscillator 0x1 HSIRDYF HSI16 ready interrupt flag Set by hardware when the HSI16 clock becomes stable and HSIRDYDIE is set in a response to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit. 3 1 read-only B_0x0 No clock ready interrupt caused by the HSI16 oscillator 0x0 B_0x1 Clock ready interrupt caused by the HSI16 oscillator 0x1 HSERDYF HSE ready interrupt flag Set by hardware when the HSE clock becomes stable and HSERDYDIE is set. Cleared by software setting the HSERDYC bit. 4 1 read-only B_0x0 No clock ready interrupt caused by the HSE oscillator 0x0 B_0x1 Clock ready interrupt caused by the HSE oscillator 0x1 PLLRDYF PLL ready interrupt flag Set by hardware when the PLL locks and PLLRDYDIE is set. Cleared by software setting the PLLRDYC bit. 5 1 read-only B_0x0 No clock ready interrupt caused by PLL lock 0x0 B_0x1 Clock ready interrupt caused by PLL lock 0x1 CSSF Clock security system interrupt flag Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit. 8 1 read-only B_0x0 No clock security interrupt caused by HSE clock failure 0x0 B_0x1 Clock security interrupt caused by HSE clock failure 0x1 LSECSSF LSE Clock security system interrupt flag Set by hardware when a failure is detected in the LSE oscillator. Cleared by software setting the LSECSSC bit. 9 1 read-only B_0x0 No clock security interrupt caused by LSE clock failure 0x0 B_0x1 Clock security interrupt caused by LSE clock failure 0x1 HSI48RDYF HSI48 ready interrupt flag Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a response to setting the HSI48ON (refer to Clock recovery RC register (RCC_CRRCR)). Cleared by software setting the HSI48RDYC bit. 10 1 read-only B_0x0 No clock ready interrupt caused by the HSI48 oscillator 0x0 B_0x1 Clock ready interrupt caused by the HSI48 oscillator 0x1 RCC_CICR RCC_CICR Clock interrupt clear register 0x20 0x20 0x00000000 0xFFFFFFFF LSIRDYC LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag. 0 1 write-only B_0x0 No effect 0x0 B_0x1 LSIRDYF cleared 0x1 LSERDYC LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. 1 1 write-only B_0x0 No effect 0x0 B_0x1 LSERDYF cleared 0x1 HSIRDYC HSI16 ready interrupt clear This bit is set software to clear the HSIRDYF flag. 3 1 write-only B_0x0 No effect 0x0 B_0x1 Clear HSIRDYF flag 0x1 HSERDYC HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag. 4 1 write-only B_0x0 No effect 0x0 B_0x1 Clear HSERDYF flag 0x1 PLLRDYC PLL ready interrupt clear This bit is set by software to clear the PLLRDYF flag. 5 1 write-only B_0x0 No effect 0x0 B_0x1 Clear PLLRDYF flag 0x1 CSSC Clock security system interrupt clear This bit is set by software to clear the CSSF flag. 8 1 write-only B_0x0 No effect 0x0 B_0x1 Clear CSSF flag 0x1 LSECSSC LSE Clock security system interrupt clear This bit is set by software to clear the LSECSSF flag. 9 1 write-only B_0x0 No effect 0x0 B_0x1 Clear LSECSSF flag 0x1 HSI48RDYC HSI48 oscillator ready interrupt clear This bit is set by software to clear the HSI48RDYF flag. 10 1 write-only B_0x0 No effect 0x0 B_0x1 Clear the HSI48RDYC flag 0x1 RCC_AHB1RSTR RCC_AHB1RSTR AHB1 peripheral reset register 0x28 0x20 0x00000000 0xFFFFFFFF DMA1RST DMA1 reset Set and cleared by software. 0 1 read-write B_0x0 No effect 0x0 B_0x1 Reset DMA1 0x1 DMA2RST DMA2 reset Set and cleared by software. 1 1 read-write B_0x0 No effect 0x0 B_0x1 Reset DMA2 0x1 DMAMUX1RST Set and cleared by software. 2 1 read-write B_0x0 No effect 0x0 B_0x1 Reset DMAMUX1 0x1 CORDICRST Set and cleared by software 3 1 read-write B_0x0 No effect 0x0 B_0x1 Reset CORDIC 0x1 FMACRST Set and cleared by software 4 1 read-write B_0x0 No effect 0x0 B_0x1 Reset FMAC 0x1 FLASHRST Flash memory interface reset Set and cleared by software. This bit can be activated only when the Flash memory is in power down mode. 8 1 read-write B_0x0 No effect 0x0 B_0x1 Reset Flash memory interface 0x1 CRCRST CRC reset Set and cleared by software. 12 1 read-write B_0x0 No effect 0x0 B_0x1 Reset CRC 0x1 RCC_AHB2RSTR RCC_AHB2RSTR AHB2 peripheral reset register 0x2C 0x20 0x00000000 0xFFFFFFFF GPIOARST IO port A reset Set and cleared by software. 0 1 read-write B_0x0 No effect 0x0 B_0x1 Reset IO port A 0x1 GPIOBRST IO port B reset Set and cleared by software. 1 1 read-write B_0x0 No effect 0x0 B_0x1 Reset IO port B 0x1 GPIOCRST IO port C reset Set and cleared by software. 2 1 read-write B_0x0 No effect 0x0 B_0x1 Reset IO port C 0x1 GPIODRST IO port D reset Set and cleared by software. 3 1 read-write B_0x0 No effect 0x0 B_0x1 Reset IO port D 0x1 GPIOERST IO port E reset Set and cleared by software. 4 1 read-write B_0x0 No effect 0x0 B_0x1 Reset IO port E 0x1 GPIOFRST IO port F reset Set and cleared by software. 5 1 read-write B_0x0 No effect 0x0 B_0x1 Reset IO port F 0x1 GPIOGRST IO port G reset Set and cleared by software. 6 1 read-write B_0x0 No effect 0x0 B_0x1 Reset IO port G 0x1 ADC12RST ADC12 reset Set and cleared by software. 13 1 read-write B_0x0 No effect 0x0 B_0x1 Reset ADC12 interface 0x1 ADC345RST ADC345 reset Set and cleared by software. 14 1 read-write B_0x0 No effect 0x0 B_0x1 Reset ADC345 0x1 DAC1RST DAC1 reset Set and cleared by software. 16 1 read-write B_0x0 No effect 0x0 B_0x1 Reset DAC1 0x1 DAC2RST DAC2 reset Set and cleared by software. 17 1 read-write B_0x0 No effect 0x0 B_0x1 Reset DAC2 0x1 DAC3RST DAC3 reset Set and cleared by software. 18 1 read-write B_0x0 No effect 0x0 B_0x1 Reset DAC3 0x1 DAC4RST DAC4 reset Set and cleared by software. 19 1 read-write B_0x0 No effect 0x0 B_0x1 Reset DAC4 0x1 AESRST AESRST reset Set and cleared by software. 24 1 read-write B_0x0 No effect 0x0 B_0x1 Reset AES 0x1 RNGRST RNG reset Set and cleared by software. 26 1 read-write B_0x0 No effect 0x0 B_0x1 Reset RNG 0x1 RCC_AHB3RSTR RCC_AHB3RSTR AHB3 peripheral reset register 0x30 0x20 0x00000000 0xFFFFFFFF FMCRST Flexible static memory controller reset Set and cleared by software. 0 1 read-write B_0x0 No effect 0x0 B_0x1 Reset FSMC 0x1 QSPIRST QUADSPI reset Set and cleared by software. 8 1 read-write B_0x0 No effect 0x0 B_0x1 Reset QUADSPI 0x1 RCC_APB1RSTR1 RCC_APB1RSTR1 APB1 peripheral reset register 1 0x38 0x20 0x00000000 0xFFFFFFFF TIM2RST TIM2 timer reset Set and cleared by software. 0 1 read-write B_0x0 No effect 0x0 B_0x1 Reset TIM2 0x1 TIM3RST TIM3 timer reset Set and cleared by software. 1 1 read-write B_0x0 No effect 0x0 B_0x1 Reset TIM3 0x1 TIM4RST TIM3 timer reset Set and cleared by software. 2 1 read-write B_0x0 No effect 0x0 B_0x1 Reset TIM3 0x1 TIM5RST TIM5 timer reset Set and cleared by software. 3 1 read-write B_0x0 No effect 0x0 B_0x1 Reset TIM5 0x1 TIM6RST TIM6 timer reset Set and cleared by software. 4 1 read-write B_0x0 No effect 0x0 B_0x1 Reset TIM7 0x1 TIM7RST TIM7 timer reset Set and cleared by software. 5 1 read-write B_0x0 No effect 0x0 B_0x1 Reset TIM7 0x1 CRSRST CRS reset Set and cleared by software. 8 1 read-write B_0x0 No effect 0x0 B_0x1 Reset CRS 0x1 SPI2RST SPI2 reset Set and cleared by software. 14 1 read-write B_0x0 No effect 0x0 B_0x1 Reset SPI2 0x1 SPI3RST SPI3 reset Set and cleared by software. 15 1 read-write B_0x0 No effect 0x0 B_0x1 Reset SPI3 0x1 USART2RST USART2 reset Set and cleared by software. 17 1 read-write B_0x0 No effect 0x0 B_0x1 Reset USART2 0x1 USART3RST USART3 reset Set and cleared by software. 18 1 read-write B_0x0 No effect 0x0 B_0x1 Reset USART3 0x1 UART4RST UART4 reset Set and cleared by software. 19 1 read-write B_0x0 No effect 0x0 B_0x1 Reset UART4 0x1 UART5RST UART5 reset Set and cleared by software. 20 1 read-write B_0x0 No effect 0x0 B_0x1 Reset UART5 0x1 I2C1RST I2C1 reset Set and cleared by software. 21 1 read-write B_0x0 No effect 0x0 B_0x1 Reset I2C1 0x1 I2C2RST I2C2 reset Set and cleared by software. 22 1 read-write B_0x0 No effect 0x0 B_0x1 Reset I2C2 0x1 USBRST USB device reset Set and reset by software. 23 1 read-write B_0x0 No effect 0x0 B_0x1 Reset USB device 0x1 FDCANRST FDCAN reset Set and reset by software. 25 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the FDCAN 0x1 PWRRST Power interface reset Set and cleared by software. 28 1 read-write B_0x0 No effect 0x0 B_0x1 Reset PWR 0x1 I2C3RST I2C3 reset Set and cleared by software. 30 1 read-write B_0x0 No effect 0x0 B_0x1 Reset I2C3 interface 0x1 LPTIM1RST Low Power Timer 1 reset Set and cleared by software. 31 1 read-write B_0x0 No effect 0x0 B_0x1 Reset LPTIM1 0x1 RCC_APB1RSTR2 RCC_APB1RSTR2 APB1 peripheral reset register 2 0x3C 0x20 0x00000000 0xFFFFFFFF LPUART1RST Low-power UART 1 reset Set and cleared by software. 0 1 read-write B_0x0 No effect 0x0 B_0x1 Reset LPUART1 0x1 I2C4RST I2C4 reset Set and cleared by software 1 1 read-write B_0x0 No effect 0x0 B_0x1 Reset I2C4 0x1 UCPD1RST UCPD1 reset Set and cleared by software. 8 1 read-write B_0x0 No effect 0x0 B_0x1 Reset UCPD1 0x1 RCC_APB2RSTR RCC_APB2RSTR APB2 peripheral reset register 0x40 0x20 0x00000000 0xFFFFFFFF SYSCFGRST SYSCFG + COMP + OPAMP + VREFBUF reset 0 1 read-write B_0x0 No effect 0x0 B_0x1 Reset SYSCFG + COMP + OPAMP + VREFBUF 0x1 TIM1RST TIM1 timer reset Set and cleared by software. 11 1 read-write B_0x0 No effect 0x0 B_0x1 Reset TIM1 timer 0x1 SPI1RST SPI1 reset Set and cleared by software. 12 1 read-write B_0x0 No effect 0x0 B_0x1 Reset SPI1 0x1 TIM8RST TIM8 timer reset Set and cleared by software. 13 1 read-write B_0x0 No effect 0x0 B_0x1 Reset TIM8 timer 0x1 USART1RST USART1 reset Set and cleared by software. 14 1 read-write B_0x0 No effect 0x0 B_0x1 Reset USART1 0x1 SPI4RST SPI4 reset Set and cleared by software. 15 1 read-write B_0x0 No effect 0x0 B_0x1 Reset SPI4 0x1 TIM15RST TIM15 timer reset Set and cleared by software. 16 1 read-write B_0x0 No effect 0x0 B_0x1 Reset TIM15 timer 0x1 TIM16RST TIM16 timer reset Set and cleared by software. 17 1 read-write B_0x0 No effect 0x0 B_0x1 Reset TIM16 timer 0x1 TIM17RST TIM17 timer reset Set and cleared by software. 18 1 read-write B_0x0 No effect 0x0 B_0x1 Reset TIM17 timer 0x1 TIM20RST TIM20 reset Set and cleared by software. 20 1 read-write B_0x0 No effect 0x0 B_0x1 Reset TIM20 0x1 SAI1RST Serial audio interface 1 (SAI1) reset Set and cleared by software. 21 1 read-write B_0x0 No effect 0x0 B_0x1 Reset SAI1 0x1 HRTIM1RST HRTIM1 reset Set and cleared by software. 26 1 read-write B_0x0 No effect 0x0 B_0x1 Reset HRTIM1 0x1 RCC_AHB1ENR RCC_AHB1ENR AHB1 peripheral clock enable register 0x48 0x20 0x00000100 0xFFFFFFFF DMA1EN DMA1 clock enable Set and cleared by software. 0 1 read-write B_0x0 DMA1 clock disable 0x0 B_0x1 DMA1 clock enable 0x1 DMA2EN DMA2 clock enable Set and cleared by software. 1 1 read-write B_0x0 DMA2 clock disable 0x0 B_0x1 DMA2 clock enable 0x1 DMAMUX1EN DMAMUX1 clock enable Set and reset by software. 2 1 read-write B_0x0 DMAMUX1 clock disabled 0x0 B_0x1 DMAMUX1 clock enabled 0x1 CORDICEN CORDIC clock enable Set and reset by software. 3 1 read-write B_0x0 CORDIC clock disabled 0x0 B_0x1 CORDIC clock enabled 0x1 FMACEN FMAC enable Set and reset by software. 4 1 read-write B_0x0 FMAC clock disabled 0x0 B_0x1 FMAC clock enabled 0x1 FLASHEN Flash memory interface clock enable Set and cleared by software. This bit can be disabled only when the Flash is in power down mode. 8 1 read-write B_0x0 Flash memory interface clock disable 0x0 B_0x1 Flash memory interface clock enable 0x1 CRCEN CRC clock enable Set and cleared by software. 12 1 read-write B_0x0 CRC clock disable 0x0 B_0x1 CRC clock enable 0x1 RCC_AHB2ENR RCC_AHB2ENR AHB2 peripheral clock enable register 0x4C 0x20 0x00000000 0xFFFFFFFF GPIOAEN IO port A clock enable Set and cleared by software. 0 1 read-write B_0x0 IO port A clock disabled 0x0 B_0x1 IO port A clock enabled 0x1 GPIOBEN IO port B clock enable Set and cleared by software. 1 1 read-write B_0x0 IO port B clock disabled 0x0 B_0x1 IO port B clock enabled 0x1 GPIOCEN IO port C clock enable Set and cleared by software. 2 1 read-write B_0x0 IO port C clock disabled 0x0 B_0x1 IO port C clock enabled 0x1 GPIODEN IO port D clock enable Set and cleared by software. 3 1 read-write B_0x0 IO port D clock disabled 0x0 B_0x1 IO port D clock enabled 0x1 GPIOEEN IO port E clock enable Set and cleared by software. 4 1 read-write B_0x0 IO port E clock disabled 0x0 B_0x1 IO port E clock enabled 0x1 GPIOFEN IO port F clock enable Set and cleared by software. 5 1 read-write B_0x0 IO port F clock disabled 0x0 B_0x1 IO port F clock enabled 0x1 GPIOGEN IO port G clock enable Set and cleared by software. 6 1 read-write B_0x0 IO port G clock disabled 0x0 B_0x1 IO port G clock enabled 0x1 ADC12EN ADC12 clock enable Set and cleared by software. 13 1 read-write B_0x0 ADC12 clock disabled 0x0 B_0x1 ADC12 clock enabled 0x1 ADC345EN ADC345 clock enable Set and cleared by software 14 1 read-write B_0x0 ADC345 clock disabled 0x0 B_0x1 ADC345 clock enabled 0x1 DAC1EN DAC1 clock enable Set and cleared by software. 16 1 read-write B_0x0 DAC1 clock disabled 0x0 B_0x1 DAC1 clock enabled 0x1 DAC2EN DAC2 clock enable Set and cleared by software. 17 1 read-write B_0x0 DAC2 clock disabled 0x0 B_0x1 DAC2 clock enabled 0x1 DAC3EN DAC3 clock enable Set and cleared by software. 18 1 read-write B_0x0 DAC3 clock disabled 0x0 B_0x1 DAC3 clock enabled 0x1 DAC4EN DAC4 clock enable Set and cleared by software. 19 1 read-write B_0x0 DAC4 clock disabled 0x0 B_0x1 DAC4 clock enabled 0x1 AESEN AES clock enable Set and cleared by software. 24 1 read-write B_0x0 AES clock disabled 0x0 B_0x1 AES clock enabled 0x1 RNGEN RNG enable Set and cleared by software. 26 1 read-write B_0x0 RNG disabled 0x0 B_0x1 RNG enabled 0x1 RCC_AHB3ENR RCC_AHB3ENR AHB3 peripheral clock enable register 0x50 0x20 0x00000000 0xFFFFFFFF FMCEN Flexible static memory controller clock enable Set and cleared by software. 0 1 read-write B_0x0 FSMC clock disable 0x0 B_0x1 FSMC clock enable 0x1 QSPIEN QUADSPI memory interface clock enable Set and cleared by software. 8 1 read-write B_0x0 QUADSPI clock disable 0x0 B_0x1 QUADSPI clock enable 0x1 RCC_APB1ENR1 RCC_APB1ENR1 APB1 peripheral clock enable register 1 0x58 0x20 0x00000400 0xFFFFFFFF TIM2EN TIM2 timer clock enable Set and cleared by software. 0 1 read-write B_0x0 TIM2 clock disabled 0x0 B_0x1 TIM2 clock enabled 0x1 TIM3EN TIM3 timer clock enable Set and cleared by software. 1 1 read-write B_0x0 TIM3 clock disabled 0x0 B_0x1 TIM3 clock enabled 0x1 TIM4EN TIM4 timer clock enable Set and cleared by software. 2 1 read-write B_0x0 TIM4 clock disabled 0x0 B_0x1 TIM4 clock enabled 0x1 TIM5EN TIM5 timer clock enable Set and cleared by software. 3 1 read-write B_0x0 TIM5 clock disabled 0x0 B_0x1 TIM5 clock enabled 0x1 TIM6EN TIM6 timer clock enable Set and cleared by software. 4 1 read-write B_0x0 TIM6 clock disabled 0x0 B_0x1 TIM6 clock enabled 0x1 TIM7EN TIM7 timer clock enable Set and cleared by software. 5 1 read-write B_0x0 TIM7 clock disabled 0x0 B_0x1 TIM7 clock enabled 0x1 CRSEN CRS Recovery System clock enable Set and cleared by software. 8 1 read-write B_0x0 CRS clock disabled 0x0 B_0x1 CRS clock enabled 0x1 RTCAPBEN RTC APB clock enable Set and cleared by software 10 1 read-write B_0x0 RTC APB clock disabled 0x0 B_0x1 RTC APB clock enabled 0x1 WWDGEN Window watchdog clock enable Set by software to enable the window watchdog clock. Reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset. 11 1 read-write B_0x0 Window watchdog clock disabled 0x0 B_0x1 Window watchdog clock enabled 0x1 SPI2EN SPI2 clock enable Set and cleared by software. 14 1 read-write B_0x0 SPI2 clock disabled 0x0 B_0x1 SPI2 clock enabled 0x1 SPI3EN SPI3 clock enable Set and cleared by software. 15 1 read-write B_0x0 SPI3 clock disabled 0x0 B_0x1 SPI3 clock enabled 0x1 USART2EN USART2 clock enable Set and cleared by software. 17 1 read-write B_0x0 USART2 clock disabled 0x0 B_0x1 USART2 clock enabled 0x1 USART3EN USART3 clock enable Set and cleared by software. 18 1 read-write B_0x0 USART3 clock disabled 0x0 B_0x1 USART3 clock enabled 0x1 UART4EN UART4 clock enable Set and cleared by software. 19 1 read-write B_0x0 UART4 clock disabled 0x0 B_0x1 UART4 clock enabled 0x1 UART5EN UART5 clock enable Set and cleared by software. 20 1 read-write B_0x0 UART5 clock disabled 0x0 B_0x1 UART5 clock enabled 0x1 I2C1EN I2C1 clock enable Set and cleared by software. 21 1 read-write B_0x0 I2C1 clock disabled 0x0 B_0x1 I2C1 clock enabled 0x1 I2C2EN I2C2 clock enable Set and cleared by software. 22 1 read-write B_0x0 I2C2 clock disabled 0x0 B_0x1 I2C2 clock enabled 0x1 USBEN USB device clock enable Set and cleared by software. 23 1 read-write B_0x0 USB device clock disabled 0x0 B_0x1 USB device clock enabled 0x1 FDCANEN FDCAN clock enable Set and cleared by software. 25 1 read-write B_0x0 FDCAN clock disabled 0x0 B_0x1 FDCAN clock enabled 0x1 PWREN Power interface clock enable Set and cleared by software. 28 1 read-write B_0x0 Power interface clock disabled 0x0 B_0x1 Power interface clock enabled 0x1 I2C3EN I2C3 clock enable Set and cleared by software. 30 1 read-write B_0x0 I2C3 clock disabled 0x0 B_0x1 I2C3 clock enabled 0x1 LPTIM1EN Low power timer 1 clock enable Set and cleared by software. 31 1 read-write B_0x0 LPTIM1 clock disabled 0x0 B_0x1 LPTIM1 clock enabled 0x1 RCC_APB1ENR2 RCC_APB1ENR2 APB1 peripheral clock enable register 2 0x5C 0x20 0x00000000 0xFFFFFFFF LPUART1EN Low power UART 1 clock enable Set and cleared by software. 0 1 read-write B_0x0 LPUART1 clock disable 0x0 B_0x1 LPUART1 clock enable 0x1 I2C4EN I2C4 clock enable Set and cleared by software 1 1 read-write B_0x0 I2C4 clock disabled 0x0 B_0x1 I2C4 clock enabled 0x1 UCPD1EN UCPD1 clock enable Set and cleared by software. 8 1 read-write B_0x0 UCPD1 clock disable 0x0 B_0x1 UCPD1 clock enable 0x1 RCC_APB2ENR RCC_APB2ENR APB2 peripheral clock enable register 0x60 0x20 0x00000000 0xFFFFFFFF SYSCFGEN SYSCFG + COMP + VREFBUF + OPAMP clock enable Set and cleared by software. 0 1 read-write B_0x0 SYSCFG + COMP + VREFBUF + OPAMP clock disabled 0x0 B_0x1 SYSCFG + COMP + VREFBUF + OPAMP clock enabled 0x1 TIM1EN TIM1 timer clock enable Set and cleared by software. 11 1 read-write B_0x0 TIM1 timer clock disabled 0x0 B_0x1 TIM1P timer clock enabled 0x1 SPI1EN SPI1 clock enable Set and cleared by software. 12 1 read-write B_0x0 SPI1 clock disabled 0x0 B_0x1 SPI1 clock enabled 0x1 TIM8EN TIM8 timer clock enable Set and cleared by software. 13 1 read-write B_0x0 TIM8 timer clock disabled 0x0 B_0x1 TIM8 timer clock enabled 0x1 USART1EN USART1clock enable Set and cleared by software. 14 1 read-write B_0x0 USART1clock disabled 0x0 B_0x1 USART1clock enabled 0x1 SPI4EN SPI4 clock enable Set and cleared by software. 15 1 read-write B_0x0 SPI4 clock disabled 0x0 B_0x1 SPI4 clock enabled 0x1 TIM15EN TIM15 timer clock enable Set and cleared by software. 16 1 read-write B_0x0 TIM15 timer clock disabled 0x0 B_0x1 TIM15 timer clock enabled 0x1 TIM16EN TIM16 timer clock enable Set and cleared by software. 17 1 read-write B_0x0 TIM16 timer clock disabled 0x0 B_0x1 TIM16 timer clock enabled 0x1 TIM17EN TIM17 timer clock enable Set and cleared by software. 18 1 read-write B_0x0 TIM17 timer clock disabled 0x0 B_0x1 TIM17 timer clock enabled 0x1 TIM20EN TIM20 timer clock enable Set and cleared by software. 20 1 read-write B_0x0 TIM20 clock disabled 0x0 B_0x1 TIM20 clock enabled 0x1 SAI1EN SAI1 clock enable Set and cleared by software. 21 1 read-write B_0x0 SAI1 clock disabled 0x0 B_0x1 SAI1 clock enabled 0x1 HRTIM1EN HRTIM1 clock enable Set and cleared by software. 26 1 read-write B_0x0 HRTIM1 clock disabled 0x0 B_0x1 HRTIM1 clock enable 0x1 RCC_AHB1SMENR RCC_AHB1SMENR AHB1 peripheral clocks enable in Sleep and Stop modes register 0x68 0x20 0x0000130F 0xFFFFFFFF DMA1SMEN DMA1 clocks enable during Sleep and Stop modes Set and cleared by software. 0 1 read-write B_0x0 DMA1 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 DMA1 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 DMA2SMEN DMA2 clocks enable during Sleep and Stop modes Set and cleared by software during Sleep mode. 1 1 read-write B_0x0 DMA2 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 DMA2 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 DMAMUX1SMEN DMAMUX1 clock enable during Sleep and Stop modes. Set and cleared by software. 2 1 read-write B_0x0 DMAMUX1 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 DMAMUX1 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 CORDICSMEN CORDICSM clock enable. Set and cleared by software. 3 1 read-write B_0x0 CORDICSM clocks disabled. 0x0 B_0x1 CORDICSM clocks enabled. 0x1 FMACSMEN FMACSM clock enable. Set and cleared by software. 4 1 read-write B_0x0 FMACSM clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 FMACSM clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 FLASHSMEN Flash memory interface clocks enable during Sleep and Stop modes Set and cleared by software. 8 1 read-write B_0x0 Flash memory interface clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 Flash memory interface clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 SRAM1SMEN SRAM1 interface clocks enable during Sleep and Stop modes Set and cleared by software. 9 1 read-write B_0x0 SRAM1 interface clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 SRAM1 interface clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 CRCSMEN CRC clocks enable during Sleep and Stop modes Set and cleared by software. 12 1 read-write B_0x0 CRC clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 CRC clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 RCC_AHB2SMENR RCC_AHB2SMENR AHB2 peripheral clocks enable in Sleep and Stop modes register 0x6C 0x20 0x050F667F 0xFFFFFFFF GPIOASMEN IO port A clocks enable during Sleep and Stop modes Set and cleared by software. 0 1 read-write B_0x0 IO port A clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 IO port A clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 GPIOBSMEN IO port B clocks enable during Sleep and Stop modes Set and cleared by software. 1 1 read-write B_0x0 IO port B clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 IO port B clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 GPIOCSMEN IO port C clocks enable during Sleep and Stop modes Set and cleared by software. 2 1 read-write B_0x0 IO port C clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 IO port C clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 GPIODSMEN IO port D clocks enable during Sleep and Stop modes Set and cleared by software. 3 1 read-write B_0x0 IO port D clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 IO port D clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 GPIOESMEN IO port E clocks enable during Sleep and Stop modes Set and cleared by software. 4 1 read-write B_0x0 IO port E clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 IO port E clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 GPIOFSMEN IO port F clocks enable during Sleep and Stop modes Set and cleared by software. 5 1 read-write B_0x0 IO port F clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 IO port F clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 GPIOGSMEN IO port G clocks enable during Sleep and Stop modes Set and cleared by software. 6 1 read-write B_0x0 IO port G clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 IO port G clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 CCMSRAMSMEN CCM SRAM interface clocks enable during Sleep and Stop modes Set and cleared by software. 9 1 read-write B_0x0 CCM SRAM interface clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 CCM SRAM interface clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 SRAM2SMEN SRAM2 interface clocks enable during Sleep and Stop modes Set and cleared by software. 10 1 read-write B_0x0 SRAM2 interface clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 SRAM2 interface clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 ADC12SMEN ADC12 clocks enable during Sleep and Stop modes Set and cleared by software. 13 1 read-write B_0x0 ADC12 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 ADC12 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 ADC345SMEN ADC345 clock enable Set and cleared by software. 14 1 read-write B_0x0 ADC345 clock disabled 0x0 B_0x1 ADC345 clock enabled 0x1 DAC1SMEN DAC1 clock enable Set and cleared by software. 16 1 read-write B_0x0 DAC1 clock disabled 0x0 B_0x1 DAC1 clock enabled during sleep and stop modes 0x1 DAC2SMEN DAC2 clock enable Set and cleared by software. 17 1 read-write B_0x0 DAC2 clock disabled 0x0 B_0x1 DAC2 clock enabled during sleep and stop modes 0x1 DAC3SMEN DAC3 clock enable Set and cleared by software. 18 1 read-write B_0x0 DAC3 clock disabled 0x0 B_0x1 DAC3 clock enabled during sleep and stop modes 0x1 DAC4SMEN DAC4 clock enable Set and cleared by software. 19 1 read-write B_0x0 DAC4 clock disabled 0x0 B_0x1 DAC4 clock enabled during sleep and stop modes 0x1 AESSMEN AESM clocks enable Set and cleared by software. 24 1 read-write B_0x0 AESM clocks disabled 0x0 B_0x1 AESM clocks enabled 0x1 RNGEN RNG enable Set and cleared by software. 26 1 read-write B_0x0 RNG disabled 0x0 B_0x1 RNG enabled 0x1 RCC_AHB3SMENR RCC_AHB3SMENR AHB3 peripheral clocks enable in Sleep and Stop modes register 0x70 0x20 0x00000101 0xFFFFFFFF FMCSMEN Flexible static memory controller clocks enable during Sleep and Stop modes Set and cleared by software. 0 1 read-write B_0x0 FSMC clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 FSMC clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 QSPISMEN QUADSPI memory interface clock enable during Sleep and Stop modes Set and cleared by software. 8 1 read-write B_0x0 QUADSPI clock disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 QUADSPI clock enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 RCC_APB1SMENR1 RCC_APB1SMENR1 APB1 peripheral clocks enable in Sleep and Stop modes register 1 0x78 0x20 0xD2FECD3F 0xFFFFFFFF TIM2SMEN TIM2 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0 1 read-write B_0x0 TIM2 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 TIM2 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 TIM3SMEN TIM3 timer clocks enable during Sleep and Stop modes Set and cleared by software. 1 1 read-write B_0x0 TIM3 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 TIM3 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 TIM4SMEN TIM4 timer clocks enable during Sleep and Stop modes Set and cleared by software. 2 1 read-write B_0x0 TIM4 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 TIM4 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 TIM5SMEN TIM5 timer clocks enable during Sleep and Stop modes Set and cleared by software. 3 1 read-write B_0x0 TIM5 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 TIM5 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 TIM6SMEN TIM6 timer clocks enable during Sleep and Stop modes Set and cleared by software. 4 1 read-write B_0x0 TIM6 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 TIM6 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 TIM7SMEN TIM7 timer clocks enable during Sleep and Stop modes Set and cleared by software. 5 1 read-write B_0x0 TIM7 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 TIM7 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 CRSSMEN CRS timer clocks enable during Sleep and Stop modes Set and cleared by software. 8 1 read-write B_0x0 CRS clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 CRS clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 RTCAPBSMEN RTC APB clock enable during Sleep and Stop modes Set and cleared by software 10 1 read-write B_0x0 RTC APB clock disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 RTC APB clock enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 WWDGSMEN Window watchdog clocks enable during Sleep and Stop modes Set and cleared by software. This bit is forced to ‘1’ by hardware when the hardware WWDG option is activated. 11 1 read-write B_0x0 Window watchdog clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 Window watchdog clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 SPI2SMEN SPI2 clocks enable during Sleep and Stop modes Set and cleared by software. 14 1 read-write B_0x0 SPI2 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 SPI2 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 SPI3SMEN SPI3 clocks enable during Sleep and Stop modes Set and cleared by software. 15 1 read-write B_0x0 SPI3 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 SPI3 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 USART2SMEN USART2 clocks enable during Sleep and Stop modes Set and cleared by software. 17 1 read-write B_0x0 USART2 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 USART2 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 USART3SMEN USART3 clocks enable during Sleep and Stop modes Set and cleared by software. 18 1 read-write B_0x0 USART3 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 USART3 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 UART4SMEN UART4 clocks enable during Sleep and Stop modes Set and cleared by software. 19 1 read-write B_0x0 UART4 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 UART4 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 UART5SMEN UART5 clocks enable during Sleep and Stop modes Set and cleared by software. 20 1 read-write B_0x0 UART5 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 UART5 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 I2C1SMEN I2C1 clocks enable during Sleep and Stop modes Set and cleared by software. 21 1 read-write B_0x0 I2C1 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 I2C1 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 I2C2SMEN I2C2 clocks enable during Sleep and Stop modes Set and cleared by software. 22 1 read-write B_0x0 I2C2 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 I2C2 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 USBSMEN USB device clocks enable during Sleep and Stop modes Set and cleared by software. 23 1 read-write B_0x0 USB device clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 USB device clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 FDCANSMEN FDCAN clocks enable during Sleep and Stop modes Set and cleared by software. 25 1 read-write B_0x0 FDCAN clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 FDCAN clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 PWRSMEN Power interface clocks enable during Sleep and Stop modes Set and cleared by software. 28 1 read-write B_0x0 Power interface clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 Power interface clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 I2C3SMEN I2C3 clocks enable during Sleep and Stop modes Set and cleared by software. 30 1 read-write B_0x0 I2C3 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 I2C3 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 LPTIM1SMEN Low power timer 1 clocks enable during Sleep and Stop modes Set and cleared by software. 31 1 read-write B_0x0 LPTIM1 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 LPTIM1 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 RCC_APB1SMENR2 RCC_APB1SMENR2 APB1 peripheral clocks enable in Sleep and Stop modes register 2 0x7C 0x20 0x00000103 0xFFFFFFFF LPUART1SMEN Low power UART 1 clocks enable during Sleep and Stop modes Set and cleared by software. 0 1 read-write B_0x0 LPUART1 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 LPUART1 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 I2C4SMEN I2C4 clocks enable during Sleep and Stop modes Set and cleared by software 1 1 read-write B_0x0 I2C4 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 I2C4 clock enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 UCPD1SMEN UCPD1 clocks enable during Sleep and Stop modes Set and cleared by software. 8 1 read-write B_0x0 UCPD1 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 UCPD1 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 RCC_APB2SMENR RCC_APB2SMENR APB2 peripheral clocks enable in Sleep and Stop modes register 0x80 0x20 0x0437F801 0xFFFFFFFF SYSCFGSMEN SYSCFG + COMP + VREFBUF + OPAMP clocks enable during Sleep and Stop modes Set and cleared by software. 0 1 read-write B_0x0 SYSCFG + COMP + VREFBUF + OPAMP clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 SYSCFG + COMP + VREFBUF + OPAMP clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 TIM1SMEN TIM1 timer clocks enable during Sleep and Stop modes Set and cleared by software. 11 1 read-write B_0x0 TIM1 timer clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 TIM1P timer clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 SPI1SMEN SPI1 clocks enable during Sleep and Stop modes Set and cleared by software. 12 1 read-write B_0x0 SPI1 clocks disabled by the clock gating during⁽¹⁾ Sleep and Stop modes 0x0 B_0x1 SPI1 clocks enabled by the clock gating during⁽¹⁾ Sleep and Stop modes 0x1 TIM8SMEN TIM8 timer clocks enable during Sleep and Stop modes Set and cleared by software. 13 1 read-write B_0x0 TIM8 timer clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 TIM8 timer clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 USART1SMEN USART1clocks enable during Sleep and Stop modes Set and cleared by software. 14 1 read-write B_0x0 USART1clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 USART1clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 SPI4SMEN SPI4 timer clocks enable during Sleep and Stop modes Set and cleared by software. 15 1 read-write B_0x0 SPI4 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 SPI4 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop mode 0x1 TIM15SMEN TIM15 timer clocks enable during Sleep and Stop modes Set and cleared by software. 16 1 read-write B_0x0 TIM15 timer clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 TIM15 timer clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop mode 0x1 TIM16SMEN TIM16 timer clocks enable during Sleep and Stop modes Set and cleared by software. 17 1 read-write B_0x0 TIM16 timer clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 TIM16 timer clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 TIM17SMEN TIM17 timer clocks enable during Sleep and Stop modes Set and cleared by software. 18 1 read-write B_0x0 TIM17 timer clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 TIM17 timer clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 TIM20SMEN TIM20 timer clocks enable during Sleep and Stop modes Set and cleared by software. 20 1 read-write B_0x0 TIM20 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 TIM20 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 SAI1SMEN SAI1 clocks enable during Sleep and Stop modes Set and cleared by software. 21 1 read-write B_0x0 SAI1 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 SAI1 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 HRTIM1SMEN HRTIM1 timer clocks enable during Sleep and Stop modes Set and cleared by software. 26 1 read-write B_0x0 HRTIM1 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x0 B_0x1 HRTIM1 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes 0x1 RCC_CCIPR RCC_CCIPR Peripherals independent clock configuration register 0x88 0x20 0x00000000 0xFFFFFFFF USART1SEL USART1 clock source selection This bit is set and cleared by software to select the USART1 clock source. 0 2 read-write B_0x0 PCLK selected as USART1 clock 0x0 B_0x1 System clock (SYSCLK) selected as USART1 clock 0x1 B_0x2 HSI16 clock selected as USART1 clock 0x2 B_0x3 LSE clock selected as USART1 clock 0x3 USART2SEL USART2 clock source selection This bit is set and cleared by software to select the USART2 clock source. 2 2 read-write B_0x0 PCLK selected as USART2 clock 0x0 B_0x1 System clock (SYSCLK) selected as USART2 clock 0x1 B_0x2 HSI16 clock selected as USART2 clock 0x2 B_0x3 LSE clock selected as USART2 clock 0x3 USART3SEL USART3 clock source selection This bit is set and cleared by software to select the USART3 clock source. 4 2 read-write B_0x0 PCLK selected as USART3 clock 0x0 B_0x1 System clock (SYSCLK) selected as USART3 clock 0x1 B_0x2 HSI16 clock selected as USART3 clock 0x2 B_0x3 LSE clock selected as USART3 clock 0x3 UART4SEL UART4 clock source selection This bit is set and cleared by software to select the UART4 clock source. 6 2 read-write B_0x0 PCLK selected as UART4 clock 0x0 B_0x1 System clock (SYSCLK) selected as UART4 clock 0x1 B_0x2 HSI16 clock selected as UART4 clock 0x2 B_0x3 LSE clock selected as UART4 clock 0x3 UART5SEL UART5 clock source selection These bits are set and cleared by software to select the UART5 clock source. 8 2 read-write B_0x0 PCLK selected as UART5 clock 0x0 B_0x1 System clock (SYSCLK) selected as UART5 clock 0x1 B_0x2 HSI16 clock selected as UART5 clock 0x2 B_0x3 LSE clock selected as UART5 clock 0x3 LPUART1SEL LPUART1 clock source selection These bits are set and cleared by software to select the LPUART1 clock source. 10 2 read-write B_0x0 PCLK selected as LPUART1 clock 0x0 B_0x1 System clock (SYSCLK) selected as LPUART1 clock 0x1 B_0x2 HSI16 clock selected as LPUART1 clock 0x2 B_0x3 LSE clock selected as LPUART1 clock 0x3 I2C1SEL I2C1 clock source selection These bits are set and cleared by software to select the I2C1 clock source. 12 2 read-write B_0x0 PCLK selected as I2C1 clock 0x0 B_0x1 System clock (SYSCLK) selected as I2C1 clock 0x1 B_0x2 HSI16 clock selected as I2C1 clock 0x2 B_0x3 Reserved 0x3 I2C2SEL I2C2 clock source selection These bits are set and cleared by software to select the I2C2 clock source. 14 2 read-write B_0x0 PCLK selected as I2C2 clock 0x0 B_0x1 System clock (SYSCLK) selected as I2C2 clock 0x1 B_0x2 HSI16 clock selected as I2C2 clock 0x2 B_0x3 Reserved 0x3 I2C3SEL I2C3 clock source selection These bits are set and cleared by software to select the I2C3 clock source. 16 2 read-write B_0x0 PCLK selected as I2C3 clock 0x0 B_0x1 System clock (SYSCLK) selected as I2C3 clock 0x1 B_0x2 HSI16 clock selected as I2C3 clock 0x2 B_0x3 Reserved 0x3 LPTIM1SEL Low power timer 1 clock source selection These bits are set and cleared by software to select the LPTIM1 clock source. 18 2 read-write B_0x0 PCLK selected as LPTIM1 clock 0x0 B_0x1 LSI clock selected as LPTIM1 clock 0x1 B_0x2 HSI16 clock selected as LPTIM1 clock 0x2 B_0x3 LSE clock selected as LPTIM1 clock 0x3 SAI1SEL clock source selection These bits are set and cleared by software to select the SAI clock source. 20 2 read-write B_0x0 System clock selected as SAI clock 0x0 B_0x1 PLL “Q” clock selected as SAI clock 0x1 B_0x2 Clock provided on I2S_CKIN pin selected as SAI clock 0x2 B_0x3 HSI16 clock selected as SAI clock 0x3 I2S23SEL clock source selection These bits are set and cleared by software to select the I2S23 clock source. 22 2 read-write B_0x0 System clock selected as I2S23 clock 0x0 B_0x1 PLL “Q” clock selected as I2S23 clock 0x1 B_0x2 Clock provided on I2S_CKIN pin is selected as I2S23 clock 0x2 B_0x3 HSI16 clock selected as I2S23 clock. 0x3 FDCANSEL None 24 2 read-write CLK48SEL 48 MHz clock source selection These bits are set and cleared by software to select the 48 MHz clock source used by USB device FS and RNG. 26 2 read-write B_0x0 HSI48 clock selected as 48 MHz clock 0x0 B_0x1 Reserved 0x1 B_0x2 PLL “Q” clock (PLL48M1CLK) selected as 48 MHz clock 0x2 B_0x3 Reserved, must be kept at reset value 0x3 ADC12SEL ADC1/2 clock source selection These bits are set and cleared by software to select the clock source used by the ADC interface. 28 2 read-write B_0x0 No clock selected 0x0 B_0x1 PLL “P” clock selected as ADC1/2 clock 0x1 B_0x2 System clock selected as ADC1/2 clock 0x2 B_0x3 Reserved 0x3 ADC345SEL ADC3/4/5 clock source selection These bits are set and cleared by software to select the clock source used by the ADC345 interface. 30 2 read-write B_0x0 No clock selected 0x0 B_0x1 PLL “P” clock selected as ADC345 clock 0x1 B_0x2 System clock selected as ADC3/4/5 clock 0x2 B_0x3 Reserved. 0x3 RCC_BDCR RCC_BDCR RTC domain control register 0x90 0x20 0x00000000 0xFFFFFFFF LSEON LSE oscillator enable Set and cleared by software. 0 1 read-write B_0x0 LSE oscillator OFF 0x0 B_0x1 LSE oscillator ON 0x1 LSERDY LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. 1 1 read-only B_0x0 LSE oscillator not ready 0x0 B_0x1 LSE oscillator ready 0x1 LSEBYP LSE oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0). 2 1 read-write B_0x0 LSE oscillator not bypassed 0x0 B_0x1 LSE oscillator bypassed 0x1 LSEDRV LSE oscillator drive capability Set by software to modulate the LSE oscillator’s drive capability. The oscillator is in Xtal mode when it is not in bypass mode. 3 2 read-write B_0x0 ‘Xtal mode’ lower driving capability 0x0 B_0x1 ‘Xtal mode’ medium low driving capability 0x1 B_0x2 ‘Xtal mode’ medium high driving capability 0x2 B_0x3 ‘Xtal mode’ higher driving capability 0x3 LSECSSON CSS on LSE enable Set by software to enable the Clock Security System on LSE (32 kHz oscillator). LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled this bit cannot be disabled, except after a LSE failure detection (LSECSSD =1). In that case the software MUST disable the LSECSSON bit. 5 1 read-write B_0x0 CSS on LSE (32 kHz external oscillator) OFF 0x0 B_0x1 CSS on LSE (32 kHz external oscillator) ON 0x1 LSECSSD CSS on LSE failure Detection Set by hardware to indicate when a failure has been detected by the Clock Security System on the external 32 kHz oscillator (LSE). 6 1 read-only B_0x0 No failure detected on LSE (32 kHz oscillator) 0x0 B_0x1 Failure detected on LSE (32 kHz oscillator) 0x1 RTCSEL RTC clock source selection Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them. 8 2 read-write B_0x0 No clock 0x0 B_0x1 LSE oscillator clock used as RTC clock 0x1 B_0x2 LSI oscillator clock used as RTC clock 0x2 B_0x3 HSE oscillator clock divided by 32 used as RTC clock 0x3 RTCEN RTC clock enable Set and cleared by software. 15 1 read-write B_0x0 RTC clock disabled 0x0 B_0x1 RTC clock enabled 0x1 BDRST RTC domain software reset Set and cleared by software. 16 1 read-write B_0x0 Reset not activated 0x0 B_0x1 Reset the entire RTC domain 0x1 LSCOEN Low speed clock output enable Set and cleared by software. 24 1 read-write B_0x0 Low speed clock output (LSCO) disable 0x0 B_0x1 Low speed clock output (LSCO) enable 0x1 LSCOSEL Low speed clock output selection Set and cleared by software. 25 1 read-write B_0x0 LSI clock selected 0x0 B_0x1 LSE clock selected 0x1 RCC_CSR RCC_CSR Control/status register 0x94 0x20 0x0C000000 0xFFFFFFFF LSION LSI oscillator enable Set and cleared by software. 0 1 read-write B_0x0 LSI oscillator OFF 0x0 B_0x1 LSI oscillator ON 0x1 LSIRDY LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC. 1 1 read-only B_0x0 LSI oscillator not ready 0x0 B_0x1 LSI oscillator ready 0x1 RMVF Remove reset flag Set by software to clear the reset flags. 23 1 read-write B_0x0 No effect 0x0 B_0x1 Clear the reset flags 0x1 OBLRSTF Option byte loader reset flag Set by hardware when a reset from the Option Byte loading occurs. Cleared by writing to the RMVF bit. 25 1 read-only B_0x0 No reset from Option Byte loading occurred 0x0 B_0x1 Reset from Option Byte loading occurred 0x1 PINRSTF Pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit. 26 1 read-only B_0x0 No reset from NRST pin occurred 0x0 B_0x1 Reset from NRST pin occurred 0x1 BORRSTF BOR flag Set by hardware when a BOR occurs. Cleared by writing to the RMVF bit. 27 1 read-only B_0x0 No BOR occurred 0x0 B_0x1 BOR occurred 0x1 SFTRSTF Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. 28 1 read-only B_0x0 No software reset occurred 0x0 B_0x1 Software reset occurred 0x1 IWDGRSTF Independent window watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by writing to the RMVF bit. 29 1 read-only B_0x0 No independent watchdog reset occurred 0x0 B_0x1 Independent watchdog reset occurred 0x1 WWDGRSTF Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by writing to the RMVF bit. 30 1 read-only B_0x0 No window watchdog reset occurred 0x0 B_0x1 Window watchdog reset occurred 0x1 LPWRRSTF Low-power reset flag Set by hardware when a reset occurs due to illegal Stop, Standby or Shutdown mode entry. Cleared by writing to the RMVF bit. 31 1 read-only B_0x0 No illegal mode reset occurred 0x0 B_0x1 Illegal mode reset occurred 0x1 RCC_CRRCR RCC_CRRCR Clock recovery RC register 0x98 0x20 0x00000000 0xFFFFFFFF HSI48ON HSI48 clock enable Set and cleared by software. Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes. 0 1 read-write B_0x0 HSI48 oscillator OFF 0x0 B_0x1 HSI48 oscillator ON 0x1 HSI48RDY HSI48 clock ready flag Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON. 1 1 read-only B_0x0 HSI48 oscillator not ready 0x0 B_0x1 HSI48 oscillator ready 0x1 HSI48CAL HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value. They are ready only. 7 9 read-only RCC_CCIPR2 RCC_CCIPR2 Peripherals independent clock configuration register 0x9C 0x20 0x00000000 0xFFFFFFFF I2C4SEL I2C4 clock source selection These bits are set and cleared by software to select the I2C4 clock source. 0 2 read-write B_0x0 PCLK selected as I2C4 clock 0x0 B_0x1 System clock (SYSCLK) selected as I2C4 clock 0x1 B_0x2 HSI16 clock selected as I2C4 clock 0x2 B_0x3 reserved 0x3 QSPISEL QUADSPI clock source selection Set and reset by software. 20 2 read-write B_0x0 system clock selected as QUADSPI kernel clock 0x0 B_0x1 HSI16 clock selected as QUADSPI kernel clock 0x1 B_0x2 PLL “Q” clock selected as QUADSPI kernel clock 0x2 B_0x3 reserved 0x3 PWR Power control PWR 0x40007000 0x0 0x400 registers PWR_CR1 PWR_CR1 Power control register 1 0x00 0x20 0x00000200 0xFFFFFFFF LPMS Low-power mode selection These bits select the low-power mode entered when CPU enters the deepsleep mode. 1xx: Shutdown mode Note: In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3. 0 3 read-write B_0x0 Stop 0 mode 0x0 B_0x1 Stop 1 mode 0x1 B_0x2 Reserved 0x2 B_0x3 Standby mode 0x3 FPD_STOP FPD_STOP 3 1 read-write DBP Disable backup domain write protection In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. 8 1 read-write B_0x0 Access to RTC and Backup registers disabled 0x0 B_0x1 Access to RTC and Backup registers enabled 0x1 VOS Voltage scaling range selection 9 2 read-write B_0x0 Cannot be written (forbidden by hardware) 0x0 B_0x1 Range 1 0x1 B_0x2 Range 2 0x2 B_0x3 Cannot be written (forbidden by hardware) 0x3 LPR Low-power run When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR). 14 1 read-write PWR_CR2 PWR_CR2 Power control register 2 0x04 0x20 0x00000000 0xFFFFFFFF PVDE Programmable voltage detector enable Note: This bit is write-protected when the PVDL bit is set in the SYSCFG_CFGR2 register. The protection can be reset only by a system reset. 0 1 read-write B_0x0 Programmable voltage detector disable. 0x0 B_0x1 Programmable voltage detector enable. 0x1 PVDLS Programmable voltage detector level selection. These bits select the PVD falling threshold: Note: These bits are write-protected when the PVDL bit is set in the SYSCFG_CFGR2 register. The protection can be reset only by a system reset. 1 3 read-write B_0x0 V_PVD0 PVD threshold 0 0x0 B_0x1 V_PVD1 PVD threshold 1 0x1 B_0x2 V_PVD2 PVD threshold 2 0x2 B_0x3 V_PVD3 PVD threshold 3 0x3 B_0x4 V_PVD4 PVD threshold 4 0x4 B_0x5 V_PVD5 PVD threshold 5 0x5 B_0x6 V_PVD6 PVD threshold 6 0x6 B_0x7 External input analog voltage PVD_IN (compared internally to V_REFINT) 0x7 PVMEN1 Peripheral voltage monitoring 3 enable: V_DDA vs. ADC/COMP min voltage 1.62V 6 1 read-write B_0x0 PVM1 (V_DDA monitoring vs. 1.62V threshold) disable. 0x0 B_0x1 PVM1 (V_DDA monitoring vs. 1.62V threshold) enable. 0x1 PVMEN2 Peripheral voltage monitoring 4 enable: V_DDA vs. DAC 1MSPS /DAC 15MSPS min voltage. 7 1 read-write B_0x0 PVM2 (V_DDA monitoring vs. 1.8 V threshold) disable. 0x0 B_0x1 PVM2 (V_DDA monitoring vs. 1.8 V threshold) enable. 0x1 PWR_CR3 PWR_CR3 Power control register 3 0x08 0x20 0x00008000 0xFFFFFFFF EWUP1 Enable Wakeup pin WKUP1 When this bit is set, the external wakeup pin WKUP1 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit in the PWR_CR4 register. 0 1 read-write EWUP2 Enable Wakeup pin WKUP2 When this bit is set, the external wakeup pin WKUP2 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit in the PWR_CR4 register. 1 1 read-write EWUP3 Enable Wakeup pin WKUP3 When this bit is set, the external wakeup pin WKUP3 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit in the PWR_CR4 register. 2 1 read-write EWUP4 Enable Wakeup pin WKUP4 When this bit is set, the external wakeup pin WKUP4 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register. 3 1 read-write EWUP5 Enable Wakeup pin WKUP5 When this bit is set, the external wakeup pin WKUP5 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP5 bit in the PWR_CR4 register. 4 1 read-write RRS SRAM2 retention in Standby mode 8 1 read-write B_0x0 SRAM2 is powered off in Standby mode (SRAM2 content is lost). 0x0 B_0x1 SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 content is kept). 0x1 APC Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os. 10 1 read-write UCPD1_STDBY UCPD1_STDBY USB Type-C and Power Delivery standby mode. 13 1 read-write B_0x0 Write ‘0’ immediately after standby exit when using UCPD1, (and before writing any UCPD1 registers). 0x0 B_0x1 Write ‘1’ just before entering standby when using UCPD1. 0x1 UCPD1_DBDIS USB Type-C and Power Delivery Dead Battery disable. After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to hand over control to the UCPD1 (which should therefore be initialized before doing the disable). 14 1 read-write B_0x0 Enable USB Type-C dead battery pull-down behavior on UCPD1_CC1 and UCPD1_CC2 pins. 0x0 B_0x1 Disable USB Type-C dead battery pull-down behavior on UCPD1_CC1 and UCPD1_CC2 pins. 0x1 EIWUL Enable internal wakeup line 15 1 read-write B_0x0 Internal wakeup line disable. 0x0 B_0x1 Internal wakeup line enable. 0x1 PWR_CR4 PWR_CR4 Power control register 4 0x0C 0x20 0x00000000 0xFFFFFFFF WP1 Wakeup pin WKUP1 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP1 0 1 read-write B_0x0 Detection on high level (rising edge) 0x0 B_0x1 Detection on low level (falling edge) 0x1 WP2 Wakeup pin WKUP2 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP2 1 1 read-write B_0x0 Detection on high level (rising edge) 0x0 B_0x1 Detection on low level (falling edge) 0x1 WP3 Wakeup pin WKUP3 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP3 2 1 read-write B_0x0 Detection on high level (rising edge) 0x0 B_0x1 Detection on low level (falling edge) 0x1 WP4 Wakeup pin WKUP4 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP4 3 1 read-write B_0x0 Detection on high level (rising edge) 0x0 B_0x1 Detection on low level (falling edge) 0x1 WP5 Wakeup pin WKUP5 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP5 4 1 read-write B_0x0 Detection on high level (rising edge) 0x0 B_0x1 Detection on low level (falling edge) 0x1 VBE V_BAT battery charging enable 8 1 read-write B_0x0 V_BAT battery charging disable 0x0 B_0x1 V_BAT battery charging enable 0x1 VBRS V_BAT battery charging resistor selection 9 1 read-write B_0x0 Charge V_BAT through a 5 kOhms resistor 0x0 B_0x1 Charge V_BAT through a 1.5 kOhms resistor 0x1 PWR_SR1 PWR_SR1 Power status register 1 0x10 0x20 0x00000000 0xFFFFFFFF WUF1 Wakeup flag 1 This bit is set when a wakeup event is detected on wakeup pin, WKUP1. It is cleared by writing ‘1’ in the CWUF1 bit of the PWR_SCR register. 0 1 read-only WUF2 Wakeup flag 2 This bit is set when a wakeup event is detected on wakeup pin, WKUP2. It is cleared by writing ‘1’ in the CWUF2 bit of the PWR_SCR register. 1 1 read-only WUF3 Wakeup flag 3 This bit is set when a wakeup event is detected on wakeup pin, WKUP3. It is cleared by writing ‘1’ in the CWUF3 bit of the PWR_SCR register. 2 1 read-only WUF4 Wakeup flag 4 This bit is set when a wakeup event is detected on wakeup pin,WKUP4. It is cleared by writing ‘1’ in the CWUF4 bit of the PWR_SCR register. 3 1 read-only WUF5 Wakeup flag 5 This bit is set when a wakeup event is detected on wakeup pin, WKUP5. It is cleared by writing ‘1’ in the CWUF5 bit of the PWR_SCR register. 4 1 read-only SBF Standby flag This bit is set by hardware when the device enters the Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. 8 1 read-only B_0x0 The device did not enter the Standby mode 0x0 B_0x1 The device entered the Standby mode 0x1 WUFI Wakeup flag internal This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared. 15 1 read-only PWR_SR2 PWR_SR2 Power status register 2 0x14 0x20 0x00000000 0xFFFFFFFF REGLPS Low-power regulator started This bit provides the information whether the low-power regulator is ready after a power-on reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wakeup from Standby mode time may be increased. 8 1 read-only B_0x0 The low-power regulator is not ready 0x0 B_0x1 The low-power regulator is ready 0x1 REGLPF Low-power regulator flag This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency. This bit is cleared by hardware when the regulator is ready. 9 1 read-only B_0x0 The regulator is ready in main mode (MR) 0x0 B_0x1 The regulator is in low-power mode (LPR) 0x1 VOSF Voltage scaling flag A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register. 10 1 read-only B_0x0 The regulator is ready in the selected voltage range 0x0 B_0x1 The regulator output voltage is changing to the required voltage level 0x1 PVDO Programmable voltage detector output 11 1 read-only B_0x0 V_DD is above the selected PVD threshold 0x0 B_0x1 V_DD is below the selected PVD threshold 0x1 PVMO1 Peripheral voltage monitoring output: V_DDA vs. 1.62 V Note: PVMO1 is cleared when PVM1 is disabled (PVME = 0). After enabling PVM1, the PVM1 output is valid after the PVM1 wakeup time. 14 1 read-only B_0x0 V_DDA voltage is above PVM1 threshold (around 1.62 V). 0x0 B_0x1 V_DDA voltage is below PVM1 threshold (around 1.62 V). 0x1 PVMO2 Peripheral voltage monitoring output: V_DDA vs. 1.8 V Note: PVMO2 is cleared when PVM2 is disabled (PVME = 0). After enabling PVM2, the PVM2 output is valid after the PVM2 wakeup time. 15 1 read-only B_0x0 V_DDA voltage is above PVM2 threshold (around 1.8 V). 0x0 B_0x1 V_DDA voltage is below PVM2 threshold (around 1.8 V). 0x1 PWR_SCR PWR_SCR Power status clear register 0x18 0x20 0x00000000 0xFFFFFFFF CWUF1 Clear wakeup flag 1 Setting this bit clears the WUF1 flag in the PWR_SR1 register. 0 1 write-only CWUF2 Clear wakeup flag 2 Setting this bit clears the WUF2 flag in the PWR_SR1 register. 1 1 write-only CWUF3 Clear wakeup flag 3 Setting this bit clears the WUF3 flag in the PWR_SR1 register. 2 1 write-only CWUF4 Clear wakeup flag 4 Setting this bit clears the WUF4 flag in the PWR_SR1 register. 3 1 write-only CWUF5 Clear wakeup flag 5 Setting this bit clears the WUF5 flag in the PWR_SR1 register. 4 1 write-only CSBF Clear standby flag Setting this bit clears the SBF flag in the PWR_SR1 register. 8 1 write-only PWR_PUCRA PWR_PUCRA Power Port A pull-up control register 0x20 0x20 0x00000000 0xFFFFFFFF PU0 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU1 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PU11 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 11 1 read-write PU12 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 12 1 read-write PU13 Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 13 1 read-write PU15 Port A pull-up bit 15 When set, this bit activates the pull-up on PA[15] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PD15 bit is also set. 15 1 read-write PWR_PDCRA PWR_PDCRA Power Port A pull-down control register 0x24 0x20 0x00000000 0xFFFFFFFF PD0 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD1 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD4 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 4 1 read-write PD5 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 11 1 read-write PD12 Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 12 1 read-write PD14 Port A pull-down bit 14 When set, this bit activates the pull-down on PA[14] when APC bit is set in PWR_CR3 register. 14 1 read-write PWR_PUCRB PWR_PUCRB Power Port B pull-up control register 0x28 0x20 0x00000000 0xFFFFFFFF PU0 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU1 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PU11 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 11 1 read-write PU12 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 12 1 read-write PU13 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 13 1 read-write PU14 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 14 1 read-write PU15 Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 15 1 read-write PWR_PDCRB PWR_PDCRB Power Port B pull-down control register 0x2C 0x20 0x00000000 0xFFFFFFFF PD0 Port B pull-down bit y (y=0..3) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD1 Port B pull-down bit y (y=0..3) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port B pull-down bit y (y=0..3) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port B pull-down bit y (y=0..3) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD5 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 11 1 read-write PD12 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 12 1 read-write PD13 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 13 1 read-write PD14 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 14 1 read-write PD15 Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 15 1 read-write PWR_PUCRC PWR_PUCRC Power Port C pull-up control register 0x30 0x20 0x00000000 0xFFFFFFFF PU0 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU1 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PU11 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 11 1 read-write PU12 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 12 1 read-write PU13 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 13 1 read-write PU14 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 14 1 read-write PU15 Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 15 1 read-write PWR_PDCRC PWR_PDCRC Power Port C pull-down control register 0x34 0x20 0x00000000 0xFFFFFFFF PD0 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD1 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD4 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 4 1 read-write PD5 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 11 1 read-write PD12 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 12 1 read-write PD13 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 13 1 read-write PD14 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 14 1 read-write PD15 Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 15 1 read-write PWR_PUCRD PWR_PUCRD Power Port D pull-up control register 0x38 0x20 0x00000000 0xFFFFFFFF PU0 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU1 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PU11 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 11 1 read-write PU12 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 12 1 read-write PU13 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 13 1 read-write PU14 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 14 1 read-write PU15 Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 15 1 read-write PWR_PDCRD PWR_PDCRD Power Port D pull-down control register 0x3C 0x20 0x00000000 0xFFFFFFFF PD0 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD1 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD4 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 4 1 read-write PD5 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 11 1 read-write PD12 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 12 1 read-write PD13 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 13 1 read-write PD14 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 14 1 read-write PD15 Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 15 1 read-write PWR_PUCRE PWR_PUCRE Power Port E pull-up control register 0x40 0x20 0x00000000 0xFFFFFFFF PU0 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU1 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PU11 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 11 1 read-write PU12 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 12 1 read-write PU13 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 13 1 read-write PU14 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 14 1 read-write PU15 Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 15 1 read-write PWR_PDCRE PWR_PDCRE Power Port E pull-down control register 0x44 0x20 0x00000000 0xFFFFFFFF PD0 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD1 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD4 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 4 1 read-write PD5 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 11 1 read-write PD12 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 12 1 read-write PD13 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 13 1 read-write PD14 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 14 1 read-write PD15 Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 15 1 read-write PWR_PUCRF PWR_PUCRF Power Port F pull-up control register 0x48 0x20 0x00000000 0xFFFFFFFF PU0 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU1 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PU11 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 11 1 read-write PU12 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 12 1 read-write PU13 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 13 1 read-write PU14 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 14 1 read-write PU15 Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 15 1 read-write PWR_PDCRF PWR_PDCRF Power Port F pull-down control register 0x4C 0x20 0x00000000 0xFFFFFFFF PD0 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD1 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD4 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 4 1 read-write PD5 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PD11 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 11 1 read-write PD12 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 12 1 read-write PD13 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 13 1 read-write PD14 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 14 1 read-write PD15 Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 15 1 read-write PWR_PUCRG PWR_PUCRG Power Port G pull-up control register 0x50 0x20 0x00000000 0xFFFFFFFF PU0 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 0 1 read-write PU1 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 1 1 read-write PU2 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 2 1 read-write PU3 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 3 1 read-write PU4 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 4 1 read-write PU5 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5 1 read-write PU6 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6 1 read-write PU7 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 7 1 read-write PU8 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 8 1 read-write PU9 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 9 1 read-write PU10 Port G pull-up bit y (y=0..10) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 10 1 read-write PWR_PDCRG PWR_PDCRG Power Port G pull-down control register 0x54 0x20 0x00000000 0xFFFFFFFF PD0 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 0 1 read-write PD1 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 1 1 read-write PD2 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 2 1 read-write PD3 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 3 1 read-write PD4 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 4 1 read-write PD5 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 5 1 read-write PD6 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 6 1 read-write PD7 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 7 1 read-write PD8 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 8 1 read-write PD9 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 9 1 read-write PD10 Port G pull-down bit y (y=0..10) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 10 1 read-write PWR_CR5 PWR_CR5 Power control register 0x80 0x20 0x00000100 0xFFFFFFFF R1MODE Main regular range 1 mode This bit is only valid for the main regulator in range 1 and has no effect on range 2. It is recommended to reset this bit when the system frequency is greater than 150 MHz. Refer to 8 1 read-write B_0x0 Main regulator in range 1 boost mode. 0x0 B_0x1 Main regulator in range 1 normal mode. 0x1 RNG Random number generator RNG 0x50060800 0x0 0x400 registers RNG RNG 90 CR CR control register 0x0 0x20 read-write 0x00000000 CED Clock error detection 5 1 IE Interrupt enable 3 1 RNGEN Random number generator enable 2 1 SR SR status register 0x4 0x20 0x00000000 SEIS Seed error interrupt status 6 1 read-write CEIS Clock error interrupt status 5 1 read-write SECS Seed error current status 2 1 read-only CECS Clock error current status 1 1 read-only DRDY Data ready 0 1 read-only DR DR data register 0x8 0x20 read-only 0x00000000 RNDATA Random data 0 32 AES Advanced encryption standard hardware accelerator AES 0x50060000 0x0 0x400 registers AES AES 85 CR CR control register 0x0 0x20 read-write 0x00000000 NPBLB NPBLB 20 4 KEYSIZE KEYSIZE 18 1 CHMOD_2 CHMOD_2 16 1 GCMPH GCMPH 13 2 DMAOUTEN Enable DMA management of data output phase 12 1 DMAINEN Enable DMA management of data input phase 11 1 ERRIE Error interrupt enable 10 1 CCFIE CCF flag interrupt enable 9 1 ERRC Error clear 8 1 CCFC Computation Complete Flag Clear 7 1 CHMOD AES chaining mode 5 2 MODE AES operating mode 3 2 DATATYPE Data type selection (for data in and data out to/from the cryptographic block) 1 2 EN AES enable 0 1 SR SR status register 0x4 0x20 read-only 0x00000000 BUSY BUSY 3 1 WRERR Write error flag 2 1 RDERR Read error flag 1 1 CCF Computation complete flag 0 1 DINR DINR data input register 0x8 0x20 read-write 0x00000000 AES_DINR Data Input Register 0 32 DOUTR DOUTR data output register 0xC 0x20 read-only 0x00000000 AES_DOUTR Data output register 0 32 KEYR0 KEYR0 key register 0 0x10 0x20 read-write 0x00000000 AES_KEYR0 Data Output Register (LSB key [31:0]) 0 32 KEYR1 KEYR1 key register 1 0x14 0x20 read-write 0x00000000 AES_KEYR1 AES key register (key [63:32]) 0 32 KEYR2 KEYR2 key register 2 0x18 0x20 read-write 0x00000000 AES_KEYR2 AES key register (key [95:64]) 0 32 KEYR3 KEYR3 key register 3 0x1C 0x20 read-write 0x00000000 AES_KEYR3 AES key register (MSB key [127:96]) 0 32 IVR0 IVR0 initialization vector register 0 0x20 0x20 read-write 0x00000000 AES_IVR0 initialization vector register (LSB IVR [31:0]) 0 32 IVR1 IVR1 initialization vector register 1 0x24 0x20 read-write 0x00000000 AES_IVR1 Initialization Vector Register (IVR [63:32]) 0 32 IVR2 IVR2 initialization vector register 2 0x28 0x20 read-write 0x00000000 AES_IVR2 Initialization Vector Register (IVR [95:64]) 0 32 IVR3 IVR3 initialization vector register 3 0x2C 0x20 read-write 0x00000000 AES_IVR3 Initialization Vector Register (MSB IVR [127:96]) 0 32 KEYR4 KEYR4 key register 4 0x30 0x20 read-write 0x00000000 KEY AES key 0 32 KEYR5 KEYR5 key register 5 0x34 0x20 read-write 0x00000000 KEY AES key 0 32 KEYR6 KEYR6 key register 6 0x38 0x20 read-write 0x00000000 KEY AES key 0 32 KEYR7 KEYR7 key register 7 0x3C 0x20 read-write 0x00000000 KEY AES key 0 32 SUSP0R SUSP0R suspend registers 0x40 0x20 read-write 0x00000000 SUSP AES suspend 0 32 SUSP1R SUSP1R suspend registers 0x44 0x20 read-write 0x00000000 SUSP AES suspend 0 32 SUSP2R SUSP2R suspend registers 0x48 0x20 read-write 0x00000000 SUSP AES suspend 0 32 SUSP3R SUSP3R suspend registers 0x4C 0x20 read-write 0x00000000 SUSP AES suspend 0 32 SUSP4R SUSP4R suspend registers 0x50 0x20 read-write 0x00000000 SUSP AES suspend 0 32 SUSP5R SUSP5R suspend registers 0x54 0x20 read-write 0x00000000 SUSP AES suspend 0 32 SUSP6R SUSP6R suspend registers 0x58 0x20 read-write 0x00000000 SUSP AES suspend 0 32 SUSP7R SUSP7R suspend registers 0x5C 0x20 read-write 0x00000000 SUSP AES suspend 0 32 GPIOA General-purpose I/Os GPIO 0x48000000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xABFFFFFF MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x0C000000 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x64000000 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR GPIO port bit reset register 0x28 0x20 write-only 0x00000000 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 GPIOB General-purpose I/Os GPIO 0x48000400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFEBF MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x000000C0 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000100 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR GPIO port bit reset register 0x28 0x20 write-only 0x00000000 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 GPIOC General-purpose I/Os GPIO 0x48000800 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR GPIO port bit reset register 0x28 0x20 write-only 0x00000000 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 GPIOD 0x48000C00 GPIOE 0x48001000 GPIOF 0x48001400 GPIOG 0x48001800 TIM15 General purpose timers TIM 0x40014000 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 CEN Counter enable 0 1 UDIS Update disable 1 1 URS Update request source 2 1 OPM One-pulse mode 3 1 ARPE Auto-reload preload enable 7 1 CKD Clock division 8 2 UIFREMAP UIF status bit remapping 11 1 DITHEN Dithering Enable 12 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 OIS2 Output idle state 2 (OC2 output) 10 1 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 TS_4_3 Trigger selection - bit 4:3 20 2 SMS_3 Slave mode selection - bit 3 16 1 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 TDE Trigger DMA request enable 14 1 COMDE COM DMA request enable 13 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 BIE Break interrupt enable 7 1 TIE Trigger interrupt enable 6 1 COMIE COM interrupt enable 5 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x00000000 CC2OF Capture/Compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 BIF Break interrupt flag 7 1 TIF Trigger interrupt flag 6 1 COMIF COM interrupt flag 5 1 CC2IF Capture/compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 BG Break generation 7 1 TG Trigger generation 6 1 COMG Capture/Compare control update generation 5 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC1M_3 Output Compare 1 mode 16 1 OC2M OC2M 12 3 OC2PE OC2PE 11 1 OC2FE OC2FE 10 1 CC2S CC2S 8 2 OC1CE OC1CE 7 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F IC2F 12 4 IC2PSC IC2PSC 10 2 CC2S CC2S 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 CC2NP Capture/Compare 2 complementary output polarity 7 1 CC2P Capture/Compare 2 output polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x0000FFFF ARR Auto-reload value 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x00000000 REP Repetition counter value 0 8 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2 Capture/Compare 1 value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 BKE Break enable 12 1 BKP Break polarity 13 1 AOE Automatic output enable 14 1 MOE Main output enable 15 1 BKF Break filter 16 4 BKDSRM BKDSRM 26 1 BKBID BKBID 28 1 DTR2 DTR2 timer Deadtime Register 2 0x54 0x20 read-write 0x00000000 DTGF Dead-time generator setup 0 8 DTAE Deadtime Asymmetric Enable 16 1 DTPE Deadtime Preload Enable 17 1 TISEL TISEL TIM timer input selection register 0x5C 0x20 read-write 0x00000000 TI1SEL TI1[0] to TI1[15] input selection 0 4 TI2SEL TI2[0] to TI2[15] input selection 8 4 AF1 AF1 TIM alternate function option register 1 0x60 0x20 read-write 0x00000000 BKCMP4P BRK COMP4 input polarity 13 1 BKCMP3P BRK COMP3 input polarity 12 1 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP1P BRK COMP1 input polarity 10 1 BKINP BRK BKIN input polarity 9 1 BKCMP7E BRK COMP7 enable 7 1 BKCMP6E BRK COMP6 enable 6 1 BKCMP5E BRK COMP5 enable 5 1 BKCMP4E BRK COMP4 enable 4 1 BKCMP3E BRK COMP3 enable 3 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP1E BRK COMP1 enable 1 1 BKINE BRK BKIN input enable 0 1 AF2 AF2 TIM alternate function option register 2 0x64 0x20 read-write 0x00000000 OCRSEL OCREF_CLR source selection 16 3 DCR DCR DMA control register 0x3DC 0x20 read-write 0x00000000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x3E0 0x20 read-write 0x00000000 DMAB DMA register for burst accesses 0 32 TIM16 General purpose timers TIM 0x40014400 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 CEN Counter enable 0 1 UDIS Update disable 1 1 URS Update request source 2 1 OPM One-pulse mode 3 1 ARPE Auto-reload preload enable 7 1 CKD Clock division 8 2 UIFREMAP UIF status bit remapping 11 1 DITHEN Dithering Enable 12 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 COMDE COM DMA request enable 13 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 BIE Break interrupt enable 7 1 COMIE COM interrupt enable 5 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x00000000 CC1OF Capture/Compare 1 overcapture flag 9 1 BIF Break interrupt flag 7 1 COMIF COM interrupt flag 5 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 BG Break generation 7 1 COMG Capture/Compare control update generation 5 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 OC1M_3 Output Compare 1 mode 16 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x0000FFFF ARR Auto-reload value 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x00000000 REP Repetition counter value 0 8 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 BKE Break enable 12 1 BKP Break polarity 13 1 AOE Automatic output enable 14 1 MOE Main output enable 15 1 BKF Break filter 16 4 BKDSRM BKDSRM 26 1 BKBID BKBID 28 1 DTR2 DTR2 timer Deadtime Register 2 0x54 0x20 read-write 0x00000000 DTGF Dead-time generator setup 0 8 DTAE Deadtime Asymmetric Enable 16 1 DTPE Deadtime Preload Enable 17 1 TISEL TISEL TIM timer input selection register 0x5C 0x20 read-write 0x00000000 TI1SEL TI1[0] to TI1[15] input selection 0 4 AF1 AF1 TIM alternate function option register 1 0x60 0x20 read-write 0x00000000 BKCMP4P BRK COMP4 input polarity 13 1 BKCMP3P BRK COMP3 input polarity 12 1 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP1P BRK COMP1 input polarity 10 1 BKINP BRK BKIN input polarity 9 1 BKCMP7E BRK COMP7 enable 7 1 BKCMP6E BRK COMP6 enable 6 1 BKCMP5E BRK COMP5 enable 5 1 BKCMP4E BRK COMP4 enable 4 1 BKCMP3E BRK COMP3 enable 3 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP1E BRK COMP1 enable 1 1 BKINE BRK BKIN input enable 0 1 AF2 AF2 TIM alternate function option register 2 0x64 0x20 read-write 0x00000000 OCRSEL OCREF_CLR source selection 16 3 OR1 OR1 TIM option register 1 0x68 0x20 read-write 0x00000000 HSE32EN HSE Divided by 32 enable 0 1 DCR DCR DMA control register 0x3DC 0x20 read-write 0x00000000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x3E0 0x20 read-write 0x00000000 DMAB DMA register for burst accesses 0 32 TIM17 0x40014800 TIM1 Advanced-timers TIM 0x40012C00 0x0 0x400 registers TIM1_BRK_TIM15 TIM1_BRK_TIM15 24 TIM1_UP_TIM16 TIM1_UP_TIM16 25 TIM1_TRG_COM TIM1_TRG_COM/ 26 TIM1_CC TIM1 capture compare interrupt 27 TIM8_CC TIM8_CC 46 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 DITHEN Dithering Enable 12 1 UIFREMAP UIF status bit remapping 11 1 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 MMS_3 Master mode selection - bit 3 25 1 MMS2 Master mode selection 2 20 4 OIS6 Output Idle state 6 (OC6 output) 18 1 OIS5 Output Idle state 5 (OC5 output) 16 1 OIS4N Output Idle state 4 (OC4N output) 15 1 OIS4 Output Idle state 4 14 1 OIS3N Output Idle state 3 13 1 OIS3 Output Idle state 3 12 1 OIS2N Output Idle state 2 11 1 OIS2 Output Idle state 2 10 1 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 SMSPS SMS Preload Source 25 1 SMSPE SMS Preload Enable 24 1 TS_4_3 Trigger selection - bit 4:3 20 2 SMS_3 Slave mode selection - bit 3 16 1 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 TERRIE Transition Error interrupt enable 23 1 IERRIE Index Error interrupt enable 22 1 DIRIE Direction Change interrupt enable 21 1 IDXIE Index interrupt enable 20 1 TDE Trigger DMA request enable 14 1 COMDE COM DMA request enable 13 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 TIE Trigger interrupt enable 6 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 BIE Break interrupt enable 7 1 COMIE COM interrupt enable 5 1 SR SR status register 0x10 0x20 read-write 0x00000000 TERRF Transition Error interrupt flag 23 1 IERRF Index Error interrupt flag 22 1 DIRF Direction Change interrupt flag 21 1 IDXF Index interrupt flag 20 1 CC6IF Compare 6 interrupt flag 17 1 CC5IF Compare 5 interrupt flag 16 1 SBIF System Break interrupt flag 13 1 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 B2IF Break 2 interrupt flag 8 1 BIF Break interrupt flag 7 1 TIF Trigger interrupt flag 6 1 COMIF COM interrupt flag 5 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 B2G Break 2 generation 8 1 BG Break generation 7 1 TG Trigger generation 6 1 COMG Capture/Compare control update generation 5 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC2CE Output Compare 2 clear enable 15 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 OC2FE Output Compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 ICPCS Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 OC4M_3 Output Compare 4 mode - bit 3 24 1 OC3M_3 Output Compare 3 mode - bit 3 16 1 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 CC6P Capture/Compare 6 output polarity 21 1 CC6E Capture/Compare 6 output enable 20 1 CC5P Capture/Compare 5 output polarity 17 1 CC5E Capture/Compare 5 output enable 16 1 CC4NP Capture/Compare 4 complementary output polarity 15 1 CC4NE Capture/Compare 4 complementary output enable 14 1 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 0x00000000 UIFCPY UIFCPY 31 1 read-only CNT counter value 0 16 read-write PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x0000FFFF ARR Auto-reload value 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x00000000 REP Repetition counter value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2 Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3 Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4 Capture/Compare value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 BK2ID BK2ID 29 1 BKBID BKBID 28 1 BK2DSRM BK2DSRM 27 1 BKDSRM BKDSRM 26 1 BK2P Break 2 polarity 25 1 BK2E Break 2 Enable 24 1 BK2F Break 2 filter 20 4 BKF Break filter 16 4 MOE Main output enable 15 1 AOE Automatic output enable 14 1 BKP Break polarity 13 1 BKE Break enable 12 1 OSSR Off-state selection for Run mode 11 1 OSSI Off-state selection for Idle mode 10 1 LOCK Lock configuration 8 2 DTG Dead-time generator setup 0 8 CCR5 CCR5 capture/compare register 4 0x48 0x20 read-write 0x00000000 CCR5 Capture/Compare value 0 16 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 4 0x4C 0x20 read-write 0x00000000 CCR6 Capture/Compare value 0 16 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x50 0x20 read-write 0x00000000 OC6M_bit3 Output Compare 6 mode bit 3 24 1 OC5M_bit3 Output Compare 5 mode bit 3 16 3 OC6CE Output compare 6 clear enable 15 1 OC6M Output compare 6 mode 12 3 OC6PE Output compare 6 preload enable 11 1 OC6FE Output compare 6 fast enable 10 1 OC5CE Output compare 5 clear enable 7 1 OC5M Output compare 5 mode 4 3 OC5PE Output compare 5 preload enable 3 1 OC5FE Output compare 5 fast enable 2 1 DTR2 DTR2 timer Deadtime Register 2 0x54 0x20 read-write 0x00000000 DTPE Deadtime Preload Enable 17 1 DTAE Deadtime Asymmetric Enable 16 1 DTGF Dead-time falling edge generator setup 0 8 ECR ECR DMA control register 0x58 0x20 read-write 0x00000000 IE Index Enable 0 1 IDIR Index Direction 1 2 IBLK Index Blanking 3 2 FIDX First Index 5 1 IPOS Index Positioning 6 2 PW Pulse width 16 8 PWPRSC Pulse Width prescaler 24 3 TISEL TISEL TIM timer input selection register 0x5C 0x20 read-write 0x00000000 TI1SEL TI1[0] to TI1[15] input selection 0 4 TI2SEL TI2[0] to TI2[15] input selection 8 4 TI3SEL TI3[0] to TI3[15] input selection 16 4 TI4SEL TI4[0] to TI4[15] input selection 24 4 AF1 AF1 TIM alternate function option register 1 0x60 0x20 read-write 0x00000000 ETRSEL ETR source selection 14 4 BKCMP4P BRK COMP4 input polarity 13 1 BKCMP3P BRK COMP3 input polarity 12 1 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP1P BRK COMP1 input polarity 10 1 BKINP BRK BKIN input polarity 9 1 BKCMP7E BRK COMP7 enable 7 1 BKCMP6E BRK COMP6 enable 6 1 BKCMP5E BRK COMP5 enable 5 1 BKCMP4E BRK COMP4 enable 4 1 BKCMP3E BRK COMP3 enable 3 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP1E BRK COMP1 enable 1 1 BKINE BRK BKIN input enable 0 1 AF2 AF2 TIM alternate function option register 2 0x64 0x20 read-write 0x00000000 OCRSEL OCREF_CLR source selection 16 3 BK2CMP4P BRK2 COMP4 input polarity 13 1 BK2CMP3P BRK2 COMP3 input polarity 12 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2INP BRK2 BKIN input polarity 9 1 BK2CMP7E BRK2 COMP7 enable 7 1 BK2CMP6E BRK2 COMP6 enable 6 1 BK2CMP5E BRK2 COMP5 enable 5 1 BK2CMP4E BRK2 COMP4 enable 4 1 BK2CMP3E BRK2 COMP3 enable 3 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2CMP1E BRK2 COMP1 enable 1 1 BKINE BRK BKIN input enable 0 1 DCR DCR control register 0x3DC 0x20 read-write 0x00000000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x3E0 0x20 read-write 0x00000000 DMAB DMA register for burst accesses 0 32 TIM8 0x40013400 TIM8_BRK TIM8_BRK 43 TIM8_UP TIM8_UP 44 TIM8_TRG_COM TIM8_TRG_COM 45 TIM2 Advanced-timers TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 28 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 DITHEN Dithering Enable 12 1 UIFREMAP UIF status bit remapping 11 1 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 MMS_3 Master mode selection - bit 3 25 1 MMS2 Master mode selection 2 20 4 OIS6 Output Idle state 6 (OC6 output) 18 1 OIS5 Output Idle state 5 (OC5 output) 16 1 OIS4N Output Idle state 4 (OC4N output) 15 1 OIS4 Output Idle state 4 14 1 OIS3N Output Idle state 3 13 1 OIS3 Output Idle state 3 12 1 OIS2N Output Idle state 2 11 1 OIS2 Output Idle state 2 10 1 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x00000000 SMSPS SMS Preload Source 25 1 SMSPE SMS Preload Enable 24 1 TS_4_3 Trigger selection - bit 4:3 20 2 SMS_3 Slave mode selection - bit 3 16 1 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 TERRIE Transition Error interrupt enable 23 1 IERRIE Index Error interrupt enable 22 1 DIRIE Direction Change interrupt enable 21 1 IDXIE Index interrupt enable 20 1 TDE Trigger DMA request enable 14 1 COMDE COM DMA request enable 13 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 TIE Trigger interrupt enable 6 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 BIE Break interrupt enable 7 1 COMIE COM interrupt enable 5 1 SR SR status register 0x10 0x20 read-write 0x00000000 TERRF Transition Error interrupt flag 23 1 IERRF Index Error interrupt flag 22 1 DIRF Direction Change interrupt flag 21 1 IDXF Index interrupt flag 20 1 CC6IF Compare 6 interrupt flag 17 1 CC5IF Compare 5 interrupt flag 16 1 SBIF System Break interrupt flag 13 1 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 B2IF Break 2 interrupt flag 8 1 BIF Break interrupt flag 7 1 TIF Trigger interrupt flag 6 1 COMIF COM interrupt flag 5 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 B2G Break 2 generation 8 1 BG Break generation 7 1 TG Trigger generation 6 1 COMG Capture/Compare control update generation 5 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC2CE Output Compare 2 clear enable 15 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 OC2FE Output Compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 ICPCS Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 OC4M_3 Output Compare 4 mode - bit 3 24 1 OC3M_3 Output Compare 3 mode - bit 3 16 1 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x00000000 CC6P Capture/Compare 6 output polarity 21 1 CC6E Capture/Compare 6 output enable 20 1 CC5P Capture/Compare 5 output polarity 17 1 CC5E Capture/Compare 5 output enable 16 1 CC4NP Capture/Compare 4 complementary output polarity 15 1 CC4NE Capture/Compare 4 complementary output enable 14 1 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 UIFCPY UIFCPY 31 1 CNT counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0xFFFFFFFF ARR Auto-reload value 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x00000000 REP Repetition counter value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2 Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3 Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4 Capture/Compare value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x00000000 BK2ID BK2ID 29 1 BKBID BKBID 28 1 BK2DSRM BK2DSRM 27 1 BKDSRM BKDSRM 26 1 BK2P Break 2 polarity 25 1 BK2E Break 2 Enable 24 1 BK2F Break 2 filter 20 4 BKF Break filter 16 4 MOE Main output enable 15 1 AOE Automatic output enable 14 1 BKP Break polarity 13 1 BKE Break enable 12 1 OSSR Off-state selection for Run mode 11 1 OSSI Off-state selection for Idle mode 10 1 LOCK Lock configuration 8 2 DTG Dead-time generator setup 0 8 CCR5 CCR5 capture/compare register 4 0x48 0x20 read-write 0x00000000 CCR5 Capture/Compare value 0 16 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 4 0x4C 0x20 read-write 0x00000000 CCR6 Capture/Compare value 0 16 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x50 0x20 read-write 0x00000000 OC6M_bit3 Output Compare 6 mode bit 3 24 1 OC5M_bit3 Output Compare 5 mode bit 3 16 3 OC6CE Output compare 6 clear enable 15 1 OC6M Output compare 6 mode 12 3 OC6PE Output compare 6 preload enable 11 1 OC6FE Output compare 6 fast enable 10 1 OC5CE Output compare 5 clear enable 7 1 OC5M Output compare 5 mode 4 3 OC5PE Output compare 5 preload enable 3 1 OC5FE Output compare 5 fast enable 2 1 DTR2 DTR2 timer Deadtime Register 2 0x54 0x20 read-write 0x00000000 DTPE Deadtime Preload Enable 17 1 DTAE Deadtime Asymmetric Enable 16 1 DTGF Dead-time falling edge generator setup 0 8 ECR ECR DMA control register 0x58 0x20 read-write 0x00000000 IE Index Enable 0 1 IDIR Index Direction 1 2 IBLK Index Blanking 3 2 FIDX First Index 5 1 IPOS Index Positioning 6 2 PW Pulse width 16 8 PWPRSC Pulse Width prescaler 24 3 TISEL TISEL TIM timer input selection register 0x5C 0x20 read-write 0x00000000 TI1SEL TI1[0] to TI1[15] input selection 0 4 TI2SEL TI2[0] to TI2[15] input selection 8 4 TI3SEL TI3[0] to TI3[15] input selection 16 4 TI4SEL TI4[0] to TI4[15] input selection 24 4 AF1 AF1 TIM alternate function option register 1 0x60 0x20 read-write 0x00000000 ETRSEL ETR source selection 14 4 BKCMP4P BRK COMP4 input polarity 13 1 BKCMP3P BRK COMP3 input polarity 12 1 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP1P BRK COMP1 input polarity 10 1 BKINP BRK BKIN input polarity 9 1 BKCMP7E BRK COMP7 enable 7 1 BKCMP6E BRK COMP6 enable 6 1 BKCMP5E BRK COMP5 enable 5 1 BKCMP4E BRK COMP4 enable 4 1 BKCMP3E BRK COMP3 enable 3 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP1E BRK COMP1 enable 1 1 BKINE BRK BKIN input enable 0 1 AF2 AF2 TIM alternate function option register 2 0x64 0x20 read-write 0x00000000 OCRSEL OCREF_CLR source selection 16 3 BK2CMP4P BRK2 COMP4 input polarity 13 1 BK2CMP3P BRK2 COMP3 input polarity 12 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2INP BRK2 BKIN input polarity 9 1 BK2CMP7E BRK2 COMP7 enable 7 1 BK2CMP6E BRK2 COMP6 enable 6 1 BK2CMP5E BRK2 COMP5 enable 5 1 BK2CMP4E BRK2 COMP4 enable 4 1 BK2CMP3E BRK2 COMP3 enable 3 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2CMP1E BRK2 COMP1 enable 1 1 BKINE BRK BKIN input enable 0 1 DCR DCR control register 0x3DC 0x20 read-write 0x00000000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x3E0 0x20 read-write 0x00000000 DMAB DMA register for burst accesses 0 32 TIM3 0x40000400 TIM3 TIM3 29 TIM4 0x40000800 TIM4 TIM4 30 TIM6 Basic-timers TIM 0x40001000 0x0 0x400 registers TIM6_DACUNDER TIM6_DACUNDER 54 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 DITHEN Dithering Enable 12 1 UIFREMAP UIF status bit remapping 11 1 ARPE Auto-reload preload enable 7 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 MMS Master mode selection 4 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x00000000 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x00000000 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x00000000 UG Update generation 0 1 CNT CNT counter 0x24 0x20 0x00000000 UIFCPY UIF Copy 31 1 read-only CNT Low counter value 0 16 read-write PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x0000FFFF ARR Low Auto-reload value 0 16 TIM7 0x40001400 TIM7 TIM7 55 LPTIMER1 Low power timer LPTIM 0x40007C00 0x0 0x400 registers ISR ISR Interrupt and Status Register 0x0 0x20 read-only 0x00000000 DOWN Counter direction change up to down 6 1 UP Counter direction change down to up 5 1 ARROK Autoreload register update OK 4 1 CMPOK Compare register update OK 3 1 EXTTRIG External trigger edge event 2 1 ARRM Autoreload match 1 1 CMPM Compare match 0 1 ICR ICR Interrupt Clear Register 0x4 0x20 write-only 0x00000000 DOWNCF Direction change to down Clear Flag 6 1 UPCF Direction change to UP Clear Flag 5 1 ARROKCF Autoreload register update OK Clear Flag 4 1 CMPOKCF Compare register update OK Clear Flag 3 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 ARRMCF Autoreload match Clear Flag 1 1 CMPMCF compare match Clear Flag 0 1 IER IER Interrupt Enable Register 0x8 0x20 read-write 0x00000000 DOWNIE Direction change to down Interrupt Enable 6 1 UPIE Direction change to UP Interrupt Enable 5 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 CMPOKIE Compare register update OK Interrupt Enable 3 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 ARRMIE Autoreload match Interrupt Enable 1 1 CMPMIE Compare match Interrupt Enable 0 1 CFGR CFGR Configuration Register 0xC 0x20 read-write 0x00000000 ENC Encoder mode enable 24 1 COUNTMODE counter mode enabled 23 1 PRELOAD Registers update mode 22 1 WAVPOL Waveform shape polarity 21 1 WAVE Waveform shape 20 1 TIMOUT Timeout enable 19 1 TRIGEN Trigger enable and polarity 17 2 TRIGSEL Trigger selector 13 4 PRESC Clock prescaler 9 3 TRGFLT Configurable digital filter for trigger 6 2 CKFLT Configurable digital filter for external clock 3 2 CKPOL Clock Polarity 1 2 CKSEL Clock selector 0 1 CR CR Control Register 0x10 0x20 read-write 0x00000000 RSTARE RSTARE 4 1 COUNTRST COUNTRST 3 1 CNTSTRT Timer start in continuous mode 2 1 SNGSTRT LPTIM start in single mode 1 1 ENABLE LPTIM Enable 0 1 CMP CMP Compare Register 0x14 0x20 read-write 0x00000000 CMP Compare value 0 16 ARR ARR Autoreload Register 0x18 0x20 read-write 0x00000001 ARR Auto reload value 0 16 CNT CNT Counter Register 0x1C 0x20 read-only 0x00000000 CNT Counter value 0 16 OR OR option register 0x20 0x20 read-write 0x00000000 IN1 IN1 0 1 IN2 IN2 1 1 IN1_2_1 IN1_2_1 2 2 IN2_2_1 IN2_2_1 4 2 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 37 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 RXFFIE RXFFIE 31 1 TXFEIE TXFEIE 30 1 FIFOEN FIFOEN 29 1 M1 M1 28 1 EOBIE End of Block interrupt enable 27 1 RTOIE Receiver timeout interrupt enable 26 1 DEAT4 Driver Enable assertion time 25 1 DEAT3 DEAT3 24 1 DEAT2 DEAT2 23 1 DEAT1 DEAT1 22 1 DEAT0 DEAT0 21 1 DEDT4 Driver Enable de-assertion time 20 1 DEDT3 DEDT3 19 1 DEDT2 DEDT2 18 1 DEDT1 DEDT1 17 1 DEDT0 DEDT0 16 1 OVER8 Oversampling mode 15 1 CMIE Character match interrupt enable 14 1 MME Mute mode enable 13 1 M0 Word length 12 1 WAKE Receiver wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXEIE interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXNEIE RXNE interrupt enable 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 UESM USART enable in Stop mode 1 1 UE USART enable 0 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 ADD4_7 Address of the USART node 28 4 ADD0_3 Address of the USART node 24 4 RTOEN Receiver timeout enable 23 1 ABRMOD1 Auto baud rate mode 22 1 ABRMOD0 ABRMOD0 21 1 ABREN Auto baud rate enable 20 1 MSBFIRST Most significant bit first 19 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 RXINV RX pin active level inversion 16 1 SWAP Swap TX/RX pins 15 1 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CLKEN Clock enable 11 1 CPOL Clock polarity 10 1 CPHA Clock phase 9 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 DIS_NSS DIS_NSS 3 1 SLVEN SLVEN 0 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x00000000 TXFTCFG TXFTCFG 29 3 RXFTIE RXFTIE 28 1 RXFTCFG RXFTCFG 25 3 TCBGTIE TCBGTIE 24 1 TXFTIE TXFTIE 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 SCARCNT Smartcard auto-retry count 17 3 DEP Driver enable polarity selection 15 1 DEM Driver enable mode 14 1 DDRE DMA Disable on Reception Error 13 1 OVRDIS Overrun Disable 12 1 ONEBIT One sample bit method enable 11 1 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 SCEN Smartcard mode enable 5 1 NACK Smartcard NACK enable 4 1 HDSEL Half-duplex selection 3 1 IRLP Ir low-power 2 1 IREN Ir mode enable 1 1 EIE Error interrupt enable 0 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x00000000 DIV_Mantissa DIV_Mantissa 4 12 DIV_Fraction DIV_Fraction 0 4 GTPR GTPR Guard time and prescaler register 0x10 0x20 read-write 0x00000000 GT Guard time value 8 8 PSC Prescaler value 0 8 RTOR RTOR Receiver timeout register 0x14 0x20 read-write 0x00000000 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 RQR RQR Request register 0x18 0x20 write-only 0x00000000 TXFRQ Transmit data flush request 4 1 RXFRQ Receive data flush request 3 1 MMRQ Mute mode request 2 1 SBKRQ Send break request 1 1 ABRRQ Auto baud rate request 0 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x00000000 TXFT TXFT 27 1 RXFT RXFT 26 1 TCBGT TCBGT 25 1 RXFF RXFF 24 1 TXFE TXFE 23 1 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 SBKF SBKF 18 1 CMF CMF 17 1 BUSY BUSY 16 1 ABRF ABRF 15 1 ABRE ABRE 14 1 UDR UDR 13 1 EOBF EOBF 12 1 RTOF RTOF 11 1 CTS CTS 10 1 CTSIF CTSIF 9 1 LBDF LBDF 8 1 TXE TXE 7 1 TC TC 6 1 RXNE RXNE 5 1 IDLE IDLE 4 1 ORE ORE 3 1 NF NF 2 1 FE FE 1 1 PE PE 0 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x00000000 WUCF Wakeup from Stop mode clear flag 20 1 CMCF Character match clear flag 17 1 UDRCF UDRCF 13 1 EOBCF End of block clear flag 12 1 RTOCF Receiver timeout clear flag 11 1 CTSCF CTS clear flag 9 1 LBDCF LIN break detection clear flag 8 1 TCBGTCF TCBGTCF 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFECF 5 1 IDLECF Idle line detected clear flag 4 1 ORECF Overrun error clear flag 3 1 NCF Noise detected clear flag 2 1 FECF Framing error clear flag 1 1 PECF Parity error clear flag 0 1 RDR RDR Receive data register 0x24 0x20 read-only 0x00000000 RDR Receive data value 0 9 TDR TDR Transmit data register 0x28 0x20 read-write 0x00000000 TDR Transmit data value 0 9 PRESC PRESC USART prescaler register 0x2C 0x20 read-write 0x00000000 PRESCALER PRESCALER 0 4 USART2 0x40004400 USART2 USART2 38 USART3 0x40004800 USART3 USART3 39 UART4 Universal synchronous asynchronous receiver transmitter USART 0x40004C00 0x0 0x400 registers UART4 UART4 52 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 RXFFIE RXFFIE 31 1 TXFEIE TXFEIE 30 1 FIFOEN FIFOEN 29 1 M1 M1 28 1 EOBIE End of Block interrupt enable 27 1 RTOIE Receiver timeout interrupt enable 26 1 DEAT4 Driver Enable assertion time 25 1 DEAT3 DEAT3 24 1 DEAT2 DEAT2 23 1 DEAT1 DEAT1 22 1 DEAT0 DEAT0 21 1 DEDT4 Driver Enable de-assertion time 20 1 DEDT3 DEDT3 19 1 DEDT2 DEDT2 18 1 DEDT1 DEDT1 17 1 DEDT0 DEDT0 16 1 OVER8 Oversampling mode 15 1 CMIE Character match interrupt enable 14 1 MME Mute mode enable 13 1 M0 Word length 12 1 WAKE Receiver wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXEIE interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXNEIE RXNE interrupt enable 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 UESM USART enable in Stop mode 1 1 UE USART enable 0 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 ADD4_7 Address of the USART node 28 4 ADD0_3 Address of the USART node 24 4 RTOEN Receiver timeout enable 23 1 ABRMOD1 Auto baud rate mode 22 1 ABRMOD0 ABRMOD0 21 1 ABREN Auto baud rate enable 20 1 MSBFIRST Most significant bit first 19 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 RXINV RX pin active level inversion 16 1 SWAP Swap TX/RX pins 15 1 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CLKEN Clock enable 11 1 CPOL Clock polarity 10 1 CPHA Clock phase 9 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 DIS_NSS DIS_NSS 3 1 SLVEN SLVEN 0 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x00000000 TXFTCFG TXFTCFG 29 3 RXFTIE RXFTIE 28 1 RXFTCFG RXFTCFG 25 3 TCBGTIE TCBGTIE 24 1 TXFTIE TXFTIE 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 SCARCNT Smartcard auto-retry count 17 3 DEP Driver enable polarity selection 15 1 DEM Driver enable mode 14 1 DDRE DMA Disable on Reception Error 13 1 OVRDIS Overrun Disable 12 1 ONEBIT One sample bit method enable 11 1 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 SCEN Smartcard mode enable 5 1 NACK Smartcard NACK enable 4 1 HDSEL Half-duplex selection 3 1 IRLP Ir low-power 2 1 IREN Ir mode enable 1 1 EIE Error interrupt enable 0 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x00000000 DIV_Mantissa DIV_Mantissa 4 12 DIV_Fraction DIV_Fraction 0 4 GTPR GTPR Guard time and prescaler register 0x10 0x20 read-write 0x00000000 GT Guard time value 8 8 PSC Prescaler value 0 8 RTOR RTOR Receiver timeout register 0x14 0x20 read-write 0x00000000 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 RQR RQR Request register 0x18 0x20 write-only 0x00000000 TXFRQ Transmit data flush request 4 1 RXFRQ Receive data flush request 3 1 MMRQ Mute mode request 2 1 SBKRQ Send break request 1 1 ABRRQ Auto baud rate request 0 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x000000C0 TXFT TXFT 27 1 RXFT RXFT 26 1 TCBGT TCBGT 25 1 RXFF RXFF 24 1 TXFE TXFE 23 1 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 SBKF SBKF 18 1 CMF CMF 17 1 BUSY BUSY 16 1 ABRF ABRF 15 1 ABRE ABRE 14 1 UDR UDR 13 1 EOBF EOBF 12 1 RTOF RTOF 11 1 CTS CTS 10 1 CTSIF CTSIF 9 1 LBDF LBDF 8 1 TXE TXE 7 1 TC TC 6 1 RXNE RXNE 5 1 IDLE IDLE 4 1 ORE ORE 3 1 NF NF 2 1 FE FE 1 1 PE PE 0 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x00000000 WUCF Wakeup from Stop mode clear flag 20 1 CMCF Character match clear flag 17 1 UDRCF UDRCF 13 1 EOBCF End of block clear flag 12 1 RTOCF Receiver timeout clear flag 11 1 CTSCF CTS clear flag 9 1 LBDCF LIN break detection clear flag 8 1 TCBGTCF TCBGTCF 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFECF 5 1 IDLECF Idle line detected clear flag 4 1 ORECF Overrun error clear flag 3 1 NCF Noise detected clear flag 2 1 FECF Framing error clear flag 1 1 PECF Parity error clear flag 0 1 RDR RDR Receive data register 0x24 0x20 read-only 0x00000000 RDR Receive data value 0 9 TDR TDR Transmit data register 0x28 0x20 read-write 0x00000000 TDR Transmit data value 0 9 PRESC PRESC USART prescaler register 0x2C 0x20 read-write 0x00000000 PRESCALER PRESCALER 0 4 LPUART1 Universal synchronous asynchronous receiver transmitter USART 0x40008000 0x0 0x400 registers LPTIM1 LPTIM1 49 LPUART LPUART 91 CR1 CR1 Control register 1 0x0 0x20 read-write 0x0000 RXFFIE RXFFIE 31 1 TXFEIE TXFEIE 30 1 FIFOEN FIFOEN 29 1 M1 Word length 28 1 DEAT4 Driver Enable assertion time 25 1 DEAT3 DEAT3 24 1 DEAT2 DEAT2 23 1 DEAT1 DEAT1 22 1 DEAT0 DEAT0 21 1 DEDT4 Driver Enable de-assertion time 20 1 DEDT3 DEDT3 19 1 DEDT2 DEDT2 18 1 DEDT1 DEDT1 17 1 DEDT0 DEDT0 16 1 CMIE Character match interrupt enable 14 1 MME Mute mode enable 13 1 M0 Word length 12 1 WAKE Receiver wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXEIE interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXNEIE RXNE interrupt enable 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 UESM USART enable in Stop mode 1 1 UE USART enable 0 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x0000 ADD4_7 Address of the USART node 28 4 ADD0_3 Address of the USART node 24 4 MSBFIRST Most significant bit first 19 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 RXINV RX pin active level inversion 16 1 SWAP Swap TX/RX pins 15 1 STOP STOP bits 12 2 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x0000 TXFTCFG TXFTCFG 29 3 RXFTIE RXFTIE 28 1 RXFTCFG RXFTCFG 25 3 TXFTIE TXFTIE 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 DEP Driver enable polarity selection 15 1 DEM Driver enable mode 14 1 DDRE DMA Disable on Reception Error 13 1 OVRDIS Overrun Disable 12 1 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 HDSEL Half-duplex selection 3 1 EIE Error interrupt enable 0 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x0000 BRR BRR 0 20 RQR RQR Request register 0x18 0x20 write-only 0x0000 TXFRQ TXFRQ 4 1 RXFRQ Receive data flush request 3 1 MMRQ Mute mode request 2 1 SBKRQ Send break request 1 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x00C0 TXFT TXFT 27 1 RXFT RXFT 26 1 RXFF RXFF 24 1 TXFE TXFE 23 1 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 SBKF SBKF 18 1 CMF CMF 17 1 BUSY BUSY 16 1 CTS CTS 10 1 CTSIF CTSIF 9 1 TXE TXE 7 1 TC TC 6 1 RXNE RXNE 5 1 IDLE IDLE 4 1 ORE ORE 3 1 NF NF 2 1 FE FE 1 1 PE PE 0 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x0000 WUCF Wakeup from Stop mode clear flag 20 1 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 TCCF Transmission complete clear flag 6 1 IDLECF Idle line detected clear flag 4 1 ORECF Overrun error clear flag 3 1 NCF Noise detected clear flag 2 1 FECF Framing error clear flag 1 1 PECF Parity error clear flag 0 1 RDR RDR Receive data register 0x24 0x20 read-only 0x0000 RDR Receive data value 0 9 TDR TDR Transmit data register 0x28 0x20 read-write 0x0000 TDR Transmit data value 0 9 PRESC PRESC Prescaler register 0x2C 0x20 read-write 0x0000 PRESCALER PRESCALER 0 4 SPI1 Serial peripheral interface/Inter-IC sound SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 35 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 RXONLY Receive only 10 1 SSM Software slave management 9 1 SSI Internal slave select 8 1 LSBFIRST Frame format 7 1 SPE SPI enable 6 1 BR Baud rate control 3 3 MSTR Master selection 2 1 CPOL Clock polarity 1 1 CPHA Clock phase 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000700 RXDMAEN Rx buffer DMA enable 0 1 TXDMAEN Tx buffer DMA enable 1 1 SSOE SS output enable 2 1 NSSP NSS pulse management 3 1 FRF Frame format 4 1 ERRIE Error interrupt enable 5 1 RXNEIE RX buffer not empty interrupt enable 6 1 TXEIE Tx buffer empty interrupt enable 7 1 DS Data size 8 4 FRXTH FIFO reception threshold 12 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_TX Last DMA transfer for transmission 14 1 SR SR status register 0x8 0x20 0x00000002 RXNE Receive buffer not empty 0 1 read-only TXE Transmit buffer empty 1 1 read-only CRCERR CRC error flag 4 1 read-write MODF Mode fault 5 1 read-only OVR Overrun flag 6 1 read-only BSY Busy flag 7 1 read-only TIFRFE TI frame format error 8 1 read-only FRLVL FIFO reception level 9 2 read-only FTLVL FIFO transmission level 11 2 read-only DR DR data register 0xC 0x20 read-write 0x00000000 DR Data register 0 16 CRCPR CRCPR CRC polynomial register 0x10 0x20 read-write 0x00000007 CRCPOLY CRC polynomial register 0 16 RXCRCR RXCRCR RX CRC register 0x14 0x20 read-only 0x00000000 RxCRC Rx CRC register 0 16 TXCRCR TXCRCR TX CRC register 0x18 0x20 read-only 0x00000000 TxCRC Tx CRC register 0 16 I2SCFGR I2SCFGR configuration register 0x1C 0x20 read-write 0x00000000 CHLEN CHLEN 0 1 DATLEN DATLEN 1 2 CKPOL CKPOL 3 1 I2SSTD I2SSTD 4 2 PCMSYNC PCMSYNC 7 1 I2SCFG I2SCFG 8 2 I2SE I2SE 10 1 I2SMOD I2SMOD 11 1 I2SPR I2SPR prescaler register 0x20 0x20 read-write 0x00000002 I2SDIV I2SDIV 0 8 ODD ODD 8 1 MCKOE MCKOE 9 1 SPI3 0x40003C00 SPI3 SPI3 51 SPI2 0x40003800 SPI2 SPI2 36 EXTI External interrupt/event controller EXTI 0x40010400 0x0 0x400 registers PVD_PVM PVD through EXTI line detection 1 EXTI0 EXTI Line0 interrupt 6 EXTI1 EXTI Line1 interrupt 7 EXTI2 EXTI Line2 interrupt 8 EXTI3 EXTI Line3 interrupt 9 EXTI4 EXTI Line4 interrupt 10 USB_HP USB_HP 19 USB_LP USB_LP 20 EXTI9_5 EXTI9_5 23 EXTI15_10 EXTI15_10 40 USBWakeUP USBWakeUP 42 CRS CRS 75 IMR1 IMR1 Interrupt mask register 0x0 0x20 read-write 0xFF820000 IM0 Interrupt Mask on line 0 0 1 IM1 Interrupt Mask on line 1 1 1 IM2 Interrupt Mask on line 2 2 1 IM3 Interrupt Mask on line 3 3 1 IM4 Interrupt Mask on line 4 4 1 IM5 Interrupt Mask on line 5 5 1 IM6 Interrupt Mask on line 6 6 1 IM7 Interrupt Mask on line 7 7 1 IM8 Interrupt Mask on line 8 8 1 IM9 Interrupt Mask on line 9 9 1 IM10 Interrupt Mask on line 10 10 1 IM11 Interrupt Mask on line 11 11 1 IM12 Interrupt Mask on line 12 12 1 IM13 Interrupt Mask on line 13 13 1 IM14 Interrupt Mask on line 14 14 1 IM15 Interrupt Mask on line 15 15 1 IM16 Interrupt Mask on line 16 16 1 IM17 Interrupt Mask on line 17 17 1 IM18 Interrupt Mask on line 18 18 1 IM19 Interrupt Mask on line 19 19 1 IM20 Interrupt Mask on line 20 20 1 IM21 Interrupt Mask on line 21 21 1 IM22 Interrupt Mask on line 22 22 1 IM23 Interrupt Mask on line 23 23 1 IM24 Interrupt Mask on line 24 24 1 IM25 Interrupt Mask on line 25 25 1 IM26 Interrupt Mask on line 26 26 1 IM27 Interrupt Mask on line 27 27 1 IM28 Interrupt Mask on line 28 28 1 IM29 Interrupt Mask on line 29 29 1 IM30 Interrupt Mask on line 30 30 1 IM31 Interrupt Mask on line 31 31 1 EMR1 EMR1 Event mask register 0x4 0x20 read-write 0x00000000 EM0 Event Mask on line 0 0 1 EM1 Event Mask on line 1 1 1 EM2 Event Mask on line 2 2 1 EM3 Event Mask on line 3 3 1 EM4 Event Mask on line 4 4 1 EM5 Event Mask on line 5 5 1 EM6 Event Mask on line 6 6 1 EM7 Event Mask on line 7 7 1 EM8 Event Mask on line 8 8 1 EM9 Event Mask on line 9 9 1 EM10 Event Mask on line 10 10 1 EM11 Event Mask on line 11 11 1 EM12 Event Mask on line 12 12 1 EM13 Event Mask on line 13 13 1 EM14 Event Mask on line 14 14 1 EM15 Event Mask on line 15 15 1 EM16 Event Mask on line 16 16 1 EM17 Event Mask on line 17 17 1 EM18 Event Mask on line 18 18 1 EM19 Event Mask on line 19 19 1 EM20 Event Mask on line 20 20 1 EM21 Event Mask on line 21 21 1 EM22 Event Mask on line 22 22 1 EM23 Event Mask on line 23 23 1 EM24 Event Mask on line 24 24 1 EM25 Event Mask on line 25 25 1 EM26 Event Mask on line 26 26 1 EM27 Event Mask on line 27 27 1 EM28 Event Mask on line 28 28 1 EM29 Event Mask on line 29 29 1 EM30 Event Mask on line 30 30 1 EM31 Event Mask on line 31 31 1 RTSR1 RTSR1 Rising Trigger selection register 0x8 0x20 read-write 0x00000000 RT0 Rising trigger event configuration of line 0 0 1 RT1 Rising trigger event configuration of line 1 1 1 RT2 Rising trigger event configuration of line 2 2 1 RT3 Rising trigger event configuration of line 3 3 1 RT4 Rising trigger event configuration of line 4 4 1 RT5 Rising trigger event configuration of line 5 5 1 RT6 Rising trigger event configuration of line 6 6 1 RT7 Rising trigger event configuration of line 7 7 1 RT8 Rising trigger event configuration of line 8 8 1 RT9 Rising trigger event configuration of line 9 9 1 RT10 Rising trigger event configuration of line 10 10 1 RT11 Rising trigger event configuration of line 11 11 1 RT12 Rising trigger event configuration of line 12 12 1 RT13 Rising trigger event configuration of line 13 13 1 RT14 Rising trigger event configuration of line 14 14 1 RT15 Rising trigger event configuration of line 15 15 1 RT16 Rising trigger event configuration of line 16 16 1 RT18 Rising trigger event configuration of line 18 18 1 RT19 Rising trigger event configuration of line 19 19 1 RT20 Rising trigger event configuration of line 20 20 1 RT21 Rising trigger event configuration of line 21 21 1 RT22 Rising trigger event configuration of line 22 22 1 RT RT 29 3 FTSR1 FTSR1 Falling Trigger selection register 0xC 0x20 read-write 0x00000000 FT0 Falling trigger event configuration of line 0 0 1 FT1 Falling trigger event configuration of line 1 1 1 FT2 Falling trigger event configuration of line 2 2 1 FT3 Falling trigger event configuration of line 3 3 1 FT4 Falling trigger event configuration of line 4 4 1 FT5 Falling trigger event configuration of line 5 5 1 FT6 Falling trigger event configuration of line 6 6 1 FT7 Falling trigger event configuration of line 7 7 1 FT8 Falling trigger event configuration of line 8 8 1 FT9 Falling trigger event configuration of line 9 9 1 FT10 Falling trigger event configuration of line 10 10 1 FT11 Falling trigger event configuration of line 11 11 1 FT12 Falling trigger event configuration of line 12 12 1 FT13 Falling trigger event configuration of line 13 13 1 FT14 Falling trigger event configuration of line 14 14 1 FT15 Falling trigger event configuration of line 15 15 1 FT16 Falling trigger event configuration of line 16 16 1 FT18 Falling trigger event configuration of line 18 18 1 FT19 Falling trigger event configuration of line 19 19 1 FT20 Falling trigger event configuration of line 20 20 1 FT21 Falling trigger event configuration of line 21 21 1 FT22 Falling trigger event configuration of line 22 22 1 SWIER1 SWIER1 Software interrupt event register 0x10 0x20 read-write 0x00000000 SWI0 Software Interrupt on line 0 0 1 SWI1 Software Interrupt on line 1 1 1 SWI2 Software Interrupt on line 2 2 1 SWI3 Software Interrupt on line 3 3 1 SWI4 Software Interrupt on line 4 4 1 SWI5 Software Interrupt on line 5 5 1 SWI6 Software Interrupt on line 6 6 1 SWI7 Software Interrupt on line 7 7 1 SWI8 Software Interrupt on line 8 8 1 SWI9 Software Interrupt on line 9 9 1 SWI10 Software Interrupt on line 10 10 1 SWI11 Software Interrupt on line 11 11 1 SWI12 Software Interrupt on line 12 12 1 SWI13 Software Interrupt on line 13 13 1 SWI14 Software Interrupt on line 14 14 1 SWI15 Software Interrupt on line 15 15 1 SWI16 Software Interrupt on line 16 16 1 SWI18 Software Interrupt on line 18 18 1 SWI19 Software Interrupt on line 19 19 1 SWI20 Software Interrupt on line 20 20 1 SWI21 Software Interrupt on line 21 21 1 SWI22 Software Interrupt on line 22 22 1 PR1 PR1 Pending register 0x14 0x20 read-write 0x00000000 PIF0 Pending bit 0 0 1 PIF1 Pending bit 1 1 1 PIF2 Pending bit 2 2 1 PIF3 Pending bit 3 3 1 PIF4 Pending bit 4 4 1 PIF5 Pending bit 5 5 1 PIF6 Pending bit 6 6 1 PIF7 Pending bit 7 7 1 PIF8 Pending bit 8 8 1 PIF9 Pending bit 9 9 1 PIF10 Pending bit 10 10 1 PIF11 Pending bit 11 11 1 PIF12 Pending bit 12 12 1 PIF13 Pending bit 13 13 1 PIF14 Pending bit 14 14 1 PIF15 Pending bit 15 15 1 PIF16 Pending bit 16 16 1 PIF18 Pending bit 18 18 1 PIF19 Pending bit 19 19 1 PIF20 Pending bit 20 20 1 PIF21 Pending bit 21 21 1 PIF22 Pending bit 22 22 1 IMR2 IMR2 Interrupt mask register 0x20 0x20 read-write 0xFFFFFF87 IM32 Interrupt Mask on external/internal line 32 0 1 IM33 Interrupt Mask on external/internal line 33 1 1 IM34 Interrupt Mask on external/internal line 34 2 1 IM35 Interrupt Mask on external/internal line 35 3 1 IM36 Interrupt Mask on external/internal line 36 4 1 IM37 Interrupt Mask on external/internal line 37 5 1 IM38 Interrupt Mask on external/internal line 38 6 1 IM39 Interrupt Mask on external/internal line 39 7 1 IM40 Interrupt Mask on external/internal line 40 8 1 IM41 Interrupt Mask on external/internal line 41 9 1 IM42 Interrupt Mask on external/internal line 42 10 1 IM43 Interrupt Mask on external/internal line 43 11 1 EMR2 EMR2 Event mask register 0x24 0x20 read-write 0x00000000 EM32 Event mask on external/internal line 32 0 1 EM33 Event mask on external/internal line 33 1 1 EM34 Event mask on external/internal line 34 2 1 EM35 Event mask on external/internal line 35 3 1 EM36 Event mask on external/internal line 36 4 1 EM37 Event mask on external/internal line 37 5 1 EM38 Event mask on external/internal line 38 6 1 EM39 Event mask on external/internal line 39 7 1 EM40 Event mask on external/internal line 40 8 1 RTSR2 RTSR2 Rising Trigger selection register 0x28 0x20 read-write 0x00000000 RT32 Rising trigger event configuration bit of line 32 0 1 RT33 Rising trigger event configuration bit of line 32 1 1 RT38 Rising trigger event configuration bit of line 38 6 1 RT39 Rising trigger event configuration bit of line 39 7 1 RT40 Rising trigger event configuration bit of line 40 8 1 RT41 Rising trigger event configuration bit of line 41 9 1 FTSR2 FTSR2 Falling Trigger selection register 0x2C 0x20 read-write 0x00000000 FT35 Falling trigger event configuration bit of line 35 3 1 FT36 Falling trigger event configuration bit of line 36 4 1 FT37 Falling trigger event configuration bit of line 37 5 1 FT38 Falling trigger event configuration bit of line 38 6 1 SWIER2 SWIER2 Software interrupt event register 0x30 0x20 read-write 0x00000000 SWI35 Software interrupt on line 35 3 1 SWI36 Software interrupt on line 36 4 1 SWI37 Software interrupt on line 37 5 1 SWI38 Software interrupt on line 38 6 1 PR2 PR2 Pending register 0x34 0x20 read-write 0x00000000 PIF35 Pending interrupt flag on line 35 3 1 PIF36 Pending interrupt flag on line 36 4 1 PIF37 Pending interrupt flag on line 37 5 1 PIF38 Pending interrupt flag on line 38 6 1 RTC Real-time clock RTC 0x40002800 0x0 0x400 registers RTC_TAMP_CSS_LSE RTC_TAMP_CSS_LSE 2 RTC_WKUP RTC Wakeup timer 3 RTC_ALARM RTC_ALARM 41 TR TR time register 0x0 0x20 read-write 0x00000000 PM AM/PM notation 22 1 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 DR DR date register 0x4 0x20 read-write 0x00002101 YT Year tens in BCD format 20 4 YU Year units in BCD format 16 4 WDU Week day units 13 3 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 SSR SSR sub second register 0x8 0x20 read-only 0x00000000 SS Sub second value 0 16 ICSR ICSR initialization and status register 0xC 0x20 0x00000007 ALRAWF Alarm A write flag 0 1 read-only ALRBWF Alarm B write flag 1 1 read-only WUTWF Wakeup timer write flag 2 1 read-only SHPF Shift operation pending 3 1 read-write INITS Initialization status flag 4 1 read-only RSF Registers synchronization flag 5 1 read-write INITF Initialization flag 6 1 read-only INIT Initialization mode 7 1 read-write RECALPF Recalibration pending Flag 16 1 read-only PRER PRER prescaler register 0x10 0x20 read-write 0x007F00FF PREDIV_A Asynchronous prescaler factor 16 7 PREDIV_S Synchronous prescaler factor 0 15 WUTR WUTR wakeup timer register 0x14 0x20 read-write 0x0000FFFF WUT Wakeup auto-reload value bits 0 16 CR CR control register 0x18 0x20 read-write 0x00000000 WCKSEL Wakeup clock selection 0 3 TSEDGE Time-stamp event active edge 3 1 REFCKON Reference clock detection enable (50 or 60 Hz) 4 1 BYPSHAD Bypass the shadow registers 5 1 FMT Hour format 6 1 ALRAE Alarm A enable 8 1 ALRBE Alarm B enable 9 1 WUTE Wakeup timer enable 10 1 TSE Time stamp enable 11 1 ALRAIE Alarm A interrupt enable 12 1 ALRBIE Alarm B interrupt enable 13 1 WUTIE Wakeup timer interrupt enable 14 1 TSIE Time-stamp interrupt enable 15 1 ADD1H Add 1 hour (summer time change) 16 1 SUB1H Subtract 1 hour (winter time change) 17 1 BKP Backup 18 1 COSEL Calibration output selection 19 1 POL Output polarity 20 1 OSEL Output selection 21 2 COE Calibration output enable 23 1 ITSE timestamp on internal event enable 24 1 TAMPTS TAMPTS 25 1 TAMPOE TAMPOE 26 1 TAMPALRM_PU TAMPALRM_PU 29 1 TAMPALRM_TYPE TAMPALRM_TYPE 30 1 OUT2EN OUT2EN 31 1 WPR WPR write protection register 0x24 0x20 write-only 0x00000000 KEY Write protection key 0 8 CALR CALR calibration register 0x28 0x20 read-write 0x00000000 CALP Increase frequency of RTC by 488.5 ppm 15 1 CALW8 Use an 8-second calibration cycle period 14 1 CALW16 Use a 16-second calibration cycle period 13 1 CALM Calibration minus 0 9 SHIFTR SHIFTR shift control register 0x2C 0x20 write-only 0x00000000 ADD1S Add one second 31 1 SUBFS Subtract a fraction of a second 0 15 TSTR TSTR time stamp time register 0x30 0x20 read-only 0x00000000 SU Second units in BCD format 0 4 ST Second tens in BCD format 4 3 MNU Minute units in BCD format 8 4 MNT Minute tens in BCD format 12 3 HU Hour units in BCD format 16 4 HT Hour tens in BCD format 20 2 PM AM/PM notation 22 1 TSDR TSDR time stamp date register 0x34 0x20 read-only 0x00000000 WDU Week day units 13 3 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 TSSSR TSSSR timestamp sub second register 0x38 0x20 read-only 0x00000000 SS Sub second value 0 16 ALRMAR ALRMAR alarm A register 0x40 0x20 read-write 0x00000000 MSK4 Alarm A date mask 31 1 WDSEL Week day selection 30 1 DT Date tens in BCD format 28 2 DU Date units or day in BCD format 24 4 MSK3 Alarm A hours mask 23 1 PM AM/PM notation 22 1 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MSK2 Alarm A minutes mask 15 1 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 MSK1 Alarm A seconds mask 7 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 ALRMASSR ALRMASSR alarm A sub second register 0x44 0x20 read-write 0x00000000 MASKSS Mask the most-significant bits starting at this bit 24 4 SS Sub seconds value 0 15 ALRMBR ALRMBR alarm B register 0x48 0x20 read-write 0x00000000 MSK4 Alarm B date mask 31 1 WDSEL Week day selection 30 1 DT Date tens in BCD format 28 2 DU Date units or day in BCD format 24 4 MSK3 Alarm B hours mask 23 1 PM AM/PM notation 22 1 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MSK2 Alarm B minutes mask 15 1 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 MSK1 Alarm B seconds mask 7 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 ALRMBSSR ALRMBSSR alarm B sub second register 0x4C 0x20 read-write 0x00000000 MASKSS Mask the most-significant bits starting at this bit 24 4 SS Sub seconds value 0 15 SR SR status register 0x50 0x20 read-only 0x00000000 ALRAF ALRAF 0 1 ALRBF ALRBF 1 1 WUTF WUTF 2 1 TSF TSF 3 1 TSOVF TSOVF 4 1 ITSF ITSF 5 1 MISR MISR status register 0x54 0x20 read-only 0x00000000 ALRAMF ALRAMF 0 1 ALRBMF ALRBMF 1 1 WUTMF WUTMF 2 1 TSMF TSMF 3 1 TSOVMF TSOVMF 4 1 ITSMF ITSMF 5 1 SCR SCR status register 0x5C 0x20 write-only 0x00000000 CALRAF CALRAF 0 1 CALRBF CALRBF 1 1 CWUTF CWUTF 2 1 CTSF CTSF 3 1 CTSOVF CTSOVF 4 1 CITSF CITSF 5 1 DMA1 DMA controller DMA 0x40020000 0x0 0x400 registers DMA1_CH1 DMA1 channel 1 interrupt 11 DMA1_CH2 DMA1 channel 2 interrupt 12 DMA1_CH3 DMA1 channel 3 interrupt 13 DMA1_CH4 DMA1 channel 4 interrupt 14 DMA1_CH5 DMA1 channel 5 interrupt 15 DMA1_CH6 DMA1 channel 6 interrupt 16 ISR ISR interrupt status register 0x0 0x20 read-only 0x00000000 TEIF8 TEIF8 31 1 HTIF8 HTIF8 30 1 TCIF8 TCIF8 29 1 GIF8 GIF8 28 1 TEIF7 TEIF7 27 1 HTIF7 HTIF7 26 1 TCIF7 TCIF7 25 1 GIF7 GIF7 24 1 TEIF6 TEIF6 23 1 HTIF6 HTIF6 22 1 TCIF6 TCIF6 21 1 GIF6 GIF6 20 1 TEIF5 TEIF5 19 1 HTIF5 HTIF5 18 1 TCIF5 TCIF5 17 1 GIF5 GIF5 16 1 TEIF4 TEIF4 15 1 HTIF4 HTIF4 14 1 TCIF4 TCIF4 13 1 GIF4 GIF4 12 1 TEIF3 TEIF3 11 1 HTIF3 HTIF3 10 1 TCIF3 TCIF3 9 1 GIF3 GIF3 8 1 TEIF2 TEIF2 7 1 HTIF2 HTIF2 6 1 TCIF2 TCIF2 5 1 GIF2 GIF2 4 1 TEIF1 TEIF1 3 1 HTIF1 HTIF1 2 1 TCIF1 TCIF1 1 1 GIF1 GIF1 0 1 IFCR IFCR DMA interrupt flag clear register 0x4 0x20 write-only 0x00000000 TEIF8 TEIF8 31 1 HTIF8 HTIF8 30 1 TCIF8 TCIF8 29 1 GIF8 GIF8 28 1 TEIF7 TEIF7 27 1 HTIF7 HTIF7 26 1 TCIF7 TCIF7 25 1 GIF7 GIF7 24 1 TEIF6 TEIF6 23 1 HTIF6 HTIF6 22 1 TCIF6 TCIF6 21 1 GIF6 GIF6 20 1 TEIF5 TEIF5 19 1 HTIF5 HTIF5 18 1 TCIF5 TCIF5 17 1 GIF5 GIF5 16 1 TEIF4 TEIF4 15 1 HTIF4 HTIF4 14 1 TCIF4 TCIF4 13 1 GIF4 GIF4 12 1 TEIF3 TEIF3 11 1 HTIF3 HTIF3 10 1 TCIF3 TCIF3 9 1 GIF3 GIF3 8 1 TEIF2 TEIF2 7 1 HTIF2 HTIF2 6 1 TCIF2 TCIF2 5 1 GIF2 GIF2 4 1 TEIF1 TEIF1 3 1 HTIF1 HTIF1 2 1 TCIF1 TCIF1 1 1 GIF1 GIF1 0 1 CCR1 CCR1 DMA channel 1 configuration register 0x8 0x20 read-write 0x00000000 EN channel enable 0 1 TCIE TCIE 1 1 HTIE HTIE 2 1 TEIE TEIE 3 1 DIR DIR 4 1 CIRC CIRC 5 1 PINC PINC 6 1 MINC MINC 7 1 PSIZE PSIZE 8 2 MSIZE MSIZE 10 2 PL PL 12 2 MEM2MEM MEM2MEM 14 1 CCR2 CCR2 DMA channel 2 configuration register 0x1C 0x20 read-write 0x00000000 EN channel enable 0 1 TCIE TCIE 1 1 HTIE HTIE 2 1 TEIE TEIE 3 1 DIR DIR 4 1 CIRC CIRC 5 1 PINC PINC 6 1 MINC MINC 7 1 PSIZE PSIZE 8 2 MSIZE MSIZE 10 2 PL PL 12 2 MEM2MEM MEM2MEM 14 1 CCR3 CCR3 DMA channel 3 configuration register 0x30 0x20 read-write 0x00000000 EN channel enable 0 1 TCIE TCIE 1 1 HTIE HTIE 2 1 TEIE TEIE 3 1 DIR DIR 4 1 CIRC CIRC 5 1 PINC PINC 6 1 MINC MINC 7 1 PSIZE PSIZE 8 2 MSIZE MSIZE 10 2 PL PL 12 2 MEM2MEM MEM2MEM 14 1 CCR4 CCR4 DMA channel 3 configuration register 0x44 0x20 read-write 0x00000000 EN channel enable 0 1 TCIE TCIE 1 1 HTIE HTIE 2 1 TEIE TEIE 3 1 DIR DIR 4 1 CIRC CIRC 5 1 PINC PINC 6 1 MINC MINC 7 1 PSIZE PSIZE 8 2 MSIZE MSIZE 10 2 PL PL 12 2 MEM2MEM MEM2MEM 14 1 CCR5 CCR5 DMA channel 4 configuration register 0x58 0x20 read-write 0x00000000 EN channel enable 0 1 TCIE TCIE 1 1 HTIE HTIE 2 1 TEIE TEIE 3 1 DIR DIR 4 1 CIRC CIRC 5 1 PINC PINC 6 1 MINC MINC 7 1 PSIZE PSIZE 8 2 MSIZE MSIZE 10 2 PL PL 12 2 MEM2MEM MEM2MEM 14 1 CCR6 CCR6 DMA channel 5 configuration register 0x6C 0x20 read-write 0x00000000 EN channel enable 0 1 TCIE TCIE 1 1 HTIE HTIE 2 1 TEIE TEIE 3 1 DIR DIR 4 1 CIRC CIRC 5 1 PINC PINC 6 1 MINC MINC 7 1 PSIZE PSIZE 8 2 MSIZE MSIZE 10 2 PL PL 12 2 MEM2MEM MEM2MEM 14 1 CCR7 CCR7 DMA channel 6 configuration register 0x80 0x20 read-write 0x00000000 EN channel enable 0 1 TCIE TCIE 1 1 HTIE HTIE 2 1 TEIE TEIE 3 1 DIR DIR 4 1 CIRC CIRC 5 1 PINC PINC 6 1 MINC MINC 7 1 PSIZE PSIZE 8 2 MSIZE MSIZE 10 2 PL PL 12 2 MEM2MEM MEM2MEM 14 1 CCR8 CCR8 DMA channel 7 configuration register 0x94 0x20 read-write 0x00000000 EN channel enable 0 1 TCIE TCIE 1 1 HTIE HTIE 2 1 TEIE TEIE 3 1 DIR DIR 4 1 CIRC CIRC 5 1 PINC PINC 6 1 MINC MINC 7 1 PSIZE PSIZE 8 2 MSIZE MSIZE 10 2 PL PL 12 2 MEM2MEM MEM2MEM 14 1 CNDTR1 CNDTR1 channel x number of data to transfer register 0xC 0x20 read-write 0x00000000 NDT Number of data items to transfer 0 16 CNDTR2 CNDTR2 channel x number of data to transfer register 0x20 0x20 read-write 0x00000000 NDT Number of data items to transfer 0 16 CNDTR3 CNDTR3 channel x number of data to transfer register 0x34 0x20 read-write 0x00000000 NDT Number of data items to transfer 0 16 CNDTR4 CNDTR4 channel x number of data to transfer register 0x48 0x20 read-write 0x00000000 NDT Number of data items to transfer 0 16 CNDTR5 CNDTR5 channel x number of data to transfer register 0x5C 0x20 read-write 0x00000000 NDT Number of data items to transfer 0 16 CNDTR6 CNDTR6 channel x number of data to transfer register 0x70 0x20 read-write 0x00000000 NDT Number of data items to transfer 0 16 CNDTR7 CNDTR7 channel x number of data to transfer register 0x84 0x20 read-write 0x00000000 NDT Number of data items to transfer 0 16 CNDTR8 CNDTR8 channel x number of data to transfer register 0x98 0x20 read-write 0x00000000 NDT Number of data items to transfer 0 16 CPAR1 CPAR1 DMA channel x peripheral address register 0x10 0x20 read-write 0x00000000 PA Peripheral address 0 32 CPAR2 CPAR2 DMA channel x peripheral address register 0x24 0x20 read-write 0x00000000 PA Peripheral address 0 32 CPAR3 CPAR3 DMA channel x peripheral address register 0x38 0x20 read-write 0x00000000 PA Peripheral address 0 32 CPAR4 CPAR4 DMA channel x peripheral address register 0x4C 0x20 read-write 0x00000000 PA Peripheral address 0 32 CPAR5 CPAR5 DMA channel x peripheral address register 0x60 0x20 read-write 0x00000000 PA Peripheral address 0 32 CPAR6 CPAR6 DMA channel x peripheral address register 0x74 0x20 read-write 0x00000000 PA Peripheral address 0 32 CPAR7 CPAR7 DMA channel x peripheral address register 0x88 0x20 read-write 0x00000000 PA Peripheral address 0 32 CPAR8 CPAR8 DMA channel x peripheral address register 0x9C 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR1 CMAR1 DMA channel x memory address register 0x14 0x20 read-write 0x00000000 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR2 CMAR2 DMA channel x memory address register 0x28 0x20 read-write 0x00000000 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR3 CMAR3 DMA channel x memory address register 0x3C 0x20 read-write 0x00000000 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR4 CMAR4 DMA channel x memory address register 0x50 0x20 read-write 0x00000000 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR5 CMAR5 DMA channel x memory address register 0x64 0x20 read-write 0x00000000 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR6 CMAR6 DMA channel x memory address register 0x78 0x20 read-write 0x00000000 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR7 CMAR7 DMA channel x memory address register 0x8C 0x20 read-write 0x00000000 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR8 CMAR8 DMA channel x memory address register 0xA0 0x20 read-write 0x00000000 MA Memory 1 address (used in case of Double buffer mode) 0 32 DMA2 0x40020400 DMA2_CH1 DMA2_CH1 56 DMA2_CH2 DMA2_CH2 57 DMA2_CH3 DMA2_CH3 58 DMA2_CH4 DMA2_CH4 59 DMA2_CH5 DMA2_CH5 60 DMA2_CH6 DMA2_CH6 97 DMAMUX DMAMUX DMAMUX 0x40020800 0x0 0x400 registers DMAMUX_OVR DMAMUX_OVR 94 C0CR C0CR DMAMux - DMA request line multiplexer channel x control register 0x0 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 7 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 C1CR C1CR DMAMux - DMA request line multiplexer channel x control register 0x4 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 7 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 C2CR C2CR DMAMux - DMA request line multiplexer channel x control register 0x8 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 7 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 C3CR C3CR DMAMux - DMA request line multiplexer channel x control register 0xC 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 7 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 C4CR C4CR DMAMux - DMA request line multiplexer channel x control register 0x10 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 7 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 C5CR C5CR DMAMux - DMA request line multiplexer channel x control register 0x14 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 7 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 C6CR C6CR DMAMux - DMA request line multiplexer channel x control register 0x18 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 7 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 C7CR C7CR DMAMux - DMA request line multiplexer channel x control register 0x1C 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 7 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 C8CR C8CR DMAMux - DMA request line multiplexer channel x control register 0x20 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 7 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 C9CR C9CR DMAMux - DMA request line multiplexer channel x control register 0x24 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 7 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 C10CR C10CR DMAMux - DMA request line multiplexer channel x control register 0x28 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 7 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 C11CR C11CR DMAMux - DMA request line multiplexer channel x control register 0x2C 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 7 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 C12CR C12CR DMAMux - DMA request line multiplexer channel x control register 0x30 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 7 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 C13CR C13CR DMAMux - DMA request line multiplexer channel x control register 0x34 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 7 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 C14CR C14CR DMAMux - DMA request line multiplexer channel x control register 0x38 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 7 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 C15CR C15CR DMAMux - DMA request line multiplexer channel x control register 0x3C 0x20 read-write 0x00000000 DMAREQ_ID Input DMA request line selected 0 7 SOIE Interrupt enable at synchronization event overrun 8 1 EGE Event generation enable/disable 9 1 SE Synchronous operating mode enable/disable 16 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SYNC_ID Synchronization input selected 24 5 RG0CR RG0CR DMAMux - DMA request generator channel x control register 0x100 0x20 read-write 0x00000000 SIG_ID DMA request trigger input selected 0 5 OIE Interrupt enable at trigger event overrun 8 1 GE DMA request generator channel enable/disable 16 1 GPOL DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input 17 2 GNBREQ Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. 19 5 RG1CR RG1CR DMAMux - DMA request generator channel x control register 0x104 0x20 read-write 0x00000000 SIG_ID DMA request trigger input selected 0 5 OIE Interrupt enable at trigger event overrun 8 1 GE DMA request generator channel enable/disable 16 1 GPOL DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input 17 2 GNBREQ Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. 19 5 RG2CR RG2CR DMAMux - DMA request generator channel x control register 0x108 0x20 read-write 0x00000000 SIG_ID DMA request trigger input selected 0 5 OIE Interrupt enable at trigger event overrun 8 1 GE DMA request generator channel enable/disable 16 1 GPOL DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input 17 2 GNBREQ Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. 19 5 RG3CR RG3CR DMAMux - DMA request generator channel x control register 0x10C 0x20 read-write 0x00000000 SIG_ID DMA request trigger input selected 0 5 OIE Interrupt enable at trigger event overrun 8 1 GE DMA request generator channel enable/disable 16 1 GPOL DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input 17 2 GNBREQ Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. 19 5 RGSR RGSR DMAMux - DMA request generator status register 0x140 0x20 read-only 0x00000000 OF Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. 0 4 RGCFR RGCFR DMAMux - DMA request generator clear flag register 0x144 0x20 write-only 0x00000000 COF Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register. 0 4 CSR CSR DMAMUX request line multiplexer interrupt channel status register 0x80 0x20 read-only 0x00000000 SOF Synchronization overrun event flag 0 16 CFR CFR DMAMUX request line multiplexer interrupt clear flag register 0x84 0x20 write-only 0x00000000 CSOF Clear synchronization overrun event flag 0 16 SYSCFG System configuration controller SYSCFG 0x40010000 0x0 0x2A registers MEMRMP MEMRMP Remap Memory register 0x0 0x20 read-write 0x00000000 MEM_MODE Memory mapping selection 0 3 FB_mode User Flash Bank mode 8 1 CFGR1 CFGR1 peripheral mode configuration register 0x4 0x20 read-write 0x7C000001 BOOSTEN BOOSTEN 8 1 ANASWVDD GPIO analog switch control voltage selection 9 1 I2C_PB6_FMP FM+ drive capability on PB6 16 1 I2C_PB7_FMP FM+ drive capability on PB6 17 1 I2C_PB8_FMP FM+ drive capability on PB6 18 1 I2C_PB9_FMP FM+ drive capability on PB6 19 1 I2C1_FMP I2C1 FM+ drive capability enable 20 1 I2C2_FMP I2C1 FM+ drive capability enable 21 1 I2C3_FMP I2C1 FM+ drive capability enable 22 1 I2C4_FMP I2C1 FM+ drive capability enable 23 1 FPU_IE FPU Interrupts Enable 26 6 EXTICR1 EXTICR1 external interrupt configuration register 1 0x8 0x20 read-write 0x0000 EXTI3 EXTI x configuration (x = 0 to 3) 12 4 EXTI2 EXTI x configuration (x = 0 to 3) 8 4 EXTI1 EXTI x configuration (x = 0 to 3) 4 4 EXTI0 EXTI x configuration (x = 0 to 3) 0 4 EXTICR2 EXTICR2 external interrupt configuration register 2 0xC 0x20 read-write 0x0000 EXTI7 EXTI x configuration (x = 4 to 7) 12 4 EXTI6 EXTI x configuration (x = 4 to 7) 8 4 EXTI5 EXTI x configuration (x = 4 to 7) 4 4 EXTI4 EXTI x configuration (x = 4 to 7) 0 4 EXTICR3 EXTICR3 external interrupt configuration register 3 0x10 0x20 read-write 0x0000 EXTI11 EXTI x configuration (x = 8 to 11) 12 4 EXTI10 EXTI10 8 4 EXTI9 EXTI x configuration (x = 8 to 11) 4 4 EXTI8 EXTI x configuration (x = 8 to 11) 0 4 EXTICR4 EXTICR4 external interrupt configuration register 4 0x14 0x20 read-write 0x0000 EXTI15 EXTI x configuration (x = 12 to 15) 12 4 EXTI14 EXTI x configuration (x = 12 to 15) 8 4 EXTI13 EXTI x configuration (x = 12 to 15) 4 4 EXTI12 EXTI x configuration (x = 12 to 15) 0 4 SCSR SCSR CCM SRAM control and status register 0x18 0x20 0x00000000 CCMER CCM SRAM Erase 0 1 read-write CCMBSY CCM SRAM busy by erase operation 1 1 read-only CFGR2 CFGR2 configuration register 2 0x1C 0x20 read-write 0x00000000 CLL Core Lockup Lock 0 1 SPL SRAM Parity Lock 1 1 PVDL PVD Lock 2 1 ECCL ECC Lock 3 1 SPF SRAM Parity Flag 8 1 SWPR SWPR SRAM Write protection register 1 0x20 0x20 read-write 0x00000000 Page0_WP Write protection 0 1 Page1_WP Write protection 1 1 Page2_WP Write protection 2 1 Page3_WP Write protection 3 1 Page4_WP Write protection 4 1 Page5_WP Write protection 5 1 Page6_WP Write protection 6 1 Page7_WP Write protection 7 1 Page8_WP Write protection 8 1 Page9_WP Write protection 9 1 Page10_WP Write protection 10 1 Page11_WP Write protection 11 1 Page12_WP Write protection 12 1 Page13_WP Write protection 13 1 Page14_WP Write protection 14 1 Page15_WP Write protection 15 1 Page16_WP Write protection 16 1 Page17_WP Write protection 17 1 Page18_WP Write protection 18 1 Page19_WP Write protection 19 1 Page20_WP Write protection 20 1 Page21_WP Write protection 21 1 Page22_WP Write protection 22 1 Page23_WP Write protection 23 1 Page24_WP Write protection 24 1 Page25_WP Write protection 25 1 Page26_WP Write protection 26 1 Page27_WP Write protection 27 1 Page28_WP Write protection 28 1 Page29_WP Write protection 29 1 Page30_WP Write protection 30 1 Page31_WP Write protection 31 1 SKR SKR SRAM2 Key Register 0x24 0x20 write-only 0x00000000 KEY SRAM2 Key for software erase 0 8 VREFBUF Voltage reference buffer VREFBUF 0x40010030 0x0 0x1D0 registers VREFBUF_CSR VREFBUF_CSR VREF_BUF Control and Status Register 0x0 0x20 0x00000002 ENVR Enable Voltage Reference 0 1 read-write HIZ High impedence mode for the VREF_BUF 1 1 read-write VRR Voltage reference buffer ready 3 1 read-only VRS Voltage reference scale 4 2 read-write VREFBUF_CCR VREFBUF_CCR VREF_BUF Calibration Control Register 0x04 0x20 read-write 0x00000000 TRIM Trimming code 0 6 COMP Comparator control and status register COMP 0x40010200 0x0 0x100 registers COMP1_2_3 COMP1_2_3 64 COMP4_5_6 COMP4_5_6 65 COMP7 COMP7 66 COMP_C1CSR COMP_C1CSR Comparator control/status register 0x0 0x20 0x00000000 EN EN 0 1 read-write INMSEL INMSEL 4 3 read-write INPSEL INPSEL 8 1 read-write POL POL 15 1 read-write HYST HYST 16 3 read-write BLANKSEL BLANKSEL 19 3 read-write BRGEN BRGEN 22 1 read-write SCALEN SCALEN 23 1 read-write VALUE VALUE 30 1 read-only LOCK LOCK 31 1 read-write COMP_C2CSR COMP_C2CSR Comparator control/status register 0x4 0x20 0x00000000 EN EN 0 1 read-write INMSEL INMSEL 4 3 read-write INPSEL INPSEL 8 1 read-write POL POL 15 1 read-write HYST HYST 16 3 read-write BLANKSEL BLANKSEL 19 3 read-write BRGEN BRGEN 22 1 read-write SCALEN SCALEN 23 1 read-write VALUE VALUE 30 1 read-only LOCK LOCK 31 1 read-write COMP_C3CSR COMP_C3CSR Comparator control/status register 0x8 0x20 0x00000000 EN EN 0 1 read-write INMSEL INMSEL 4 3 read-write INPSEL INPSEL 8 1 read-write POL POL 15 1 read-write HYST HYST 16 3 read-write BLANKSEL BLANKSEL 19 3 read-write BRGEN BRGEN 22 1 read-write SCALEN SCALEN 23 1 read-write VALUE VALUE 30 1 read-only LOCK LOCK 31 1 read-write COMP_C4CSR COMP_C4CSR Comparator control/status register 0x0C 0x20 0x00000000 EN EN 0 1 read-write INMSEL INMSEL 4 3 read-write INPSEL INPSEL 8 1 read-write POL POL 15 1 read-write HYST HYST 16 3 read-write BLANKSEL BLANKSEL 19 3 read-write BRGEN BRGEN 22 1 read-write SCALEN SCALEN 23 1 read-write VALUE VALUE 30 1 read-only LOCK LOCK 31 1 read-write OPAMP Operational amplifiers OPAMP 0x40010300 0x0 0x100 registers OPAMP1_CSR OPAMP1_CSR OPAMP1 control/status register 0x0 0x20 read-write 0x00000000 OPAEN Operational amplifier Enable 0 1 FORCE_VP FORCE_VP 1 1 VP_SEL VP_SEL 2 2 USERTRIM USERTRIM 4 1 VM_SEL VM_SEL 5 2 OPAHSM OPAHSM 7 1 OPAINTOEN OPAINTOEN 8 1 CALON CALON 11 1 CALSEL CALSEL 12 2 PGA_GAIN PGA_GAIN 14 5 TRIMOFFSETP TRIMOFFSETP 19 5 TRIMOFFSETN TRIMOFFSETN 24 5 CALOUT CALOUT 30 1 LOCK LOCK 31 1 OPAMP2_CSR OPAMP2_CSR OPAMP2 control/status register 0x4 0x20 read-write 0x00000000 OPAEN Operational amplifier Enable 0 1 FORCE_VP FORCE_VP 1 1 VP_SEL VP_SEL 2 2 USERTRIM USERTRIM 4 1 VM_SEL VM_SEL 5 2 OPAHSM OPAHSM 7 1 OPAINTOEN OPAINTOEN 8 1 CALON CALON 11 1 CALSEL CALSEL 12 2 PGA_GAIN PGA_GAIN 14 5 TRIMOFFSETP TRIMOFFSETP 19 5 TRIMOFFSETN TRIMOFFSETN 24 5 CALOUT CALOUT 30 1 LOCK LOCK 31 1 OPAMP3_CSR OPAMP3_CSR OPAMP3 control/status register 0x8 0x20 read-write 0x00000000 OPAEN Operational amplifier Enable 0 1 FORCE_VP FORCE_VP 1 1 VP_SEL VP_SEL 2 2 USERTRIM USERTRIM 4 1 VM_SEL VM_SEL 5 2 OPAHSM OPAHSM 7 1 OPAINTOEN OPAINTOEN 8 1 CALON CALON 11 1 CALSEL CALSEL 12 2 PGA_GAIN PGA_GAIN 14 5 TRIMOFFSETP TRIMOFFSETP 19 5 TRIMOFFSETN TRIMOFFSETN 24 5 CALOUT CALOUT 30 1 LOCK LOCK 31 1 OPAMP1_TCMR OPAMP1_TCMR OPAMP1 control/status register 0x18 0x20 read-write 0x00000000 VMS_SEL VMS_SEL 0 1 VPS_SEL VPS_SEL 1 2 T1CM_EN T1CM_EN 3 1 T8CM_EN T8CM_EN 4 1 T20CM_EN T20CM_EN 5 1 LOCK LOCK 31 1 OPAMP2_TCMR OPAMP2_TCMR OPAMP2 control/status register 0x1C 0x20 read-write 0x00000000 VMS_SEL VMS_SEL 0 1 VPS_SEL VPS_SEL 1 2 T1CM_EN T1CM_EN 3 1 T8CM_EN T8CM_EN 4 1 T20CM_EN T20CM_EN 5 1 LOCK LOCK 31 1 OPAMP3_TCMR OPAMP3_TCMR OPAMP3 control/status register 0x20 0x20 read-write 0x00000000 VMS_SEL VMS_SEL 0 1 VPS_SEL VPS_SEL 1 2 T1CM_EN T1CM_EN 3 1 T8CM_EN T8CM_EN 4 1 T20CM_EN T20CM_EN 5 1 LOCK LOCK 31 1 DAC1 Digital-to-analog converter DAC 0x50000800 0x0 0x400 registers DAC_CR DAC_CR DAC control register 0x0 0x20 read-write 0x00000000 EN1 DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1. 0 1 TEN1 DAC channel1 trigger enable 1 1 TSEL1 DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). 2 4 WAVE1 DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). 6 2 MAMP1 DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 8 4 DMAEN1 DAC channel1 DMA enable This bit is set and cleared by software. 12 1 DMAUDRIE1 DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software. 13 1 CEN1 DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 14 1 EN2 DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. 16 1 TEN2 DAC channel2 trigger enable 17 1 TSEL2 DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). 18 4 WAVE2 DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) 22 2 MAMP2 DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 24 4 DMAEN2 DAC channel2 DMA enable This bit is set and cleared by software. 28 1 DMAUDRIE2 DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. 29 1 CEN2 DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 30 1 DAC_SWTRGR DAC_SWTRGR DAC software trigger register 0x4 0x20 write-only 0x00000000 SWTRIG1 DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register. 0 1 SWTRIG2 DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. 1 1 SWTRIGB1 DAC channel1 software trigger B 16 1 SWTRIGB2 DAC channel2 software trigger B 17 1 DAC_DHR12R1 DAC_DHR12R1 DAC channel1 12-bit right-aligned data holding register 0x8 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 0 12 DACC1DHRB DAC channel1 12-bit right-aligned data B 16 12 DAC_DHR12L1 DAC_DHR12L1 DAC channel1 12-bit left aligned data holding register 0xC 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 4 12 DACC1DHRB DAC channel1 12-bit left-aligned data B 20 12 DAC_DHR8R1 DAC_DHR8R1 DAC channel1 8-bit right aligned data holding register 0x10 0x20 read-write 0x00000000 DACC1DHR DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 0 8 DACC1DHRB DAC channel1 8-bit right-aligned data 8 8 DAC_DHR12R2 DAC_DHR12R2 DAC channel2 12-bit right aligned data holding register 0x14 0x20 read-write 0x00000000 DACC2DHR DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 0 12 DACC2DHRB DAC channel2 12-bit right-aligned data 16 12 DAC_DHR12L2 DAC_DHR12L2 DAC channel2 12-bit left aligned data holding register 0x18 0x20 read-write 0x00000000 DACC2DHR DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2. 4 12 DACC2DHRB DAC channel2 12-bit left-aligned data B 20 12 DAC_DHR8R2 DAC_DHR8R2 DAC channel2 8-bit right-aligned data holding register 0x1C 0x20 read-write 0x00000000 DACC2DHR DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. 0 8 DACC2DHRB DAC channel2 8-bit right-aligned data 8 8 DAC_DHR12RD DAC_DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 0 12 DACC2DHR DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 16 12 DAC_DHR12LD DAC_DHR12LD DUAL DAC 12-bit left aligned data holding register 0x24 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 4 12 DACC2DHR DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 20 12 DAC_DHR8RD DAC_DHR8RD DUAL DAC 8-bit right aligned data holding register 0x28 0x20 read-write 0x00000000 DACC1DHR DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 0 8 DACC2DHR DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. 8 8 DAC_DOR1 DAC_DOR1 DAC channel1 data output register 0x2C 0x20 read-only 0x00000000 DACC1DOR DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. 0 12 DACC1DORB DAC channel1 data output 16 12 DAC_DOR2 DAC_DOR2 DAC channel2 data output register 0x30 0x20 read-only 0x00000000 DACC2DOR DAC channel2 data output These bits are read-only, they contain data output for DAC channel2. 0 12 DACC2DORB DAC channel2 data output 16 12 DAC_SR DAC_SR DAC status register 0x34 0x20 0x00000000 DAC1RDY DAC channel1 ready status bit 11 1 read-write DORSTAT1 DAC channel1 output register status bit 12 1 read-write DMAUDR1 DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 13 1 read-write CAL_FLAG1 DAC Channel 1 calibration offset status This bit is set and cleared by hardware 14 1 read-only BWST1 DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization). 15 1 read-only DAC2RDY DAC channel 2 ready status bit 27 1 read-write DORSTAT2 DAC channel 2 output register status bit 28 1 read-write DMAUDR2 DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 29 1 read-write CAL_FLAG2 DAC Channel 2 calibration offset status This bit is set and cleared by hardware 30 1 read-only BWST2 DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). 31 1 read-only DAC_CCR DAC_CCR DAC calibration control register 0x38 0x20 read-write 0x00000000 OTRIM1 DAC Channel 1 offset trimming value 0 5 OTRIM2 DAC Channel 2 offset trimming value 16 5 DAC_MCR DAC_MCR DAC mode control register 0x3C 0x20 read-write 0x00000000 MODE1 DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample &amp; hold mode 0 3 DMADOUBLE1 DAC Channel1 DMA double data mode 8 1 SINFORMAT1 Enable signed format for DAC channel1 9 1 HFSEL High frequency interface mode selection 14 2 MODE2 DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample &amp; hold mode 16 3 DMADOUBLE2 DAC Channel2 DMA double data mode 24 1 SINFORMAT2 Enable signed format for DAC channel2 25 1 DAC_SHSR1 DAC_SHSR1 DAC Sample and Hold sample time register 1 0x40 0x20 read-write 0x00000000 TSAMPLE1 DAC Channel 1 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored. 0 10 DAC_SHSR2 DAC_SHSR2 DAC Sample and Hold sample time register 2 0x44 0x20 read-write 0x00000000 TSAMPLE2 DAC Channel 2 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored. 0 10 DAC_SHHR DAC_SHHR DAC Sample and Hold hold time register 0x48 0x20 read-write 0x00010001 THOLD1 DAC Channel 1 hold Time (only valid in sample &amp; hold mode) Hold time= (THOLD[9:0]) x T LSI 0 10 THOLD2 DAC Channel 2 hold time (only valid in sample &amp; hold mode). Hold time= (THOLD[9:0]) x T LSI 16 10 DAC_SHRR DAC_SHRR DAC Sample and Hold refresh time register 0x4C 0x20 read-write 0x00010001 TREFRESH1 DAC Channel 1 refresh Time (only valid in sample &amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI 0 8 TREFRESH2 DAC Channel 2 refresh Time (only valid in sample &amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI 16 8 DAC_STR1 DAC_STR1 Sawtooth register 0x58 0x20 read-write 0x00000000 STRSTDATA1 DAC Channel 1 Sawtooth reset value 0 12 STDIR1 DAC Channel1 Sawtooth direction setting 12 1 STINCDATA1 DAC CH1 Sawtooth increment value (12.4 bit format) 16 16 DAC_STR2 DAC_STR2 Sawtooth register 0x5C 0x20 read-write 0x00000000 STRSTDATA2 DAC Channel 2 Sawtooth reset value 0 12 STDIR2 DAC Channel2 Sawtooth direction setting 12 1 STINCDATA2 DAC CH2 Sawtooth increment value (12.4 bit format) 16 16 DAC_STMODR DAC_STMODR Sawtooth Mode register 0x60 0x20 read-write 0x00000000 STRSTTRIGSEL1 DAC Channel 1 Sawtooth Reset trigger selection 0 4 STINCTRIGSEL1 DAC Channel 1 Sawtooth Increment trigger selection 8 4 STRSTTRIGSEL2 DAC Channel 1 Sawtooth Reset trigger selection 16 4 STINCTRIGSEL2 DAC Channel 2 Sawtooth Increment trigger selection 24 4 DAC2 0x50000C00 DAC3 0x50001000 DAC4 0x50001400 ADC1 Analog-to-Digital Converter ADC 0x50000000 0x0 0xD0 registers ADC1_2 ADC1 and ADC2 global interrupt 18 ISR ISR interrupt and status register 0x0 0x20 read-write 0x00000000 JQOVF JQOVF 10 1 AWD3 AWD3 9 1 AWD2 AWD2 8 1 AWD1 AWD1 7 1 JEOS JEOS 6 1 JEOC JEOC 5 1 OVR OVR 4 1 EOS EOS 3 1 EOC EOC 2 1 EOSMP EOSMP 1 1 ADRDY ADRDY 0 1 IER IER interrupt enable register 0x4 0x20 read-write 0x00000000 JQOVFIE JQOVFIE 10 1 AWD3IE AWD3IE 9 1 AWD2IE AWD2IE 8 1 AWD1IE AWD1IE 7 1 JEOSIE JEOSIE 6 1 JEOCIE JEOCIE 5 1 OVRIE OVRIE 4 1 EOSIE EOSIE 3 1 EOCIE EOCIE 2 1 EOSMPIE EOSMPIE 1 1 ADRDYIE ADRDYIE 0 1 CR CR control register 0x8 0x20 read-write 0x20000000 ADCAL ADCAL 31 1 ADCALDIF ADCALDIF 30 1 DEEPPWD DEEPPWD 29 1 ADVREGEN ADVREGEN 28 1 JADSTP JADSTP 5 1 ADSTP ADSTP 4 1 JADSTART JADSTART 3 1 ADSTART ADSTART 2 1 ADDIS ADDIS 1 1 ADEN ADEN 0 1 CFGR CFGR configuration register 0xC 0x20 read-write 0x80000000 JQDIS Injected Queue disable 31 1 AWD1CH Analog watchdog 1 channel selection 26 5 JAUTO JAUTO 25 1 JAWD1EN JAWD1EN 24 1 AWD1EN AWD1EN 23 1 AWD1SGL AWD1SGL 22 1 JQM JQM 21 1 JDISCEN JDISCEN 20 1 DISCNUM DISCNUM 17 3 DISCEN DISCEN 16 1 ALIGN ALIGN 15 1 AUTDLY AUTDLY 14 1 CONT CONT 13 1 OVRMOD OVRMOD 12 1 EXTEN EXTEN 10 2 EXTSEL External trigger selection for regular group 5 5 RES RES 3 2 DMACFG DMACFG 1 1 DMAEN DMAEN 0 1 CFGR2 CFGR2 configuration register 0x10 0x20 read-write 0x00000000 SMPTRIG SMPTRIG 27 1 BULB BULB 26 1 SWTRIG SWTRIG 25 1 GCOMP GCOMP 16 1 ROVSM EXTEN 10 1 TROVS Triggered Regular Oversampling 9 1 OVSS ALIGN 5 4 OVSR RES 2 3 JOVSE DMACFG 1 1 ROVSE DMAEN 0 1 SMPR1 SMPR1 sample time register 1 0x14 0x20 read-write 0x00000000 SMP9 SMP9 27 3 SMP8 SMP8 24 3 SMP7 SMP7 21 3 SMP6 SMP6 18 3 SMP5 SMP5 15 3 SMP4 SMP4 12 3 SMP3 SMP3 9 3 SMP2 SMP2 6 3 SMP1 SMP1 3 3 SMPPLUS Addition of one clock cycle to the sampling time 31 1 SMP0 SMP0 0 3 SMPR2 SMPR2 sample time register 2 0x18 0x20 read-write 0x00000000 SMP18 SMP18 24 3 SMP17 SMP17 21 3 SMP16 SMP16 18 3 SMP15 SMP15 15 3 SMP14 SMP14 12 3 SMP13 SMP13 9 3 SMP12 SMP12 6 3 SMP11 SMP11 3 3 SMP10 SMP10 0 3 TR1 TR1 watchdog threshold register 1 0x20 0x20 read-write 0x0FFF0000 HT1 HT1 16 12 AWDFILT AWDFILT 12 3 LT1 LT1 0 12 TR2 TR2 watchdog threshold register 0x24 0x20 read-write 0x00FF0000 HT2 HT2 16 8 LT2 LT2 0 8 TR3 TR3 watchdog threshold register 3 0x28 0x20 read-write 0x00FF0000 HT3 HT3 16 8 LT3 LT3 0 8 SQR1 SQR1 regular sequence register 1 0x30 0x20 read-write 0x00000000 SQ4 SQ4 24 5 SQ3 SQ3 18 5 SQ2 SQ2 12 5 SQ1 SQ1 6 5 L Regular channel sequence length 0 4 SQR2 SQR2 regular sequence register 2 0x34 0x20 read-write 0x00000000 SQ9 SQ9 24 5 SQ8 SQ8 18 5 SQ7 SQ7 12 5 SQ6 SQ6 6 5 SQ5 SQ5 0 5 SQR3 SQR3 regular sequence register 3 0x38 0x20 read-write 0x00000000 SQ14 SQ14 24 5 SQ13 SQ13 18 5 SQ12 SQ12 12 5 SQ11 SQ11 6 5 SQ10 SQ10 0 5 SQR4 SQR4 regular sequence register 4 0x3C 0x20 read-write 0x00000000 SQ16 SQ16 6 5 SQ15 SQ15 0 5 DR DR regular Data Register 0x40 0x20 read-only 0x00000000 RDATA Regular Data converted 0 16 JSQR JSQR injected sequence register 0x4C 0x20 read-write 0x00000000 JSQ4 JSQ4 27 5 JSQ3 JSQ3 21 5 JSQ2 JSQ2 15 5 JSQ1 JSQ1 9 5 JEXTEN JEXTEN 7 2 JEXTSEL JEXTSEL 2 5 JL JL 0 2 OFR1 OFR1 offset register 1 0x60 0x20 read-write 0x00000000 OFFSET1_EN OFFSET1_EN 31 1 OFFSET1_CH OFFSET1_CH 26 5 SATEN SATEN 25 1 OFFSETPOS OFFSETPOS 24 1 OFFSET1 OFFSET1 0 12 OFR2 OFR2 offset register 2 0x64 0x20 read-write 0x00000000 OFFSET1_EN OFFSET1_EN 31 1 OFFSET1_CH OFFSET1_CH 26 5 SATEN SATEN 25 1 OFFSETPOS OFFSETPOS 24 1 OFFSET1 OFFSET1 0 12 OFR3 OFR3 offset register 3 0x68 0x20 read-write 0x00000000 OFFSET1_EN OFFSET1_EN 31 1 OFFSET1_CH OFFSET1_CH 26 5 SATEN SATEN 25 1 OFFSETPOS OFFSETPOS 24 1 OFFSET1 OFFSET1 0 12 OFR4 OFR4 offset register 4 0x6C 0x20 read-write 0x00000000 OFFSET1_EN OFFSET1_EN 31 1 OFFSET1_CH OFFSET1_CH 26 5 SATEN SATEN 25 1 OFFSETPOS OFFSETPOS 24 1 OFFSET1 OFFSET1 0 12 JDR1 JDR1 injected data register 1 0x80 0x20 read-only 0x00000000 JDATA1 JDATA1 0 16 JDR2 JDR2 injected data register 2 0x84 0x20 read-only 0x00000000 JDATA2 JDATA2 0 16 JDR3 JDR3 injected data register 3 0x88 0x20 read-only 0x00000000 JDATA3 JDATA3 0 16 JDR4 JDR4 injected data register 4 0x8C 0x20 read-only 0x00000000 JDATA4 JDATA4 0 16 AWD2CR AWD2CR Analog Watchdog 2 Configuration Register 0xA0 0x20 read-write 0x00000000 AWD2CH AWD2CH 0 19 AWD3CR AWD3CR Analog Watchdog 3 Configuration Register 0xA4 0x20 read-write 0x00000000 AWD3CH AWD3CH 0 19 DIFSEL DIFSEL Differential Mode Selection Register 2 0xB0 0x20 0x00000000 DIFSEL_0 Differential mode for channels 0 0 1 read-only DIFSEL_1_18 Differential mode for channels 15 to 1 1 18 read-write CALFACT CALFACT Calibration Factors 0xB4 0x20 read-write 0x00000000 CALFACT_D CALFACT_D 16 7 CALFACT_S CALFACT_S 0 7 GCOMP GCOMP Gain compensation Register 0xC0 0x20 read-write 0x00000000 GCOMPCOEFF GCOMPCOEFF 0 14 ADC2 0x50000100 ADC12_Common Analog-to-Digital Converter ADC 0x50000300 0x0 0x11 registers CSR CSR ADC Common status register 0x0 0x20 read-only 0x00000000 ADDRDY_MST ADDRDY_MST 0 1 EOSMP_MST EOSMP_MST 1 1 EOC_MST EOC_MST 2 1 EOS_MST EOS_MST 3 1 OVR_MST OVR_MST 4 1 JEOC_MST JEOC_MST 5 1 JEOS_MST JEOS_MST 6 1 AWD1_MST AWD1_MST 7 1 AWD2_MST AWD2_MST 8 1 AWD3_MST AWD3_MST 9 1 JQOVF_MST JQOVF_MST 10 1 ADRDY_SLV ADRDY_SLV 16 1 EOSMP_SLV EOSMP_SLV 17 1 EOC_SLV End of regular conversion of the slave ADC 18 1 EOS_SLV End of regular sequence flag of the slave ADC 19 1 OVR_SLV Overrun flag of the slave ADC 20 1 JEOC_SLV End of injected conversion flag of the slave ADC 21 1 JEOS_SLV End of injected sequence flag of the slave ADC 22 1 AWD1_SLV Analog watchdog 1 flag of the slave ADC 23 1 AWD2_SLV Analog watchdog 2 flag of the slave ADC 24 1 AWD3_SLV Analog watchdog 3 flag of the slave ADC 25 1 JQOVF_SLV Injected Context Queue Overflow flag of the slave ADC 26 1 CCR CCR ADC common control register 0x8 0x20 read-write 0x00000000 DUAL Dual ADC mode selection 0 5 DELAY Delay between 2 sampling phases 8 4 DMACFG DMA configuration (for multi-ADC mode) 13 1 MDMA Direct memory access mode for multi ADC mode 14 2 CKMODE ADC clock mode 16 2 VREFEN VREFINT enable 22 1 VSENSESEL VTS selection 23 1 VBATSEL VBAT selection 24 1 PRESC ADC prescaler 18 4 CDR CDR ADC common regular data register for dual and triple modes 0xC 0x20 read-only 0x00000000 RDATA_SLV Regular data of the slave ADC 16 16 RDATA_MST Regular data of the master ADC 0 16 ADC345_Common 0x50000700 FMAC Filter Math Accelerator FMAC 0x40021400 0x0 0xC00 registers FMAC FMAC 101 X1BUFCFG X1BUFCFG FMAC X1 Buffer Configuration register 0x0 0x20 read-write 0x00000000 X1_BASE X1_BASE 0 8 X1_BUF_SIZE X1_BUF_SIZE 8 8 FULL_WM FULL_WM 24 2 X2BUFCFG X2BUFCFG FMAC X2 Buffer Configuration register 0x4 0x20 read-write 0x00000000 X2_BASE X1_BASE 0 8 X2_BUF_SIZE X1_BUF_SIZE 8 8 YBUFCFG YBUFCFG FMAC Y Buffer Configuration register 0x8 0x20 read-write 0x00000000 Y_BASE X1_BASE 0 8 Y_BUF_SIZE X1_BUF_SIZE 8 8 EMPTY_WM EMPTY_WM 24 2 PARAM PARAM FMAC Parameter register 0xC 0x20 read-write 0x00000000 START START 31 1 FUNC FUNC 24 7 R R 16 8 Q Q 8 8 P P 0 8 CR CR FMAC Control register 0x10 0x20 read-write 0x00000000 RESET RESET 16 1 CLIPEN CLIPEN 15 1 DMAWEN DMAWEN 9 1 DMAREN DMAREN 8 1 SATIEN SATIEN 4 1 UNFLIEN UNFLIEN 3 1 OVFLIEN OVFLIEN 2 1 WIEN WIEN 1 1 RIEN RIEN 0 1 SR SR FMAC Status register 0x14 0x20 read-only 0x00000000 YEMPTY YEMPTY 0 1 X1FULL X1FULL 1 1 OVFL OVFL 8 1 UNFL UNFL 9 1 SAT SAT 10 1 WDATA WDATA FMAC Write Data register 0x18 0x20 write-only 0x00000000 WDATA WDATA 0 16 RDATA RDATA FMAC Read Data register 0x1C 0x20 read-only 0x00000000 RDATA RDATA 0 16 CORDIC CORDIC Co-processor CORDIC 0x40020C00 0x0 0x400 registers Cordic Cordic 100 CSR CSR CORDIC Control Status register 0x0 0x20 read-write 0x00000000 FUNC FUNC 0 4 PRECISION PRECISION 4 4 SCALE SCALE 8 3 IEN IEN 16 1 DMAREN DMAREN 17 1 DMAWEN DMAWEN 18 1 NRES NRES 19 1 NARGS NARGS 20 1 RESSIZE RESSIZE 21 1 ARGSIZE ARGSIZE 22 1 RRDY RRDY 31 1 WDATA WDATA FMAC Write Data register 0x4 0x20 read-write 0x00000000 ARG ARG 0 32 RDATA RDATA FMAC Read Data register 0x8 0x20 read-only 0x00000000 RES RES 0 32 SAI Serial audio interface SAI 0x40015400 0x0 0x400 registers SAI SAI 76 BCR1 BCR1 BConfiguration register 1 0x24 0x20 read-write 0x00000040 MCKEN MCKEN 27 1 OSR OSR 26 1 MCJDIV Master clock divider 20 6 NODIV No divider 19 1 DMAEN DMA enable 17 1 SAIBEN Audio block B enable 16 1 OutDri Output drive 13 1 MONO Mono mode 12 1 SYNCEN Synchronization enable 10 2 CKSTR Clock strobing edge 9 1 LSBFIRST Least significant bit first 8 1 DS Data size 5 3 PRTCFG Protocol configuration 2 2 MODE Audio block mode 0 2 BCR2 BCR2 BConfiguration register 2 0x28 0x20 read-write 0x00000000 COMP Companding mode 14 2 CPL Complement bit 13 1 MUTECN Mute counter 7 6 MUTEVAL Mute value 6 1 MUTE Mute 5 1 TRIS Tristate management on data line 4 1 FFLUS FIFO flush 3 1 FTH FIFO threshold 0 3 BFRCR BFRCR BFRCR 0x2C 0x20 read-write 0x00000007 FSOFF Frame synchronization offset 18 1 FSPOL Frame synchronization polarity 17 1 FSDEF Frame synchronization definition 16 1 FSALL Frame synchronization active level length 8 7 FRL Frame length 0 8 BSLOTR BSLOTR BSlot register 0x30 0x20 read-write 0x00000000 SLOTEN Slot enable 16 16 NBSLOT Number of slots in an audio frame 8 4 SLOTSZ Slot size 6 2 FBOFF First bit offset 0 5 BIM BIM BInterrupt mask register2 0x34 0x20 read-write 0x00000000 LFSDETIE Late frame synchronization detection interrupt enable 6 1 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 CNRDYIE Codec not ready interrupt enable 4 1 FREQIE FIFO request interrupt enable 3 1 WCKCFG Wrong clock configuration interrupt enable 2 1 MUTEDET Mute detection interrupt enable 1 1 OVRUDRIE Overrun/underrun interrupt enable 0 1 BSR BSR BStatus register 0x38 0x20 read-only 0x00000000 FLVL FIFO level threshold 16 3 LFSDET Late frame synchronization detection 6 1 AFSDET Anticipated frame synchronization detection 5 1 CNRDY Codec not ready 4 1 FREQ FIFO request 3 1 WCKCFG Wrong clock configuration flag 2 1 MUTEDET Mute detection 1 1 OVRUDR Overrun / underrun 0 1 BCLRFR BCLRFR BClear flag register 0x3C 0x20 write-only 0x00000000 LFSDET Clear late frame synchronization detection flag 6 1 CAFSDET Clear anticipated frame synchronization detection flag 5 1 CNRDY Clear codec not ready flag 4 1 WCKCFG Clear wrong clock configuration flag 2 1 MUTEDET Mute detection flag 1 1 OVRUDR Clear overrun / underrun 0 1 BDR BDR BData register 0x40 0x20 read-write 0x00000000 DATA Data 0 32 ACR1 ACR1 AConfiguration register 1 0x4 0x20 read-write 0x00000040 MCKEN MCKEN 27 1 OSR OSR 26 1 MCJDIV Master clock divider 20 6 NODIV No divider 19 1 DMAEN DMA enable 17 1 SAIAEN Audio block A enable 16 1 OutDri Output drive 13 1 MONO Mono mode 12 1 SYNCEN Synchronization enable 10 2 CKSTR Clock strobing edge 9 1 LSBFIRST Least significant bit first 8 1 DS Data size 5 3 PRTCFG Protocol configuration 2 2 MODE Audio block mode 0 2 ACR2 ACR2 AConfiguration register 2 0x8 0x20 read-write 0x00000000 COMP Companding mode 14 2 CPL Complement bit 13 1 MUTECN Mute counter 7 6 MUTEVAL Mute value 6 1 MUTE Mute 5 1 TRIS Tristate management on data line 4 1 FFLUS FIFO flush 3 1 FTH FIFO threshold 0 3 AFRCR AFRCR AFRCR 0xC 0x20 read-write 0x00000007 FSOFF Frame synchronization offset 18 1 FSPOL Frame synchronization polarity 17 1 FSDEF Frame synchronization definition 16 1 FSALL Frame synchronization active level length 8 7 FRL Frame length 0 8 ASLOTR ASLOTR ASlot register 0x10 0x20 read-write 0x00000000 SLOTEN Slot enable 16 16 NBSLOT Number of slots in an audio frame 8 4 SLOTSZ Slot size 6 2 FBOFF First bit offset 0 5 AIM AIM AInterrupt mask register2 0x14 0x20 read-write 0x00000000 LFSDET Late frame synchronization detection interrupt enable 6 1 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 CNRDYIE Codec not ready interrupt enable 4 1 FREQIE FIFO request interrupt enable 3 1 WCKCFG Wrong clock configuration interrupt enable 2 1 MUTEDET Mute detection interrupt enable 1 1 OVRUDRIE Overrun/underrun interrupt enable 0 1 ASR ASR AStatus register 0x18 0x20 read-write 0x00000000 FLVL FIFO level threshold 16 3 LFSDET Late frame synchronization detection 6 1 AFSDET Anticipated frame synchronization detection 5 1 CNRDY Codec not ready 4 1 FREQ FIFO request 3 1 WCKCFG Wrong clock configuration flag. This bit is read only 2 1 MUTEDET Mute detection 1 1 OVRUDR Overrun / underrun 0 1 ACLRFR ACLRFR AClear flag register 0x1C 0x20 read-write 0x00000000 LFSDET Clear late frame synchronization detection flag 6 1 CAFSDET Clear anticipated frame synchronization detection flag 5 1 CNRDY Clear codec not ready flag 4 1 WCKCFG Clear wrong clock configuration flag 2 1 MUTEDET Mute detection flag 1 1 OVRUDR Clear overrun / underrun 0 1 ADR ADR AData register 0x20 0x20 read-write 0x00000000 DATA Data 0 32 PDMCR PDMCR PDM control register 0x44 0x20 read-write 0x00000000 PDMEN PDMEN 0 1 MICNBR MICNBR 4 2 CKEN1 CKEN1 8 1 CKEN2 CKEN2 9 1 CKEN3 CKEN3 10 1 CKEN4 CKEN4 11 1 PDMDLY PDMDLY PDM delay register 0x48 0x20 read-write 0x00000000 DLYM1L DLYM1L 0 3 DLYM1R DLYM1R 4 3 DLYM2L DLYM2L 8 3 DLYM2R DLYM2R 12 3 DLYM3L DLYM3L 16 3 DLYM3R DLYM3R 20 3 DLYM4L DLYM4L 24 3 DLYM4R DLYM4R 28 3 TAMP Tamper and backup registers TAMP 0x40002400 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0xFFFF0000 TAMP1E TAMP1E 0 1 TAMP2E TAMP2E 1 1 TAMP3E TAMP2E 2 1 ITAMP3E ITAMP3E 18 1 ITAMP4E ITAMP4E 19 1 ITAMP5E ITAMP5E 20 1 ITAMP6E ITAMP6E 21 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 TAMP1NOER TAMP1NOER 0 1 TAMP2NOER TAMP2NOER 1 1 TAMP3NOER TAMP3NOER 2 1 TAMP1MSK TAMP1MSK 16 1 TAMP2MSK TAMP2MSK 17 1 TAMP3MSK TAMP3MSK 18 1 TAMP1TRG TAMP1TRG 24 1 TAMP2TRG TAMP2TRG 25 1 TAMP3TRG TAMP3TRG 26 1 FLTCR FLTCR TAMP filter control register 0xC 0x20 read-write 0x00000000 TAMPFREQ TAMPFREQ 0 3 TAMPFLT TAMPFLT 3 2 TAMPPRCH TAMPPRCH 5 2 TAMPPUDIS TAMPPUDIS 7 1 IER IER TAMP interrupt enable register 0x2C 0x20 read-write 0x00000000 TAMP1IE TAMP1IE 0 1 TAMP2IE TAMP2IE 1 1 TAMP3IE TAMP3IE 2 1 ITAMP3IE ITAMP3IE 18 1 ITAMP4IE ITAMP4IE 19 1 ITAMP5IE ITAMP5IE 20 1 ITAMP6IE ITAMP6IE 21 1 SR SR TAMP status register 0x30 0x20 read-only 0x00000000 TAMP1F TAMP1F 0 1 TAMP2F TAMP2F 1 1 TAMP3F TAMP3F 2 1 ITAMP3F ITAMP3F 18 1 ITAMP4F ITAMP4F 19 1 ITAMP5F ITAMP5F 20 1 ITAMP6F ITAMP6F 21 1 MISR MISR TAMP masked interrupt status register 0x34 0x20 read-only 0x00000000 TAMP1MF TAMP1MF: 0 1 TAMP2MF TAMP2MF 1 1 TAMP3MF TAMP3MF 2 1 ITAMP3MF ITAMP3MF 18 1 ITAMP4MF ITAMP4MF 19 1 ITAMP5MF ITAMP5MF 20 1 ITAMP6MF ITAMP6MF 21 1 SCR SCR TAMP status clear register 0x3C 0x20 read-write 0x00000000 CTAMP1F CTAMP1F 0 1 CTAMP2F CTAMP2F 1 1 CTAMP3F CTAMP3F 2 1 CITAMP3F CITAMP3F 18 1 CITAMP4F CITAMP4F 19 1 CITAMP5F CITAMP5F 20 1 CITAMP6F CITAMP6F 21 1 BKP0R BKP0R TAMP backup register 0x100 0x20 read-write 0x00000000 BKP BKP 0 32 BKP1R BKP1R TAMP backup register 0x104 0x20 read-write 0x00000000 BKP BKP 0 32 BKP2R BKP2R TAMP backup register 0x108 0x20 read-write 0x00000000 BKP BKP 0 32 BKP3R BKP3R TAMP backup register 0x10C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP4R BKP4R TAMP backup register 0x110 0x20 read-write 0x00000000 BKP BKP 0 32 BKP5R BKP5R TAMP backup register 0x114 0x20 read-write 0x00000000 BKP BKP 0 32 BKP6R BKP6R TAMP backup register 0x118 0x20 read-write 0x00000000 BKP BKP 0 32 BKP7R BKP7R TAMP backup register 0x11C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP8R BKP8R TAMP backup register 0x120 0x20 read-write 0x00000000 BKP BKP 0 32 BKP9R BKP9R TAMP backup register 0x124 0x20 read-write 0x00000000 BKP BKP 0 32 BKP10R BKP10R TAMP backup register 0x128 0x20 read-write 0x00000000 BKP BKP 0 32 BKP11R BKP11R TAMP backup register 0x12C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP12R BKP12R TAMP backup register 0x130 0x20 read-write 0x00000000 BKP BKP 0 32 BKP13R BKP13R TAMP backup register 0x134 0x20 read-write 0x00000000 BKP BKP 0 32 BKP14R BKP14R TAMP backup register 0x138 0x20 read-write 0x00000000 BKP BKP 0 32 BKP15R BKP15R TAMP backup register 0x13C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP16R BKP16R TAMP backup register 0x140 0x20 read-write 0x00000000 BKP BKP 0 32 BKP17R BKP17R TAMP backup register 0x144 0x20 read-write 0x00000000 BKP BKP 0 32 BKP18R BKP18R TAMP backup register 0x148 0x20 read-write 0x00000000 BKP BKP 0 32 BKP19R BKP19R TAMP backup register 0x14C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP20R BKP20R TAMP backup register 0x150 0x20 read-write 0x00000000 BKP BKP 0 32 BKP21R BKP21R TAMP backup register 0x154 0x20 read-write 0x00000000 BKP BKP 0 32 BKP22R BKP22R TAMP backup register 0x158 0x20 read-write 0x00000000 BKP BKP 0 32 BKP23R BKP23R TAMP backup register 0x15C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP24R BKP24R TAMP backup register 0x160 0x20 read-write 0x00000000 BKP BKP 0 32 BKP25R BKP25R TAMP backup register 0x164 0x20 read-write 0x00000000 BKP BKP 0 32 BKP26R BKP26R TAMP backup register 0x168 0x20 read-write 0x00000000 BKP BKP 0 32 BKP27R BKP27R TAMP backup register 0x16C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP28R BKP28R TAMP backup register 0x170 0x20 read-write 0x00000000 BKP BKP 0 32 BKP29R BKP29R TAMP backup register 0x174 0x20 read-write 0x00000000 BKP BKP 0 32 BKP30R BKP30R TAMP backup register 0x178 0x20 read-write 0x00000000 BKP BKP 0 32 BKP31R BKP31R TAMP backup register 0x17C 0x20 read-write 0x00000000 BKP BKP 0 32 FPU Floting point unit FPU 0xE000EF34 0x0 0xD registers FPU Floating point unit interrupt 81 FPCCR FPCCR Floating-point context control register 0x0 0x20 read-write 0x00000000 LSPACT LSPACT 0 1 USER USER 1 1 THREAD THREAD 3 1 HFRDY HFRDY 4 1 MMRDY MMRDY 5 1 BFRDY BFRDY 6 1 MONRDY MONRDY 8 1 LSPEN LSPEN 30 1 ASPEN ASPEN 31 1 FPCAR FPCAR Floating-point context address register 0x4 0x20 read-write 0x00000000 ADDRESS Location of unpopulated floating-point 3 29 FPSCR FPSCR Floating-point status control register 0x8 0x20 read-write 0x00000000 IOC Invalid operation cumulative exception bit 0 1 DZC Division by zero cumulative exception bit. 1 1 OFC Overflow cumulative exception bit 2 1 UFC Underflow cumulative exception bit 3 1 IXC Inexact cumulative exception bit 4 1 IDC Input denormal cumulative exception bit. 7 1 RMode Rounding Mode control field 22 2 FZ Flush-to-zero mode control bit: 24 1 DN Default NaN mode control bit 25 1 AHP Alternative half-precision control bit 26 1 V Overflow condition code flag 28 1 C Carry condition code flag 29 1 Z Zero condition code flag 30 1 N Negative condition code flag 31 1 MPU Memory protection unit MPU 0xE000E084 0x0 0x15 registers TYPER TYPER MPU type register 0x0 0x20 read-only 0X00000800 SEPARATE Separate flag 0 1 DREGION Number of MPU data regions 8 8 IREGION Number of MPU instruction regions 16 8 CTRL CTRL MPU control register 0x4 0x20 read-write 0X00000000 ENABLE Enables the MPU 0 1 HFNMIENA Enables the operation of MPU during hard fault 1 1 PRIVDEFENA Enable priviliged software access to default memory map 2 1 RNR RNR MPU region number register 0x8 0x20 read-write 0X00000000 REGION MPU region 0 8 RBAR RBAR MPU region base address register 0xC 0x20 read-write 0X00000000 REGION MPU region field 0 4 VALID MPU region number valid 4 1 ADDR Region base address field 5 27 RASR RASR MPU region attribute and size register 0x10 0x20 read-write 0X00000000 ENABLE Region enable bit. 0 1 SIZE Size of the MPU protection region 1 5 SRD Subregion disable bits 8 8 B memory attribute 16 1 C memory attribute 17 1 S Shareable memory attribute 18 1 TEX memory attribute 19 3 AP Access permission 24 3 XN Instruction access disable bit 28 1 STK SysTick timer STK 0xE000E010 0x0 0x11 registers CTRL CTRL SysTick control and status register 0x0 0x20 read-write 0X00000000 ENABLE Counter enable 0 1 TICKINT SysTick exception request enable 1 1 CLKSOURCE Clock source selection 2 1 COUNTFLAG COUNTFLAG 16 1 LOAD LOAD SysTick reload value register 0x4 0x20 read-write 0X00000000 RELOAD RELOAD value 0 24 VAL VAL SysTick current value register 0x8 0x20 read-write 0X00000000 CURRENT Current counter value 0 24 CALIB CALIB SysTick calibration value register 0xC 0x20 read-write 0X00000000 TENMS Calibration value 0 24 SKEW SKEW flag: Indicates whether the TENMS value is exact 30 1 NOREF NOREF flag. Reads as zero 31 1 SCB System control block SCB 0xE000ED00 0x0 0x41 registers CPUID CPUID CPUID base register 0x0 0x20 read-only 0x410FC241 Revision Revision number 0 4 PartNo Part number of the processor 4 12 Constant Reads as 0xF 16 4 Variant Variant number 20 4 Implementer Implementer code 24 8 ICSR ICSR Interrupt control and state register 0x4 0x20 read-write 0x00000000 VECTACTIVE Active vector 0 9 RETTOBASE Return to base level 11 1 VECTPENDING Pending vector 12 7 ISRPENDING Interrupt pending flag 22 1 PENDSTCLR SysTick exception clear-pending bit 25 1 PENDSTSET SysTick exception set-pending bit 26 1 PENDSVCLR PendSV clear-pending bit 27 1 PENDSVSET PendSV set-pending bit 28 1 NMIPENDSET NMI set-pending bit. 31 1 VTOR VTOR Vector table offset register 0x8 0x20 read-write 0x00000000 TBLOFF Vector table base offset field 9 21 AIRCR AIRCR Application interrupt and reset control register 0xC 0x20 read-write 0x00000000 VECTRESET VECTRESET 0 1 VECTCLRACTIVE VECTCLRACTIVE 1 1 SYSRESETREQ SYSRESETREQ 2 1 PRIGROUP PRIGROUP 8 3 ENDIANESS ENDIANESS 15 1 VECTKEYSTAT Register key 16 16 SCR SCR System control register 0x10 0x20 read-write 0x00000000 SLEEPONEXIT SLEEPONEXIT 1 1 SLEEPDEEP SLEEPDEEP 2 1 SEVEONPEND Send Event on Pending bit 4 1 CCR CCR Configuration and control register 0x14 0x20 read-write 0x00000000 NONBASETHRDENA Configures how the processor enters Thread mode 0 1 USERSETMPEND USERSETMPEND 1 1 UNALIGN__TRP UNALIGN_ TRP 3 1 DIV_0_TRP DIV_0_TRP 4 1 BFHFNMIGN BFHFNMIGN 8 1 STKALIGN STKALIGN 9 1 SHPR1 SHPR1 System handler priority registers 0x18 0x20 read-write 0x00000000 PRI_4 Priority of system handler 4 0 8 PRI_5 Priority of system handler 5 8 8 PRI_6 Priority of system handler 6 16 8 SHPR2 SHPR2 System handler priority registers 0x1C 0x20 read-write 0x00000000 PRI_11 Priority of system handler 11 24 8 SHPR3 SHPR3 System handler priority registers 0x20 0x20 read-write 0x00000000 PRI_14 Priority of system handler 14 16 8 PRI_15 Priority of system handler 15 24 8 SHCSR SHCSR System handler control and state register 0x24 0x20 read-write 0x00000000 MEMFAULTACT Memory management fault exception active bit 0 1 BUSFAULTACT Bus fault exception active bit 1 1 USGFAULTACT Usage fault exception active bit 3 1 SVCALLACT SVC call active bit 7 1 MONITORACT Debug monitor active bit 8 1 PENDSVACT PendSV exception active bit 10 1 SYSTICKACT SysTick exception active bit 11 1 USGFAULTPENDED Usage fault exception pending bit 12 1 MEMFAULTPENDED Memory management fault exception pending bit 13 1 BUSFAULTPENDED Bus fault exception pending bit 14 1 SVCALLPENDED SVC call pending bit 15 1 MEMFAULTENA Memory management fault enable bit 16 1 BUSFAULTENA Bus fault enable bit 17 1 USGFAULTENA Usage fault enable bit 18 1 CFSR_UFSR_BFSR_MMFSR CFSR_UFSR_BFSR_MMFSR Configurable fault status register 0x28 0x20 read-write 0x00000000 IACCVIOL Instruction access violation flag 1 1 MUNSTKERR Memory manager fault on unstacking for a return from exception 3 1 MSTKERR Memory manager fault on stacking for exception entry. 4 1 MLSPERR MLSPERR 5 1 MMARVALID Memory Management Fault Address Register (MMAR) valid flag 7 1 IBUSERR Instruction bus error 8 1 PRECISERR Precise data bus error 9 1 IMPRECISERR Imprecise data bus error 10 1 UNSTKERR Bus fault on unstacking for a return from exception 11 1 STKERR Bus fault on stacking for exception entry 12 1 LSPERR Bus fault on floating-point lazy state preservation 13 1 BFARVALID Bus Fault Address Register (BFAR) valid flag 15 1 UNDEFINSTR Undefined instruction usage fault 16 1 INVSTATE Invalid state usage fault 17 1 INVPC Invalid PC load usage fault 18 1 NOCP No coprocessor usage fault. 19 1 UNALIGNED Unaligned access usage fault 24 1 DIVBYZERO Divide by zero usage fault 25 1 HFSR HFSR Hard fault status register 0x2C 0x20 read-write 0x00000000 VECTTBL Vector table hard fault 1 1 FORCED Forced hard fault 30 1 DEBUG_VT Reserved for Debug use 31 1 MMFAR MMFAR Memory management fault address register 0x34 0x20 read-write 0x00000000 MMFAR Memory management fault address 0 32 BFAR BFAR Bus fault address register 0x38 0x20 read-write 0x00000000 BFAR Bus fault address 0 32 AFSR AFSR Auxiliary fault status register 0x3C 0x20 read-write 0x00000000 IMPDEF Implementation defined 0 32 NVIC Nested Vectored Interrupt Controller NVIC 0xE000E100 0x0 0x400 registers ISER0 ISER0 Interrupt Set-Enable Register 0x0 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER1 ISER1 Interrupt Set-Enable Register 0x4 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER2 ISER2 Interrupt Set-Enable Register 0x8 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER3 ISER3 Interrupt Set-Enable Register 0xC 0x20 read-write 0x00000000 SETENA SETENA 0 32 ICER0 ICER0 Interrupt Clear-Enable Register 0x80 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER1 ICER1 Interrupt Clear-Enable Register 0x84 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER2 ICER2 Interrupt Clear-Enable Register 0x88 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER3 ICER3 Interrupt Clear-Enable Register 0x8C 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ISPR0 ISPR0 Interrupt Set-Pending Register 0x100 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR1 ISPR1 Interrupt Set-Pending Register 0x104 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR2 ISPR2 Interrupt Set-Pending Register 0x108 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR3 ISPR3 Interrupt Set-Pending Register 0x10C 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ICPR0 ICPR0 Interrupt Clear-Pending Register 0x180 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR1 ICPR1 Interrupt Clear-Pending Register 0x184 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR2 ICPR2 Interrupt Clear-Pending Register 0x188 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR3 ICPR3 Interrupt Clear-Pending Register 0x18C 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 IABR0 IABR0 Interrupt Active Bit Register 0x200 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR1 IABR1 Interrupt Active Bit Register 0x204 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR2 IABR2 Interrupt Active Bit Register 0x208 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR3 IABR3 Interrupt Active Bit Register 0x20C 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IPR0 IPR0 Interrupt Priority Register 0x300 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR1 IPR1 Interrupt Priority Register 0x304 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR2 IPR2 Interrupt Priority Register 0x308 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR3 IPR3 Interrupt Priority Register 0x30C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR4 IPR4 Interrupt Priority Register 0x310 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR5 IPR5 Interrupt Priority Register 0x314 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR6 IPR6 Interrupt Priority Register 0x318 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR7 IPR7 Interrupt Priority Register 0x31C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR8 IPR8 Interrupt Priority Register 0x320 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR9 IPR9 Interrupt Priority Register 0x324 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR10 IPR10 Interrupt Priority Register 0x328 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR11 IPR11 Interrupt Priority Register 0x32C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR12 IPR12 Interrupt Priority Register 0x330 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR13 IPR13 Interrupt Priority Register 0x334 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR14 IPR14 Interrupt Priority Register 0x338 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR15 IPR15 Interrupt Priority Register 0x33C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR16 IPR16 Interrupt Priority Register 0x340 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR17 IPR17 Interrupt Priority Register 0x344 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR18 IPR18 Interrupt Priority Register 0x348 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR19 IPR19 Interrupt Priority Register 0x34C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR20 IPR20 Interrupt Priority Register 0x350 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR21 IPR21 Interrupt Priority Register 0x354 0x20 read-write 0x00000000 IPR22 IPR22 Interrupt Priority Register 0x358 0x20 read-write 0x00000000 IPR23 IPR23 Interrupt Priority Register 0x35C 0x20 read-write 0x00000000 IPR24 IPR24 Interrupt Priority Register 0x360 0x20 read-write 0x00000000 IPR25 IPR25 Interrupt Priority Register 0x364 0x20 read-write 0x00000000 NVIC_STIR Nested vectored interrupt controller NVIC 0xE000EF00 0x0 0x5 registers STIR STIR Software trigger interrupt register 0x0 0x20 read-write 0x00000000 INTID Software generated interrupt ID 0 9 FPU_CPACR Floating point unit CPACR FPU 0xE000ED88 0x0 0x5 registers CPACR CPACR Coprocessor access control register 0x0 0x20 read-write 0x0000000 CP CP 20 4 SCB_ACTLR System control block ACTLR SCB 0xE000E008 0x0 0x5 registers ACTRL ACTRL Auxiliary control register 0x0 0x20 read-write 0x00000000 DISMCYCINT DISMCYCINT 0 1 DISDEFWBUF DISDEFWBUF 1 1 DISFOLD DISFOLD 2 1 DISFPCA DISFPCA 8 1 DISOOFP DISOOFP 9 1 FDCAN FDCAN FDCAN 0x4000A400 0x0 0x400 registers CREL CREL FDCAN Core Release Register 0x0 0x20 read-only 0x32141218 DAY DAY 0 8 MON MON 8 8 YEAR YEAR 16 4 SUBSTEP SUBSTEP 20 4 STEP STEP 24 4 REL REL 28 4 ENDN ENDN FDCAN Core Release Register 0x4 0x20 read-only 0x87654321 ETV ETV 0 32 DBTP DBTP This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. 0xC 0x20 0x00000A33 DSJW DSJW 0 4 read-write DTSEG2 DTSEG2 4 4 read-write DTSEG1 DTSEG1 8 5 read-write DBRP DBRP 16 5 read-write TDC TDC 23 1 read-write TEST TEST Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus. 0x10 0x20 0x00000000 LBCK LBCK 4 1 read-write TX TX 5 2 read-write RX RX 7 1 read-only RWD RWD The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock. 0x14 0x20 0x00000000 WDC WDC 0 8 read-write WDV WDV 8 8 read-only CCCR CCCR For details about setting and resetting of single bits see Software initialization. 0x18 0x20 0x00000001 INIT INIT 0 1 read-write CCE CCE 1 1 read-write ASM ASM 2 1 read-write CSA CSA 3 1 read-only CSR CSR 4 1 read-write MON MON 5 1 read-write DAR DAR 6 1 read-write TEST TEST 7 1 read-write FDOE FDOE 8 1 read-write BRSE BRSE 9 1 read-write PXHD PXHD 12 1 read-write EFBI EFBI 13 1 read-write TXP TXP 14 1 read-write NISO NISO 15 1 read-write NBTP NBTP FDCAN_NBTP 0x1C 0x20 read-write 0x06000A03 NTSEG2 NTSEG2 0 7 NTSEG1 NTSEG1 8 8 NBRP NBRP 16 9 NSJW NSJW 25 7 TSCC TSCC FDCAN Timestamp Counter Configuration Register 0x20 0x20 read-write 0x00000000 TSS TSS 0 2 TCP TCP 16 4 TSCV TSCV FDCAN Timestamp Counter Value Register 0x24 0x20 read-only 0x00000000 TSC TSC 0 16 TOCC TOCC FDCAN Timeout Counter Configuration Register 0x28 0x20 0xFFFF0000 ETOC ETOC 0 1 read-write TOS TOS 1 2 read-write TOP TOP 16 16 read-write TOCV TOCV FDCAN Timeout Counter Value Register 0x2C 0x20 read-only 0x0000FFFF TOC TOC 0 16 ECR ECR FDCAN Error Counter Register 0x40 0x20 read-only 0x00000000 TEC TEC 0 8 REC TREC 8 7 RP RP 15 1 CEL CEL 16 8 PSR PSR FDCAN Protocol Status Register 0x44 0x20 0x00000707 LEC LEC 0 3 read-write ACT ACT 3 2 read-only EP EP 5 1 read-only EW EW 6 1 read-only BO BO 7 1 read-only DLEC DLEC 8 3 read-write RESI RESI 11 1 read-write RBRS RBRS 12 1 read-write REDL REDL 13 1 read-write PXE PXE 14 1 read-write TDCV TDCV 16 7 read-write TDCR TDCR FDCAN Transmitter Delay Compensation Register 0x48 0x20 read-write 0x00000000 TDCF TDCF 0 7 TDCO TDCO 8 7 IR IR The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled. 0x50 0x20 read-write 0x00000000 RF0N RF0N 0 1 RF0F RF0F 1 1 RF0L RF0L 2 1 RF1N RF1N 3 1 RF1F RF1F 4 1 RF1L RF1L 5 1 HPM HPM 6 1 TC TC 7 1 TCF TCF 8 1 TFE TFE 9 1 TEFN TEFN 10 1 TEFF TEFF 11 1 TEFL TEFL 12 1 TSW TSW 13 1 MRAF MRAF 14 1 TOO TOO 15 1 ELO ELO 16 1 EP EP 17 1 EW EW 18 1 BO BO 19 1 WDI WDI 20 1 PEA PEA 21 1 PED PED 22 1 ARA ARA 23 1 IE IE The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line. 0x54 0x20 read-write 0x00000000 RF0NE RF0NE 0 1 RF0FE RF0FE 1 1 RF0LE RF0LE 2 1 RF1NE RF1NE 3 1 RF1FE RF1FE 4 1 RF1LE RF1LE 5 1 HPME HPME 6 1 TCE TCE 7 1 TCFE TCFE 8 1 TFEE TFEE 9 1 TEFNE TEFNE 10 1 TEFFE TEFFE 11 1 TEFLE TEFLE 12 1 TSWE TSWE 13 1 MRAFE MRAFE 14 1 TOOE TOOE 15 1 ELOE ELOE 16 1 EPE EPE 17 1 EWE EWE 18 1 BOE BOE 19 1 WDIE WDIE 20 1 PEAE PEAE 21 1 PEDE PEDE 22 1 ARAE ARAE 23 1 ILS ILS The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1]. 0x58 0x20 read-write 0x00000000 RxFIFO0 RxFIFO0 0 1 RxFIFO1 RxFIFO1 1 1 SMSG SMSG 2 1 TFERR TFERR 3 1 MISC MISC 4 1 BERR BERR 5 1 PERR PERR 6 1 ILE ILE Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1. 0x5C 0x20 read-write 0x00000000 EINT0 EINT0 0 1 EINT1 EINT1 1 1 RXGFC RXGFC Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path. 0x80 0x20 0x00000000 RRFE RRFE 0 1 read-write RRFS RRFS 1 1 read-write ANFE ANFE 2 2 read-write ANFS ANFS 4 2 read-write F1OM F1OM 8 1 read-write F0OM F0OM 9 1 read-write LSS LSS 16 5 read-write LSE LSE 24 4 read-write XIDAM XIDAM FDCAN Extended ID and Mask Register 0x84 0x20 read-write 0x1FFFFFFF EIDM EIDM 0 29 HPMS HPMS This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages. 0x88 0x20 read-only 0x00000000 BIDX BIDX 0 3 MSI MSI 6 2 FIDX FIDX 8 5 FLST FLST 15 1 RXF0S RXF0S FDCAN Rx FIFO 0 Status Register 0x90 0x20 read-only 0x00000000 F0FL F0FL 0 4 F0GI F0GI 8 2 F0PI F0PI 16 2 F0F F0F 24 1 RF0L RF0L 25 1 RXF0A RXF0A CAN Rx FIFO 0 Acknowledge Register 0x94 0x20 read-write 0x00000000 F0AI F0AI 0 3 RXF1S RXF1S FDCAN Rx FIFO 1 Status Register 0x98 0x20 read-only 0x00000000 F1FL F1FL 0 4 F1GI F1GI 8 2 F1PI F1PI 16 2 F1F F1F 24 1 RF1L RF1L 25 1 RXF1A RXF1A FDCAN Rx FIFO 1 Acknowledge Register 0x9C 0x20 read-write 0x00000000 F1AI F1AI 0 3 TXBC TXBC FDCAN Tx Buffer Configuration Register 0xC0 0x20 read-write 0x00000000 TFQM TFQM 24 1 TXFQS TXFQS The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated). 0xC4 0x20 read-only 0x00000003 TFFL TFFL 0 3 TFGI TFGI 8 2 TFQPI TFQPI 16 2 TFQF TFQF 21 1 TXBRP TXBRP FDCAN Tx Buffer Request Pending Register 0xC8 0x20 read-only 0x00000000 TRP TRP 0 3 TXBAR TXBAR FDCAN Tx Buffer Add Request Register 0xCC 0x20 read-write 0x00000000 AR AR 0 3 TXBCR TXBCR FDCAN Tx Buffer Cancellation Request Register 0xD0 0x20 read-write 0x00000000 CR CR 0 3 TXBTO TXBTO FDCAN Tx Buffer Transmission Occurred Register 0xD4 0x20 read-only 0x00000000 TO TO 0 3 TXBCF TXBCF FDCAN Tx Buffer Cancellation Finished Register 0xD8 0x20 read-only 0x00000000 CF CF 0 3 TXBTIE TXBTIE FDCAN Tx Buffer Transmission Interrupt Enable Register 0xDC 0x20 read-write 0x00000000 TIE TIE 0 3 TXBCIE TXBCIE FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register 0xE0 0x20 read-write 0x00000000 CFIE CFIE 0 3 TXEFS TXEFS FDCAN Tx Event FIFO Status Register 0xE4 0x20 read-only 0x00000000 EFFL EFFL 0 3 EFGI EFGI 8 2 EFPI EFPI 16 2 EFF EFF 24 1 TEFL TEFL 25 1 TXEFA TXEFA FDCAN Tx Event FIFO Acknowledge Register 0xE8 0x20 read-write 0x00000000 EFAI EFAI 0 2 CKDIV CKDIV FDCAN CFG clock divider register 0x100 0x20 read-write 0x00000000 PDIV input clock divider. the APB clock could be divided prior to be used by the CAN sub 0 4 FDCAN1 0x40006400 FDCAN1_IT0 FDCAN1 interrupt 0 21 FDCAN1_IT1 FDCAN1 interrupt 1 22 UCPD1 UCPD1 UCPD 0x4000A000 0x0 0x400 registers UCPD1 UCPD1 63 CFG1 CFG1 UCPD configuration register 1 0x0 0x20 read-write 0x00000000 HBITCLKDIV HBITCLKDIV 0 6 IFRGAP IFRGAP 6 5 TRANSWIN TRANSWIN 11 5 PSC_USBPDCLK PSC_USBPDCLK 17 3 RXORDSETEN RXORDSETEN 20 9 TXDMAEN TXDMAEN 29 1 RXDMAEN RXDMAEN 30 1 UCPDEN UCPDEN 31 1 CFG2 CFG2 UCPD configuration register 2 0x4 0x20 read-write 0x00000000 RXFILTDIS RXFILTDIS 0 1 RXFILT2N3 RXFILT2N3 1 1 FORCECLK FORCECLK 2 1 WUPEN WUPEN 3 1 CR CR UCPD configuration register 2 0xC 0x20 read-write 0x00000000 TXMODE TXMODE 0 2 TXSEND TXSEND 2 1 TXHRST TXHRST 3 1 RXMODE RXMODE 4 1 PHYRXEN PHYRXEN 5 1 PHYCCSEL PHYCCSEL 6 1 ANASUBMODE ANASUBMODE 7 2 ANAMODE ANAMODE 9 1 CCENABLE CCENABLE 10 2 FRSRXEN FRSRXEN 16 1 FRSTX FRSTX 17 1 RDCH RDCH 18 1 CC1TCDIS CC1TCDIS 20 1 CC2TCDIS CC2TCDIS 21 1 IMR IMR UCPD Interrupt Mask Register 0x10 0x20 read-write 0x00000000 TXISIE TXISIE 0 1 TXMSGDISCIE TXMSGDISCIE 1 1 TXMSGSENTIE TXMSGSENTIE 2 1 TXMSGABTIE TXMSGABTIE 3 1 HRSTDISCIE HRSTDISCIE 4 1 HRSTSENTIE HRSTSENTIE 5 1 TXUNDIE TXUNDIE 6 1 RXNEIE RXNEIE 8 1 RXORDDETIE RXORDDETIE 9 1 RXHRSTDETIE RXHRSTDETIE 10 1 RXOVRIE RXOVRIE 11 1 RXMSGENDIE RXMSGENDIE 12 1 TYPECEVT1IE TYPECEVT1IE 14 1 TYPECEVT2IE TYPECEVT2IE 15 1 FRSEVTIE FRSEVTIE 20 1 SR SR UCPD Status Register 0x14 0x20 read-write 0x00000000 TXIS TXIS 0 1 TXMSGDISC TXMSGDISC 1 1 TXMSGSENT TXMSGSENT 2 1 TXMSGABT TXMSGABT 3 1 HRSTDISC HRSTDISC 4 1 HRSTSENT HRSTSENT 5 1 TXUND TXUND 6 1 RXNE RXNE 8 1 RXORDDET RXORDDET 9 1 RXHRSTDET RXHRSTDET 10 1 RXOVR RXOVR 11 1 RXMSGEND RXMSGEND 12 1 RXERR RXERR 13 1 TYPECEVT1 TYPECEVT1 14 1 TYPECEVT2 TYPECEVT2 15 1 TYPEC_VSTATE_CC1 TYPEC_VSTATE_CC1 16 2 TYPEC_VSTATE_CC2 TYPEC_VSTATE_CC2 18 2 FRSEVT FRSEVT 20 1 ICR ICR UCPD Interrupt Clear Register 0x18 0x20 read-write 0x00000000 TXMSGDISCCF TXMSGDISCCF 1 1 TXMSGSENTCF TXMSGSENTCF 2 1 TXMSGABTCF TXMSGABTCF 3 1 HRSTDISCCF HRSTDISCCF 4 1 HRSTSENTCF HRSTSENTCF 5 1 TXUNDCF TXUNDCF 6 1 RXORDDETCF RXORDDETCF 9 1 RXHRSTDETCF RXHRSTDETCF 10 1 RXOVRCF RXOVRCF 11 1 RXMSGENDCF RXMSGENDCF 12 1 TYPECEVT1CF TYPECEVT1CF 14 1 TYPECEVT2CF TYPECEVT2CF 15 1 FRSEVTCF FRSEVTCF 20 1 TX_ORDSET TX_ORDSET UCPD Tx Ordered Set Type Register 0x1C 0x20 read-write 0x00000000 TXORDSET TXORDSET 0 20 TX_PAYSZ TX_PAYSZ UCPD Tx Paysize Register 0x20 0x20 read-write 0x00000000 TXPAYSZ TXPAYSZ 0 10 TXDR TXDR UCPD Tx Data Register 0x24 0x20 read-write 0x00000000 TXDATA TXDATA 0 8 RX_ORDSET RX_ORDSET UCPD Rx Ordered Set Register 0x28 0x20 read-only 0x00000000 RXORDSET RXORDSET 0 3 RXSOP3OF4 RXSOP3OF4 3 1 RXSOPKINVALID RXSOPKINVALID 4 3 RX_PAYSZ RX_PAYSZ UCPD Rx Paysize Register 0x2C 0x20 read-only 0x00000000 RXPAYSZ RXPAYSZ 0 10 RXDR RXDR UCPD Rx Data Register 0x30 0x20 read-only 0x00000000 RXDATA RXDATA 0 8 RX_ORDEXT1 RX_ORDEXT1 UCPD Rx Ordered Set Extension Register 1 0x34 0x20 read-write 0x00000000 RXSOPX1 RXSOPX1 0 20 RX_ORDEXT2 RX_ORDEXT2 UCPD Rx Ordered Set Extension Register 2 0x38 0x20 read-write 0x00000000 RXSOPX2 RXSOPX2 0 20 USB_FS_device USB_FS_device USB 0x40005C00 0x0 0x400 registers EP0R EP0R USB endpoint n register 0x0 0x20 read-write 0x00000000 EA EA 0 4 STAT_TX STAT_TX 4 2 DTOG_TX DTOG_TX 6 1 CTR_TX CTR_TX 7 1 EP_KIND EP_KIND 8 1 EP_TYPE EP_TYPE 9 2 SETUP SETUP 11 1 STAT_RX STAT_RX 12 2 DTOG_RX DTOG_RX 14 1 CTR_RX CTR_RX 15 1 EP1R EP1R USB endpoint n register 0x4 0x20 read-write 0x00000000 EA EA 0 4 STAT_TX STAT_TX 4 2 DTOG_TX DTOG_TX 6 1 CTR_TX CTR_TX 7 1 EP_KIND EP_KIND 8 1 EP_TYPE EP_TYPE 9 2 SETUP SETUP 11 1 STAT_RX STAT_RX 12 2 DTOG_RX DTOG_RX 14 1 CTR_RX CTR_RX 15 1 EP2R EP2R USB endpoint n register 0x8 0x20 read-write 0x00000000 EA EA 0 4 STAT_TX STAT_TX 4 2 DTOG_TX DTOG_TX 6 1 CTR_TX CTR_TX 7 1 EP_KIND EP_KIND 8 1 EP_TYPE EP_TYPE 9 2 SETUP SETUP 11 1 STAT_RX STAT_RX 12 2 DTOG_RX DTOG_RX 14 1 CTR_RX CTR_RX 15 1 EP3R EP3R USB endpoint n register 0xC 0x20 read-write 0x00000000 EA EA 0 4 STAT_TX STAT_TX 4 2 DTOG_TX DTOG_TX 6 1 CTR_TX CTR_TX 7 1 EP_KIND EP_KIND 8 1 EP_TYPE EP_TYPE 9 2 SETUP SETUP 11 1 STAT_RX STAT_RX 12 2 DTOG_RX DTOG_RX 14 1 CTR_RX CTR_RX 15 1 EP4R EP4R USB endpoint n register 0x10 0x20 read-write 0x00000000 EA EA 0 4 STAT_TX STAT_TX 4 2 DTOG_TX DTOG_TX 6 1 CTR_TX CTR_TX 7 1 EP_KIND EP_KIND 8 1 EP_TYPE EP_TYPE 9 2 SETUP SETUP 11 1 STAT_RX STAT_RX 12 2 DTOG_RX DTOG_RX 14 1 CTR_RX CTR_RX 15 1 EP5R EP5R USB endpoint n register 0x14 0x20 read-write 0x00000000 EA EA 0 4 STAT_TX STAT_TX 4 2 DTOG_TX DTOG_TX 6 1 CTR_TX CTR_TX 7 1 EP_KIND EP_KIND 8 1 EP_TYPE EP_TYPE 9 2 SETUP SETUP 11 1 STAT_RX STAT_RX 12 2 DTOG_RX DTOG_RX 14 1 CTR_RX CTR_RX 15 1 EP6R EP6R USB endpoint n register 0x18 0x20 read-write 0x00000000 EA EA 0 4 STAT_TX STAT_TX 4 2 DTOG_TX DTOG_TX 6 1 CTR_TX CTR_TX 7 1 EP_KIND EP_KIND 8 1 EP_TYPE EP_TYPE 9 2 SETUP SETUP 11 1 STAT_RX STAT_RX 12 2 DTOG_RX DTOG_RX 14 1 CTR_RX CTR_RX 15 1 EP7R EP7R USB endpoint n register 0x1C 0x20 read-write 0x00000000 EA EA 0 4 STAT_TX STAT_TX 4 2 DTOG_TX DTOG_TX 6 1 CTR_TX CTR_TX 7 1 EP_KIND EP_KIND 8 1 EP_TYPE EP_TYPE 9 2 SETUP SETUP 11 1 STAT_RX STAT_RX 12 2 DTOG_RX DTOG_RX 14 1 CTR_RX CTR_RX 15 1 CNTR CNTR USB control register 0x40 0x20 read-write 0x00000000 FRES FRES 0 1 PDWN PDWN 1 1 LP_MODE LP_MODE 2 1 FSUSP FSUSP 3 1 RESUME RESUME 4 1 L1RESUME L1RESUME 5 1 L1REQM L1REQM 7 1 ESOFM ESOFM 8 1 SOFM SOFM 9 1 RESETM RESETM 10 1 SUSPM SUSPM 11 1 WKUPM WKUPM 12 1 ERRM ERRM 13 1 PMAOVRM PMAOVRM 14 1 CTRM CTRM 15 1 ISTR ISTR USB interrupt status register 0x44 0x20 read-write 0x00000000 EP_ID EP_ID 0 4 DIR DIR 4 1 L1REQ L1REQ 7 1 ESOF ESOF 8 1 SOF SOF 9 1 RESET RESET 10 1 SUSP SUSP 11 1 WKUP WKUP 12 1 ERR ERR 13 1 PMAOVR PMAOVR 14 1 CTR CTR 15 1 FNR FNR USB frame number register 0x48 0x20 read-only 0x00000000 FN FN 0 11 LSOF LSOF 11 2 LCK LCK 13 1 RXDM RXDM 14 1 RXDP RXDP 15 1 DADDR DADDR USB device address 0x4C 0x20 read-write 0x00000000 ADD ADD 0 7 EF EF 7 1 BTABLE BTABLE Buffer table address 0x50 0x20 read-write 0x00000000 BTABLE BTABLE 3 13 CRS CRS CRS 0x40002000 0x0 0x400 registers CR CR CRS control register 0x0 0x20 0x00004000 SYNCOKIE SYNC event OK interrupt enable 0 1 read-write SYNCWARNIE SYNC warning interrupt enable 1 1 read-write ERRIE Synchronization or trimming error interrupt enable 2 1 read-write ESYNCIE Expected SYNC interrupt enable 3 1 read-write CEN Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set, the CRS_CFGR register is write-protected and cannot be modified. 5 1 read-write AUTOTRIMEN Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details. 6 1 read-write SWSYNC Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware. 7 1 read-write TRIM HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only. 8 7 read-write CFGR CFGR This register can be written only when the frequency error counter is disabled (CEN bit is cleared in CRS_CR). When the counter is enabled, this register is write-protected. 0x4 0x20 read-write 0x2022BB7F RELOAD Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section7.3.3: Frequency error measurement for more details about counter behavior. 0 16 FELIM Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP evaluation. 16 8 SYNCDIV SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal. 24 3 SYNCSRC SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs should be used as SYNC signal. 28 2 SYNCPOL SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source. 31 1 ISR ISR CRS interrupt and status register 0x8 0x20 read-only 0x00000000 SYNCOKF SYNC event OK flag This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register. 0 1 SYNCWARNF SYNC warning flag This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register. 1 1 ERRF Error flag This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits. 2 1 ESYNCF Expected SYNC flag This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register. 3 1 SYNCERR SYNC error This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action should be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 8 1 SYNCMISS SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action should be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 9 1 TRIMOVF Trimming overflow or underflow This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 10 1 FEDIR Frequency error direction FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. 15 1 FECAP Frequency error capture FECAP is the frequency error counter value latched in the time ofthe last SYNC event. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP usage. 16 16 ICR ICR CRS interrupt flag clear register 0xC 0x20 read-write 0x00000000 SYNCOKC SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register. 0 1 SYNCWARNC SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register. 1 1 ERRC Error clear flag Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register. 2 1 ESYNCC Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register. 3 1