From 7795a7cd7dbce6bd6ed3f289dd8247fae5c45738 Mon Sep 17 00:00:00 2001 From: jazzpi Date: Mon, 18 Jul 2022 16:54:42 +0200 Subject: [PATCH] Working version --- .mxproject | 20 +- Core/Inc/AIR_State_Maschine.h | 21 +- Core/Inc/CAN_Communication.h | 2 +- Core/Inc/SPI_Slave_Communication.h | 1 - Core/Inc/Slave_Monitoring.h | 3 +- Core/Inc/main.h | 28 - Core/Inc/stm32g4xx_hal_conf.h | 2 +- Core/Inc/stm32g4xx_it.h | 3 - Core/Src/AIR_State_Maschine.c | 116 +- Core/Src/CAN_Communication.c | 45 +- Core/Src/Error_Check.c | 19 - Core/Src/SPI_Slave_Communication.c | 31 +- Core/Src/main.c | 191 +- Core/Src/stm32g4xx_hal_msp.c | 209 - Core/Src/stm32g4xx_it.c | 47 - .../Inc/stm32g4xx_hal_adc.h | 2034 - .../Inc/stm32g4xx_hal_adc_ex.h | 1393 - .../Inc/stm32g4xx_ll_adc.h | 8183 ---- .../Src/stm32g4xx_hal_adc.c | 3682 -- .../Src/stm32g4xx_hal_adc_ex.c | 2373 - .../Src/stm32g4xx_ll_adc.c | 1425 - Makefile | 5 +- Master_Control.ioc | 268 +- STM32Make.make | 14 +- stm32g441xx.svd | 40278 ++++++++++++++++ 25 files changed, 40462 insertions(+), 19931 deletions(-) delete mode 100644 Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h delete mode 100644 Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h delete mode 100644 Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h delete mode 100644 Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c delete mode 100644 Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c delete mode 100644 Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c create mode 100644 stm32g441xx.svd diff --git a/.mxproject b/.mxproject index 15bedb0..c50bd05 100644 --- a/.mxproject +++ b/.mxproject @@ -1,25 +1,25 @@ [PreviousLibFiles] -LibFiles=Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h;Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h;Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h;Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g441xx.h;Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h;Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h;Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c;Drivers/CMSIS/Include/cmsis_armclang_ltm.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/core_cm35p.h; +LibFiles=Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h;Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h;Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h;Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g441xx.h;Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h;Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h;Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c;Drivers/CMSIS/Include/cmsis_armclang_ltm.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/core_cm35p.h; [PreviousUsedMakefileFiles] -SourceFiles=Core/Src/main.c;Core/Src/stm32g4xx_it.c;Core/Src/stm32g4xx_hal_msp.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c;Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c;Core/Src/system_stm32g4xx.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c;Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c;Core/Src/system_stm32g4xx.c;;; +SourceFiles=Core/Src/main.c;Core/Src/stm32g4xx_it.c;Core/Src/stm32g4xx_hal_msp.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c;Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c;Core/Src/system_stm32g4xx.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_fdcan.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c;Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c;Core/Src/system_stm32g4xx.c;;; HeaderPath=Drivers/STM32G4xx_HAL_Driver/Inc;Drivers/STM32G4xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32G4xx/Include;Drivers/CMSIS/Include;Core/Inc; CDefines=USE_HAL_DRIVER;STM32G441xx;USE_HAL_DRIVER;USE_HAL_DRIVER; [PreviousGenFiles] AdvancedFolderStructure=true HeaderFileListSize=3 -HeaderFiles#0=/home/jasper/dev/Master_Control/Core/Inc/stm32g4xx_it.h -HeaderFiles#1=/home/jasper/dev/Master_Control/Core/Inc/stm32g4xx_hal_conf.h -HeaderFiles#2=/home/jasper/dev/Master_Control/Core/Inc/main.h +HeaderFiles#0=../Core/Inc/stm32g4xx_it.h +HeaderFiles#1=../Core/Inc/stm32g4xx_hal_conf.h +HeaderFiles#2=../Core/Inc/main.h HeaderFolderListSize=1 -HeaderPath#0=/home/jasper/dev/Master_Control/Core/Inc +HeaderPath#0=../Core/Inc HeaderFiles=; SourceFileListSize=3 -SourceFiles#0=/home/jasper/dev/Master_Control/Core/Src/stm32g4xx_it.c -SourceFiles#1=/home/jasper/dev/Master_Control/Core/Src/stm32g4xx_hal_msp.c -SourceFiles#2=/home/jasper/dev/Master_Control/Core/Src/main.c +SourceFiles#0=../Core/Src/stm32g4xx_it.c +SourceFiles#1=../Core/Src/stm32g4xx_hal_msp.c +SourceFiles#2=../Core/Src/main.c SourceFolderListSize=1 -SourcePath#0=/home/jasper/dev/Master_Control/Core/Src +SourcePath#0=../Core/Src SourceFiles=; diff --git a/Core/Inc/AIR_State_Maschine.h b/Core/Inc/AIR_State_Maschine.h index 9286950..b523445 100644 --- a/Core/Inc/AIR_State_Maschine.h +++ b/Core/Inc/AIR_State_Maschine.h @@ -18,9 +18,12 @@ #define TS_DISCHARGE 3 #define TS_ERROR 4 #define TS_ACTIVE 1 +#define TS_CHARGING_CHECK 5 +#define TS_CHARGING 6 -#define ADC_READ_TIMEOUT 500 // in ms -#define SDC_LOWER_THRESHOLD 2500 // in ADC Values +#define ADC_READ_TIMEOUT 500 // in ms +#define SDC_LOWER_THRESHOLD 2500 // in ADC Values +#define PRECHARGE_95_DURATION 1000 // in ms // FIXME #define LOWER_VEHICLE_SIDE_VOLTAGE_LIMIT 150000 // in mV @@ -30,18 +33,12 @@ typedef struct { int32_t BatteryVoltageBatterySide; uint8_t targetTSState; uint8_t currentTSState; - uint16_t AIRPrechargeCurrent; // ADC Value - uint16_t AIRPositiveCurrent; // ADC Value - uint16_t AIRNegativeCurrent; // ADC Value - uint16_t RelaisSupplyVoltage; - uint16_t ShutdownCircuitVoltage; + uint32_t precharge95ReachedTimestamp; + uint32_t chargingCheckTimestamp; } AIRStateHandler; -AIRStateHandler init_AIR_State_Maschine(ADC_HandleTypeDef* relay_adc, - ADC_HandleTypeDef* sc_adc, - DMA_HandleTypeDef* relay_dma, - DMA_HandleTypeDef* sc_dma); +AIRStateHandler init_AIR_State_Maschine(); void Update_AIR_Info(AIRStateHandler* airstate); uint8_t Update_AIR_State(AIRStateHandler* airstate); @@ -54,6 +51,4 @@ void AIR_Discharge_Position(); void AIR_Active_Position(); void AIR_Error_Position(); -void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); - #endif /* INC_AIR_STATE_MASCHINE_H_ */ diff --git a/Core/Inc/CAN_Communication.h b/Core/Inc/CAN_Communication.h index ce1baed..b2cac6d 100644 --- a/Core/Inc/CAN_Communication.h +++ b/Core/Inc/CAN_Communication.h @@ -15,7 +15,7 @@ #include "stm32g4xx_hal.h" #include "stm32g4xx_hal_fdcan.h" -#define CANFRAMEBUFFERSIZE 256 +#define CANFRAMEBUFFERSIZE 512 // Frame ID = Base Address + Slave ID + MessageNr. #define SLAVE_STATUS_BASE_ADDRESS 0x600 diff --git a/Core/Inc/SPI_Slave_Communication.h b/Core/Inc/SPI_Slave_Communication.h index d5d9988..2eaee6b 100644 --- a/Core/Inc/SPI_Slave_Communication.h +++ b/Core/Inc/SPI_Slave_Communication.h @@ -14,7 +14,6 @@ #include "stm32g4xx_hal_crc.h" - #define SET_SHUNTDATA 0x01 #define SET_TSSTATE 0x02 #define GET_TSSTATE 0x03 diff --git a/Core/Inc/Slave_Monitoring.h b/Core/Inc/Slave_Monitoring.h index dd93c27..204f563 100644 --- a/Core/Inc/Slave_Monitoring.h +++ b/Core/Inc/Slave_Monitoring.h @@ -14,12 +14,11 @@ #include "stm32g441xx.h" - #define NUMBEROFSLAVES 6 #define NUMBEROFCELLS 10 #define NUMBEROFTEMPS 32 -#define SLAVETIMEOUT 2000 +#define SLAVETIMEOUT 500 typedef struct { diff --git a/Core/Inc/main.h b/Core/Inc/main.h index fd86fcb..8937c6c 100644 --- a/Core/Inc/main.h +++ b/Core/Inc/main.h @@ -67,42 +67,14 @@ void AMS_Error_Handler(AMSErrorHandle); #define BOOT0_FF_CLK_GPIO_Port GPIOC #define BOOT0_FF_DATA_Pin GPIO_PIN_15 #define BOOT0_FF_DATA_GPIO_Port GPIOC -#define Relay_Supply_Voltage_Pin GPIO_PIN_0 -#define Relay_Supply_Voltage_GPIO_Port GPIOA -#define Pos_AIR_Current_Pin GPIO_PIN_1 -#define Pos_AIR_Current_GPIO_Port GPIOA -#define Neg_AIR_Current_Pin GPIO_PIN_2 -#define Neg_AIR_Current_GPIO_Port GPIOA -#define PreCharge_AIR_Current_Pin GPIO_PIN_3 -#define PreCharge_AIR_Current_GPIO_Port GPIOA -#define SC_Supply_Voltage_Pin GPIO_PIN_4 -#define SC_Supply_Voltage_GPIO_Port GPIOA #define AMS_ERROR_Pin GPIO_PIN_0 #define AMS_ERROR_GPIO_Port GPIOB -#define IMD_Error_Pin GPIO_PIN_1 -#define IMD_Error_GPIO_Port GPIOB -#define AMS_Error_LED_Pin GPIO_PIN_2 -#define AMS_Error_LED_GPIO_Port GPIOB -#define Volt_Error_CPU_Pin GPIO_PIN_10 -#define Volt_Error_CPU_GPIO_Port GPIOB -#define Positive_Side_Error_CPU_Pin GPIO_PIN_11 -#define Positive_Side_Error_CPU_GPIO_Port GPIOB -#define Neg_Side_Error_CPU_Pin GPIO_PIN_12 -#define Neg_Side_Error_CPU_GPIO_Port GPIOB -#define HV_Inactive_CPU_Pin GPIO_PIN_13 -#define HV_Inactive_CPU_GPIO_Port GPIOB -#define Neg_AIR_Open_CPU_Pin GPIO_PIN_14 -#define Neg_AIR_Open_CPU_GPIO_Port GPIOB -#define High_Side_Open_CPU_Pin GPIO_PIN_15 -#define High_Side_Open_CPU_GPIO_Port GPIOB #define Inter_STM_CS_Pin GPIO_PIN_8 #define Inter_STM_CS_GPIO_Port GPIOA #define Inter_STM_IRQ_Pin GPIO_PIN_9 #define Inter_STM_IRQ_GPIO_Port GPIOA #define Status_LED_Pin GPIO_PIN_10 #define Status_LED_GPIO_Port GPIOA -#define IMD_Error_LED_Pin GPIO_PIN_3 -#define IMD_Error_LED_GPIO_Port GPIOB #define PreCharge_Control_Pin GPIO_PIN_5 #define PreCharge_Control_GPIO_Port GPIOB #define AIR_Positive_Control_Pin GPIO_PIN_6 diff --git a/Core/Inc/stm32g4xx_hal_conf.h b/Core/Inc/stm32g4xx_hal_conf.h index 24f0a8b..8415aea 100644 --- a/Core/Inc/stm32g4xx_hal_conf.h +++ b/Core/Inc/stm32g4xx_hal_conf.h @@ -36,7 +36,7 @@ #define HAL_MODULE_ENABLED - #define HAL_ADC_MODULE_ENABLED + /*#define HAL_ADC_MODULE_ENABLED */ /*#define HAL_COMP_MODULE_ENABLED */ /*#define HAL_CORDIC_MODULE_ENABLED */ #define HAL_CRC_MODULE_ENABLED diff --git a/Core/Inc/stm32g4xx_it.h b/Core/Inc/stm32g4xx_it.h index 8645c61..8334460 100644 --- a/Core/Inc/stm32g4xx_it.h +++ b/Core/Inc/stm32g4xx_it.h @@ -56,12 +56,9 @@ void SVC_Handler(void); void DebugMon_Handler(void); void PendSV_Handler(void); void SysTick_Handler(void); -void DMA1_Channel2_IRQHandler(void); -void ADC1_2_IRQHandler(void); void FDCAN1_IT0_IRQHandler(void); void FDCAN1_IT1_IRQHandler(void); void SPI1_IRQHandler(void); -void DMA2_Channel1_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ diff --git a/Core/Src/AIR_State_Maschine.c b/Core/Src/AIR_State_Maschine.c index 93d5ae9..1c11165 100644 --- a/Core/Src/AIR_State_Maschine.c +++ b/Core/Src/AIR_State_Maschine.c @@ -7,8 +7,7 @@ #include "AIR_State_Maschine.h" -ADC_HandleTypeDef* air_current_adc = {0}; -ADC_HandleTypeDef* sdc_voltage_adc = {0}; +#include "stm32g4xx_hal.h" DMA_HandleTypeDef* air_current_dma = {0}; DMA_HandleTypeDef* sdc_voltage_dma = {0}; @@ -16,25 +15,11 @@ DMA_HandleTypeDef* sdc_voltage_dma = {0}; uint8_t air_adc_complete = 0; uint8_t sdc_adc_complete = 0; -AIRStateHandler init_AIR_State_Maschine(ADC_HandleTypeDef* relay_adc, - ADC_HandleTypeDef* sc_adc, - DMA_HandleTypeDef* relay_dma, - DMA_HandleTypeDef* sc_dma) { - air_current_adc = relay_adc; - sdc_voltage_adc = sc_adc; - - air_current_dma = relay_dma; - sdc_voltage_dma = sc_dma; - +AIRStateHandler init_AIR_State_Maschine() { AIRStateHandler airstate = {0}; airstate.targetTSState = TS_INACTIVE; airstate.currentTSState = TS_INACTIVE; - airstate.ShutdownCircuitVoltage = 0; - airstate.RelaisSupplyVoltage = 0; - airstate.AIRNegativeCurrent = 0; - airstate.AIRPositiveCurrent = 0; - airstate.AIRPrechargeCurrent = 0; airstate.BatteryVoltageBatterySide = 0; airstate.BatteryVoltageVehicleSide = 0; @@ -65,16 +50,6 @@ void Update_AIR_Info(AIRStateHandler* airstate) { status = HAL_ADC_PollForConversion(air_current_adc, 10); uint32_t adcval5 = HAL_ADC_GetValue(air_current_adc); HAL_ADC_Stop(air_current_adc);*/ - - uint32_t startmils = HAL_GetTick() + ADC_READ_TIMEOUT; - - { - airstate->RelaisSupplyVoltage = 3000; - airstate->AIRPositiveCurrent = 0; - airstate->AIRNegativeCurrent = 0; - airstate->AIRPrechargeCurrent = 0; - airstate->ShutdownCircuitVoltage = 3000; - } } uint8_t Update_AIR_State(AIRStateHandler* airstate) { @@ -91,25 +66,7 @@ uint8_t Update_AIR_State(AIRStateHandler* airstate) { if (airstate->currentTSState == TS_ERROR) // No Escape from TS Error State { - return TS_ERROR; - } - - else if ((airstate->currentTSState == TS_INACTIVE) && - (airstate->targetTSState == - TS_ACTIVE)) // Transition from Inactive to Active via Precharge - { - if ((airstate->RelaisSupplyVoltage) > SDC_LOWER_THRESHOLD) { - airstate->currentTSState = TS_PRECHARGE; - } - } - - // TODO: Is it correct that we also go from precharge to discharge? - else if ((airstate->currentTSState == TS_ACTIVE || - airstate->currentTSState == TS_PRECHARGE) && - (airstate->targetTSState == - TS_INACTIVE)) // Transition from Active to Inactive via Discharge - { - airstate->currentTSState = TS_DISCHARGE; + // Don't change anything, but prevent any other if from being entered } else if (airstate->targetTSState == @@ -118,6 +75,41 @@ uint8_t Update_AIR_State(AIRStateHandler* airstate) { airstate->currentTSState = TS_ERROR; } + else if ((airstate->currentTSState == TS_INACTIVE) && + (airstate->targetTSState == + TS_ACTIVE)) // Transition from Inactive to Active via Precharge + { + airstate->currentTSState = TS_PRECHARGE; + airstate->precharge95ReachedTimestamp = 0; + } + + else if ((airstate->currentTSState == TS_INACTIVE) && + (airstate->targetTSState == TS_CHARGING)) { + airstate->currentTSState = TS_CHARGING_CHECK; + airstate->chargingCheckTimestamp = HAL_GetTick(); + } + + // TODO: Is it correct that we also go from precharge to discharge? + else if ((airstate->currentTSState == TS_ACTIVE || + airstate->currentTSState == TS_PRECHARGE || + airstate->currentTSState == TS_CHARGING_CHECK || + airstate->currentTSState == TS_CHARGING) && + (airstate->targetTSState == + TS_INACTIVE)) // Transition from Active to Inactive via Discharge + { + airstate->currentTSState = TS_DISCHARGE; + } + + else if ((airstate->targetTSState == TS_CHARGING) && + (airstate->currentTSState == TS_CHARGING_CHECK)) { + if (airstate->BatteryVoltageVehicleSide > + airstate->BatteryVoltageBatterySide) { + airstate->currentTSState = TS_CHARGING; + } else if (HAL_GetTick() > airstate->chargingCheckTimestamp + 2000) { + airstate->currentTSState = TS_ERROR; + } + } + else if (airstate->currentTSState == TS_PRECHARGE) // Change from Precharge to Active at 95% TS Voltage at // Vehicle Side @@ -125,15 +117,20 @@ uint8_t Update_AIR_State(AIRStateHandler* airstate) { if ((airstate->BatteryVoltageVehicleSide > LOWER_VEHICLE_SIDE_VOLTAGE_LIMIT)) { if (airstate->BatteryVoltageVehicleSide > - (airstate->BatteryVoltageBatterySide * 0.90)) { - airstate->currentTSState = TS_ACTIVE; + (airstate->BatteryVoltageBatterySide * 0.95)) { + if (airstate->precharge95ReachedTimestamp == 0) { + airstate->precharge95ReachedTimestamp = HAL_GetTick(); + } else if (HAL_GetTick() - airstate->precharge95ReachedTimestamp >= + PRECHARGE_95_DURATION) { + airstate->currentTSState = TS_ACTIVE; + } } } } else if (airstate->currentTSState == - TS_DISCHARGE) // Change from Discharge to Inactive at 95% TS Voltage - // at Vehicle Side + TS_DISCHARGE) // Change from Discharge to Inactive at 95% TS + // Voltage at Vehicle Side { airstate->currentTSState = TS_INACTIVE; } @@ -149,6 +146,14 @@ uint8_t Update_AIR_State(AIRStateHandler* airstate) { AIR_Discharge_Position(); } + if (airstate->currentTSState == TS_CHARGING_CHECK) { + AIR_Precharge_Position(); + } + + if (airstate->currentTSState == TS_CHARGING) { + AIR_Active_Position(); + } + if (airstate->currentTSState == TS_ACTIVE) { AIR_Active_Position(); } @@ -218,14 +223,3 @@ void AIR_Error_Position() { HAL_GPIO_WritePin(AIR_Positive_Control_GPIO_Port, AIR_Positive_Control_Pin, GPIO_PIN_RESET); } - -void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) { - if (hadc == air_current_adc) { - air_adc_complete = 1; - HAL_ADC_Stop_DMA(air_current_adc); - } - if (hadc == sdc_voltage_adc) { - sdc_adc_complete = 1; - HAL_ADC_Stop_DMA(sdc_voltage_adc); - } -} diff --git a/Core/Src/CAN_Communication.c b/Core/Src/CAN_Communication.c index 93283aa..a37a2c4 100644 --- a/Core/Src/CAN_Communication.c +++ b/Core/Src/CAN_Communication.c @@ -11,12 +11,12 @@ #include "stm32g4xx_hal_fdcan.h" - +// 3 should be programmed with CAN id 2 const uint16_t slave_CAN_id_to_slave_index[7] = { - 0, 1, 2, 3, 255, 5, 4}; // TODO: Make this pretty pls + 0, 1, 2, 3, 4, 5, 255}; // TODO: Make this pretty pls canFrame framebuffer[CANFRAMEBUFFERSIZE] = {0}; -uint8_t framebufferwritepointer; -uint8_t framebufferreadpointer; +uint32_t framebufferwritepointer; +uint32_t framebufferreadpointer; void CAN_Init(FDCAN_HandleTypeDef* hcan) { HAL_FDCAN_Stop(hcan); @@ -27,8 +27,8 @@ void CAN_Init(FDCAN_HandleTypeDef* hcan) { FDCAN_FilterTypeDef fdfilter = {0}; fdfilter.FilterConfig = FDCAN_FILTER_TO_RXFIFO0; - fdfilter.FilterID1 = 0x000; // Range start - fdfilter.FilterID2 = 0x000; // Range stop + fdfilter.FilterID1 = 0x000; // ID + fdfilter.FilterID2 = 0x000; // Mask fdfilter.FilterIndex = 0; fdfilter.FilterType = FDCAN_FILTER_MASK; @@ -38,6 +38,10 @@ void CAN_Init(FDCAN_HandleTypeDef* hcan) { HAL_StatusTypeDef status = HAL_FDCAN_Start(hcan); + if (status) { + return; + } + status = HAL_FDCAN_ActivateNotification(hcan, FDCAN_IT_RX_FIFO0_NEW_MESSAGE, 0); } @@ -59,23 +63,20 @@ uint8_t CAN_Receive(FDCAN_HandleTypeDef* hcan) { slaveID = slave_CAN_id_to_slave_index[slaveID]; uint8_t messageID = msg & 0x00F; updateSlaveInfo(slaveID, messageID, rxFrame); + } else if (rxFrame.FrameID == SLAVE_EMERGENCY_ADDRESS) { + AMSErrorHandle errorframe = {0}; + errorframe.errorcode = SlavesErrorFrameError; + errorframe.errorarg[0] = rxFrame.data[0]; + errorframe.errorarg[1] = rxFrame.data[1]; + errorframe.errorarg[2] = rxFrame.data[2]; + errorframe.errorarg[3] = rxFrame.data[3]; + errorframe.errorarg[4] = rxFrame.data[4]; + errorframe.errorarg[5] = rxFrame.data[5]; + errorframe.errorarg[6] = rxFrame.data[6]; + errorframe.errorarg[7] = rxFrame.data[7]; + + AMS_Error_Handler(errorframe); } - - /* if(rxFrame.FrameID == SLAVE_EMERGENCY_ADDRESS) - { - AMSErrorHandle errorframe = {0}; - errorframe.errorcode = SlavesErrorFrameError; - errorframe.errorarg[0] = rxFrame.data[0]; - errorframe.errorarg[1] = rxFrame.data[1]; - errorframe.errorarg[2] = rxFrame.data[2]; - errorframe.errorarg[3] = rxFrame.data[3]; - errorframe.errorarg[4] = rxFrame.data[4]; - errorframe.errorarg[5] = rxFrame.data[5]; - errorframe.errorarg[6] = rxFrame.data[6]; - errorframe.errorarg[7] = rxFrame.data[7]; - - AMS_Error_Handler(errorframe); - }*/ } return 0; diff --git a/Core/Src/Error_Check.c b/Core/Src/Error_Check.c index 8269d27..0720708 100644 --- a/Core/Src/Error_Check.c +++ b/Core/Src/Error_Check.c @@ -9,24 +9,5 @@ ErrorFlags CheckErrorFlags() { ErrorFlags errors = {0}; - errors.IMD_ERROR = !HAL_GPIO_ReadPin(IMD_Error_GPIO_Port, IMD_Error_Pin); - errors.IMD_ERROR_LED = - HAL_GPIO_ReadPin(IMD_Error_LED_GPIO_Port, IMD_Error_LED_Pin); - errors.AMS_ERROR_LED = - HAL_GPIO_ReadPin(AMS_ERROR_GPIO_Port, AMS_Error_LED_Pin); - - errors.TS_no_voltage_error = - HAL_GPIO_ReadPin(Volt_Error_CPU_GPIO_Port, Volt_Error_CPU_Pin); - errors.positive_AIR_or_PC_error = HAL_GPIO_ReadPin( - Positive_Side_Error_CPU_GPIO_Port, Positive_Side_Error_CPU_Pin); - errors.negative_AIR_error = - HAL_GPIO_ReadPin(Neg_Side_Error_CPU_GPIO_Port, Neg_Side_Error_CPU_Pin); - - errors.HV_inactive = - HAL_GPIO_ReadPin(HV_Inactive_CPU_GPIO_Port, HV_Inactive_CPU_Pin); - errors.negative_AIR_open = - HAL_GPIO_ReadPin(Neg_AIR_Open_CPU_GPIO_Port, Neg_AIR_Open_CPU_Pin); - errors.positive_AIR_and_PC_open = - HAL_GPIO_ReadPin(High_Side_Open_CPU_GPIO_Port, High_Side_Open_CPU_Pin); return errors; } diff --git a/Core/Src/SPI_Slave_Communication.c b/Core/Src/SPI_Slave_Communication.c index a994778..96019f5 100644 --- a/Core/Src/SPI_Slave_Communication.c +++ b/Core/Src/SPI_Slave_Communication.c @@ -15,7 +15,6 @@ #include - #define SPI_BUFFER_SIZE 1024 #define DUMMYBYTES 2 @@ -313,26 +312,16 @@ void InterSTMFrame() { spitxbuf[tsstatebaseaddress + 0] = spi_airstates->currentTSState; spitxbuf[tsstatebaseaddress + 1] = (uint8_t)(spi_airstates->targetTSState); - spitxbuf[tsstatebaseaddress + 2] = - (uint8_t)(spi_airstates->RelaisSupplyVoltage >> 8) & 0xFF; - spitxbuf[tsstatebaseaddress + 3] = - (uint8_t)(spi_airstates->RelaisSupplyVoltage & 0xFF); - spitxbuf[tsstatebaseaddress + 4] = - (uint8_t)((spi_airstates->ShutdownCircuitVoltage >> 8) & 0xFF); - spitxbuf[tsstatebaseaddress + 5] = - (uint8_t)(spi_airstates->ShutdownCircuitVoltage & 0xFF); - spitxbuf[tsstatebaseaddress + 6] = - (uint8_t)((spi_airstates->AIRNegativeCurrent >> 8) & 0xFF); - spitxbuf[tsstatebaseaddress + 7] = - (uint8_t)(spi_airstates->AIRNegativeCurrent & 0xFF); - spitxbuf[tsstatebaseaddress + 8] = - (uint8_t)((spi_airstates->AIRPositiveCurrent >> 8) & 0xFF); - spitxbuf[tsstatebaseaddress + 9] = - (uint8_t)((spi_airstates->AIRPositiveCurrent) & 0xFF); - spitxbuf[tsstatebaseaddress + 10] = - (uint8_t)((spi_airstates->AIRPrechargeCurrent >> 8) & 0xFF); - spitxbuf[tsstatebaseaddress + 11] = - (uint8_t)((spi_airstates->AIRPrechargeCurrent) & 0xFF); + spitxbuf[tsstatebaseaddress + 2] = (uint8_t)(0) & 0xFF; + spitxbuf[tsstatebaseaddress + 3] = (uint8_t)(0); + spitxbuf[tsstatebaseaddress + 4] = (uint8_t)((0) & 0xFF); + spitxbuf[tsstatebaseaddress + 5] = (uint8_t)(0); + spitxbuf[tsstatebaseaddress + 6] = (uint8_t)((0) & 0xFF); + spitxbuf[tsstatebaseaddress + 7] = (uint8_t)(0); + spitxbuf[tsstatebaseaddress + 8] = (uint8_t)((0) & 0xFF); + spitxbuf[tsstatebaseaddress + 9] = (uint8_t)((0) & 0xFF); + spitxbuf[tsstatebaseaddress + 10] = (uint8_t)((0) & 0xFF); + spitxbuf[tsstatebaseaddress + 11] = (uint8_t)((0) & 0xFF); spitxbuf[tsstatebaseaddress + 12] = (uint8_t)((spi_airstates->BatteryVoltageBatterySide >> 24) & 0xFF); spitxbuf[tsstatebaseaddress + 13] = diff --git a/Core/Src/main.c b/Core/Src/main.c index 9e5b616..618e016 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -46,11 +46,6 @@ /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ -ADC_HandleTypeDef hadc1; -ADC_HandleTypeDef hadc2; -DMA_HandleTypeDef hdma_adc1; -DMA_HandleTypeDef hdma_adc2; - CRC_HandleTypeDef hcrc; FDCAN_HandleTypeDef hfdcan1; @@ -64,9 +59,6 @@ SPI_HandleTypeDef hspi1; /* Private function prototypes -----------------------------------------------*/ void SystemClock_Config(void); static void MX_GPIO_Init(void); -static void MX_DMA_Init(void); -static void MX_ADC1_Init(void); -static void MX_ADC2_Init(void); static void MX_FDCAN1_Init(void); static void MX_SPI1_Init(void); static void MX_CRC_Init(void); @@ -110,15 +102,12 @@ int main(void) { /* Initialize all configured peripherals */ MX_GPIO_Init(); - MX_DMA_Init(); - MX_ADC1_Init(); - MX_ADC2_Init(); MX_FDCAN1_Init(); MX_SPI1_Init(); MX_CRC_Init(); /* USER CODE BEGIN 2 */ - airstates = init_AIR_State_Maschine(&hadc1, &hadc2, &hdma_adc1, &hdma_adc2); + airstates = init_AIR_State_Maschine(); initSlaves(); set_SPI_errorInfo(&defaulterrorhandle); spi_communication_init(&hspi1, &airstates); @@ -173,7 +162,7 @@ void SystemClock_Config(void) { RCC_OscInitStruct.PLL.PLLN = 8; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV8; - RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV8; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } @@ -187,153 +176,11 @@ void SystemClock_Config(void) { RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) { Error_Handler(); } } -/** - * @brief ADC1 Initialization Function - * @param None - * @retval None - */ -static void MX_ADC1_Init(void) { - - /* USER CODE BEGIN ADC1_Init 0 */ - - /* USER CODE END ADC1_Init 0 */ - - ADC_MultiModeTypeDef multimode = {0}; - ADC_ChannelConfTypeDef sConfig = {0}; - - /* USER CODE BEGIN ADC1_Init 1 */ - - /* USER CODE END ADC1_Init 1 */ - - /** Common config - */ - hadc1.Instance = ADC1; - hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV64; - hadc1.Init.Resolution = ADC_RESOLUTION_12B; - hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; - hadc1.Init.GainCompensation = 0; - hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; - hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; - hadc1.Init.LowPowerAutoWait = DISABLE; - hadc1.Init.ContinuousConvMode = DISABLE; - hadc1.Init.NbrOfConversion = 4; - hadc1.Init.DiscontinuousConvMode = DISABLE; - hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; - hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - hadc1.Init.DMAContinuousRequests = DISABLE; - hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; - hadc1.Init.OversamplingMode = DISABLE; - if (HAL_ADC_Init(&hadc1) != HAL_OK) { - Error_Handler(); - } - - /** Configure the ADC multi-mode - */ - multimode.Mode = ADC_MODE_INDEPENDENT; - if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) { - Error_Handler(); - } - - /** Configure Regular Channel - */ - sConfig.Channel = ADC_CHANNEL_1; - sConfig.Rank = ADC_REGULAR_RANK_1; - sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5; - sConfig.SingleDiff = ADC_SINGLE_ENDED; - sConfig.OffsetNumber = ADC_OFFSET_NONE; - sConfig.Offset = 0; - if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { - Error_Handler(); - } - - /** Configure Regular Channel - */ - sConfig.Channel = ADC_CHANNEL_2; - sConfig.Rank = ADC_REGULAR_RANK_2; - if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { - Error_Handler(); - } - - /** Configure Regular Channel - */ - sConfig.Channel = ADC_CHANNEL_3; - sConfig.Rank = ADC_REGULAR_RANK_3; - if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { - Error_Handler(); - } - - /** Configure Regular Channel - */ - sConfig.Channel = ADC_CHANNEL_4; - sConfig.Rank = ADC_REGULAR_RANK_4; - if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { - Error_Handler(); - } - /* USER CODE BEGIN ADC1_Init 2 */ - - /* USER CODE END ADC1_Init 2 */ -} - -/** - * @brief ADC2 Initialization Function - * @param None - * @retval None - */ -static void MX_ADC2_Init(void) { - - /* USER CODE BEGIN ADC2_Init 0 */ - - /* USER CODE END ADC2_Init 0 */ - - ADC_ChannelConfTypeDef sConfig = {0}; - - /* USER CODE BEGIN ADC2_Init 1 */ - - /* USER CODE END ADC2_Init 1 */ - - /** Common config - */ - hadc2.Instance = ADC2; - hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV64; - hadc2.Init.Resolution = ADC_RESOLUTION_12B; - hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; - hadc2.Init.GainCompensation = 0; - hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE; - hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV; - hadc2.Init.LowPowerAutoWait = DISABLE; - hadc2.Init.ContinuousConvMode = DISABLE; - hadc2.Init.NbrOfConversion = 1; - hadc2.Init.DiscontinuousConvMode = DISABLE; - hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START; - hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - hadc2.Init.DMAContinuousRequests = DISABLE; - hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED; - hadc2.Init.OversamplingMode = DISABLE; - if (HAL_ADC_Init(&hadc2) != HAL_OK) { - Error_Handler(); - } - - /** Configure Regular Channel - */ - sConfig.Channel = ADC_CHANNEL_17; - sConfig.Rank = ADC_REGULAR_RANK_1; - sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5; - sConfig.SingleDiff = ADC_SINGLE_ENDED; - sConfig.OffsetNumber = ADC_OFFSET_NONE; - sConfig.Offset = 0; - if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) { - Error_Handler(); - } - /* USER CODE BEGIN ADC2_Init 2 */ - - /* USER CODE END ADC2_Init 2 */ -} - /** * @brief CRC Initialization Function * @param None @@ -438,25 +285,6 @@ static void MX_SPI1_Init(void) { /* USER CODE END SPI1_Init 2 */ } -/** - * Enable DMA controller clock - */ -static void MX_DMA_Init(void) { - - /* DMA controller clock enable */ - __HAL_RCC_DMAMUX1_CLK_ENABLE(); - __HAL_RCC_DMA1_CLK_ENABLE(); - __HAL_RCC_DMA2_CLK_ENABLE(); - - /* DMA interrupt init */ - /* DMA1_Channel2_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 4, 0); - HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn); - /* DMA2_Channel1_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA2_Channel1_IRQn, 4, 0); - HAL_NVIC_EnableIRQ(DMA2_Channel1_IRQn); -} - /** * @brief GPIO Initialization Function * @param None @@ -493,18 +321,11 @@ static void MX_GPIO_Init(void) { GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - /*Configure GPIO pins : AMS_ERROR_Pin IMD_Error_Pin AMS_Error_LED_Pin - Volt_Error_CPU_Pin Positive_Side_Error_CPU_Pin Neg_Side_Error_CPU_Pin - HV_Inactive_CPU_Pin Neg_AIR_Open_CPU_Pin High_Side_Open_CPU_Pin - IMD_Error_LED_Pin */ - GPIO_InitStruct.Pin = AMS_ERROR_Pin | IMD_Error_Pin | AMS_Error_LED_Pin | - Volt_Error_CPU_Pin | Positive_Side_Error_CPU_Pin | - Neg_Side_Error_CPU_Pin | HV_Inactive_CPU_Pin | - Neg_AIR_Open_CPU_Pin | High_Side_Open_CPU_Pin | - IMD_Error_LED_Pin; + /*Configure GPIO pin : AMS_ERROR_Pin */ + GPIO_InitStruct.Pin = AMS_ERROR_Pin; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + HAL_GPIO_Init(AMS_ERROR_GPIO_Port, &GPIO_InitStruct); /*Configure GPIO pin : Inter_STM_CS_Pin */ GPIO_InitStruct.Pin = Inter_STM_CS_Pin; diff --git a/Core/Src/stm32g4xx_hal_msp.c b/Core/Src/stm32g4xx_hal_msp.c index a9dfd4d..0174abc 100644 --- a/Core/Src/stm32g4xx_hal_msp.c +++ b/Core/Src/stm32g4xx_hal_msp.c @@ -24,9 +24,6 @@ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ -extern DMA_HandleTypeDef hdma_adc1; - -extern DMA_HandleTypeDef hdma_adc2; /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN TD */ @@ -96,212 +93,6 @@ void HAL_MspInit(void) /* USER CODE END MspInit 1 */ } -static uint32_t HAL_RCC_ADC12_CLK_ENABLED=0; - -/** -* @brief ADC MSP Initialization -* This function configures the hardware resources used in this example -* @param hadc: ADC handle pointer -* @retval None -*/ -void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - if(hadc->Instance==ADC1) - { - /* USER CODE BEGIN ADC1_MspInit 0 */ - - /* USER CODE END ADC1_MspInit 0 */ - - /** Initializes the peripherals clocks - */ - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12; - PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } - - /* Peripheral clock enable */ - HAL_RCC_ADC12_CLK_ENABLED++; - if(HAL_RCC_ADC12_CLK_ENABLED==1){ - __HAL_RCC_ADC12_CLK_ENABLE(); - } - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**ADC1 GPIO Configuration - PA0 ------> ADC1_IN1 - PA1 ------> ADC1_IN2 - PA2 ------> ADC1_IN3 - PA3 ------> ADC1_IN4 - */ - GPIO_InitStruct.Pin = Relay_Supply_Voltage_Pin|Pos_AIR_Current_Pin|Neg_AIR_Current_Pin|PreCharge_AIR_Current_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* ADC1 DMA Init */ - /* ADC1 Init */ - hdma_adc1.Instance = DMA1_Channel2; - hdma_adc1.Init.Request = DMA_REQUEST_ADC1; - hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; - hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; - hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; - hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; - hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; - hdma_adc1.Init.Mode = DMA_NORMAL; - hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; - if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) - { - Error_Handler(); - } - - __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); - - /* ADC1 interrupt Init */ - HAL_NVIC_SetPriority(ADC1_2_IRQn, 4, 0); - HAL_NVIC_EnableIRQ(ADC1_2_IRQn); - /* USER CODE BEGIN ADC1_MspInit 1 */ - - /* USER CODE END ADC1_MspInit 1 */ - } - else if(hadc->Instance==ADC2) - { - /* USER CODE BEGIN ADC2_MspInit 0 */ - - /* USER CODE END ADC2_MspInit 0 */ - - /** Initializes the peripherals clocks - */ - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12; - PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } - - /* Peripheral clock enable */ - HAL_RCC_ADC12_CLK_ENABLED++; - if(HAL_RCC_ADC12_CLK_ENABLED==1){ - __HAL_RCC_ADC12_CLK_ENABLE(); - } - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**ADC2 GPIO Configuration - PA4 ------> ADC2_IN17 - */ - GPIO_InitStruct.Pin = SC_Supply_Voltage_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(SC_Supply_Voltage_GPIO_Port, &GPIO_InitStruct); - - /* ADC2 DMA Init */ - /* ADC2 Init */ - hdma_adc2.Instance = DMA2_Channel1; - hdma_adc2.Init.Request = DMA_REQUEST_ADC2; - hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY; - hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE; - hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; - hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; - hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; - hdma_adc2.Init.Mode = DMA_NORMAL; - hdma_adc2.Init.Priority = DMA_PRIORITY_LOW; - if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) - { - Error_Handler(); - } - - __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2); - - /* ADC2 interrupt Init */ - HAL_NVIC_SetPriority(ADC1_2_IRQn, 4, 0); - HAL_NVIC_EnableIRQ(ADC1_2_IRQn); - /* USER CODE BEGIN ADC2_MspInit 1 */ - - /* USER CODE END ADC2_MspInit 1 */ - } - -} - -/** -* @brief ADC MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hadc: ADC handle pointer -* @retval None -*/ -void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) -{ - if(hadc->Instance==ADC1) - { - /* USER CODE BEGIN ADC1_MspDeInit 0 */ - - /* USER CODE END ADC1_MspDeInit 0 */ - /* Peripheral clock disable */ - HAL_RCC_ADC12_CLK_ENABLED--; - if(HAL_RCC_ADC12_CLK_ENABLED==0){ - __HAL_RCC_ADC12_CLK_DISABLE(); - } - - /**ADC1 GPIO Configuration - PA0 ------> ADC1_IN1 - PA1 ------> ADC1_IN2 - PA2 ------> ADC1_IN3 - PA3 ------> ADC1_IN4 - */ - HAL_GPIO_DeInit(GPIOA, Relay_Supply_Voltage_Pin|Pos_AIR_Current_Pin|Neg_AIR_Current_Pin|PreCharge_AIR_Current_Pin); - - /* ADC1 DMA DeInit */ - HAL_DMA_DeInit(hadc->DMA_Handle); - - /* ADC1 interrupt DeInit */ - /* USER CODE BEGIN ADC1:ADC1_2_IRQn disable */ - /** - * Uncomment the line below to disable the "ADC1_2_IRQn" interrupt - * Be aware, disabling shared interrupt may affect other IPs - */ - /* HAL_NVIC_DisableIRQ(ADC1_2_IRQn); */ - /* USER CODE END ADC1:ADC1_2_IRQn disable */ - - /* USER CODE BEGIN ADC1_MspDeInit 1 */ - - /* USER CODE END ADC1_MspDeInit 1 */ - } - else if(hadc->Instance==ADC2) - { - /* USER CODE BEGIN ADC2_MspDeInit 0 */ - - /* USER CODE END ADC2_MspDeInit 0 */ - /* Peripheral clock disable */ - HAL_RCC_ADC12_CLK_ENABLED--; - if(HAL_RCC_ADC12_CLK_ENABLED==0){ - __HAL_RCC_ADC12_CLK_DISABLE(); - } - - /**ADC2 GPIO Configuration - PA4 ------> ADC2_IN17 - */ - HAL_GPIO_DeInit(SC_Supply_Voltage_GPIO_Port, SC_Supply_Voltage_Pin); - - /* ADC2 DMA DeInit */ - HAL_DMA_DeInit(hadc->DMA_Handle); - - /* ADC2 interrupt DeInit */ - /* USER CODE BEGIN ADC2:ADC1_2_IRQn disable */ - /** - * Uncomment the line below to disable the "ADC1_2_IRQn" interrupt - * Be aware, disabling shared interrupt may affect other IPs - */ - /* HAL_NVIC_DisableIRQ(ADC1_2_IRQn); */ - /* USER CODE END ADC2:ADC1_2_IRQn disable */ - - /* USER CODE BEGIN ADC2_MspDeInit 1 */ - - /* USER CODE END ADC2_MspDeInit 1 */ - } - -} - /** * @brief CRC MSP Initialization * This function configures the hardware resources used in this example diff --git a/Core/Src/stm32g4xx_it.c b/Core/Src/stm32g4xx_it.c index 4d18eef..ae27c25 100644 --- a/Core/Src/stm32g4xx_it.c +++ b/Core/Src/stm32g4xx_it.c @@ -57,10 +57,6 @@ /* USER CODE END 0 */ /* External variables --------------------------------------------------------*/ -extern DMA_HandleTypeDef hdma_adc1; -extern DMA_HandleTypeDef hdma_adc2; -extern ADC_HandleTypeDef hadc1; -extern ADC_HandleTypeDef hadc2; extern FDCAN_HandleTypeDef hfdcan1; extern SPI_HandleTypeDef hspi1; /* USER CODE BEGIN EV */ @@ -211,35 +207,6 @@ void SysTick_Handler(void) /* please refer to the startup file (startup_stm32g4xx.s). */ /******************************************************************************/ -/** - * @brief This function handles DMA1 channel2 global interrupt. - */ -void DMA1_Channel2_IRQHandler(void) -{ - /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */ - - /* USER CODE END DMA1_Channel2_IRQn 0 */ - HAL_DMA_IRQHandler(&hdma_adc1); - /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */ - - /* USER CODE END DMA1_Channel2_IRQn 1 */ -} - -/** - * @brief This function handles ADC1 and ADC2 global interrupt. - */ -void ADC1_2_IRQHandler(void) -{ - /* USER CODE BEGIN ADC1_2_IRQn 0 */ - - /* USER CODE END ADC1_2_IRQn 0 */ - HAL_ADC_IRQHandler(&hadc1); - HAL_ADC_IRQHandler(&hadc2); - /* USER CODE BEGIN ADC1_2_IRQn 1 */ - - /* USER CODE END ADC1_2_IRQn 1 */ -} - /** * @brief This function handles FDCAN1 interrupt 0. */ @@ -282,20 +249,6 @@ void SPI1_IRQHandler(void) /* USER CODE END SPI1_IRQn 1 */ } -/** - * @brief This function handles DMA2 channel1 global interrupt. - */ -void DMA2_Channel1_IRQHandler(void) -{ - /* USER CODE BEGIN DMA2_Channel1_IRQn 0 */ - - /* USER CODE END DMA2_Channel1_IRQn 0 */ - HAL_DMA_IRQHandler(&hdma_adc2); - /* USER CODE BEGIN DMA2_Channel1_IRQn 1 */ - - /* USER CODE END DMA2_Channel1_IRQn 1 */ -} - /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h b/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h deleted file mode 100644 index f0114a3..0000000 --- a/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h +++ /dev/null @@ -1,2034 +0,0 @@ -/** - ****************************************************************************** - * @file stm32g4xx_hal_adc.h - * @author MCD Application Team - * @brief Header file of ADC HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2019 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32G4xx_HAL_ADC_H -#define STM32G4xx_HAL_ADC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32g4xx_hal_def.h" - -/* Include low level driver */ -#include "stm32g4xx_ll_adc.h" - -/** @addtogroup STM32G4xx_HAL_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup ADC_Exported_Types ADC Exported Types - * @{ - */ - -/** - * @brief ADC group regular oversampling structure definition - */ -typedef struct -{ - uint32_t Ratio; /*!< Configures the oversampling ratio. - This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ - - uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. - This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ - - uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. - This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ - - uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. - The oversampling is either temporary stopped or reset upon an injected - sequence interruption. - If oversampling is enabled on both regular and injected groups, this parameter - is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" - (the oversampling buffer is zeroed during injection sequence). - This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ - -} ADC_OversamplingTypeDef; - -/** - * @brief Structure definition of ADC instance and ADC group regular. - * @note Parameters of this structure are shared within 2 scopes: - * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, - * GainCompensation, ScanConvMode, EOCSelection, LowPowerAutoWait. - * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, - * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling, SamplingMode. - * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. - * ADC state can be either: - * - For all parameters: ADC disabled - * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular. - * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected. - * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed - * without error reporting (as it can be the expected behavior in case of intended action to update another parameter - * (which fulfills the ADC state condition) on the fly). - */ -typedef struct -{ - uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. - This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. - Note: The ADC clock configuration is common to all ADC instances. - Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, - AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. - Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only - if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC - must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. - Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. - Note: This parameter can be modified only if all ADC instances are disabled. */ - - uint32_t Resolution; /*!< Configure the ADC resolution. - This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ - - uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). - Refer to reference manual for alignments formats versus resolutions. - This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ - - uint32_t GainCompensation; /*!< Specify the ADC gain compensation coefficient to be applied to ADC raw conversion data, based on following formula: - DATA = DATA(raw) * (gain compensation coef) / 4096 - 2.12 bit format, unsigned: 2 bits exponents / 12 bits mantissa - Gain step is 1/4096 = 0.000244 - Gain range is 0.0000 to 3.999756 - This parameter value can be - 0 Gain compensation will be disabled and coefficient set to 0 - 1 -> 0x3FFF Gain compensation will be enabled and coefficient set to specified value - - Note: Gain compensation when enabled is applied to all channels. */ - - uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. - This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. - If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). - Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). - If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer). - Scan direction is upward: from rank 1 to rank 'n'. - This parameter can be a value of @ref ADC_Scan_mode */ - - uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. - This parameter can be a value of @ref ADC_EOCSelection. */ - - FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous - conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software, - using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). - This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun - for low frequency applications. - This parameter can be set to ENABLE or DISABLE. - Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). - Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). - Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: - use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. - (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ - - FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, - after the first ADC conversion start trigger occurred (software start or external trigger). - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. - To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. - This parameter must be a number between Min_Data = 1 and Max_Data = 16. - Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without - continuous mode or external trigger that could launch a conversion). */ - - FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence - (main sequence subdivided in successive parts). - Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. - Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided. - If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. - This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ - - uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. - If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. - This parameter can be a value of @ref ADC_regular_external_trigger_source. - Caution: external trigger source is common to all ADC instances. */ - - uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. - If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. - This parameter can be a value of @ref ADC_regular_external_trigger_edge */ - - uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group regular conversion. - This parameter can be a value of @ref ADC_regular_sampling_mode */ - - FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) - or in continuous mode (DMA transfer unlimited, whatever number of conversions). - This parameter can be set to ENABLE or DISABLE. - Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */ - - uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). - This parameter applies to ADC group regular only. - This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. - Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear - end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function - HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). - Note: Error reporting with respect to the conversion mode: - - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data - overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. - - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ - - FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. - This parameter can be set to ENABLE or DISABLE. - Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */ - - ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. - Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ - -} ADC_InitTypeDef; - -/** - * @brief Structure definition of ADC channel for regular group - * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. - * ADC state can be either: - * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') - * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group. - * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. - * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed - * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) - * on the fly). - */ -typedef struct -{ - uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. - This parameter can be a value of @ref ADC_HAL_EC_CHANNEL - Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ - - uint32_t Rank; /*!< Specify the rank in the regular group sequencer. - This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS - Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by - the new channel setting (or parameter number of conversions adjusted) */ - - uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. - Unit: ADC clock cycles - Conversion time is the addition of sampling time and processing time - (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). - This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME - Caution: This parameter applies to a channel that can be used into regular and/or injected group. - It overwrites the last setting. - Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), - sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) - Refer to device datasheet for timings values. */ - - uint32_t SingleDiff; /*!< Select single-ended or differential input. - In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). - Only channel 'i' has to be configured, channel 'i+1' is configured automatically. - This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING - Caution: This parameter applies to a channel that can be used in a regular and/or injected group. - It overwrites the last setting. - Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. - Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. - Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). - If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case - of another parameter update on the fly) */ - - uint32_t OffsetNumber; /*!< Select the offset number - This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB - Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ - - uint32_t Offset; /*!< Define the offset to be applied on the raw converted data. - Offset value must be a positive number. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, - 0x3FF, 0xFF or 0x3F respectively. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled - without continuous mode or external trigger that could launch a conversion). */ - - uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. - This parameter can be a value of @ref ADCEx_OffsetSign. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled - without continuous mode or external trigger that could launch a conversion). */ - FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. - This parameter value can be ENABLE or DISABLE. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled - without continuous mode or external trigger that could launch a conversion). */ - -} ADC_ChannelConfTypeDef; - -/** - * @brief Structure definition of ADC analog watchdog - * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. - * ADC state can be either: - * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected. - * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular and injected groups. - */ -typedef struct -{ - uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. - For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') - For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) - This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ - - uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. - For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected. - For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. - This parameter can be a value of @ref ADC_analog_watchdog_mode. */ - - uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. - For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). - For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). - This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ - - FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. - This parameter can be set to ENABLE or DISABLE */ - - uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number - between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. - Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits - the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. - Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are - impacted: the comparison of analog watchdog thresholds is done on - oversampling final computation (after ratio and shift application): - ADC data register bitfield [15:4] (12 most significant bits). */ - - uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number - between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. - Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits - the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. - Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are - impacted: the comparison of analog watchdog thresholds is done on - oversampling final computation (after ratio and shift application): - ADC data register bitfield [15:4] (12 most significant bits). */ - - uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider. - Before setting flag or raising interrupt, analog watchdog can wait to have several - consecutive out-of-window samples. This parameter allows to configure this number. - This parameter only applies to Analog watchdog 1. For others, use value ADC_AWD_FILTERING_NONE. - This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */ -} ADC_AnalogWDGConfTypeDef; - -/** - * @brief ADC group injected contexts queue configuration - * @note Structure intended to be used only through structure "ADC_HandleTypeDef" - */ -typedef struct -{ - uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each - HAL_ADCEx_InjectedConfigChannel() call to finally initialize - JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ - - uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ -} ADC_InjectionConfigTypeDef; - -/** @defgroup ADC_States ADC States - * @{ - */ - -/** - * @brief HAL ADC state machine: ADC states definition (bitfields) - * @note ADC state machine is managed by bitfields, state must be compared - * with bit by bit. - * For example: - * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " - * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " - */ -/* States of ADC global scope */ -#define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ -#define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ -#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */ -#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ - -/* States of ADC errors */ -#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ -#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ -#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ - -/* States of ADC group regular */ -#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, - external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ -#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ -#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ -#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */ - -/* States of ADC group injected */ -#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, - external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ -#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ -#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ - -/* States of ADC analog watchdogs */ -#define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ -#define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ -#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ - -/* States of ADC multi-mode */ -#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ - -/** - * @} - */ - -/** - * @brief ADC handle Structure definition - */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -typedef struct __ADC_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -{ - ADC_TypeDef *Instance; /*!< Register base address */ - ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ - DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ - HAL_LockTypeDef Lock; /*!< ADC locking object */ - __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ - __IO uint32_t ErrorCode; /*!< ADC Error code */ - ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ - void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ - void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ - void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ - void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ - void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */ - void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ - void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ - void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ - void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ - void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -} ADC_HandleTypeDef; - -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -/** - * @brief HAL ADC Callback ID enumeration definition - */ -typedef enum -{ - HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ - HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ - HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ - HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ - HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ - HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ - HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ - HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ - HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ - HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ - HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ -} HAL_ADC_CallbackIDTypeDef; - -/** - * @brief HAL ADC Callback pointer definition - */ -typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ - -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - -/** - * @} - */ - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Constants ADC Exported Constants - * @{ - */ - -/** @defgroup ADC_Error_Code ADC Error Code - * @{ - */ -#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ -#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, - enable/disable, erroneous state, ...) */ -#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ -#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ -#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source - * @{ - */ -#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */ -#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ -#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ - -#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */ -#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */ -#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */ -#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */ -#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */ -#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */ -#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */ -#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */ -#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */ -#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ -#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ -#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution - * @{ - */ -#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ -#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ -#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ -#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment - * @{ - */ -#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ -#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ -/** - * @} - */ - -/** @defgroup ADC_Scan_mode ADC sequencer scan mode - * @{ - */ -#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ -#define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ -/** - * @} - */ - -/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source - * @{ - */ -/* ADC group regular trigger sources for all ADC instances */ -#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ -#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T2_CC1 (LL_ADC_REG_TRIG_EXT_TIM2_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T3_CC1 (LL_ADC_REG_TRIG_EXT_TIM3_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T4_CC1 (LL_ADC_REG_TRIG_EXT_TIM4_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T7_TRGO (LL_ADC_REG_TRIG_EXT_TIM7_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T8_CC1 (LL_ADC_REG_TRIG_EXT_TIM8_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T20_TRGO (LL_ADC_REG_TRIG_EXT_TIM20_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T20_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T20_CC1 (LL_ADC_REG_TRIG_EXT_TIM20_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T20_CC2 (LL_ADC_REG_TRIG_EXT_TIM20_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T20_CC3 (LL_ADC_REG_TRIG_EXT_TIM20_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_HRTIM_TRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_HRTIM_TRG2 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG2) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_HRTIM_TRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_HRTIM_TRG4 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG4) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_HRTIM_TRG5 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG5) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_HRTIM_TRG6 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG6) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_HRTIM_TRG7 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG7) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_HRTIM_TRG8 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG8) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_HRTIM_TRG9 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG9) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_HRTIM_TRG10 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG10) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_EXT_IT2 (LL_ADC_REG_TRIG_EXT_EXTI_LINE2) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 2. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_LPTIM_OUT (LL_ADC_REG_TRIG_EXT_LPTIM_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */ -/** - * @} - */ - -/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) - * @{ - */ -#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */ -#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */ -#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */ -#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ -/** - * @} - */ - -/** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode - * @{ - */ -#define ADC_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */ -#define ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event. - Note: First conversion is using minimal sampling time (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) */ -#define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events: - Trigger rising edge = start sampling - Trigger falling edge = stop sampling and start conversion */ -/** - * @} - */ - -/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions - * @{ - */ -#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ -#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data - * @{ - */ -#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */ -#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks - * @{ - */ -#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ -#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ -#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ -#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ -#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ -#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ -#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ -#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ -#define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ -#define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ -#define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ -#define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ -#define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ -#define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ -#define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ -#define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time - * @{ - */ -#define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */ -#define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */ -#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ -#define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */ -#define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */ -#define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */ -#define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */ -#define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */ -#define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number - * @{ - */ -/* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ -/* all ADC instances (refer to Reference Manual). */ -#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ -#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ -#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ -#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ -#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ -#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ -#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ -#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ -#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ -#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ -#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ -#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ -#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ -#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ -#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ -#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ -#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ -#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ -#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ -#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 series, ADC channel available on all instances but ADC2. */ -#define ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_TEMPSENSOR_ADC1) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC1 instance. */ -#define ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_TEMPSENSOR_ADC5) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */ -#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 series, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */ -#define ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_VOPAMP1) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 series, ADC channel available only on ADC1 instance. */ -#define ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_VOPAMP2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 series, ADC channel available only on ADC2 instance. */ -#define ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_VOPAMP3_ADC2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC2 instance. */ -#define ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_VOPAMP3_ADC3) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */ -#define ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_VOPAMP4) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */ -#define ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_VOPAMP5) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */ -#define ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_VOPAMP6) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 series, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 availability */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number - * @{ - */ -#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ -#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ -#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ -/** - * @} - */ - -/** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration - * @{ - */ -#define ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_2SAMPLES ((ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_3SAMPLES ((ADC_TR1_AWDFILT_1)) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_4SAMPLES ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_5SAMPLES ((ADC_TR1_AWDFILT_2)) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_6SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_7SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1)) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_8SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */ -/** - * @} - */ - -/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode - * @{ - */ -#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ -#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ -#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */ -#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */ -#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ -#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */ -#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio - * @{ - */ -#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift - * @{ - */ -#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ -#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode - * @{ - */ -#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ -#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular - * @{ - */ -#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */ -#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */ -/** - * @} - */ - -/** @defgroup ADC_Event_type ADC Event type - * @{ - */ -#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ -#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ -#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ -#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ -#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ -#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ -/** - * @} - */ -#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ - -/** @defgroup ADC_interrupts_definition ADC interrupts definition - * @{ - */ -#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ -#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ -#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ -#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ -#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ -#define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ -#define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ -#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ -#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ -#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ -#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ - -#define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ - -/** - * @} - */ - -/** @defgroup ADC_flags_definition ADC flags definition - * @{ - */ -#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ -#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ -#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ -#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ -#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ -#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ -#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ -#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ -#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ -#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ -#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ - -/** - * @} - */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ - -/** @defgroup ADC_Private_Macros ADC Private Macros - * @{ - */ -/* Macro reserved for internal HAL driver usage, not intended to be used in */ -/* code of final user. */ - -/** - * @brief Return resolution bits in CFGR register RES[1:0] field. - * @param __HANDLE__ ADC handle - * @retval Value of bitfield RES in CFGR register. - */ -#define ADC_GET_RESOLUTION(__HANDLE__) \ - (LL_ADC_GetResolution((__HANDLE__)->Instance)) - -/** - * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). - * @param __HANDLE__ ADC handle - * @retval None - */ -#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) - -/** - * @brief Simultaneously clear and set specific bits of the handle State. - * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), - * the first parameter is the ADC handle State, the second parameter is the - * bit field to clear, the third and last parameter is the bit field to set. - * @retval None - */ -#define ADC_STATE_CLR_SET MODIFY_REG - -/** - * @brief Verify that a given value is aligned with the ADC resolution range. - * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). - * @param __ADC_VALUE__ value checked against the resolution. - * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) - */ -#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ - ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) - -/** - * @brief Verify the length of the scheduled regular conversions group. - * @param __LENGTH__ number of programmed conversions. - * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) - */ -#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) - - -/** - * @brief Verify the number of scheduled regular conversions in discontinuous mode. - * @param NUMBER number of scheduled regular conversions in discontinuous mode. - * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large) - */ -#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) - - -/** - * @brief Verify the ADC clock setting. - * @param __ADC_CLOCK__ programmed ADC clock. - * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) - */ -#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ - ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ - ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ - ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \ - ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \ - ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \ - ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \ - ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \ - ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \ - ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \ - ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \ - ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ - ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ - ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ - ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) - -/** - * @brief Verify the ADC resolution setting. - * @param __RESOLUTION__ programmed ADC resolution. - * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) - */ -#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ - ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ - ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ - ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) - -/** - * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. - * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. - * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) - */ -#define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ - ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) - -/** - * @brief Verify the ADC converted data alignment. - * @param __ALIGN__ programmed ADC converted data alignment. - * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) - */ -#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ - ((__ALIGN__) == ADC_DATAALIGN_LEFT) ) - -/** - * @brief Verify the ADC gain compensation. - * @param __GAIN_COMPENSATION__ programmed ADC gain compensation coefficient. - * @retval SET (__GAIN_COMPENSATION__ is a valid value) or RESET (__GAIN_COMPENSATION__ is invalid) - */ -#define IS_ADC_GAIN_COMPENSATION(__GAIN_COMPENSATION__) ((__GAIN_COMPENSATION__) <= 16393UL) - -/** - * @brief Verify the ADC scan mode. - * @param __SCAN_MODE__ programmed ADC scan mode. - * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) - */ -#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ - ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) - -/** - * @brief Verify the ADC edge trigger setting for regular group. - * @param __EDGE__ programmed ADC edge trigger setting. - * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) - */ -#define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ - ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ - ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ - ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) - -/** - * @brief Verify the ADC regular conversions external trigger. - * @param __HANDLE__ ADC handle - * @param __REGTRIG__ programmed ADC regular conversions external trigger. - * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) - */ -#if defined(STM32G474xx) || defined(STM32G484xx) -#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG5) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG6) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG7) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG8) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG9) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG10) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ - ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ - (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ - ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ - (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ - ((__REGTRIG__) == ADC_SOFTWARE_START) ) -#elif defined(STM32G473xx) || defined(STM32G483xx) -#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ - ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ - (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ - ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ - (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ - ((__REGTRIG__) == ADC_SOFTWARE_START) ) -#elif defined(STM32G471xx) -#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ - ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ - (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ - ((((__HANDLE__)->Instance == ADC3)) && \ - (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ - ((__REGTRIG__) == ADC_SOFTWARE_START) ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) -#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ - ((__REGTRIG__) == ADC_SOFTWARE_START) ) -#elif defined(STM32G491xx) || defined(STM32G4A1xx) -#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ - ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ - (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ - (((__HANDLE__)->Instance == ADC3) && \ - (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ - ((__REGTRIG__) == ADC_SOFTWARE_START) ) -#endif - -/** - * @brief Verify the ADC regular conversions external trigger. - * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger. - * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid) - */ -#define IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL) || \ - ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB) || \ - ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED) ) - -/** - * @brief Verify the ADC regular conversions check for converted data availability. - * @param __EOC_SELECTION__ converted data availability check. - * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) - */ -#define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ - ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) - -/** - * @brief Verify the ADC regular conversions overrun handling. - * @param __OVR__ ADC regular conversions overrun handling. - * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) - */ -#define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ - ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) - -/** - * @brief Verify the ADC conversions sampling time. - * @param __TIME__ ADC conversions sampling time. - * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) - */ -#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ - ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \ - ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ - ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ - ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \ - ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \ - ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ - ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ - ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) - -/** - * @brief Verify the ADC regular channel setting. - * @param __CHANNEL__ programmed ADC regular channel. - * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) - */ -#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ - ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) - -/** - * @} - */ - - -/* Private constants ---------------------------------------------------------*/ - -/** @defgroup ADC_Private_Constants ADC Private Constants - * @{ - */ - -/* Fixed timeout values for ADC conversion (including sampling time) */ -/* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */ -/* Maximum conversion time is 12.5 + Maximum sampling time */ -/* or 12.5 + 640.5 = 653 ADC clock cycles */ -/* Minimum ADC Clock frequency is 0.14 MHz */ -/* Maximum conversion time is */ -/* 653 / 0.14 MHz = 4.66 ms */ -#define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ - -/* Delay for temperature sensor stabilization time. */ -/* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ -/* Unit: us */ -#define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Macros ADC Exported Macros - * @{ - */ -/* Macro for internal HAL driver usage, and possibly can be used into code of */ -/* final user. */ - -/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. - * @{ - */ - -/** @brief Reset ADC handle state. - * @param __HANDLE__ ADC handle - * @retval None - */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ - do{ \ - (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ - ((__HANDLE__)->State = HAL_ADC_STATE_RESET) -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - -/** - * @brief Enable ADC interrupt. - * @param __HANDLE__ ADC handle - * @param __INTERRUPT__ ADC Interrupt - * This parameter can be one of the following values: - * @arg @ref ADC_IT_RDY ADC Ready interrupt source - * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source - * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source - * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source - * @arg @ref ADC_IT_OVR ADC overrun interrupt source - * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source - * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source - * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) - * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. - * @retval None - */ -#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ - (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) - -/** - * @brief Disable ADC interrupt. - * @param __HANDLE__ ADC handle - * @param __INTERRUPT__ ADC Interrupt - * This parameter can be one of the following values: - * @arg @ref ADC_IT_RDY ADC Ready interrupt source - * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source - * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source - * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source - * @arg @ref ADC_IT_OVR ADC overrun interrupt source - * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source - * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source - * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) - * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. - * @retval None - */ -#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ - (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) - -/** @brief Checks if the specified ADC interrupt source is enabled or disabled. - * @param __HANDLE__ ADC handle - * @param __INTERRUPT__ ADC interrupt source to check - * This parameter can be one of the following values: - * @arg @ref ADC_IT_RDY ADC Ready interrupt source - * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source - * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source - * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source - * @arg @ref ADC_IT_OVR ADC overrun interrupt source - * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source - * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source - * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) - * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. - * @retval State of interruption (SET or RESET) - */ -#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ - (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) - -/** - * @brief Check whether the specified ADC flag is set or not. - * @param __HANDLE__ ADC handle - * @param __FLAG__ ADC flag - * This parameter can be one of the following values: - * @arg @ref ADC_FLAG_RDY ADC Ready flag - * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag - * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag - * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag - * @arg @ref ADC_FLAG_OVR ADC overrun flag - * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag - * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag - * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) - * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. - * @retval State of flag (TRUE or FALSE). - */ -#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ - ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear the specified ADC flag. - * @param __HANDLE__ ADC handle - * @param __FLAG__ ADC flag - * This parameter can be one of the following values: - * @arg @ref ADC_FLAG_RDY ADC Ready flag - * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag - * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag - * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag - * @arg @ref ADC_FLAG_OVR ADC overrun flag - * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag - * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag - * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) - * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. - * @retval None - */ -/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ -#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ - (((__HANDLE__)->Instance->ISR) = (__FLAG__)) - -/** - * @} - */ - -/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro - * @{ - */ - -/** - * @brief Helper macro to get ADC channel number in decimal format - * from literals ADC_CHANNEL_x. - * @note Example: - * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) - * will return decimal number "4". - * @note The input can be a value from functions where a channel - * number is returned, either defined with number - * or with bitfield (only one bit must be set). - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 (8) - * @arg @ref ADC_CHANNEL_2 (8) - * @arg @ref ADC_CHANNEL_3 (8) - * @arg @ref ADC_CHANNEL_4 (8) - * @arg @ref ADC_CHANNEL_5 (8) - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 - * @arg @ref ADC_CHANNEL_9 - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 - * @arg @ref ADC_CHANNEL_16 - * @arg @ref ADC_CHANNEL_17 - * @arg @ref ADC_CHANNEL_18 - * @arg @ref ADC_CHANNEL_VREFINT (7) - * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref ADC_CHANNEL_VBAT (6) - * @arg @ref ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * @retval Value between Min_Data=0 and Max_Data=18 - */ -#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ - __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) - -/** - * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x - * from number in decimal format. - * @note Example: - * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) - * will return a data equivalent to "ADC_CHANNEL_4". - * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 - * @retval Returned value can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 (8) - * @arg @ref ADC_CHANNEL_2 (8) - * @arg @ref ADC_CHANNEL_3 (8) - * @arg @ref ADC_CHANNEL_4 (8) - * @arg @ref ADC_CHANNEL_5 (8) - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 - * @arg @ref ADC_CHANNEL_9 - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 - * @arg @ref ADC_CHANNEL_16 - * @arg @ref ADC_CHANNEL_17 - * @arg @ref ADC_CHANNEL_18 - * @arg @ref ADC_CHANNEL_VREFINT (7) - * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref ADC_CHANNEL_VBAT (6) - * @arg @ref ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - */ -#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) - -/** - * @brief Helper macro to determine whether the selected channel - * corresponds to literal definitions of driver. - * @note The different literal definitions of ADC channels are: - * - ADC internal channel: - * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... - * - ADC external channel (channel connected to a GPIO pin): - * ADC_CHANNEL_1, ADC_CHANNEL_2, ... - * @note The channel parameter must be a value defined from literal - * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, - * ADC_CHANNEL_TEMPSENSOR, ...), - * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), - * must not be a value from functions where a channel number is - * returned from ADC registers, - * because internal and external channels share the same channel - * number in ADC registers. The differentiation is made only with - * parameters definitions of driver. - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 (8) - * @arg @ref ADC_CHANNEL_2 (8) - * @arg @ref ADC_CHANNEL_3 (8) - * @arg @ref ADC_CHANNEL_4 (8) - * @arg @ref ADC_CHANNEL_5 (8) - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 - * @arg @ref ADC_CHANNEL_9 - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 - * @arg @ref ADC_CHANNEL_16 - * @arg @ref ADC_CHANNEL_17 - * @arg @ref ADC_CHANNEL_18 - * @arg @ref ADC_CHANNEL_VREFINT (7) - * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref ADC_CHANNEL_VBAT (6) - * @arg @ref ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). - * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. - */ -#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ - __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) - -/** - * @brief Helper macro to convert a channel defined from parameter - * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, - * ADC_CHANNEL_TEMPSENSOR, ...), - * to its equivalent parameter definition of a ADC external channel - * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). - * @note The channel parameter can be, additionally to a value - * defined from parameter definition of a ADC internal channel - * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), - * a value defined from parameter definition of - * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) - * or a value from functions where a channel number is returned - * from ADC registers. - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 (8) - * @arg @ref ADC_CHANNEL_2 (8) - * @arg @ref ADC_CHANNEL_3 (8) - * @arg @ref ADC_CHANNEL_4 (8) - * @arg @ref ADC_CHANNEL_5 (8) - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 - * @arg @ref ADC_CHANNEL_9 - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 - * @arg @ref ADC_CHANNEL_16 - * @arg @ref ADC_CHANNEL_17 - * @arg @ref ADC_CHANNEL_18 - * @arg @ref ADC_CHANNEL_VREFINT (7) - * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref ADC_CHANNEL_VBAT (6) - * @arg @ref ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * @retval Returned value can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 - * @arg @ref ADC_CHANNEL_9 - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 - * @arg @ref ADC_CHANNEL_16 - * @arg @ref ADC_CHANNEL_17 - * @arg @ref ADC_CHANNEL_18 - */ -#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ - __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) - -/** - * @brief Helper macro to determine whether the internal channel - * selected is available on the ADC instance selected. - * @note The channel parameter must be a value defined from parameter - * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, - * ADC_CHANNEL_TEMPSENSOR, ...), - * must not be a value defined from parameter definition of - * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) - * or a value from functions where a channel number is - * returned from ADC registers, - * because internal and external channels share the same channel - * number in ADC registers. The differentiation is made only with - * parameters definitions of driver. - * @param __ADC_INSTANCE__ ADC instance - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_VREFINT (7) - * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref ADC_CHANNEL_VBAT (6) - * @arg @ref ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. - * Value "1" if the internal channel selected is available on the ADC instance selected. - */ -#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ - __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) - -#if defined(ADC_MULTIMODE_SUPPORT) -/** - * @brief Helper macro to get the ADC multimode conversion data of ADC master - * or ADC slave from raw value with both ADC conversion data concatenated. - * @note This macro is intended to be used when multimode transfer by DMA - * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). - * In this case the transferred data need to processed with this macro - * to separate the conversion data of ADC master and ADC slave. - * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: - * @arg @ref LL_ADC_MULTI_MASTER - * @arg @ref LL_ADC_MULTI_SLAVE - * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ - __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) -#endif /* ADC_MULTIMODE_SUPPORT */ - -/** - * @brief Helper macro to select the ADC common instance - * to which is belonging the selected ADC instance. - * @note ADC common register instance can be used for: - * - Set parameters common to several ADC instances - * - Multimode (for devices with several ADC instances) - * Refer to functions having argument "ADCxy_COMMON" as parameter. - * @param __ADCx__ ADC instance - * @retval ADC common register instance - */ -#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ - __LL_ADC_COMMON_INSTANCE((__ADCx__)) - -/** - * @brief Helper macro to check if all ADC instances sharing the same - * ADC common instance are disabled. - * @note This check is required by functions with setting conditioned to - * ADC state: - * All ADC instances of the ADC common group must be disabled. - * Refer to functions having argument "ADCxy_COMMON" as parameter. - * @note On devices with only 1 ADC common instance, parameter of this macro - * is useless and can be ignored (parameter kept for compatibility - * with devices featuring several ADC common instances). - * @param __ADCXY_COMMON__ ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Value "0" if all ADC instances sharing the same ADC common instance - * are disabled. - * Value "1" if at least one ADC instance sharing the same ADC common instance - * is enabled. - */ -#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ - __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) - -/** - * @brief Helper macro to define the ADC conversion data full-scale digital - * value corresponding to the selected ADC resolution. - * @note ADC conversion data full-scale corresponds to voltage range - * determined by analog voltage references Vref+ and Vref- - * (refer to reference manual). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref ADC_RESOLUTION_12B - * @arg @ref ADC_RESOLUTION_10B - * @arg @ref ADC_RESOLUTION_8B - * @arg @ref ADC_RESOLUTION_6B - * @retval ADC conversion data full-scale digital value - */ -#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ - __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) - -/** - * @brief Helper macro to convert the ADC conversion data from - * a resolution to another resolution. - * @param __DATA__ ADC conversion data to be converted - * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted - * This parameter can be one of the following values: - * @arg @ref ADC_RESOLUTION_12B - * @arg @ref ADC_RESOLUTION_10B - * @arg @ref ADC_RESOLUTION_8B - * @arg @ref ADC_RESOLUTION_6B - * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion - * This parameter can be one of the following values: - * @arg @ref ADC_RESOLUTION_12B - * @arg @ref ADC_RESOLUTION_10B - * @arg @ref ADC_RESOLUTION_8B - * @arg @ref ADC_RESOLUTION_6B - * @retval ADC conversion data to the requested resolution - */ -#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ - __ADC_RESOLUTION_CURRENT__,\ - __ADC_RESOLUTION_TARGET__) \ -__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ - (__ADC_RESOLUTION_CURRENT__),\ - (__ADC_RESOLUTION_TARGET__)) - -/** - * @brief Helper macro to calculate the voltage (unit: mVolt) - * corresponding to a ADC conversion data (unit: digital value). - * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) - * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) - * (unit: digital value). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref ADC_RESOLUTION_12B - * @arg @ref ADC_RESOLUTION_10B - * @arg @ref ADC_RESOLUTION_8B - * @arg @ref ADC_RESOLUTION_6B - * @retval ADC conversion data equivalent voltage value (unit: mVolt) - */ -#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ - __ADC_DATA__,\ - __ADC_RESOLUTION__) \ -__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ - (__ADC_DATA__),\ - (__ADC_RESOLUTION__)) - -/** - * @brief Helper macro to calculate analog reference voltage (Vref+) - * (unit: mVolt) from ADC conversion data of internal voltage - * reference VrefInt. - * @note Computation is using VrefInt calibration value - * stored in system memory for each device during production. - * @note This voltage depends on user board environment: voltage level - * connected to pin Vref+. - * On devices with small package, the pin Vref+ is not present - * and internally bonded to pin Vdda. - * @note On this STM32 series, calibration data of internal voltage reference - * VrefInt corresponds to a resolution of 12 bits, - * this is the recommended ADC resolution to convert voltage of - * internal voltage reference VrefInt. - * Otherwise, this macro performs the processing to scale - * ADC conversion data to 12 bits. - * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) - * of internal voltage reference VrefInt (unit: digital value). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref ADC_RESOLUTION_12B - * @arg @ref ADC_RESOLUTION_10B - * @arg @ref ADC_RESOLUTION_8B - * @arg @ref ADC_RESOLUTION_6B - * @retval Analog reference voltage (unit: mV) - */ -#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ - __ADC_RESOLUTION__) \ -__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ - (__ADC_RESOLUTION__)) - -/** - * @brief Helper macro to calculate the temperature (unit: degree Celsius) - * from ADC conversion data of internal temperature sensor. - * @note Computation is using temperature sensor calibration values - * stored in system memory for each device during production. - * @note Calculation formula: - * Temperature = ((TS_ADC_DATA - TS_CAL1) - * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) - * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP - * with TS_ADC_DATA = temperature sensor raw data measured by ADC - * Avg_Slope = (TS_CAL2 - TS_CAL1) - * / (TS_CAL2_TEMP - TS_CAL1_TEMP) - * TS_CAL1 = equivalent TS_ADC_DATA at temperature - * TEMP_DEGC_CAL1 (calibrated in factory) - * TS_CAL2 = equivalent TS_ADC_DATA at temperature - * TEMP_DEGC_CAL2 (calibrated in factory) - * Caution: Calculation relevancy under reserve that calibration - * parameters are correct (address and data). - * To calculate temperature using temperature sensor - * datasheet typical values (generic values less, therefore - * less accurate than calibrated values), - * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). - * @note As calculation input, the analog reference voltage (Vref+) must be - * defined as it impacts the ADC LSB equivalent voltage. - * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note On this STM32 series, calibration data of temperature sensor - * corresponds to a resolution of 12 bits, - * this is the recommended ADC resolution to convert voltage of - * temperature sensor. - * Otherwise, this macro performs the processing to scale - * ADC conversion data to 12 bits. - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) - * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal - * temperature sensor (unit: digital value). - * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature - * sensor voltage has been measured. - * This parameter can be one of the following values: - * @arg @ref ADC_RESOLUTION_12B - * @arg @ref ADC_RESOLUTION_10B - * @arg @ref ADC_RESOLUTION_8B - * @arg @ref ADC_RESOLUTION_6B - * @retval Temperature (unit: degree Celsius) - */ -#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ - __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ -__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ - (__TEMPSENSOR_ADC_DATA__),\ - (__ADC_RESOLUTION__)) - -/** - * @brief Helper macro to calculate the temperature (unit: degree Celsius) - * from ADC conversion data of internal temperature sensor. - * @note Computation is using temperature sensor typical values - * (refer to device datasheet). - * @note Calculation formula: - * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) - * / Avg_Slope + CALx_TEMP - * with TS_ADC_DATA = temperature sensor raw data measured by ADC - * (unit: digital value) - * Avg_Slope = temperature sensor slope - * (unit: uV/Degree Celsius) - * TS_TYP_CALx_VOLT = temperature sensor digital value at - * temperature CALx_TEMP (unit: mV) - * Caution: Calculation relevancy under reserve the temperature sensor - * of the current device has characteristics in line with - * datasheet typical values. - * If temperature sensor calibration values are available on - * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), - * temperature calculation will be more accurate using - * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). - * @note As calculation input, the analog reference voltage (Vref+) must be - * defined as it impacts the ADC LSB equivalent voltage. - * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note ADC measurement data must correspond to a resolution of 12bits - * (full scale digital value 4095). If not the case, the data must be - * preliminarily rescaled to an equivalent resolution of 12 bits. - * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). - * On STM32G4, refer to device datasheet parameter "Avg_Slope". - * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). - * On STM32G4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). - * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) - * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) - * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). - * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. - * This parameter can be one of the following values: - * @arg @ref ADC_RESOLUTION_12B - * @arg @ref ADC_RESOLUTION_10B - * @arg @ref ADC_RESOLUTION_8B - * @arg @ref ADC_RESOLUTION_6B - * @retval Temperature (unit: degree Celsius) - */ -#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ - __TEMPSENSOR_TYP_CALX_V__,\ - __TEMPSENSOR_CALX_TEMP__,\ - __VREFANALOG_VOLTAGE__,\ - __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ -__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ - (__TEMPSENSOR_TYP_CALX_V__),\ - (__TEMPSENSOR_CALX_TEMP__),\ - (__VREFANALOG_VOLTAGE__),\ - (__TEMPSENSOR_ADC_DATA__),\ - (__ADC_RESOLUTION__)) - -/** - * @} - */ - -/** - * @} - */ - -/* Include ADC HAL Extended module */ -#include "stm32g4xx_hal_adc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup ADC_Exported_Functions - * @{ - */ - -/** @addtogroup ADC_Exported_Functions_Group1 - * @brief Initialization and Configuration functions - * @{ - */ -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); -void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); -void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); - -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -/* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, - pADC_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @addtogroup ADC_Exported_Functions_Group2 - * @brief IO operation functions - * @{ - */ -/* IO operation functions *****************************************************/ - -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); - -/* Non-blocking mode: Interruption */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); - -/* Non-blocking mode: DMA */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); - -/* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); - -/* ADC sampling control */ -HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc); - -/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); -void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); -void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); -void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); -void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); -/** - * @} - */ - -/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ -/* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); - -/** - * @} - */ - -/* Peripheral State functions *************************************************/ -/** @addtogroup ADC_Exported_Functions_Group4 - * @{ - */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions -----------------------------------------------------------*/ -/** @addtogroup ADC_Private_Functions ADC Private Functions - * @{ - */ -HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); -HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); -void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); -void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); -void ADC_DMAError(DMA_HandleTypeDef *hdma); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* STM32G4xx_HAL_ADC_H */ diff --git a/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h b/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h deleted file mode 100644 index d2da2c2..0000000 --- a/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h +++ /dev/null @@ -1,1393 +0,0 @@ -/** - ****************************************************************************** - * @file stm32g4xx_hal_adc_ex.h - * @author MCD Application Team - * @brief Header file of ADC HAL extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2019 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32G4xx_HAL_ADC_EX_H -#define STM32G4xx_HAL_ADC_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32g4xx_hal_def.h" - -/** @addtogroup STM32G4xx_HAL_Driver - * @{ - */ - -/** @addtogroup ADCEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types - * @{ - */ - -/** - * @brief ADC Injected Conversion Oversampling structure definition - */ -typedef struct -{ - uint32_t Ratio; /*!< Configures the oversampling ratio. - This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ - - uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. - This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ -} ADC_InjOversamplingTypeDef; - -/** - * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected - * @note Parameters of this structure are shared within 2 scopes: - * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset, InjectedOffsetSign, InjectedOffsetSaturation - * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, - * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling. - * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. - * ADC state can be either: - * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') - * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group. - * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'InjectedOffsetSign', 'InjectedOffsetSaturation', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. - * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going - * on ADC groups regular and injected. - * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed - * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). - */ -typedef struct -{ - uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. - This parameter can be a value of @ref ADC_HAL_EC_CHANNEL - Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ - - uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. - This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. - Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by - the new channel setting (or parameter number of conversions adjusted) */ - - uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. - Unit: ADC clock cycles. - Conversion time is the addition of sampling time and processing time - (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). - This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. - Caution: This parameter applies to a channel that can be used in a regular and/or injected group. - It overwrites the last setting. - Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), - sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) - Refer to device datasheet for timings values. */ - - uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. - In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). - Only channel 'i' has to be configured, channel 'i+1' is configured automatically. - This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. - Caution: This parameter applies to a channel that can be used in a regular and/or injected group. - It overwrites the last setting. - Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. - Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. - Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). - If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case - of another parameter update on the fly) */ - - uint32_t InjectedOffsetNumber; /*!< Selects the offset number. - This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. - Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ - - uint32_t InjectedOffset; /*!< Defines the offset to be applied on the raw converted data. - Offset value must be a positive number. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number - between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled - without continuous mode or external trigger that could launch a conversion). */ - - uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. - This parameter can be a value of @ref ADCEx_OffsetSign. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ - FunctionalState InjectedOffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. - This parameter value can be ENABLE or DISABLE. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ - - uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer. - To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. - This parameter must be a number between Min_Data = 1 and Max_Data = 4. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ - - FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence - (main sequence subdivided in successive parts). - Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. - Discontinuous mode can be enabled only if continuous mode is disabled. - This parameter can be set to ENABLE or DISABLE. - Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). - Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ - - FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one - This parameter can be set to ENABLE or DISABLE. - Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) - Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) - Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. - To maintain JAUTO always enabled, DMA must be configured in circular mode. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ - - FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. - This parameter can be set to ENABLE or DISABLE. - If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a - new injected context is set when queue is full, error is triggered by interruption and through function - 'HAL_ADCEx_InjectedQueueOverflowCallback'. - Caution: This feature request that the sequence is fully configured before injected conversion start. - Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. - Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ - - uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. - If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. - This parameter can be a value of @ref ADC_injected_external_trigger_source. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ - - uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. - This parameter can be a value of @ref ADC_injected_external_trigger_edge. - If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ - - FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. - This parameter can be set to ENABLE or DISABLE. - Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ - - ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. - Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. - Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ -} ADC_InjectionConfTypeDef; - -#if defined(ADC_MULTIMODE_SUPPORT) -/** - * @brief Structure definition of ADC multimode - * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). - * Both Master and Slave ADCs must be disabled. - */ -typedef struct -{ - uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. - This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ - - uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC: - selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master) - This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */ - - uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. - This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. - Delay range depends on selected resolution: - from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits, - from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */ -} ADC_MultiModeTypeDef; -#endif /* ADC_MULTIMODE_SUPPORT */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants - * @{ - */ - -/** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source - * @{ - */ -/* ADC group regular trigger sources for all ADC instances */ -#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T1_CC3 (LL_ADC_INJ_TRIG_EXT_TIM1_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T4_CC3 (LL_ADC_INJ_TRIG_EXT_TIM4_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T4_CC4 (LL_ADC_INJ_TRIG_EXT_TIM4_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T7_TRGO (LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T8_CC2 (LL_ADC_INJ_TRIG_EXT_TIM8_CH2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T16_CC1 (LL_ADC_INJ_TRIG_EXT_TIM16_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T20_TRGO (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T20_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T20_CC2 (LL_ADC_INJ_TRIG_EXT_TIM20_CH2) /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T20_CC4 (LL_ADC_INJ_TRIG_EXT_TIM20_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG1 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG3 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG5 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG6 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG7 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG8 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG9 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG10 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_EXT_IT3 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 3. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_LPTIM_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */ -/** - * @} - */ - -/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) - * @{ - */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending - * @{ - */ -#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ -#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number - * @{ - */ -#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */ -#define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ -#define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ -#define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ -#define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ -/** - * @} - */ - -/** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign - * @{ - */ -#define ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is subtracted */ -#define ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< Offset sign positive, offset is added */ -/** - * @} - */ - -/** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks - * @{ - */ -#define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ -#define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ -#define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ -#define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ -/** - * @} - */ - -#if defined(ADC_MULTIMODE_SUPPORT) -/** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode - * @{ - */ -#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */ -#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */ -#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */ -#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */ -#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ -#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ -#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ -#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ - -/** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution - * @{ - */ -#define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ -#define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ -#define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases - * @{ - */ -#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ -#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ -/** - * @} - */ - -/** - * @} - */ -#endif /* ADC_MULTIMODE_SUPPORT */ - -/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups - * @{ - */ -#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ -#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/ -#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ -/** - * @} - */ - -/** @defgroup ADC_CFGR_fields ADCx CFGR fields - * @{ - */ -#define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ - ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ - ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ - ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ - ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ - ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ) -/** - * @} - */ - -/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields - * @{ - */ -#if defined(ADC_SMPR1_SMPPLUS) -#define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ - ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ - ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ - ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS) -#else -#define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ - ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ - ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ - ADC_SMPR1_SMP0) -#endif /* ADC_SMPR1_SMPPLUS */ -/** - * @} - */ - -/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields - * @{ - */ -/* ADC_CFGR fields of parameters that can be updated when no conversion - (neither regular nor injected) is on-going */ -#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -#if defined(ADC_MULTIMODE_SUPPORT) -/** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros - * @{ - */ - -/** @brief Force ADC instance in multimode mode independent (multimode disable). - * @note This macro must be used only in case of transition from multimode - * to mode independent and in case of unknown previous state, - * to ensure ADC configuration is in mode independent. - * @note Standard way of multimode configuration change is done from - * HAL ADC handle of ADC master using function - * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". - * Usage of this macro is not the Standard way of multimode - * configuration and can lead to have HAL ADC handles status - * misaligned. Usage of this macro must be limited to cases - * mentioned above. - * @param __HANDLE__ ADC handle. - * @retval None - */ -#define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ - LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) - -/** - * @} - */ -#endif /* ADC_MULTIMODE_SUPPORT */ - -/* Private macros ------------------------------------------------------------*/ - -/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros - * @{ - */ -/* Macro reserved for internal HAL driver usage, not intended to be used in */ -/* code of final user. */ - -/** - * @brief Test if conversion trigger of injected group is software start - * or external trigger. - * @param __HANDLE__ ADC handle. - * @retval SET (software start) or RESET (external trigger). - */ -#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ - (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) - -/** - * @brief Check whether or not ADC is independent. - * @param __HANDLE__ ADC handle. - * @note When multimode feature is not available, the macro always returns SET. - * @retval SET (ADC is independent) or RESET (ADC is not). - */ -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) -#define ADC_IS_INDEPENDENT(__HANDLE__) \ - ( ( ( ((__HANDLE__)->Instance) == ADC5) \ - )? \ - SET \ - : \ - RESET \ - ) -#elif defined(STM32G491xx) || defined(STM32G4A1xx) -#define ADC_IS_INDEPENDENT(__HANDLE__) \ - ( ( ( ((__HANDLE__)->Instance) == ADC3) \ - )? \ - SET \ - : \ - RESET \ - ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) -#define ADC_IS_INDEPENDENT(__HANDLE__) (RESET) -#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ - -/** - * @brief Set the selected injected Channel rank. - * @param __CHANNELNB__ Channel number. - * @param __RANKNB__ Rank number. - * @retval None - */ -#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)\ - & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) - -/** - * @brief Configure ADC injected context queue - * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. - * @retval None - */ -#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) - -/** - * @brief Configure ADC discontinuous conversion mode for injected group - * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. - * @retval None - */ -#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) - -/** - * @brief Configure ADC discontinuous conversion mode for regular group - * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. - * @retval None - */ -#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) - -/** - * @brief Configure the number of discontinuous conversions for regular group. - * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. - * @retval None - */ -#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) - -/** - * @brief Configure the ADC auto delay mode. - * @param __AUTOWAIT__ Auto delay bit enable or disable. - * @retval None - */ -#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos) - -/** - * @brief Configure ADC continuous conversion mode. - * @param __CONTINUOUS_MODE__ Continuous mode. - * @retval None - */ -#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) - -/** - * @brief Configure the ADC DMA continuous request. - * @param __DMACONTREQ_MODE__ DMA continuous request mode. - * @retval None - */ -#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos) - -#if defined(ADC_MULTIMODE_SUPPORT) -/** - * @brief Configure the ADC DMA continuous request for ADC multimode. - * @param __DMACONTREQ_MODE__ DMA continuous request mode. - * @retval None - */ -#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) -#endif /* ADC_MULTIMODE_SUPPORT */ - -/** - * @brief Shift the offset with respect to the selected ADC resolution. - * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. - * If resolution 12 bits, no shift. - * If resolution 10 bits, shift of 2 ranks on the left. - * If resolution 8 bits, shift of 4 ranks on the left. - * If resolution 6 bits, shift of 6 ranks on the left. - * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). - * @param __HANDLE__ ADC handle - * @param __OFFSET__ Value to be shifted - * @retval None - */ -#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ - ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) - -/** - * @brief Shift the AWD1 threshold with respect to the selected ADC resolution. - * @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. - * If resolution 12 bits, no shift. - * If resolution 10 bits, shift of 2 ranks on the left. - * If resolution 8 bits, shift of 4 ranks on the left. - * If resolution 6 bits, shift of 6 ranks on the left. - * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). - * @param __HANDLE__ ADC handle - * @param __THRESHOLD__ Value to be shifted - * @retval None - */ -#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ - ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) - -/** - * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution. - * @note Thresholds have to be left-aligned on bit 7. - * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded). - * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded). - * If resolution 8 bits, no shift. - * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0). - * @param __HANDLE__ ADC handle - * @param __THRESHOLD__ Value to be shifted - * @retval None - */ -#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \ - ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \ - ((__THRESHOLD__) << 2UL) \ - ) - -/** - * @brief Clear Common Control Register. - * @param __HANDLE__ ADC handle. - * @retval None - */ -#if defined(ADC_MULTIMODE_SUPPORT) -#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ - ADC_CCR_CKMODE | \ - ADC_CCR_PRESC | \ - ADC_CCR_VBATSEL | \ - ADC_CCR_VSENSESEL | \ - ADC_CCR_VREFEN | \ - ADC_CCR_MDMA | \ - ADC_CCR_DMACFG | \ - ADC_CCR_DELAY | \ - ADC_CCR_DUAL) -#endif /* ADC_MULTIMODE_SUPPORT */ - -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) -/** - * @brief Set handle instance of the ADC slave associated to the ADC master. - * @param __HANDLE_MASTER__ ADC master handle. - * @param __HANDLE_SLAVE__ ADC slave handle. - * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. - * @retval None - */ -#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ - ( ((__HANDLE_MASTER__)->Instance == ADC1) ? \ - ((__HANDLE_SLAVE__)->Instance = ADC2) \ - : \ - ((__HANDLE_MASTER__)->Instance == ADC3) ? \ - ((__HANDLE_SLAVE__)->Instance = ADC4) \ - : \ - ((__HANDLE_SLAVE__)->Instance = NULL) \ - ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) -/** - * @brief Set handle instance of the ADC slave associated to the ADC master. - * @param __HANDLE_MASTER__ ADC master handle. - * @param __HANDLE_SLAVE__ ADC slave handle. - * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. - * @retval None - */ -#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ - ( ((__HANDLE_MASTER__)->Instance == ADC1) ? \ - ((__HANDLE_SLAVE__)->Instance = ADC2) \ - : \ - ((__HANDLE_SLAVE__)->Instance = NULL) \ - ) -#endif - - -/** - * @brief Verify the ADC instance connected to the temperature sensor. - * @param __HANDLE__ ADC handle. - * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) - */ -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) -#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5)) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) -#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) -#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ - -/** - * @brief Verify the ADC instance connected to the battery voltage VBAT. - * @param __HANDLE__ ADC handle. - * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) - */ -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) -#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) != ADC2) || (((__HANDLE__)->Instance) != ADC4)) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) -#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2) -#elif defined(STM32G491xx) || defined(STM32G4A1xx) -#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) -#endif - -/** - * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. - * @param __HANDLE__ ADC handle. - * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) - */ -#define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2) - -/** - * @brief Verify the length of scheduled injected conversions group. - * @param __LENGTH__ number of programmed conversions. - * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) - */ -#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) - -/** - * @brief Calibration factor size verification (7 bits maximum). - * @param __CALIBRATION_FACTOR__ Calibration factor value. - * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) - */ -#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) - - -/** - * @brief Verify the ADC channel setting. - * @param __HANDLE__ ADC handle. - * @param __CHANNEL__ programmed ADC channel. - * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) - */ -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) -#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ - ((__CHANNEL__) == ADC_CHANNEL_2) || \ - ((__CHANNEL__) == ADC_CHANNEL_6) || \ - ((__CHANNEL__) == ADC_CHANNEL_7) || \ - ((__CHANNEL__) == ADC_CHANNEL_8) || \ - ((__CHANNEL__) == ADC_CHANNEL_9) || \ - ((__CHANNEL__) == ADC_CHANNEL_10) || \ - ((__CHANNEL__) == ADC_CHANNEL_11) || \ - ((__CHANNEL__) == ADC_CHANNEL_12) || \ - ((__CHANNEL__) == ADC_CHANNEL_14) || \ - ((__CHANNEL__) == ADC_CHANNEL_15)) || \ - ((((__HANDLE__)->Instance) == ADC1) && \ - (((__CHANNEL__) == ADC_CHANNEL_3) || \ - ((__CHANNEL__) == ADC_CHANNEL_4) || \ - ((__CHANNEL__) == ADC_CHANNEL_5) || \ - ((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \ - ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \ - ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ - ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ - ((((__HANDLE__)->Instance) == ADC2) && \ - (((__CHANNEL__) == ADC_CHANNEL_3) || \ - ((__CHANNEL__) == ADC_CHANNEL_4) || \ - ((__CHANNEL__) == ADC_CHANNEL_5) || \ - ((__CHANNEL__) == ADC_CHANNEL_13) || \ - ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ - ((__CHANNEL__) == ADC_CHANNEL_17) || \ - ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \ - ((((__HANDLE__)->Instance) == ADC3) && \ - (((__CHANNEL__) == ADC_CHANNEL_3) || \ - ((__CHANNEL__) == ADC_CHANNEL_4) || \ - ((__CHANNEL__) == ADC_CHANNEL_5) || \ - ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \ - ((__CHANNEL__) == ADC_CHANNEL_16) || \ - ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ - ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ - ((((__HANDLE__)->Instance) == ADC4) && \ - (((__CHANNEL__) == ADC_CHANNEL_3) || \ - ((__CHANNEL__) == ADC_CHANNEL_4) || \ - ((__CHANNEL__) == ADC_CHANNEL_5) || \ - ((__CHANNEL__) == ADC_CHANNEL_13) || \ - ((__CHANNEL__) == ADC_CHANNEL_16) || \ - ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6) || \ - ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ - ((((__HANDLE__)->Instance) == ADC5) && \ - (((__CHANNEL__) == ADC_CHANNEL_VOPAMP5) || \ - ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC5) || \ - ((__CHANNEL__) == ADC_CHANNEL_VOPAMP4) || \ - ((__CHANNEL__) == ADC_CHANNEL_13) || \ - ((__CHANNEL__) == ADC_CHANNEL_16) || \ - ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ - ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) -#elif defined(STM32G471xx) -#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ - ((__CHANNEL__) == ADC_CHANNEL_2) || \ - ((__CHANNEL__) == ADC_CHANNEL_3) || \ - ((__CHANNEL__) == ADC_CHANNEL_4) || \ - ((__CHANNEL__) == ADC_CHANNEL_5) || \ - ((__CHANNEL__) == ADC_CHANNEL_6) || \ - ((__CHANNEL__) == ADC_CHANNEL_7) || \ - ((__CHANNEL__) == ADC_CHANNEL_8) || \ - ((__CHANNEL__) == ADC_CHANNEL_9) || \ - ((__CHANNEL__) == ADC_CHANNEL_10) || \ - ((__CHANNEL__) == ADC_CHANNEL_11) || \ - ((__CHANNEL__) == ADC_CHANNEL_12) || \ - ((__CHANNEL__) == ADC_CHANNEL_14) || \ - ((__CHANNEL__) == ADC_CHANNEL_15)) || \ - ((((__HANDLE__)->Instance) == ADC1) && \ - (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \ - ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \ - ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ - ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ - ((((__HANDLE__)->Instance) == ADC2) && \ - (((__CHANNEL__) == ADC_CHANNEL_13) || \ - ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ - ((__CHANNEL__) == ADC_CHANNEL_17) || \ - ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \ - ((((__HANDLE__)->Instance) == ADC3) && \ - (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \ - ((__CHANNEL__) == ADC_CHANNEL_16) || \ - ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ - ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) -#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ - ((__CHANNEL__) == ADC_CHANNEL_2) || \ - ((__CHANNEL__) == ADC_CHANNEL_3) || \ - ((__CHANNEL__) == ADC_CHANNEL_4) || \ - ((__CHANNEL__) == ADC_CHANNEL_5) || \ - ((__CHANNEL__) == ADC_CHANNEL_6) || \ - ((__CHANNEL__) == ADC_CHANNEL_7) || \ - ((__CHANNEL__) == ADC_CHANNEL_8) || \ - ((__CHANNEL__) == ADC_CHANNEL_9) || \ - ((__CHANNEL__) == ADC_CHANNEL_10) || \ - ((__CHANNEL__) == ADC_CHANNEL_11) || \ - ((__CHANNEL__) == ADC_CHANNEL_12) || \ - ((__CHANNEL__) == ADC_CHANNEL_14) || \ - ((__CHANNEL__) == ADC_CHANNEL_15)) || \ - ((((__HANDLE__)->Instance) == ADC1) && \ - (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \ - ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \ - ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ - ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ - ((((__HANDLE__)->Instance) == ADC2) && \ - (((__CHANNEL__) == ADC_CHANNEL_13) || \ - ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ - ((__CHANNEL__) == ADC_CHANNEL_17) || \ - ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2)))) -#elif defined(STM32G491xx) || defined(STM32G4A1xx) -#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ - ((__CHANNEL__) == ADC_CHANNEL_2) || \ - ((__CHANNEL__) == ADC_CHANNEL_3) || \ - ((__CHANNEL__) == ADC_CHANNEL_4) || \ - ((__CHANNEL__) == ADC_CHANNEL_5) || \ - ((__CHANNEL__) == ADC_CHANNEL_6) || \ - ((__CHANNEL__) == ADC_CHANNEL_7) || \ - ((__CHANNEL__) == ADC_CHANNEL_8) || \ - ((__CHANNEL__) == ADC_CHANNEL_9) || \ - ((__CHANNEL__) == ADC_CHANNEL_10) || \ - ((__CHANNEL__) == ADC_CHANNEL_11) || \ - ((__CHANNEL__) == ADC_CHANNEL_12) || \ - ((__CHANNEL__) == ADC_CHANNEL_14) || \ - ((__CHANNEL__) == ADC_CHANNEL_15)) || \ - ((((__HANDLE__)->Instance) == ADC1) && \ - (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \ - ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \ - ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ - ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ - ((((__HANDLE__)->Instance) == ADC2) && \ - (((__CHANNEL__) == ADC_CHANNEL_13) || \ - ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ - ((__CHANNEL__) == ADC_CHANNEL_17) || \ - ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \ - ((((__HANDLE__)->Instance) == ADC3) && \ - (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \ - ((__CHANNEL__) == ADC_CHANNEL_16) || \ - ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6) || \ - ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) -#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ - -/** - * @brief Verify the ADC channel setting in differential mode. - * @param __HANDLE__ ADC handle. - * @param __CHANNEL__ programmed ADC channel. - * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) - */ -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) -#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ - ((__CHANNEL__) == ADC_CHANNEL_6) || \ - ((__CHANNEL__) == ADC_CHANNEL_7) || \ - ((__CHANNEL__) == ADC_CHANNEL_8) || \ - ((__CHANNEL__) == ADC_CHANNEL_9) || \ - ((__CHANNEL__) == ADC_CHANNEL_10) || \ - ((__CHANNEL__) == ADC_CHANNEL_11) || \ - ((__CHANNEL__) == ADC_CHANNEL_14)) || \ - ((((__HANDLE__)->Instance) == ADC1) && \ - (((__CHANNEL__) == ADC_CHANNEL_2) || \ - ((__CHANNEL__) == ADC_CHANNEL_3) || \ - ((__CHANNEL__) == ADC_CHANNEL_4) || \ - ((__CHANNEL__) == ADC_CHANNEL_5))) || \ - ((((__HANDLE__)->Instance) == ADC2) && \ - (((__CHANNEL__) == ADC_CHANNEL_2) || \ - ((__CHANNEL__) == ADC_CHANNEL_3) || \ - ((__CHANNEL__) == ADC_CHANNEL_4) || \ - ((__CHANNEL__) == ADC_CHANNEL_5) || \ - ((__CHANNEL__) == ADC_CHANNEL_12) || \ - ((__CHANNEL__) == ADC_CHANNEL_13))) || \ - ((((__HANDLE__)->Instance) == ADC3) && \ - (((__CHANNEL__) == ADC_CHANNEL_2) || \ - ((__CHANNEL__) == ADC_CHANNEL_3) || \ - ((__CHANNEL__) == ADC_CHANNEL_4) || \ - ((__CHANNEL__) == ADC_CHANNEL_5) || \ - ((__CHANNEL__) == ADC_CHANNEL_15))) || \ - ((((__HANDLE__)->Instance) == ADC4) && \ - (((__CHANNEL__) == ADC_CHANNEL_2) || \ - ((__CHANNEL__) == ADC_CHANNEL_3) || \ - ((__CHANNEL__) == ADC_CHANNEL_4) || \ - ((__CHANNEL__) == ADC_CHANNEL_5) || \ - ((__CHANNEL__) == ADC_CHANNEL_12) || \ - ((__CHANNEL__) == ADC_CHANNEL_13) || \ - ((__CHANNEL__) == ADC_CHANNEL_15))) || \ - ((((__HANDLE__)->Instance) == ADC5) && \ - (((__CHANNEL__) == ADC_CHANNEL_12) || \ - ((__CHANNEL__) == ADC_CHANNEL_13) || \ - ((__CHANNEL__) == ADC_CHANNEL_15))) ) -#elif defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) -#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ - (((__CHANNEL__) == ADC_CHANNEL_2) || \ - ((__CHANNEL__) == ADC_CHANNEL_3) || \ - ((__CHANNEL__) == ADC_CHANNEL_4) || \ - ((__CHANNEL__) == ADC_CHANNEL_5) || \ - ((__CHANNEL__) == ADC_CHANNEL_6) || \ - ((__CHANNEL__) == ADC_CHANNEL_7) || \ - ((__CHANNEL__) == ADC_CHANNEL_8) || \ - ((__CHANNEL__) == ADC_CHANNEL_9) || \ - ((__CHANNEL__) == ADC_CHANNEL_10) || \ - ((__CHANNEL__) == ADC_CHANNEL_11) || \ - ((__CHANNEL__) == ADC_CHANNEL_14)) || \ - ((((__HANDLE__)->Instance) == ADC2) && \ - (((__CHANNEL__) == ADC_CHANNEL_12) || \ - ((__CHANNEL__) == ADC_CHANNEL_13))) || \ - ((((__HANDLE__)->Instance) == ADC3) && \ - ((__CHANNEL__) == ADC_CHANNEL_15))) ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) -#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ - ((__CHANNEL__) == ADC_CHANNEL_2) || \ - ((__CHANNEL__) == ADC_CHANNEL_3) || \ - ((__CHANNEL__) == ADC_CHANNEL_4) || \ - ((__CHANNEL__) == ADC_CHANNEL_5) || \ - ((__CHANNEL__) == ADC_CHANNEL_6) || \ - ((__CHANNEL__) == ADC_CHANNEL_7) || \ - ((__CHANNEL__) == ADC_CHANNEL_8) || \ - ((__CHANNEL__) == ADC_CHANNEL_9) || \ - ((__CHANNEL__) == ADC_CHANNEL_10) || \ - ((__CHANNEL__) == ADC_CHANNEL_11) || \ - ((__CHANNEL__) == ADC_CHANNEL_14)) || \ - ((((__HANDLE__)->Instance) == ADC2) && \ - (((__CHANNEL__) == ADC_CHANNEL_12) || \ - ((__CHANNEL__) == ADC_CHANNEL_13))) ) -#endif - -/** - * @brief Verify the ADC single-ended input or differential mode setting. - * @param __SING_DIFF__ programmed channel setting. - * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) - */ -#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ - ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) - -/** - * @brief Verify the ADC offset management setting. - * @param __OFFSET_NUMBER__ ADC offset management. - * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) - */ -#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ - ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ - ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ - ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ - ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) - -/** - * @brief Verify the ADC offset sign setting. - * @param __OFFSET_SIGN__ ADC offset sign. - * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid) - */ -#define IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__) (((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_NEGATIVE) || \ - ((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_POSITIVE) ) - -/** - * @brief Verify the ADC injected channel setting. - * @param __CHANNEL__ programmed ADC injected channel. - * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) - */ -#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ - ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ - ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ - ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) - -/** - * @brief Verify the ADC injected conversions external trigger. - * @param __HANDLE__ ADC handle. - * @param __INJTRIG__ programmed ADC injected conversions external trigger. - * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) - */ -#if defined(STM32G474xx) || defined(STM32G484xx) -#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG5) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG6) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG7) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG8) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG9) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG10) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ - ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ - (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ - ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ - (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ - ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) -#elif defined(STM32G473xx) || defined(STM32G483xx) -#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ - ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ - (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ - ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ - (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ - ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) -#elif defined(STM32G471xx) -#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ - ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ - (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ - ((((__HANDLE__)->Instance == ADC3)) && \ - (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ - ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) -#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ - ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) -#elif defined(STM32G491xx) || defined(STM32G4A1xx) -#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ - ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ - (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ - (((__HANDLE__)->Instance == ADC3) && \ - (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ - ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) -#endif - -/** - * @brief Verify the ADC edge trigger setting for injected group. - * @param __EDGE__ programmed ADC edge trigger setting. - * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) - */ -#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ - ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ - ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ - ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) - -#if defined(ADC_MULTIMODE_SUPPORT) -/** - * @brief Verify the ADC multimode setting. - * @param __MODE__ programmed ADC multimode setting. - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ - ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ - ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ - ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ - ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ - ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ - ((__MODE__) == ADC_DUALMODE_INTERL) || \ - ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) - -/** - * @brief Verify the ADC multimode DMA access setting. - * @param __MODE__ programmed ADC multimode DMA access setting. - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \ - ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \ - ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) ) - -/** - * @brief Verify the ADC multimode delay setting. - * @param __DELAY__ programmed ADC multimode delay setting. - * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) - */ -#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) ) -#endif /* ADC_MULTIMODE_SUPPORT */ - -/** - * @brief Verify the ADC analog watchdog setting. - * @param __WATCHDOG__ programmed ADC analog watchdog setting. - * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) - */ -#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ - ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ - ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) - -/** - * @brief Verify the ADC analog watchdog mode setting. - * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. - * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) - */ -#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ - ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ - ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ - ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ - ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ - ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ - ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) - -/** - * @brief Verify the ADC analog watchdog filtering setting. - * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting. - * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid) - */ -#define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__) (((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE) || \ - ((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES) || \ - ((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES) || \ - ((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES) || \ - ((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES) || \ - ((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES) || \ - ((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES) || \ - ((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES) ) - - -/** - * @brief Verify the ADC conversion (regular or injected or both). - * @param __CONVERSION__ ADC conversion group. - * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) - */ -#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ - ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ - ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) - -/** - * @brief Verify the ADC event type. - * @param __EVENT__ ADC event. - * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) - */ -#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ - ((__EVENT__) == ADC_AWD_EVENT) || \ - ((__EVENT__) == ADC_AWD2_EVENT) || \ - ((__EVENT__) == ADC_AWD3_EVENT) || \ - ((__EVENT__) == ADC_OVR_EVENT) || \ - ((__EVENT__) == ADC_JQOVF_EVENT) ) - -/** - * @brief Verify the ADC oversampling ratio. - * @param __RATIO__ programmed ADC oversampling ratio. - * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) - */ -#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ - ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ - ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ - ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ - ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ - ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ - ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \ - ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) - -/** - * @brief Verify the ADC oversampling shift. - * @param __SHIFT__ programmed ADC oversampling shift. - * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) - */ -#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ - ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ - ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ - ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ - ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ - ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ - ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ - ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ - ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) - -/** - * @brief Verify the ADC oversampling triggered mode. - * @param __MODE__ programmed ADC oversampling triggered mode. - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ - ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) - -/** - * @brief Verify the ADC oversampling regular conversion resumed or continued mode. - * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ - ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) - -/** - * @brief Verify the DFSDM mode configuration. - * @param __HANDLE__ ADC handle. - * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For - * this reason, the input parameter is the ADC handle and not the configuration parameter - * directly. - * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) - */ -#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) - -/** - * @brief Return the DFSDM configuration mode. - * @param __HANDLE__ ADC handle. - * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). - * For this reason, the input parameter is the ADC handle and not the configuration parameter - * directly. - * @retval DFSDM configuration mode - */ -#define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup ADCEx_Exported_Functions - * @{ - */ - -/** @addtogroup ADCEx_Exported_Functions_Group1 - * @{ - */ -/* IO operation functions *****************************************************/ - -/* ADC calibration */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); -uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); -HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, - uint32_t CalibrationFactor); - -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); - -/* Non-blocking mode: Interruption */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); - -#if defined(ADC_MULTIMODE_SUPPORT) -/* ADC multimode */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); -HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); -#endif /* ADC_MULTIMODE_SUPPORT */ - -/* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); - -/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ -void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); -void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); -void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); -void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); -void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); - -/* ADC group regular conversions stop */ -HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); -#if defined(ADC_MULTIMODE_SUPPORT) -HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); -#endif /* ADC_MULTIMODE_SUPPORT */ - -/** - * @} - */ - -/** @addtogroup ADCEx_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, - ADC_InjectionConfTypeDef *sConfigInjected); -#if defined(ADC_MULTIMODE_SUPPORT) -HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); -#endif /* ADC_MULTIMODE_SUPPORT */ -HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32G4xx_HAL_ADC_EX_H */ diff --git a/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h b/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h deleted file mode 100644 index 11dc3e6..0000000 --- a/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h +++ /dev/null @@ -1,8183 +0,0 @@ -/** - ****************************************************************************** - * @file stm32g4xx_ll_adc.h - * @author MCD Application Team - * @brief Header file of ADC LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2019 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32G4xx_LL_ADC_H -#define STM32G4xx_LL_ADC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32g4xx.h" - -/** @addtogroup STM32G4xx_LL_Driver - * @{ - */ - -#if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5) - -/** @defgroup ADC_LL ADC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup ADC_LL_Private_Constants ADC Private Constants - * @{ - */ - -/* Internal mask for ADC group regular sequencer: */ -/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ -/* - sequencer register offset */ -/* - sequencer rank bits position into the selected register */ - -/* Internal register offset for ADC group regular sequencer configuration */ -/* (offset placed into a spare area of literal definition) */ -#define ADC_SQR1_REGOFFSET (0x00000000UL) -#define ADC_SQR2_REGOFFSET (0x00000100UL) -#define ADC_SQR3_REGOFFSET (0x00000200UL) -#define ADC_SQR4_REGOFFSET (0x00000300UL) - -#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \ - | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) -#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */ -#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) - -/* Definition of ADC group regular sequencer bits information to be inserted */ -/* into ADC group regular sequencer ranks literals definition. */ -#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS (ADC_SQR1_SQ1_Pos) -#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (ADC_SQR1_SQ2_Pos) -#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (ADC_SQR1_SQ3_Pos) -#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (ADC_SQR1_SQ4_Pos) -#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (ADC_SQR2_SQ5_Pos) -#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (ADC_SQR2_SQ6_Pos) -#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (ADC_SQR2_SQ7_Pos) -#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (ADC_SQR2_SQ8_Pos) -#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (ADC_SQR2_SQ9_Pos) -#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos) -#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos) -#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos) -#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos) -#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos) -#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos) -#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos) - - - -/* Internal mask for ADC group injected sequencer: */ -/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ -/* - data register offset */ -/* - sequencer rank bits position into the selected register */ - -/* Internal register offset for ADC group injected data register */ -/* (offset placed into a spare area of literal definition) */ -#define ADC_JDR1_REGOFFSET (0x00000000UL) -#define ADC_JDR2_REGOFFSET (0x00000100UL) -#define ADC_JDR3_REGOFFSET (0x00000200UL) -#define ADC_JDR4_REGOFFSET (0x00000300UL) - -#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \ - | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) -#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) -#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */ - -/* Definition of ADC group injected sequencer bits information to be inserted */ -/* into ADC group injected sequencer ranks literals definition. */ -#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos) -#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos) -#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos) -#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos) - - - -/* Internal mask for ADC group regular trigger: */ -/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ -/* - regular trigger source */ -/* - regular trigger edge */ -#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ - -/* Mask containing trigger source masks for each of possible */ -/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ -/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \ - ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \ - ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \ - ((ADC_CFGR_EXTSEL) << (4U * 3UL)) ) - -/* Mask containing trigger edge masks for each of possible */ -/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ -/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) - -/* Definition of ADC group regular trigger bits information. */ -#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR_EXTSEL_Pos) -#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_CFGR_EXTEN_Pos) - - - -/* Internal mask for ADC group injected trigger: */ -/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */ -/* - injected trigger source */ -/* - injected trigger edge */ -#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ - -/* Mask containing trigger source masks for each of possible */ -/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ -/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \ - ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \ - ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \ - ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) ) - -/* Mask containing trigger edge masks for each of possible */ -/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ -/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \ - ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ - ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ - ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) - -/* Definition of ADC group injected trigger bits information. */ -#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JSQR_JEXTSEL_Pos) -#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (ADC_JSQR_JEXTEN_Pos) - - - - - - -/* Internal mask for ADC channel: */ -/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ -/* - channel identifier defined by number */ -/* - channel identifier defined by bitfield */ -/* - channel differentiation between external channels (connected to */ -/* GPIO pins) and internal channels (connected to internal paths) */ -/* - channel sampling time defined by SMPRx register offset */ -/* and SMPx bits positions into SMPRx register */ -#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH) -#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH) -#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos) -#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \ - | ADC_CHANNEL_ID_INTERNAL_CH_MASK) -/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ -#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */ - -/* Channel differentiation between external and internal channels */ -#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */ -#define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ -#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) - -/* Internal register offset for ADC channel sampling time configuration */ -/* (offset placed into a spare area of literal definition) */ -#define ADC_SMPR1_REGOFFSET (0x00000000UL) -#define ADC_SMPR2_REGOFFSET (0x02000000UL) -#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) -#define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */ - -#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL) -#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */ - -/* Definition of channels ID number information to be inserted into */ -/* channels literals definition. */ -#define ADC_CHANNEL_0_NUMBER (0x00000000UL) -#define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1) -#define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2) -#define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1) -#define ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3) -#define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1) -#define ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2) -#define ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1) -#define ADC_CHANNEL_15_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \ - ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4) -#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1) - -/* Definition of channels ID bitfield information to be inserted into */ -/* channels literals definition. */ -#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0) -#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1) -#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2) -#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3) -#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4) -#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5) -#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6) -#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7) -#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8) -#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9) -#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10) -#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11) -#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12) -#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13) -#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14) -#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15) -#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16) -#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17) -#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18) - -/* Definition of channels sampling time information to be inserted into */ -/* channels literals definition. */ -#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */ -#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */ -#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */ -#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */ -#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */ -#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */ -#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */ -#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */ -#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */ -#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */ -#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */ -#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */ -#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */ -#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */ -#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */ -#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */ -#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */ -#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */ -#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */ - - -/* Internal mask for ADC mode single or differential ended: */ -/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */ -/* the relevant bits for: */ -/* (concatenation of multiple bits used in different registers) */ -/* - ADC calibration: calibration start, calibration factor get or set */ -/* - ADC channels: set each ADC channel ending mode */ -#define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF) -#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S) -#define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */ -#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */ -#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */ -#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */ -#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */ - -/* Internal mask for ADC analog watchdog: */ -/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ -/* (concatenation of multiple bits used in different analog watchdogs, */ -/* (feature of several watchdogs not available on all STM32 families)). */ -/* - analog watchdog 1: monitored channel defined by number, */ -/* selection of ADC group (ADC groups regular and-or injected). */ -/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */ -/* selection on groups. */ - -/* Internal register offset for ADC analog watchdog channel configuration */ -#define ADC_AWD_CR1_REGOFFSET (0x00000000UL) -#define ADC_AWD_CR2_REGOFFSET (0x00100000UL) -#define ADC_AWD_CR3_REGOFFSET (0x00200000UL) - -/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */ -/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */ -#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0) -#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL) - -#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET) - -#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) -#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH) -#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK) - -#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */ - -/* Internal register offset for ADC analog watchdog threshold configuration */ -#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) -#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET) -#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET) -#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET) -#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */ -#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */ -#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */ -#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */ - -/* Internal mask for ADC offset: */ -/* Internal register offset for ADC offset number configuration */ -#define ADC_OFR1_REGOFFSET (0x00000000UL) -#define ADC_OFR2_REGOFFSET (0x00000001UL) -#define ADC_OFR3_REGOFFSET (0x00000002UL) -#define ADC_OFR4_REGOFFSET (0x00000003UL) -#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \ - | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET) - - -/* ADC registers bits positions */ -#define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos) -#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos) -#define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos) -#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos) -#define ADC_TR1_HT1_BITOFFSET_POS (ADC_TR1_HT1_Pos) - - -/* ADC registers bits groups */ -#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */ - - -/* ADC internal channels related definitions */ -/* Internal voltage reference VrefInt */ -#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ -#define VREFINT_CAL_VREF (3000UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ -/* Temperature sensor */ -#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32G4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32G4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ - -/** - * @} - */ - - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup ADC_LL_Private_Macros ADC Private Macros - * @{ - */ - -/** - * @brief Driver macro reserved for internal use: set a pointer to - * a register from a register basis from which an offset - * is applied. - * @param __REG__ Register basis from which the offset is applied. - * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). - * @retval Pointer to register address - */ -#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ - ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) - -/** - * @} - */ - - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure - * @{ - */ - -/** - * @brief Structure definition of some features of ADC common parameters - * and multimode - * (all ADC instances belonging to the same ADC common instance). - * @note The setting of these parameters by function @ref LL_ADC_CommonInit() - * is conditioned to ADC instances state (all ADC instances - * sharing the same ADC common instance): - * All ADC instances sharing the same ADC common instance must be - * disabled. - */ -typedef struct -{ - uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. - This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE - @note On this STM32 series, if ADC group injected is used, some - clock ratio constraints between ADC clock and AHB clock - must be respected. Refer to reference manual. - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */ - -#if defined(ADC_MULTIMODE_SUPPORT) - uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). - This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */ - - uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA. - This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */ - - uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases. - This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */ -#endif /* ADC_MULTIMODE_SUPPORT */ - -} LL_ADC_CommonInitTypeDef; - -/** - * @brief Structure definition of some features of ADC instance. - * @note These parameters have an impact on ADC scope: ADC instance. - * Affects both group regular and group injected (availability - * of ADC group injected depends on STM32 families). - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Instance . - * @note The setting of these parameters by function @ref LL_ADC_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - */ -typedef struct -{ - uint32_t Resolution; /*!< Set ADC resolution. - This parameter can be a value of @ref ADC_LL_EC_RESOLUTION - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ - - uint32_t DataAlignment; /*!< Set ADC conversion data alignment. - This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ - - uint32_t LowPowerMode; /*!< Set ADC low power mode. - This parameter can be a value of @ref ADC_LL_EC_LP_MODE - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */ - -} LL_ADC_InitTypeDef; - -/** - * @brief Structure definition of some features of ADC group regular. - * @note These parameters have an impact on ADC scope: ADC group regular. - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Group_Regular - * (functions with prefix "REG"). - * @note The setting of these parameters by function @ref LL_ADC_REG_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - */ -typedef struct -{ - uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). - This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE - @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge - (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). - In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge(). - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ - - uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. - This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ - - uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. - This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE - @note This parameter has an effect only if group regular sequencer is enabled - (scan length of 2 ranks or more). - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ - - uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). - This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE - Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ - - uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. - This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ - - uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun: - data preserved or overwritten. - This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */ - -} LL_ADC_REG_InitTypeDef; - -/** - * @brief Structure definition of some features of ADC group injected. - * @note These parameters have an impact on ADC scope: ADC group injected. - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Group_Regular - * (functions with prefix "INJ"). - * @note The setting of these parameters by function @ref LL_ADC_INJ_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - */ -typedef struct -{ - uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). - This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE - @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge - (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). - In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge(). - - This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ - - uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. - This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH - - This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ - - uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. - This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE - @note This parameter has an effect only if group injected sequencer is enabled - (scan length of 2 ranks or more). - - This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ - - uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. - This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO - Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. - - This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ - -} LL_ADC_INJ_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants - * @{ - */ - -/** @defgroup ADC_LL_EC_FLAG ADC flags - * @brief Flags defines which can be used with LL_ADC_ReadReg function - * @{ - */ -#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */ -#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */ -#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */ -#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */ -#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */ -#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */ -#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */ -#define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */ -#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */ -#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */ -#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */ -#if defined(ADC_MULTIMODE_SUPPORT) -#define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */ -#define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */ -#define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */ -#define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */ -#define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */ -#define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */ -#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */ -#define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */ -#define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */ -#define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */ -#define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */ -#define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */ -#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */ -#define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */ -#define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */ -#define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */ -#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */ -#define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */ -#define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */ -#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */ -#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */ -#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */ -#endif /* ADC_MULTIMODE_SUPPORT */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) - * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions - * @{ - */ -#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */ -#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */ -#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */ -#define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */ -#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */ -#define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */ -#define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */ -#define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */ -#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */ -#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */ -#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose - * @{ - */ -/* List of ADC registers intended to be used (most commonly) with */ -/* DMA transfer. */ -/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ -#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ -#if defined(ADC_MULTIMODE_SUPPORT) -#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ -#endif /* ADC_MULTIMODE_SUPPORT */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source - * @{ - */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ -#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */ -#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */ -#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */ -#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6 */ -#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8 */ -#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10 */ -#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12 */ -#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16 */ -#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32 */ -#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64 */ -#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128 */ -#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels - * @{ - */ -/* Note: Other measurement paths to internal channels may be available */ -/* (connections to other peripherals). */ -/* If they are not listed below, they do not require any specific */ -/* path enable. In this case, Access to measurement path is done */ -/* only by selecting the corresponding ADC internal channel. */ -#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */ -#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ -#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSESEL) /*!< ADC measurement path to internal channel temperature sensor */ -#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATSEL) /*!< ADC measurement path to internal channel Vbat */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution - * @{ - */ -#define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */ -#define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */ -#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */ -#define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment - * @{ - */ -#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ -#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode - * @{ - */ -#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */ -#define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number - * @{ - */ -#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ -#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ -#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ -#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state - * @{ - */ -#define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */ -#define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign - * @{ - */ -#define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative (among ADC selected offset number 1, 2, 3 or 4) */ -#define LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive (among ADC selected offset number 1, 2, 3 or 4) */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode - * @{ - */ -#define LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */ -#define LL_ADC_OFFSET_SATURATION_ENABLE (ADC_OFR1_SATEN) /*!< ADC offset saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */ -/** - * @} - */ -/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups - * @{ - */ -#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */ -#define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/ -#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number - * @{ - */ -#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ -#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ -#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ -#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ -#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ -#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ -#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ -#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ -#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ -#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ -#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ -#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ -#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ -#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ -#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ -#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ -#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ -#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ -#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ -#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 series, ADC channel available on all instances but ADC2. */ -#define LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC1 instance. */ -#define LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_4 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */ -#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 series, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */ -#define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 series, ADC channel available only on ADC1 instance. */ -#define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 series, ADC channel available only on ADC2 instance. */ -#define LL_ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC2 instance. */ -#define LL_ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */ -#define LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_5 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP4 availability */ -#define LL_ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP5 availability */ -#define LL_ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 series, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 & OPAMP6 availability */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source - * @{ - */ -#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< - ADC group regular conversion trigger internal: SW start. */ -#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM2_CH1 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM4_CH1 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM7_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM20_TRGO (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_TIM20_CH1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_TIM20_CH2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_TIM20_CH3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: external interrupt line 2. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_REG_TRIG_EXT_LPTIM_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group regular conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge - * @{ - */ -#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */ -#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */ -#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode - * @{ - */ -#define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME */ -#define LL_ADC_REG_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event. - Note: First conversion is using minimal sampling time (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME) */ -#define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events: - Trigger rising edge = start sampling - Trigger falling edge = stop sampling and start conversion */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode - * @{ - */ -#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */ -#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data - * @{ - */ -#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */ -#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ -#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ -/** - * @} - */ - -#if defined(ADC_SMPR1_SMPPLUS) -/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration - * @{ - */ -#define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL) /*!< ADC sampling time let to default settings. */ -#define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped with selection sampling time 2.5 ADC clock cycles, whatever channels mapped on ADC groups regular or injected). */ -/** - * @} - */ -#endif - -/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data - * @{ - */ -#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */ -#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length - * @{ - */ -#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode - * @{ - */ -#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */ -#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ -#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks - * @{ - */ -#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ -#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ -#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ -#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ -#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ -#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ -#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ -#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ -#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */ -#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */ -#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */ -#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */ -#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */ -#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */ -#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */ -#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source - * @{ - */ -#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< - ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ -#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Trigger available only on ADC3/4/5 instances. On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Trigger available only on ADC1/2 instances. On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ -#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: external interrupt line 3. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ -#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). - Note: On this STM32 series, this trigger is available only on ADC1/2 instances. */ -#define LL_ADC_INJ_TRIG_EXT_LPTIM_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< - ADC group injected conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge - * @{ - */ -#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */ -#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */ -#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode - * @{ - */ -#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ -#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode - * @{ - */ -#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */ -#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */ -#define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length - * @{ - */ -#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ -#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ -#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ -#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode - * @{ - */ -#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */ -#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks - * @{ - */ -#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */ -#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */ -#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */ -#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time - * @{ - */ -#define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 47.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 247.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending - * @{ - */ -#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ -#define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ -#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number - * @{ - */ -#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ -#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */ -#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels - * @{ - */ -#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */ -#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ -#define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ -#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ -#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */ -#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by group regular only */ -#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by group injected only */ -#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by group regular only */ -#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by group injected only */ -#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */ -#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */ -#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */ -#define LL_ADC_AWD_CH_VOPAMP1_REG ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by group regular only */ -#define LL_ADC_AWD_CH_VOPAMP1_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by group injected only */ -#define LL_ADC_AWD_CH_VOPAMP1_REG_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_VOPAMP2_REG ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by group regular only */ -#define LL_ADC_AWD_CH_VOPAMP2_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by group injected only */ -#define LL_ADC_AWD_CH_VOPAMP2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by group regular only */ -#define LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by group injected only */ -#define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by group regular only */ -#define LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by group injected only */ -#define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_VOPAMP4_REG ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by group regular only */ -#define LL_ADC_AWD_CH_VOPAMP4_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by group injected only */ -#define LL_ADC_AWD_CH_VOPAMP4_REG_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_VOPAMP5_REG ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by group regular only */ -#define LL_ADC_AWD_CH_VOPAMP5_INJ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by group injected only */ -#define LL_ADC_AWD_CH_VOPAMP5_REG_INJ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_VOPAMP6_REG ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by group regular only */ -#define LL_ADC_AWD_CH_VOPAMP6_INJ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by group injected only */ -#define LL_ADC_AWD_CH_VOPAMP6_REG_INJ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by either group regular or injected */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds - * @{ - */ -#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /*!< ADC analog watchdog threshold high */ -#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */ -#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config - * @{ - */ -#define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_2SAMPLES ( ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_3SAMPLES ( ADC_TR1_AWDFILT_1 ) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_4SAMPLES ( ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_TR1_AWDFILT_2 ) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 ) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_8SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope - * @{ - */ -#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */ -#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */ -#define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */ -#define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */ -#define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode - * @{ - */ -#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ -#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio - * @{ - */ -#define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift - * @{ - */ -#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ -/** - * @} - */ - -#if defined(ADC_MULTIMODE_SUPPORT) -/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode - * @{ - */ -#define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */ -#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ -#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */ -#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */ -#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ -#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ -#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ -#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer - * @{ - */ -#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ -#define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */ -#define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */ -#define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */ -#define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases - * @{ - */ -#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ -#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave - * @{ - */ -#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */ -#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */ -#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */ -/** - * @} - */ - -#endif /* ADC_MULTIMODE_SUPPORT */ - - -/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays - * @note Only ADC peripheral HW delays are defined in ADC LL driver driver, - * not timeout values. - * For details on delays values, refer to descriptions in source code - * above each literal definition. - * @{ - */ - -/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ -/* not timeout values. */ -/* Timeout values for ADC operations are dependent to device clock */ -/* configuration (system clock versus ADC clock), */ -/* and therefore must be defined in user application. */ -/* Indications for estimation of ADC timeout delays, for this */ -/* STM32 series: */ -/* - ADC calibration time: maximum delay is 112/fADC. */ -/* (refer to device datasheet, parameter "tCAL") */ -/* - ADC enable time: maximum delay is 1 conversion cycle. */ -/* (refer to device datasheet, parameter "tSTAB") */ -/* - ADC disable time: maximum delay should be a few ADC clock cycles */ -/* - ADC stop conversion time: maximum delay should be a few ADC clock */ -/* cycles */ -/* - ADC conversion time: duration depending on ADC clock and ADC */ -/* configuration. */ -/* (refer to device reference manual, section "Timing") */ - -/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */ -/* Delay set to maximum value (refer to device datasheet, */ -/* parameter "tADCVREG_STUP"). */ -/* Unit: us */ -#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */ - -/* Delay for internal voltage reference stabilization time. */ -/* Delay set to maximum value (refer to device datasheet, */ -/* parameter "tstart_vrefint"). */ -/* Unit: us */ -#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */ - -/* Delay for temperature sensor stabilization time. */ -/* Literal set to maximum value (refer to device datasheet, */ -/* parameter "tSTART"). */ -/* Unit: us */ -#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */ - -/* Delay required between ADC end of calibration and ADC enable. */ -/* Note: On this STM32 series, a minimum number of ADC clock cycles */ -/* are required between ADC end of calibration and ADC enable. */ -/* Wait time can be computed in user application by waiting for the */ -/* equivalent number of CPU cycles, by taking into account */ -/* ratio of CPU clock versus ADC clock prescalers. */ -/* Unit: ADC clock cycles. */ -#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */ - -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros - * @{ - */ - -/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in ADC register - * @param __INSTANCE__ ADC Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in ADC register - * @param __INSTANCE__ ADC Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro - * @{ - */ - -/** - * @brief Helper macro to get ADC channel number in decimal format - * from literals LL_ADC_CHANNEL_x. - * @note Example: - * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) - * will return decimal number "4". - * @note The input can be a value from functions where a channel - * number is returned, either defined with number - * or with bitfield (only one bit must be set). - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 (8) - * @arg @ref LL_ADC_CHANNEL_2 (8) - * @arg @ref LL_ADC_CHANNEL_3 (8) - * @arg @ref LL_ADC_CHANNEL_4 (8) - * @arg @ref LL_ADC_CHANNEL_5 (8) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (7) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref LL_ADC_CHANNEL_VBAT (6) - * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * @retval Value between Min_Data=0 and Max_Data=18 - */ -#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ - ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \ - ( \ - ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \ - ) \ - : \ - ( \ - (uint32_t)POSITION_VAL((__CHANNEL__)) \ - ) \ - ) - -/** - * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x - * from number in decimal format. - * @note Example: - * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) - * will return a data equivalent to "LL_ADC_CHANNEL_4". - * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 (8) - * @arg @ref LL_ADC_CHANNEL_2 (8) - * @arg @ref LL_ADC_CHANNEL_3 (8) - * @arg @ref LL_ADC_CHANNEL_4 (8) - * @arg @ref LL_ADC_CHANNEL_5 (8) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (7) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref LL_ADC_CHANNEL_VBAT (6) - * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - */ -#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - (((__DECIMAL_NB__) <= 9UL) ? \ - ( \ - ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ - (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ - (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ - ) \ - : \ - ( \ - ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ - (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ - (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ - ) \ - ) - -/** - * @brief Helper macro to determine whether the selected channel - * corresponds to literal definitions of driver. - * @note The different literal definitions of ADC channels are: - * - ADC internal channel: - * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... - * - ADC external channel (channel connected to a GPIO pin): - * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... - * @note The channel parameter must be a value defined from literal - * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, - * LL_ADC_CHANNEL_TEMPSENSOR, ...), - * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), - * must not be a value from functions where a channel number is - * returned from ADC registers, - * because internal and external channels share the same channel - * number in ADC registers. The differentiation is made only with - * parameters definitions of driver. - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 (8) - * @arg @ref LL_ADC_CHANNEL_2 (8) - * @arg @ref LL_ADC_CHANNEL_3 (8) - * @arg @ref LL_ADC_CHANNEL_4 (8) - * @arg @ref LL_ADC_CHANNEL_5 (8) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (7) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref LL_ADC_CHANNEL_VBAT (6) - * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). - * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. - */ -#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ - (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL) - -/** - * @brief Helper macro to convert a channel defined from parameter - * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, - * LL_ADC_CHANNEL_TEMPSENSOR, ...), - * to its equivalent parameter definition of a ADC external channel - * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). - * @note The channel parameter can be, additionally to a value - * defined from parameter definition of a ADC internal channel - * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), - * a value defined from parameter definition of - * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) - * or a value from functions where a channel number is returned - * from ADC registers. - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 (8) - * @arg @ref LL_ADC_CHANNEL_2 (8) - * @arg @ref LL_ADC_CHANNEL_3 (8) - * @arg @ref LL_ADC_CHANNEL_4 (8) - * @arg @ref LL_ADC_CHANNEL_5 (8) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (7) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref LL_ADC_CHANNEL_VBAT (6) - * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - */ -#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ - ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) - -/** - * @brief Helper macro to determine whether the internal channel - * selected is available on the ADC instance selected. - * @note The channel parameter must be a value defined from parameter - * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, - * LL_ADC_CHANNEL_TEMPSENSOR, ...), - * must not be a value defined from parameter definition of - * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) - * or a value from functions where a channel number is - * returned from ADC registers, - * because internal and external channels share the same channel - * number in ADC registers. The differentiation is made only with - * parameters definitions of driver. - * @param __ADC_INSTANCE__ ADC instance - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_VREFINT (7) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref LL_ADC_CHANNEL_VBAT (6) - * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. - * Value "1" if the internal channel selected is available on the ADC instance selected. - */ -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) -#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ - ((((__ADC_INSTANCE__) == ADC1) \ - &&( \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ - ) \ - ) \ - || \ - (((__ADC_INSTANCE__) == ADC2) \ - &&( \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \ - ) \ - ) \ - || \ - (((__ADC_INSTANCE__) == ADC3) \ - &&( \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ - ) \ - ) \ - || \ - (((__ADC_INSTANCE__) == ADC4) \ - &&( \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ - ) \ - ) \ - || \ - (((__ADC_INSTANCE__) == ADC5) \ - &&( \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP5) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC5) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP4) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ - ) \ - ) \ - ) -#elif defined(STM32G471xx) -#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ - ((((__ADC_INSTANCE__) == ADC1) \ - &&( \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ - ) \ - ) \ - || \ - (((__ADC_INSTANCE__) == ADC2) \ - &&( \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \ - ) \ - ) \ - || \ - (((__ADC_INSTANCE__) == ADC3) \ - &&( \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ - ) \ - ) \ - ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) -#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ - ((((__ADC_INSTANCE__) == ADC1) \ - &&( \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ - ) \ - ) \ - || \ - (((__ADC_INSTANCE__) == ADC2) \ - &&( \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \ - ) \ - ) \ - ) -#elif defined(STM32G491xx) || defined(STM32G4A1xx) -#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ - ((((__ADC_INSTANCE__) == ADC1) \ - &&( \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ - ) \ - ) \ - || \ - (((__ADC_INSTANCE__) == ADC2) \ - &&( \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \ - ) \ - ) \ - || \ - (((__ADC_INSTANCE__) == ADC3) \ - &&( \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ - ) \ - ) \ - ) -#endif - -/** - * @brief Helper macro to define ADC analog watchdog parameter: - * define a single channel to monitor with analog watchdog - * from sequencer channel and groups definition. - * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). - * Example: - * LL_ADC_SetAnalogWDMonitChannels( - * ADC1, LL_ADC_AWD1, - * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 (8) - * @arg @ref LL_ADC_CHANNEL_2 (8) - * @arg @ref LL_ADC_CHANNEL_3 (8) - * @arg @ref LL_ADC_CHANNEL_4 (8) - * @arg @ref LL_ADC_CHANNEL_5 (8) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (7) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref LL_ADC_CHANNEL_VBAT (6) - * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * @param __GROUP__ This parameter can be one of the following values: - * @arg @ref LL_ADC_GROUP_REGULAR - * @arg @ref LL_ADC_GROUP_INJECTED - * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_AWD_DISABLE - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ - * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0) - * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0) - * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG (0)(1) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ (0)(1) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG (0)(5) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ (0)(5) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5) - * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(6) - * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(6) - * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (6) - * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1) - * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1) - * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1) - * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2) - * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2) - * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2) - * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG (0)(2) - * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ (0)(2) - * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ (2) - * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG (0)(3) - * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ (0)(3) - * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ (3) - * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(5) - * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(5) - * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (5) - * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG (0)(5) - * @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ (0)(5) - * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ (5) - * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG (0)(4) - * @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ (0)(4) - * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ (4) - * - * (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - */ -#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ - (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ - ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ - : \ - ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ - ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \ - : \ - (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ - ) - -/** - * @brief Helper macro to set the value of ADC analog watchdog threshold high - * or low in function of ADC resolution, when ADC resolution is - * different of 12 bits. - * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds() - * or @ref LL_ADC_SetAnalogWDThresholds(). - * Example, with a ADC resolution of 8 bits, to set the value of - * analog watchdog threshold high (on 8 bits): - * LL_ADC_SetAnalogWDThresholds - * (< ADCx param >, - * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, ) - * ); - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ - ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) - -/** - * @brief Helper macro to get the value of ADC analog watchdog threshold high - * or low in function of ADC resolution, when ADC resolution is - * different of 12 bits. - * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). - * Example, with a ADC resolution of 8 bits, to get the value of - * analog watchdog threshold high (on 8 bits): - * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION - * (LL_ADC_RESOLUTION_8B, - * LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH) - * ); - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ - ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) - -/** - * @brief Helper macro to get the ADC analog watchdog threshold high - * or low from raw value containing both thresholds concatenated. - * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). - * Example, to get analog watchdog threshold high from the register raw value: - * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, ); - * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH - * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ - (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW) - -/** - * @brief Helper macro to set the ADC calibration value with both single ended - * and differential modes calibration factors concatenated. - * @note To be used with function @ref LL_ADC_SetCalibrationFactor(). - * Example, to set calibration factors single ended to 0x55 - * and differential ended to 0x2A: - * LL_ADC_SetCalibrationFactor( - * ADC1, - * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A)) - * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F - * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F - * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF - */ -#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \ - (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__)) - -#if defined(ADC_MULTIMODE_SUPPORT) -/** - * @brief Helper macro to get the ADC multimode conversion data of ADC master - * or ADC slave from raw value with both ADC conversion data concatenated. - * @note This macro is intended to be used when multimode transfer by DMA - * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). - * In this case the transferred data need to processed with this macro - * to separate the conversion data of ADC master and ADC slave. - * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: - * @arg @ref LL_ADC_MULTI_MASTER - * @arg @ref LL_ADC_MULTI_SLAVE - * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ - (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST) -#endif /* ADC_MULTIMODE_SUPPORT */ - -#if defined(ADC_MULTIMODE_SUPPORT) -/** - * @brief Helper macro to select, from a ADC instance, to which ADC instance - * it has a dependence in multimode (ADC master of the corresponding - * ADC common instance). - * @note In case of device with multimode available and a mix of - * ADC instances compliant and not compliant with multimode feature, - * ADC instances not compliant with multimode feature are - * considered as master instances (do not depend to - * any other ADC instance). - * @param __ADCx__ ADC instance - * @retval __ADCx__ ADC instance master of the corresponding ADC common instance - */ -#if defined(ADC5) -#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \ - ( ( ((__ADCx__) == ADC2) \ - )? \ - (ADC1) \ - : \ - ( ( ((__ADCx__) == ADC4) \ - )? \ - (ADC3) \ - : \ - (__ADCx__) \ - ) \ - ) -#else -#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \ - ( ( ((__ADCx__) == ADC2) \ - )? \ - (ADC1) \ - : \ - (__ADCx__) \ - ) -#endif /* ADC5 */ -#endif /* ADC_MULTIMODE_SUPPORT */ - -/** - * @brief Helper macro to select the ADC common instance - * to which is belonging the selected ADC instance. - * @note ADC common register instance can be used for: - * - Set parameters common to several ADC instances - * - Multimode (for devices with several ADC instances) - * Refer to functions having argument "ADCxy_COMMON" as parameter. - * @param __ADCx__ ADC instance - * @retval ADC common register instance - */ -#if defined(ADC345_COMMON) -#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ - ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \ - ? ( \ - (ADC12_COMMON) \ - ) \ - : \ - ( \ - (ADC345_COMMON) \ - ) \ - ) -#else -#define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON) -#endif /* ADC345_COMMON */ -/** - * @brief Helper macro to check if all ADC instances sharing the same - * ADC common instance are disabled. - * @note This check is required by functions with setting conditioned to - * ADC state: - * All ADC instances of the ADC common group must be disabled. - * Refer to functions having argument "ADCxy_COMMON" as parameter. - * @note On devices with only 1 ADC common instance, parameter of this macro - * is useless and can be ignored (parameter kept for compatibility - * with devices featuring several ADC common instances). - * @param __ADCXY_COMMON__ ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Value "0" if all ADC instances sharing the same ADC common instance - * are disabled. - * Value "1" if at least one ADC instance sharing the same ADC common instance - * is enabled. - */ -#if defined(ADC345_COMMON) -#if defined(ADC4) && defined(ADC5) -#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ - (((__ADCXY_COMMON__) == ADC12_COMMON) \ - ? ( \ - (LL_ADC_IsEnabled(ADC1) | \ - LL_ADC_IsEnabled(ADC2) ) \ - ) \ - : \ - ( \ - (LL_ADC_IsEnabled(ADC3) | \ - LL_ADC_IsEnabled(ADC4) | \ - LL_ADC_IsEnabled(ADC5) ) \ - ) \ - ) -#else -#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ - (((__ADCXY_COMMON__) == ADC12_COMMON) \ - ? ( \ - (LL_ADC_IsEnabled(ADC1) | \ - LL_ADC_IsEnabled(ADC2) ) \ - ) \ - : \ - (LL_ADC_IsEnabled(ADC3)) \ - ) -#endif /* ADC4 && ADC5 */ -#else -#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ - (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2)) -#endif - -/** - * @brief Helper macro to define the ADC conversion data full-scale digital - * value corresponding to the selected ADC resolution. - * @note ADC conversion data full-scale corresponds to voltage range - * determined by analog voltage references Vref+ and Vref- - * (refer to reference manual). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data) - */ -#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ - (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) - -/** - * @brief Helper macro to convert the ADC conversion data from - * a resolution to another resolution. - * @param __DATA__ ADC conversion data to be converted - * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted - * This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion - * This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval ADC conversion data to the requested resolution - */ -#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ - __ADC_RESOLUTION_CURRENT__,\ - __ADC_RESOLUTION_TARGET__) \ -(((__DATA__) \ - << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \ - >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \ -) - -/** - * @brief Helper macro to calculate the voltage (unit: mVolt) - * corresponding to a ADC conversion data (unit: digital value). - * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) - * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) - * (unit: digital value). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval ADC conversion data equivalent voltage value (unit: mVolt) - */ -#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ - __ADC_DATA__,\ - __ADC_RESOLUTION__) \ -((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ - / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ -) - -/** - * @brief Helper macro to calculate analog reference voltage (Vref+) - * (unit: mVolt) from ADC conversion data of internal voltage - * reference VrefInt. - * @note Computation is using VrefInt calibration value - * stored in system memory for each device during production. - * @note This voltage depends on user board environment: voltage level - * connected to pin Vref+. - * On devices with small package, the pin Vref+ is not present - * and internally bonded to pin Vdda. - * @note On this STM32 series, calibration data of internal voltage reference - * VrefInt corresponds to a resolution of 12 bits, - * this is the recommended ADC resolution to convert voltage of - * internal voltage reference VrefInt. - * Otherwise, this macro performs the processing to scale - * ADC conversion data to 12 bits. - * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) - * of internal voltage reference VrefInt (unit: digital value). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval Analog reference voltage (unit: mV) - */ -#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ - __ADC_RESOLUTION__) \ -(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ - / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_12B) \ -) - -/** - * @brief Helper macro to calculate the temperature (unit: degree Celsius) - * from ADC conversion data of internal temperature sensor. - * @note Computation is using temperature sensor calibration values - * stored in system memory for each device during production. - * @note Calculation formula: - * Temperature = ((TS_ADC_DATA - TS_CAL1) - * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) - * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP - * with TS_ADC_DATA = temperature sensor raw data measured by ADC - * Avg_Slope = (TS_CAL2 - TS_CAL1) - * / (TS_CAL2_TEMP - TS_CAL1_TEMP) - * TS_CAL1 = equivalent TS_ADC_DATA at temperature - * TEMP_DEGC_CAL1 (calibrated in factory) - * TS_CAL2 = equivalent TS_ADC_DATA at temperature - * TEMP_DEGC_CAL2 (calibrated in factory) - * Caution: Calculation relevancy under reserve that calibration - * parameters are correct (address and data). - * To calculate temperature using temperature sensor - * datasheet typical values (generic values less, therefore - * less accurate than calibrated values), - * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). - * @note As calculation input, the analog reference voltage (Vref+) must be - * defined as it impacts the ADC LSB equivalent voltage. - * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note On this STM32 series, calibration data of temperature sensor - * corresponds to a resolution of 12 bits, - * this is the recommended ADC resolution to convert voltage of - * temperature sensor. - * Otherwise, this macro performs the processing to scale - * ADC conversion data to 12 bits. - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) - * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal - * temperature sensor (unit: digital value). - * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature - * sensor voltage has been measured. - * This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval Temperature (unit: degree Celsius) - */ -#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ - __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ -(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_12B) \ - * (__VREFANALOG_VOLTAGE__)) \ - / TEMPSENSOR_CAL_VREFANALOG) \ - - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ - ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ - ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ - ) + TEMPSENSOR_CAL1_TEMP \ -) - -/** - * @brief Helper macro to calculate the temperature (unit: degree Celsius) - * from ADC conversion data of internal temperature sensor. - * @note Computation is using temperature sensor typical values - * (refer to device datasheet). - * @note Calculation formula: - * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) - * / Avg_Slope + CALx_TEMP - * with TS_ADC_DATA = temperature sensor raw data measured by ADC - * (unit: digital value) - * Avg_Slope = temperature sensor slope - * (unit: uV/Degree Celsius) - * TS_TYP_CALx_VOLT = temperature sensor digital value at - * temperature CALx_TEMP (unit: mV) - * Caution: Calculation relevancy under reserve the temperature sensor - * of the current device has characteristics in line with - * datasheet typical values. - * If temperature sensor calibration values are available on - * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), - * temperature calculation will be more accurate using - * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). - * @note As calculation input, the analog reference voltage (Vref+) must be - * defined as it impacts the ADC LSB equivalent voltage. - * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note ADC measurement data must correspond to a resolution of 12 bits - * (full scale digital value 4095). If not the case, the data must be - * preliminarily rescaled to an equivalent resolution of 12 bits. - * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). - * On STM32G4, refer to device datasheet parameter "Avg_Slope". - * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). - * On STM32G4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). - * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) - * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) - * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). - * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. - * This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval Temperature (unit: degree Celsius) - */ -#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ - __TEMPSENSOR_TYP_CALX_V__,\ - __TEMPSENSOR_CALX_TEMP__,\ - __VREFANALOG_VOLTAGE__,\ - __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ -(((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ - / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ - * 1000UL) \ - - \ - (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ - * 1000UL) \ - ) \ - ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \ - ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \ -) - -/** - * @} - */ - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions - * @{ - */ - -/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management - * @{ - */ -/* Note: LL ADC functions to set DMA transfer are located into sections of */ -/* configuration of ADC instance, groups and multimode (if available): */ -/* @ref LL_ADC_REG_SetDMATransfer(), ... */ - -/** - * @brief Function to help to configure DMA transfer from ADC: retrieve the - * ADC register address from ADC instance and a list of ADC registers - * intended to be used (most commonly) with DMA transfer. - * @note These ADC registers are data registers: - * when ADC conversion data is available in ADC data registers, - * ADC generates a DMA transfer request. - * @note This macro is intended to be used with LL DMA driver, refer to - * function "LL_DMA_ConfigAddresses()". - * Example: - * LL_DMA_ConfigAddresses(DMA1, - * LL_DMA_CHANNEL_1, - * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), - * (uint32_t)&< array or variable >, - * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); - * @note For devices with several ADC: in multimode, some devices - * use a different data register outside of ADC instance scope - * (common data register). This macro manages this register difference, - * only ADC instance has to be set as parameter. - * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n - * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n - * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr - * @param ADCx ADC instance - * @param Register This parameter can be one of the following values: - * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA - * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1) - * - * (1) Available on devices with several ADC instances. - * @retval ADC register address - */ -#if defined(ADC_MULTIMODE_SUPPORT) -__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) -{ - uint32_t data_reg_addr; - - if (Register == LL_ADC_DMA_REG_REGULAR_DATA) - { - /* Retrieve address of register DR */ - data_reg_addr = (uint32_t) &(ADCx->DR); - } - else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ - { - /* Retrieve address of register CDR */ - data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); - } - - return data_reg_addr; -} -#else -__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) -{ - /* Prevent unused argument(s) compilation warning */ - (void)(Register); - - /* Retrieve address of register DR */ - return (uint32_t) &(ADCx->DR); -} -#endif /* ADC_MULTIMODE_SUPPORT */ - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances - * @{ - */ - -/** - * @brief Set parameter common to several ADC: Clock source and prescaler. - * @note On this STM32 series, if ADC group injected is used, some - * clock ratio constraints between ADC clock and AHB clock - * must be respected. - * Refer to reference manual. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * All ADC instances of the ADC common group must be disabled. - * This check can be done with function @ref LL_ADC_IsEnabled() for each - * ADC instance or by using helper macro helper macro - * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). - * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n - * CCR PRESC LL_ADC_SetCommonClock - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param CommonClock This parameter can be one of the following values: - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) -{ - MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); -} - -/** - * @brief Get parameter common to several ADC: Clock source and prescaler. - * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n - * CCR PRESC LL_ADC_GetCommonClock - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 - */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC)); -} - -/** - * @brief Set parameter common to several ADC: measurement path to - * internal channels (VrefInt, temperature sensor, ...). - * Configure all paths (overwrite current configuration). - * @note One or several values can be selected. - * Example: (LL_ADC_PATH_INTERNAL_VREFINT | - * LL_ADC_PATH_INTERNAL_TEMPSENSOR) - * The values not selected are removed from configuration. - * @note Stabilization time of measurement path to internal channel: - * After enabling internal paths, before starting ADC conversion, - * a delay is required for internal voltage reference and - * temperature sensor stabilization time. - * Refer to device datasheet. - * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. - * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. - * @note ADC internal channel sampling time constraint: - * For ADC conversion of internal channels, - * a sampling time minimum value is required. - * Refer to device datasheet. - * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n - * CCR VSENSESEL LL_ADC_SetCommonPathInternalCh\n - * CCR VBATSEL LL_ADC_SetCommonPathInternalCh - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param PathInternal This parameter can be a combination of the following values: - * @arg @ref LL_ADC_PATH_INTERNAL_NONE - * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT - * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR - * @arg @ref LL_ADC_PATH_INTERNAL_VBAT - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) -{ - MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal); -} - -/** - * @brief Set parameter common to several ADC: measurement path to - * internal channels (VrefInt, temperature sensor, ...). - * Add paths to the current configuration. - * @note One or several values can be selected. - * Example: (LL_ADC_PATH_INTERNAL_VREFINT | - * LL_ADC_PATH_INTERNAL_TEMPSENSOR) - * @note Stabilization time of measurement path to internal channel: - * After enabling internal paths, before starting ADC conversion, - * a delay is required for internal voltage reference and - * temperature sensor stabilization time. - * Refer to device datasheet. - * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. - * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. - * @note ADC internal channel sampling time constraint: - * For ADC conversion of internal channels, - * a sampling time minimum value is required. - * Refer to device datasheet. - * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n - * CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd\n - * CCR VBATSEL LL_ADC_SetCommonPathInternalChAdd - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param PathInternal This parameter can be a combination of the following values: - * @arg @ref LL_ADC_PATH_INTERNAL_NONE - * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT - * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR - * @arg @ref LL_ADC_PATH_INTERNAL_VBAT - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) -{ - SET_BIT(ADCxy_COMMON->CCR, PathInternal); -} - -/** - * @brief Set parameter common to several ADC: measurement path to - * internal channels (VrefInt, temperature sensor, ...). - * Remove paths to the current configuration. - * @note One or several values can be selected. - * Example: (LL_ADC_PATH_INTERNAL_VREFINT | - * LL_ADC_PATH_INTERNAL_TEMPSENSOR) - * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n - * CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem\n - * CCR VBATSEL LL_ADC_SetCommonPathInternalChRem - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param PathInternal This parameter can be a combination of the following values: - * @arg @ref LL_ADC_PATH_INTERNAL_NONE - * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT - * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR - * @arg @ref LL_ADC_PATH_INTERNAL_VBAT - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) -{ - CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal); -} - -/** - * @brief Get parameter common to several ADC: measurement path to internal - * channels (VrefInt, temperature sensor, ...). - * @note One or several values can be selected. - * Example: (LL_ADC_PATH_INTERNAL_VREFINT | - * LL_ADC_PATH_INTERNAL_TEMPSENSOR) - * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n - * CCR VSENSESEL LL_ADC_GetCommonPathInternalCh\n - * CCR VBATSEL LL_ADC_GetCommonPathInternalCh - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Returned value can be a combination of the following values: - * @arg @ref LL_ADC_PATH_INTERNAL_NONE - * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT - * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR - * @arg @ref LL_ADC_PATH_INTERNAL_VBAT - */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance - * @{ - */ - -/** - * @brief Set ADC calibration factor in the mode single-ended - * or differential (for devices with differential mode available). - * @note This function is intended to set calibration parameters - * without having to perform a new calibration using - * @ref LL_ADC_StartCalibration(). - * @note For devices with differential mode available: - * Calibration of offset is specific to each of - * single-ended and differential modes - * (calibration factor must be specified for each of these - * differential modes, if used afterwards and if the application - * requires their calibration). - * @note In case of setting calibration factors of both modes single ended - * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED): - * both calibration factors must be concatenated. - * To perform this processing, use helper macro - * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(). - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be enabled, without calibration on going, without conversion - * on going on group regular. - * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n - * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor - * @param ADCx ADC instance - * @param SingleDiff This parameter can be one of the following values: - * @arg @ref LL_ADC_SINGLE_ENDED - * @arg @ref LL_ADC_DIFFERENTIAL_ENDED - * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED - * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor) -{ - MODIFY_REG(ADCx->CALFACT, - SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK, - CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S))); -} - -/** - * @brief Get ADC calibration factor in the mode single-ended - * or differential (for devices with differential mode available). - * @note Calibration factors are set by hardware after performing - * a calibration run using function @ref LL_ADC_StartCalibration(). - * @note For devices with differential mode available: - * Calibration of offset is specific to each of - * single-ended and differential modes - * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n - * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor - * @param ADCx ADC instance - * @param SingleDiff This parameter can be one of the following values: - * @arg @ref LL_ADC_SINGLE_ENDED - * @arg @ref LL_ADC_DIFFERENTIAL_ENDED - * @retval Value between Min_Data=0x00 and Max_Data=0x7F - */ -__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff) -{ - /* Retrieve bits with position in register depending on parameter */ - /* "SingleDiff". */ - /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ - /* containing other bits reserved for other purpose. */ - return (uint32_t)(READ_BIT(ADCx->CALFACT, - (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> - ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); -} - -/** - * @brief Set ADC resolution. - * Refer to reference manual for alignments formats - * dependencies to ADC resolutions. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on either groups regular or injected. - * @rmtoll CFGR RES LL_ADC_SetResolution - * @param ADCx ADC instance - * @param Resolution This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) -{ - MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution); -} - -/** - * @brief Get ADC resolution. - * Refer to reference manual for alignments formats - * dependencies to ADC resolutions. - * @rmtoll CFGR RES LL_ADC_GetResolution - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - */ -__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)); -} - -/** - * @brief Set ADC conversion data alignment. - * @note Refer to reference manual for alignments formats - * dependencies to ADC resolutions. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on either groups regular or injected. - * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment - * @param ADCx ADC instance - * @param DataAlignment This parameter can be one of the following values: - * @arg @ref LL_ADC_DATA_ALIGN_RIGHT - * @arg @ref LL_ADC_DATA_ALIGN_LEFT - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) -{ - MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment); -} - -/** - * @brief Get ADC conversion data alignment. - * @note Refer to reference manual for alignments formats - * dependencies to ADC resolutions. - * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_DATA_ALIGN_RIGHT - * @arg @ref LL_ADC_DATA_ALIGN_LEFT - */ -__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN)); -} - -/** - * @brief Set ADC low power mode. - * @note Description of ADC low power modes: - * - ADC low power mode "auto wait": Dynamic low power mode, - * ADC conversions occurrences are limited to the minimum necessary - * in order to reduce power consumption. - * New ADC conversion starts only when the previous - * unitary conversion data (for ADC group regular) - * or previous sequence conversions data (for ADC group injected) - * has been retrieved by user software. - * In the meantime, ADC remains idle: does not performs any - * other conversion. - * This mode allows to automatically adapt the ADC conversions - * triggers to the speed of the software that reads the data. - * Moreover, this avoids risk of overrun for low frequency - * applications. - * How to use this low power mode: - * - It is not recommended to use with interruption or DMA - * since these modes have to clear immediately the EOC flag - * (by CPU to free the IRQ pending event or by DMA). - * Auto wait will work but fort a very short time, discarding - * its intended benefit (except specific case of high load of CPU - * or DMA transfers which can justify usage of auto wait). - * - Do use with polling: 1. Start conversion, - * 2. Later on, when conversion data is needed: poll for end of - * conversion to ensure that conversion is completed and - * retrieve ADC conversion data. This will trig another - * ADC conversion start. - * - ADC low power mode "auto power-off" (feature available on - * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): - * the ADC automatically powers-off after a conversion and - * automatically wakes up when a new conversion is triggered - * (with startup time between trigger and start of sampling). - * This feature can be combined with low power mode "auto wait". - * @note With ADC low power mode "auto wait", the ADC conversion data read - * is corresponding to previous ADC conversion start, independently - * of delay during which ADC was idle. - * Therefore, the ADC conversion data may be outdated: does not - * correspond to the current voltage level on the selected - * ADC channel. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on either groups regular or injected. - * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode - * @param ADCx ADC instance - * @param LowPowerMode This parameter can be one of the following values: - * @arg @ref LL_ADC_LP_MODE_NONE - * @arg @ref LL_ADC_LP_AUTOWAIT - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode) -{ - MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode); -} - -/** - * @brief Get ADC low power mode: - * @note Description of ADC low power modes: - * - ADC low power mode "auto wait": Dynamic low power mode, - * ADC conversions occurrences are limited to the minimum necessary - * in order to reduce power consumption. - * New ADC conversion starts only when the previous - * unitary conversion data (for ADC group regular) - * or previous sequence conversions data (for ADC group injected) - * has been retrieved by user software. - * In the meantime, ADC remains idle: does not performs any - * other conversion. - * This mode allows to automatically adapt the ADC conversions - * triggers to the speed of the software that reads the data. - * Moreover, this avoids risk of overrun for low frequency - * applications. - * How to use this low power mode: - * - It is not recommended to use with interruption or DMA - * since these modes have to clear immediately the EOC flag - * (by CPU to free the IRQ pending event or by DMA). - * Auto wait will work but fort a very short time, discarding - * its intended benefit (except specific case of high load of CPU - * or DMA transfers which can justify usage of auto wait). - * - Do use with polling: 1. Start conversion, - * 2. Later on, when conversion data is needed: poll for end of - * conversion to ensure that conversion is completed and - * retrieve ADC conversion data. This will trig another - * ADC conversion start. - * - ADC low power mode "auto power-off" (feature available on - * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): - * the ADC automatically powers-off after a conversion and - * automatically wakes up when a new conversion is triggered - * (with startup time between trigger and start of sampling). - * This feature can be combined with low power mode "auto wait". - * @note With ADC low power mode "auto wait", the ADC conversion data read - * is corresponding to previous ADC conversion start, independently - * of delay during which ADC was idle. - * Therefore, the ADC conversion data may be outdated: does not - * correspond to the current voltage level on the selected - * ADC channel. - * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_LP_MODE_NONE - * @arg @ref LL_ADC_LP_AUTOWAIT - */ -__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY)); -} - -/** - * @brief Set ADC selected offset number 1, 2, 3 or 4. - * @note This function set the 2 items of offset configuration: - * - ADC channel to which the offset programmed will be applied - * (independently of channel mapped on ADC group regular - * or group injected) - * - Offset level (offset to be subtracted from the raw - * converted data). - * @note Caution: Offset format is dependent to ADC resolution: - * offset has to be left-aligned on bit 11, the LSB (right bits) - * are set to 0. - * @note This function enables the offset, by default. It can be forced - * to disable state using function LL_ADC_SetOffsetState(). - * @note If a channel is mapped on several offsets numbers, only the offset - * with the lowest value is considered for the subtraction. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on either groups regular or injected. - * @note On STM32G4, some fast channels are available: fast analog inputs - * coming from GPIO pads (ADC_IN1..5). - * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n - * OFR1 OFFSET1 LL_ADC_SetOffset\n - * OFR1 OFFSET1_EN LL_ADC_SetOffset\n - * OFR2 OFFSET2_CH LL_ADC_SetOffset\n - * OFR2 OFFSET2 LL_ADC_SetOffset\n - * OFR2 OFFSET2_EN LL_ADC_SetOffset\n - * OFR3 OFFSET3_CH LL_ADC_SetOffset\n - * OFR3 OFFSET3 LL_ADC_SetOffset\n - * OFR3 OFFSET3_EN LL_ADC_SetOffset\n - * OFR4 OFFSET4_CH LL_ADC_SetOffset\n - * OFR4 OFFSET4 LL_ADC_SetOffset\n - * OFR4 OFFSET4_EN LL_ADC_SetOffset - * @param ADCx ADC instance - * @param Offsety This parameter can be one of the following values: - * @arg @ref LL_ADC_OFFSET_1 - * @arg @ref LL_ADC_OFFSET_2 - * @arg @ref LL_ADC_OFFSET_3 - * @arg @ref LL_ADC_OFFSET_4 - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 (8) - * @arg @ref LL_ADC_CHANNEL_2 (8) - * @arg @ref LL_ADC_CHANNEL_3 (8) - * @arg @ref LL_ADC_CHANNEL_4 (8) - * @arg @ref LL_ADC_CHANNEL_5 (8) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (7) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref LL_ADC_CHANNEL_VBAT (6) - * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - - MODIFY_REG(*preg, - ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, - ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); -} - -/** - * @brief Get for the ADC selected offset number 1, 2, 3 or 4: - * Channel to which the offset programmed will be applied - * (independently of channel mapped on ADC group regular - * or group injected) - * @note Usage of the returned channel number: - * - To reinject this channel into another function LL_ADC_xxx: - * the returned channel number is only partly formatted on definition - * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared - * with parts of literals LL_ADC_CHANNEL_x or using - * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * Then the selected literal LL_ADC_CHANNEL_x can be used - * as parameter for another function. - * - To get the channel number in decimal format: - * process the returned value with the helper macro - * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * @note On STM32G4, some fast channels are available: fast analog inputs - * coming from GPIO pads (ADC_IN1..5). - * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n - * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n - * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n - * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel - * @param ADCx ADC instance - * @param Offsety This parameter can be one of the following values: - * @arg @ref LL_ADC_OFFSET_1 - * @arg @ref LL_ADC_OFFSET_2 - * @arg @ref LL_ADC_OFFSET_3 - * @arg @ref LL_ADC_OFFSET_4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 (8) - * @arg @ref LL_ADC_CHANNEL_2 (8) - * @arg @ref LL_ADC_CHANNEL_3 (8) - * @arg @ref LL_ADC_CHANNEL_4 (8) - * @arg @ref LL_ADC_CHANNEL_5 (8) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (7) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref LL_ADC_CHANNEL_VBAT (6) - * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety) -{ - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - - return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); -} - -/** - * @brief Get for the ADC selected offset number 1, 2, 3 or 4: - * Offset level (offset to be subtracted from the raw - * converted data). - * @note Caution: Offset format is dependent to ADC resolution: - * offset has to be left-aligned on bit 11, the LSB (right bits) - * are set to 0. - * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n - * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n - * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n - * OFR4 OFFSET4 LL_ADC_GetOffsetLevel - * @param ADCx ADC instance - * @param Offsety This parameter can be one of the following values: - * @arg @ref LL_ADC_OFFSET_1 - * @arg @ref LL_ADC_OFFSET_2 - * @arg @ref LL_ADC_OFFSET_3 - * @arg @ref LL_ADC_OFFSET_4 - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety) -{ - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - - return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1); -} - -/** - * @brief Set for the ADC selected offset number 1, 2, 3 or 4: - * force offset state disable or enable - * without modifying offset channel or offset value. - * @note This function should be needed only in case of offset to be - * enabled-disabled dynamically, and should not be needed in other cases: - * function LL_ADC_SetOffset() automatically enables the offset. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on either groups regular or injected. - * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n - * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n - * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n - * OFR4 OFFSET4_EN LL_ADC_SetOffsetState - * @param ADCx ADC instance - * @param Offsety This parameter can be one of the following values: - * @arg @ref LL_ADC_OFFSET_1 - * @arg @ref LL_ADC_OFFSET_2 - * @arg @ref LL_ADC_OFFSET_3 - * @arg @ref LL_ADC_OFFSET_4 - * @param OffsetState This parameter can be one of the following values: - * @arg @ref LL_ADC_OFFSET_DISABLE - * @arg @ref LL_ADC_OFFSET_ENABLE - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - - MODIFY_REG(*preg, - ADC_OFR1_OFFSET1_EN, - OffsetState); -} - -/** - * @brief Get for the ADC selected offset number 1, 2, 3 or 4: - * offset state disabled or enabled. - * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n - * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n - * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n - * OFR4 OFFSET4_EN LL_ADC_GetOffsetState - * @param ADCx ADC instance - * @param Offsety This parameter can be one of the following values: - * @arg @ref LL_ADC_OFFSET_1 - * @arg @ref LL_ADC_OFFSET_2 - * @arg @ref LL_ADC_OFFSET_3 - * @arg @ref LL_ADC_OFFSET_4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_OFFSET_DISABLE - * @arg @ref LL_ADC_OFFSET_ENABLE - */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety) -{ - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - - return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN); -} - -/** - * @brief Set for the ADC selected offset number 1, 2, 3 or 4: - * choose offset sign. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on either groups regular or injected. - * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign\n - * OFR2 OFFSETPOS LL_ADC_SetOffsetSign\n - * OFR3 OFFSETPOS LL_ADC_SetOffsetSign\n - * OFR4 OFFSETPOS LL_ADC_SetOffsetSign - * @param ADCx ADC instance - * @param Offsety This parameter can be one of the following values: - * @arg @ref LL_ADC_OFFSET_1 - * @arg @ref LL_ADC_OFFSET_2 - * @arg @ref LL_ADC_OFFSET_3 - * @arg @ref LL_ADC_OFFSET_4 - * @param OffsetSign This parameter can be one of the following values: - * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE - * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - - MODIFY_REG(*preg, - ADC_OFR1_OFFSETPOS, - OffsetSign); -} - -/** - * @brief Get for the ADC selected offset number 1, 2, 3 or 4: - * offset sign if positive or negative. - * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign\n - * OFR2 OFFSETPOS LL_ADC_GetOffsetSign\n - * OFR3 OFFSETPOS LL_ADC_GetOffsetSign\n - * OFR4 OFFSETPOS LL_ADC_GetOffsetSign - * @param ADCx ADC instance - * @param Offsety This parameter can be one of the following values: - * @arg @ref LL_ADC_OFFSET_1 - * @arg @ref LL_ADC_OFFSET_2 - * @arg @ref LL_ADC_OFFSET_3 - * @arg @ref LL_ADC_OFFSET_4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE - * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE - */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety) -{ - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - - return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS); -} - -/** - * @brief Set for the ADC selected offset number 1, 2, 3 or 4: - * choose offset saturation mode. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on either groups regular or injected. - * @rmtoll OFR1 SATEN LL_ADC_SetOffsetSaturation\n - * OFR2 SATEN LL_ADC_SetOffsetSaturation\n - * OFR3 SATEN LL_ADC_SetOffsetSaturation\n - * OFR4 SATEN LL_ADC_SetOffsetSaturation - * @param ADCx ADC instance - * @param Offsety This parameter can be one of the following values: - * @arg @ref LL_ADC_OFFSET_1 - * @arg @ref LL_ADC_OFFSET_2 - * @arg @ref LL_ADC_OFFSET_3 - * @arg @ref LL_ADC_OFFSET_4 - * @param OffsetSaturation This parameter can be one of the following values: - * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE - * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - - MODIFY_REG(*preg, - ADC_OFR1_SATEN, - OffsetSaturation); -} - -/** - * @brief Get for the ADC selected offset number 1, 2, 3 or 4: - * offset saturation if enabled or disabled. - * @rmtoll OFR1 SATEN LL_ADC_GetOffsetSaturation\n - * OFR2 SATEN LL_ADC_GetOffsetSaturation\n - * OFR3 SATEN LL_ADC_GetOffsetSaturation\n - * OFR4 SATEN LL_ADC_GetOffsetSaturation - * @param ADCx ADC instance - * @param Offsety This parameter can be one of the following values: - * @arg @ref LL_ADC_OFFSET_1 - * @arg @ref LL_ADC_OFFSET_2 - * @arg @ref LL_ADC_OFFSET_3 - * @arg @ref LL_ADC_OFFSET_4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE - * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE - */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety) -{ - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - - return (uint32_t) READ_BIT(*preg, ADC_OFR1_SATEN); -} - -/** - * @brief Set ADC gain compensation. - * @note This function set the gain compensation coefficient - * that is applied to raw converted data using the formula: - * DATA = DATA(raw) * (gain compensation coef) / 4096 - * @note This function enables the gain compensation if given - * coefficient is above 0, otherwise it disables it. - * @note Gain compensation when enabled is applied to all channels. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on either groups regular or injected. - * @rmtoll GCOMP GCOMPCOEFF LL_ADC_SetGainCompensation\n - * CFGR2 GCOMP LL_ADC_SetGainCompensation - * @param ADCx ADC instance - * @param GainCompensation This parameter can be: - * 0 Gain compensation will be disabled and value set to 0 - * 1 -> 16393 Gain compensation will be enabled with specified value - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t GainCompensation) -{ - MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF, GainCompensation); - MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_GCOMP, ((GainCompensation == 0UL) ? 0UL : 1UL) << ADC_CFGR2_GCOMP_Pos); -} - -/** - * @brief Get the ADC gain compensation value - * @rmtoll GCOMP GCOMPCOEFF LL_ADC_GetGainCompensation\n - * CFGR2 GCOMP LL_ADC_GetGainCompensation - * @param ADCx ADC instance - * @retval Returned value can be: - * 0 Gain compensation is disabled - * 1 -> 16393 Gain compensation is enabled with returned value - */ -__STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->CFGR2, ADC_CFGR2_GCOMP) == ADC_CFGR2_GCOMP) ? READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF) : 0UL); -} - -#if defined(ADC_SMPR1_SMPPLUS) -/** - * @brief Set ADC sampling time common configuration impacting - * settings of sampling time channel wise. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on either groups regular or injected. - * @rmtoll SMPR1 SMPPLUS LL_ADC_SetSamplingTimeCommonConfig - * @param ADCx ADC instance - * @param SamplingTimeCommonConfig This parameter can be one of the following values: - * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT - * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig) -{ - MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig); -} - -/** - * @brief Get ADC sampling time common configuration impacting - * settings of sampling time channel wise. - * @rmtoll SMPR1 SMPPLUS LL_ADC_GetSamplingTimeCommonConfig - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT - * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 - */ -__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS)); -} -#endif /* ADC_SMPR1_SMPPLUS */ - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular - * @{ - */ - -/** - * @brief Set ADC group regular conversion trigger source: - * internal (SW start) or from external peripheral (timer event, - * external interrupt line). - * @note On this STM32 series, setting trigger source to external trigger - * also set trigger polarity to rising edge - * (default setting for compatibility with some ADC on other - * STM32 families having this setting set by HW default value). - * In case of need to modify trigger edge, use - * function @ref LL_ADC_REG_SetTriggerEdge(). - * @note Availability of parameters of trigger sources from timer - * depends on timers availability on the selected device. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n - * CFGR EXTEN LL_ADC_REG_SetTriggerSource - * @param ADCx ADC instance - * @param TriggerSource This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_TRIG_SOFTWARE - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (1) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (1) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2 (1) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3 (1) - * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 - * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 - * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 - * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 - * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 - * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 - * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 - * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 - * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (1) - * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT - * - * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n - * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. - * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) -{ - MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource); -} - -/** - * @brief Get ADC group regular conversion trigger source: - * internal (SW start) or from external peripheral (timer event, - * external interrupt line). - * @note To determine whether group regular trigger source is - * internal (SW start) or external, without detail - * of which peripheral is selected as external trigger, - * (equivalent to - * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") - * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. - * @note Availability of parameters of trigger sources from timer - * depends on timers availability on the selected device. - * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n - * CFGR EXTEN LL_ADC_REG_GetTriggerSource - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_TRIG_SOFTWARE - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (1) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (1) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2 (1) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3 (1) - * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 - * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 - * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 - * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 - * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 - * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 - * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 - * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 - * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (1) - * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT - * - * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n - * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. - * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) -{ - __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); - - /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ - /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */ - uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); - - /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */ - /* to match with triggers literals definition. */ - return ((TriggerSource - & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL) - | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN) - ); -} - -/** - * @brief Get ADC group regular conversion trigger source internal (SW start) - * or external. - * @note In case of group regular trigger source set to external trigger, - * to determine which peripheral is selected as external trigger, - * use function @ref LL_ADC_REG_GetTriggerSource(). - * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart - * @param ADCx ADC instance - * @retval Value "0" if trigger source external trigger - * Value "1" if trigger source SW start. - */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); -} - -/** - * @brief Set ADC group regular conversion trigger polarity. - * @note Applicable only for trigger source set to external trigger. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge - * @param ADCx ADC instance - * @param ExternalTriggerEdge This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_TRIG_EXT_RISING - * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING - * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) -{ - MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge); -} - -/** - * @brief Get ADC group regular conversion trigger polarity. - * @note Applicable only for trigger source set to external trigger. - * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_TRIG_EXT_RISING - * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING - * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN)); -} - -/** - * @brief Set ADC sampling mode. - * @note This function set the ADC conversion sampling mode - * @note This mode applies to regular group only. - * @note Set sampling mode is applied to all conversion of regular group. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode\n - * CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode - * @param ADCx ADC instance - * @param SamplingMode This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL - * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB - * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode) -{ - MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode); -} - -/** - * @brief Get the ADC sampling mode - * @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode\n - * CFGR2 SMPTRIG LL_ADC_REG_GetSamplingMode - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL - * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB - * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG)); -} - -/** - * @brief Set ADC group regular sequencer length and scan direction. - * @note Description of ADC group regular sequencer features: - * - For devices with sequencer fully configurable - * (function "LL_ADC_REG_SetSequencerRanks()" available): - * sequencer length and each rank affectation to a channel - * are configurable. - * This function performs configuration of: - * - Sequence length: Number of ranks in the scan sequence. - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from rank 1 to rank n). - * Sequencer ranks are selected using - * function "LL_ADC_REG_SetSequencerRanks()". - * - For devices with sequencer not fully configurable - * (function "LL_ADC_REG_SetSequencerChannels()" available): - * sequencer length and each rank affectation to a channel - * are defined by channel number. - * This function performs configuration of: - * - Sequence length: Number of ranks in the scan sequence is - * defined by number of channels set in the sequence, - * rank of each channel is fixed by channel HW number. - * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from lowest channel number to - * highest channel number). - * Sequencer ranks are selected using - * function "LL_ADC_REG_SetSequencerChannels()". - * @note Sequencer disabled is equivalent to sequencer of 1 rank: - * ADC conversion on only 1 channel. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength - * @param ADCx ADC instance - * @param SequencerNbRanks This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) -{ - MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks); -} - -/** - * @brief Get ADC group regular sequencer length and scan direction. - * @note Description of ADC group regular sequencer features: - * - For devices with sequencer fully configurable - * (function "LL_ADC_REG_SetSequencerRanks()" available): - * sequencer length and each rank affectation to a channel - * are configurable. - * This function retrieves: - * - Sequence length: Number of ranks in the scan sequence. - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from rank 1 to rank n). - * Sequencer ranks are selected using - * function "LL_ADC_REG_SetSequencerRanks()". - * - For devices with sequencer not fully configurable - * (function "LL_ADC_REG_SetSequencerChannels()" available): - * sequencer length and each rank affectation to a channel - * are defined by channel number. - * This function retrieves: - * - Sequence length: Number of ranks in the scan sequence is - * defined by number of channels set in the sequence, - * rank of each channel is fixed by channel HW number. - * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from lowest channel number to - * highest channel number). - * Sequencer ranks are selected using - * function "LL_ADC_REG_SetSequencerChannels()". - * @note Sequencer disabled is equivalent to sequencer of 1 rank: - * ADC conversion on only 1 channel. - * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); -} - -/** - * @brief Set ADC group regular sequencer discontinuous mode: - * sequence subdivided and scan conversions interrupted every selected - * number of ranks. - * @note It is not possible to enable both ADC group regular - * continuous mode and sequencer discontinuous mode. - * @note It is not possible to enable both ADC auto-injected mode - * and ADC group regular sequencer discontinuous mode. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n - * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont - * @param ADCx ADC instance - * @param SeqDiscont This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE - * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK - * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) -{ - MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont); -} - -/** - * @brief Get ADC group regular sequencer discontinuous mode: - * sequence subdivided and scan conversions interrupted every selected - * number of ranks. - * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n - * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE - * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK - * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM)); -} - -/** - * @brief Set ADC group regular sequence: channel on the selected - * scan sequence rank. - * @note This function performs configuration of: - * - Channels ordering into each rank of scan sequence: - * whatever channel can be placed into whatever rank. - * @note On this STM32 series, ADC group regular sequencer is - * fully configurable: sequencer length and each rank - * affectation to a channel are configurable. - * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note On this STM32 series, to measure internal channels (VrefInt, - * TempSensor, ...), measurement paths to internal channels must be - * enabled separately. - * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n - * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n - * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n - * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n - * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n - * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n - * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n - * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n - * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n - * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n - * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n - * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n - * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n - * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n - * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n - * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_RANK_1 - * @arg @ref LL_ADC_REG_RANK_2 - * @arg @ref LL_ADC_REG_RANK_3 - * @arg @ref LL_ADC_REG_RANK_4 - * @arg @ref LL_ADC_REG_RANK_5 - * @arg @ref LL_ADC_REG_RANK_6 - * @arg @ref LL_ADC_REG_RANK_7 - * @arg @ref LL_ADC_REG_RANK_8 - * @arg @ref LL_ADC_REG_RANK_9 - * @arg @ref LL_ADC_REG_RANK_10 - * @arg @ref LL_ADC_REG_RANK_11 - * @arg @ref LL_ADC_REG_RANK_12 - * @arg @ref LL_ADC_REG_RANK_13 - * @arg @ref LL_ADC_REG_RANK_14 - * @arg @ref LL_ADC_REG_RANK_15 - * @arg @ref LL_ADC_REG_RANK_16 - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 (8) - * @arg @ref LL_ADC_CHANNEL_2 (8) - * @arg @ref LL_ADC_CHANNEL_3 (8) - * @arg @ref LL_ADC_CHANNEL_4 (8) - * @arg @ref LL_ADC_CHANNEL_5 (8) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (7) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref LL_ADC_CHANNEL_VBAT (6) - * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) -{ - /* Set bits with content of parameter "Channel" with bits position */ - /* in register and register position depending on parameter "Rank". */ - /* Parameters "Rank" and "Channel" are used with masks because containing */ - /* other bits reserved for other purpose. */ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); - - MODIFY_REG(*preg, - ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), - ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); -} - -/** - * @brief Get ADC group regular sequence: channel on the selected - * scan sequence rank. - * @note On this STM32 series, ADC group regular sequencer is - * fully configurable: sequencer length and each rank - * affectation to a channel are configurable. - * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note Usage of the returned channel number: - * - To reinject this channel into another function LL_ADC_xxx: - * the returned channel number is only partly formatted on definition - * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared - * with parts of literals LL_ADC_CHANNEL_x or using - * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * Then the selected literal LL_ADC_CHANNEL_x can be used - * as parameter for another function. - * - To get the channel number in decimal format: - * process the returned value with the helper macro - * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n - * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n - * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n - * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n - * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n - * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n - * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n - * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n - * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n - * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n - * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n - * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n - * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n - * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n - * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n - * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_RANK_1 - * @arg @ref LL_ADC_REG_RANK_2 - * @arg @ref LL_ADC_REG_RANK_3 - * @arg @ref LL_ADC_REG_RANK_4 - * @arg @ref LL_ADC_REG_RANK_5 - * @arg @ref LL_ADC_REG_RANK_6 - * @arg @ref LL_ADC_REG_RANK_7 - * @arg @ref LL_ADC_REG_RANK_8 - * @arg @ref LL_ADC_REG_RANK_9 - * @arg @ref LL_ADC_REG_RANK_10 - * @arg @ref LL_ADC_REG_RANK_11 - * @arg @ref LL_ADC_REG_RANK_12 - * @arg @ref LL_ADC_REG_RANK_13 - * @arg @ref LL_ADC_REG_RANK_14 - * @arg @ref LL_ADC_REG_RANK_15 - * @arg @ref LL_ADC_REG_RANK_16 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 (8) - * @arg @ref LL_ADC_CHANNEL_2 (8) - * @arg @ref LL_ADC_CHANNEL_3 (8) - * @arg @ref LL_ADC_CHANNEL_4 (8) - * @arg @ref LL_ADC_CHANNEL_5 (8) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (7) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref LL_ADC_CHANNEL_VBAT (6) - * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) -{ - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); - - return (uint32_t)((READ_BIT(*preg, - ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) - >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - ); -} - -/** - * @brief Set ADC continuous conversion mode on ADC group regular. - * @note Description of ADC continuous conversion mode: - * - single mode: one conversion per trigger - * - continuous mode: after the first trigger, following - * conversions launched successively automatically. - * @note It is not possible to enable both ADC group regular - * continuous mode and sequencer discontinuous mode. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode - * @param ADCx ADC instance - * @param Continuous This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_CONV_SINGLE - * @arg @ref LL_ADC_REG_CONV_CONTINUOUS - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) -{ - MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous); -} - -/** - * @brief Get ADC continuous conversion mode on ADC group regular. - * @note Description of ADC continuous conversion mode: - * - single mode: one conversion per trigger - * - continuous mode: after the first trigger, following - * conversions launched successively automatically. - * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_CONV_SINGLE - * @arg @ref LL_ADC_REG_CONV_CONTINUOUS - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT)); -} - -/** - * @brief Set ADC group regular conversion data transfer: no transfer or - * transfer by DMA, and DMA requests mode. - * @note If transfer by DMA selected, specifies the DMA requests - * mode: - * - Limited mode (One shot mode): DMA transfer requests are stopped - * when number of DMA data transfers (number of - * ADC conversions) is reached. - * This ADC mode is intended to be used with DMA mode non-circular. - * - Unlimited mode: DMA transfer requests are unlimited, - * whatever number of DMA data transfers (number of - * ADC conversions). - * This ADC mode is intended to be used with DMA mode circular. - * @note If ADC DMA requests mode is set to unlimited and DMA is set to - * mode non-circular: - * when DMA transfers size will be reached, DMA will stop transfers of - * ADC conversions data ADC will raise an overrun error - * (overrun flag and interruption if enabled). - * @note For devices with several ADC instances: ADC multimode DMA - * settings are available using function @ref LL_ADC_SetMultiDMATransfer(). - * @note To configure DMA source address (peripheral address), - * use function @ref LL_ADC_DMA_GetRegAddr(). - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on either groups regular or injected. - * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n - * CFGR DMACFG LL_ADC_REG_SetDMATransfer - * @param ADCx ADC instance - * @param DMATransfer This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE - * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED - * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) -{ - MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer); -} - -/** - * @brief Get ADC group regular conversion data transfer: no transfer or - * transfer by DMA, and DMA requests mode. - * @note If transfer by DMA selected, specifies the DMA requests - * mode: - * - Limited mode (One shot mode): DMA transfer requests are stopped - * when number of DMA data transfers (number of - * ADC conversions) is reached. - * This ADC mode is intended to be used with DMA mode non-circular. - * - Unlimited mode: DMA transfer requests are unlimited, - * whatever number of DMA data transfers (number of - * ADC conversions). - * This ADC mode is intended to be used with DMA mode circular. - * @note If ADC DMA requests mode is set to unlimited and DMA is set to - * mode non-circular: - * when DMA transfers size will be reached, DMA will stop transfers of - * ADC conversions data ADC will raise an overrun error - * (overrun flag and interruption if enabled). - * @note For devices with several ADC instances: ADC multimode DMA - * settings are available using function @ref LL_ADC_GetMultiDMATransfer(). - * @note To configure DMA source address (peripheral address), - * use function @ref LL_ADC_DMA_GetRegAddr(). - * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n - * CFGR DMACFG LL_ADC_REG_GetDMATransfer - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE - * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED - * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG)); -} - -/** - * @brief Set ADC group regular behavior in case of overrun: - * data preserved or overwritten. - * @note Compatibility with devices without feature overrun: - * other devices without this feature have a behavior - * equivalent to data overwritten. - * The default setting of overrun is data preserved. - * Therefore, for compatibility with all devices, parameter - * overrun should be set to data overwritten. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun - * @param ADCx ADC instance - * @param Overrun This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED - * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) -{ - MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun); -} - -/** - * @brief Get ADC group regular behavior in case of overrun: - * data preserved or overwritten. - * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED - * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected - * @{ - */ - -/** - * @brief Set ADC group injected conversion trigger source: - * internal (SW start) or from external peripheral (timer event, - * external interrupt line). - * @note On this STM32 series, setting trigger source to external trigger - * also set trigger polarity to rising edge - * (default setting for compatibility with some ADC on other - * STM32 families having this setting set by HW default value). - * In case of need to modify trigger edge, use - * function @ref LL_ADC_INJ_SetTriggerEdge(). - * @note Availability of parameters of trigger sources from timer - * depends on timers availability on the selected device. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must not be disabled. Can be enabled with or without conversion - * on going on either groups regular or injected. - * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n - * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource - * @param ADCx ADC instance - * @param TriggerSource This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 - * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT - * - * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n - * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. - * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) -{ - MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource); -} - -/** - * @brief Get ADC group injected conversion trigger source: - * internal (SW start) or from external peripheral (timer event, - * external interrupt line). - * @note To determine whether group injected trigger source is - * internal (SW start) or external, without detail - * of which peripheral is selected as external trigger, - * (equivalent to - * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") - * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. - * @note Availability of parameters of trigger sources from timer - * depends on timers availability on the selected device. - * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n - * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 - * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT - * - * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n - * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. - * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) -{ - __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); - - /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ - /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */ - uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); - - /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */ - /* to match with triggers literals definition. */ - return ((TriggerSource - & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL) - | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN) - ); -} - -/** - * @brief Get ADC group injected conversion trigger source internal (SW start) - or external - * @note In case of group injected trigger source set to external trigger, - * to determine which peripheral is selected as external trigger, - * use function @ref LL_ADC_INJ_GetTriggerSource. - * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart - * @param ADCx ADC instance - * @retval Value "0" if trigger source external trigger - * Value "1" if trigger source SW start. - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL); -} - -/** - * @brief Set ADC group injected conversion trigger polarity. - * Applicable only for trigger source set to external trigger. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must not be disabled. Can be enabled with or without conversion - * on going on either groups regular or injected. - * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge - * @param ADCx ADC instance - * @param ExternalTriggerEdge This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING - * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING - * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) -{ - MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge); -} - -/** - * @brief Get ADC group injected conversion trigger polarity. - * Applicable only for trigger source set to external trigger. - * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING - * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING - * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN)); -} - -/** - * @brief Set ADC group injected sequencer length and scan direction. - * @note This function performs configuration of: - * - Sequence length: Number of ranks in the scan sequence. - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from rank 1 to rank n). - * @note Sequencer disabled is equivalent to sequencer of 1 rank: - * ADC conversion on only 1 channel. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must not be disabled. Can be enabled with or without conversion - * on going on either groups regular or injected. - * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength - * @param ADCx ADC instance - * @param SequencerNbRanks This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) -{ - MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks); -} - -/** - * @brief Get ADC group injected sequencer length and scan direction. - * @note This function retrieves: - * - Sequence length: Number of ranks in the scan sequence. - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from rank 1 to rank n). - * @note Sequencer disabled is equivalent to sequencer of 1 rank: - * ADC conversion on only 1 channel. - * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); -} - -/** - * @brief Set ADC group injected sequencer discontinuous mode: - * sequence subdivided and scan conversions interrupted every selected - * number of ranks. - * @note It is not possible to enable both ADC group injected - * auto-injected mode and sequencer discontinuous mode. - * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont - * @param ADCx ADC instance - * @param SeqDiscont This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE - * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) -{ - MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont); -} - -/** - * @brief Get ADC group injected sequencer discontinuous mode: - * sequence subdivided and scan conversions interrupted every selected - * number of ranks. - * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE - * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN)); -} - -/** - * @brief Set ADC group injected sequence: channel on the selected - * sequence rank. - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note On this STM32 series, to measure internal channels (VrefInt, - * TempSensor, ...), measurement paths to internal channels must be - * enabled separately. - * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On STM32G4, some fast channels are available: fast analog inputs - * coming from GPIO pads (ADC_IN1..5). - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must not be disabled. Can be enabled with or without conversion - * on going on either groups regular or injected. - * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n - * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n - * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n - * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 (8) - * @arg @ref LL_ADC_CHANNEL_2 (8) - * @arg @ref LL_ADC_CHANNEL_3 (8) - * @arg @ref LL_ADC_CHANNEL_4 (8) - * @arg @ref LL_ADC_CHANNEL_5 (8) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (7) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref LL_ADC_CHANNEL_VBAT (6) - * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) -{ - /* Set bits with content of parameter "Channel" with bits position */ - /* in register depending on parameter "Rank". */ - /* Parameters "Rank" and "Channel" are used with masks because containing */ - /* other bits reserved for other purpose. */ - MODIFY_REG(ADCx->JSQR, - (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK), - ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)); -} - -/** - * @brief Get ADC group injected sequence: channel on the selected - * sequence rank. - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note Usage of the returned channel number: - * - To reinject this channel into another function LL_ADC_xxx: - * the returned channel number is only partly formatted on definition - * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared - * with parts of literals LL_ADC_CHANNEL_x or using - * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * Then the selected literal LL_ADC_CHANNEL_x can be used - * as parameter for another function. - * - To get the channel number in decimal format: - * process the returned value with the helper macro - * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n - * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n - * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n - * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 (8) - * @arg @ref LL_ADC_CHANNEL_2 (8) - * @arg @ref LL_ADC_CHANNEL_3 (8) - * @arg @ref LL_ADC_CHANNEL_4 (8) - * @arg @ref LL_ADC_CHANNEL_5 (8) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (7) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref LL_ADC_CHANNEL_VBAT (6) - * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) -{ - return (uint32_t)((READ_BIT(ADCx->JSQR, - (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) - >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - ); -} - -/** - * @brief Set ADC group injected conversion trigger: - * independent or from ADC group regular. - * @note This mode can be used to extend number of data registers - * updated after one ADC conversion trigger and with data - * permanently kept (not erased by successive conversions of scan of - * ADC sequencer ranks), up to 5 data registers: - * 1 data register on ADC group regular, 4 data registers - * on ADC group injected. - * @note If ADC group injected injected trigger source is set to an - * external trigger, this feature must be must be set to - * independent trigger. - * ADC group injected automatic trigger is compliant only with - * group injected trigger source set to SW start, without any - * further action on ADC group injected conversion start or stop: - * in this case, ADC group injected is controlled only - * from ADC group regular. - * @note It is not possible to enable both ADC group injected - * auto-injected mode and sequencer discontinuous mode. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on either groups regular or injected. - * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto - * @param ADCx ADC instance - * @param TrigAuto This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT - * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto) -{ - MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto); -} - -/** - * @brief Get ADC group injected conversion trigger: - * independent or from ADC group regular. - * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT - * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO)); -} - -/** - * @brief Set ADC group injected contexts queue mode. - * @note A context is a setting of group injected sequencer: - * - group injected trigger - * - sequencer length - * - sequencer ranks - * If contexts queue is disabled: - * - only 1 sequence can be configured - * and is active perpetually. - * If contexts queue is enabled: - * - up to 2 contexts can be queued - * and are checked in and out as a FIFO stack (first-in, first-out). - * - If a new context is set when queues is full, error is triggered - * by interruption "Injected Queue Overflow". - * - Two behaviors are possible when all contexts have been processed: - * the contexts queue can maintain the last context active perpetually - * or can be empty and injected group triggers are disabled. - * - Triggers can be only external (not internal SW start) - * - Caution: The sequence must be fully configured in one time - * (one write of register JSQR makes a check-in of a new context - * into the queue). - * Therefore functions to set separately injected trigger and - * sequencer channels cannot be used, register JSQR must be set - * using function @ref LL_ADC_INJ_ConfigQueueContext(). - * @note This parameter can be modified only when no conversion is on going - * on either groups regular or injected. - * @note A modification of the context mode (bit JQDIS) causes the contexts - * queue to be flushed and the register JSQR is cleared. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on either groups regular or injected. - * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n - * CFGR JQDIS LL_ADC_INJ_SetQueueMode - * @param ADCx ADC instance - * @param QueueMode This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_QUEUE_DISABLE - * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE - * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode) -{ - MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode); -} - -/** - * @brief Get ADC group injected context queue mode. - * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n - * CFGR JQDIS LL_ADC_INJ_GetQueueMode - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_INJ_QUEUE_DISABLE - * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE - * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS)); -} - -/** - * @brief Set one context on ADC group injected that will be checked in - * contexts queue. - * @note A context is a setting of group injected sequencer: - * - group injected trigger - * - sequencer length - * - sequencer ranks - * This function is intended to be used when contexts queue is enabled, - * because the sequence must be fully configured in one time - * (functions to set separately injected trigger and sequencer channels - * cannot be used): - * Refer to function @ref LL_ADC_INJ_SetQueueMode(). - * @note In the contexts queue, only the active context can be read. - * The parameters of this function can be read using functions: - * @arg @ref LL_ADC_INJ_GetTriggerSource() - * @arg @ref LL_ADC_INJ_GetTriggerEdge() - * @arg @ref LL_ADC_INJ_GetSequencerRanks() - * @note On this STM32 series, to measure internal channels (VrefInt, - * TempSensor, ...), measurement paths to internal channels must be - * enabled separately. - * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On STM32G4, some fast channels are available: fast analog inputs - * coming from GPIO pads (ADC_IN1..5). - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must not be disabled. Can be enabled with or without conversion - * on going on either groups regular or injected. - * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n - * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n - * JSQR JL LL_ADC_INJ_ConfigQueueContext\n - * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n - * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n - * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n - * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext - * @param ADCx ADC instance - * @param TriggerSource This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 - * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 - * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT - * - * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n - * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. - * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * @param ExternalTriggerEdge This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING - * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING - * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING - * - * Note: This parameter is discarded in case of SW start: - * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE". - * @param SequencerNbRanks This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS - * @param Rank1_Channel This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 (8) - * @arg @ref LL_ADC_CHANNEL_2 (8) - * @arg @ref LL_ADC_CHANNEL_3 (8) - * @arg @ref LL_ADC_CHANNEL_4 (8) - * @arg @ref LL_ADC_CHANNEL_5 (8) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (7) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref LL_ADC_CHANNEL_VBAT (6) - * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * @param Rank2_Channel This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 (8) - * @arg @ref LL_ADC_CHANNEL_2 (8) - * @arg @ref LL_ADC_CHANNEL_3 (8) - * @arg @ref LL_ADC_CHANNEL_4 (8) - * @arg @ref LL_ADC_CHANNEL_5 (8) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (7) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref LL_ADC_CHANNEL_VBAT (6) - * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * @param Rank3_Channel This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 (8) - * @arg @ref LL_ADC_CHANNEL_2 (8) - * @arg @ref LL_ADC_CHANNEL_3 (8) - * @arg @ref LL_ADC_CHANNEL_4 (8) - * @arg @ref LL_ADC_CHANNEL_5 (8) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (7) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref LL_ADC_CHANNEL_VBAT (6) - * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * @param Rank4_Channel This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 (8) - * @arg @ref LL_ADC_CHANNEL_2 (8) - * @arg @ref LL_ADC_CHANNEL_3 (8) - * @arg @ref LL_ADC_CHANNEL_4 (8) - * @arg @ref LL_ADC_CHANNEL_5 (8) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (7) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref LL_ADC_CHANNEL_VBAT (6) - * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, - uint32_t TriggerSource, - uint32_t ExternalTriggerEdge, - uint32_t SequencerNbRanks, - uint32_t Rank1_Channel, - uint32_t Rank2_Channel, - uint32_t Rank3_Channel, - uint32_t Rank4_Channel) -{ - /* Set bits with content of parameter "Rankx_Channel" with bits position */ - /* in register depending on literal "LL_ADC_INJ_RANK_x". */ - /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */ - /* because containing other bits reserved for other purpose. */ - /* If parameter "TriggerSource" is set to SW start, then parameter */ - /* "ExternalTriggerEdge" is discarded. */ - uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL); - MODIFY_REG(ADCx->JSQR, - ADC_JSQR_JEXTSEL | - ADC_JSQR_JEXTEN | - ADC_JSQR_JSQ4 | - ADC_JSQR_JSQ3 | - ADC_JSQR_JSQ2 | - ADC_JSQR_JSQ1 | - ADC_JSQR_JL, - (TriggerSource & ADC_JSQR_JEXTSEL) | - (ExternalTriggerEdge * (is_trigger_not_sw)) | - (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) | - (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) | - (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) | - (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) | - SequencerNbRanks - ); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels - * @{ - */ - -/** - * @brief Set sampling time of the selected ADC channel - * Unit: ADC clock cycles. - * @note On this device, sampling time is on channel scope: independently - * of channel mapped on ADC group regular or injected. - * @note In case of internal channel (VrefInt, TempSensor, ...) to be - * converted: - * sampling time constraints must be respected (sampling time can be - * adjusted in function of ADC clock frequency and sampling time - * setting). - * Refer to device datasheet for timings values (parameters TS_vrefint, - * TS_temp, ...). - * @note Conversion time is the addition of sampling time and processing time. - * On this STM32 series, ADC processing time is: - * - 12.5 ADC clock cycles at ADC resolution 12 bits - * - 10.5 ADC clock cycles at ADC resolution 10 bits - * - 8.5 ADC clock cycles at ADC resolution 8 bits - * - 6.5 ADC clock cycles at ADC resolution 6 bits - * @note In case of ADC conversion of internal channel (VrefInt, - * temperature sensor, ...), a sampling time minimum value - * is required. - * Refer to device datasheet. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on either groups regular or injected. - * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime - * @param ADCx ADC instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 (8) - * @arg @ref LL_ADC_CHANNEL_2 (8) - * @arg @ref LL_ADC_CHANNEL_3 (8) - * @arg @ref LL_ADC_CHANNEL_4 (8) - * @arg @ref LL_ADC_CHANNEL_5 (8) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (7) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref LL_ADC_CHANNEL_VBAT (6) - * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * @param SamplingTime This parameter can be one of the following values: - * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1) - * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5 - * - * (1) On some devices, ADC sampling time 2.5 ADC clock cycles - * can be replaced by 3.5 ADC clock cycles. - * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig(). - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) -{ - /* Set bits with content of parameter "SamplingTime" with bits position */ - /* in register and register position depending on parameter "Channel". */ - /* Parameter "Channel" is used with masks because containing */ - /* other bits reserved for other purpose. */ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); - - MODIFY_REG(*preg, - ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), - SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); -} - -/** - * @brief Get sampling time of the selected ADC channel - * Unit: ADC clock cycles. - * @note On this device, sampling time is on channel scope: independently - * of channel mapped on ADC group regular or injected. - * @note Conversion time is the addition of sampling time and processing time. - * On this STM32 series, ADC processing time is: - * - 12.5 ADC clock cycles at ADC resolution 12 bits - * - 10.5 ADC clock cycles at ADC resolution 10 bits - * - 8.5 ADC clock cycles at ADC resolution 8 bits - * - 6.5 ADC clock cycles at ADC resolution 6 bits - * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime - * @param ADCx ADC instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 (8) - * @arg @ref LL_ADC_CHANNEL_2 (8) - * @arg @ref LL_ADC_CHANNEL_3 (8) - * @arg @ref LL_ADC_CHANNEL_4 (8) - * @arg @ref LL_ADC_CHANNEL_5 (8) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (7) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) - * @arg @ref LL_ADC_CHANNEL_VBAT (6) - * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) - * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) - * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) - * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) - * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) - * - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. - * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1) - * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5 - * - * (1) On some devices, ADC sampling time 2.5 ADC clock cycles - * can be replaced by 3.5 ADC clock cycles. - * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig(). - */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) -{ - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); - - return (uint32_t)(READ_BIT(*preg, - ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)) - >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS) - ); -} - -/** - * @brief Set mode single-ended or differential input of the selected - * ADC channel. - * @note Channel ending is on channel scope: independently of channel mapped - * on ADC group regular or injected. - * In differential mode: Differential measurement is carried out - * between the selected channel 'i' (positive input) and - * channel 'i+1' (negative input). Only channel 'i' has to be - * configured, channel 'i+1' is configured automatically. - * @note Refer to Reference Manual to ensure the selected channel is - * available in differential mode. - * For example, internal channels (VrefInt, TempSensor, ...) are - * not available in differential mode. - * @note When configuring a channel 'i' in differential mode, - * the channel 'i+1' is not usable separately. - * @note On STM32G4, some channels are internally fixed to single-ended inputs - * configuration: - * - ADC1: Channels 12, 15, 16, 17 and 18 - * - ADC2: Channels 15, 17 and 18 - * - ADC3: Channels 12, 16, 17 and 18 (1) - * - ADC4: Channels 16, 17 and 18 (1) - * - ADC5: Channels 2, 3, 4, 16, 17 and 18 (1) - * (1) ADC3/4/5 are not available on all devices, refer to device datasheet - * for more details. - * @note For ADC channels configured in differential mode, both inputs - * should be biased at (Vref+)/2 +/-200mV. - * (Vref+ is the analog voltage reference) - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be ADC disabled. - * @note One or several values can be selected. - * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff - * @param ADCx ADC instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @param SingleDiff This parameter can be a combination of the following values: - * @arg @ref LL_ADC_SINGLE_ENDED - * @arg @ref LL_ADC_DIFFERENTIAL_ENDED - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) -{ - /* Bits for single or differential mode selection for each channel are set */ - /* to 1 only when the differential mode is selected, and to 0 when the */ - /* single mode is selected. */ - - if (SingleDiff == LL_ADC_DIFFERENTIAL_ENDED) - { - SET_BIT(ADCx->DIFSEL, - Channel & ADC_SINGLEDIFF_CHANNEL_MASK); - } - else - { - CLEAR_BIT(ADCx->DIFSEL, - Channel & ADC_SINGLEDIFF_CHANNEL_MASK); - } -} - -/** - * @brief Get mode single-ended or differential input of the selected - * ADC channel. - * @note When configuring a channel 'i' in differential mode, - * the channel 'i+1' is not usable separately. - * Therefore, to ensure a channel is configured in single-ended mode, - * the configuration of channel itself and the channel 'i-1' must be - * read back (to ensure that the selected channel channel has not been - * configured in differential mode by the previous channel). - * @note Refer to Reference Manual to ensure the selected channel is - * available in differential mode. - * For example, internal channels (VrefInt, TempSensor, ...) are - * not available in differential mode. - * @note When configuring a channel 'i' in differential mode, - * the channel 'i+1' is not usable separately. - * @note On STM32G4, some channels are internally fixed to single-ended inputs - * configuration: - * - ADC1: Channels 12, 15, 16, 17 and 18 - * - ADC2: Channels 15, 17 and 18 - * - ADC3: Channels 12, 16, 17 and 18 (1) - * - ADC4: Channels 16, 17 and 18 (1) - * - ADC5: Channels 2, 3, 4, 16, 17 and 18 (1) - * (1) ADC3/4/5 are not available on all devices, refer to device datasheet - * for more details. - * @note One or several values can be selected. In this case, the value - * returned is null if all channels are in single ended-mode. - * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff - * @param ADCx ADC instance - * @param Channel This parameter can be a combination of the following values: - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @retval 0: channel in single-ended mode, else: channel in differential mode - */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel) -{ - return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK))); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog - * @{ - */ - -/** - * @brief Set ADC analog watchdog monitored channels: - * a single channel, multiple channels or all channels, - * on ADC groups regular and-or injected. - * @note Once monitored channels are selected, analog watchdog - * is enabled. - * @note In case of need to define a single channel to monitor - * with analog watchdog from sequencer channel definition, - * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). - * @note On this STM32 series, there are 2 kinds of analog watchdog - * instance: - * - AWD standard (instance AWD1): - * - channels monitored: can monitor 1 channel or all channels. - * - groups monitored: ADC groups regular and-or injected. - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * - AWD flexible (instances AWD2, AWD3): - * - channels monitored: flexible on channels monitored, selection is - * channel wise, from from 1 to all channels. - * Specificity of this analog watchdog: Multiple channels can - * be selected. For example: - * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) - * - groups monitored: not selection possible (monitoring on both - * groups regular and injected). - * Channels selected are monitored on groups regular and injected: - * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters - * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) - * - resolution: resolution is limited to 8 bits: if ADC resolution is - * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits - * the 2 LSB are ignored. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on either groups regular or injected. - * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n - * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n - * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n - * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n - * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n - * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels - * @param ADCx ADC instance - * @param AWDy This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD1 - * @arg @ref LL_ADC_AWD2 - * @arg @ref LL_ADC_AWD3 - * @param AWDChannelGroup This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD_DISABLE - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ - * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0) - * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0) - * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG (0)(1) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ (0)(1) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG (0)(5) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ (0)(5) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5) - * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(6) - * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(6) - * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (6) - * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1) - * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1) - * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1) - * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2) - * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2) - * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2) - * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG (0)(2) - * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ (0)(2) - * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ (2) - * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG (0)(3) - * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ (0)(3) - * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ (3) - * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(5) - * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(5) - * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (5) - * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG (0)(5) - * @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ (0)(5) - * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ (5) - * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG (0)(4) - * @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ (0)(4) - * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ (4) - * - * (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n - * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n - * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n - * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n - * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n - * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n - * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n - * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup) -{ - /* Set bits with content of parameter "AWDChannelGroup" with bits position */ - /* in register and register position depending on parameter "AWDy". */ - /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ - /* containing other bits reserved for other purpose. */ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); - - MODIFY_REG(*preg, - (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), - AWDChannelGroup & AWDy); -} - -/** - * @brief Get ADC analog watchdog monitored channel. - * @note Usage of the returned channel number: - * - To reinject this channel into another function LL_ADC_xxx: - * the returned channel number is only partly formatted on definition - * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared - * with parts of literals LL_ADC_CHANNEL_x or using - * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * Then the selected literal LL_ADC_CHANNEL_x can be used - * as parameter for another function. - * - To get the channel number in decimal format: - * process the returned value with the helper macro - * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * Applicable only when the analog watchdog is set to monitor - * one channel. - * @note On this STM32 series, there are 2 kinds of analog watchdog - * instance: - * - AWD standard (instance AWD1): - * - channels monitored: can monitor 1 channel or all channels. - * - groups monitored: ADC groups regular and-or injected. - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * - AWD flexible (instances AWD2, AWD3): - * - channels monitored: flexible on channels monitored, selection is - * channel wise, from from 1 to all channels. - * Specificity of this analog watchdog: Multiple channels can - * be selected. For example: - * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) - * - groups monitored: not selection possible (monitoring on both - * groups regular and injected). - * Channels selected are monitored on groups regular and injected: - * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters - * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) - * - resolution: resolution is limited to 8 bits: if ADC resolution is - * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits - * the 2 LSB are ignored. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on either groups regular or injected. - * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n - * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n - * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n - * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n - * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n - * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels - * @param ADCx ADC instance - * @param AWDy This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD1 - * @arg @ref LL_ADC_AWD2 (1) - * @arg @ref LL_ADC_AWD3 (1) - * - * (1) On this AWD number, monitored channel can be retrieved - * if only 1 channel is programmed (or none or all channels). - * This function cannot retrieve monitored channel if - * multiple channels are programmed simultaneously - * by bitfield. - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_AWD_DISABLE - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) - * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) - * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ - * - * (0) On STM32G4, parameter available only on analog watchdog number: AWD1. - */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) -{ - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); - - uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & ADC_AWD_CR_ALL_CHANNEL_MASK); - - /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */ - /* (parameter value LL_ADC_AWD_DISABLE). */ - /* Else, the selected AWD is enabled and is monitoring a group of channels */ - /* or a single channel. */ - if (AnalogWDMonitChannels != 0UL) - { - if (AWDy == LL_ADC_AWD1) - { - if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL) - { - /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = ((AnalogWDMonitChannels - | (ADC_AWD_CR23_CHANNEL_MASK) - ) - & (~(ADC_CFGR_AWD1CH)) - ); - } - else - { - /* AWD monitoring a single channel */ - AnalogWDMonitChannels = (AnalogWDMonitChannels - | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos)) - ); - } - } - else - { - if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) - { - /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK - | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)) - ); - } - else - { - /* AWD monitoring a single channel */ - /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = (AnalogWDMonitChannels - | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) - | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos) - ); - } - } - } - - return AnalogWDMonitChannels; -} - -/** - * @brief Set ADC analog watchdog thresholds value of both thresholds - * high and low. - * @note If value of only one threshold high or low must be set, - * use function @ref LL_ADC_SetAnalogWDThresholds(). - * @note In case of ADC resolution different of 12 bits, - * analog watchdog thresholds data require a specific shift. - * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). - * @note On this STM32 series, there are 2 kinds of analog watchdog - * instance: - * - AWD standard (instance AWD1): - * - channels monitored: can monitor 1 channel or all channels. - * - groups monitored: ADC groups regular and-or injected. - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * - AWD flexible (instances AWD2, AWD3): - * - channels monitored: flexible on channels monitored, selection is - * channel wise, from from 1 to all channels. - * Specificity of this analog watchdog: Multiple channels can - * be selected. For example: - * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) - * - groups monitored: not selection possible (monitoring on both - * groups regular and injected). - * Channels selected are monitored on groups regular and injected: - * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters - * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) - * - resolution: resolution is limited to 8 bits: if ADC resolution is - * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits - * the 2 LSB are ignored. - * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are - * impacted: the comparison of analog watchdog thresholds is done on - * oversampling final computation (after ratio and shift application): - * ADC data register bitfield [15:4] (12 most significant bits). - * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n - * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n - * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n - * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n - * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n - * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds - * @param ADCx ADC instance - * @param AWDy This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD1 - * @arg @ref LL_ADC_AWD2 - * @arg @ref LL_ADC_AWD3 - * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF - * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval None - */ -__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, - uint32_t AWDThresholdLowValue) -{ - /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */ - /* position in register and register position depending on parameter */ - /* "AWDy". */ - /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ - /* containing other bits reserved for other purpose. */ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); - - MODIFY_REG(*preg, - ADC_TR1_HT1 | ADC_TR1_LT1, - (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue); -} - -/** - * @brief Set ADC analog watchdog threshold value of threshold - * high or low. - * @note If values of both thresholds high or low must be set, - * use function @ref LL_ADC_ConfigAnalogWDThresholds(). - * @note In case of ADC resolution different of 12 bits, - * analog watchdog thresholds data require a specific shift. - * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). - * @note On this STM32 series, there are 2 kinds of analog watchdog - * instance: - * - AWD standard (instance AWD1): - * - channels monitored: can monitor 1 channel or all channels. - * - groups monitored: ADC groups regular and-or injected. - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * - AWD flexible (instances AWD2, AWD3): - * - channels monitored: flexible on channels monitored, selection is - * channel wise, from from 1 to all channels. - * Specificity of this analog watchdog: Multiple channels can - * be selected. For example: - * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) - * - groups monitored: not selection possible (monitoring on both - * groups regular and injected). - * Channels selected are monitored on groups regular and injected: - * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters - * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) - * - resolution: resolution is limited to 8 bits: if ADC resolution is - * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits - * the 2 LSB are ignored. - * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are - * impacted: the comparison of analog watchdog thresholds is done on - * oversampling final computation (after ratio and shift application): - * ADC data register bitfield [15:4] (12 most significant bits). - * @note On this STM32 series, setting of this feature is not conditioned to - * ADC state: - * ADC can be disabled, enabled with or without conversion on going - * on either ADC groups regular or injected. - * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n - * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n - * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n - * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n - * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n - * TR3 LT3 LL_ADC_SetAnalogWDThresholds - * @param ADCx ADC instance - * @param AWDy This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD1 - * @arg @ref LL_ADC_AWD2 - * @arg @ref LL_ADC_AWD3 - * @param AWDThresholdsHighLow This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH - * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, - uint32_t AWDThresholdValue) -{ - /* Set bits with content of parameter "AWDThresholdValue" with bits */ - /* position in register and register position depending on parameters */ - /* "AWDThresholdsHighLow" and "AWDy". */ - /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ - /* containing other bits reserved for other purpose. */ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, - ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); - - MODIFY_REG(*preg, - AWDThresholdsHighLow, - AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)); -} - -/** - * @brief Get ADC analog watchdog threshold value of threshold high, - * threshold low or raw data with ADC thresholds high and low - * concatenated. - * @note If raw data with ADC thresholds high and low is retrieved, - * the data of each threshold high or low can be isolated - * using helper macro: - * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(). - * @note In case of ADC resolution different of 12 bits, - * analog watchdog thresholds data require a specific shift. - * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). - * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n - * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n - * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n - * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n - * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n - * TR3 LT3 LL_ADC_GetAnalogWDThresholds - * @param ADCx ADC instance - * @param AWDy This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD1 - * @arg @ref LL_ADC_AWD2 - * @arg @ref LL_ADC_AWD3 - * @param AWDThresholdsHighLow This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH - * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) -{ - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, - ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); - - return (uint32_t)(READ_BIT(*preg, - (AWDThresholdsHighLow | ADC_TR1_LT1)) - >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) - & ~(AWDThresholdsHighLow & ADC_TR1_LT1))); -} - -/** - * @brief Set ADC analog watchdog filtering configuration - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on either groups regular or injected. - * @note On this STM32 series, this feature is only available on first - * analog watchdog (AWD1) - * @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration - * @param ADCx ADC instance - * @param AWDy This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD1 - * @param FilteringConfig This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD_FILTERING_NONE - * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES - * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES - * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES - * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES - * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES - * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES - * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig) -{ - /* Prevent unused argument(s) compilation warning */ - (void)(AWDy); - MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT, FilteringConfig); -} - -/** - * @brief Get ADC analog watchdog filtering configuration - * @note On this STM32 series, this feature is only available on first - * analog watchdog (AWD1) - * @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration - * @param ADCx ADC instance - * @param AWDy This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD1 - * @retval Returned value can be: - * @arg @ref LL_ADC_AWD_FILTERING_NONE - * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES - * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES - * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES - * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES - * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES - * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES - * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES - */ -__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy) -{ - /* Prevent unused argument(s) compilation warning */ - (void)(AWDy); - return (uint32_t)(READ_BIT(ADCx->TR1, ADC_TR1_AWDFILT)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling - * @{ - */ - -/** - * @brief Set ADC oversampling scope: ADC groups regular and-or injected - * (availability of ADC group injected depends on STM32 families). - * @note If both groups regular and injected are selected, - * specify behavior of ADC group injected interrupting - * group regular: when ADC group injected is triggered, - * the oversampling on ADC group regular is either - * temporary stopped and continued, or resumed from start - * (oversampler buffer reset). - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on either groups regular or injected. - * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n - * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n - * CFGR2 ROVSM LL_ADC_SetOverSamplingScope - * @param ADCx ADC instance - * @param OvsScope This parameter can be one of the following values: - * @arg @ref LL_ADC_OVS_DISABLE - * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED - * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED - * @arg @ref LL_ADC_OVS_GRP_INJECTED - * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope) -{ - MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope); -} - -/** - * @brief Get ADC oversampling scope: ADC groups regular and-or injected - * (availability of ADC group injected depends on STM32 families). - * @note If both groups regular and injected are selected, - * specify behavior of ADC group injected interrupting - * group regular: when ADC group injected is triggered, - * the oversampling on ADC group regular is either - * temporary stopped and continued, or resumed from start - * (oversampler buffer reset). - * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n - * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n - * CFGR2 ROVSM LL_ADC_GetOverSamplingScope - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_OVS_DISABLE - * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED - * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED - * @arg @ref LL_ADC_OVS_GRP_INJECTED - * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED - */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM)); -} - -/** - * @brief Set ADC oversampling discontinuous mode (triggered mode) - * on the selected ADC group. - * @note Number of oversampled conversions are done either in: - * - continuous mode (all conversions of oversampling ratio - * are done from 1 trigger) - * - discontinuous mode (each conversion of oversampling ratio - * needs a trigger) - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @note On this STM32 series, oversampling discontinuous mode - * (triggered mode) can be used only when oversampling is - * set on group regular only and in resumed mode. - * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont - * @param ADCx ADC instance - * @param OverSamplingDiscont This parameter can be one of the following values: - * @arg @ref LL_ADC_OVS_REG_CONT - * @arg @ref LL_ADC_OVS_REG_DISCONT - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont) -{ - MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont); -} - -/** - * @brief Get ADC oversampling discontinuous mode (triggered mode) - * on the selected ADC group. - * @note Number of oversampled conversions are done either in: - * - continuous mode (all conversions of oversampling ratio - * are done from 1 trigger) - * - discontinuous mode (each conversion of oversampling ratio - * needs a trigger) - * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_OVS_REG_CONT - * @arg @ref LL_ADC_OVS_REG_DISCONT - */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS)); -} - -/** - * @brief Set ADC oversampling - * (impacting both ADC groups regular and injected) - * @note This function set the 2 items of oversampling configuration: - * - ratio - * - shift - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on either groups regular or injected. - * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n - * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift - * @param ADCx ADC instance - * @param Ratio This parameter can be one of the following values: - * @arg @ref LL_ADC_OVS_RATIO_2 - * @arg @ref LL_ADC_OVS_RATIO_4 - * @arg @ref LL_ADC_OVS_RATIO_8 - * @arg @ref LL_ADC_OVS_RATIO_16 - * @arg @ref LL_ADC_OVS_RATIO_32 - * @arg @ref LL_ADC_OVS_RATIO_64 - * @arg @ref LL_ADC_OVS_RATIO_128 - * @arg @ref LL_ADC_OVS_RATIO_256 - * @param Shift This parameter can be one of the following values: - * @arg @ref LL_ADC_OVS_SHIFT_NONE - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 - * @retval None - */ -__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift) -{ - MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio)); -} - -/** - * @brief Get ADC oversampling ratio - * (impacting both ADC groups regular and injected) - * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio - * @param ADCx ADC instance - * @retval Ratio This parameter can be one of the following values: - * @arg @ref LL_ADC_OVS_RATIO_2 - * @arg @ref LL_ADC_OVS_RATIO_4 - * @arg @ref LL_ADC_OVS_RATIO_8 - * @arg @ref LL_ADC_OVS_RATIO_16 - * @arg @ref LL_ADC_OVS_RATIO_32 - * @arg @ref LL_ADC_OVS_RATIO_64 - * @arg @ref LL_ADC_OVS_RATIO_128 - * @arg @ref LL_ADC_OVS_RATIO_256 - */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); -} - -/** - * @brief Get ADC oversampling shift - * (impacting both ADC groups regular and injected) - * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift - * @param ADCx ADC instance - * @retval Shift This parameter can be one of the following values: - * @arg @ref LL_ADC_OVS_SHIFT_NONE - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 - */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode - * @{ - */ - -#if defined(ADC_MULTIMODE_SUPPORT) -/** - * @brief Set ADC multimode configuration to operate in independent mode - * or multimode (for devices with several ADC instances). - * @note If multimode configuration: the selected ADC instance is - * either master or slave depending on hardware. - * Refer to reference manual. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * All ADC instances of the ADC common group must be disabled. - * This check can be done with function @ref LL_ADC_IsEnabled() for each - * ADC instance or by using helper macro - * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). - * @rmtoll CCR DUAL LL_ADC_SetMultimode - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param Multimode This parameter can be one of the following values: - * @arg @ref LL_ADC_MULTI_INDEPENDENT - * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT - * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL - * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT - * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN - * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM - * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT - * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode) -{ - MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode); -} - -/** - * @brief Get ADC multimode configuration to operate in independent mode - * or multimode (for devices with several ADC instances). - * @note If multimode configuration: the selected ADC instance is - * either master or slave depending on hardware. - * Refer to reference manual. - * @rmtoll CCR DUAL LL_ADC_GetMultimode - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_MULTI_INDEPENDENT - * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT - * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL - * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT - * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN - * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM - * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT - * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM - */ -__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); -} - -/** - * @brief Set ADC multimode conversion data transfer: no transfer - * or transfer by DMA. - * @note If ADC multimode transfer by DMA is not selected: - * each ADC uses its own DMA channel, with its individual - * DMA transfer settings. - * If ADC multimode transfer by DMA is selected: - * One DMA channel is used for both ADC (DMA of ADC master) - * Specifies the DMA requests mode: - * - Limited mode (One shot mode): DMA transfer requests are stopped - * when number of DMA data transfers (number of - * ADC conversions) is reached. - * This ADC mode is intended to be used with DMA mode non-circular. - * - Unlimited mode: DMA transfer requests are unlimited, - * whatever number of DMA data transfers (number of - * ADC conversions). - * This ADC mode is intended to be used with DMA mode circular. - * @note If ADC DMA requests mode is set to unlimited and DMA is set to - * mode non-circular: - * when DMA transfers size will be reached, DMA will stop transfers of - * ADC conversions data ADC will raise an overrun error - * (overrun flag and interruption if enabled). - * @note How to retrieve multimode conversion data: - * Whatever multimode transfer by DMA setting: using function - * @ref LL_ADC_REG_ReadMultiConversionData32(). - * If ADC multimode transfer by DMA is selected: conversion data - * is a raw data with ADC master and slave concatenated. - * A macro is available to get the conversion data of - * ADC master or ADC slave: see helper macro - * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * All ADC instances of the ADC common group must be disabled - * or enabled without conversion on going on group regular. - * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n - * CCR DMACFG LL_ADC_SetMultiDMATransfer - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param MultiDMATransfer This parameter can be one of the following values: - * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC - * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B - * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B - * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B - * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer) -{ - MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer); -} - -/** - * @brief Get ADC multimode conversion data transfer: no transfer - * or transfer by DMA. - * @note If ADC multimode transfer by DMA is not selected: - * each ADC uses its own DMA channel, with its individual - * DMA transfer settings. - * If ADC multimode transfer by DMA is selected: - * One DMA channel is used for both ADC (DMA of ADC master) - * Specifies the DMA requests mode: - * - Limited mode (One shot mode): DMA transfer requests are stopped - * when number of DMA data transfers (number of - * ADC conversions) is reached. - * This ADC mode is intended to be used with DMA mode non-circular. - * - Unlimited mode: DMA transfer requests are unlimited, - * whatever number of DMA data transfers (number of - * ADC conversions). - * This ADC mode is intended to be used with DMA mode circular. - * @note If ADC DMA requests mode is set to unlimited and DMA is set to - * mode non-circular: - * when DMA transfers size will be reached, DMA will stop transfers of - * ADC conversions data ADC will raise an overrun error - * (overrun flag and interruption if enabled). - * @note How to retrieve multimode conversion data: - * Whatever multimode transfer by DMA setting: using function - * @ref LL_ADC_REG_ReadMultiConversionData32(). - * If ADC multimode transfer by DMA is selected: conversion data - * is a raw data with ADC master and slave concatenated. - * A macro is available to get the conversion data of - * ADC master or ADC slave: see helper macro - * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). - * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n - * CCR DMACFG LL_ADC_GetMultiDMATransfer - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC - * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B - * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B - * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B - * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B - */ -__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG)); -} - -/** - * @brief Set ADC multimode delay between 2 sampling phases. - * @note The sampling delay range depends on ADC resolution: - * - ADC resolution 12 bits can have maximum delay of 12 cycles. - * - ADC resolution 10 bits can have maximum delay of 10 cycles. - * - ADC resolution 8 bits can have maximum delay of 8 cycles. - * - ADC resolution 6 bits can have maximum delay of 6 cycles. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * All ADC instances of the ADC common group must be disabled. - * This check can be done with function @ref LL_ADC_IsEnabled() for each - * ADC instance or by using helper macro helper macro - * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). - * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param MultiTwoSamplingDelay This parameter can be one of the following values: - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1) - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1) - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2) - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2) - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2) - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3) - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3) - * - * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n - * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n - * (3) Parameter available only if ADC resolution is 12 bits. - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay) -{ - MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay); -} - -/** - * @brief Get ADC multimode delay between 2 sampling phases. - * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1) - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1) - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2) - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2) - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2) - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3) - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3) - * - * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n - * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n - * (3) Parameter available only if ADC resolution is 12 bits. - */ -__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY)); -} -#endif /* ADC_MULTIMODE_SUPPORT */ - -/** - * @} - */ -/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance - * @{ - */ - -/** - * @brief Put ADC instance in deep power down state. - * @note In case of ADC calibration necessary: When ADC is in deep-power-down - * state, the internal analog calibration is lost. After exiting from - * deep power down, calibration must be relaunched or calibration factor - * (preliminarily saved) must be set back into calibration register. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be ADC disabled. - * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function, */ - /* to not interfere with bits with HW property "rs". */ - MODIFY_REG(ADCx->CR, - ADC_CR_BITS_PROPERTY_RS, - ADC_CR_DEEPPWD); -} - -/** - * @brief Disable ADC deep power down mode. - * @note In case of ADC calibration necessary: When ADC is in deep-power-down - * state, the internal analog calibration is lost. After exiting from - * deep power down, calibration must be relaunched or calibration factor - * (preliminarily saved) must be set back into calibration register. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be ADC disabled. - * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function, */ - /* to not interfere with bits with HW property "rs". */ - CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); -} - -/** - * @brief Get the selected ADC instance deep power down state. - * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled - * @param ADCx ADC instance - * @retval 0: deep power down is disabled, 1: deep power down is enabled. - */ -__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); -} - -/** - * @brief Enable ADC instance internal voltage regulator. - * @note On this STM32 series, after ADC internal voltage regulator enable, - * a delay for ADC internal voltage regulator stabilization - * is required before performing a ADC calibration or ADC enable. - * Refer to device datasheet, parameter tADCVREG_STUP. - * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be ADC disabled. - * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function, */ - /* to not interfere with bits with HW property "rs". */ - MODIFY_REG(ADCx->CR, - ADC_CR_BITS_PROPERTY_RS, - ADC_CR_ADVREGEN); -} - -/** - * @brief Disable ADC internal voltage regulator. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be ADC disabled. - * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS)); -} - -/** - * @brief Get the selected ADC instance internal voltage regulator state. - * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled - * @param ADCx ADC instance - * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. - */ -__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable the selected ADC instance. - * @note On this STM32 series, after ADC enable, a delay for - * ADC internal analog stabilization is required before performing a - * ADC conversion start. - * Refer to device datasheet, parameter tSTAB. - * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC - * is enabled and when conversion clock is active. - * (not only core clock: this ADC has a dual clock domain) - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be ADC disabled and ADC internal voltage regulator enabled. - * @rmtoll CR ADEN LL_ADC_Enable - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function, */ - /* to not interfere with bits with HW property "rs". */ - MODIFY_REG(ADCx->CR, - ADC_CR_BITS_PROPERTY_RS, - ADC_CR_ADEN); -} - -/** - * @brief Disable the selected ADC instance. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be not disabled. Must be enabled without conversion on going - * on either groups regular or injected. - * @rmtoll CR ADDIS LL_ADC_Disable - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function, */ - /* to not interfere with bits with HW property "rs". */ - MODIFY_REG(ADCx->CR, - ADC_CR_BITS_PROPERTY_RS, - ADC_CR_ADDIS); -} - -/** - * @brief Get the selected ADC instance enable state. - * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC - * is enabled and when conversion clock is active. - * (not only core clock: this ADC has a dual clock domain) - * @rmtoll CR ADEN LL_ADC_IsEnabled - * @param ADCx ADC instance - * @retval 0: ADC is disabled, 1: ADC is enabled. - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); -} - -/** - * @brief Get the selected ADC instance disable state. - * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing - * @param ADCx ADC instance - * @retval 0: no ADC disable command on going. - */ -__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); -} - -/** - * @brief Start ADC calibration in the mode single-ended - * or differential (for devices with differential mode available). - * @note On this STM32 series, a minimum number of ADC clock cycles - * are required between ADC end of calibration and ADC enable. - * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. - * @note For devices with differential mode available: - * Calibration of offset is specific to each of - * single-ended and differential modes - * (calibration run must be performed for each of these - * differential modes, if used afterwards and if the application - * requires their calibration). - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be ADC disabled. - * @rmtoll CR ADCAL LL_ADC_StartCalibration\n - * CR ADCALDIF LL_ADC_StartCalibration - * @param ADCx ADC instance - * @param SingleDiff This parameter can be one of the following values: - * @arg @ref LL_ADC_SINGLE_ENDED - * @arg @ref LL_ADC_DIFFERENTIAL_ENDED - * @retval None - */ -__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function, */ - /* to not interfere with bits with HW property "rs". */ - MODIFY_REG(ADCx->CR, - ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS, - ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK)); -} - -/** - * @brief Get ADC calibration state. - * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing - * @param ADCx ADC instance - * @retval 0: calibration complete, 1: calibration in progress. - */ -__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular - * @{ - */ - -/** - * @brief Start ADC group regular conversion. - * @note On this STM32 series, this function is relevant for both - * internal trigger (SW start) and external trigger: - * - If ADC trigger has been set to software start, ADC conversion - * starts immediately. - * - If ADC trigger has been set to external trigger, ADC conversion - * will start at next trigger event (on the selected trigger edge) - * following the ADC start conversion command. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be enabled without conversion on going on group regular, - * without conversion stop command on going on group regular, - * without ADC disable command on going. - * @rmtoll CR ADSTART LL_ADC_REG_StartConversion - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function, */ - /* to not interfere with bits with HW property "rs". */ - MODIFY_REG(ADCx->CR, - ADC_CR_BITS_PROPERTY_RS, - ADC_CR_ADSTART); -} - -/** - * @brief Stop ADC group regular conversion. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be enabled with conversion on going on group regular, - * without ADC disable command on going. - * @rmtoll CR ADSTP LL_ADC_REG_StopConversion - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function, */ - /* to not interfere with bits with HW property "rs". */ - MODIFY_REG(ADCx->CR, - ADC_CR_BITS_PROPERTY_RS, - ADC_CR_ADSTP); -} - -/** - * @brief Get ADC group regular conversion state. - * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing - * @param ADCx ADC instance - * @retval 0: no conversion is on going on ADC group regular. - */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); -} - -/** - * @brief Get ADC group regular command of conversion stop state - * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing - * @param ADCx ADC instance - * @retval 0: no command of conversion stop is on going on ADC group regular. - */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL); -} - -/** - * @brief Start ADC sampling phase for sampling time trigger mode - * @note This function is relevant only when - * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set - * using @ref LL_ADC_REG_SetSamplingMode - * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be enabled without conversion on going on group regular, - * without conversion stop command on going on group regular, - * without ADC disable command on going. - * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StartSamplingPhase - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG); -} - -/** - * @brief Stop ADC sampling phase for sampling time trigger mode and start conversion - * @note This function is relevant only when - * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set - * using @ref LL_ADC_REG_SetSamplingMode - * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source - * - @ref LL_ADC_REG_StartSamplingPhase has been called to start - * the sampling phase - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be enabled without conversion on going on group regular, - * without conversion stop command on going on group regular, - * without ADC disable command on going. - * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StopSamplingPhase - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * all ADC configurations: all ADC resolutions and - * all oversampling increased data width (for devices - * with feature oversampling). - * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * ADC resolution 12 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_REG_ReadConversionData32. - * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) -{ - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * ADC resolution 10 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_REG_ReadConversionData32. - * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x000 and Max_Data=0x3FF - */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) -{ - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * ADC resolution 8 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_REG_ReadConversionData32. - * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) -{ - return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * ADC resolution 6 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_REG_ReadConversionData32. - * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x00 and Max_Data=0x3F - */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) -{ - return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); -} - -#if defined(ADC_MULTIMODE_SUPPORT) -/** - * @brief Get ADC multimode conversion data of ADC master, ADC slave - * or raw data with ADC master and slave concatenated. - * @note If raw data with ADC master and slave concatenated is retrieved, - * a macro is available to get the conversion data of - * ADC master or ADC slave: see helper macro - * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). - * (however this macro is mainly intended for multimode - * transfer by DMA, because this function can do the same - * by getting multimode conversion data of ADC master or ADC slave - * separately). - * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n - * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32 - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param ConversionData This parameter can be one of the following values: - * @arg @ref LL_ADC_MULTI_MASTER - * @arg @ref LL_ADC_MULTI_SLAVE - * @arg @ref LL_ADC_MULTI_MASTER_SLAVE - * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) -{ - return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, - ConversionData) - >> (POSITION_VAL(ConversionData) & 0x1FUL) - ); -} -#endif /* ADC_MULTIMODE_SUPPORT */ - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected - * @{ - */ - -/** - * @brief Start ADC group injected conversion. - * @note On this STM32 series, this function is relevant for both - * internal trigger (SW start) and external trigger: - * - If ADC trigger has been set to software start, ADC conversion - * starts immediately. - * - If ADC trigger has been set to external trigger, ADC conversion - * will start at next trigger event (on the selected trigger edge) - * following the ADC start conversion command. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be enabled without conversion on going on group injected, - * without conversion stop command on going on group injected, - * without ADC disable command on going. - * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function, */ - /* to not interfere with bits with HW property "rs". */ - MODIFY_REG(ADCx->CR, - ADC_CR_BITS_PROPERTY_RS, - ADC_CR_JADSTART); -} - -/** - * @brief Stop ADC group injected conversion. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be enabled with conversion on going on group injected, - * without ADC disable command on going. - * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function, */ - /* to not interfere with bits with HW property "rs". */ - MODIFY_REG(ADCx->CR, - ADC_CR_BITS_PROPERTY_RS, - ADC_CR_JADSTP); -} - -/** - * @brief Get ADC group injected conversion state. - * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing - * @param ADCx ADC instance - * @retval 0: no conversion is on going on ADC group injected. - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); -} - -/** - * @brief Get ADC group injected command of conversion stop state - * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing - * @param ADCx ADC instance - * @retval 0: no command of conversion stop is on going on ADC group injected. - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL); -} - -/** - * @brief Get ADC group injected conversion data, range fit for - * all ADC configurations: all ADC resolutions and - * all oversampling increased data width (for devices - * with feature oversampling). - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n - * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n - * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n - * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) -{ - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); - - return (uint32_t)(READ_BIT(*preg, - ADC_JDR1_JDATA) - ); -} - -/** - * @brief Get ADC group injected conversion data, range fit for - * ADC resolution 12 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_INJ_ReadConversionData32. - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n - * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n - * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n - * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) -{ - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); - - return (uint16_t)(READ_BIT(*preg, - ADC_JDR1_JDATA) - ); -} - -/** - * @brief Get ADC group injected conversion data, range fit for - * ADC resolution 10 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_INJ_ReadConversionData32. - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n - * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n - * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n - * JDR4 JDATA LL_ADC_INJ_ReadConversionData10 - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @retval Value between Min_Data=0x000 and Max_Data=0x3FF - */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) -{ - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); - - return (uint16_t)(READ_BIT(*preg, - ADC_JDR1_JDATA) - ); -} - -/** - * @brief Get ADC group injected conversion data, range fit for - * ADC resolution 8 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_INJ_ReadConversionData32. - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n - * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n - * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n - * JDR4 JDATA LL_ADC_INJ_ReadConversionData8 - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) -{ - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); - - return (uint8_t)(READ_BIT(*preg, - ADC_JDR1_JDATA) - ); -} - -/** - * @brief Get ADC group injected conversion data, range fit for - * ADC resolution 6 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_INJ_ReadConversionData32. - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n - * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n - * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n - * JDR4 JDATA LL_ADC_INJ_ReadConversionData6 - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @retval Value between Min_Data=0x00 and Max_Data=0x3F - */ -__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) -{ - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); - - return (uint8_t)(READ_BIT(*preg, - ADC_JDR1_JDATA) - ); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management - * @{ - */ - -/** - * @brief Get flag ADC ready. - * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC - * is enabled and when conversion clock is active. - * (not only core clock: this ADC has a dual clock domain) - * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); -} - -/** - * @brief Get flag ADC group regular end of unitary conversion. - * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL); -} - -/** - * @brief Get flag ADC group regular end of sequence conversions. - * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL); -} - -/** - * @brief Get flag ADC group regular overrun. - * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL); -} - -/** - * @brief Get flag ADC group regular end of sampling phase. - * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); -} - -/** - * @brief Get flag ADC group injected end of unitary conversion. - * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL); -} - -/** - * @brief Get flag ADC group injected end of sequence conversions. - * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL); -} - -/** - * @brief Get flag ADC group injected contexts queue overflow. - * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL); -} - -/** - * @brief Get flag ADC analog watchdog 1 flag - * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1 - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL); -} - -/** - * @brief Get flag ADC analog watchdog 2. - * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2 - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL); -} - -/** - * @brief Get flag ADC analog watchdog 3. - * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3 - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); -} - -/** - * @brief Clear flag ADC ready. - * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC - * is enabled and when conversion clock is active. - * (not only core clock: this ADC has a dual clock domain) - * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY); -} - -/** - * @brief Clear flag ADC group regular end of unitary conversion. - * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC); -} - -/** - * @brief Clear flag ADC group regular end of sequence conversions. - * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS); -} - -/** - * @brief Clear flag ADC group regular overrun. - * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR); -} - -/** - * @brief Clear flag ADC group regular end of sampling phase. - * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP); -} - -/** - * @brief Clear flag ADC group injected end of unitary conversion. - * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC); -} - -/** - * @brief Clear flag ADC group injected end of sequence conversions. - * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS); -} - -/** - * @brief Clear flag ADC group injected contexts queue overflow. - * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF); -} - -/** - * @brief Clear flag ADC analog watchdog 1. - * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1); -} - -/** - * @brief Clear flag ADC analog watchdog 2. - * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2); -} - -/** - * @brief Clear flag ADC analog watchdog 3. - * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3); -} - -#if defined(ADC_MULTIMODE_SUPPORT) -/** - * @brief Get flag multimode ADC ready of the ADC master. - * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode ADC ready of the ADC slave. - * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master. - * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave. - * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master. - * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave. - * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode ADC group regular overrun of the ADC master. - * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode ADC group regular overrun of the ADC slave. - * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode ADC group regular end of sampling of the ADC master. - * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode ADC group regular end of sampling of the ADC slave. - * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master. - * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave. - * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. - * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave. - * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode ADC group injected context queue overflow of the ADC master. - * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave. - * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode ADC analog watchdog 1 of the ADC master. - * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1 - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode analog watchdog 1 of the ADC slave. - * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1 - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode ADC analog watchdog 2 of the ADC master. - * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2 - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave. - * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2 - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode ADC analog watchdog 3 of the ADC master. - * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3 - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL); -} - -/** - * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave. - * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3 - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL); -} -#endif /* ADC_MULTIMODE_SUPPORT */ - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_IT_Management ADC IT management - * @{ - */ - -/** - * @brief Enable ADC ready. - * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY); -} - -/** - * @brief Enable interruption ADC group regular end of unitary conversion. - * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_EOC); -} - -/** - * @brief Enable interruption ADC group regular end of sequence conversions. - * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_EOS); -} - -/** - * @brief Enable ADC group regular interruption overrun. - * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_OVR); -} - -/** - * @brief Enable interruption ADC group regular end of sampling. - * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP); -} - -/** - * @brief Enable interruption ADC group injected end of unitary conversion. - * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_JEOC); -} - -/** - * @brief Enable interruption ADC group injected end of sequence conversions. - * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_JEOS); -} - -/** - * @brief Enable interruption ADC group injected context queue overflow. - * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF); -} - -/** - * @brief Enable interruption ADC analog watchdog 1. - * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_AWD1); -} - -/** - * @brief Enable interruption ADC analog watchdog 2. - * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_AWD2); -} - -/** - * @brief Enable interruption ADC analog watchdog 3. - * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_AWD3); -} - -/** - * @brief Disable interruption ADC ready. - * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY); -} - -/** - * @brief Disable interruption ADC group regular end of unitary conversion. - * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC); -} - -/** - * @brief Disable interruption ADC group regular end of sequence conversions. - * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS); -} - -/** - * @brief Disable interruption ADC group regular overrun. - * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR); -} - -/** - * @brief Disable interruption ADC group regular end of sampling. - * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP); -} - -/** - * @brief Disable interruption ADC group regular end of unitary conversion. - * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC); -} - -/** - * @brief Disable interruption ADC group injected end of sequence conversions. - * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS); -} - -/** - * @brief Disable interruption ADC group injected context queue overflow. - * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF); -} - -/** - * @brief Disable interruption ADC analog watchdog 1. - * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1); -} - -/** - * @brief Disable interruption ADC analog watchdog 2. - * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2); -} - -/** - * @brief Disable interruption ADC analog watchdog 3. - * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3); -} - -/** - * @brief Get state of interruption ADC ready - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); -} - -/** - * @brief Get state of interruption ADC group regular end of unitary conversion - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL); -} - -/** - * @brief Get state of interruption ADC group regular end of sequence conversions - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL); -} - -/** - * @brief Get state of interruption ADC group regular overrun - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL); -} - -/** - * @brief Get state of interruption ADC group regular end of sampling - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); -} - -/** - * @brief Get state of interruption ADC group injected end of unitary conversion - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL); -} - -/** - * @brief Get state of interruption ADC group injected end of sequence conversions - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL); -} - -/** - * @brief Get state of interruption ADC group injected context queue overflow interrupt state - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL); -} - -/** - * @brief Get state of interruption ADC analog watchdog 1 - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1 - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL); -} - -/** - * @brief Get state of interruption Get ADC analog watchdog 2 - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2 - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL); -} - -/** - * @brief Get state of interruption Get ADC analog watchdog 3 - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3 - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -/* Initialization of some features of ADC common parameters and multimode */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); -ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); -void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); - -/* De-initialization of ADC instance, ADC group regular and ADC group injected */ -/* (availability of ADC group injected depends on STM32 families) */ -ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); - -/* Initialization of some features of ADC instance */ -ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); -void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); - -/* Initialization of some features of ADC instance and ADC group regular */ -ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); -void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); - -/* Initialization of some features of ADC instance and ADC group injected */ -ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); -void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32G4xx_LL_ADC_H */ diff --git a/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c b/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c deleted file mode 100644 index 47bfcbc..0000000 --- a/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c +++ /dev/null @@ -1,3682 +0,0 @@ -/** - ****************************************************************************** - * @file stm32g4xx_hal_adc.c - * @author MCD Application Team - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Converter (ADC) - * peripheral: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * + Peripheral State functions - * Other functions (extended functions) are available in file - * "stm32g4xx_hal_adc_ex.c". - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2019 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### ADC peripheral features ##### - ============================================================================== - [..] - (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. - - (+) Interrupt generation at the end of regular conversion and in case of - analog watchdog or overrun events. - - (+) Single and continuous conversion modes. - - (+) Scan mode for conversion of several channels sequentially. - - (+) Data alignment with in-built data coherency. - - (+) Programmable sampling time (channel wise) - - (+) External trigger (timer or EXTI) with configurable polarity - - (+) DMA request generation for transfer of conversions data of regular group. - - (+) Configurable delay between conversions in Dual interleaved mode. - - (+) ADC channels selectable single/differential input. - - (+) ADC offset shared on 4 offset instances. - (+) ADC gain compensation - - (+) ADC calibration - - (+) ADC conversion of regular group. - - (+) ADC supply requirements: 1.62 V to 3.6 V. - - (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to - Vdda or to an external voltage reference). - - - ##### How to use this driver ##### - ============================================================================== - [..] - - *** Configuration of top level parameters related to ADC *** - ============================================================ - [..] - - (#) Enable the ADC interface - (++) As prerequisite, ADC clock must be configured at RCC top level. - - (++) Two clock settings are mandatory: - (+++) ADC clock (core clock, also possibly conversion clock). - - (+++) ADC clock (conversions clock). - Two possible clock sources: synchronous clock derived from AHB clock - or asynchronous clock derived from system clock or PLL (output divider P) - running up to 75MHz. - - (+++) Example: - Into HAL_ADC_MspInit() (recommended code location) or with - other device clock parameters configuration: - (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory) - - RCC_ADCCLKSOURCE_PLL enable: (optional: if asynchronous clock selected) - (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit; - (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; - (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLL; - (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); - - (++) ADC clock source and clock prescaler are configured at ADC level with - parameter "ClockPrescaler" using function HAL_ADC_Init(). - - (#) ADC pins configuration - (++) Enable the clock for the ADC GPIOs - using macro __HAL_RCC_GPIOx_CLK_ENABLE() - (++) Configure these ADC pins in analog mode - using function HAL_GPIO_Init() - - (#) Optionally, in case of usage of ADC with interruptions: - (++) Configure the NVIC for ADC - using function HAL_NVIC_EnableIRQ(ADCx_IRQn) - (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() - into the function of corresponding ADC interruption vector - ADCx_IRQHandler(). - - (#) Optionally, in case of usage of DMA: - (++) Configure the DMA (DMA channel, mode normal or circular, ...) - using function HAL_DMA_Init(). - (++) Configure the NVIC for DMA - using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) - (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() - into the function of corresponding DMA interruption vector - DMAx_Channelx_IRQHandler(). - - *** Configuration of ADC, group regular, channels parameters *** - ================================================================ - [..] - - (#) Configure the ADC parameters (resolution, data alignment, ...) - and regular group parameters (conversion trigger, sequencer, ...) - using function HAL_ADC_Init(). - - (#) Configure the channels for regular group parameters (channel number, - channel rank into sequencer, ..., into regular group) - using function HAL_ADC_ConfigChannel(). - - (#) Optionally, configure the analog watchdog parameters (channels - monitored, thresholds, ...) - using function HAL_ADC_AnalogWDGConfig(). - - *** Execution of ADC conversions *** - ==================================== - [..] - - (#) Optionally, perform an automatic ADC calibration to improve the - conversion accuracy - using function HAL_ADCEx_Calibration_Start(). - - (#) ADC driver can be used among three modes: polling, interruption, - transfer by DMA. - - (++) ADC conversion by polling: - (+++) Activate the ADC peripheral and start conversions - using function HAL_ADC_Start() - (+++) Wait for ADC conversion completion - using function HAL_ADC_PollForConversion() - (+++) Retrieve conversion results - using function HAL_ADC_GetValue() - (+++) Stop conversion and disable the ADC peripheral - using function HAL_ADC_Stop() - - (++) ADC conversion by interruption: - (+++) Activate the ADC peripheral and start conversions - using function HAL_ADC_Start_IT() - (+++) Wait for ADC conversion completion by call of function - HAL_ADC_ConvCpltCallback() - (this function must be implemented in user program) - (+++) Retrieve conversion results - using function HAL_ADC_GetValue() - (+++) Stop conversion and disable the ADC peripheral - using function HAL_ADC_Stop_IT() - - (++) ADC conversion with transfer by DMA: - (+++) Activate the ADC peripheral and start conversions - using function HAL_ADC_Start_DMA() - (+++) Wait for ADC conversion completion by call of function - HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() - (these functions must be implemented in user program) - (+++) Conversion results are automatically transferred by DMA into - destination variable address. - (+++) Stop conversion and disable the ADC peripheral - using function HAL_ADC_Stop_DMA() - - [..] - - (@) Callback functions must be implemented in user program: - (+@) HAL_ADC_ErrorCallback() - (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) - (+@) HAL_ADC_ConvCpltCallback() - (+@) HAL_ADC_ConvHalfCpltCallback - - *** Deinitialization of ADC *** - ============================================================ - [..] - - (#) Disable the ADC interface - (++) ADC clock can be hard reset and disabled at RCC top level. - (++) Hard reset of ADC peripherals - using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). - (++) ADC clock disable - using the equivalent macro/functions as configuration step. - (+++) Example: - Into HAL_ADC_MspDeInit() (recommended code location) or with - other device clock parameters configuration: - (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; - (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock) - (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); - - (#) ADC pins configuration - (++) Disable the clock for the ADC GPIOs - using macro __HAL_RCC_GPIOx_CLK_DISABLE() - - (#) Optionally, in case of usage of ADC with interruptions: - (++) Disable the NVIC for ADC - using function HAL_NVIC_EnableIRQ(ADCx_IRQn) - - (#) Optionally, in case of usage of DMA: - (++) Deinitialize the DMA - using function HAL_DMA_Init(). - (++) Disable the NVIC for DMA - using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) - - [..] - - *** Callback registration *** - ============================================= - [..] - - The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, - allows the user to configure dynamically the driver callbacks. - Use Functions HAL_ADC_RegisterCallback() - to register an interrupt callback. - [..] - - Function HAL_ADC_RegisterCallback() allows to register following callbacks: - (+) ConvCpltCallback : ADC conversion complete callback - (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback - (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback - (+) ErrorCallback : ADC error callback - (+) InjectedConvCpltCallback : ADC group injected conversion complete callback - (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback - (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback - (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback - (+) EndOfSamplingCallback : ADC end of sampling callback - (+) MspInitCallback : ADC Msp Init callback - (+) MspDeInitCallback : ADC Msp DeInit callback - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - [..] - - Use function HAL_ADC_UnRegisterCallback to reset a callback to the default - weak function. - [..] - - HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) ConvCpltCallback : ADC conversion complete callback - (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback - (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback - (+) ErrorCallback : ADC error callback - (+) InjectedConvCpltCallback : ADC group injected conversion complete callback - (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback - (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback - (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback - (+) EndOfSamplingCallback : ADC end of sampling callback - (+) MspInitCallback : ADC Msp Init callback - (+) MspDeInitCallback : ADC Msp DeInit callback - [..] - - By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when - these callbacks are null (not registered beforehand). - [..] - - If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. - [..] - - Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only. - Exception done MspInit/MspDeInit functions that can be registered/unregistered - in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - [..] - - Then, the user first registers the MspInit/MspDeInit user callbacks - using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit() - or HAL_ADC_Init() function. - [..] - - When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32g4xx_hal.h" - -/** @addtogroup STM32G4xx_HAL_Driver - * @{ - */ - -/** @defgroup ADC ADC - * @brief ADC HAL module driver - * @{ - */ - -#ifdef HAL_ADC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup ADC_Private_Constants ADC Private Constants - * @{ - */ - -#define ADC_CFGR_FIELDS_1 ((ADC_CFGR_RES | ADC_CFGR_ALIGN |\ - ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ - ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\ - ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */ - -/* Timeout values for ADC operations (enable settling time, */ -/* disable settling time, ...). */ -/* Values defined to be higher than worst cases: low clock frequency, */ -/* maximum prescalers. */ -#define ADC_ENABLE_TIMEOUT (2UL) /*!< ADC enable time-out value */ -#define ADC_DISABLE_TIMEOUT (2UL) /*!< ADC disable time-out value */ - -/* Timeout to wait for current conversion on going to be completed. */ -/* Timeout fixed to longest ADC conversion possible, for 1 channel: */ -/* - maximum sampling time (640.5 adc_clk) */ -/* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */ -/* - System clock / ADC clock <= 4096 (hypothesis of maximum clock ratio) */ -/* - ADC oversampling ratio 256 */ -/* Calculation: 653 * 4096 * 256 CPU clock cycles max */ -/* Unit: cycles of CPU clock. */ -#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL) /*!< ADC conversion completion time-out value */ - - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Functions ADC Exported Functions - * @{ - */ - -/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief ADC Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the ADC. - (+) De-initialize the ADC. -@endverbatim - * @{ - */ - -/** - * @brief Initialize the ADC peripheral and regular group according to - * parameters specified in structure "ADC_InitTypeDef". - * @note As prerequisite, ADC clock must be configured at RCC top level - * (refer to description of RCC configuration for ADC - * in header of this file). - * @note Possibility to update parameters on the fly: - * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when - * coming from ADC state reset. Following calls to this function can - * be used to reconfigure some parameters of ADC_InitTypeDef - * structure on the fly, without modifying MSP configuration. If ADC - * MSP has to be modified again, HAL_ADC_DeInit() must be called - * before HAL_ADC_Init(). - * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure - * "ADC_InitTypeDef". - * @note This function configures the ADC within 2 scopes: scope of entire - * ADC and scope of regular group. For parameters details, see comments - * of structure "ADC_InitTypeDef". - * @note Parameters related to common ADC registers (ADC clock mode) are set - * only if all ADCs are disabled. - * If this is not the case, these common parameters setting are - * bypassed without error reporting: it can be the intended behaviour in - * case of update of a parameter of ADC_InitTypeDef on the fly, - * without disabling the other ADCs. - * @param hadc ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmpCFGR; - uint32_t tmp_adc_reg_is_conversion_on_going; - __IO uint32_t wait_loop_index = 0UL; - uint32_t tmp_adc_is_conversion_on_going_regular; - uint32_t tmp_adc_is_conversion_on_going_injected; - - /* Check ADC handle */ - if (hadc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); - assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); - assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); - assert_param(IS_ADC_GAIN_COMPENSATION(hadc->Init.GainCompensation)); - assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - assert_param(IS_ADC_EXTTRIG(hadc, hadc->Init.ExternalTrigConv)); - assert_param(IS_ADC_SAMPLINGMODE(hadc->Init.SamplingMode)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); - assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); - assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); - - if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) - { - assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); - - if (hadc->Init.DiscontinuousConvMode == ENABLE) - { - assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); - } - } - - /* DISCEN and CONT bits cannot be set at the same time */ - assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); - - /* Actions performed only if ADC is coming from state reset: */ - /* - Initialization of ADC MSP */ - if (hadc->State == HAL_ADC_STATE_RESET) - { -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - /* Init the ADC Callback settings */ - hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ - hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ - hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ - hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ - hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ - hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */ - hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */ - hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */ - hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */ - - if (hadc->MspInitCallback == NULL) - { - hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ - } - - /* Init the low level hardware */ - hadc->MspInitCallback(hadc); -#else - /* Init the low level hardware */ - HAL_ADC_MspInit(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Initialize Lock */ - hadc->Lock = HAL_UNLOCKED; - } - - /* - Exit from deep-power-down mode and ADC voltage regulator enable */ - if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) - { - /* Disable ADC deep power down mode */ - LL_ADC_DisableDeepPowerDown(hadc->Instance); - - /* System was in deep power down mode, calibration must - be relaunched or a previously saved calibration factor - re-applied once the ADC voltage regulator is enabled */ - } - - if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) - { - /* Enable ADC internal voltage regulator */ - LL_ADC_EnableInternalRegulator(hadc->Instance); - - /* Note: Variable divided by 2 to compensate partially */ - /* CPU processing cycles, scaling in us split to not */ - /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); - while (wait_loop_index != 0UL) - { - wait_loop_index--; - } - } - - /* Verification that ADC voltage regulator is correctly enabled, whether */ - /* or not ADC is coming from state reset (if any potential problem of */ - /* clocking, voltage regulator would not be enabled). */ - if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - tmp_hal_status = HAL_ERROR; - } - - /* Configuration of ADC parameters if previous preliminary actions are */ - /* correctly completed and if there is no conversion on going on regular */ - /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ - /* called to update a parameter on the fly). */ - tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); - - if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) - && (tmp_adc_reg_is_conversion_on_going == 0UL) - ) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY, - HAL_ADC_STATE_BUSY_INTERNAL); - - /* Configuration of common ADC parameters */ - - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated only when ADC is disabled: */ - /* - clock configuration */ - if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - { - if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) - { - /* Reset configuration of ADC common register CCR: */ - /* */ - /* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */ - /* according to adc->Init.ClockPrescaler. It selects the clock */ - /* source and sets the clock division factor. */ - /* */ - /* Some parameters of this register are not reset, since they are set */ - /* by other functions and must be kept in case of usage of this */ - /* function on the fly (update of a parameter of ADC_InitTypeDef */ - /* without needing to reconfigure all other ADC groups/channels */ - /* parameters): */ - /* - when multimode feature is available, multimode-related */ - /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ - /* HAL_ADCEx_MultiModeConfigChannel() ) */ - /* - internal measurement paths: Vbat, temperature sensor, Vref */ - /* (set into HAL_ADC_ConfigChannel() or */ - /* HAL_ADCEx_InjectedConfigChannel() ) */ - LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); - } - } - - /* Configuration of ADC: */ - /* - resolution Init.Resolution */ - /* - data alignment Init.DataAlign */ - /* - external trigger to start conversion Init.ExternalTrigConv */ - /* - external trigger polarity Init.ExternalTrigConvEdge */ - /* - continuous conversion mode Init.ContinuousConvMode */ - /* - overrun Init.Overrun */ - /* - discontinuous mode Init.DiscontinuousConvMode */ - /* - discontinuous mode channel count Init.NbrOfDiscConversion */ - tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | - hadc->Init.Overrun | - hadc->Init.DataAlign | - hadc->Init.Resolution | - ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); - - if (hadc->Init.DiscontinuousConvMode == ENABLE) - { - tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); - } - - /* Enable external trigger if trigger selection is different of software */ - /* start. */ - /* Note: This configuration keeps the hardware feature of parameter */ - /* ExternalTrigConvEdge "trigger edge none" equivalent to */ - /* software start. */ - if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) - { - tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) - | hadc->Init.ExternalTrigConvEdge - ); - } - - /* Update Configuration Register CFGR */ - MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); - - /* Configuration of sampling mode */ - MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode); - - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated when ADC is disabled or enabled without */ - /* conversion on going on regular and injected groups: */ - /* - Gain Compensation Init.GainCompensation */ - /* - DMA continuous request Init.DMAContinuousRequests */ - /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ - /* - Oversampling parameters Init.Oversampling */ - tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); - tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - if ((tmp_adc_is_conversion_on_going_regular == 0UL) - && (tmp_adc_is_conversion_on_going_injected == 0UL) - ) - { - tmpCFGR = (ADC_CFGR_DFSDM(hadc) | - ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | - ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); - - MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); - - if (hadc->Init.GainCompensation != 0UL) - { - SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP); - MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation); - } - else - { - CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP); - MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL); - } - - if (hadc->Init.OversamplingMode == ENABLE) - { - assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio)); - assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); - assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); - assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset)); - - /* Configuration of Oversampler: */ - /* - Oversampling Ratio */ - /* - Right bit shift */ - /* - Triggered mode */ - /* - Oversampling mode (continued/resumed) */ - MODIFY_REG(hadc->Instance->CFGR2, - ADC_CFGR2_OVSR | - ADC_CFGR2_OVSS | - ADC_CFGR2_TROVS | - ADC_CFGR2_ROVSM, - ADC_CFGR2_ROVSE | - hadc->Init.Oversampling.Ratio | - hadc->Init.Oversampling.RightBitShift | - hadc->Init.Oversampling.TriggeredMode | - hadc->Init.Oversampling.OversamplingStopReset - ); - } - else - { - /* Disable ADC oversampling scope on ADC group regular */ - CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); - } - - } - - /* Configuration of regular group sequencer: */ - /* - if scan mode is disabled, regular channels sequence length is set to */ - /* 0x00: 1 channel converted (channel on regular rank 1) */ - /* Parameter "NbrOfConversion" is discarded. */ - /* Note: Scan mode is not present by hardware on this device, but */ - /* emulated by software for alignment over all STM32 devices. */ - /* - if scan mode is enabled, regular channels sequence length is set to */ - /* parameter "NbrOfConversion". */ - - if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) - { - /* Set number of ranks in regular group sequencer */ - MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); - } - else - { - CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); - } - - /* Initialize the ADC state */ - /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - tmp_hal_status = HAL_ERROR; - } - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Deinitialize the ADC peripheral registers to their default reset - * values, with deinitialization of the ADC MSP. - * @note For devices with several ADCs: reset of ADC common registers is done - * only if all ADCs sharing the same common group are disabled. - * (function "HAL_ADC_MspDeInit()" is also called under the same conditions: - * all ADC instances use the same core clock at RCC level, disabling - * the core clock reset all ADC instances). - * If this is not the case, reset of these common parameters reset is - * bypassed without error reporting: it can be the intended behavior in - * case of reset of a single ADC while the other ADCs sharing the same - * common group is still running. - * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down: - * this saves more power by reducing leakage currents - * and is particularly interesting before entering MCU low-power modes. - * @param hadc ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - - /* Check ADC handle */ - if (hadc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); - - /* Stop potential conversion on going */ - tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); - - /* Disable ADC peripheral if conversions are effectively stopped */ - /* Flush register JSQR: reset the queue sequencer when injected */ - /* queue sequencer is enabled and ADC disabled. */ - /* The software and hardware triggers of the injected sequence are both */ - /* internally disabled just after the completion of the last valid */ - /* injected sequence. */ - SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM); - - /* Disable ADC peripheral if conversions are effectively stopped */ - if (tmp_hal_status == HAL_OK) - { - /* Disable the ADC peripheral */ - tmp_hal_status = ADC_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; - } - } - - /* Note: HAL ADC deInit is done independently of ADC conversion stop */ - /* and disable return status. In case of status fail, attempt to */ - /* perform deinitialization anyway and it is up user code in */ - /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */ - /* system RCC hard reset. */ - - /* ========== Reset ADC registers ========== */ - /* Reset register IER */ - __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 | - ADC_IT_JQOVF | ADC_IT_OVR | - ADC_IT_JEOS | ADC_IT_JEOC | - ADC_IT_EOS | ADC_IT_EOC | - ADC_IT_EOSMP | ADC_IT_RDY)); - - /* Reset register ISR */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 | - ADC_FLAG_JQOVF | ADC_FLAG_OVR | - ADC_FLAG_JEOS | ADC_FLAG_JEOC | - ADC_FLAG_EOS | ADC_FLAG_EOC | - ADC_FLAG_EOSMP | ADC_FLAG_RDY)); - - /* Reset register CR */ - /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, - ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set": - no direct reset applicable. - Update CR register to reset value where doable by software */ - CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF); - SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD); - - /* Reset register CFGR */ - CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS); - SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); - - /* Reset register CFGR2 */ - CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | - ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE); - - /* Reset register SMPR1 */ - CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS); - - /* Reset register SMPR2 */ - CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | - ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | - ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10); - - /* Reset register TR1 */ - CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1); - - /* Reset register TR2 */ - CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2); - - /* Reset register TR3 */ - CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3); - - /* Reset register SQR1 */ - CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | - ADC_SQR1_SQ1 | ADC_SQR1_L); - - /* Reset register SQR2 */ - CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | - ADC_SQR2_SQ6 | ADC_SQR2_SQ5); - - /* Reset register SQR3 */ - CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | - ADC_SQR3_SQ11 | ADC_SQR3_SQ10); - - /* Reset register SQR4 */ - CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); - - /* Register JSQR was reset when the ADC was disabled */ - - /* Reset register DR */ - /* bits in access mode read only, no direct reset applicable*/ - - /* Reset register OFR1 */ - CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1); - /* Reset register OFR2 */ - CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2); - /* Reset register OFR3 */ - CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3); - /* Reset register OFR4 */ - CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4); - - /* Reset registers JDR1, JDR2, JDR3, JDR4 */ - /* bits in access mode read only, no direct reset applicable*/ - - /* Reset register AWD2CR */ - CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH); - - /* Reset register AWD3CR */ - CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH); - - /* Reset register DIFSEL */ - CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL); - - /* Reset register CALFACT */ - CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); - - - /* ========== Reset common ADC registers ========== */ - - /* Software is allowed to change common parameters only when all the other - ADCs are disabled. */ - if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) - { - /* Reset configuration of ADC common register CCR: - - clock mode: CKMODE, PRESCEN - - multimode related parameters (when this feature is available): MDMA, - DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API) - - internal measurement paths: Vbat, temperature sensor, Vref (set into - HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() ) - */ - ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc); - - /* ========== Hard reset ADC peripheral ========== */ - /* Performs a global reset of the entire ADC peripherals instances */ - /* sharing the same common ADC instance: ADC state is forced to */ - /* a similar state as after device power-on. */ - /* Note: A possible implementation is to add RCC bus reset of ADC */ - /* (for example, using macro */ - /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */ - /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - if (hadc->MspDeInitCallback == NULL) - { - hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware */ - hadc->MspDeInitCallback(hadc); -#else - /* DeInit the low level hardware */ - HAL_ADC_MspDeInit(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - } - - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Reset injected channel configuration parameters */ - hadc->InjectionConfig.ContextQueue = 0; - hadc->InjectionConfig.ChannelCount = 0; - - /* Set ADC state */ - hadc->State = HAL_ADC_STATE_RESET; - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Initialize the ADC MSP. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_MspInit must be implemented in the user file. - */ -} - -/** - * @brief DeInitialize the ADC MSP. - * @param hadc ADC handle - * @note All ADC instances use the same core clock at RCC level, disabling - * the core clock reset all ADC instances). - * @retval None - */ -__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_MspDeInit must be implemented in the user file. - */ -} - -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User ADC Callback - * To be used instead of the weak predefined callback - * @param hadc Pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID - * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID - * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID - * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID - * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID - * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID - * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID - * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID - * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID - * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID - * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID - * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, - pADC_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) - { - switch (CallbackID) - { - case HAL_ADC_CONVERSION_COMPLETE_CB_ID : - hadc->ConvCpltCallback = pCallback; - break; - - case HAL_ADC_CONVERSION_HALF_CB_ID : - hadc->ConvHalfCpltCallback = pCallback; - break; - - case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : - hadc->LevelOutOfWindowCallback = pCallback; - break; - - case HAL_ADC_ERROR_CB_ID : - hadc->ErrorCallback = pCallback; - break; - - case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : - hadc->InjectedConvCpltCallback = pCallback; - break; - - case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : - hadc->InjectedQueueOverflowCallback = pCallback; - break; - - case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : - hadc->LevelOutOfWindow2Callback = pCallback; - break; - - case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : - hadc->LevelOutOfWindow3Callback = pCallback; - break; - - case HAL_ADC_END_OF_SAMPLING_CB_ID : - hadc->EndOfSamplingCallback = pCallback; - break; - - case HAL_ADC_MSPINIT_CB_ID : - hadc->MspInitCallback = pCallback; - break; - - case HAL_ADC_MSPDEINIT_CB_ID : - hadc->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_ADC_STATE_RESET == hadc->State) - { - switch (CallbackID) - { - case HAL_ADC_MSPINIT_CB_ID : - hadc->MspInitCallback = pCallback; - break; - - case HAL_ADC_MSPDEINIT_CB_ID : - hadc->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister a ADC Callback - * ADC callback is redirected to the weak predefined callback - * @param hadc Pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID - * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID - * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID - * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID - * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID - * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID - * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID - * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID - * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID - * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID - * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID - * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) - { - switch (CallbackID) - { - case HAL_ADC_CONVERSION_COMPLETE_CB_ID : - hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; - break; - - case HAL_ADC_CONVERSION_HALF_CB_ID : - hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; - break; - - case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : - hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; - break; - - case HAL_ADC_ERROR_CB_ID : - hadc->ErrorCallback = HAL_ADC_ErrorCallback; - break; - - case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : - hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; - break; - - case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : - hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; - break; - - case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : - hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; - break; - - case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : - hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; - break; - - case HAL_ADC_END_OF_SAMPLING_CB_ID : - hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; - break; - - case HAL_ADC_MSPINIT_CB_ID : - hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_ADC_MSPDEINIT_CB_ID : - hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_ADC_STATE_RESET == hadc->State) - { - switch (CallbackID) - { - case HAL_ADC_MSPINIT_CB_ID : - hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_ADC_MSPDEINIT_CB_ID : - hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions - * @brief ADC IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Start conversion of regular group. - (+) Stop conversion of regular group. - (+) Poll for conversion complete on regular group. - (+) Poll for conversion event. - (+) Get result of regular channel conversion. - (+) Start conversion of regular group and enable interruptions. - (+) Stop conversion of regular group and disable interruptions. - (+) Handle ADC interrupt request - (+) Start conversion of regular group and enable DMA transfer. - (+) Stop conversion of regular group and disable ADC DMA transfer. -@endverbatim - * @{ - */ - -/** - * @brief Enable ADC, start conversion of regular group. - * @note Interruptions enabled in this function: None. - * @note Case of multimode enabled (when multimode feature is available): - * if ADC is Slave, ADC is enabled but conversion is not started, - * if ADC is master, ADC is enabled and multimode conversion is started. - * @param hadc ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; -#if defined(ADC_MULTIMODE_SUPPORT) - const ADC_TypeDef *tmpADC_Master; - uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); -#endif - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Perform ADC enable and conversion start if no conversion is on going */ - if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - { - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - tmp_hal_status = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, - HAL_ADC_STATE_REG_BUSY); - -#if defined(ADC_MULTIMODE_SUPPORT) - /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - - if ADC instance is master or if multimode feature is not available - - if multimode setting is disabled (ADC instance slave in independent mode) */ - if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - ) - { - CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - } -#endif - - /* Set ADC error code */ - /* Check if a conversion is on going on ADC group injected */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - /* Reset ADC error code fields related to regular conversions only */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); - } - else - { - /* Reset all ADC error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Clear ADC group regular conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Enable conversion of regular group. */ - /* If software start has been selected, conversion starts immediately. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - /* Case of multimode enabled (when multimode feature is available): */ - /* - if ADC is slave and dual regular conversions are enabled, ADC is */ - /* enabled only (conversion is not started), */ - /* - if ADC is master, ADC is enabled and conversion is started. */ -#if defined(ADC_MULTIMODE_SUPPORT) - if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) - ) - { - /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ - if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - } - - /* Start ADC group regular conversion */ - LL_ADC_REG_StartConversion(hadc->Instance); - } - else - { - /* ADC instance is a multimode slave instance with multimode regular conversions enabled */ - SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - /* if Master ADC JAUTO bit is set, update Slave State in setting - HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */ - tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); - if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - } - - } -#else - if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - } - - /* Start ADC group regular conversion */ - LL_ADC_REG_StartConversion(hadc->Instance); -#endif - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hadc); - } - } - else - { - tmp_hal_status = HAL_BUSY; - } - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Stop ADC conversion of regular group (and injected channels in - * case of auto_injection mode), disable ADC peripheral. - * @note: ADC peripheral disable is forcing stop of potential - * conversion on injected group. If injected group is under use, it - * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. - * @param hadc ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* 1. Stop potential conversion on going, on ADC groups regular and injected */ - tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); - - /* Disable ADC peripheral if conversions are effectively stopped */ - if (tmp_hal_status == HAL_OK) - { - /* 2. Disable the ADC peripheral */ - tmp_hal_status = ADC_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Wait for regular group conversion to be completed. - * @note ADC conversion flags EOS (end of sequence) and EOC (end of - * conversion) are cleared by this function, with an exception: - * if low power feature "LowPowerAutoWait" is enabled, flags are - * not cleared to not interfere with this feature until data register - * is read using function HAL_ADC_GetValue(). - * @note This function cannot be used in a particular setup: ADC configured - * in DMA mode and polling for end of each conversion (ADC init - * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). - * In this case, DMA resets the flag EOC and polling cannot be - * performed on each conversion. Nevertheless, polling can still - * be performed on the complete sequence (ADC init - * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). - * @param hadc ADC handle - * @param Timeout Timeout value in millisecond. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) -{ - uint32_t tickstart; - uint32_t tmp_Flag_End; - uint32_t tmp_cfgr; -#if defined(ADC_MULTIMODE_SUPPORT) - const ADC_TypeDef *tmpADC_Master; - uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); -#endif - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* If end of conversion selected to end of sequence conversions */ - if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) - { - tmp_Flag_End = ADC_FLAG_EOS; - } - /* If end of conversion selected to end of unitary conversion */ - else /* ADC_EOC_SINGLE_CONV */ - { - /* Verification that ADC configuration is compliant with polling for */ - /* each conversion: */ - /* Particular case is ADC configured in DMA mode and ADC sequencer with */ - /* several ranks and polling for end of each conversion. */ - /* For code simplicity sake, this particular case is generalized to */ - /* ADC configured in DMA mode and and polling for end of each conversion. */ -#if defined(ADC_MULTIMODE_SUPPORT) - if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) - ) - { - /* Check ADC DMA mode in independent mode on ADC group regular */ - if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) - { - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - return HAL_ERROR; - } - else - { - tmp_Flag_End = (ADC_FLAG_EOC); - } - } - else - { - /* Check ADC DMA mode in multimode on ADC group regular */ - if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) - { - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - return HAL_ERROR; - } - else - { - tmp_Flag_End = (ADC_FLAG_EOC); - } - } -#else - /* Check ADC DMA mode */ - if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) - { - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - return HAL_ERROR; - } - else - { - tmp_Flag_End = (ADC_FLAG_EOC); - } -#endif - } - - /* Get tick count */ - tickstart = HAL_GetTick(); - - /* Wait until End of unitary conversion or sequence conversions flag is raised */ - while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) - { - /* Check if timeout is disabled (set to infinite wait) */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) - { - /* New check to avoid false timeout detection in case of preemption */ - if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) - { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_TIMEOUT; - } - } - } - } - - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going. */ - if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) - && (hadc->Init.ContinuousConvMode == DISABLE) - ) - { - /* Check whether end of sequence is reached */ - if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) - { - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - - if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - } - - /* Get relevant register CFGR in ADC instance of ADC master or slave */ - /* in function of multimode state (for devices with multimode */ - /* available). */ -#if defined(ADC_MULTIMODE_SUPPORT) - if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) - ) - { - /* Retrieve handle ADC CFGR register */ - tmp_cfgr = READ_REG(hadc->Instance->CFGR); - } - else - { - /* Retrieve Master ADC CFGR register */ - tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); - tmp_cfgr = READ_REG(tmpADC_Master->CFGR); - } -#else - /* Retrieve handle ADC CFGR register */ - tmp_cfgr = READ_REG(hadc->Instance->CFGR); -#endif - - /* Clear polled flag */ - if (tmp_Flag_End == ADC_FLAG_EOS) - { - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS); - } - else - { - /* Clear end of conversion EOC flag of regular group if low power feature */ - /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ - /* until data register is read using function HAL_ADC_GetValue(). */ - if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL) - { - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Poll for ADC event. - * @param hadc ADC handle - * @param EventType the ADC event type. - * This parameter can be one of the following values: - * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event - * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices) - * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families) - * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families) - * @arg @ref ADC_OVR_EVENT ADC Overrun event - * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event - * @param Timeout Timeout value in millisecond. - * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. - * Indeed, the latter is reset only if hadc->Init.Overrun field is set - * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten - * by a new converted data as soon as OVR is cleared. - * To reset OVR flag once the preserved data is retrieved, the user can resort - * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout) -{ - uint32_t tickstart; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_EVENT_TYPE(EventType)); - - /* Get tick count */ - tickstart = HAL_GetTick(); - - /* Check selected event flag */ - while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) - { - /* Check if timeout is disabled (set to infinite wait) */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) - { - /* New check to avoid false timeout detection in case of preemption */ - if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) - { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_TIMEOUT; - } - } - } - } - - switch (EventType) - { - /* End Of Sampling event */ - case ADC_EOSMP_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); - - /* Clear the End Of Sampling flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); - - break; - - /* Analog watchdog (level out of window) event */ - /* Note: In case of several analog watchdog enabled, if needed to know */ - /* which one triggered and on which ADCx, test ADC state of analog watchdog */ - /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */ - /* For example: */ - /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */ - /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */ - /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */ - - /* Check analog watchdog 1 flag */ - case ADC_AWD_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); - - break; - - /* Check analog watchdog 2 flag */ - case ADC_AWD2_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); - - break; - - /* Check analog watchdog 3 flag */ - case ADC_AWD3_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); - - break; - - /* Injected context queue overflow event */ - case ADC_JQOVF_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); - - /* Set ADC error code to Injected context queue overflow */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); - - /* Clear ADC Injected context queue overflow flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); - - break; - - /* Overrun event */ - default: /* Case ADC_OVR_EVENT */ - /* If overrun is set to overwrite previous data, overrun event is not */ - /* considered as an error. */ - /* (cf ref manual "Managing conversions without using the DMA and without */ - /* overrun ") */ - if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); - - /* Set ADC error code to overrun */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - } - else - { - /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN - otherwise, data register is potentially overwritten by new converted data as soon - as OVR is cleared. */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - } - break; - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Enable ADC, start conversion of regular group with interruption. - * @note Interruptions enabled in this function according to initialization - * setting : EOC (end of conversion), EOS (end of sequence), - * OVR overrun. - * Each of these interruptions has its dedicated callback function. - * @note Case of multimode enabled (when multimode feature is available): - * HAL_ADC_Start_IT() must be called for ADC Slave first, then for - * ADC Master. - * For ADC Slave, ADC is enabled only (conversion is not started). - * For ADC Master, ADC is enabled and multimode conversion is started. - * @note To guarantee a proper reset of all interruptions once all the needed - * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure - * a correct stop of the IT-based conversions. - * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling - * interruption. If required (e.g. in case of oversampling with trigger - * mode), the user must: - * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) - * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) - * before calling HAL_ADC_Start_IT(). - * @param hadc ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; -#if defined(ADC_MULTIMODE_SUPPORT) - const ADC_TypeDef *tmpADC_Master; - uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); -#endif - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Perform ADC enable and conversion start if no conversion is on going */ - if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - { - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - tmp_hal_status = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, - HAL_ADC_STATE_REG_BUSY); - -#if defined(ADC_MULTIMODE_SUPPORT) - /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - - if ADC instance is master or if multimode feature is not available - - if multimode setting is disabled (ADC instance slave in independent mode) */ - if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - ) - { - CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - } -#endif - - /* Set ADC error code */ - /* Check if a conversion is on going on ADC group injected */ - if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) - { - /* Reset ADC error code fields related to regular conversions only */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); - } - else - { - /* Reset all ADC error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Clear ADC group regular conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Disable all interruptions before enabling the desired ones */ - __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); - - /* Enable ADC end of conversion interrupt */ - switch (hadc->Init.EOCSelection) - { - case ADC_EOC_SEQ_CONV: - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS); - break; - /* case ADC_EOC_SINGLE_CONV */ - default: - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); - break; - } - - /* Enable ADC overrun interrupt */ - /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is - ADC_IT_OVR enabled; otherwise data overwrite is considered as normal - behavior and no CPU time is lost for a non-processed interruption */ - if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) - { - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - } - - /* Enable conversion of regular group. */ - /* If software start has been selected, conversion starts immediately. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - /* Case of multimode enabled (when multimode feature is available): */ - /* - if ADC is slave and dual regular conversions are enabled, ADC is */ - /* enabled only (conversion is not started), */ - /* - if ADC is master, ADC is enabled and conversion is started. */ -#if defined(ADC_MULTIMODE_SUPPORT) - if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) - ) - { - /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ - if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - - /* Enable as well injected interruptions in case - HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This - allows to start regular and injected conversions when JAUTO is - set with a single call to HAL_ADC_Start_IT() */ - switch (hadc->Init.EOCSelection) - { - case ADC_EOC_SEQ_CONV: - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); - break; - /* case ADC_EOC_SINGLE_CONV */ - default: - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); - break; - } - } - - /* Start ADC group regular conversion */ - LL_ADC_REG_StartConversion(hadc->Instance); - } - else - { - /* ADC instance is a multimode slave instance with multimode regular conversions enabled */ - SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - /* if Master ADC JAUTO bit is set, Slave injected interruptions - are enabled nevertheless (for same reason as above) */ - tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); - if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) - { - /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit - and in resetting HAL_ADC_STATE_INJ_EOC bit */ - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - /* Next, set Slave injected interruptions */ - switch (hadc->Init.EOCSelection) - { - case ADC_EOC_SEQ_CONV: - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); - break; - /* case ADC_EOC_SINGLE_CONV */ - default: - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); - break; - } - } - } -#else - /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ - if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - - /* Enable as well injected interruptions in case - HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This - allows to start regular and injected conversions when JAUTO is - set with a single call to HAL_ADC_Start_IT() */ - switch (hadc->Init.EOCSelection) - { - case ADC_EOC_SEQ_CONV: - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); - break; - /* case ADC_EOC_SINGLE_CONV */ - default: - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); - break; - } - } - - /* Start ADC group regular conversion */ - LL_ADC_REG_StartConversion(hadc->Instance); -#endif - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hadc); - } - - } - else - { - tmp_hal_status = HAL_BUSY; - } - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Stop ADC conversion of regular group (and injected group in - * case of auto_injection mode), disable interrution of - * end-of-conversion, disable ADC peripheral. - * @param hadc ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* 1. Stop potential conversion on going, on ADC groups regular and injected */ - tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); - - /* Disable ADC peripheral if conversions are effectively stopped */ - if (tmp_hal_status == HAL_OK) - { - /* Disable ADC end of conversion interrupt for regular group */ - /* Disable ADC overrun interrupt */ - __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); - - /* 2. Disable the ADC peripheral */ - tmp_hal_status = ADC_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Enable ADC, start conversion of regular group and transfer result through DMA. - * @note Interruptions enabled in this function: - * overrun (if applicable), DMA half transfer, DMA transfer complete. - * Each of these interruptions has its dedicated callback function. - * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA() - * is designed for single-ADC mode only. For multimode, the dedicated - * HAL_ADCEx_MultiModeStart_DMA() function must be used. - * @param hadc ADC handle - * @param pData Destination Buffer address. - * @param Length Number of data to be transferred from ADC peripheral to memory - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) -{ - HAL_StatusTypeDef tmp_hal_status; -#if defined(ADC_MULTIMODE_SUPPORT) - uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); -#endif - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Perform ADC enable and conversion start if no conversion is on going */ - if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - { - /* Process locked */ - __HAL_LOCK(hadc); - -#if defined(ADC_MULTIMODE_SUPPORT) - /* Ensure that multimode regular conversions are not enabled. */ - /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */ - if ((ADC_IS_INDEPENDENT(hadc) != RESET) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) - ) -#endif /* ADC_MULTIMODE_SUPPORT */ - { - /* Enable the ADC peripheral */ - tmp_hal_status = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, - HAL_ADC_STATE_REG_BUSY); - -#if defined(ADC_MULTIMODE_SUPPORT) - /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - - if ADC instance is master or if multimode feature is not available - - if multimode setting is disabled (ADC instance slave in independent mode) */ - if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - ) - { - CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - } -#endif - - /* Check if a conversion is on going on ADC group injected */ - if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) - { - /* Reset ADC error code fields related to regular conversions only */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); - } - else - { - /* Reset all ADC error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Set the DMA transfer complete callback */ - hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; - - /* Set the DMA half transfer complete callback */ - hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; - - /* Set the DMA error callback */ - hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; - - - /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */ - /* ADC start (in case of SW start): */ - - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC */ - /* operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* With DMA, overrun event is always considered as an error even if - hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, - ADC_IT_OVR is enabled. */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - - /* Enable ADC DMA mode */ - SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); - - /* Start the DMA channel */ - tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); - - /* Enable conversion of regular group. */ - /* If software start has been selected, conversion starts immediately. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - /* Start ADC group regular conversion */ - LL_ADC_REG_StartConversion(hadc->Instance); - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hadc); - } - - } -#if defined(ADC_MULTIMODE_SUPPORT) - else - { - tmp_hal_status = HAL_ERROR; - /* Process unlocked */ - __HAL_UNLOCK(hadc); - } -#endif - } - else - { - tmp_hal_status = HAL_BUSY; - } - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Stop ADC conversion of regular group (and injected group in - * case of auto_injection mode), disable ADC DMA transfer, disable - * ADC peripheral. - * @note: ADC peripheral disable is forcing stop of potential - * conversion on ADC group injected. If ADC group injected is under use, it - * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. - * @note Case of multimode enabled (when multimode feature is available): - * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only. - * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used. - * @param hadc ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* 1. Stop potential ADC group regular conversion on going */ - tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); - - /* Disable ADC peripheral if conversions are effectively stopped */ - if (tmp_hal_status == HAL_OK) - { - /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */ - CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); - - /* Disable the DMA channel (in case of DMA in circular mode or stop */ - /* while DMA transfer is on going) */ - if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) - { - tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - - /* Check if DMA channel effectively disabled */ - if (tmp_hal_status != HAL_OK) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); - } - } - - /* Disable ADC overrun interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - - /* 2. Disable the ADC peripheral */ - /* Update "tmp_hal_status" only if DMA channel disabling passed, */ - /* to keep in memory a potential failing status. */ - if (tmp_hal_status == HAL_OK) - { - tmp_hal_status = ADC_Disable(hadc); - } - else - { - (void)ADC_Disable(hadc); - } - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Get ADC regular group conversion result. - * @note Reading register DR automatically clears ADC flag EOC - * (ADC group regular end of unitary conversion). - * @note This function does not clear ADC flag EOS - * (ADC group regular end of sequence conversion). - * Occurrence of flag EOS rising: - * - If sequencer is composed of 1 rank, flag EOS is equivalent - * to flag EOC. - * - If sequencer is composed of several ranks, during the scan - * sequence flag EOC only is raised, at the end of the scan sequence - * both flags EOC and EOS are raised. - * To clear this flag, either use function: - * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming - * model polling: @ref HAL_ADC_PollForConversion() - * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). - * @param hadc ADC handle - * @retval ADC group regular conversion data - */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Note: EOC flag is not cleared here by software because automatically */ - /* cleared by hardware when reading register DR. */ - - /* Return ADC converted value */ - return hadc->Instance->DR; -} - -/** - * @brief Start ADC conversion sampling phase of regular group - * @note: This function should only be called to start sampling when - * - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling - * mode has been selected - * - @ref ADC_SOFTWARE_START has been selected as trigger source - * @param hadc ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Start sampling */ - SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop ADC conversion sampling phase of regular group and start conversion - * @note: This function should only be called to stop sampling when - * - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling - * mode has been selected - * - @ref ADC_SOFTWARE_START has been selected as trigger source - * - after sampling has been started using @ref HAL_ADC_StartSampling. - * @param hadc ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Start sampling */ - CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Handle ADC interrupt request. - * @param hadc ADC handle - * @retval None - */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) -{ - uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */ - uint32_t tmp_isr = hadc->Instance->ISR; - uint32_t tmp_ier = hadc->Instance->IER; - uint32_t tmp_adc_inj_is_trigger_source_sw_start; - uint32_t tmp_adc_reg_is_trigger_source_sw_start; - uint32_t tmp_cfgr; -#if defined(ADC_MULTIMODE_SUPPORT) - const ADC_TypeDef *tmpADC_Master; - uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); -#endif - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); - - /* ========== Check End of Sampling flag for ADC group regular ========== */ - if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) - { - /* Update state machine on end of sampling status if not in error state */ - if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); - } - - /* End Of Sampling callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->EndOfSamplingCallback(hadc); -#else - HAL_ADCEx_EndOfSamplingCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear regular group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); - } - - /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */ - if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || - (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))) - { - /* Update state machine on conversion status if not in error state */ - if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - } - - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going */ - /* to disable interruption. */ - if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) - { - /* Get relevant register CFGR in ADC instance of ADC master or slave */ - /* in function of multimode state (for devices with multimode */ - /* available). */ -#if defined(ADC_MULTIMODE_SUPPORT) - if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) - ) - { - /* check CONT bit directly in handle ADC CFGR register */ - tmp_cfgr = READ_REG(hadc->Instance->CFGR); - } - else - { - /* else need to check Master ADC CONT bit */ - tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); - tmp_cfgr = READ_REG(tmpADC_Master->CFGR); - } -#else - tmp_cfgr = READ_REG(hadc->Instance->CFGR); -#endif - - /* Carry on if continuous mode is disabled */ - if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) - { - /* If End of Sequence is reached, disable interrupts */ - if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) - { - /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ - /* ADSTART==0 (no conversion on going) */ - if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - { - /* Disable ADC end of sequence conversion interrupt */ - /* Note: Overrun interrupt was enabled with EOC interrupt in */ - /* HAL_Start_IT(), but is not disabled here because can be used */ - /* by overrun IRQ process below. */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); - - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - - if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - else - { - /* Change ADC state to error state */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - } - } - } - } - - /* Conversion complete callback */ - /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */ - /* to determine if conversion has been triggered from EOC or EOS, */ - /* possibility to use: */ - /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ConvCpltCallback(hadc); -#else - HAL_ADC_ConvCpltCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear regular group conversion flag */ - /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ - /* conversion flags clear induces the release of the preserved data.*/ - /* Therefore, if the preserved data value is needed, it must be */ - /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); - } - - /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */ - if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || - (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS))) - { - /* Update state machine on conversion status if not in error state */ - if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); - } - - /* Retrieve ADC configuration */ - tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance); - tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance); - /* Get relevant register CFGR in ADC instance of ADC master or slave */ - /* in function of multimode state (for devices with multimode */ - /* available). */ -#if defined(ADC_MULTIMODE_SUPPORT) - if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) - ) - { - tmp_cfgr = READ_REG(hadc->Instance->CFGR); - } - else - { - tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); - tmp_cfgr = READ_REG(tmpADC_Master->CFGR); - } -#else - tmp_cfgr = READ_REG(hadc->Instance->CFGR); -#endif - - /* Disable interruption if no further conversion upcoming by injected */ - /* external trigger or by automatic injected conversion with regular */ - /* group having no further conversion upcoming (same conditions as */ - /* regular group interruption disabling above), */ - /* and if injected scan sequence is completed. */ - if (tmp_adc_inj_is_trigger_source_sw_start != 0UL) - { - if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) || - ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && - (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))) - { - /* If End of Sequence is reached, disable interrupts */ - if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) - { - /* Particular case if injected contexts queue is enabled: */ - /* when the last context has been fully processed, JSQR is reset */ - /* by the hardware. Even if no injected conversion is planned to come */ - /* (queue empty, triggers are ignored), it can start again */ - /* immediately after setting a new context (JADSTART is still set). */ - /* Therefore, state of HAL ADC injected group is kept to busy. */ - if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) - { - /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ - /* JADSTART==0 (no conversion on going) */ - if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) - { - /* Disable ADC end of sequence conversion interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); - - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - - if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - } - } - } - } - } - - /* Injected Conversion complete callback */ - /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to - if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or - if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether - interruption has been triggered by end of conversion or end of - sequence. */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->InjectedConvCpltCallback(hadc); -#else - HAL_ADCEx_InjectedConvCpltCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear injected group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); - } - - /* ========== Check Analog watchdog 1 flag ========== */ - if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - - /* Level out of window 1 callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->LevelOutOfWindowCallback(hadc); -#else - HAL_ADC_LevelOutOfWindowCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); - } - - /* ========== Check analog watchdog 2 flag ========== */ - if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); - - /* Level out of window 2 callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->LevelOutOfWindow2Callback(hadc); -#else - HAL_ADCEx_LevelOutOfWindow2Callback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); - } - - /* ========== Check analog watchdog 3 flag ========== */ - if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); - - /* Level out of window 3 callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->LevelOutOfWindow3Callback(hadc); -#else - HAL_ADCEx_LevelOutOfWindow3Callback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); - } - - /* ========== Check Overrun flag ========== */ - if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) - { - /* If overrun is set to overwrite previous data (default setting), */ - /* overrun event is not considered as an error. */ - /* (cf ref manual "Managing conversions without using the DMA and without */ - /* overrun ") */ - /* Exception for usage with DMA overrun event always considered as an */ - /* error. */ - if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) - { - overrun_error = 1UL; - } - else - { - /* Check DMA configuration */ -#if defined(ADC_MULTIMODE_SUPPORT) - if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT) - { - /* Multimode (when feature is available) is enabled, - Common Control Register MDMA bits must be checked. */ - if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) - { - overrun_error = 1UL; - } - } - else -#endif - { - /* Multimode not set or feature not available or ADC independent */ - if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL) - { - overrun_error = 1UL; - } - } - } - - if (overrun_error == 1UL) - { - /* Change ADC state to error state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); - - /* Set ADC error code to overrun */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - - /* Error callback */ - /* Note: In case of overrun, ADC conversion data is preserved until */ - /* flag OVR is reset. */ - /* Therefore, old ADC conversion data can be retrieved in */ - /* function "HAL_ADC_ErrorCallback()". */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ErrorCallback(hadc); -#else - HAL_ADC_ErrorCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - } - - /* Clear ADC overrun flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - } - - /* ========== Check Injected context queue overflow flag ========== */ - if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) - { - /* Change ADC state to overrun state */ - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); - - /* Set ADC error code to Injected context queue overflow */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); - - /* Clear the Injected context queue overflow flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); - - /* Injected context queue overflow callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->InjectedQueueOverflowCallback(hadc); -#else - HAL_ADCEx_InjectedQueueOverflowCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - } - -} - -/** - * @brief Conversion complete callback in non-blocking mode. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_ConvCpltCallback must be implemented in the user file. - */ -} - -/** - * @brief Conversion DMA half-transfer callback in non-blocking mode. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. - */ -} - -/** - * @brief Analog watchdog 1 callback in non-blocking mode. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. - */ -} - -/** - * @brief ADC error callback in non-blocking mode - * (ADC conversion with interruption or transfer by DMA). - * @note In case of error due to overrun when using ADC with DMA transfer - * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): - * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". - * - If needed, restart a new ADC conversion using function - * "HAL_ADC_Start_DMA()" - * (this function is also clearing overrun flag) - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_ErrorCallback must be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure channels on regular group - (+) Configure the analog watchdog - -@endverbatim - * @{ - */ - -/** - * @brief Configure a channel to be assigned to ADC group regular. - * @note In case of usage of internal measurement channels: - * Vbat/VrefInt/TempSensor. - * These internal paths can be disabled using function - * HAL_ADC_DeInit(). - * @note Possibility to update parameters on the fly: - * This function initializes channel into ADC group regular, - * following calls to this function can be used to reconfigure - * some parameters of structure "ADC_ChannelConfTypeDef" on the fly, - * without resetting the ADC. - * The setting of these parameters is conditioned to ADC state: - * Refer to comments of structure "ADC_ChannelConfTypeDef". - * @param hadc ADC handle - * @param sConfig Structure of ADC channel assigned to ADC group regular. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmpOffsetShifted; - uint32_t tmp_config_internal_channel; - __IO uint32_t wait_loop_index = 0UL; - uint32_t tmp_adc_is_conversion_on_going_regular; - uint32_t tmp_adc_is_conversion_on_going_injected; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); - assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); - assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff)); - assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber)); - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset)); - - /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is - ignored (considered as reset) */ - assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); - - /* Verification of channel number */ - if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) - { - assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel)); - } - else - { - assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel)); - } - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated when ADC is disabled or enabled without */ - /* conversion on going on regular group: */ - /* - Channel number */ - /* - Channel rank */ - if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - { - /* Set ADC group regular sequence: channel on the selected scan sequence rank */ - LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); - - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated when ADC is disabled or enabled without */ - /* conversion on going on regular group: */ - /* - Channel sampling time */ - /* - Channel offset */ - tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); - tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - if ((tmp_adc_is_conversion_on_going_regular == 0UL) - && (tmp_adc_is_conversion_on_going_injected == 0UL) - ) - { - /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ - if (sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5) - { - /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5); - - /* Set ADC sampling time common configuration */ - LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); - } - else - { - /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); - - /* Set ADC sampling time common configuration */ - LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); - } - - /* Configure the offset: offset enable/disable, channel, offset value */ - - /* Shift the offset with respect to the selected ADC resolution. */ - /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ - tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); - - if (sConfig->OffsetNumber != ADC_OFFSET_NONE) - { - /* Set ADC selected offset number */ - LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); - - assert_param(IS_ADC_OFFSET_SIGN(sConfig->OffsetSign)); - assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSaturation)); - /* Set ADC selected offset sign & saturation */ - LL_ADC_SetOffsetSign(hadc->Instance, sConfig->OffsetNumber, sConfig->OffsetSign); - LL_ADC_SetOffsetSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSaturation == ENABLE) ? LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE); - } - else - { - /* Scan each offset register to check if the selected channel is targeted. */ - /* If this is the case, the corresponding offset number is disabled. */ - if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) - { - LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); - } - if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) - { - LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); - } - if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) - { - LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); - } - if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) - { - LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); - } - } - } - - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated only when ADC is disabled: */ - /* - Single or differential mode */ - if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - { - /* Set mode single-ended or differential input of the selected ADC channel */ - LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); - - /* Configuration of differential mode */ - if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) - { - /* Set sampling time of the selected ADC channel */ - /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, - (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), - sConfig->SamplingTime); - } - - } - - /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ - /* If internal channel selected, enable dedicated internal buffers and */ - /* paths. */ - /* Note: these internal measurement paths can be disabled using */ - /* HAL_ADC_DeInit(). */ - - if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) - { - tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - - /* If the requested internal measurement path has already been enabled, */ - /* bypass the configuration processing. */ - if (((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5)) - && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) - { - if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), - LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); - - /* Delay for temperature sensor stabilization time */ - /* Wait loop initialization and execution */ - /* Note: Variable divided by 2 to compensate partially */ - /* CPU processing cycles, scaling in us split to not */ - /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); - while (wait_loop_index != 0UL) - { - wait_loop_index--; - } - } - } - else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) - { - if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), - LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); - } - } - else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) - && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) - { - if (ADC_VREFINT_INSTANCE(hadc)) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), - LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); - } - } - else - { - /* nothing to do */ - } - } - } - - /* If a conversion is on going on regular group, no update on regular */ - /* channel could be done on neither of the channel configuration structure */ - /* parameters. */ - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Configure the analog watchdog. - * @note Possibility to update parameters on the fly: - * This function initializes the selected analog watchdog, successive - * calls to this function can be used to reconfigure some parameters - * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting - * the ADC. - * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure - * "ADC_AnalogWDGConfTypeDef". - * @note On this STM32 series, analog watchdog thresholds can be modified - * while ADC conversion is on going. - * In this case, some constraints must be taken into account: - * the programmed threshold values are effective from the next - * ADC EOC (end of unitary conversion). - * Considering that registers write delay may happen due to - * bus activity, this might cause an uncertainty on the - * effective timing of the new programmed threshold values. - * @param hadc ADC handle - * @param AnalogWDGConfig Structure of ADC analog watchdog configuration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmpAWDHighThresholdShifted; - uint32_t tmpAWDLowThresholdShifted; - uint32_t tmp_adc_is_conversion_on_going_regular; - uint32_t tmp_adc_is_conversion_on_going_injected; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber)); - assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); - assert_param(IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(AnalogWDGConfig->FilteringConfig)); - assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); - - if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || - (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || - (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)) - { - assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel)); - } - - /* Verify thresholds range */ - if (hadc->Init.OversamplingMode == ENABLE) - { - /* Case of oversampling enabled: depending on ratio and shift configuration, - analog watchdog thresholds can be higher than ADC resolution. - Verify if thresholds are within maximum thresholds range. */ - assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold)); - } - else - { - /* Verify if thresholds are within the selected ADC resolution */ - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); - } - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated when ADC is disabled or enabled without */ - /* conversion on going on ADC groups regular and injected: */ - /* - Analog watchdog channels */ - tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); - tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - if ((tmp_adc_is_conversion_on_going_regular == 0UL) - && (tmp_adc_is_conversion_on_going_injected == 0UL) - ) - { - /* Analog watchdog configuration */ - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) - { - /* Configuration of analog watchdog: */ - /* - Set the analog watchdog enable mode: one or overall group of */ - /* channels, on groups regular and-or injected. */ - switch (AnalogWDGConfig->WatchdogMode) - { - case ADC_ANALOGWATCHDOG_SINGLE_REG: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, - LL_ADC_GROUP_REGULAR)); - break; - - case ADC_ANALOGWATCHDOG_SINGLE_INJEC: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, - LL_ADC_GROUP_INJECTED)); - break; - - case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, - LL_ADC_GROUP_REGULAR_INJECTED)); - break; - - case ADC_ANALOGWATCHDOG_ALL_REG: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG); - break; - - case ADC_ANALOGWATCHDOG_ALL_INJEC: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ); - break; - - case ADC_ANALOGWATCHDOG_ALL_REGINJEC: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); - break; - - default: /* ADC_ANALOGWATCHDOG_NONE */ - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE); - break; - } - - /* Set the filtering configuration */ - MODIFY_REG(hadc->Instance->TR1, - ADC_TR1_AWDFILT, - AnalogWDGConfig->FilteringConfig); - - /* Update state, clear previous result related to AWD1 */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1); - - /* Clear flag ADC analog watchdog */ - /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ - /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ - /* (in case left enabled by previous ADC operations). */ - LL_ADC_ClearFlag_AWD1(hadc->Instance); - - /* Configure ADC analog watchdog interrupt */ - if (AnalogWDGConfig->ITMode == ENABLE) - { - LL_ADC_EnableIT_AWD1(hadc->Instance); - } - else - { - LL_ADC_DisableIT_AWD1(hadc->Instance); - } - } - /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */ - else - { - switch (AnalogWDGConfig->WatchdogMode) - { - case ADC_ANALOGWATCHDOG_SINGLE_REG: - case ADC_ANALOGWATCHDOG_SINGLE_INJEC: - case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: - /* Update AWD by bitfield to keep the possibility to monitor */ - /* several channels by successive calls of this function. */ - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) - { - SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL))); - } - else - { - SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL))); - } - break; - - case ADC_ANALOGWATCHDOG_ALL_REG: - case ADC_ANALOGWATCHDOG_ALL_INJEC: - case ADC_ANALOGWATCHDOG_ALL_REGINJEC: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); - break; - - default: /* ADC_ANALOGWATCHDOG_NONE */ - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); - break; - } - - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) - { - /* Update state, clear previous result related to AWD2 */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2); - - /* Clear flag ADC analog watchdog */ - /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ - /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ - /* (in case left enabled by previous ADC operations). */ - LL_ADC_ClearFlag_AWD2(hadc->Instance); - - /* Configure ADC analog watchdog interrupt */ - if (AnalogWDGConfig->ITMode == ENABLE) - { - LL_ADC_EnableIT_AWD2(hadc->Instance); - } - else - { - LL_ADC_DisableIT_AWD2(hadc->Instance); - } - } - /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ - else - { - /* Update state, clear previous result related to AWD3 */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3); - - /* Clear flag ADC analog watchdog */ - /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ - /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ - /* (in case left enabled by previous ADC operations). */ - LL_ADC_ClearFlag_AWD3(hadc->Instance); - - /* Configure ADC analog watchdog interrupt */ - if (AnalogWDGConfig->ITMode == ENABLE) - { - LL_ADC_EnableIT_AWD3(hadc->Instance); - } - else - { - LL_ADC_DisableIT_AWD3(hadc->Instance); - } - } - } - - } - - /* Analog watchdog thresholds configuration */ - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) - { - /* Shift the offset with respect to the selected ADC resolution: */ - /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ - /* are set to 0. */ - tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); - tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); - } - /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */ - else - { - /* Shift the offset with respect to the selected ADC resolution: */ - /* Thresholds have to be left-aligned on bit 7, the LSB (right bits) */ - /* are set to 0. */ - tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); - tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); - } - - /* Set ADC analog watchdog thresholds value of both thresholds high and low */ - LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, - tmpAWDLowThresholdShifted); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions - * @brief ADC Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral state and errors functions ##### - =============================================================================== - [..] - This subsection provides functions to get in run-time the status of the - peripheral. - (+) Check the ADC state - (+) Check the ADC error code - -@endverbatim - * @{ - */ - -/** - * @brief Return the ADC handle state. - * @note ADC state machine is managed by bitfields, ADC status must be - * compared with states bits. - * For example: - * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " - * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " - * @param hadc ADC handle - * @retval ADC handle state (bitfield on 32 bits) - */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Return ADC handle state */ - return hadc->State; -} - -/** - * @brief Return the ADC error code. - * @param hadc ADC handle - * @retval ADC error code (bitfield on 32 bits) - */ -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - return hadc->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Functions ADC Private Functions - * @{ - */ - -/** - * @brief Stop ADC conversion. - * @param hadc ADC handle - * @param ConversionGroup ADC group regular and/or injected. - * This parameter can be one of the following values: - * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type. - * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type. - * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type. - * @retval HAL status. - */ -HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup) -{ - uint32_t tickstart; - uint32_t Conversion_Timeout_CPU_cycles = 0UL; - uint32_t conversion_group_reassigned = ConversionGroup; - uint32_t tmp_ADC_CR_ADSTART_JADSTART; - uint32_t tmp_adc_is_conversion_on_going_regular; - uint32_t tmp_adc_is_conversion_on_going_injected; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup)); - - /* Verification if ADC is not already stopped (on regular and injected */ - /* groups) to bypass this function if not needed. */ - tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); - tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - if ((tmp_adc_is_conversion_on_going_regular != 0UL) - || (tmp_adc_is_conversion_on_going_injected != 0UL) - ) - { - /* Particular case of continuous auto-injection mode combined with */ - /* auto-delay mode. */ - /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */ - /* injected group stop ADC_CR_JADSTP). */ - /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */ - /* (see reference manual). */ - if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL) - && (hadc->Init.ContinuousConvMode == ENABLE) - && (hadc->Init.LowPowerAutoWait == ENABLE) - ) - { - /* Use stop of regular group */ - conversion_group_reassigned = ADC_REGULAR_GROUP; - - /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */ - while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL) - { - if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL)) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - return HAL_ERROR; - } - Conversion_Timeout_CPU_cycles ++; - } - - /* Clear JEOS */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS); - } - - /* Stop potential conversion on going on ADC group regular */ - if (conversion_group_reassigned != ADC_INJECTED_GROUP) - { - /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ - if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) - { - if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) - { - /* Stop ADC group regular conversion */ - LL_ADC_REG_StopConversion(hadc->Instance); - } - } - } - - /* Stop potential conversion on going on ADC group injected */ - if (conversion_group_reassigned != ADC_REGULAR_GROUP) - { - /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */ - if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) - { - if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) - { - /* Stop ADC group injected conversion */ - LL_ADC_INJ_StopConversion(hadc->Instance); - } - } - } - - /* Selection of start and stop bits with respect to the regular or injected group */ - switch (conversion_group_reassigned) - { - case ADC_REGULAR_INJECTED_GROUP: - tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART); - break; - case ADC_INJECTED_GROUP: - tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART; - break; - /* Case ADC_REGULAR_GROUP only*/ - default: - tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART; - break; - } - - /* Wait for conversion effectively stopped */ - tickstart = HAL_GetTick(); - - while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) - { - if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) - { - /* New check to avoid false timeout detection in case of preemption */ - if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - return HAL_ERROR; - } - } - } - - } - - /* Return HAL status */ - return HAL_OK; -} - -/** - * @brief Enable the selected ADC. - * @note Prerequisite condition to use this function: ADC must be disabled - * and voltage regulator must be enabled (done into HAL_ADC_Init()). - * @param hadc ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) -{ - uint32_t tickstart; - - /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ - /* enabling phase not yet completed: flag ADC ready not yet set). */ - /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ - /* causes: ADC clock not running, ...). */ - if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - { - /* Check if conditions to enable the ADC are fulfilled */ - if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART - | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - return HAL_ERROR; - } - - /* Enable the ADC peripheral */ - LL_ADC_Enable(hadc->Instance); - - /* Wait for ADC effectively enabled */ - tickstart = HAL_GetTick(); - - while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) - { - /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit - has been cleared (after a calibration), ADEN bit is reset by the - calibration logic. - The workaround is to continue setting ADEN until ADRDY is becomes 1. - Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this - 4 ADC clock cycle duration */ - /* Note: Test of ADC enabled required due to hardware constraint to */ - /* not enable ADC if already enabled. */ - if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - { - LL_ADC_Enable(hadc->Instance); - } - - if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) - { - /* New check to avoid false timeout detection in case of preemption */ - if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - return HAL_ERROR; - } - } - } - } - - /* Return HAL status */ - return HAL_OK; -} - -/** - * @brief Disable the selected ADC. - * @note Prerequisite condition to use this function: ADC conversions must be - * stopped. - * @param hadc ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) -{ - uint32_t tickstart; - const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); - - /* Verification if ADC is not already disabled: */ - /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ - /* disabled. */ - if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) - && (tmp_adc_is_disable_on_going == 0UL) - ) - { - /* Check if conditions to disable the ADC are fulfilled */ - if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) - { - /* Disable the ADC peripheral */ - LL_ADC_Disable(hadc->Instance); - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - return HAL_ERROR; - } - - /* Wait for ADC effectively disabled */ - /* Get tick count */ - tickstart = HAL_GetTick(); - - while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) - { - if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) - { - /* New check to avoid false timeout detection in case of preemption */ - if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - return HAL_ERROR; - } - } - } - } - - /* Return HAL status */ - return HAL_OK; -} - -/** - * @brief DMA transfer complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Update state machine on conversion status if not in error state */ - if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going */ - /* to disable interruption. */ - /* Is it the end of the regular sequence ? */ - if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) - { - /* Are conversions software-triggered ? */ - if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) - { - /* Is CONT bit set ? */ - if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) - { - /* CONT bit is not set, no more conversions expected */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - } - } - else - { - /* DMA End of Transfer interrupt was triggered but conversions sequence - is not over. If DMACFG is set to 0, conversions are stopped. */ - if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL) - { - /* DMACFG bit is not set, conversions are stopped. */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - } - - /* Conversion complete callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ConvCpltCallback(hadc); -#else - HAL_ADC_ConvCpltCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - } - else /* DMA and-or internal error occurred */ - { - if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) - { - /* Call HAL ADC Error Callback function */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ErrorCallback(hadc); -#else - HAL_ADC_ErrorCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - } - else - { - /* Call ADC DMA error callback */ - hadc->DMA_Handle->XferErrorCallback(hdma); - } - } -} - -/** - * @brief DMA half transfer complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Half conversion callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ConvHalfCpltCallback(hadc); -#else - HAL_ADC_ConvHalfCpltCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA error callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void ADC_DMAError(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); - - /* Set ADC error code to DMA error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); - - /* Error callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ErrorCallback(hadc); -#else - HAL_ADC_ErrorCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -} - -/** - * @} - */ - -#endif /* HAL_ADC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c b/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c deleted file mode 100644 index c45adc4..0000000 --- a/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c +++ /dev/null @@ -1,2373 +0,0 @@ -/** - ****************************************************************************** - * @file stm32g4xx_hal_adc_ex.c - * @author MCD Application Team - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Converter (ADC) - * peripheral: - * + Peripheral Control functions - * Other functions (generic functions) are available in file - * "stm32g4xx_hal_adc.c". - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2019 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - [..] - (@) Sections "ADC peripheral features" and "How to use this driver" are - available in file of generic functions "stm32g4xx_hal_adc.c". - [..] - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32g4xx_hal.h" - -/** @addtogroup STM32G4xx_HAL_Driver - * @{ - */ - -/** @defgroup ADCEx ADCEx - * @brief ADC Extended HAL module driver - * @{ - */ - -#ifdef HAL_ADC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants - * @{ - */ - -#define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\ - ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\ - ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled */ - -/* Fixed timeout value for ADC calibration. */ -/* Values defined to be higher than worst cases: low clock frequency, */ -/* maximum prescalers. */ -/* Ex of profile low frequency : f_ADC at f_CPU/3968 (minimum value */ -/* considering both possible ADC clocking scheme: */ -/* - ADC clock from synchronous clock with AHB prescaler 512, */ -/* ADC prescaler 4. */ -/* Ratio max = 512 *4 = 2048 */ -/* - ADC clock from asynchronous clock (PLLP) with prescaler 256. */ -/* Highest CPU clock PLL (PLLR). */ -/* Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256 */ -/* = 3968 ) */ -/* Calibration_time MAX = 81 / f_ADC */ -/* = 81 / (f_CPU/3938) = 318978 CPU cycles */ -#define ADC_CALIBRATION_TIMEOUT (318978UL) /*!< ADC calibration time-out value (unit: CPU cycles) */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions - * @{ - */ - -/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions - * @brief Extended IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - - (+) Perform the ADC self-calibration for single or differential ending. - (+) Get calibration factors for single or differential ending. - (+) Set calibration factors for single or differential ending. - - (+) Start conversion of ADC group injected. - (+) Stop conversion of ADC group injected. - (+) Poll for conversion complete on ADC group injected. - (+) Get result of ADC group injected channel conversion. - (+) Start conversion of ADC group injected and enable interruptions. - (+) Stop conversion of ADC group injected and disable interruptions. - - (+) When multimode feature is available, start multimode and enable DMA transfer. - (+) Stop multimode and disable ADC DMA transfer. - (+) Get result of multimode conversion. - -@endverbatim - * @{ - */ - -/** - * @brief Perform an ADC automatic self-calibration - * Calibration prerequisite: ADC must be disabled (execute this - * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). - * @param hadc ADC handle - * @param SingleDiff Selection of single-ended or differential input - * This parameter can be one of the following values: - * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended - * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) -{ - HAL_StatusTypeDef tmp_hal_status; - __IO uint32_t wait_loop_index = 0UL; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Calibration prerequisite: ADC must be disabled. */ - - /* Disable the ADC (if not already disabled) */ - tmp_hal_status = ADC_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_BUSY_INTERNAL); - - /* Start ADC calibration in mode single-ended or differential */ - LL_ADC_StartCalibration(hadc->Instance, SingleDiff); - - /* Wait for calibration completion */ - while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) - { - wait_loop_index++; - if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) - { - /* Update ADC state machine to error */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_ERROR_INTERNAL); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - } - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_READY); - } - else - { - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Note: No need to update variable "tmp_hal_status" here: already set */ - /* to state "HAL_ERROR" by function disabling the ADC. */ - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Get the calibration factor. - * @param hadc ADC handle. - * @param SingleDiff This parameter can be only: - * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended - * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended - * @retval Calibration value. - */ -uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); - - /* Return the selected ADC calibration value */ - return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff); -} - -/** - * @brief Set the calibration factor to overwrite automatic conversion result. - * ADC must be enabled and no conversion is ongoing. - * @param hadc ADC handle - * @param SingleDiff This parameter can be only: - * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended - * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended - * @param CalibrationFactor Calibration factor (coded on 7 bits maximum) - * @retval HAL state - */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, - uint32_t CalibrationFactor) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmp_adc_is_conversion_on_going_regular; - uint32_t tmp_adc_is_conversion_on_going_injected; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); - assert_param(IS_ADC_CALFACT(CalibrationFactor)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Verification of hardware constraints before modifying the calibration */ - /* factors register: ADC must be enabled, no conversion on going. */ - tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); - tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - - if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) - && (tmp_adc_is_conversion_on_going_regular == 0UL) - && (tmp_adc_is_conversion_on_going_injected == 0UL) - ) - { - /* Set the selected ADC calibration value */ - LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor); - } - else - { - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - /* Update ADC error code */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - /* Update ADC state machine to error */ - tmp_hal_status = HAL_ERROR; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Enable ADC, start conversion of injected group. - * @note Interruptions enabled in this function: None. - * @note Case of multimode enabled when multimode feature is available: - * HAL_ADCEx_InjectedStart() API must be called for ADC slave first, - * then for ADC master. - * For ADC slave, ADC is enabled only (conversion is not started). - * For ADC master, ADC is enabled and multimode conversion is started. - * @param hadc ADC handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - uint32_t tmp_config_injected_queue; -#if defined(ADC_MULTIMODE_SUPPORT) - uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); -#endif - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) - { - return HAL_BUSY; - } - else - { - /* In case of software trigger detection enabled, JQDIS must be set - (which can be done only if ADSTART and JADSTART are both cleared). - If JQDIS is not set at that point, returns an error - - since software trigger detection is disabled. User needs to - resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. - - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means - the queue is empty */ - tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); - - if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) - && (tmp_config_injected_queue == 0UL) - ) - { - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - tmp_hal_status = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmp_hal_status == HAL_OK) - { - /* Check if a regular conversion is ongoing */ - if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL) - { - /* Reset ADC error code field related to injected conversions only */ - CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); - } - else - { - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Set ADC state */ - /* - Clear state bitfield related to injected group conversion results */ - /* - Set state bitfield related to injected operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, - HAL_ADC_STATE_INJ_BUSY); - -#if defined(ADC_MULTIMODE_SUPPORT) - /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - - if ADC instance is master or if multimode feature is not available - - if multimode setting is disabled (ADC instance slave in independent mode) */ - if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - ) - { - CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - } -#endif - - /* Clear ADC group injected group conversion flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Enable conversion of injected group, if automatic injected conversion */ - /* is disabled. */ - /* If software start has been selected, conversion starts immediately. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - /* Case of multimode enabled (when multimode feature is available): */ - /* if ADC is slave, */ - /* - ADC is enabled only (conversion is not started), */ - /* - if multimode only concerns regular conversion, ADC is enabled */ - /* and conversion is started. */ - /* If ADC is master or independent, */ - /* - ADC is enabled and conversion is started. */ -#if defined(ADC_MULTIMODE_SUPPORT) - if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) - ) - { - /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ - if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) - { - LL_ADC_INJ_StartConversion(hadc->Instance); - } - } - else - { - /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ - SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - } -#else - if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) - { - /* Start ADC group injected conversion */ - LL_ADC_INJ_StartConversion(hadc->Instance); - } -#endif - - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hadc); - } - - /* Return function status */ - return tmp_hal_status; - } -} - -/** - * @brief Stop conversion of injected channels. Disable ADC peripheral if - * no regular conversion is on going. - * @note If ADC must be disabled and if conversion is on going on - * regular group, function HAL_ADC_Stop must be used to stop both - * injected and regular groups, and disable the ADC. - * @note If injected group mode auto-injection is enabled, - * function HAL_ADC_Stop must be used. - * @note In case of multimode enabled (when multimode feature is available), - * HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave. - * For ADC master, conversion is stopped and ADC is disabled. - * For ADC slave, ADC is disabled only (conversion stop of ADC master - * has already stopped conversion of ADC slave). - * @param hadc ADC handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* 1. Stop potential conversion on going on injected group only. */ - tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP); - - /* Disable ADC peripheral if injected conversions are effectively stopped */ - /* and if no conversion on regular group is on-going */ - if (tmp_hal_status == HAL_OK) - { - if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - { - /* 2. Disable the ADC peripheral */ - tmp_hal_status = ADC_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - } - /* Conversion on injected group is stopped, but ADC not disabled since */ - /* conversion on regular group is still running. */ - else - { - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Wait for injected group conversion to be completed. - * @param hadc ADC handle - * @param Timeout Timeout value in millisecond. - * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is - * checked and cleared depending on AUTDLY bit status. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) -{ - uint32_t tickstart; - uint32_t tmp_Flag_End; - uint32_t tmp_adc_inj_is_trigger_source_sw_start; - uint32_t tmp_adc_reg_is_trigger_source_sw_start; - uint32_t tmp_cfgr; -#if defined(ADC_MULTIMODE_SUPPORT) - const ADC_TypeDef *tmpADC_Master; - uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); -#endif - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* If end of sequence selected */ - if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) - { - tmp_Flag_End = ADC_FLAG_JEOS; - } - else /* end of conversion selected */ - { - tmp_Flag_End = ADC_FLAG_JEOC; - } - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait until End of Conversion or Sequence flag is raised */ - while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) - { - /* Check if timeout is disabled (set to infinite wait) */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) - { - /* New check to avoid false timeout detection in case of preemption */ - if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) - { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_TIMEOUT; - } - } - } - } - - /* Retrieve ADC configuration */ - tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance); - tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance); - /* Get relevant register CFGR in ADC instance of ADC master or slave */ - /* in function of multimode state (for devices with multimode */ - /* available). */ -#if defined(ADC_MULTIMODE_SUPPORT) - if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) - ) - { - tmp_cfgr = READ_REG(hadc->Instance->CFGR); - } - else - { - tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); - tmp_cfgr = READ_REG(tmpADC_Master->CFGR); - } -#else - tmp_cfgr = READ_REG(hadc->Instance->CFGR); -#endif - - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); - - /* Determine whether any further conversion upcoming on group injected */ - /* by external trigger or by automatic injected conversion */ - /* from group regular. */ - if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || - ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && - ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && - (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))) - { - /* Check whether end of sequence is reached */ - if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) - { - /* Particular case if injected contexts queue is enabled: */ - /* when the last context has been fully processed, JSQR is reset */ - /* by the hardware. Even if no injected conversion is planned to come */ - /* (queue empty, triggers are ignored), it can start again */ - /* immediately after setting a new context (JADSTART is still set). */ - /* Therefore, state of HAL ADC injected group is kept to busy. */ - if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) - { - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - - if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - } - } - - /* Clear polled flag */ - if (tmp_Flag_End == ADC_FLAG_JEOS) - { - /* Clear end of sequence JEOS flag of injected group if low power feature */ - /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */ - /* For injected groups, no new conversion will start before JEOS is */ - /* cleared. */ - if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL) - { - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); - } - } - else - { - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); - } - - /* Return API HAL status */ - return HAL_OK; -} - -/** - * @brief Enable ADC, start conversion of injected group with interruption. - * @note Interruptions enabled in this function according to initialization - * setting : JEOC (end of conversion) or JEOS (end of sequence) - * @note Case of multimode enabled (when multimode feature is enabled): - * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first, - * then for ADC master. - * For ADC slave, ADC is enabled only (conversion is not started). - * For ADC master, ADC is enabled and multimode conversion is started. - * @param hadc ADC handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - uint32_t tmp_config_injected_queue; -#if defined(ADC_MULTIMODE_SUPPORT) - uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); -#endif - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) - { - return HAL_BUSY; - } - else - { - /* In case of software trigger detection enabled, JQDIS must be set - (which can be done only if ADSTART and JADSTART are both cleared). - If JQDIS is not set at that point, returns an error - - since software trigger detection is disabled. User needs to - resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. - - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means - the queue is empty */ - tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); - - if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) - && (tmp_config_injected_queue == 0UL) - ) - { - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - tmp_hal_status = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmp_hal_status == HAL_OK) - { - /* Check if a regular conversion is ongoing */ - if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL) - { - /* Reset ADC error code field related to injected conversions only */ - CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); - } - else - { - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Set ADC state */ - /* - Clear state bitfield related to injected group conversion results */ - /* - Set state bitfield related to injected operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, - HAL_ADC_STATE_INJ_BUSY); - -#if defined(ADC_MULTIMODE_SUPPORT) - /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - - if ADC instance is master or if multimode feature is not available - - if multimode setting is disabled (ADC instance slave in independent mode) */ - if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - ) - { - CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - } -#endif - - /* Clear ADC group injected group conversion flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Enable ADC Injected context queue overflow interrupt if this feature */ - /* is enabled. */ - if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL) - { - __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF); - } - - /* Enable ADC end of conversion interrupt */ - switch (hadc->Init.EOCSelection) - { - case ADC_EOC_SEQ_CONV: - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); - break; - /* case ADC_EOC_SINGLE_CONV */ - default: - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); - break; - } - - /* Enable conversion of injected group, if automatic injected conversion */ - /* is disabled. */ - /* If software start has been selected, conversion starts immediately. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - /* Case of multimode enabled (when multimode feature is available): */ - /* if ADC is slave, */ - /* - ADC is enabled only (conversion is not started), */ - /* - if multimode only concerns regular conversion, ADC is enabled */ - /* and conversion is started. */ - /* If ADC is master or independent, */ - /* - ADC is enabled and conversion is started. */ -#if defined(ADC_MULTIMODE_SUPPORT) - if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) - ) - { - /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ - if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) - { - LL_ADC_INJ_StartConversion(hadc->Instance); - } - } - else - { - /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ - SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - } -#else - if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) - { - /* Start ADC group injected conversion */ - LL_ADC_INJ_StartConversion(hadc->Instance); - } -#endif - - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hadc); - } - - /* Return function status */ - return tmp_hal_status; - } -} - -/** - * @brief Stop conversion of injected channels, disable interruption of - * end-of-conversion. Disable ADC peripheral if no regular conversion - * is on going. - * @note If ADC must be disabled and if conversion is on going on - * regular group, function HAL_ADC_Stop must be used to stop both - * injected and regular groups, and disable the ADC. - * @note If injected group mode auto-injection is enabled, - * function HAL_ADC_Stop must be used. - * @note Case of multimode enabled (when multimode feature is available): - * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first, - * then for ADC slave. - * For ADC master, conversion is stopped and ADC is disabled. - * For ADC slave, ADC is disabled only (conversion stop of ADC master - * has already stopped conversion of ADC slave). - * @note In case of auto-injection mode, HAL_ADC_Stop() must be used. - * @param hadc ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* 1. Stop potential conversion on going on injected group only. */ - tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP); - - /* Disable ADC peripheral if injected conversions are effectively stopped */ - /* and if no conversion on the other group (regular group) is intended to */ - /* continue. */ - if (tmp_hal_status == HAL_OK) - { - /* Disable ADC end of conversion interrupt for injected channels */ - __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF)); - - if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - { - /* 2. Disable the ADC peripheral */ - tmp_hal_status = ADC_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - } - /* Conversion on injected group is stopped, but ADC not disabled since */ - /* conversion on regular group is still running. */ - else - { - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -#if defined(ADC_MULTIMODE_SUPPORT) -/** - * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA. - * @note Multimode must have been previously configured using - * HAL_ADCEx_MultiModeConfigChannel() function. - * Interruptions enabled in this function: - * overrun, DMA half transfer, DMA transfer complete. - * Each of these interruptions has its dedicated callback function. - * @note State field of Slave ADC handle is not updated in this configuration: - * user should not rely on it for information related to Slave regular - * conversions. - * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) - * @param pData Destination Buffer address. - * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) -{ - HAL_StatusTypeDef tmp_hal_status; - ADC_HandleTypeDef tmphadcSlave; - ADC_Common_TypeDef *tmpADC_Common; - - /* Check the parameters */ - assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); - - if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) - { - return HAL_BUSY; - } - else - { - /* Process locked */ - __HAL_LOCK(hadc); - - /* Temporary handle minimum initialization */ - __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); - ADC_CLEAR_ERRORCODE(&tmphadcSlave); - - /* Set a temporary handle of the ADC slave associated to the ADC master */ - ADC_MULTI_SLAVE(hadc, &tmphadcSlave); - - if (tmphadcSlave.Instance == NULL) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - - /* Enable the ADC peripherals: master and slave (in case if not already */ - /* enabled previously) */ - tmp_hal_status = ADC_Enable(hadc); - if (tmp_hal_status == HAL_OK) - { - tmp_hal_status = ADC_Enable(&tmphadcSlave); - } - - /* Start multimode conversion of ADCs pair */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP), - HAL_ADC_STATE_REG_BUSY); - - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Set the DMA transfer complete callback */ - hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; - - /* Set the DMA half transfer complete callback */ - hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; - - /* Set the DMA error callback */ - hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ; - - /* Pointer to the common control register */ - tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); - - /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ - /* start (in case of SW start): */ - - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Enable ADC overrun interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - - /* Start the DMA channel */ - tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); - - /* Enable conversion of regular group. */ - /* If software start has been selected, conversion starts immediately. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - /* Start ADC group regular conversion */ - LL_ADC_REG_StartConversion(hadc->Instance); - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hadc); - } - - /* Return function status */ - return tmp_hal_status; - } -} - -/** - * @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral. - * @note Multimode is kept enabled after this function. MultiMode DMA bits - * (MDMA and DMACFG bits of common CCR register) are maintained. To disable - * Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be - * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can - * resort to HAL_ADCEx_DisableMultiMode() API. - * @note In case of DMA configured in circular mode, function - * HAL_ADC_Stop_DMA() must be called after this function with handle of - * ADC slave, to properly disable the DMA channel. - * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - uint32_t tickstart; - ADC_HandleTypeDef tmphadcSlave; - uint32_t tmphadcSlave_conversion_on_going; - HAL_StatusTypeDef tmphadcSlave_disable_status; - - /* Check the parameters */ - assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - - /* 1. Stop potential multimode conversion on going, on regular and injected groups */ - tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); - - /* Disable ADC peripheral if conversions are effectively stopped */ - if (tmp_hal_status == HAL_OK) - { - /* Temporary handle minimum initialization */ - __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); - ADC_CLEAR_ERRORCODE(&tmphadcSlave); - - /* Set a temporary handle of the ADC slave associated to the ADC master */ - ADC_MULTI_SLAVE(hadc, &tmphadcSlave); - - if (tmphadcSlave.Instance == NULL) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - - /* Procedure to disable the ADC peripheral: wait for conversions */ - /* effectively stopped (ADC master and ADC slave), then disable ADC */ - - /* 1. Wait for ADC conversion completion for ADC master and ADC slave */ - tickstart = HAL_GetTick(); - - tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); - while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) - || (tmphadcSlave_conversion_on_going == 1UL) - ) - { - if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) - { - /* New check to avoid false timeout detection in case of preemption */ - tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); - if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) - || (tmphadcSlave_conversion_on_going == 1UL) - ) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - } - - tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); - } - - /* Disable the DMA channel (in case of DMA in circular mode or stop */ - /* while DMA transfer is on going) */ - /* Note: DMA channel of ADC slave should be stopped after this function */ - /* with HAL_ADC_Stop_DMA() API. */ - tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - - /* Check if DMA channel effectively disabled */ - if (tmp_hal_status == HAL_ERROR) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); - } - - /* Disable ADC overrun interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - - /* 2. Disable the ADC peripherals: master and slave */ - /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */ - /* memory a potential failing status. */ - if (tmp_hal_status == HAL_OK) - { - tmphadcSlave_disable_status = ADC_Disable(&tmphadcSlave); - if ((ADC_Disable(hadc) == HAL_OK) && - (tmphadcSlave_disable_status == HAL_OK)) - { - tmp_hal_status = HAL_OK; - } - } - else - { - /* In case of error, attempt to disable ADC master and slave without status assert */ - (void) ADC_Disable(hadc); - (void) ADC_Disable(&tmphadcSlave); - } - - /* Set ADC state (ADC master) */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration. - * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used) - * @retval The converted data values. - */ -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) -{ - const ADC_Common_TypeDef *tmpADC_Common; - - /* Check the parameters */ - assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); - - /* Prevent unused argument(s) compilation warning if no assert_param check */ - /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */ - UNUSED(hadc); - - /* Pointer to the common control register */ - tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); - - /* Return the multi mode conversion value */ - return tmpADC_Common->CDR; -} -#endif /* ADC_MULTIMODE_SUPPORT */ - -/** - * @brief Get ADC injected group conversion result. - * @note Reading register JDRx automatically clears ADC flag JEOC - * (ADC group injected end of unitary conversion). - * @note This function does not clear ADC flag JEOS - * (ADC group injected end of sequence conversion) - * Occurrence of flag JEOS rising: - * - If sequencer is composed of 1 rank, flag JEOS is equivalent - * to flag JEOC. - * - If sequencer is composed of several ranks, during the scan - * sequence flag JEOC only is raised, at the end of the scan sequence - * both flags JEOC and EOS are raised. - * Flag JEOS must not be cleared by this function because - * it would not be compliant with low power features - * (feature low power auto-wait, not available on all STM32 families). - * To clear this flag, either use function: - * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming - * model polling: @ref HAL_ADCEx_InjectedPollForConversion() - * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS). - * @param hadc ADC handle - * @param InjectedRank the converted ADC injected rank. - * This parameter can be one of the following values: - * @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1 - * @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2 - * @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3 - * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4 - * @retval ADC group injected conversion data - */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank) -{ - uint32_t tmp_jdr; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); - - /* Get ADC converted value */ - switch (InjectedRank) - { - case ADC_INJECTED_RANK_4: - tmp_jdr = hadc->Instance->JDR4; - break; - case ADC_INJECTED_RANK_3: - tmp_jdr = hadc->Instance->JDR3; - break; - case ADC_INJECTED_RANK_2: - tmp_jdr = hadc->Instance->JDR2; - break; - case ADC_INJECTED_RANK_1: - default: - tmp_jdr = hadc->Instance->JDR1; - break; - } - - /* Return ADC converted value */ - return tmp_jdr; -} - -/** - * @brief Injected conversion complete callback in non-blocking mode. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file. - */ -} - -/** - * @brief Injected context queue overflow callback. - * @note This callback is called if injected context queue is enabled - (parameter "QueueInjectedContext" in injected channel configuration) - and if a new injected context is set when queue is full (maximum 2 - contexts). - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file. - */ -} - -/** - * @brief Analog watchdog 2 callback in non-blocking mode. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file. - */ -} - -/** - * @brief Analog watchdog 3 callback in non-blocking mode. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file. - */ -} - - -/** - * @brief End Of Sampling callback in non-blocking mode. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file. - */ -} - -/** - * @brief Stop ADC conversion of regular group (and injected channels in - * case of auto_injection mode), disable ADC peripheral if no - * conversion is on going on injected group. - * @param hadc ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* 1. Stop potential regular conversion on going */ - tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); - - /* Disable ADC peripheral if regular conversions are effectively stopped - and if no injected conversions are on-going */ - if (tmp_hal_status == HAL_OK) - { - /* Clear HAL_ADC_STATE_REG_BUSY bit */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - - if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) - { - /* 2. Disable the ADC peripheral */ - tmp_hal_status = ADC_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - } - /* Conversion on injected group is stopped, but ADC not disabled since */ - /* conversion on regular group is still running. */ - else - { - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - - -/** - * @brief Stop ADC conversion of ADC groups regular and injected, - * disable interrution of end-of-conversion, - * disable ADC peripheral if no conversion is on going - * on injected group. - * @param hadc ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* 1. Stop potential regular conversion on going */ - tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); - - /* Disable ADC peripheral if conversions are effectively stopped - and if no injected conversion is on-going */ - if (tmp_hal_status == HAL_OK) - { - /* Clear HAL_ADC_STATE_REG_BUSY bit */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - - /* Disable all regular-related interrupts */ - __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); - - /* 2. Disable ADC peripheral if no injected conversions are on-going */ - if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) - { - tmp_hal_status = ADC_Disable(hadc); - /* if no issue reported */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - } - else - { - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Stop ADC conversion of regular group (and injected group in - * case of auto_injection mode), disable ADC DMA transfer, disable - * ADC peripheral if no conversion is on going - * on injected group. - * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only. - * For multimode (when multimode feature is available), - * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used. - * @param hadc ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* 1. Stop potential regular conversion on going */ - tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); - - /* Disable ADC peripheral if conversions are effectively stopped - and if no injected conversion is on-going */ - if (tmp_hal_status == HAL_OK) - { - /* Clear HAL_ADC_STATE_REG_BUSY bit */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - - /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ - CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); - - /* Disable the DMA channel (in case of DMA in circular mode or stop while */ - /* while DMA transfer is on going) */ - tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - - /* Check if DMA channel effectively disabled */ - if (tmp_hal_status != HAL_OK) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); - } - - /* Disable ADC overrun interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - - /* 2. Disable the ADC peripheral */ - /* Update "tmp_hal_status" only if DMA channel disabling passed, */ - /* to keep in memory a potential failing status. */ - if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) - { - if (tmp_hal_status == HAL_OK) - { - tmp_hal_status = ADC_Disable(hadc); - } - else - { - (void)ADC_Disable(hadc); - } - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - } - else - { - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -#if defined(ADC_MULTIMODE_SUPPORT) -/** - * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going. - * @note Multimode is kept enabled after this function. Multimode DMA bits - * (MDMA and DMACFG bits of common CCR register) are maintained. To disable - * multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be - * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can - * resort to HAL_ADCEx_DisableMultiMode() API. - * @note In case of DMA configured in circular mode, function - * HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of - * ADC slave, to properly disable the DMA channel. - * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - uint32_t tickstart; - ADC_HandleTypeDef tmphadcSlave; - uint32_t tmphadcSlave_conversion_on_going; - - /* Check the parameters */ - assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - - /* 1. Stop potential multimode conversion on going, on regular groups */ - tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); - - /* Disable ADC peripheral if conversions are effectively stopped */ - if (tmp_hal_status == HAL_OK) - { - /* Clear HAL_ADC_STATE_REG_BUSY bit */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - - /* Temporary handle minimum initialization */ - __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); - ADC_CLEAR_ERRORCODE(&tmphadcSlave); - - /* Set a temporary handle of the ADC slave associated to the ADC master */ - ADC_MULTI_SLAVE(hadc, &tmphadcSlave); - - if (tmphadcSlave.Instance == NULL) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - - /* Procedure to disable the ADC peripheral: wait for conversions */ - /* effectively stopped (ADC master and ADC slave), then disable ADC */ - - /* 1. Wait for ADC conversion completion for ADC master and ADC slave */ - tickstart = HAL_GetTick(); - - tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); - while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) - || (tmphadcSlave_conversion_on_going == 1UL) - ) - { - if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) - { - /* New check to avoid false timeout detection in case of preemption */ - tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); - if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) - || (tmphadcSlave_conversion_on_going == 1UL) - ) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - } - - tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); - } - - /* Disable the DMA channel (in case of DMA in circular mode or stop */ - /* while DMA transfer is on going) */ - /* Note: DMA channel of ADC slave should be stopped after this function */ - /* with HAL_ADCEx_RegularStop_DMA() API. */ - tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - - /* Check if DMA channel effectively disabled */ - if (tmp_hal_status != HAL_OK) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); - } - - /* Disable ADC overrun interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - - /* 2. Disable the ADC peripherals: master and slave if no injected */ - /* conversion is on-going. */ - /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */ - /* memory a potential failing status. */ - if (tmp_hal_status == HAL_OK) - { - if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) - { - tmp_hal_status = ADC_Disable(hadc); - if (tmp_hal_status == HAL_OK) - { - if (LL_ADC_INJ_IsConversionOngoing((&tmphadcSlave)->Instance) == 0UL) - { - tmp_hal_status = ADC_Disable(&tmphadcSlave); - } - } - } - - if (tmp_hal_status == HAL_OK) - { - /* Both Master and Slave ADC's could be disabled. Update Master State */ - /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */ - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); - } - else - { - /* injected (Master or Slave) conversions are still on-going, - no Master State change */ - } - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} -#endif /* ADC_MULTIMODE_SUPPORT */ - -/** - * @} - */ - -/** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions - * @brief ADC Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure channels on injected group - (+) Configure multimode when multimode feature is available - (+) Enable or Disable Injected Queue - (+) Disable ADC voltage regulator - (+) Enter ADC deep-power-down mode - -@endverbatim - * @{ - */ - -/** - * @brief Configure a channel to be assigned to ADC group injected. - * @note Possibility to update parameters on the fly: - * This function initializes injected group, following calls to this - * function can be used to reconfigure some parameters of structure - * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC. - * The setting of these parameters is conditioned to ADC state: - * Refer to comments of structure "ADC_InjectionConfTypeDef". - * @note In case of usage of internal measurement channels: - * Vbat/VrefInt/TempSensor. - * These internal paths can be disabled using function - * HAL_ADC_DeInit(). - * @note Caution: For Injected Context Queue use, a context must be fully - * defined before start of injected conversion. All channels are configured - * consecutively for the same ADC instance. Therefore, the number of calls to - * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter - * InjectedNbrOfConversion for each context. - * - Example 1: If 1 context is intended to be used (or if there is no use of the - * Injected Queue Context feature) and if the context contains 3 injected ranks - * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be - * called once for each channel (i.e. 3 times) before starting a conversion. - * This function must not be called to configure a 4th injected channel: - * it would start a new context into context queue. - * - Example 2: If 2 contexts are intended to be used and each of them contains - * 3 injected ranks (InjectedNbrOfConversion = 3), - * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and - * for each context (3 channels x 2 contexts = 6 calls). Conversion can - * start once the 1st context is set, that is after the first three - * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly. - * @param hadc ADC handle - * @param sConfigInjected Structure of ADC injected group and ADC channel for - * injected group. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmpOffsetShifted; - uint32_t tmp_config_internal_channel; - uint32_t tmp_adc_is_conversion_on_going_regular; - uint32_t tmp_adc_is_conversion_on_going_injected; - __IO uint32_t wait_loop_index = 0; - - uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); - assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext)); - assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); - assert_param(IS_ADC_EXTTRIGINJEC(hadc, sConfigInjected->ExternalTrigInjecConv)); - assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber)); - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset)); - assert_param(IS_ADC_OFFSET_SIGN(sConfigInjected->InjectedOffsetSign)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedOffsetSaturation)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode)); - - if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) - { - assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); - assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); - } - - - /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is - ignored (considered as reset) */ - assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE))); - - /* JDISCEN and JAUTO bits can't be set at the same time */ - assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); - - /* DISCEN and JAUTO bits can't be set at the same time */ - assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); - - /* Verification of channel number */ - if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) - { - assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel)); - } - else - { - assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfigInjected->InjectedChannel)); - } - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Configuration of injected group sequencer: */ - /* Hardware constraint: Must fully define injected context register JSQR */ - /* before make it entering into injected sequencer queue. */ - /* */ - /* - if scan mode is disabled: */ - /* * Injected channels sequence length is set to 0x00: 1 channel */ - /* converted (channel on injected rank 1) */ - /* Parameter "InjectedNbrOfConversion" is discarded. */ - /* * Injected context register JSQR setting is simple: register is fully */ - /* defined on one call of this function (for injected rank 1) and can */ - /* be entered into queue directly. */ - /* - if scan mode is enabled: */ - /* * Injected channels sequence length is set to parameter */ - /* "InjectedNbrOfConversion". */ - /* * Injected context register JSQR setting more complex: register is */ - /* fully defined over successive calls of this function, for each */ - /* injected channel rank. It is entered into queue only when all */ - /* injected ranks have been set. */ - /* Note: Scan mode is not present by hardware on this device, but used */ - /* by software for alignment over all STM32 devices. */ - - if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) || - (sConfigInjected->InjectedNbrOfConversion == 1U)) - { - /* Configuration of context register JSQR: */ - /* - number of ranks in injected group sequencer: fixed to 1st rank */ - /* (scan mode disabled, only rank 1 used) */ - /* - external trigger to start conversion */ - /* - external trigger polarity */ - /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */ - - if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) - { - /* Enable external trigger if trigger selection is different of */ - /* software start. */ - /* Note: This configuration keeps the hardware feature of parameter */ - /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ - /* software start. */ - if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) - { - tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) - | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) - | sConfigInjected->ExternalTrigInjecConvEdge - ); - } - else - { - tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)); - } - - MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt); - /* For debug and informative reasons, hadc handle saves JSQR setting */ - hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt; - - } - } - else - { - /* Case of scan mode enabled, several channels to set into injected group */ - /* sequencer. */ - /* */ - /* Procedure to define injected context register JSQR over successive */ - /* calls of this function, for each injected channel rank: */ - /* 1. Start new context and set parameters related to all injected */ - /* channels: injected sequence length and trigger. */ - - /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */ - /* call of the context under setting */ - if (hadc->InjectionConfig.ChannelCount == 0U) - { - /* Initialize number of channels that will be configured on the context */ - /* being built */ - hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion; - /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel() - call, this context will be written in JSQR register at the last call. - At this point, the context is merely reset */ - hadc->InjectionConfig.ContextQueue = 0x00000000U; - - /* Configuration of context register JSQR: */ - /* - number of ranks in injected group sequencer */ - /* - external trigger to start conversion */ - /* - external trigger polarity */ - - /* Enable external trigger if trigger selection is different of */ - /* software start. */ - /* Note: This configuration keeps the hardware feature of parameter */ - /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ - /* software start. */ - if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) - { - tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U) - | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) - | sConfigInjected->ExternalTrigInjecConvEdge - ); - } - else - { - tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U)); - } - - } - - /* 2. Continue setting of context under definition with parameter */ - /* related to each channel: channel rank sequence */ - /* Clear the old JSQx bits for the selected rank */ - tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank); - - /* Set the JSQx bits for the selected rank */ - tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank); - - /* Decrease channel count */ - hadc->InjectionConfig.ChannelCount--; - - /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel() - call, aggregate the setting to those already built during the previous - HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */ - hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt; - - /* 4. End of context setting: if this is the last channel set, then write context - into register JSQR and make it enter into queue */ - if (hadc->InjectionConfig.ChannelCount == 0U) - { - MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue); - } - } - - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated when ADC is disabled or enabled without */ - /* conversion on going on injected group: */ - /* - Injected context queue: Queue disable (active context is kept) or */ - /* enable (context decremented, up to 2 contexts queued) */ - /* - Injected discontinuous mode: can be enabled only if auto-injected */ - /* mode is disabled. */ - if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) - { - /* If auto-injected mode is disabled: no constraint */ - if (sConfigInjected->AutoInjectedConv == DISABLE) - { - MODIFY_REG(hadc->Instance->CFGR, - ADC_CFGR_JQM | ADC_CFGR_JDISCEN, - ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) | - ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode)); - } - /* If auto-injected mode is enabled: Injected discontinuous setting is */ - /* discarded. */ - else - { - MODIFY_REG(hadc->Instance->CFGR, - ADC_CFGR_JQM | ADC_CFGR_JDISCEN, - ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext)); - } - - } - - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated when ADC is disabled or enabled without */ - /* conversion on going on regular and injected groups: */ - /* - Automatic injected conversion: can be enabled if injected group */ - /* external triggers are disabled. */ - /* - Channel sampling time */ - /* - Channel offset */ - tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); - tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - - if ((tmp_adc_is_conversion_on_going_regular == 0UL) - && (tmp_adc_is_conversion_on_going_injected == 0UL) - ) - { - /* If injected group external triggers are disabled (set to injected */ - /* software start): no constraint */ - if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) - || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) - { - if (sConfigInjected->AutoInjectedConv == ENABLE) - { - SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); - } - else - { - CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); - } - } - /* If Automatic injected conversion was intended to be set and could not */ - /* due to injected group external triggers enabled, error is reported. */ - else - { - if (sConfigInjected->AutoInjectedConv == ENABLE) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; - } - else - { - CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); - } - } - - if (sConfigInjected->InjecOversamplingMode == ENABLE) - { - assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio)); - assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift)); - - /* JOVSE must be reset in case of triggered regular mode */ - assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS))); - - /* Configuration of Injected Oversampler: */ - /* - Oversampling Ratio */ - /* - Right bit shift */ - - /* Enable OverSampling mode */ - MODIFY_REG(hadc->Instance->CFGR2, - ADC_CFGR2_JOVSE | - ADC_CFGR2_OVSR | - ADC_CFGR2_OVSS, - ADC_CFGR2_JOVSE | - sConfigInjected->InjecOversampling.Ratio | - sConfigInjected->InjecOversampling.RightBitShift - ); - } - else - { - /* Disable Regular OverSampling */ - CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE); - } - - /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ - if (sConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5) - { - /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5); - - /* Set ADC sampling time common configuration */ - LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); - } - else - { - /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime); - - /* Set ADC sampling time common configuration */ - LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); - } - - /* Configure the offset: offset enable/disable, channel, offset value */ - - /* Shift the offset with respect to the selected ADC resolution. */ - /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ - tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset); - - if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) - { - /* Set ADC selected offset number */ - LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel, - tmpOffsetShifted); - - /* Set ADC selected offset sign & saturation */ - LL_ADC_SetOffsetSign(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedOffsetSign); - LL_ADC_SetOffsetSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber, - (sConfigInjected->InjectedOffsetSaturation == ENABLE) ? LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE); - } - else - { - /* Scan each offset register to check if the selected channel is targeted. */ - /* If this is the case, the corresponding offset number is disabled. */ - if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) - { - LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); - } - if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) - { - LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); - } - if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) - { - LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); - } - if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) - { - LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); - } - } - - } - - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated only when ADC is disabled: */ - /* - Single or differential mode */ - if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - { - /* Set mode single-ended or differential input of the selected ADC channel */ - LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff); - - /* Configuration of differential mode */ - /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ - if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) - { - /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, - (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) - + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime); - } - - } - - /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ - /* internal measurement paths enable: If internal channel selected, */ - /* enable dedicated internal buffers and path. */ - /* Note: these internal measurement paths can be disabled using */ - /* HAL_ADC_DeInit(). */ - - if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel)) - { - tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - - /* If the requested internal measurement path has already been enabled, */ - /* bypass the configuration processing. */ - if (((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC1) - || (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC5)) - && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) - { - if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), - LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); - - /* Delay for temperature sensor stabilization time */ - /* Wait loop initialization and execution */ - /* Note: Variable divided by 2 to compensate partially */ - /* CPU processing cycles, scaling in us split to not */ - /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL)); - while (wait_loop_index != 0UL) - { - wait_loop_index--; - } - } - } - else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) - && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) - { - if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), - LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); - } - } - else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) - && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) - { - if (ADC_VREFINT_INSTANCE(hadc)) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), - LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); - } - } - else - { - /* nothing to do */ - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -#if defined(ADC_MULTIMODE_SUPPORT) -/** - * @brief Enable ADC multimode and configure multimode parameters - * @note Possibility to update parameters on the fly: - * This function initializes multimode parameters, following - * calls to this function can be used to reconfigure some parameters - * of structure "ADC_MultiModeTypeDef" on the fly, without resetting - * the ADCs. - * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure - * "ADC_MultiModeTypeDef". - * @note To move back configuration from multimode to single mode, ADC must - * be reset (using function HAL_ADC_Init() ). - * @param hadc Master ADC handle - * @param multimode Structure of ADC multimode configuration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - ADC_Common_TypeDef *tmpADC_Common; - ADC_HandleTypeDef tmphadcSlave; - uint32_t tmphadcSlave_conversion_on_going; - - /* Check the parameters */ - assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_MULTIMODE(multimode->Mode)); - if (multimode->Mode != ADC_MODE_INDEPENDENT) - { - assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode)); - assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); - } - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Temporary handle minimum initialization */ - __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); - ADC_CLEAR_ERRORCODE(&tmphadcSlave); - - ADC_MULTI_SLAVE(hadc, &tmphadcSlave); - - if (tmphadcSlave.Instance == NULL) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated when ADC is disabled or enabled without */ - /* conversion on going on regular group: */ - /* - Multimode DMA configuration */ - /* - Multimode DMA mode */ - tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); - if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - && (tmphadcSlave_conversion_on_going == 0UL)) - { - /* Pointer to the common control register */ - tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); - - /* If multimode is selected, configure all multimode parameters. */ - /* Otherwise, reset multimode parameters (can be used in case of */ - /* transition from multimode to independent mode). */ - if (multimode->Mode != ADC_MODE_INDEPENDENT) - { - MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, - multimode->DMAAccessMode | - ADC_CCR_MULTI_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); - - /* Parameters that can be updated only when ADC is disabled: */ - /* - Multimode mode selection */ - /* - Multimode delay */ - /* Note: Delay range depends on selected resolution: */ - /* from 1 to 12 clock cycles for 12 bits */ - /* from 1 to 10 clock cycles for 10 bits, */ - /* from 1 to 8 clock cycles for 8 bits */ - /* from 1 to 6 clock cycles for 6 bits */ - /* If a higher delay is selected, it will be clipped to maximum delay */ - /* range */ - if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) - { - MODIFY_REG(tmpADC_Common->CCR, - ADC_CCR_DUAL | - ADC_CCR_DELAY, - multimode->Mode | - multimode->TwoSamplingDelay - ); - } - } - else /* ADC_MODE_INDEPENDENT */ - { - CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG); - - /* Parameters that can be updated only when ADC is disabled: */ - /* - Multimode mode selection */ - /* - Multimode delay */ - if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) - { - CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); - } - } - } - /* If one of the ADC sharing the same common group is enabled, no update */ - /* could be done on neither of the multimode structure parameters. */ - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} -#endif /* ADC_MULTIMODE_SUPPORT */ - -/** - * @brief Enable Injected Queue - * @note This function resets CFGR register JQDIS bit in order to enable the - * Injected Queue. JQDIS can be written only when ADSTART and JDSTART - * are both equal to 0 to ensure that no regular nor injected - * conversion is ongoing. - * @param hadc ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - uint32_t tmp_adc_is_conversion_on_going_regular; - uint32_t tmp_adc_is_conversion_on_going_injected; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); - tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - - /* Parameter can be set only if no conversion is on-going */ - if ((tmp_adc_is_conversion_on_going_regular == 0UL) - && (tmp_adc_is_conversion_on_going_injected == 0UL) - ) - { - CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); - - /* Update state, clear previous result related to injected queue overflow */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); - - tmp_hal_status = HAL_OK; - } - else - { - tmp_hal_status = HAL_ERROR; - } - - return tmp_hal_status; -} - -/** - * @brief Disable Injected Queue - * @note This function sets CFGR register JQDIS bit in order to disable the - * Injected Queue. JQDIS can be written only when ADSTART and JDSTART - * are both equal to 0 to ensure that no regular nor injected - * conversion is ongoing. - * @param hadc ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - uint32_t tmp_adc_is_conversion_on_going_regular; - uint32_t tmp_adc_is_conversion_on_going_injected; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); - tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - - /* Parameter can be set only if no conversion is on-going */ - if ((tmp_adc_is_conversion_on_going_regular == 0UL) - && (tmp_adc_is_conversion_on_going_injected == 0UL) - ) - { - LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE); - tmp_hal_status = HAL_OK; - } - else - { - tmp_hal_status = HAL_ERROR; - } - - return tmp_hal_status; -} - -/** - * @brief Disable ADC voltage regulator. - * @note Disabling voltage regulator allows to save power. This operation can - * be carried out only when ADC is disabled. - * @note To enable again the voltage regulator, the user is expected to - * resort to HAL_ADC_Init() API. - * @param hadc ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ - if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - { - LL_ADC_DisableInternalRegulator(hadc->Instance); - tmp_hal_status = HAL_OK; - } - else - { - tmp_hal_status = HAL_ERROR; - } - - return tmp_hal_status; -} - -/** - * @brief Enter ADC deep-power-down mode - * @note This mode is achieved in setting DEEPPWD bit and allows to save power - * in reducing leakage currents. It is particularly interesting before - * entering stop modes. - * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the - * ADC voltage regulator. This means that this API encompasses - * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal - * calibration is lost. - * @note To exit the ADC deep-power-down mode, the user is expected to - * resort to HAL_ADC_Init() API as well as to relaunch a calibration - * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously - * saved calibration factor. - * @param hadc ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ - if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - { - LL_ADC_EnableDeepPowerDown(hadc->Instance); - tmp_hal_status = HAL_OK; - } - else - { - tmp_hal_status = HAL_ERROR; - } - - return tmp_hal_status; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_ADC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c b/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c deleted file mode 100644 index b40c47c..0000000 --- a/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c +++ /dev/null @@ -1,1425 +0,0 @@ -/** - ****************************************************************************** - * @file stm32g4xx_ll_adc.c - * @author MCD Application Team - * @brief ADC LL module driver - ****************************************************************************** - * @attention - * - * Copyright (c) 2019 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32g4xx_ll_adc.h" -#include "stm32g4xx_ll_bus.h" - -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup STM32G4xx_LL_Driver - * @{ - */ - -#if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5) - -/** @addtogroup ADC_LL ADC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup ADC_LL_Private_Constants - * @{ - */ - -/* Definitions of ADC hardware constraints delays */ -/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ -/* not timeout values: */ -/* Timeout values for ADC operations are dependent to device clock */ -/* configuration (system clock versus ADC clock), */ -/* and therefore must be defined in user application. */ -/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */ -/* values definition. */ -/* Note: ADC timeout values are defined here in CPU cycles to be independent */ -/* of device clock setting. */ -/* In user application, ADC timeout values should be defined with */ -/* temporal values, in function of device clock settings. */ -/* Highest ratio CPU clock frequency vs ADC clock frequency: */ -/* - ADC clock from synchronous clock with AHB prescaler 512, */ -/* ADC prescaler 4. */ -/* Ratio max = 512 *4 = 2048 */ -/* - ADC clock from asynchronous clock (PLLP) with prescaler 256. */ -/* Highest CPU clock PLL (PLLR). */ -/* Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256 */ -/* = 3968 */ -/* Unit: CPU cycles. */ -#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (3968UL) -#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) -#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/** @addtogroup ADC_LL_Private_Macros - * @{ - */ - -/* Check of parameters for configuration of ADC hierarchical scope: */ -/* common to several ADC instances. */ -#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ - (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ - || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ - || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ - || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \ - || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \ - || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \ - || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \ - || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \ - || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \ - || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \ - || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \ - || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \ - || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \ - || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \ - || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \ - ) - -/* Check of parameters for configuration of ADC hierarchical scope: */ -/* ADC instance. */ -#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ - (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ - || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ - || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ - || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ - ) - -#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ - (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ - || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ - ) - -#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \ - (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \ - || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ - ) - -/* Check of parameters for configuration of ADC hierarchical scope: */ -/* ADC group regular */ -#if defined(STM32G474xx) || defined(STM32G484xx) -#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ - (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG5) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG6) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG7) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG8) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG9) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG10) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ - || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ - && ( \ - ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ - ) \ - ) \ - || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \ - && ( \ - ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG4) \ - ) \ - ) \ - ) -#elif defined(STM32G473xx) || defined(STM32G483xx) -#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ - (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ - || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ - && ( \ - ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ - ) \ - ) \ - || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \ - && ( \ - ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \ - ) \ - ) \ - ) -#elif defined(STM32G471xx) -#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ - (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ - || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ - && ( \ - ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ - ) \ - ) \ - || (((__ADC_INSTANCE__) == ADC3) \ - && ( \ - ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \ - ) \ - ) \ - ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) -#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ - (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ - ) -#elif defined(STM32G491xx) || defined(STM32G4A1xx) -#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ - (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ - || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ - && ( \ - ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ - ) \ - ) \ - || (((__ADC_INSTANCE__) == ADC3) \ - && ( \ - ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \ - ) \ - ) \ - ) -#endif - -#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ - (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ - || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ - ) - -#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ - (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ - || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ - || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ - ) - -#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \ - (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \ - || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \ - ) - -#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ - (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ - ) - -#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ - (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ - || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ - || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ - || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ - || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ - || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ - || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ - || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ - || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ - ) - -/* Check of parameters for configuration of ADC hierarchical scope: */ -/* ADC group injected */ -#if defined(STM32G474xx) || defined(STM32G484xx) -#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ - (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \ - || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ - && ( \ - ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ - ) \ - ) \ - || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \ - && ( \ - ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \ - ) \ - ) \ - ) -#elif defined(STM32G473xx) || defined(STM32G483xx) -#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ - (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \ - || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ - && ( \ - ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ - ) \ - ) \ - || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \ - && ( \ - ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \ - ) \ - ) \ - ) -#elif defined(STM32G471xx) -#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ - (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \ - || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ - && ( \ - ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ - ) \ - ) \ - || ((((__ADC_INSTANCE__) == ADC3)) \ - && ( \ - ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \ - ) \ - ) \ - ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) -#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ - (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ - ) -#elif defined(STM32G491xx) || defined(STM32G4A1xx) -#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ - (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \ - || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ - && ( \ - ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ - ) \ - ) \ - || ((((__ADC_INSTANCE__) == ADC3)) \ - && ( \ - ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \ - ) \ - ) \ - ) -#endif - -#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ - (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ - || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ - || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ - ) - -#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ - (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ - || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ - ) - -#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ - (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ - || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ - || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ - || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ - ) - -#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ - (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ - || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ - ) - -#if defined(ADC_MULTIMODE_SUPPORT) -/* Check of parameters for configuration of ADC hierarchical scope: */ -/* multimode. */ -#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ - (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ - ) - -#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \ - (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ - || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \ - || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \ - || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \ - || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B) \ - ) - -#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \ - (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \ - ) - -#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ - (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ - || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ - || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ - ) - -#endif /* ADC_MULTIMODE_SUPPORT */ -/** - * @} - */ - - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup ADC_LL_Exported_Functions - * @{ - */ - -/** @addtogroup ADC_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize registers of all ADC instances belonging to - * the same ADC common instance to their default reset values. - * @note This function is performing a hard reset, using high level - * clock source RCC ADC reset. - * Caution: On this STM32 series, if several ADC instances are available - * on the selected device, RCC ADC reset will reset - * all ADC instances belonging to the common ADC instance. - * To de-initialize only 1 ADC instance, use - * function @ref LL_ADC_DeInit(). - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: ADC common registers are de-initialized - * - ERROR: not applicable - */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) -{ - /* Check the parameters */ - assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); - - if (ADCxy_COMMON == ADC12_COMMON) - { - /* Force reset of ADC clock (core clock) */ - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC12); - - /* Release reset of ADC clock (core clock) */ - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC12); - } -#if defined(ADC345_COMMON) - else - { - /* Force reset of ADC clock (core clock) */ - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC345); - - /* Release reset of ADC clock (core clock) */ - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC345); - } -#endif - - return SUCCESS; -} - -/** - * @brief Initialize some features of ADC common parameters - * (all ADC instances belonging to the same ADC common instance) - * and multimode (for devices with several ADC instances available). - * @note The setting of ADC common parameters is conditioned to - * ADC instances state: - * All ADC instances belonging to the same ADC common instance - * must be disabled. - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: ADC common registers are initialized - * - ERROR: ADC common registers are not initialized - */ -ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); - assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); - -#if defined(ADC_MULTIMODE_SUPPORT) - assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); - if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) - { - assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer)); - assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay)); - } -#endif /* ADC_MULTIMODE_SUPPORT */ - - /* Note: Hardware constraint (refer to description of functions */ - /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ - /* On this STM32 series, setting of these features is conditioned to */ - /* ADC state: */ - /* All ADC instances of the ADC common group must be disabled. */ - if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) - { - /* Configuration of ADC hierarchical scope: */ - /* - common to several ADC */ - /* (all ADC instances belonging to the same ADC common instance) */ - /* - Set ADC clock (conversion clock) */ - /* - multimode (if several ADC instances available on the */ - /* selected device) */ - /* - Set ADC multimode configuration */ - /* - Set ADC multimode DMA transfer */ - /* - Set ADC multimode: delay between 2 sampling phases */ -#if defined(ADC_MULTIMODE_SUPPORT) - if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) - { - MODIFY_REG(ADCxy_COMMON->CCR, - ADC_CCR_CKMODE - | ADC_CCR_PRESC - | ADC_CCR_DUAL - | ADC_CCR_MDMA - | ADC_CCR_DELAY - , - ADC_CommonInitStruct->CommonClock - | ADC_CommonInitStruct->Multimode - | ADC_CommonInitStruct->MultiDMATransfer - | ADC_CommonInitStruct->MultiTwoSamplingDelay - ); - } - else - { - MODIFY_REG(ADCxy_COMMON->CCR, - ADC_CCR_CKMODE - | ADC_CCR_PRESC - | ADC_CCR_DUAL - | ADC_CCR_MDMA - | ADC_CCR_DELAY - , - ADC_CommonInitStruct->CommonClock - | LL_ADC_MULTI_INDEPENDENT - ); - } -#else - LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock); -#endif - } - else - { - /* Initialization error: One or several ADC instances belonging to */ - /* the same ADC common instance are not disabled. */ - status = ERROR; - } - - return status; -} - -/** - * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. - * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) -{ - /* Set ADC_CommonInitStruct fields to default values */ - /* Set fields of ADC common */ - /* (all ADC instances belonging to the same ADC common instance) */ - ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; - -#if defined(ADC_MULTIMODE_SUPPORT) - /* Set fields of ADC multimode */ - ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; - ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; - ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE; -#endif /* ADC_MULTIMODE_SUPPORT */ -} - -/** - * @brief De-initialize registers of the selected ADC instance - * to their default reset values. - * @note To reset all ADC instances quickly (perform a hard reset), - * use function @ref LL_ADC_CommonDeInit(). - * @note If this functions returns error status, it means that ADC instance - * is in an unknown state. - * In this case, perform a hard reset using high level - * clock source RCC ADC reset. - * Caution: On this STM32 series, if several ADC instances are available - * on the selected device, RCC ADC reset will reset - * all ADC instances belonging to the common ADC instance. - * Refer to function @ref LL_ADC_CommonDeInit(). - * @param ADCx ADC instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: ADC registers are de-initialized - * - ERROR: ADC registers are not de-initialized - */ -ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) -{ - ErrorStatus status = SUCCESS; - - __IO uint32_t timeout_cpu_cycles = 0UL; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - - /* Disable ADC instance if not already disabled. */ - if (LL_ADC_IsEnabled(ADCx) == 1UL) - { - /* Set ADC group regular trigger source to SW start to ensure to not */ - /* have an external trigger event occurring during the conversion stop */ - /* ADC disable process. */ - LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); - - /* Stop potential ADC conversion on going on ADC group regular. */ - if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL) - { - if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL) - { - LL_ADC_REG_StopConversion(ADCx); - } - } - - /* Set ADC group injected trigger source to SW start to ensure to not */ - /* have an external trigger event occurring during the conversion stop */ - /* ADC disable process. */ - LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); - - /* Stop potential ADC conversion on going on ADC group injected. */ - if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL) - { - if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL) - { - LL_ADC_INJ_StopConversion(ADCx); - } - } - - /* Wait for ADC conversions are effectively stopped */ - timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; - while ((LL_ADC_REG_IsStopConversionOngoing(ADCx) - | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL) - { - timeout_cpu_cycles--; - if (timeout_cpu_cycles == 0UL) - { - /* Time-out error */ - status = ERROR; - break; - } - } - - /* Flush group injected contexts queue (register JSQR): */ - /* Note: Bit JQM must be set to empty the contexts queue (otherwise */ - /* contexts queue is maintained with the last active context). */ - LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY); - - /* Disable the ADC instance */ - LL_ADC_Disable(ADCx); - - /* Wait for ADC instance is effectively disabled */ - timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES; - while (LL_ADC_IsDisableOngoing(ADCx) == 1UL) - { - timeout_cpu_cycles--; - if (timeout_cpu_cycles == 0UL) - { - /* Time-out error */ - status = ERROR; - break; - } - } - } - - /* Check whether ADC state is compliant with expected state */ - if (READ_BIT(ADCx->CR, - (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART - | ADC_CR_ADDIS | ADC_CR_ADEN) - ) - == 0UL) - { - /* ========== Reset ADC registers ========== */ - /* Reset register IER */ - CLEAR_BIT(ADCx->IER, - (LL_ADC_IT_ADRDY - | LL_ADC_IT_EOC - | LL_ADC_IT_EOS - | LL_ADC_IT_OVR - | LL_ADC_IT_EOSMP - | LL_ADC_IT_JEOC - | LL_ADC_IT_JEOS - | LL_ADC_IT_JQOVF - | LL_ADC_IT_AWD1 - | LL_ADC_IT_AWD2 - | LL_ADC_IT_AWD3 - ) - ); - - /* Reset register ISR */ - SET_BIT(ADCx->ISR, - (LL_ADC_FLAG_ADRDY - | LL_ADC_FLAG_EOC - | LL_ADC_FLAG_EOS - | LL_ADC_FLAG_OVR - | LL_ADC_FLAG_EOSMP - | LL_ADC_FLAG_JEOC - | LL_ADC_FLAG_JEOS - | LL_ADC_FLAG_JQOVF - | LL_ADC_FLAG_AWD1 - | LL_ADC_FLAG_AWD2 - | LL_ADC_FLAG_AWD3 - ) - ); - - /* Reset register CR */ - /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */ - /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */ - /* access mode "read-set": no direct reset applicable. */ - /* - Reset Calibration mode to default setting (single ended). */ - /* - Disable ADC internal voltage regulator. */ - /* - Enable ADC deep power down. */ - /* Note: ADC internal voltage regulator disable and ADC deep power */ - /* down enable are conditioned to ADC state disabled: */ - /* already done above. */ - CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF); - SET_BIT(ADCx->CR, ADC_CR_DEEPPWD); - - /* Reset register CFGR */ - MODIFY_REG(ADCx->CFGR, - (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN - | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM - | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN - | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD - | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN - | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN), - ADC_CFGR_JQDIS - ); - - /* Reset register CFGR2 */ - CLEAR_BIT(ADCx->CFGR2, - (ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS - | ADC_CFGR2_SWTRIG | ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG - | ADC_CFGR2_GCOMP - | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) - ); - - /* Reset register SMPR1 */ - CLEAR_BIT(ADCx->SMPR1, - (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 - | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 - | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1) - ); - - /* Reset register SMPR2 */ - CLEAR_BIT(ADCx->SMPR2, - (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 - | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 - | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10) - ); - - /* Reset register TR1 */ - MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT | ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1); - - /* Reset register TR2 */ - MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2); - - /* Reset register TR3 */ - MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3); - - /* Reset register SQR1 */ - CLEAR_BIT(ADCx->SQR1, - (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 - | ADC_SQR1_SQ1 | ADC_SQR1_L) - ); - - /* Reset register SQR2 */ - CLEAR_BIT(ADCx->SQR2, - (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 - | ADC_SQR2_SQ6 | ADC_SQR2_SQ5) - ); - - /* Reset register SQR3 */ - CLEAR_BIT(ADCx->SQR3, - (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 - | ADC_SQR3_SQ11 | ADC_SQR3_SQ10) - ); - - /* Reset register SQR4 */ - CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); - - /* Reset register JSQR */ - CLEAR_BIT(ADCx->JSQR, - (ADC_JSQR_JL - | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN - | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 - | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1) - ); - - /* Reset register DR */ - /* Note: bits in access mode read only, no direct reset applicable */ - - /* Reset register OFR1 */ - CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 | ADC_OFR1_SATEN | ADC_OFR1_OFFSETPOS); - /* Reset register OFR2 */ - CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 | ADC_OFR2_SATEN | ADC_OFR2_OFFSETPOS); - /* Reset register OFR3 */ - CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 | ADC_OFR3_SATEN | ADC_OFR3_OFFSETPOS); - /* Reset register OFR4 */ - CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 | ADC_OFR4_SATEN | ADC_OFR4_OFFSETPOS); - - /* Reset registers JDR1, JDR2, JDR3, JDR4 */ - /* Note: bits in access mode read only, no direct reset applicable */ - - /* Reset register AWD2CR */ - CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH); - - /* Reset register AWD3CR */ - CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH); - - /* Reset register DIFSEL */ - CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL); - - /* Reset register CALFACT */ - CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); - - /* Reset register GCOMP */ - CLEAR_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF); - } - else - { - /* ADC instance is in an unknown state */ - /* Need to performing a hard reset of ADC instance, using high level */ - /* clock source RCC ADC reset. */ - /* Caution: On this STM32 series, if several ADC instances are available */ - /* on the selected device, RCC ADC reset will reset */ - /* all ADC instances belonging to the common ADC instance. */ - /* Caution: On this STM32 series, if several ADC instances are available */ - /* on the selected device, RCC ADC reset will reset */ - /* all ADC instances belonging to the common ADC instance. */ - status = ERROR; - } - - return status; -} - -/** - * @brief Initialize some features of ADC instance. - * @note These parameters have an impact on ADC scope: ADC instance. - * Affects both group regular and group injected (availability - * of ADC group injected depends on STM32 families). - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Instance . - * @note The setting of these parameters by function @ref LL_ADC_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - * @note After using this function, some other features must be configured - * using LL unitary functions. - * The minimum configuration remaining to be done is: - * - Set ADC group regular or group injected sequencer: - * map channel on the selected sequencer rank. - * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). - * - Set ADC channel sampling time - * Refer to function LL_ADC_SetChannelSamplingTime(); - * @param ADCx ADC instance - * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: ADC registers are initialized - * - ERROR: ADC registers are not initialized - */ -ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - - assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); - assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); - assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode)); - - /* Note: Hardware constraint (refer to description of this function): */ - /* ADC instance must be disabled. */ - if (LL_ADC_IsEnabled(ADCx) == 0UL) - { - /* Configuration of ADC hierarchical scope: */ - /* - ADC instance */ - /* - Set ADC data resolution */ - /* - Set ADC conversion data alignment */ - /* - Set ADC low power mode */ - MODIFY_REG(ADCx->CFGR, - ADC_CFGR_RES - | ADC_CFGR_ALIGN - | ADC_CFGR_AUTDLY - , - ADC_InitStruct->Resolution - | ADC_InitStruct->DataAlignment - | ADC_InitStruct->LowPowerMode - ); - - } - else - { - /* Initialization error: ADC instance is not disabled. */ - status = ERROR; - } - - return status; -} - -/** - * @brief Set each @ref LL_ADC_InitTypeDef field to default value. - * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) -{ - /* Set ADC_InitStruct fields to default values */ - /* Set fields of ADC instance */ - ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; - ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; - ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; - -} - -/** - * @brief Initialize some features of ADC group regular. - * @note These parameters have an impact on ADC scope: ADC group regular. - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Group_Regular - * (functions with prefix "REG"). - * @note The setting of these parameters by function @ref LL_ADC_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - * @note After using this function, other features must be configured - * using LL unitary functions. - * The minimum configuration remaining to be done is: - * - Set ADC group regular or group injected sequencer: - * map channel on the selected sequencer rank. - * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). - * - Set ADC channel sampling time - * Refer to function LL_ADC_SetChannelSamplingTime(); - * @param ADCx ADC instance - * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: ADC registers are initialized - * - ERROR: ADC registers are not initialized - */ -ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource)); - assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); - if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) - { - assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); - - /* ADC group regular continuous mode and discontinuous mode */ - /* can not be enabled simultenaeously */ - assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) - || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); - } - assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); - assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); - assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun)); - - /* Note: Hardware constraint (refer to description of this function): */ - /* ADC instance must be disabled. */ - if (LL_ADC_IsEnabled(ADCx) == 0UL) - { - /* Configuration of ADC hierarchical scope: */ - /* - ADC group regular */ - /* - Set ADC group regular trigger source */ - /* - Set ADC group regular sequencer length */ - /* - Set ADC group regular sequencer discontinuous mode */ - /* - Set ADC group regular continuous mode */ - /* - Set ADC group regular conversion data transfer: no transfer or */ - /* transfer by DMA, and DMA requests mode */ - /* - Set ADC group regular overrun behavior */ - /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ - /* setting of trigger source to SW start. */ - if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) - { - MODIFY_REG(ADCx->CFGR, - ADC_CFGR_EXTSEL - | ADC_CFGR_EXTEN - | ADC_CFGR_DISCEN - | ADC_CFGR_DISCNUM - | ADC_CFGR_CONT - | ADC_CFGR_DMAEN - | ADC_CFGR_DMACFG - | ADC_CFGR_OVRMOD - , - ADC_REG_InitStruct->TriggerSource - | ADC_REG_InitStruct->SequencerDiscont - | ADC_REG_InitStruct->ContinuousMode - | ADC_REG_InitStruct->DMATransfer - | ADC_REG_InitStruct->Overrun - ); - } - else - { - MODIFY_REG(ADCx->CFGR, - ADC_CFGR_EXTSEL - | ADC_CFGR_EXTEN - | ADC_CFGR_DISCEN - | ADC_CFGR_DISCNUM - | ADC_CFGR_CONT - | ADC_CFGR_DMAEN - | ADC_CFGR_DMACFG - | ADC_CFGR_OVRMOD - , - ADC_REG_InitStruct->TriggerSource - | LL_ADC_REG_SEQ_DISCONT_DISABLE - | ADC_REG_InitStruct->ContinuousMode - | ADC_REG_InitStruct->DMATransfer - | ADC_REG_InitStruct->Overrun - ); - } - - /* Set ADC group regular sequencer length and scan direction */ - LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); - } - else - { - /* Initialization error: ADC instance is not disabled. */ - status = ERROR; - } - return status; -} - -/** - * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. - * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) -{ - /* Set ADC_REG_InitStruct fields to default values */ - /* Set fields of ADC group regular */ - /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ - /* setting of trigger source to SW start. */ - ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; - ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; - ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; - ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; - ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; - ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; -} - -/** - * @brief Initialize some features of ADC group injected. - * @note These parameters have an impact on ADC scope: ADC group injected. - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Group_Regular - * (functions with prefix "INJ"). - * @note The setting of these parameters by function @ref LL_ADC_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - * @note After using this function, other features must be configured - * using LL unitary functions. - * The minimum configuration remaining to be done is: - * - Set ADC group injected sequencer: - * map channel on the selected sequencer rank. - * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). - * - Set ADC channel sampling time - * Refer to function LL_ADC_SetChannelSamplingTime(); - * @note Caution if feature ADC group injected contexts queue is enabled - * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ): - * using successively several times this function will appear as - * having no effect. - * To set several features of ADC group injected, use - * function @ref LL_ADC_INJ_ConfigQueueContext(). - * @param ADCx ADC instance - * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: ADC registers are initialized - * - ERROR: ADC registers are not initialized - */ -ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource)); - assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); - if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) - { - assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); - } - assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); - - /* Note: Hardware constraint (refer to description of this function): */ - /* ADC instance must be disabled. */ - if (LL_ADC_IsEnabled(ADCx) == 0UL) - { - /* Configuration of ADC hierarchical scope: */ - /* - ADC group injected */ - /* - Set ADC group injected trigger source */ - /* - Set ADC group injected sequencer length */ - /* - Set ADC group injected sequencer discontinuous mode */ - /* - Set ADC group injected conversion trigger: independent or */ - /* from ADC group regular */ - /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ - /* setting of trigger source to SW start. */ - if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) - { - MODIFY_REG(ADCx->CFGR, - ADC_CFGR_JDISCEN - | ADC_CFGR_JAUTO - , - ADC_INJ_InitStruct->SequencerDiscont - | ADC_INJ_InitStruct->TrigAuto - ); - } - else - { - MODIFY_REG(ADCx->CFGR, - ADC_CFGR_JDISCEN - | ADC_CFGR_JAUTO - , - LL_ADC_REG_SEQ_DISCONT_DISABLE - | ADC_INJ_InitStruct->TrigAuto - ); - } - - MODIFY_REG(ADCx->JSQR, - ADC_JSQR_JEXTSEL - | ADC_JSQR_JEXTEN - | ADC_JSQR_JL - , - ADC_INJ_InitStruct->TriggerSource - | ADC_INJ_InitStruct->SequencerLength - ); - } - else - { - /* Initialization error: ADC instance is not disabled. */ - status = ERROR; - } - return status; -} - -/** - * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. - * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) -{ - /* Set ADC_INJ_InitStruct fields to default values */ - /* Set fields of ADC group injected */ - ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; - ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; - ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; - ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ diff --git a/Makefile b/Makefile index 59b30e2..3309444 100644 --- a/Makefile +++ b/Makefile @@ -1,5 +1,5 @@ ########################################################################################################################## -# File automatically-generated by tool: [projectgenerator] version: [3.16.0] date: [Thu Jun 30 03:25:47 CEST 2022] +# File automatically-generated by tool: [projectgenerator] version: [3.17.1] date: [Tue Jul 12 23:51:59 CEST 2022] ########################################################################################################################## # ------------------------------------------------ @@ -39,9 +39,6 @@ C_SOURCES = \ Core/Src/main.c \ Core/Src/stm32g4xx_it.c \ Core/Src/stm32g4xx_hal_msp.c \ -Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c \ -Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c \ -Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c \ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c \ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c \ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c \ diff --git a/Master_Control.ioc b/Master_Control.ioc index 17ae1d2..ca3e805 100644 --- a/Master_Control.ioc +++ b/Master_Control.ioc @@ -1,74 +1,4 @@ #MicroXplorer Configuration settings - do not modify -ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_1 -ADC1.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_2 -ADC1.Channel-2\#ChannelRegularConversion=ADC_CHANNEL_3 -ADC1.Channel-3\#ChannelRegularConversion=ADC_CHANNEL_4 -ADC1.ClockPrescaler=ADC_CLOCK_ASYNC_DIV64 -ADC1.ContinuousConvMode=DISABLE -ADC1.EOCSelection=ADC_EOC_SINGLE_CONV -ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag,master,ContinuousConvMode,EOCSelection,Rank-1\#ChannelRegularConversion,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,OffsetNumber-1\#ChannelRegularConversion,Rank-2\#ChannelRegularConversion,Channel-2\#ChannelRegularConversion,SamplingTime-2\#ChannelRegularConversion,OffsetNumber-2\#ChannelRegularConversion,Rank-3\#ChannelRegularConversion,Channel-3\#ChannelRegularConversion,SamplingTime-3\#ChannelRegularConversion,OffsetNumber-3\#ChannelRegularConversion,NbrOfConversion,ClockPrescaler -ADC1.NbrOfConversion=4 -ADC1.NbrOfConversionFlag=1 -ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE -ADC1.OffsetNumber-1\#ChannelRegularConversion=ADC_OFFSET_NONE -ADC1.OffsetNumber-2\#ChannelRegularConversion=ADC_OFFSET_NONE -ADC1.OffsetNumber-3\#ChannelRegularConversion=ADC_OFFSET_NONE -ADC1.Rank-0\#ChannelRegularConversion=1 -ADC1.Rank-1\#ChannelRegularConversion=2 -ADC1.Rank-2\#ChannelRegularConversion=3 -ADC1.Rank-3\#ChannelRegularConversion=4 -ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5 -ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5 -ADC1.SamplingTime-2\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5 -ADC1.SamplingTime-3\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5 -ADC1.master=1 -ADC2.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_17 -ADC2.ClockPrescaler=ADC_CLOCK_ASYNC_DIV64 -ADC2.ContinuousConvMode=DISABLE -ADC2.EOCSelection=ADC_EOC_SINGLE_CONV -ADC2.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag,ContinuousConvMode,EOCSelection,NbrOfConversion,ClockPrescaler -ADC2.NbrOfConversion=1 -ADC2.NbrOfConversionFlag=1 -ADC2.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE -ADC2.Rank-0\#ChannelRegularConversion=1 -ADC2.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5 -Dma.ADC1.0.Direction=DMA_PERIPH_TO_MEMORY -Dma.ADC1.0.EventEnable=DISABLE -Dma.ADC1.0.Instance=DMA1_Channel2 -Dma.ADC1.0.MemDataAlignment=DMA_MDATAALIGN_HALFWORD -Dma.ADC1.0.MemInc=DMA_MINC_ENABLE -Dma.ADC1.0.Mode=DMA_NORMAL -Dma.ADC1.0.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD -Dma.ADC1.0.PeriphInc=DMA_PINC_DISABLE -Dma.ADC1.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING -Dma.ADC1.0.Priority=DMA_PRIORITY_LOW -Dma.ADC1.0.RequestNumber=1 -Dma.ADC1.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber -Dma.ADC1.0.SignalID=NONE -Dma.ADC1.0.SyncEnable=DISABLE -Dma.ADC1.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT -Dma.ADC1.0.SyncRequestNumber=1 -Dma.ADC1.0.SyncSignalID=NONE -Dma.ADC2.1.Direction=DMA_PERIPH_TO_MEMORY -Dma.ADC2.1.EventEnable=DISABLE -Dma.ADC2.1.Instance=DMA2_Channel1 -Dma.ADC2.1.MemDataAlignment=DMA_MDATAALIGN_HALFWORD -Dma.ADC2.1.MemInc=DMA_MINC_ENABLE -Dma.ADC2.1.Mode=DMA_NORMAL -Dma.ADC2.1.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD -Dma.ADC2.1.PeriphInc=DMA_PINC_DISABLE -Dma.ADC2.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING -Dma.ADC2.1.Priority=DMA_PRIORITY_LOW -Dma.ADC2.1.RequestNumber=1 -Dma.ADC2.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber -Dma.ADC2.1.SignalID=NONE -Dma.ADC2.1.SyncEnable=DISABLE -Dma.ADC2.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT -Dma.ADC2.1.SyncRequestNumber=1 -Dma.ADC2.1.SyncSignalID=NONE -Dma.Request0=ADC1 -Dma.Request1=ADC2 -Dma.RequestsNb=2 FDCAN1.DataPrescaler=2 FDCAN1.DataSyncJumpWidth=4 FDCAN1.DataTimeSeg1=13 @@ -82,85 +12,55 @@ GPIO.groupedBy=Group By Peripherals KeepUserPlacement=false Mcu.CPN=STM32G441CBT3 Mcu.Family=STM32G4 -Mcu.IP0=ADC1 -Mcu.IP1=ADC2 -Mcu.IP2=CRC -Mcu.IP3=DMA -Mcu.IP4=FDCAN1 -Mcu.IP5=NVIC -Mcu.IP6=RCC -Mcu.IP7=SPI1 -Mcu.IP8=SYS -Mcu.IPNb=9 +Mcu.IP0=CRC +Mcu.IP1=FDCAN1 +Mcu.IP2=NVIC +Mcu.IP3=RCC +Mcu.IP4=SPI1 +Mcu.IP5=SYS +Mcu.IPNb=6 Mcu.Name=STM32G441CBTx Mcu.Package=LQFP48 Mcu.Pin0=PC13 Mcu.Pin1=PC14-OSC32_IN -Mcu.Pin10=PA7 -Mcu.Pin11=PB0 -Mcu.Pin12=PB1 -Mcu.Pin13=PB2 -Mcu.Pin14=PB10 -Mcu.Pin15=PB11 -Mcu.Pin16=PB12 -Mcu.Pin17=PB13 -Mcu.Pin18=PB14 -Mcu.Pin19=PB15 +Mcu.Pin10=PA11 +Mcu.Pin11=PA12 +Mcu.Pin12=PA13 +Mcu.Pin13=PA14 +Mcu.Pin14=PB5 +Mcu.Pin15=PB6 +Mcu.Pin16=PB7 +Mcu.Pin17=VP_CRC_VS_CRC +Mcu.Pin18=VP_SYS_VS_Systick +Mcu.Pin19=VP_SYS_VS_DBSignals Mcu.Pin2=PC15-OSC32_OUT -Mcu.Pin20=PA8 -Mcu.Pin21=PA9 -Mcu.Pin22=PA10 -Mcu.Pin23=PA11 -Mcu.Pin24=PA12 -Mcu.Pin25=PA13 -Mcu.Pin26=PA14 -Mcu.Pin27=PB3 -Mcu.Pin28=PB5 -Mcu.Pin29=PB6 -Mcu.Pin3=PA0 -Mcu.Pin30=PB7 -Mcu.Pin31=VP_CRC_VS_CRC -Mcu.Pin32=VP_SYS_VS_Systick -Mcu.Pin33=VP_SYS_VS_DBSignals -Mcu.Pin4=PA1 -Mcu.Pin5=PA2 -Mcu.Pin6=PA3 -Mcu.Pin7=PA4 -Mcu.Pin8=PA5 -Mcu.Pin9=PA6 -Mcu.PinsNb=34 +Mcu.Pin3=PA5 +Mcu.Pin4=PA6 +Mcu.Pin5=PA7 +Mcu.Pin6=PB0 +Mcu.Pin7=PA8 +Mcu.Pin8=PA9 +Mcu.Pin9=PA10 +Mcu.PinsNb=20 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32G441CBTx MxCube.Version=6.5.0 MxDb.Version=DB.6.0.50 -NVIC.ADC1_2_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true -NVIC.BusFault_IRQn=true\:4\:0\:true\:false\:true\:false\:false\:true -NVIC.DMA1_Channel2_IRQn=true\:4\:0\:true\:false\:true\:false\:true\:true -NVIC.DMA2_Channel1_IRQn=true\:4\:0\:true\:false\:true\:false\:true\:true -NVIC.DebugMonitor_IRQn=true\:4\:0\:true\:false\:true\:false\:false\:true +NVIC.BusFault_IRQn=true\:4\:0\:true\:false\:true\:false\:false\:false +NVIC.DebugMonitor_IRQn=true\:4\:0\:true\:false\:true\:false\:false\:false NVIC.FDCAN1_IT0_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true NVIC.FDCAN1_IT1_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true NVIC.ForceEnableDMAVector=true -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true -NVIC.MemoryManagement_IRQn=true\:4\:0\:true\:false\:true\:false\:false\:true -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true -NVIC.PendSV_IRQn=true\:4\:0\:true\:false\:true\:false\:false\:true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:4\:0\:true\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PendSV_IRQn=true\:4\:0\:true\:false\:true\:false\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SPI1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true -NVIC.SVCall_IRQn=true\:4\:0\:true\:false\:true\:false\:false\:true -NVIC.SysTick_IRQn=true\:4\:0\:true\:false\:true\:false\:true\:true -NVIC.UsageFault_IRQn=true\:4\:0\:true\:false\:true\:false\:false\:true -PA0.GPIOParameters=GPIO_Label -PA0.GPIO_Label=Relay_Supply_Voltage -PA0.Locked=true -PA0.Mode=IN1-Single-Ended -PA0.Signal=ADC1_IN1 -PA1.GPIOParameters=GPIO_Label -PA1.GPIO_Label=Pos_AIR_Current -PA1.Locked=true -PA1.Mode=IN2-Single-Ended -PA1.Signal=ADC1_IN2 +NVIC.SVCall_IRQn=true\:4\:0\:true\:false\:true\:false\:false\:false +NVIC.SysTick_IRQn=true\:4\:0\:true\:false\:true\:false\:true\:false +NVIC.UsageFault_IRQn=true\:4\:0\:true\:false\:true\:false\:false\:false PA10.GPIOParameters=GPIO_Label PA10.GPIO_Label=Status_LED PA10.Locked=true @@ -176,21 +76,6 @@ PA13.Signal=SYS_JTMS-SWDIO PA14.Locked=true PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK -PA2.GPIOParameters=GPIO_Label -PA2.GPIO_Label=Neg_AIR_Current -PA2.Locked=true -PA2.Mode=IN3-Single-Ended -PA2.Signal=ADC1_IN3 -PA3.GPIOParameters=GPIO_Label -PA3.GPIO_Label=PreCharge_AIR_Current -PA3.Locked=true -PA3.Mode=IN4-Single-Ended -PA3.Signal=ADC1_IN4 -PA4.GPIOParameters=GPIO_Label -PA4.GPIO_Label=SC_Supply_Voltage -PA4.Locked=true -PA4.Mode=IN17-Single-Ended -PA4.Signal=ADC2_IN17 PA5.Mode=Full_Duplex_Slave PA5.Signal=SPI1_SCK PA6.Mode=Full_Duplex_Slave @@ -209,42 +94,6 @@ PB0.GPIOParameters=GPIO_Label PB0.GPIO_Label=AMS_ERROR PB0.Locked=true PB0.Signal=GPIO_Input -PB1.GPIOParameters=GPIO_Label -PB1.GPIO_Label=IMD_Error -PB1.Locked=true -PB1.Signal=GPIO_Input -PB10.GPIOParameters=GPIO_Label -PB10.GPIO_Label=Volt_Error_CPU -PB10.Locked=true -PB10.Signal=GPIO_Input -PB11.GPIOParameters=GPIO_Label -PB11.GPIO_Label=Positive_Side_Error_CPU -PB11.Locked=true -PB11.Signal=GPIO_Input -PB12.GPIOParameters=GPIO_Label -PB12.GPIO_Label=Neg_Side_Error_CPU -PB12.Locked=true -PB12.Signal=GPIO_Input -PB13.GPIOParameters=GPIO_Label -PB13.GPIO_Label=HV_Inactive_CPU -PB13.Locked=true -PB13.Signal=GPIO_Input -PB14.GPIOParameters=GPIO_Label -PB14.GPIO_Label=Neg_AIR_Open_CPU -PB14.Locked=true -PB14.Signal=GPIO_Input -PB15.GPIOParameters=GPIO_Label -PB15.GPIO_Label=High_Side_Open_CPU -PB15.Locked=true -PB15.Signal=GPIO_Input -PB2.GPIOParameters=GPIO_Label -PB2.GPIO_Label=AMS_Error_LED -PB2.Locked=true -PB2.Signal=GPIO_Input -PB3.GPIOParameters=GPIO_Label -PB3.GPIO_Label=IMD_Error_LED -PB3.Locked=true -PB3.Signal=GPIO_Input PB5.GPIOParameters=GPIO_Label PB5.GPIO_Label=PreCharge_Control PB5.Locked=true @@ -297,31 +146,31 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=Makefile ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_ADC2_Init-ADC2-false-HAL-true,6-MX_FDCAN1_Init-FDCAN1-false-HAL-true,7-MX_SPI1_Init-SPI1-false-HAL-true -RCC.ADC12Freq_Value=64000000 -RCC.AHBFreq_Value=64000000 -RCC.APB1Freq_Value=64000000 -RCC.APB1TimFreq_Value=64000000 -RCC.APB2Freq_Value=64000000 -RCC.APB2TimFreq_Value=64000000 +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_ADC2_Init-ADC2-false-HAL-true,6-MX_FDCAN1_Init-FDCAN1-false-HAL-true,7-MX_SPI1_Init-SPI1-false-HAL-true,8-MX_CRC_Init-CRC-false-HAL-true +RCC.ADC12Freq_Value=16000000 +RCC.AHBFreq_Value=16000000 +RCC.APB1Freq_Value=16000000 +RCC.APB1TimFreq_Value=16000000 +RCC.APB2Freq_Value=16000000 +RCC.APB2TimFreq_Value=16000000 RCC.CRSFreq_Value=48000000 -RCC.CortexFreq_Value=64000000 +RCC.CortexFreq_Value=16000000 RCC.EXTERNAL_CLOCK_VALUE=12288000 -RCC.FCLKCortexFreq_Value=64000000 +RCC.FCLKCortexFreq_Value=16000000 RCC.FDCANCLockSelection=RCC_FDCANCLKSOURCE_PLL RCC.FDCANFreq_Value=16000000 RCC.FamilyName=M -RCC.HCLKFreq_Value=64000000 +RCC.HCLKFreq_Value=16000000 RCC.HSE_VALUE=8000000 RCC.HSI48_VALUE=48000000 RCC.HSI_VALUE=16000000 -RCC.I2C1Freq_Value=64000000 -RCC.I2C2Freq_Value=64000000 -RCC.I2C3Freq_Value=64000000 -RCC.I2SFreq_Value=64000000 -RCC.IPParameters=ADC12Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANCLockSelection,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2SFreq_Value,LPTIM1Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQ,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value -RCC.LPTIM1Freq_Value=64000000 -RCC.LPUART1Freq_Value=64000000 +RCC.I2C1Freq_Value=16000000 +RCC.I2C2Freq_Value=16000000 +RCC.I2C3Freq_Value=16000000 +RCC.I2SFreq_Value=16000000 +RCC.IPParameters=ADC12Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANCLockSelection,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2SFreq_Value,LPTIM1Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQ,PLLQoutputFreq_Value,PLLR,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value +RCC.LPTIM1Freq_Value=16000000 +RCC.LPUART1Freq_Value=16000000 RCC.LSCOPinFreq_Value=32000 RCC.LSE_VALUE=32768 RCC.LSI_VALUE=32000 @@ -329,16 +178,17 @@ RCC.MCO1PinFreq_Value=16000000 RCC.PLLPoutputFreq_Value=64000000 RCC.PLLQ=RCC_PLLQ_DIV8 RCC.PLLQoutputFreq_Value=16000000 -RCC.PLLRCLKFreq_Value=64000000 -RCC.PWRFreq_Value=64000000 +RCC.PLLR=RCC_PLLR_DIV8 +RCC.PLLRCLKFreq_Value=16000000 +RCC.PWRFreq_Value=16000000 RCC.RNGFreq_Value=16000000 -RCC.SAI1Freq_Value=64000000 -RCC.SYSCLKFreq_VALUE=64000000 +RCC.SAI1Freq_Value=16000000 +RCC.SYSCLKFreq_VALUE=16000000 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK RCC.UART4Freq_Value=64000000 -RCC.USART1Freq_Value=64000000 -RCC.USART2Freq_Value=64000000 -RCC.USART3Freq_Value=64000000 +RCC.USART1Freq_Value=16000000 +RCC.USART2Freq_Value=16000000 +RCC.USART3Freq_Value=16000000 RCC.USBFreq_Value=16000000 RCC.VCOInputFreq_Value=16000000 RCC.VCOOutputFreq_Value=128000000 diff --git a/STM32Make.make b/STM32Make.make index a9af956..5ed0916 100644 --- a/STM32Make.make +++ b/STM32Make.make @@ -48,8 +48,6 @@ Core/Src/syscalls.c \ Core/Src/sysmem.c \ Core/Src/system_stm32g4xx.c \ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c \ -Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c \ -Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c \ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c \ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc.c \ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc_ex.c \ @@ -68,8 +66,7 @@ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c \ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c \ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c \ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c \ -Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c \ -Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c +Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c CPP_SOURCES = \ @@ -157,7 +154,8 @@ CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction- CXXFLAGS = $(MCU) $(CXX_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections -feliminate-unused-debug-types ifeq ($(DEBUG), 1) -CFLAGS += -g -gdwarf-2 +CFLAGS += -g -gdwarf -ggdb +CXXFLAGS += -g -gdwarf -ggdb endif # Add additional flags @@ -245,6 +243,12 @@ erase: $(BUILD_DIR)/$(TARGET).elf ####################################### clean: -rm -fR $(BUILD_DIR) + +####################################### +# custom makefile rules +####################################### + + ####################################### # dependencies diff --git a/stm32g441xx.svd b/stm32g441xx.svd new file mode 100644 index 0000000..b7c94dd --- /dev/null +++ b/stm32g441xx.svd @@ -0,0 +1,40278 @@ + + + + STM32G441xx + 1.9 + STM32G441xx + + CM4 + r0p1 + little + true + true + 4 + false + + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + CRC + Cyclic redundancy check calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data register bits + 0 + 32 + + + + + IDR + IDR + Independent data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + General-purpose 8-bit data register bits + 0 + 32 + + + + + CR + CR + Control register + 0x8 + 0x20 + 0x00000000 + + + REV_OUT + Reverse output data + 7 + 1 + read-write + + + REV_IN + Reverse input data + 5 + 2 + read-write + + + POLYSIZE + Polynomial size + 3 + 2 + read-write + + + RESET + RESET bit + 0 + 1 + write-only + + + + + INIT + INIT + Initial CRC value + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + CRC_INIT + Programmable initial CRC value + 0 + 32 + + + + + POL + POL + polynomial + 0x14 + 0x20 + read-write + 0x04C11DB7 + + + POL + Programmable polynomial + 0 + 32 + + + + + + + IWDG + WinWATCHDOG + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value (write only, read 0x0000) + 0 + 16 + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload value + 0 + 12 + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + WVU + Watchdog counter window value update + 2 + 1 + + + RVU + Watchdog counter reload value update + 1 + 1 + + + PVU + Watchdog prescaler value update + 0 + 1 + + + + + WINR + WINR + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window value + 0 + 12 + + + + + + + WWDG + System window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + WDGA + Activation bit + 7 + 1 + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + WDGTB + Timer base + 11 + 3 + + + EWI + Early wakeup interrupt + 9 + 1 + + + W + 7-bit window value + 0 + 7 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt flag + 0 + 1 + + + + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EV + I2C1_EV + 31 + + + I2C1_ER + I2C1_ER + 32 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + PE + Peripheral enable + 0 + 1 + + + TXIE + TX Interrupt enable + 1 + 1 + + + RXIE + RX Interrupt enable + 2 + 1 + + + ADDRIE + Address match interrupt enable (slave only) + 3 + 1 + + + NACKIE + Not acknowledge received interrupt enable + 4 + 1 + + + STOPIE + STOP detection Interrupt enable + 5 + 1 + + + TCIE + Transfer Complete interrupt enable + 6 + 1 + + + ERRIE + Error interrupts enable + 7 + 1 + + + DNF + Digital noise filter + 8 + 4 + + + ANFOFF + Analog noise filter OFF + 12 + 1 + + + TXDMAEN + DMA transmission requests enable + 14 + 1 + + + RXDMAEN + DMA reception requests enable + 15 + 1 + + + SBC + Slave byte control + 16 + 1 + + + NOSTRETCH + Clock stretching disable + 17 + 1 + + + WUPEN + Wakeup from STOP enable + 18 + 1 + + + GCEN + General call enable + 19 + 1 + + + SMBHEN + SMBus Host address enable + 20 + 1 + + + SMBDEN + SMBus Device Default address enable + 21 + 1 + + + ALERTEN + SMBUS alert enable + 22 + 1 + + + PECEN + PEC enable + 23 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECBYTE + Packet error checking byte + 26 + 1 + + + AUTOEND + Automatic end mode (master mode) + 25 + 1 + + + RELOAD + NBYTES reload mode + 24 + 1 + + + NBYTES + Number of bytes + 16 + 8 + + + NACK + NACK generation (slave mode) + 15 + 1 + + + STOP + Stop generation (master mode) + 14 + 1 + + + START + Start generation + 13 + 1 + + + HEAD10R + 10-bit address header only read direction (master receiver mode) + 12 + 1 + + + ADD10 + 10-bit addressing mode (master mode) + 11 + 1 + + + RD_WRN + Transfer direction (master mode) + 10 + 1 + + + SADD + Slave address bit (master mode) + 0 + 10 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + OA1 + Interface address + 0 + 10 + + + OA1MODE + Own Address 1 10-bit mode + 10 + 1 + + + OA1EN + Own Address 1 enable + 15 + 1 + + + + + OAR2 + OAR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address + 1 + 7 + + + OA2MSK + Own Address 2 masks + 8 + 3 + + + OA2EN + Own Address 2 enable + 15 + 1 + + + + + TIMINGR + TIMINGR + Timing register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master mode) + 0 + 8 + + + SCLH + SCL high period (master mode) + 8 + 8 + + + SDADEL + Data hold time + 16 + 4 + + + SCLDEL + Data setup time + 20 + 4 + + + PRESC + Timing prescaler + 28 + 4 + + + + + TIMEOUTR + TIMEOUTR + Status register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus timeout A + 0 + 12 + + + TIDLE + Idle clock timeout detection + 12 + 1 + + + TIMOUTEN + Clock timeout enable + 15 + 1 + + + TIMEOUTB + Bus timeout B + 16 + 12 + + + TEXTEN + Extended clock timeout enable + 31 + 1 + + + + + ISR + ISR + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDCODE + Address match code (Slave mode) + 17 + 7 + read-only + + + DIR + Transfer direction (Slave mode) + 16 + 1 + read-only + + + BUSY + Bus busy + 15 + 1 + read-only + + + ALERT + SMBus alert + 13 + 1 + read-only + + + TIMEOUT + Timeout or t_low detection flag + 12 + 1 + read-only + + + PECERR + PEC Error in reception + 11 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) + 10 + 1 + read-only + + + ARLO + Arbitration lost + 9 + 1 + read-only + + + BERR + Bus error + 8 + 1 + read-only + + + TCR + Transfer Complete Reload + 7 + 1 + read-only + + + TC + Transfer Complete (master mode) + 6 + 1 + read-only + + + STOPF + Stop detection flag + 5 + 1 + read-only + + + NACKF + Not acknowledge received flag + 4 + 1 + read-only + + + ADDR + Address matched (slave mode) + 3 + 1 + read-only + + + RXNE + Receive data register not empty (receivers) + 2 + 1 + read-only + + + TXIS + Transmit interrupt status (transmitters) + 1 + 1 + read-write + + + TXE + Transmit data register empty (transmitters) + 0 + 1 + read-write + + + + + ICR + ICR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTCF + Alert flag clear + 13 + 1 + + + TIMOUTCF + Timeout detection flag clear + 12 + 1 + + + PECCF + PEC Error flag clear + 11 + 1 + + + OVRCF + Overrun/Underrun flag clear + 10 + 1 + + + ARLOCF + Arbitration lost flag clear + 9 + 1 + + + BERRCF + Bus error flag clear + 8 + 1 + + + STOPCF + Stop detection flag clear + 5 + 1 + + + NACKCF + Not Acknowledge flag clear + 4 + 1 + + + ADDRCF + Address Matched flag clear + 3 + 1 + + + + + PECR + PECR + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking register + 0 + 8 + + + + + RXDR + RXDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + 8-bit receive data + 0 + 8 + + + + + TXDR + TXDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TXDATA + 8-bit transmit data + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + WWDG + Window Watchdog interrupt + 0 + + + I2C2_EV + I2C2_EV + 33 + + + I2C2_ER + I2C2_ER + 34 + + + + I2C3 + 0x40007800 + + I2C3_EV + I2C3_EV + 92 + + + I2C3_ER + I2C3_ER + 93 + + + + + FLASH + Flash + Flash + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + FLASH + 4 + + + + ACR + ACR + Access control register + 0x0 + 0x20 + read-write + 0x00000600 + + + LATENCY + Latency + 0 + 4 + + + PRFTEN + Prefetch enable + 8 + 1 + + + ICEN + Instruction cache enable + 9 + 1 + + + DCEN + Data cache enable + 10 + 1 + + + ICRST + Instruction cache reset + 11 + 1 + + + DCRST + Data cache reset + 12 + 1 + + + RUN_PD + Flash Power-down mode during Low-power run mode + 13 + 1 + + + SLEEP_PD + Flash Power-down mode during Low-power sleep mode + 14 + 1 + + + DBG_SWEN + Debug software enable + 18 + 1 + + + + + PDKEYR + PDKEYR + Power down key register + 0x4 + 0x20 + write-only + 0x00000000 + + + PDKEYR + RUN_PD in FLASH_ACR key + 0 + 32 + + + + + KEYR + KEYR + Flash key register + 0x8 + 0x20 + write-only + 0x00000000 + + + KEYR + KEYR + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Option byte key register + 0xC + 0x20 + write-only + 0x00000000 + + + OPTKEYR + Option byte key + 0 + 32 + + + + + SR + SR + Status register + 0x10 + 0x20 + 0x00000000 + + + EOP + End of operation + 0 + 1 + read-write + + + OPERR + Operation error + 1 + 1 + read-write + + + PROGERR + Programming error + 3 + 1 + read-write + + + WRPERR + Write protected error + 4 + 1 + read-write + + + PGAERR + Programming alignment error + 5 + 1 + read-write + + + SIZERR + Size error + 6 + 1 + read-write + + + PGSERR + Programming sequence error + 7 + 1 + read-write + + + MISERR + Fast programming data miss error + 8 + 1 + read-write + + + FASTERR + Fast programming error + 9 + 1 + read-write + + + RDERR + PCROP read error + 14 + 1 + read-write + + + OPTVERR + Option validity error + 15 + 1 + read-write + + + BSY + Busy + 16 + 1 + read-only + + + + + CR + CR + Flash control register + 0x14 + 0x20 + read-write + 0xC0000000 + + + PG + Programming + 0 + 1 + + + PER + Page erase + 1 + 1 + + + MER1 + Bank 1 Mass erase + 2 + 1 + + + PNB + Page number + 3 + 7 + + + STRT + Start + 16 + 1 + + + OPTSTRT + Options modification start + 17 + 1 + + + FSTPG + Fast programming + 18 + 1 + + + EOPIE + End of operation interrupt enable + 24 + 1 + + + ERRIE + Error interrupt enable + 25 + 1 + + + RDERRIE + PCROP read error interrupt enable + 26 + 1 + + + OBL_LAUNCH + Force the option byte loading + 27 + 1 + + + SEC_PROT1 + SEC_PROT1 + 28 + 1 + + + OPTLOCK + Options Lock + 30 + 1 + + + LOCK + FLASH_CR Lock + 31 + 1 + + + + + ECCR + ECCR + Flash ECC register + 0x18 + 0x20 + 0x00000000 + + + ADDR_ECC + ECC fail address + 0 + 19 + read-only + + + BK_ECC + BK_ECC + 21 + 1 + read-only + + + SYSF_ECC + SYSF_ECC + 22 + 1 + read-only + + + ECCIE + ECCIE + 24 + 1 + read-write + + + ECCC2 + ECC correction + 28 + 1 + read-write + + + ECCD2 + ECC2 detection + 29 + 1 + read-write + + + ECCC + ECC correction + 30 + 1 + read-write + + + ECCD + ECC detection + 31 + 1 + read-write + + + + + OPTR + OPTR + Flash option register + 0x20 + 0x20 + read-write + 0xF0000000 + + + RDP + Read protection level + 0 + 8 + + + BOR_LEV + BOR reset Level + 8 + 3 + + + nRST_STOP + nRST_STOP + 12 + 1 + + + nRST_STDBY + nRST_STDBY + 13 + 1 + + + nRST_SHDW + nRST_SHDW + 14 + 1 + + + IDWG_SW + Independent watchdog selection + 16 + 1 + + + IWDG_STOP + Independent watchdog counter freeze in Stop mode + 17 + 1 + + + IWDG_STDBY + Independent watchdog counter freeze in Standby mode + 18 + 1 + + + WWDG_SW + Window watchdog selection + 19 + 1 + + + nBOOT1 + Boot configuration + 23 + 1 + + + SRAM2_PE + SRAM2 parity check enable + 24 + 1 + + + SRAM2_RST + SRAM2 Erase when system reset + 25 + 1 + + + nSWBOOT0 + nSWBOOT0 + 26 + 1 + + + nBOOT0 + nBOOT0 + 27 + 1 + + + NRST_MODE + NRST_MODE + 28 + 2 + + + IRHEN + IRHEN + 30 + 1 + + + + + PCROP1SR + PCROP1SR + Flash Bank 1 PCROP Start address register + 0x24 + 0x20 + read-write + 0xFFFF0000 + + + PCROP1_STRT + Bank 1 PCROP area start offset + 0 + 15 + + + + + PCROP1ER + PCROP1ER + Flash Bank 1 PCROP End address register + 0x28 + 0x20 + read-write + 0x0FFF0000 + + + PCROP1_END + Bank 1 PCROP area end offset + 0 + 15 + + + PCROP_RDP + PCROP area preserved when RDP level decreased + 31 + 1 + + + + + WRP1AR + WRP1AR + Flash Bank 1 WRP area A address register + 0x2C + 0x20 + read-write + 0x00000000 + + + WRP1A_STRT + Bank 1 WRP first area start offset + 0 + 7 + + + WRP1A_END + Bank 1 WRP first area A end offset + 16 + 7 + + + + + WRP1BR + WRP1BR + Flash Bank 1 WRP area B address register + 0x30 + 0x20 + read-write + 0x00000000 + + + WRP1B_STRT + Bank 1 WRP second area B end offset + 0 + 7 + + + WRP1B_END + Bank 1 WRP second area B start offset + 16 + 7 + + + + + SEC1R + SEC1R + securable area bank1 register + 0x70 + 0x20 + read-write + 0xFF00FF00 + + + BOOT_LOCK + BOOT_LOCK + 16 + 1 + + + SEC_SIZE1 + SEC_SIZE1 + 0 + 8 + + + + + + + DBGMCU + Debug support + DBGMCU + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + MCU Device ID Code Register + 0x0 + 0x20 + read-only + 0x0 + + + DEV_ID + Device Identifier + 0 + 16 + + + REV_ID + Revision Identifier + 16 + 16 + + + + + CR + CR + Debug MCU Configuration Register + 0x4 + 0x20 + read-write + 0x0 + + + DBG_SLEEP + Debug Sleep Mode + 0 + 1 + + + DBG_STOP + Debug Stop Mode + 1 + 1 + + + DBG_STANDBY + Debug Standby Mode + 2 + 1 + + + TRACE_IOEN + Trace pin assignment control + 5 + 1 + + + TRACE_MODE + Trace pin assignment control + 6 + 2 + + + + + APB1L_FZ + APB1L_FZ + APB Low Freeze Register 1 + 0x8 + 0x20 + read-write + 0x0 + + + DBG_TIMER2_STOP + Debug Timer 2 stopped when Core is halted + 0 + 1 + + + DBG_TIM3_STOP + TIM3 counter stopped when core is halted + 1 + 1 + + + DBG_TIM4_STOP + TIM4 counter stopped when core is halted + 2 + 1 + + + DBG_TIM5_STOP + TIM5 counter stopped when core is halted + 3 + 1 + + + DBG_TIMER6_STOP + Debug Timer 6 stopped when Core is halted + 4 + 1 + + + DBG_TIM7_STOP + TIM7 counter stopped when core is halted + 5 + 1 + + + DBG_RTC_STOP + Debug RTC stopped when Core is halted + 10 + 1 + + + DBG_WWDG_STOP + Debug Window Wachdog stopped when Core is halted + 11 + 1 + + + DBG_IWDG_STOP + Debug Independent Wachdog stopped when Core is halted + 12 + 1 + + + DBG_I2C1_STOP + I2C1 SMBUS timeout mode stopped when core is halted + 21 + 1 + + + DBG_I2C2_STOP + I2C2 SMBUS timeout mode stopped when core is halted + 22 + 1 + + + DBG_I2C3_STOP + I2C3 SMBUS timeout mode stopped when core is halted + 30 + 1 + + + DBG_LPTIMER_STOP + LPTIM1 counter stopped when core is halted + 31 + 1 + + + + + APB1H_FZ + APB1H_FZ + APB Low Freeze Register 2 + 0xC + 0x20 + read-write + 0x0 + + + DBG_I2C4_STOP + DBG_I2C4_STOP + 1 + 1 + + + + + APB2_FZ + APB2_FZ + APB High Freeze Register + 0x10 + 0x20 + read-write + 0x0 + + + DBG_TIM1_STOP + TIM1 counter stopped when core is halted + 11 + 1 + + + DBG_TIM8_STOP + TIM8 counter stopped when core is halted + 13 + 1 + + + DBG_TIM15_STOP + TIM15 counter stopped when core is halted + 16 + 1 + + + DBG_TIM16_STOP + TIM16 counter stopped when core is halted + 17 + 1 + + + DBG_TIM17_STOP + TIM17 counter stopped when core is halted + 18 + 1 + + + DBG_TIM20_STOP + TIM20counter stopped when core is halted + 20 + 1 + + + DBG_HRTIM0_STOP + DBG_HRTIM0_STOP + 26 + 1 + + + DBG_HRTIM1_STOP + DBG_HRTIM0_STOP + 27 + 1 + + + DBG_HRTIM2_STOP + DBG_HRTIM0_STOP + 28 + 1 + + + DBG_HRTIM3_STOP + DBG_HRTIM0_STOP + 29 + 1 + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x0 + 0x400 + registers + + + RCC + RCC global interrupt + 5 + + + + RCC_CR + RCC_CR + Clock control register + 0x00 + 0x20 + 0x00000063 + 0xFFFFFFFF + + + HSION + HSI16 clock enable +Set and cleared by software. +Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown mode. +Set by hardware to force the HSI16 oscillator ON when STOPWUCK=1 or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator. +This bit is set by hardware if the HSI16 is used directly or indirectly as system clock. + 8 + 1 + read-write + + + B_0x0 + HSI16 oscillator OFF + 0x0 + + + B_0x1 + HSI16 oscillator ON + 0x1 + + + + + HSIKERON + HSI16 always enable for peripheral kernels. +Set and cleared by software to force HSI16 ON even in Stop modes. The HSI16 can only feed USARTs and I<sup>2</sup>Cs peripherals configured with HSI16 as kernel clock. Keeping the HSI16 ON in Stop mode allows to avoid slowing down the communication speed because of the HSI16 startup time. This bit has no effect on HSION value. + 9 + 1 + read-write + + + B_0x0 + No effect on HSI16 oscillator. + 0x0 + + + B_0x1 + HSI16 oscillator is forced ON even in Stop mode. + 0x1 + + + + + HSIRDY + HSI16 clock ready flag +Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION. +Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI16 clock cycles. + 10 + 1 + read-only + + + B_0x0 + HSI16 oscillator not ready + 0x0 + + + B_0x1 + HSI16 oscillator ready + 0x1 + + + + + HSEON + HSE clock enable +Set and cleared by software. +Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. + 16 + 1 + read-write + + + B_0x0 + HSE oscillator OFF + 0x0 + + + B_0x1 + HSE oscillator ON + 0x1 + + + + + HSERDY + HSE clock ready flag +Set by hardware to indicate that the HSE oscillator is stable. +Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles. + 17 + 1 + read-only + + + B_0x0 + HSE oscillator not ready + 0x0 + + + B_0x1 + HSE oscillator ready + 0x1 + + + + + HSEBYP + HSE crystal oscillator bypass +Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. + 18 + 1 + read-write + + + B_0x0 + HSE crystal oscillator not bypassed + 0x0 + + + B_0x1 + HSE crystal oscillator bypassed with external clock + 0x1 + + + + + CSSON + Clock security system enable +Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. + 19 + 1 + read-write + + + B_0x0 + Clock security system OFF (clock detector OFF) + 0x0 + + + B_0x1 + Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not). + 0x1 + + + + + PLLON + Main PLL enable +Set and cleared by software to enable the main PLL. +Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL clock is used as the system clock. + 24 + 1 + read-write + + + B_0x0 + PLL OFF + 0x0 + + + B_0x1 + PLL ON + 0x1 + + + + + PLLRDY + Main PLL clock ready flag +Set by hardware to indicate that the main PLL is locked. + 25 + 1 + read-only + + + B_0x0 + PLL unlocked + 0x0 + + + B_0x1 + PLL locked + 0x1 + + + + + + + RCC_ICSCR + RCC_ICSCR + Internal clock sources calibration register + 0x04 + 0x20 + 0x40000000 + 0xFFFFFFFF + + + HSICAL + HSI16 clock calibration +These bits are initialized at startup with the factory-programmed HSI16 calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value. + 16 + 8 + read-only + + + HSITRIM + HSI16 clock trimming +These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI16. +The default value is 16, which, when added to the HSICAL value, should trim the HSI16 to 16 MHz � 1 %. + 24 + 7 + read-write + + + + + RCC_CFGR + RCC_CFGR + Clock configuration register + 0x08 + 0x20 + 0x00000005 + 0xFFFFFFFF + + + SW + System clock switch +Set and cleared by software to select system clock source (SYSCLK). +Configured by hardware to force HSI16 oscillator selection when exiting stop and standby modes or in case of failure of the HSE oscillator. + 0 + 2 + read-write + + + B_0x0 + Reserved, must be kept at reset value + 0x0 + + + B_0x1 + HSI16 selected as system clock + 0x1 + + + B_0x2 + HSE selected as system clock + 0x2 + + + B_0x3 + PLL selected as system clock + 0x3 + + + + + SWS + System clock switch status +Set and cleared by hardware to indicate which clock source is used as system clock. + 2 + 2 + read-only + + + B_0x0 + Reserved, must be kept at reset value + 0x0 + + + B_0x1 + HSI16 oscillator used as system clock + 0x1 + + + B_0x2 + HSE used as system clock + 0x2 + + + B_0x3 + PLL used as system clock + 0x3 + + + + + HPRE + AHB prescaler +Set and cleared by software to control the division factor of the AHB clock. +Note: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details please refer to Section 6.1.5: Dynamic voltage scaling management). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account. +0xxx: SYSCLK not divided + 4 + 4 + read-write + + + B_0x8 + SYSCLK divided by 2 + 0x8 + + + B_0x9 + SYSCLK divided by 4 + 0x9 + + + B_0xA + SYSCLK divided by 8 + 0xA + + + B_0xB + SYSCLK divided by 16 + 0xB + + + B_0xC + SYSCLK divided by 64 + 0xC + + + B_0xD + SYSCLK divided by 128 + 0xD + + + B_0xE + SYSCLK divided by 256 + 0xE + + + B_0xF + SYSCLK divided by 512 + 0xF + + + + + PPRE1 + APB1 prescaler +Set and cleared by software to control the division factor of the APB1 clock (PCLK1). +0xx: HCLK not divided + 8 + 3 + read-write + + + B_0x4 + HCLK divided by 2 + 0x4 + + + B_0x5 + HCLK divided by 4 + 0x5 + + + B_0x6 + HCLK divided by 8 + 0x6 + + + B_0x7 + HCLK divided by 16 + 0x7 + + + + + PPRE2 + APB2 prescaler +Set and cleared by software to control the division factor of the APB2 clock (PCLK2). +0xx: HCLK not divided + 11 + 3 + read-write + + + B_0x4 + HCLK divided by 2 + 0x4 + + + B_0x5 + HCLK divided by 4 + 0x5 + + + B_0x6 + HCLK divided by 8 + 0x6 + + + B_0x7 + HCLK divided by 16 + 0x7 + + + + + MCOSEL + Microcontroller clock output +Set and cleared by software. +Others: Reserved +Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. + 24 + 4 + read-write + + + B_0x0 + MCO output disabled, no clock on MCO + 0x0 + + + B_0x1 + SYSCLK system clock selected + 0x1 + + + B_0x2 + Reserved, must be kept at reset value + 0x2 + + + B_0x3 + HSI16 clock selected + 0x3 + + + B_0x4 + HSE clock selected + 0x4 + + + B_0x5 + Main PLL clock selected + 0x5 + + + B_0x6 + LSI clock selected + 0x6 + + + B_0x7 + LSE clock selected + 0x7 + + + B_0x8 + Internal HSI48 clock selected + 0x8 + + + + + MCOPRE + Microcontroller clock output prescaler +These bits are set and cleared by software. +It is highly recommended to change this prescaler before MCO output is enabled. +Others: not allowed + 28 + 3 + read-write + + + B_0x0 + MCO is divided by 1 + 0x0 + + + B_0x1 + MCO is divided by 2 + 0x1 + + + B_0x2 + MCO is divided by 4 + 0x2 + + + B_0x3 + MCO is divided by 8 + 0x3 + + + B_0x4 + MCO is divided by 16 + 0x4 + + + + + + + RCC_PLLCFGR + RCC_PLLCFGR + PLL configuration register + 0x0C + 0x20 + 0x00001000 + 0xFFFFFFFF + + + PLLSRC + Main PLL entry clock source +Set and cleared by software to select PLL clock source. These bits can be written only when PLL is disabled. +In order to save power, when no PLL is used, the value of PLLSRC should be 00. + 0 + 2 + read-write + + + B_0x0 + No clock sent to PLL + 0x0 + + + B_0x1 + No clock sent to PLL + 0x1 + + + B_0x2 + HSI16 clock selected as PLL clock entry + 0x2 + + + B_0x3 + HSE clock selected as PLL clock entry + 0x3 + + + + + PLLM + Division factor for the main PLL input clock +Set and cleared by software to divide the PLL input clock before the VCO. These bits can be written only when all PLLs are disabled. +VCO input frequency = PLL input clock frequency / PLLM with 1 <= PLLM <= 16 +... +Note: The software has to set these bits correctly to ensure that the VCO input frequency is within the range defined in the device datasheet. + 4 + 4 + read-write + + + B_0x0 + PLLM = 1 + 0x0 + + + B_0x1 + PLLM = 2 + 0x1 + + + B_0x2 + PLLM = 3 + 0x2 + + + B_0x3 + PLLM = 4 + 0x3 + + + B_0x4 + PLLM = 5 + 0x4 + + + B_0x5 + PLLM = 6 + 0x5 + + + B_0x6 + PLLM = 7 + 0x6 + + + B_0x7 + PLLM = 8 + 0x7 + + + B_0x8 + PLLSYSM = 9 + 0x8 + + + B_0xF + PLLSYSM= 16 + 0xF + + + + + PLLN + Main PLL multiplication factor for VCO +Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled. +VCO output frequency = VCO input frequency x PLLN with 8 =< PLLN =< 127 +... +... +Note: The software has to set correctly these bits to assure that the VCO output frequency is within the range defined in the device datasheet. + 8 + 7 + read-write + + + B_0x0 + PLLN = 0 wrong configuration + 0x0 + + + B_0x1 + PLLN = 1 wrong configuration + 0x1 + + + B_0x7 + PLLN = 7 wrong configuration + 0x7 + + + B_0x8 + PLLN = 8 + 0x8 + + + B_0x9 + PLLN = 9 + 0x9 + + + B_0x7F + PLLN = 127 + 0x7F + + + + + PLLPEN + Main PLL PLL “P” clock output enable +Set and reset by software to enable the PLL “P” clock output of the PLL. +In order to save power, when the PLL “P” clock output of the PLL is not used, the value of PLLPEN should be 0. + 16 + 1 + read-write + + + B_0x0 + PLL “P” clock output disable + 0x0 + + + B_0x1 + PLL “P” clock output enable + 0x1 + + + + + PLLP + Main PLL division factor for PLL “P” clock. +Set and cleared by software to control the frequency of the main PLL output clock PLL “P” clock. These bits can be written only if PLL is disabled. +When the PLLPDIV[4:0] is set to “00000”PLL “P” output clock frequency = VCO frequency / PLLP with PLLP =7, or 17 +Note: The software has to set these bits correctly not to exceed 170 MHz on this domain. + 17 + 1 + read-write + + + B_0x0 + PLLP = 7 + 0x0 + + + B_0x1 + PLLP = 17 + 0x1 + + + + + PLLQEN + Main PLL “Q” clock output enable +Set and reset by software to enable the PLL “Q” clock output of the PLL. +In order to save power, when the PLL “Q” clock output of the PLL is not used, the value of PLLQEN should be 0. + 20 + 1 + read-write + + + B_0x0 + PLL “Q” clock output disable + 0x0 + + + B_0x1 + PLL “Q” clock output enable + 0x1 + + + + + PLLQ + Main PLL division factor for PLL “Q” clock. +Set and cleared by software to control the frequency of the main PLL output clock PLL “Q” clock. This output can be selected for USB, RNG, SAI (48 MHz clock). These bits can be written only if PLL is disabled. +PLL “Q” output clock frequency = VCO frequency / PLLQ with PLLQ = 2, 4, 6, or 8 +Note: The software has to set these bits correctly not to exceed 170 MHz on this domain. + 21 + 2 + read-write + + + B_0x0 + PLLQ = 2 + 0x0 + + + B_0x1 + PLLQ = 4 + 0x1 + + + B_0x2 + PLLQ = 6 + 0x2 + + + B_0x3 + PLLQ = 8 + 0x3 + + + + + PLLREN + PLL “R” clock output enable +Set and reset by software to enable the PLL “R” clock output of the PLL (used as system clock). +This bit cannot be written when PLL “R” clock output of the PLL is used as System Clock. +In order to save power, when the PLL “R” clock output of the PLL is not used, the value of PLLREN should be 0. + 24 + 1 + read-write + + + B_0x0 + PLL “R” clock output disable + 0x0 + + + B_0x1 + PLL “R” clock output enable + 0x1 + + + + + PLLR + Main PLL division factor for PLL “R” clock (system clock) +Set and cleared by software to control the frequency of the main PLL output clock PLLCLK. This output can be selected as system clock. These bits can be written only if PLL is disabled. +PLL “R” output clock frequency = VCO frequency / PLLR with PLLR = 2, 4, 6, or 8 +Note: The software has to set these bits correctly not to exceed 170 MHz on this domain. + 25 + 2 + read-write + + + B_0x0 + PLLR = 2 + 0x0 + + + B_0x1 + PLLR = 4 + 0x1 + + + B_0x2 + PLLR = 6 + 0x2 + + + B_0x3 + PLLR = 8 + 0x3 + + + + + PLLPDIV + Main PLLP division factor +Set and cleared by software to control the PLL “P” frequency. PLL “P” output clock frequency = VCO frequency / PLLPDIV. +.... + 27 + 5 + read-write + + + B_0x0 + PLL “P” clock is controlled by the bit PLLP + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + B_0x2 + PLL “P” clock = VCO / 2 + 0x2 + + + B_0x1F + PLL “P” clock = VCO / 31 + 0x1F + + + + + + + RCC_CIER + RCC_CIER + Clock interrupt enable register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYIE + LSI ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization. + 0 + 1 + read-write + + + B_0x0 + LSI ready interrupt disabled + 0x0 + + + B_0x1 + LSI ready interrupt enabled + 0x1 + + + + + LSERDYIE + LSE ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization. + 1 + 1 + read-write + + + B_0x0 + LSE ready interrupt disabled + 0x0 + + + B_0x1 + LSE ready interrupt enabled + 0x1 + + + + + HSIRDYIE + HSI16 ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization. + 3 + 1 + read-write + + + B_0x0 + HSI16 ready interrupt disabled + 0x0 + + + B_0x1 + HSI16 ready interrupt enabled + 0x1 + + + + + HSERDYIE + HSE ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization. + 4 + 1 + read-write + + + B_0x0 + HSE ready interrupt disabled + 0x0 + + + B_0x1 + HSE ready interrupt enabled + 0x1 + + + + + PLLRDYIE + PLL ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by PLL lock. + 5 + 1 + read-write + + + B_0x0 + PLL lock interrupt disabled + 0x0 + + + B_0x1 + PLL lock interrupt enabled + 0x1 + + + + + LSECSSIE + LSE clock security system interrupt enable +Set and cleared by software to enable/disable interrupt caused by the clock security system on LSE. + 9 + 1 + read-write + + + B_0x0 + Clock security interrupt caused by LSE clock failure disabled + 0x0 + + + B_0x1 + Clock security interrupt caused by LSE clock failure enabled + 0x1 + + + + + HSI48RDYIE + HSI48 ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the internal HSI48 oscillator. + 10 + 1 + read-write + + + B_0x0 + HSI48 ready interrupt disabled + 0x0 + + + B_0x1 + HSI48 ready interrupt enabled + 0x1 + + + + + + + RCC_CIFR + RCC_CIFR + Clock interrupt flag register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYF + LSI ready interrupt flag +Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. +Cleared by software setting the LSIRDYC bit. + 0 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the LSI oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the LSI oscillator + 0x1 + + + + + LSERDYF + LSE ready interrupt flag +Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. +Cleared by software setting the LSERDYC bit. + 1 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the LSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the LSE oscillator + 0x1 + + + + + HSIRDYF + HSI16 ready interrupt flag +Set by hardware when the HSI16 clock becomes stable and HSIRDYDIE is set in a response to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. +Cleared by software setting the HSIRDYC bit. + 3 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSI16 oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI16 oscillator + 0x1 + + + + + HSERDYF + HSE ready interrupt flag +Set by hardware when the HSE clock becomes stable and HSERDYDIE is set. +Cleared by software setting the HSERDYC bit. + 4 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSE oscillator + 0x1 + + + + + PLLRDYF + PLL ready interrupt flag +Set by hardware when the PLL locks and PLLRDYDIE is set. +Cleared by software setting the PLLRDYC bit. + 5 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by PLL lock + 0x0 + + + B_0x1 + Clock ready interrupt caused by PLL lock + 0x1 + + + + + CSSF + Clock security system interrupt flag +Set by hardware when a failure is detected in the HSE oscillator. +Cleared by software setting the CSSC bit. + 8 + 1 + read-only + + + B_0x0 + No clock security interrupt caused by HSE clock failure + 0x0 + + + B_0x1 + Clock security interrupt caused by HSE clock failure + 0x1 + + + + + LSECSSF + LSE Clock security system interrupt flag +Set by hardware when a failure is detected in the LSE oscillator. +Cleared by software setting the LSECSSC bit. + 9 + 1 + read-only + + + B_0x0 + No clock security interrupt caused by LSE clock failure + 0x0 + + + B_0x1 + Clock security interrupt caused by LSE clock failure + 0x1 + + + + + HSI48RDYF + HSI48 ready interrupt flag +Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a response to setting the HSI48ON (refer to Clock recovery RC register (RCC_CRRCR)). +Cleared by software setting the HSI48RDYC bit. + 10 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSI48 oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI48 oscillator + 0x1 + + + + + + + RCC_CICR + RCC_CICR + Clock interrupt clear register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYC + LSI ready interrupt clear +This bit is set by software to clear the LSIRDYF flag. + 0 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + LSIRDYF cleared + 0x1 + + + + + LSERDYC + LSE ready interrupt clear +This bit is set by software to clear the LSERDYF flag. + 1 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + LSERDYF cleared + 0x1 + + + + + HSIRDYC + HSI16 ready interrupt clear +This bit is set software to clear the HSIRDYF flag. + 3 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear HSIRDYF flag + 0x1 + + + + + HSERDYC + HSE ready interrupt clear +This bit is set by software to clear the HSERDYF flag. + 4 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear HSERDYF flag + 0x1 + + + + + PLLRDYC + PLL ready interrupt clear +This bit is set by software to clear the PLLRDYF flag. + 5 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear PLLRDYF flag + 0x1 + + + + + CSSC + Clock security system interrupt clear +This bit is set by software to clear the CSSF flag. + 8 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear CSSF flag + 0x1 + + + + + LSECSSC + LSE Clock security system interrupt clear +This bit is set by software to clear the LSECSSF flag. + 9 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear LSECSSF flag + 0x1 + + + + + HSI48RDYC + HSI48 oscillator ready interrupt clear +This bit is set by software to clear the HSI48RDYF flag. + 10 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear the HSI48RDYC flag + 0x1 + + + + + + + RCC_AHB1RSTR + RCC_AHB1RSTR + AHB1 peripheral reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMA1RST + DMA1 reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DMA1 + 0x1 + + + + + DMA2RST + DMA2 reset +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DMA2 + 0x1 + + + + + DMAMUX1RST + Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DMAMUX1 + 0x1 + + + + + CORDICRST + Set and cleared by software + 3 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset CORDIC + 0x1 + + + + + FMACRST + Set and cleared by software + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset FMAC + 0x1 + + + + + FLASHRST + Flash memory interface reset +Set and cleared by software. This bit can be activated only when the Flash memory is in power down mode. + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset Flash memory interface + 0x1 + + + + + CRCRST + CRC reset +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset CRC + 0x1 + + + + + + + RCC_AHB2RSTR + RCC_AHB2RSTR + AHB2 peripheral reset register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GPIOARST + IO port A reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port A + 0x1 + + + + + GPIOBRST + IO port B reset +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port B + 0x1 + + + + + GPIOCRST + IO port C reset +Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port C + 0x1 + + + + + GPIODRST + IO port D reset +Set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port D + 0x1 + + + + + GPIOERST + IO port E reset +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port E + 0x1 + + + + + GPIOFRST + IO port F reset +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port F + 0x1 + + + + + GPIOGRST + IO port G reset +Set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset IO port G + 0x1 + + + + + ADC12RST + ADC12 reset +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset ADC12 interface + 0x1 + + + + + ADC345RST + ADC345 reset +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset ADC345 + 0x1 + + + + + DAC1RST + DAC1 reset +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DAC1 + 0x1 + + + + + DAC2RST + DAC2 reset +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DAC2 + 0x1 + + + + + DAC3RST + DAC3 reset +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DAC3 + 0x1 + + + + + DAC4RST + DAC4 reset +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DAC4 + 0x1 + + + + + AESRST + AESRST reset +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset AES + 0x1 + + + + + RNGRST + RNG reset +Set and cleared by software. + 26 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset RNG + 0x1 + + + + + + + RCC_AHB3RSTR + RCC_AHB3RSTR + AHB3 peripheral reset register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FMCRST + Flexible static memory controller reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset FSMC + 0x1 + + + + + QSPIRST + QUADSPI reset +Set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset QUADSPI + 0x1 + + + + + + + RCC_APB1RSTR1 + RCC_APB1RSTR1 + APB1 peripheral reset register 1 + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM2RST + TIM2 timer reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM2 + 0x1 + + + + + TIM3RST + TIM3 timer reset +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM3 + 0x1 + + + + + TIM4RST + TIM3 timer reset +Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM3 + 0x1 + + + + + TIM5RST + TIM5 timer reset +Set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM5 + 0x1 + + + + + TIM6RST + TIM6 timer reset +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM7 + 0x1 + + + + + TIM7RST + TIM7 timer reset +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM7 + 0x1 + + + + + CRSRST + CRS reset +Set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset CRS + 0x1 + + + + + SPI2RST + SPI2 reset +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI2 + 0x1 + + + + + SPI3RST + SPI3 reset +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI3 + 0x1 + + + + + USART2RST + USART2 reset +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART2 + 0x1 + + + + + USART3RST + USART3 reset +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART3 + 0x1 + + + + + UART4RST + UART4 reset +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset UART4 + 0x1 + + + + + UART5RST + UART5 reset +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset UART5 + 0x1 + + + + + I2C1RST + I2C1 reset +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C1 + 0x1 + + + + + I2C2RST + I2C2 reset +Set and cleared by software. + 22 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C2 + 0x1 + + + + + USBRST + USB device reset +Set and reset by software. + 23 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USB device + 0x1 + + + + + FDCANRST + FDCAN reset +Set and reset by software. + 25 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the FDCAN + 0x1 + + + + + PWRRST + Power interface reset +Set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset PWR + 0x1 + + + + + I2C3RST + I2C3 reset +Set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C3 interface + 0x1 + + + + + LPTIM1RST + Low Power Timer 1 reset +Set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPTIM1 + 0x1 + + + + + + + RCC_APB1RSTR2 + RCC_APB1RSTR2 + APB1 peripheral reset register 2 + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LPUART1RST + Low-power UART 1 reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPUART1 + 0x1 + + + + + I2C4RST + I2C4 reset + Set and cleared by software + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C4 + 0x1 + + + + + UCPD1RST + UCPD1 reset +Set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset UCPD1 + 0x1 + + + + + + + RCC_APB2RSTR + RCC_APB2RSTR + APB2 peripheral reset register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SYSCFGRST + SYSCFG + COMP + OPAMP + VREFBUF reset + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SYSCFG + COMP + OPAMP + VREFBUF + 0x1 + + + + + TIM1RST + TIM1 timer reset +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM1 timer + 0x1 + + + + + SPI1RST + SPI1 reset +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI1 + 0x1 + + + + + TIM8RST + TIM8 timer reset +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM8 timer + 0x1 + + + + + USART1RST + USART1 reset +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART1 + 0x1 + + + + + SPI4RST + SPI4 reset +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI4 + 0x1 + + + + + TIM15RST + TIM15 timer reset +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM15 timer + 0x1 + + + + + TIM16RST + TIM16 timer reset +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM16 timer + 0x1 + + + + + TIM17RST + TIM17 timer reset +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM17 timer + 0x1 + + + + + TIM20RST + TIM20 reset +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM20 + 0x1 + + + + + SAI1RST + Serial audio interface 1 (SAI1) reset +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SAI1 + 0x1 + + + + + HRTIM1RST + HRTIM1 reset +Set and cleared by software. + 26 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset HRTIM1 + 0x1 + + + + + + + RCC_AHB1ENR + RCC_AHB1ENR + AHB1 peripheral clock enable register + 0x48 + 0x20 + 0x00000100 + 0xFFFFFFFF + + + DMA1EN + DMA1 clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + DMA1 clock disable + 0x0 + + + B_0x1 + DMA1 clock enable + 0x1 + + + + + DMA2EN + DMA2 clock enable +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + DMA2 clock disable + 0x0 + + + B_0x1 + DMA2 clock enable + 0x1 + + + + + DMAMUX1EN + DMAMUX1 clock enable +Set and reset by software. + 2 + 1 + read-write + + + B_0x0 + DMAMUX1 clock disabled + 0x0 + + + B_0x1 + DMAMUX1 clock enabled + 0x1 + + + + + CORDICEN + CORDIC clock enable +Set and reset by software. + 3 + 1 + read-write + + + B_0x0 + CORDIC clock disabled + 0x0 + + + B_0x1 + CORDIC clock enabled + 0x1 + + + + + FMACEN + FMAC enable +Set and reset by software. + 4 + 1 + read-write + + + B_0x0 + FMAC clock disabled + 0x0 + + + B_0x1 + FMAC clock enabled + 0x1 + + + + + FLASHEN + Flash memory interface clock enable +Set and cleared by software. This bit can be disabled only when the Flash is in power down mode. + 8 + 1 + read-write + + + B_0x0 + Flash memory interface clock disable + 0x0 + + + B_0x1 + Flash memory interface clock enable + 0x1 + + + + + CRCEN + CRC clock enable +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + CRC clock disable + 0x0 + + + B_0x1 + CRC clock enable + 0x1 + + + + + + + RCC_AHB2ENR + RCC_AHB2ENR + AHB2 peripheral clock enable register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GPIOAEN + IO port A clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + IO port A clock disabled + 0x0 + + + B_0x1 + IO port A clock enabled + 0x1 + + + + + GPIOBEN + IO port B clock enable +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + IO port B clock disabled + 0x0 + + + B_0x1 + IO port B clock enabled + 0x1 + + + + + GPIOCEN + IO port C clock enable +Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + IO port C clock disabled + 0x0 + + + B_0x1 + IO port C clock enabled + 0x1 + + + + + GPIODEN + IO port D clock enable +Set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + IO port D clock disabled + 0x0 + + + B_0x1 + IO port D clock enabled + 0x1 + + + + + GPIOEEN + IO port E clock enable +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + IO port E clock disabled + 0x0 + + + B_0x1 + IO port E clock enabled + 0x1 + + + + + GPIOFEN + IO port F clock enable +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + IO port F clock disabled + 0x0 + + + B_0x1 + IO port F clock enabled + 0x1 + + + + + GPIOGEN + IO port G clock enable +Set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + IO port G clock disabled + 0x0 + + + B_0x1 + IO port G clock enabled + 0x1 + + + + + ADC12EN + ADC12 clock enable +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + ADC12 clock disabled + 0x0 + + + B_0x1 + ADC12 clock enabled + 0x1 + + + + + ADC345EN + ADC345 clock enable + Set and cleared by software + 14 + 1 + read-write + + + B_0x0 + ADC345 clock disabled + 0x0 + + + B_0x1 + ADC345 clock enabled + 0x1 + + + + + DAC1EN + DAC1 clock enable +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + DAC1 clock disabled + 0x0 + + + B_0x1 + DAC1 clock enabled + 0x1 + + + + + DAC2EN + DAC2 clock enable +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + DAC2 clock disabled + 0x0 + + + B_0x1 + DAC2 clock enabled + 0x1 + + + + + DAC3EN + DAC3 clock enable +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + DAC3 clock disabled + 0x0 + + + B_0x1 + DAC3 clock enabled + 0x1 + + + + + DAC4EN + DAC4 clock enable +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + DAC4 clock disabled + 0x0 + + + B_0x1 + DAC4 clock enabled + 0x1 + + + + + AESEN + AES clock enable +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + AES clock disabled + 0x0 + + + B_0x1 + AES clock enabled + 0x1 + + + + + RNGEN + RNG enable +Set and cleared by software. + 26 + 1 + read-write + + + B_0x0 + RNG disabled + 0x0 + + + B_0x1 + RNG enabled + 0x1 + + + + + + + RCC_AHB3ENR + RCC_AHB3ENR + AHB3 peripheral clock enable register + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FMCEN + Flexible static memory controller clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + FSMC clock disable + 0x0 + + + B_0x1 + FSMC clock enable + 0x1 + + + + + QSPIEN + QUADSPI memory interface clock enable +Set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + QUADSPI clock disable + 0x0 + + + B_0x1 + QUADSPI clock enable + 0x1 + + + + + + + RCC_APB1ENR1 + RCC_APB1ENR1 + APB1 peripheral clock enable register 1 + 0x58 + 0x20 + 0x00000400 + 0xFFFFFFFF + + + TIM2EN + TIM2 timer clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + TIM2 clock disabled + 0x0 + + + B_0x1 + TIM2 clock enabled + 0x1 + + + + + TIM3EN + TIM3 timer clock enable +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + TIM3 clock disabled + 0x0 + + + B_0x1 + TIM3 clock enabled + 0x1 + + + + + TIM4EN + TIM4 timer clock enable +Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + TIM4 clock disabled + 0x0 + + + B_0x1 + TIM4 clock enabled + 0x1 + + + + + TIM5EN + TIM5 timer clock enable +Set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + TIM5 clock disabled + 0x0 + + + B_0x1 + TIM5 clock enabled + 0x1 + + + + + TIM6EN + TIM6 timer clock enable +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + TIM6 clock disabled + 0x0 + + + B_0x1 + TIM6 clock enabled + 0x1 + + + + + TIM7EN + TIM7 timer clock enable +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + TIM7 clock disabled + 0x0 + + + B_0x1 + TIM7 clock enabled + 0x1 + + + + + CRSEN + CRS Recovery System clock enable +Set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + CRS clock disabled + 0x0 + + + B_0x1 + CRS clock enabled + 0x1 + + + + + RTCAPBEN + RTC APB clock enable +Set and cleared by software + 10 + 1 + read-write + + + B_0x0 + RTC APB clock disabled + 0x0 + + + B_0x1 + RTC APB clock enabled + 0x1 + + + + + WWDGEN + Window watchdog clock enable +Set by software to enable the window watchdog clock. Reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset. + 11 + 1 + read-write + + + B_0x0 + Window watchdog clock disabled + 0x0 + + + B_0x1 + Window watchdog clock enabled + 0x1 + + + + + SPI2EN + SPI2 clock enable +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + SPI2 clock disabled + 0x0 + + + B_0x1 + SPI2 clock enabled + 0x1 + + + + + SPI3EN + SPI3 clock enable +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + SPI3 clock disabled + 0x0 + + + B_0x1 + SPI3 clock enabled + 0x1 + + + + + USART2EN + USART2 clock enable +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + USART2 clock disabled + 0x0 + + + B_0x1 + USART2 clock enabled + 0x1 + + + + + USART3EN + USART3 clock enable +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + USART3 clock disabled + 0x0 + + + B_0x1 + USART3 clock enabled + 0x1 + + + + + UART4EN + UART4 clock enable +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + UART4 clock disabled + 0x0 + + + B_0x1 + UART4 clock enabled + 0x1 + + + + + UART5EN + UART5 clock enable +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + UART5 clock disabled + 0x0 + + + B_0x1 + UART5 clock enabled + 0x1 + + + + + I2C1EN + I2C1 clock enable +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + I2C1 clock disabled + 0x0 + + + B_0x1 + I2C1 clock enabled + 0x1 + + + + + I2C2EN + I2C2 clock enable +Set and cleared by software. + 22 + 1 + read-write + + + B_0x0 + I2C2 clock disabled + 0x0 + + + B_0x1 + I2C2 clock enabled + 0x1 + + + + + USBEN + USB device clock enable +Set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + USB device clock disabled + 0x0 + + + B_0x1 + USB device clock enabled + 0x1 + + + + + FDCANEN + FDCAN clock enable +Set and cleared by software. + 25 + 1 + read-write + + + B_0x0 + FDCAN clock disabled + 0x0 + + + B_0x1 + FDCAN clock enabled + 0x1 + + + + + PWREN + Power interface clock enable +Set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Power interface clock disabled + 0x0 + + + B_0x1 + Power interface clock enabled + 0x1 + + + + + I2C3EN + I2C3 clock enable +Set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + I2C3 clock disabled + 0x0 + + + B_0x1 + I2C3 clock enabled + 0x1 + + + + + LPTIM1EN + Low power timer 1 clock enable +Set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + LPTIM1 clock disabled + 0x0 + + + B_0x1 + LPTIM1 clock enabled + 0x1 + + + + + + + RCC_APB1ENR2 + RCC_APB1ENR2 + APB1 peripheral clock enable register 2 + 0x5C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LPUART1EN + Low power UART 1 clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LPUART1 clock disable + 0x0 + + + B_0x1 + LPUART1 clock enable + 0x1 + + + + + I2C4EN + I2C4 clock enable +Set and cleared by software + 1 + 1 + read-write + + + B_0x0 + I2C4 clock disabled + 0x0 + + + B_0x1 + I2C4 clock enabled + 0x1 + + + + + UCPD1EN + UCPD1 clock enable +Set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + UCPD1 clock disable + 0x0 + + + B_0x1 + UCPD1 clock enable + 0x1 + + + + + + + RCC_APB2ENR + RCC_APB2ENR + APB2 peripheral clock enable register + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SYSCFGEN + SYSCFG + COMP + VREFBUF + OPAMP clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + SYSCFG + COMP + VREFBUF + OPAMP clock disabled + 0x0 + + + B_0x1 + SYSCFG + COMP + VREFBUF + OPAMP clock enabled + 0x1 + + + + + TIM1EN + TIM1 timer clock enable +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + TIM1 timer clock disabled + 0x0 + + + B_0x1 + TIM1P timer clock enabled + 0x1 + + + + + SPI1EN + SPI1 clock enable +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + SPI1 clock disabled + 0x0 + + + B_0x1 + SPI1 clock enabled + 0x1 + + + + + TIM8EN + TIM8 timer clock enable +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + TIM8 timer clock disabled + 0x0 + + + B_0x1 + TIM8 timer clock enabled + 0x1 + + + + + USART1EN + USART1clock enable +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + USART1clock disabled + 0x0 + + + B_0x1 + USART1clock enabled + 0x1 + + + + + SPI4EN + SPI4 clock enable +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + SPI4 clock disabled + 0x0 + + + B_0x1 + SPI4 clock enabled + 0x1 + + + + + TIM15EN + TIM15 timer clock enable +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + TIM15 timer clock disabled + 0x0 + + + B_0x1 + TIM15 timer clock enabled + 0x1 + + + + + TIM16EN + TIM16 timer clock enable +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + TIM16 timer clock disabled + 0x0 + + + B_0x1 + TIM16 timer clock enabled + 0x1 + + + + + TIM17EN + TIM17 timer clock enable +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + TIM17 timer clock disabled + 0x0 + + + B_0x1 + TIM17 timer clock enabled + 0x1 + + + + + TIM20EN + TIM20 timer clock enable +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + TIM20 clock disabled + 0x0 + + + B_0x1 + TIM20 clock enabled + 0x1 + + + + + SAI1EN + SAI1 clock enable +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + SAI1 clock disabled + 0x0 + + + B_0x1 + SAI1 clock enabled + 0x1 + + + + + HRTIM1EN + HRTIM1 clock enable +Set and cleared by software. + 26 + 1 + read-write + + + B_0x0 + HRTIM1 clock disabled + 0x0 + + + B_0x1 + HRTIM1 clock enable + 0x1 + + + + + + + RCC_AHB1SMENR + RCC_AHB1SMENR + AHB1 peripheral clocks enable in Sleep and Stop modes register + 0x68 + 0x20 + 0x0000130F + 0xFFFFFFFF + + + DMA1SMEN + DMA1 clocks enable during Sleep and Stop modes +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + DMA1 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + DMA1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + DMA2SMEN + DMA2 clocks enable during Sleep and Stop modes +Set and cleared by software during Sleep mode. + 1 + 1 + read-write + + + B_0x0 + DMA2 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + DMA2 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + DMAMUX1SMEN + DMAMUX1 clock enable during Sleep and Stop modes. +Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + DMAMUX1 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + DMAMUX1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + CORDICSMEN + CORDICSM clock enable. +Set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + CORDICSM clocks disabled. + 0x0 + + + B_0x1 + CORDICSM clocks enabled. + 0x1 + + + + + FMACSMEN + FMACSM clock enable. +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + FMACSM clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + FMACSM clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + FLASHSMEN + Flash memory interface clocks enable during Sleep and Stop modes +Set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + Flash memory interface clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + Flash memory interface clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SRAM1SMEN + SRAM1 interface clocks enable during Sleep and Stop modes +Set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + SRAM1 interface clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SRAM1 interface clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + CRCSMEN + CRC clocks enable during Sleep and Stop modes +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + CRC clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + CRC clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + + + RCC_AHB2SMENR + RCC_AHB2SMENR + AHB2 peripheral clocks enable in Sleep and Stop modes register + 0x6C + 0x20 + 0x050F667F + 0xFFFFFFFF + + + GPIOASMEN + IO port A clocks enable during Sleep and Stop modes +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + IO port A clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port A clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + GPIOBSMEN + IO port B clocks enable during Sleep and Stop modes +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + IO port B clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port B clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + GPIOCSMEN + IO port C clocks enable during Sleep and Stop modes +Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + IO port C clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port C clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + GPIODSMEN + IO port D clocks enable during Sleep and Stop modes +Set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + IO port D clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port D clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + GPIOESMEN + IO port E clocks enable during Sleep and Stop modes +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + IO port E clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port E clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + GPIOFSMEN + IO port F clocks enable during Sleep and Stop modes +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + IO port F clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port F clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + GPIOGSMEN + IO port G clocks enable during Sleep and Stop modes +Set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + IO port G clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + IO port G clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + CCMSRAMSMEN + CCM SRAM interface clocks enable during Sleep and Stop modes +Set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + CCM SRAM interface clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + CCM SRAM interface clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SRAM2SMEN + SRAM2 interface clocks enable during Sleep and Stop modes +Set and cleared by software. + 10 + 1 + read-write + + + B_0x0 + SRAM2 interface clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SRAM2 interface clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + ADC12SMEN + ADC12 clocks enable during Sleep and Stop modes +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + ADC12 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + ADC12 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + ADC345SMEN + ADC345 clock enable +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + ADC345 clock disabled + 0x0 + + + B_0x1 + ADC345 clock enabled + 0x1 + + + + + DAC1SMEN + DAC1 clock enable +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + DAC1 clock disabled + 0x0 + + + B_0x1 + DAC1 clock enabled during sleep and stop modes + 0x1 + + + + + DAC2SMEN + DAC2 clock enable +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + DAC2 clock disabled + 0x0 + + + B_0x1 + DAC2 clock enabled during sleep and stop modes + 0x1 + + + + + DAC3SMEN + DAC3 clock enable +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + DAC3 clock disabled + 0x0 + + + B_0x1 + DAC3 clock enabled during sleep and stop modes + 0x1 + + + + + DAC4SMEN + DAC4 clock enable +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + DAC4 clock disabled + 0x0 + + + B_0x1 + DAC4 clock enabled during sleep and stop modes + 0x1 + + + + + AESSMEN + AESM clocks enable +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + AESM clocks disabled + 0x0 + + + B_0x1 + AESM clocks enabled + 0x1 + + + + + RNGEN + RNG enable +Set and cleared by software. + 26 + 1 + read-write + + + B_0x0 + RNG disabled + 0x0 + + + B_0x1 + RNG enabled + 0x1 + + + + + + + RCC_AHB3SMENR + RCC_AHB3SMENR + AHB3 peripheral clocks enable in Sleep and Stop modes register + 0x70 + 0x20 + 0x00000101 + 0xFFFFFFFF + + + FMCSMEN + Flexible static memory controller clocks enable during Sleep and Stop modes +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + FSMC clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + FSMC clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + QSPISMEN + QUADSPI memory interface clock enable during Sleep and Stop modes +Set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + QUADSPI clock disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + QUADSPI clock enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + + + RCC_APB1SMENR1 + RCC_APB1SMENR1 + APB1 peripheral clocks enable in Sleep and Stop modes register 1 + 0x78 + 0x20 + 0xD2FECD3F + 0xFFFFFFFF + + + TIM2SMEN + TIM2 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + TIM2 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM2 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM3SMEN + TIM3 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + TIM3 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM3 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM4SMEN + TIM4 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + TIM4 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM4 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM5SMEN + TIM5 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + TIM5 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM5 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM6SMEN + TIM6 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + TIM6 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM6 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM7SMEN + TIM7 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + TIM7 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM7 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + CRSSMEN + CRS timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + CRS clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + CRS clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + RTCAPBSMEN + RTC APB clock enable during Sleep and Stop modes +Set and cleared by software + 10 + 1 + read-write + + + B_0x0 + RTC APB clock disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + RTC APB clock enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + WWDGSMEN + Window watchdog clocks enable during Sleep and Stop modes +Set and cleared by software. This bit is forced to ‘1’ by hardware when the hardware WWDG option is activated. + 11 + 1 + read-write + + + B_0x0 + Window watchdog clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + Window watchdog clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SPI2SMEN + SPI2 clocks enable during Sleep and Stop modes +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + SPI2 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SPI2 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SPI3SMEN + SPI3 clocks enable during Sleep and Stop modes +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + SPI3 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SPI3 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + USART2SMEN + USART2 clocks enable during Sleep and Stop modes +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + USART2 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + USART2 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + USART3SMEN + USART3 clocks enable during Sleep and Stop modes +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + USART3 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + USART3 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + UART4SMEN + UART4 clocks enable during Sleep and Stop modes +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + UART4 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + UART4 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + UART5SMEN + UART5 clocks enable during Sleep and Stop modes +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + UART5 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + UART5 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + I2C1SMEN + I2C1 clocks enable during Sleep and Stop modes +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + I2C1 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + I2C1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + I2C2SMEN + I2C2 clocks enable during Sleep and Stop modes +Set and cleared by software. + 22 + 1 + read-write + + + B_0x0 + I2C2 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + I2C2 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + USBSMEN + USB device clocks enable during Sleep and Stop modes +Set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + USB device clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + USB device clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + FDCANSMEN + FDCAN clocks enable during Sleep and Stop modes +Set and cleared by software. + 25 + 1 + read-write + + + B_0x0 + FDCAN clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + FDCAN clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + PWRSMEN + Power interface clocks enable during Sleep and Stop modes +Set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Power interface clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + Power interface clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + I2C3SMEN + I2C3 clocks enable during Sleep and Stop modes +Set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + I2C3 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + I2C3 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + LPTIM1SMEN + Low power timer 1 clocks enable during Sleep and Stop modes +Set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + LPTIM1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + LPTIM1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + + + RCC_APB1SMENR2 + RCC_APB1SMENR2 + APB1 peripheral clocks enable in Sleep and Stop modes register 2 + 0x7C + 0x20 + 0x00000103 + 0xFFFFFFFF + + + LPUART1SMEN + Low power UART 1 clocks enable during Sleep and Stop modes +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LPUART1 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + LPUART1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + I2C4SMEN + I2C4 clocks enable during Sleep and Stop modes + Set and cleared by software + 1 + 1 + read-write + + + B_0x0 + I2C4 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + I2C4 clock enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + UCPD1SMEN + UCPD1 clocks enable during Sleep and Stop modes +Set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + UCPD1 clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + UCPD1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + + + RCC_APB2SMENR + RCC_APB2SMENR + APB2 peripheral clocks enable in Sleep and Stop modes register + 0x80 + 0x20 + 0x0437F801 + 0xFFFFFFFF + + + SYSCFGSMEN + SYSCFG + COMP + VREFBUF + OPAMP clocks enable during Sleep and Stop modes +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + SYSCFG + COMP + VREFBUF + OPAMP clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SYSCFG + COMP + VREFBUF + OPAMP clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM1SMEN + TIM1 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + TIM1 timer clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM1P timer clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SPI1SMEN + SPI1 clocks enable during Sleep and Stop modes +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + SPI1 clocks disabled by the clock gating during<sup>(1)</sup> Sleep and Stop modes + 0x0 + + + B_0x1 + SPI1 clocks enabled by the clock gating during<sup>(1)</sup> Sleep and Stop modes + 0x1 + + + + + TIM8SMEN + TIM8 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + TIM8 timer clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM8 timer clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + USART1SMEN + USART1clocks enable during Sleep and Stop modes +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + USART1clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + USART1clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SPI4SMEN + SPI4 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + SPI4 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SPI4 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop mode + 0x1 + + + + + TIM15SMEN + TIM15 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + TIM15 timer clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM15 timer clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop mode + 0x1 + + + + + TIM16SMEN + TIM16 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + TIM16 timer clocks disabled by the clock gating during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM16 timer clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM17SMEN + TIM17 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + TIM17 timer clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM17 timer clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + TIM20SMEN + TIM20 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + TIM20 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + TIM20 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + SAI1SMEN + SAI1 clocks enable during Sleep and Stop modes +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + SAI1 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + SAI1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + HRTIM1SMEN + HRTIM1 timer clocks enable during Sleep and Stop modes +Set and cleared by software. + 26 + 1 + read-write + + + B_0x0 + HRTIM1 clocks disabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x0 + + + B_0x1 + HRTIM1 clocks enabled by the clock gating<sup>(1)</sup> during Sleep and Stop modes + 0x1 + + + + + + + RCC_CCIPR + RCC_CCIPR + Peripherals independent clock configuration register + 0x88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USART1SEL + USART1 clock source selection +This bit is set and cleared by software to select the USART1 clock source. + 0 + 2 + read-write + + + B_0x0 + PCLK selected as USART1 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as USART1 clock + 0x1 + + + B_0x2 + HSI16 clock selected as USART1 clock + 0x2 + + + B_0x3 + LSE clock selected as USART1 clock + 0x3 + + + + + USART2SEL + USART2 clock source selection +This bit is set and cleared by software to select the USART2 clock source. + 2 + 2 + read-write + + + B_0x0 + PCLK selected as USART2 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as USART2 clock + 0x1 + + + B_0x2 + HSI16 clock selected as USART2 clock + 0x2 + + + B_0x3 + LSE clock selected as USART2 clock + 0x3 + + + + + USART3SEL + USART3 clock source selection +This bit is set and cleared by software to select the USART3 clock source. + 4 + 2 + read-write + + + B_0x0 + PCLK selected as USART3 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as USART3 clock + 0x1 + + + B_0x2 + HSI16 clock selected as USART3 clock + 0x2 + + + B_0x3 + LSE clock selected as USART3 clock + 0x3 + + + + + UART4SEL + UART4 clock source selection +This bit is set and cleared by software to select the UART4 clock source. + 6 + 2 + read-write + + + B_0x0 + PCLK selected as UART4 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as UART4 clock + 0x1 + + + B_0x2 + HSI16 clock selected as UART4 clock + 0x2 + + + B_0x3 + LSE clock selected as UART4 clock + 0x3 + + + + + UART5SEL + UART5 clock source selection +These bits are set and cleared by software to select the UART5 clock source. + 8 + 2 + read-write + + + B_0x0 + PCLK selected as UART5 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as UART5 clock + 0x1 + + + B_0x2 + HSI16 clock selected as UART5 clock + 0x2 + + + B_0x3 + LSE clock selected as UART5 clock + 0x3 + + + + + LPUART1SEL + LPUART1 clock source selection +These bits are set and cleared by software to select the LPUART1 clock source. + 10 + 2 + read-write + + + B_0x0 + PCLK selected as LPUART1 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as LPUART1 clock + 0x1 + + + B_0x2 + HSI16 clock selected as LPUART1 clock + 0x2 + + + B_0x3 + LSE clock selected as LPUART1 clock + 0x3 + + + + + I2C1SEL + I2C1 clock source selection +These bits are set and cleared by software to select the I2C1 clock source. + 12 + 2 + read-write + + + B_0x0 + PCLK selected as I2C1 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as I2C1 clock + 0x1 + + + B_0x2 + HSI16 clock selected as I2C1 clock + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + I2C2SEL + I2C2 clock source selection +These bits are set and cleared by software to select the I2C2 clock source. + 14 + 2 + read-write + + + B_0x0 + PCLK selected as I2C2 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as I2C2 clock + 0x1 + + + B_0x2 + HSI16 clock selected as I2C2 clock + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + I2C3SEL + I2C3 clock source selection +These bits are set and cleared by software to select the I2C3 clock source. + 16 + 2 + read-write + + + B_0x0 + PCLK selected as I2C3 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as I2C3 clock + 0x1 + + + B_0x2 + HSI16 clock selected as I2C3 clock + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + LPTIM1SEL + Low power timer 1 clock source selection +These bits are set and cleared by software to select the LPTIM1 clock source. + 18 + 2 + read-write + + + B_0x0 + PCLK selected as LPTIM1 clock + 0x0 + + + B_0x1 + LSI clock selected as LPTIM1 clock + 0x1 + + + B_0x2 + HSI16 clock selected as LPTIM1 clock + 0x2 + + + B_0x3 + LSE clock selected as LPTIM1 clock + 0x3 + + + + + SAI1SEL + clock source selection +These bits are set and cleared by software to select the SAI clock source. + 20 + 2 + read-write + + + B_0x0 + System clock selected as SAI clock + 0x0 + + + B_0x1 + PLL “Q” clock selected as SAI clock + 0x1 + + + B_0x2 + Clock provided on I2S_CKIN pin selected as SAI clock + 0x2 + + + B_0x3 + HSI16 clock selected as SAI clock + 0x3 + + + + + I2S23SEL + clock source selection +These bits are set and cleared by software to select the I2S23 clock source. + 22 + 2 + read-write + + + B_0x0 + System clock selected as I2S23 clock + 0x0 + + + B_0x1 + PLL “Q” clock selected as I2S23 clock + 0x1 + + + B_0x2 + Clock provided on I2S_CKIN pin is selected as I2S23 clock + 0x2 + + + B_0x3 + HSI16 clock selected as I2S23 clock. + 0x3 + + + + + FDCANSEL + None + 24 + 2 + read-write + + + CLK48SEL + 48 MHz clock source selection +These bits are set and cleared by software to select the 48 MHz clock source used by USB device FS and RNG. + 26 + 2 + read-write + + + B_0x0 + HSI48 clock selected as 48 MHz clock + 0x0 + + + B_0x1 + Reserved + 0x1 + + + B_0x2 + PLL “Q” clock (PLL48M1CLK) selected as 48 MHz clock + 0x2 + + + B_0x3 + Reserved, must be kept at reset value + 0x3 + + + + + ADC12SEL + ADC1/2 clock source selection +These bits are set and cleared by software to select the clock source used by the ADC interface. + 28 + 2 + read-write + + + B_0x0 + No clock selected + 0x0 + + + B_0x1 + PLL “P” clock selected as ADC1/2 clock + 0x1 + + + B_0x2 + System clock selected as ADC1/2 clock + 0x2 + + + B_0x3 + Reserved + 0x3 + + + + + ADC345SEL + ADC3/4/5 clock source selection +These bits are set and cleared by software to select the clock source used by the ADC345 interface. + 30 + 2 + read-write + + + B_0x0 + No clock selected + 0x0 + + + B_0x1 + PLL “P” clock selected as ADC345 clock + 0x1 + + + B_0x2 + System clock selected as ADC3/4/5 clock + 0x2 + + + B_0x3 + Reserved. + 0x3 + + + + + + + RCC_BDCR + RCC_BDCR + RTC domain control register + 0x90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSEON + LSE oscillator enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LSE oscillator OFF + 0x0 + + + B_0x1 + LSE oscillator ON + 0x1 + + + + + LSERDY + LSE oscillator ready +Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. + 1 + 1 + read-only + + + B_0x0 + LSE oscillator not ready + 0x0 + + + B_0x1 + LSE oscillator ready + 0x1 + + + + + LSEBYP + LSE oscillator bypass +Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0). + 2 + 1 + read-write + + + B_0x0 + LSE oscillator not bypassed + 0x0 + + + B_0x1 + LSE oscillator bypassed + 0x1 + + + + + LSEDRV + LSE oscillator drive capability +Set by software to modulate the LSE oscillator’s drive capability. +The oscillator is in Xtal mode when it is not in bypass mode. + 3 + 2 + read-write + + + B_0x0 + ‘Xtal mode’ lower driving capability + 0x0 + + + B_0x1 + ‘Xtal mode’ medium low driving capability + 0x1 + + + B_0x2 + ‘Xtal mode’ medium high driving capability + 0x2 + + + B_0x3 + ‘Xtal mode’ higher driving capability + 0x3 + + + + + LSECSSON + CSS on LSE enable +Set by software to enable the Clock Security System on LSE (32 kHz oscillator). +LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. +Once enabled this bit cannot be disabled, except after a LSE failure detection (LSECSSD +=1). In that case the software MUST disable the LSECSSON bit. + 5 + 1 + read-write + + + B_0x0 + CSS on LSE (32 kHz external oscillator) OFF + 0x0 + + + B_0x1 + CSS on LSE (32 kHz external oscillator) ON + 0x1 + + + + + LSECSSD + CSS on LSE failure Detection +Set by hardware to indicate when a failure has been detected by the Clock Security System +on the external 32 kHz oscillator (LSE). + 6 + 1 + read-only + + + B_0x0 + No failure detected on LSE (32 kHz oscillator) + 0x0 + + + B_0x1 + Failure detected on LSE (32 kHz oscillator) + 0x1 + + + + + RTCSEL + RTC clock source selection +Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them. + 8 + 2 + read-write + + + B_0x0 + No clock + 0x0 + + + B_0x1 + LSE oscillator clock used as RTC clock + 0x1 + + + B_0x2 + LSI oscillator clock used as RTC clock + 0x2 + + + B_0x3 + HSE oscillator clock divided by 32 used as RTC clock + 0x3 + + + + + RTCEN + RTC clock enable +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + RTC clock disabled + 0x0 + + + B_0x1 + RTC clock enabled + 0x1 + + + + + BDRST + RTC domain software reset +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + Reset not activated + 0x0 + + + B_0x1 + Reset the entire RTC domain + 0x1 + + + + + LSCOEN + Low speed clock output enable +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + Low speed clock output (LSCO) disable + 0x0 + + + B_0x1 + Low speed clock output (LSCO) enable + 0x1 + + + + + LSCOSEL + Low speed clock output selection +Set and cleared by software. + 25 + 1 + read-write + + + B_0x0 + LSI clock selected + 0x0 + + + B_0x1 + LSE clock selected + 0x1 + + + + + + + RCC_CSR + RCC_CSR + Control/status register + 0x94 + 0x20 + 0x0C000000 + 0xFFFFFFFF + + + LSION + LSI oscillator enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LSI oscillator OFF + 0x0 + + + B_0x1 + LSI oscillator ON + 0x1 + + + + + LSIRDY + LSI oscillator ready +Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC. + 1 + 1 + read-only + + + B_0x0 + LSI oscillator not ready + 0x0 + + + B_0x1 + LSI oscillator ready + 0x1 + + + + + RMVF + Remove reset flag +Set by software to clear the reset flags. + 23 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear the reset flags + 0x1 + + + + + OBLRSTF + Option byte loader reset flag +Set by hardware when a reset from the Option Byte loading occurs. +Cleared by writing to the RMVF bit. + 25 + 1 + read-only + + + B_0x0 + No reset from Option Byte loading occurred + 0x0 + + + B_0x1 + Reset from Option Byte loading occurred + 0x1 + + + + + PINRSTF + Pin reset flag +Set by hardware when a reset from the NRST pin occurs. +Cleared by writing to the RMVF bit. + 26 + 1 + read-only + + + B_0x0 + No reset from NRST pin occurred + 0x0 + + + B_0x1 + Reset from NRST pin occurred + 0x1 + + + + + BORRSTF + BOR flag +Set by hardware when a BOR occurs. +Cleared by writing to the RMVF bit. + 27 + 1 + read-only + + + B_0x0 + No BOR occurred + 0x0 + + + B_0x1 + BOR occurred + 0x1 + + + + + SFTRSTF + Software reset flag +Set by hardware when a software reset occurs. +Cleared by writing to the RMVF bit. + 28 + 1 + read-only + + + B_0x0 + No software reset occurred + 0x0 + + + B_0x1 + Software reset occurred + 0x1 + + + + + IWDGRSTF + Independent window watchdog reset flag +Set by hardware when an independent watchdog reset domain occurs. +Cleared by writing to the RMVF bit. + 29 + 1 + read-only + + + B_0x0 + No independent watchdog reset occurred + 0x0 + + + B_0x1 + Independent watchdog reset occurred + 0x1 + + + + + WWDGRSTF + Window watchdog reset flag +Set by hardware when a window watchdog reset occurs. +Cleared by writing to the RMVF bit. + 30 + 1 + read-only + + + B_0x0 + No window watchdog reset occurred + 0x0 + + + B_0x1 + Window watchdog reset occurred + 0x1 + + + + + LPWRRSTF + Low-power reset flag +Set by hardware when a reset occurs due to illegal Stop, Standby or Shutdown mode entry. +Cleared by writing to the RMVF bit. + 31 + 1 + read-only + + + B_0x0 + No illegal mode reset occurred + 0x0 + + + B_0x1 + Illegal mode reset occurred + 0x1 + + + + + + + RCC_CRRCR + RCC_CRRCR + Clock recovery RC register + 0x98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HSI48ON + HSI48 clock enable +Set and cleared by software. +Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes. + 0 + 1 + read-write + + + B_0x0 + HSI48 oscillator OFF + 0x0 + + + B_0x1 + HSI48 oscillator ON + 0x1 + + + + + HSI48RDY + HSI48 clock ready flag +Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON. + 1 + 1 + read-only + + + B_0x0 + HSI48 oscillator not ready + 0x0 + + + B_0x1 + HSI48 oscillator ready + 0x1 + + + + + HSI48CAL + HSI48 clock calibration +These bits are initialized at startup with the factory-programmed HSI48 calibration trim value. +They are ready only. + 7 + 9 + read-only + + + + + RCC_CCIPR2 + RCC_CCIPR2 + Peripherals independent clock configuration register + 0x9C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + I2C4SEL + I2C4 clock source selection +These bits are set and cleared by software to select the I2C4 clock source. + 0 + 2 + read-write + + + B_0x0 + PCLK selected as I2C4 clock + 0x0 + + + B_0x1 + System clock (SYSCLK) selected as I2C4 clock + 0x1 + + + B_0x2 + HSI16 clock selected as I2C4 clock + 0x2 + + + B_0x3 + reserved + 0x3 + + + + + QSPISEL + QUADSPI clock source selection +Set and reset by software. + 20 + 2 + read-write + + + B_0x0 + system clock selected as QUADSPI kernel clock + 0x0 + + + B_0x1 + HSI16 clock selected as QUADSPI kernel clock + 0x1 + + + B_0x2 + PLL “Q” clock selected as QUADSPI kernel clock + 0x2 + + + B_0x3 + reserved + 0x3 + + + + + + + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + + PWR_CR1 + PWR_CR1 + Power control register 1 + 0x00 + 0x20 + 0x00000200 + 0xFFFFFFFF + + + LPMS + Low-power mode selection +These bits select the low-power mode entered when CPU enters the deepsleep mode. +1xx: Shutdown mode +Note: In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3. + 0 + 3 + read-write + + + B_0x0 + Stop 0 mode + 0x0 + + + B_0x1 + Stop 1 mode + 0x1 + + + B_0x2 + Reserved + 0x2 + + + B_0x3 + Standby mode + 0x3 + + + + + FPD_STOP + FPD_STOP + 3 + 1 + read-write + + + DBP + Disable backup domain write protection +In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. + 8 + 1 + read-write + + + B_0x0 + Access to RTC and Backup registers disabled + 0x0 + + + B_0x1 + Access to RTC and Backup registers enabled + 0x1 + + + + + VOS + Voltage scaling range selection + 9 + 2 + read-write + + + B_0x0 + Cannot be written (forbidden by hardware) + 0x0 + + + B_0x1 + Range 1 + 0x1 + + + B_0x2 + Range 2 + 0x2 + + + B_0x3 + Cannot be written (forbidden by hardware) + 0x3 + + + + + LPR + Low-power run +When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR). + 14 + 1 + read-write + + + + + PWR_CR2 + PWR_CR2 + Power control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PVDE + Programmable voltage detector enable +Note: This bit is write-protected when the PVDL bit is set in the SYSCFG_CFGR2 register. The protection can be reset only by a system reset. + 0 + 1 + read-write + + + B_0x0 + Programmable voltage detector disable. + 0x0 + + + B_0x1 + Programmable voltage detector enable. + 0x1 + + + + + PVDLS + Programmable voltage detector level selection. +These bits select the PVD falling threshold: +Note: These bits are write-protected when the PVDL bit is set in the SYSCFG_CFGR2 register. The protection can be reset only by a system reset. + 1 + 3 + read-write + + + B_0x0 + V<sub>PVD0</sub> PVD threshold 0 + 0x0 + + + B_0x1 + V<sub>PVD1</sub> PVD threshold 1 + 0x1 + + + B_0x2 + V<sub>PVD2</sub> PVD threshold 2 + 0x2 + + + B_0x3 + V<sub>PVD3</sub> PVD threshold 3 + 0x3 + + + B_0x4 + V<sub>PVD4</sub> PVD threshold 4 + 0x4 + + + B_0x5 + V<sub>PVD5</sub> PVD threshold 5 + 0x5 + + + B_0x6 + V<sub>PVD6</sub> PVD threshold 6 + 0x6 + + + B_0x7 + External input analog voltage PVD_IN (compared internally to V<sub>REFINT</sub>) + 0x7 + + + + + PVMEN1 + Peripheral voltage monitoring 3 enable: V<sub>DDA</sub> vs. ADC/COMP min voltage 1.62V + 6 + 1 + read-write + + + B_0x0 + PVM1 (V<sub>DDA</sub> monitoring vs. 1.62V threshold) disable. + 0x0 + + + B_0x1 + PVM1 (V<sub>DDA</sub> monitoring vs. 1.62V threshold) enable. + 0x1 + + + + + PVMEN2 + Peripheral voltage monitoring 4 enable: V<sub>DDA</sub> vs. DAC 1MSPS /DAC 15MSPS min voltage. + 7 + 1 + read-write + + + B_0x0 + PVM2 (V<sub>DDA</sub> monitoring vs. 1.8 V threshold) disable. + 0x0 + + + B_0x1 + PVM2 (V<sub>DDA</sub> monitoring vs. 1.8 V threshold) enable. + 0x1 + + + + + + + PWR_CR3 + PWR_CR3 + Power control register 3 + 0x08 + 0x20 + 0x00008000 + 0xFFFFFFFF + + + EWUP1 + Enable Wakeup pin WKUP1 +When this bit is set, the external wakeup pin WKUP1 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit in the PWR_CR4 register. + 0 + 1 + read-write + + + EWUP2 + Enable Wakeup pin WKUP2 +When this bit is set, the external wakeup pin WKUP2 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit in the PWR_CR4 register. + 1 + 1 + read-write + + + EWUP3 + Enable Wakeup pin WKUP3 +When this bit is set, the external wakeup pin WKUP3 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit in the PWR_CR4 register. + 2 + 1 + read-write + + + EWUP4 + Enable Wakeup pin WKUP4 +When this bit is set, the external wakeup pin WKUP4 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register. + 3 + 1 + read-write + + + EWUP5 + Enable Wakeup pin WKUP5 +When this bit is set, the external wakeup pin WKUP5 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP5 bit in the PWR_CR4 register. + 4 + 1 + read-write + + + RRS + SRAM2 retention in Standby mode + 8 + 1 + read-write + + + B_0x0 + SRAM2 is powered off in Standby mode (SRAM2 content is lost). + 0x0 + + + B_0x1 + SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 content is kept). + 0x1 + + + + + APC + Apply pull-up and pull-down configuration +When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx +and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and +PWR_PDCRx registers are not applied to the I/Os. + 10 + 1 + read-write + + + UCPD1_STDBY + UCPD1_STDBY USB Type-C and Power Delivery standby mode. + 13 + 1 + read-write + + + B_0x0 + Write ‘0’ immediately after standby exit when using UCPD1, (and before writing any UCPD1 registers). + 0x0 + + + B_0x1 + Write ‘1’ just before entering standby when using UCPD1. + 0x1 + + + + + UCPD1_DBDIS + USB Type-C and Power Delivery Dead Battery disable. +After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have +a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either +to stop this pull-down or to hand over control to the UCPD1 (which should therefore be +initialized before doing the disable). + 14 + 1 + read-write + + + B_0x0 + Enable USB Type-C dead battery pull-down behavior on UCPD1_CC1 and UCPD1_CC2 pins. + 0x0 + + + B_0x1 + Disable USB Type-C dead battery pull-down behavior on UCPD1_CC1 and UCPD1_CC2 pins. + 0x1 + + + + + EIWUL + Enable internal wakeup line + 15 + 1 + read-write + + + B_0x0 + Internal wakeup line disable. + 0x0 + + + B_0x1 + Internal wakeup line enable. + 0x1 + + + + + + + PWR_CR4 + PWR_CR4 + Power control register 4 + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WP1 + Wakeup pin WKUP1 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP1 + 0 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP2 + Wakeup pin WKUP2 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP2 + 1 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP3 + Wakeup pin WKUP3 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP3 + 2 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP4 + Wakeup pin WKUP4 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP4 + 3 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP5 + Wakeup pin WKUP5 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP5 + 4 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + VBE + V<sub>BAT</sub> battery charging enable + 8 + 1 + read-write + + + B_0x0 + V<sub>BAT</sub> battery charging disable + 0x0 + + + B_0x1 + V<sub>BAT</sub> battery charging enable + 0x1 + + + + + VBRS + V<sub>BAT</sub> battery charging resistor selection + 9 + 1 + read-write + + + B_0x0 + Charge V<sub>BAT</sub> through a 5 kOhms resistor + 0x0 + + + B_0x1 + Charge V<sub>BAT</sub> through a 1.5 kOhms resistor + 0x1 + + + + + + + PWR_SR1 + PWR_SR1 + Power status register 1 + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WUF1 + Wakeup flag 1 +This bit is set when a wakeup event is detected on wakeup pin, WKUP1. It is cleared by writing ‘1’ in the CWUF1 bit of the PWR_SCR register. + 0 + 1 + read-only + + + WUF2 + Wakeup flag 2 +This bit is set when a wakeup event is detected on wakeup pin, WKUP2. It is cleared by writing ‘1’ in the CWUF2 bit of the PWR_SCR register. + 1 + 1 + read-only + + + WUF3 + Wakeup flag 3 +This bit is set when a wakeup event is detected on wakeup pin, WKUP3. It is cleared by writing ‘1’ in the CWUF3 bit of the PWR_SCR register. + 2 + 1 + read-only + + + WUF4 + Wakeup flag 4 +This bit is set when a wakeup event is detected on wakeup pin,WKUP4. It is cleared by writing ‘1’ in the CWUF4 bit of the PWR_SCR register. + 3 + 1 + read-only + + + WUF5 + Wakeup flag 5 +This bit is set when a wakeup event is detected on wakeup pin, WKUP5. It is cleared by writing ‘1’ in the CWUF5 bit of the PWR_SCR register. + 4 + 1 + read-only + + + SBF + Standby flag +This bit is set by hardware when the device enters the Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. + 8 + 1 + read-only + + + B_0x0 + The device did not enter the Standby mode + 0x0 + + + B_0x1 + The device entered the Standby mode + 0x1 + + + + + WUFI + Wakeup flag internal +This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared. + 15 + 1 + read-only + + + + + PWR_SR2 + PWR_SR2 + Power status register 2 + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + REGLPS + Low-power regulator started +This bit provides the information whether the low-power regulator is ready after a power-on +reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wakeup from Standby mode time may be increased. + 8 + 1 + read-only + + + B_0x0 + The low-power regulator is not ready + 0x0 + + + B_0x1 + The low-power regulator is ready + 0x1 + + + + + REGLPF + Low-power regulator flag +This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits +the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency. +This bit is cleared by hardware when the regulator is ready. + 9 + 1 + read-only + + + B_0x0 + The regulator is ready in main mode (MR) + 0x0 + + + B_0x1 + The regulator is in low-power mode (LPR) + 0x1 + + + + + VOSF + Voltage scaling flag +A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register. + 10 + 1 + read-only + + + B_0x0 + The regulator is ready in the selected voltage range + 0x0 + + + B_0x1 + The regulator output voltage is changing to the required voltage level + 0x1 + + + + + PVDO + Programmable voltage detector output + 11 + 1 + read-only + + + B_0x0 + V<sub>DD</sub> is above the selected PVD threshold + 0x0 + + + B_0x1 + V<sub>DD</sub> is below the selected PVD threshold + 0x1 + + + + + PVMO1 + Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 1.62 V +Note: PVMO1 is cleared when PVM1 is disabled (PVME = 0). After enabling PVM1, the PVM1 output is valid after the PVM1 wakeup time. + 14 + 1 + read-only + + + B_0x0 + V<sub>DDA</sub> voltage is above PVM1 threshold (around 1.62 V). + 0x0 + + + B_0x1 + V<sub>DDA</sub> voltage is below PVM1 threshold (around 1.62 V). + 0x1 + + + + + PVMO2 + Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 1.8 V +Note: PVMO2 is cleared when PVM2 is disabled (PVME = 0). After enabling PVM2, the PVM2 output is valid after the PVM2 wakeup time. + 15 + 1 + read-only + + + B_0x0 + V<sub>DDA</sub> voltage is above PVM2 threshold (around 1.8 V). + 0x0 + + + B_0x1 + V<sub>DDA</sub> voltage is below PVM2 threshold (around 1.8 V). + 0x1 + + + + + + + PWR_SCR + PWR_SCR + Power status clear register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CWUF1 + Clear wakeup flag 1 +Setting this bit clears the WUF1 flag in the PWR_SR1 register. + 0 + 1 + write-only + + + CWUF2 + Clear wakeup flag 2 +Setting this bit clears the WUF2 flag in the PWR_SR1 register. + 1 + 1 + write-only + + + CWUF3 + Clear wakeup flag 3 +Setting this bit clears the WUF3 flag in the PWR_SR1 register. + 2 + 1 + write-only + + + CWUF4 + Clear wakeup flag 4 +Setting this bit clears the WUF4 flag in the PWR_SR1 register. + 3 + 1 + write-only + + + CWUF5 + Clear wakeup flag 5 +Setting this bit clears the WUF5 flag in the PWR_SR1 register. + 4 + 1 + write-only + + + CSBF + Clear standby flag +Setting this bit clears the SBF flag in the PWR_SR1 register. + 8 + 1 + write-only + + + + + PWR_PUCRA + PWR_PUCRA + Power Port A pull-up control register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 0 + 1 + read-write + + + PU1 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 1 + 1 + read-write + + + PU2 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 2 + 1 + read-write + + + PU3 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 3 + 1 + read-write + + + PU4 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 4 + 1 + read-write + + + PU5 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 5 + 1 + read-write + + + PU6 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 6 + 1 + read-write + + + PU7 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 7 + 1 + read-write + + + PU8 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 8 + 1 + read-write + + + PU9 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 9 + 1 + read-write + + + PU10 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 10 + 1 + read-write + + + PU11 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 11 + 1 + read-write + + + PU12 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 12 + 1 + read-write + + + PU13 + Port A pull-up bit y (y=0..13) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 13 + 1 + read-write + + + PU15 + Port A pull-up bit 15 +When set, this bit activates the pull-up on PA[15] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PD15 bit is also set. + 15 + 1 + read-write + + + + + PWR_PDCRA + PWR_PDCRA + Power Port A pull-down control register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port A pull-down bit y (y=0..12) +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD14 + Port A pull-down bit 14 +When set, this bit activates the pull-down on PA[14] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + + + PWR_PUCRB + PWR_PUCRB + Power Port B pull-up control register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 0 + 1 + read-write + + + PU1 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 1 + 1 + read-write + + + PU2 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 2 + 1 + read-write + + + PU3 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 3 + 1 + read-write + + + PU4 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 4 + 1 + read-write + + + PU5 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 5 + 1 + read-write + + + PU6 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 6 + 1 + read-write + + + PU7 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 7 + 1 + read-write + + + PU8 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 8 + 1 + read-write + + + PU9 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 9 + 1 + read-write + + + PU10 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 10 + 1 + read-write + + + PU11 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 11 + 1 + read-write + + + PU12 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 12 + 1 + read-write + + + PU13 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 13 + 1 + read-write + + + PU14 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 14 + 1 + read-write + + + PU15 + Port B pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 15 + 1 + read-write + + + + + PWR_PDCRB + PWR_PDCRB + Power Port B pull-down control register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port B pull-down bit y (y=0..3) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port B pull-down bit y (y=0..3) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port B pull-down bit y (y=0..3) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port B pull-down bit y (y=0..3) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD5 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PD14 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PD15 + Port B pull-down bit y (y=5..15) +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PUCRC + PWR_PUCRC + Power Port C pull-up control register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 0 + 1 + read-write + + + PU1 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 1 + 1 + read-write + + + PU2 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 2 + 1 + read-write + + + PU3 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 3 + 1 + read-write + + + PU4 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 4 + 1 + read-write + + + PU5 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 5 + 1 + read-write + + + PU6 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 6 + 1 + read-write + + + PU7 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 7 + 1 + read-write + + + PU8 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 8 + 1 + read-write + + + PU9 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 9 + 1 + read-write + + + PU10 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 10 + 1 + read-write + + + PU11 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 11 + 1 + read-write + + + PU12 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 12 + 1 + read-write + + + PU13 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 13 + 1 + read-write + + + PU14 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 14 + 1 + read-write + + + PU15 + Port C pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 15 + 1 + read-write + + + + + PWR_PDCRC + PWR_PDCRC + Power Port C pull-down control register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PD14 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PD15 + Port C pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PUCRD + PWR_PUCRD + Power Port D pull-up control register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 0 + 1 + read-write + + + PU1 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 1 + 1 + read-write + + + PU2 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 2 + 1 + read-write + + + PU3 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 3 + 1 + read-write + + + PU4 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 4 + 1 + read-write + + + PU5 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 5 + 1 + read-write + + + PU6 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 6 + 1 + read-write + + + PU7 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 7 + 1 + read-write + + + PU8 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 8 + 1 + read-write + + + PU9 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 9 + 1 + read-write + + + PU10 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 10 + 1 + read-write + + + PU11 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 11 + 1 + read-write + + + PU12 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 12 + 1 + read-write + + + PU13 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 13 + 1 + read-write + + + PU14 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 14 + 1 + read-write + + + PU15 + Port D pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 15 + 1 + read-write + + + + + PWR_PDCRD + PWR_PDCRD + Power Port D pull-down control register + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PD14 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PD15 + Port D pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PUCRE + PWR_PUCRE + Power Port E pull-up control register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 0 + 1 + read-write + + + PU1 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 1 + 1 + read-write + + + PU2 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 2 + 1 + read-write + + + PU3 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 3 + 1 + read-write + + + PU4 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 4 + 1 + read-write + + + PU5 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 5 + 1 + read-write + + + PU6 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 6 + 1 + read-write + + + PU7 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 7 + 1 + read-write + + + PU8 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 8 + 1 + read-write + + + PU9 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 9 + 1 + read-write + + + PU10 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 10 + 1 + read-write + + + PU11 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 11 + 1 + read-write + + + PU12 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 12 + 1 + read-write + + + PU13 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 13 + 1 + read-write + + + PU14 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 14 + 1 + read-write + + + PU15 + Port E pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 15 + 1 + read-write + + + + + PWR_PDCRE + PWR_PDCRE + Power Port E pull-down control register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PD14 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PD15 + Port E pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PUCRF + PWR_PUCRF + Power Port F pull-up control register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 0 + 1 + read-write + + + PU1 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 1 + 1 + read-write + + + PU2 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 2 + 1 + read-write + + + PU3 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 3 + 1 + read-write + + + PU4 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 4 + 1 + read-write + + + PU5 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 5 + 1 + read-write + + + PU6 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 6 + 1 + read-write + + + PU7 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 7 + 1 + read-write + + + PU8 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 8 + 1 + read-write + + + PU9 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 9 + 1 + read-write + + + PU10 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 10 + 1 + read-write + + + PU11 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 11 + 1 + read-write + + + PU12 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 12 + 1 + read-write + + + PU13 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 13 + 1 + read-write + + + PU14 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 14 + 1 + read-write + + + PU15 + Port F pull-up bit y (y=0..15) +When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 15 + 1 + read-write + + + + + PWR_PDCRF + PWR_PDCRF + Power Port F pull-down control register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PD14 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PD15 + Port F pull-down bit y (y=0..15) +When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PUCRG + PWR_PUCRG + Power Port G pull-up control register + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 0 + 1 + read-write + + + PU1 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 1 + 1 + read-write + + + PU2 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 2 + 1 + read-write + + + PU3 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 3 + 1 + read-write + + + PU4 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 4 + 1 + read-write + + + PU5 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 5 + 1 + read-write + + + PU6 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 6 + 1 + read-write + + + PU7 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 7 + 1 + read-write + + + PU8 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 8 + 1 + read-write + + + PU9 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 9 + 1 + read-write + + + PU10 + Port G pull-up bit y (y=0..10) +When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. + 10 + 1 + read-write + + + + + PWR_PDCRG + PWR_PDCRG + Power Port G pull-down control register + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port G pull-down bit y (y=0..10) +When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + + + PWR_CR5 + PWR_CR5 + Power control register + 0x80 + 0x20 + 0x00000100 + 0xFFFFFFFF + + + R1MODE + Main regular range 1 mode +This bit is only valid for the main regulator in range 1 and has no effect on range 2. It is recommended to reset this bit when the system frequency is greater than 150 MHz. Refer to + 8 + 1 + read-write + + + B_0x0 + Main regulator in range 1 boost mode. + 0x0 + + + B_0x1 + Main regulator in range 1 normal mode. + 0x1 + + + + + + + + + RNG + Random number generator + RNG + 0x50060800 + + 0x0 + 0x400 + registers + + + RNG + RNG + 90 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CED + Clock error detection + 5 + 1 + + + IE + Interrupt enable + 3 + 1 + + + RNGEN + Random number generator enable + 2 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + 0x00000000 + + + SEIS + Seed error interrupt status + 6 + 1 + read-write + + + CEIS + Clock error interrupt status + 5 + 1 + read-write + + + SECS + Seed error current status + 2 + 1 + read-only + + + CECS + Clock error current status + 1 + 1 + read-only + + + DRDY + Data ready + 0 + 1 + read-only + + + + + DR + DR + data register + 0x8 + 0x20 + read-only + 0x00000000 + + + RNDATA + Random data + 0 + 32 + + + + + + + AES + Advanced encryption standard hardware accelerator + AES + 0x50060000 + + 0x0 + 0x400 + registers + + + AES + AES + 85 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + NPBLB + NPBLB + 20 + 4 + + + KEYSIZE + KEYSIZE + 18 + 1 + + + CHMOD_2 + CHMOD_2 + 16 + 1 + + + GCMPH + GCMPH + 13 + 2 + + + DMAOUTEN + Enable DMA management of data output phase + 12 + 1 + + + DMAINEN + Enable DMA management of data input phase + 11 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + CCFIE + CCF flag interrupt enable + 9 + 1 + + + ERRC + Error clear + 8 + 1 + + + CCFC + Computation Complete Flag Clear + 7 + 1 + + + CHMOD + AES chaining mode + 5 + 2 + + + MODE + AES operating mode + 3 + 2 + + + DATATYPE + Data type selection (for data in and data out to/from the cryptographic block) + 1 + 2 + + + EN + AES enable + 0 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x00000000 + + + BUSY + BUSY + 3 + 1 + + + WRERR + Write error flag + 2 + 1 + + + RDERR + Read error flag + 1 + 1 + + + CCF + Computation complete flag + 0 + 1 + + + + + DINR + DINR + data input register + 0x8 + 0x20 + read-write + 0x00000000 + + + AES_DINR + Data Input Register + 0 + 32 + + + + + DOUTR + DOUTR + data output register + 0xC + 0x20 + read-only + 0x00000000 + + + AES_DOUTR + Data output register + 0 + 32 + + + + + KEYR0 + KEYR0 + key register 0 + 0x10 + 0x20 + read-write + 0x00000000 + + + AES_KEYR0 + Data Output Register (LSB key [31:0]) + 0 + 32 + + + + + KEYR1 + KEYR1 + key register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + AES_KEYR1 + AES key register (key [63:32]) + 0 + 32 + + + + + KEYR2 + KEYR2 + key register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + AES_KEYR2 + AES key register (key [95:64]) + 0 + 32 + + + + + KEYR3 + KEYR3 + key register 3 + 0x1C + 0x20 + read-write + 0x00000000 + + + AES_KEYR3 + AES key register (MSB key [127:96]) + 0 + 32 + + + + + IVR0 + IVR0 + initialization vector register 0 + 0x20 + 0x20 + read-write + 0x00000000 + + + AES_IVR0 + initialization vector register (LSB IVR [31:0]) + 0 + 32 + + + + + IVR1 + IVR1 + initialization vector register 1 + 0x24 + 0x20 + read-write + 0x00000000 + + + AES_IVR1 + Initialization Vector Register (IVR [63:32]) + 0 + 32 + + + + + IVR2 + IVR2 + initialization vector register 2 + 0x28 + 0x20 + read-write + 0x00000000 + + + AES_IVR2 + Initialization Vector Register (IVR [95:64]) + 0 + 32 + + + + + IVR3 + IVR3 + initialization vector register 3 + 0x2C + 0x20 + read-write + 0x00000000 + + + AES_IVR3 + Initialization Vector Register (MSB IVR [127:96]) + 0 + 32 + + + + + KEYR4 + KEYR4 + key register 4 + 0x30 + 0x20 + read-write + 0x00000000 + + + KEY + AES key + 0 + 32 + + + + + KEYR5 + KEYR5 + key register 5 + 0x34 + 0x20 + read-write + 0x00000000 + + + KEY + AES key + 0 + 32 + + + + + KEYR6 + KEYR6 + key register 6 + 0x38 + 0x20 + read-write + 0x00000000 + + + KEY + AES key + 0 + 32 + + + + + KEYR7 + KEYR7 + key register 7 + 0x3C + 0x20 + read-write + 0x00000000 + + + KEY + AES key + 0 + 32 + + + + + SUSP0R + SUSP0R + suspend registers + 0x40 + 0x20 + read-write + 0x00000000 + + + SUSP + AES suspend + 0 + 32 + + + + + SUSP1R + SUSP1R + suspend registers + 0x44 + 0x20 + read-write + 0x00000000 + + + SUSP + AES suspend + 0 + 32 + + + + + SUSP2R + SUSP2R + suspend registers + 0x48 + 0x20 + read-write + 0x00000000 + + + SUSP + AES suspend + 0 + 32 + + + + + SUSP3R + SUSP3R + suspend registers + 0x4C + 0x20 + read-write + 0x00000000 + + + SUSP + AES suspend + 0 + 32 + + + + + SUSP4R + SUSP4R + suspend registers + 0x50 + 0x20 + read-write + 0x00000000 + + + SUSP + AES suspend + 0 + 32 + + + + + SUSP5R + SUSP5R + suspend registers + 0x54 + 0x20 + read-write + 0x00000000 + + + SUSP + AES suspend + 0 + 32 + + + + + SUSP6R + SUSP6R + suspend registers + 0x58 + 0x20 + read-write + 0x00000000 + + + SUSP + AES suspend + 0 + 32 + + + + + SUSP7R + SUSP7R + suspend registers + 0x5C + 0x20 + read-write + 0x00000000 + + + SUSP + AES suspend + 0 + 32 + + + + + + + + + + GPIOA + General-purpose I/Os + GPIO + 0x48000000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xABFFFFFF + + + MODER15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x0C000000 + + + OSPEEDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x64000000 + + + PUPDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = 0..15) + 15 + 1 + + + IDR14 + Port input data (y = 0..15) + 14 + 1 + + + IDR13 + Port input data (y = 0..15) + 13 + 1 + + + IDR12 + Port input data (y = 0..15) + 12 + 1 + + + IDR11 + Port input data (y = 0..15) + 11 + 1 + + + IDR10 + Port input data (y = 0..15) + 10 + 1 + + + IDR9 + Port input data (y = 0..15) + 9 + 1 + + + IDR8 + Port input data (y = 0..15) + 8 + 1 + + + IDR7 + Port input data (y = 0..15) + 7 + 1 + + + IDR6 + Port input data (y = 0..15) + 6 + 1 + + + IDR5 + Port input data (y = 0..15) + 5 + 1 + + + IDR4 + Port input data (y = 0..15) + 4 + 1 + + + IDR3 + Port input data (y = 0..15) + 3 + 1 + + + IDR2 + Port input data (y = 0..15) + 2 + 1 + + + IDR1 + Port input data (y = 0..15) + 1 + 1 + + + IDR0 + Port input data (y = 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = 0..15) + 15 + 1 + + + ODR14 + Port output data (y = 0..15) + 14 + 1 + + + ODR13 + Port output data (y = 0..15) + 13 + 1 + + + ODR12 + Port output data (y = 0..15) + 12 + 1 + + + ODR11 + Port output data (y = 0..15) + 11 + 1 + + + ODR10 + Port output data (y = 0..15) + 10 + 1 + + + ODR9 + Port output data (y = 0..15) + 9 + 1 + + + ODR8 + Port output data (y = 0..15) + 8 + 1 + + + ODR7 + Port output data (y = 0..15) + 7 + 1 + + + ODR6 + Port output data (y = 0..15) + 6 + 1 + + + ODR5 + Port output data (y = 0..15) + 5 + 1 + + + ODR4 + Port output data (y = 0..15) + 4 + 1 + + + ODR3 + Port output data (y = 0..15) + 3 + 1 + + + ODR2 + Port output data (y = 0..15) + 2 + 1 + + + ODR1 + Port output data (y = 0..15) + 1 + 1 + + + ODR0 + Port output data (y = 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port Reset bit + 0 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR8 + Port Reset bit + 8 + 1 + + + BR9 + Port Reset bit + 9 + 1 + + + BR10 + Port Reset bit + 10 + 1 + + + BR11 + Port Reset bit + 11 + 1 + + + BR12 + Port Reset bit + 12 + 1 + + + BR13 + Port Reset bit + 13 + 1 + + + BR14 + Port Reset bit + 14 + 1 + + + BR15 + Port Reset bit + 15 + 1 + + + + + + + GPIOB + General-purpose I/Os + GPIO + 0x48000400 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFEBF + + + MODER15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x000000C0 + + + OSPEEDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000100 + + + PUPDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = 0..15) + 15 + 1 + + + IDR14 + Port input data (y = 0..15) + 14 + 1 + + + IDR13 + Port input data (y = 0..15) + 13 + 1 + + + IDR12 + Port input data (y = 0..15) + 12 + 1 + + + IDR11 + Port input data (y = 0..15) + 11 + 1 + + + IDR10 + Port input data (y = 0..15) + 10 + 1 + + + IDR9 + Port input data (y = 0..15) + 9 + 1 + + + IDR8 + Port input data (y = 0..15) + 8 + 1 + + + IDR7 + Port input data (y = 0..15) + 7 + 1 + + + IDR6 + Port input data (y = 0..15) + 6 + 1 + + + IDR5 + Port input data (y = 0..15) + 5 + 1 + + + IDR4 + Port input data (y = 0..15) + 4 + 1 + + + IDR3 + Port input data (y = 0..15) + 3 + 1 + + + IDR2 + Port input data (y = 0..15) + 2 + 1 + + + IDR1 + Port input data (y = 0..15) + 1 + 1 + + + IDR0 + Port input data (y = 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = 0..15) + 15 + 1 + + + ODR14 + Port output data (y = 0..15) + 14 + 1 + + + ODR13 + Port output data (y = 0..15) + 13 + 1 + + + ODR12 + Port output data (y = 0..15) + 12 + 1 + + + ODR11 + Port output data (y = 0..15) + 11 + 1 + + + ODR10 + Port output data (y = 0..15) + 10 + 1 + + + ODR9 + Port output data (y = 0..15) + 9 + 1 + + + ODR8 + Port output data (y = 0..15) + 8 + 1 + + + ODR7 + Port output data (y = 0..15) + 7 + 1 + + + ODR6 + Port output data (y = 0..15) + 6 + 1 + + + ODR5 + Port output data (y = 0..15) + 5 + 1 + + + ODR4 + Port output data (y = 0..15) + 4 + 1 + + + ODR3 + Port output data (y = 0..15) + 3 + 1 + + + ODR2 + Port output data (y = 0..15) + 2 + 1 + + + ODR1 + Port output data (y = 0..15) + 1 + 1 + + + ODR0 + Port output data (y = 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port Reset bit + 0 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR8 + Port Reset bit + 8 + 1 + + + BR9 + Port Reset bit + 9 + 1 + + + BR10 + Port Reset bit + 10 + 1 + + + BR11 + Port Reset bit + 11 + 1 + + + BR12 + Port Reset bit + 12 + 1 + + + BR13 + Port Reset bit + 13 + 1 + + + BR14 + Port Reset bit + 14 + 1 + + + BR15 + Port Reset bit + 15 + 1 + + + + + + + GPIOC + General-purpose I/Os + GPIO + 0x48000800 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = 0..15) + 15 + 1 + + + IDR14 + Port input data (y = 0..15) + 14 + 1 + + + IDR13 + Port input data (y = 0..15) + 13 + 1 + + + IDR12 + Port input data (y = 0..15) + 12 + 1 + + + IDR11 + Port input data (y = 0..15) + 11 + 1 + + + IDR10 + Port input data (y = 0..15) + 10 + 1 + + + IDR9 + Port input data (y = 0..15) + 9 + 1 + + + IDR8 + Port input data (y = 0..15) + 8 + 1 + + + IDR7 + Port input data (y = 0..15) + 7 + 1 + + + IDR6 + Port input data (y = 0..15) + 6 + 1 + + + IDR5 + Port input data (y = 0..15) + 5 + 1 + + + IDR4 + Port input data (y = 0..15) + 4 + 1 + + + IDR3 + Port input data (y = 0..15) + 3 + 1 + + + IDR2 + Port input data (y = 0..15) + 2 + 1 + + + IDR1 + Port input data (y = 0..15) + 1 + 1 + + + IDR0 + Port input data (y = 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = 0..15) + 15 + 1 + + + ODR14 + Port output data (y = 0..15) + 14 + 1 + + + ODR13 + Port output data (y = 0..15) + 13 + 1 + + + ODR12 + Port output data (y = 0..15) + 12 + 1 + + + ODR11 + Port output data (y = 0..15) + 11 + 1 + + + ODR10 + Port output data (y = 0..15) + 10 + 1 + + + ODR9 + Port output data (y = 0..15) + 9 + 1 + + + ODR8 + Port output data (y = 0..15) + 8 + 1 + + + ODR7 + Port output data (y = 0..15) + 7 + 1 + + + ODR6 + Port output data (y = 0..15) + 6 + 1 + + + ODR5 + Port output data (y = 0..15) + 5 + 1 + + + ODR4 + Port output data (y = 0..15) + 4 + 1 + + + ODR3 + Port output data (y = 0..15) + 3 + 1 + + + ODR2 + Port output data (y = 0..15) + 2 + 1 + + + ODR1 + Port output data (y = 0..15) + 1 + 1 + + + ODR0 + Port output data (y = 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port Reset bit + 0 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR8 + Port Reset bit + 8 + 1 + + + BR9 + Port Reset bit + 9 + 1 + + + BR10 + Port Reset bit + 10 + 1 + + + BR11 + Port Reset bit + 11 + 1 + + + BR12 + Port Reset bit + 12 + 1 + + + BR13 + Port Reset bit + 13 + 1 + + + BR14 + Port Reset bit + 14 + 1 + + + BR15 + Port Reset bit + 15 + 1 + + + + + + + GPIOD + 0x48000C00 + + + GPIOE + 0x48001000 + + + GPIOF + 0x48001400 + + + GPIOG + 0x48001800 + + + TIM15 + General purpose timers + TIM + 0x40014000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + DITHEN + Dithering Enable + 12 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + OIS2 + Output idle state 2 (OC2 output) + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + CCUS + Capture/compare control update selection + 2 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + TS_4_3 + Trigger selection - bit 4:3 + 20 + 2 + + + SMS_3 + Slave mode selection - bit 3 + 16 + 1 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + CC2OF + Capture/Compare 2 overcapture flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC2IF + Capture/compare 2 interrupt flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update generation + 5 + 1 + + + CC2G + Capture/compare 2 generation + 2 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M_3 + Output Compare 2 mode - bit 3 + 24 + 1 + + + OC1M_3 + Output Compare 1 mode + 16 + 1 + + + OC2M + OC2M + 12 + 3 + + + OC2PE + OC2PE + 11 + 1 + + + OC2FE + OC2FE + 10 + 1 + + + CC2S + CC2S + 8 + 2 + + + OC1CE + OC1CE + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + IC2F + 12 + 4 + + + IC2PSC + IC2PSC + 10 + 2 + + + CC2S + CC2S + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC2NP + Capture/Compare 2 complementary output polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x00000000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + + OSSR + Off-state selection for Run mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + BKDSRM + BKDSRM + 26 + 1 + + + BKBID + BKBID + 28 + 1 + + + + + DTR2 + DTR2 + timer Deadtime Register 2 + 0x54 + 0x20 + read-write + 0x00000000 + + + DTGF + Dead-time generator setup + 0 + 8 + + + DTAE + Deadtime Asymmetric Enable + 16 + 1 + + + DTPE + Deadtime Preload Enable + 17 + 1 + + + + + TISEL + TISEL + TIM timer input selection register + 0x5C + 0x20 + read-write + 0x00000000 + + + TI1SEL + TI1[0] to TI1[15] input selection + 0 + 4 + + + TI2SEL + TI2[0] to TI2[15] input selection + 8 + 4 + + + + + AF1 + AF1 + TIM alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + BKCMP4P + BRK COMP4 input polarity + 13 + 1 + + + BKCMP3P + BRK COMP3 input polarity + 12 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP7E + BRK COMP7 enable + 7 + 1 + + + BKCMP6E + BRK COMP6 enable + 6 + 1 + + + BKCMP5E + BRK COMP5 enable + 5 + 1 + + + BKCMP4E + BRK COMP4 enable + 4 + 1 + + + BKCMP3E + BRK COMP3 enable + 3 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + + + AF2 + AF2 + TIM alternate function option register 2 + 0x64 + 0x20 + read-write + 0x00000000 + + + OCRSEL + OCREF_CLR source selection + 16 + 3 + + + + + DCR + DCR + DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst accesses + 0 + 32 + + + + + + + TIM16 + General purpose timers + TIM + 0x40014400 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + DITHEN + Dithering Enable + 12 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + CCUS + Capture/compare control update selection + 2 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + BG + Break generation + 7 + 1 + + + COMG + Capture/Compare control update generation + 5 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M_3 + Output Compare 1 mode + 16 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x00000000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + + OSSR + Off-state selection for Run mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + BKDSRM + BKDSRM + 26 + 1 + + + BKBID + BKBID + 28 + 1 + + + + + DTR2 + DTR2 + timer Deadtime Register 2 + 0x54 + 0x20 + read-write + 0x00000000 + + + DTGF + Dead-time generator setup + 0 + 8 + + + DTAE + Deadtime Asymmetric Enable + 16 + 1 + + + DTPE + Deadtime Preload Enable + 17 + 1 + + + + + TISEL + TISEL + TIM timer input selection register + 0x5C + 0x20 + read-write + 0x00000000 + + + TI1SEL + TI1[0] to TI1[15] input selection + 0 + 4 + + + + + AF1 + AF1 + TIM alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + BKCMP4P + BRK COMP4 input polarity + 13 + 1 + + + BKCMP3P + BRK COMP3 input polarity + 12 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP7E + BRK COMP7 enable + 7 + 1 + + + BKCMP6E + BRK COMP6 enable + 6 + 1 + + + BKCMP5E + BRK COMP5 enable + 5 + 1 + + + BKCMP4E + BRK COMP4 enable + 4 + 1 + + + BKCMP3E + BRK COMP3 enable + 3 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + + + AF2 + AF2 + TIM alternate function option register 2 + 0x64 + 0x20 + read-write + 0x00000000 + + + OCRSEL + OCREF_CLR source selection + 16 + 3 + + + + + OR1 + OR1 + TIM option register 1 + 0x68 + 0x20 + read-write + 0x00000000 + + + HSE32EN + HSE Divided by 32 enable + 0 + 1 + + + + + DCR + DCR + DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst accesses + 0 + 32 + + + + + + + TIM17 + 0x40014800 + + + TIM1 + Advanced-timers + TIM + 0x40012C00 + + 0x0 + 0x400 + registers + + + TIM1_BRK_TIM15 + TIM1_BRK_TIM15 + 24 + + + TIM1_UP_TIM16 + TIM1_UP_TIM16 + 25 + + + TIM1_TRG_COM + TIM1_TRG_COM/ + 26 + + + TIM1_CC + TIM1 capture compare interrupt + 27 + + + TIM8_CC + TIM8_CC + 46 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + DITHEN + Dithering Enable + 12 + 1 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + MMS_3 + Master mode selection - bit 3 + 25 + 1 + + + MMS2 + Master mode selection 2 + 20 + 4 + + + OIS6 + Output Idle state 6 (OC6 output) + 18 + 1 + + + OIS5 + Output Idle state 5 (OC5 output) + 16 + 1 + + + OIS4N + Output Idle state 4 (OC4N output) + 15 + 1 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + CCUS + Capture/compare control update selection + 2 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + SMSPS + SMS Preload Source + 25 + 1 + + + SMSPE + SMS Preload Enable + 24 + 1 + + + TS_4_3 + Trigger selection - bit 4:3 + 20 + 2 + + + SMS_3 + Slave mode selection - bit 3 + 16 + 1 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + OCCS + OCREF clear selection + 3 + 1 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + TERRIE + Transition Error interrupt enable + 23 + 1 + + + IERRIE + Index Error interrupt enable + 22 + 1 + + + DIRIE + Direction Change interrupt enable + 21 + 1 + + + IDXIE + Index interrupt enable + 20 + 1 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + TERRF + Transition Error interrupt flag + 23 + 1 + + + IERRF + Index Error interrupt flag + 22 + 1 + + + DIRF + Direction Change interrupt flag + 21 + 1 + + + IDXF + Index interrupt flag + 20 + 1 + + + CC6IF + Compare 6 interrupt flag + 17 + 1 + + + CC5IF + Compare 5 interrupt flag + 16 + 1 + + + SBIF + System Break interrupt flag + 13 + 1 + + + CC4OF + Capture/Compare 4 overcapture flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + B2IF + Break 2 interrupt flag + 8 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC4IF + Capture/Compare 4 interrupt flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + B2G + Break 2 generation + 8 + 1 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update generation + 5 + 1 + + + CC4G + Capture/compare 4 generation + 4 + 1 + + + CC3G + Capture/compare 3 generation + 3 + 1 + + + CC2G + Capture/compare 2 generation + 2 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M_3 + Output Compare 2 mode - bit 3 + 24 + 1 + + + OC1M_3 + Output Compare 1 mode - bit 3 + 16 + 1 + + + OC2CE + Output Compare 2 clear enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload enable + 11 + 1 + + + OC2FE + Output Compare 2 fast enable + 10 + 1 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + + OC1CE + Output Compare 1 clear enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4M_3 + Output Compare 4 mode - bit 3 + 24 + 1 + + + OC3M_3 + Output Compare 3 mode - bit 3 + 16 + 1 + + + OC4CE + Output compare 4 clear enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload enable + 11 + 1 + + + OC4FE + Output compare 4 fast enable + 10 + 1 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + OC3CE + Output compare 3 clear enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload enable + 3 + 1 + + + OC3FE + Output compare 3 fast enable + 2 + 1 + + + CC3S + Capture/Compare 3 selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC6P + Capture/Compare 6 output polarity + 21 + 1 + + + CC6E + Capture/Compare 6 output enable + 20 + 1 + + + CC5P + Capture/Compare 5 output polarity + 17 + 1 + + + CC5E + Capture/Compare 5 output enable + 16 + 1 + + + CC4NP + Capture/Compare 4 complementary output polarity + 15 + 1 + + + CC4NE + Capture/Compare 4 complementary output enable + 14 + 1 + + + CC4P + Capture/Compare 3 output Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output Polarity + 11 + 1 + + + CC3NE + Capture/Compare 3 complementary output enable + 10 + 1 + + + CC3P + Capture/Compare 3 output Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output Polarity + 7 + 1 + + + CC2NE + Capture/Compare 2 complementary output enable + 6 + 1 + + + CC2P + Capture/Compare 2 output Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + UIFCPY + UIFCPY + 31 + 1 + read-only + + + CNT + counter value + 0 + 16 + read-write + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x00000000 + + + REP + Repetition counter value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + + + BK2ID + BK2ID + 29 + 1 + + + BKBID + BKBID + 28 + 1 + + + BK2DSRM + BK2DSRM + 27 + 1 + + + BKDSRM + BKDSRM + 26 + 1 + + + BK2P + Break 2 polarity + 25 + 1 + + + BK2E + Break 2 Enable + 24 + 1 + + + BK2F + Break 2 filter + 20 + 4 + + + BKF + Break filter + 16 + 4 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run mode + 11 + 1 + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + CCR5 + CCR5 + capture/compare register 4 + 0x48 + 0x20 + read-write + 0x00000000 + + + CCR5 + Capture/Compare value + 0 + 16 + + + GC5C1 + Group Channel 5 and Channel 1 + 29 + 1 + + + GC5C2 + Group Channel 5 and Channel 2 + 30 + 1 + + + GC5C3 + Group Channel 5 and Channel 3 + 31 + 1 + + + + + CCR6 + CCR6 + capture/compare register 4 + 0x4C + 0x20 + read-write + 0x00000000 + + + CCR6 + Capture/Compare value + 0 + 16 + + + + + CCMR3_Output + CCMR3_Output + capture/compare mode register 2 (output mode) + 0x50 + 0x20 + read-write + 0x00000000 + + + OC6M_bit3 + Output Compare 6 mode bit 3 + 24 + 1 + + + OC5M_bit3 + Output Compare 5 mode bit 3 + 16 + 3 + + + OC6CE + Output compare 6 clear enable + 15 + 1 + + + OC6M + Output compare 6 mode + 12 + 3 + + + OC6PE + Output compare 6 preload enable + 11 + 1 + + + OC6FE + Output compare 6 fast enable + 10 + 1 + + + OC5CE + Output compare 5 clear enable + 7 + 1 + + + OC5M + Output compare 5 mode + 4 + 3 + + + OC5PE + Output compare 5 preload enable + 3 + 1 + + + OC5FE + Output compare 5 fast enable + 2 + 1 + + + + + DTR2 + DTR2 + timer Deadtime Register 2 + 0x54 + 0x20 + read-write + 0x00000000 + + + DTPE + Deadtime Preload Enable + 17 + 1 + + + DTAE + Deadtime Asymmetric Enable + 16 + 1 + + + DTGF + Dead-time falling edge generator setup + 0 + 8 + + + + + ECR + ECR + DMA control register + 0x58 + 0x20 + read-write + 0x00000000 + + + IE + Index Enable + 0 + 1 + + + IDIR + Index Direction + 1 + 2 + + + IBLK + Index Blanking + 3 + 2 + + + FIDX + First Index + 5 + 1 + + + IPOS + Index Positioning + 6 + 2 + + + PW + Pulse width + 16 + 8 + + + PWPRSC + Pulse Width prescaler + 24 + 3 + + + + + TISEL + TISEL + TIM timer input selection register + 0x5C + 0x20 + read-write + 0x00000000 + + + TI1SEL + TI1[0] to TI1[15] input selection + 0 + 4 + + + TI2SEL + TI2[0] to TI2[15] input selection + 8 + 4 + + + TI3SEL + TI3[0] to TI3[15] input selection + 16 + 4 + + + TI4SEL + TI4[0] to TI4[15] input selection + 24 + 4 + + + + + AF1 + AF1 + TIM alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + ETRSEL + ETR source selection + 14 + 4 + + + BKCMP4P + BRK COMP4 input polarity + 13 + 1 + + + BKCMP3P + BRK COMP3 input polarity + 12 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP7E + BRK COMP7 enable + 7 + 1 + + + BKCMP6E + BRK COMP6 enable + 6 + 1 + + + BKCMP5E + BRK COMP5 enable + 5 + 1 + + + BKCMP4E + BRK COMP4 enable + 4 + 1 + + + BKCMP3E + BRK COMP3 enable + 3 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + + + AF2 + AF2 + TIM alternate function option register 2 + 0x64 + 0x20 + read-write + 0x00000000 + + + OCRSEL + OCREF_CLR source selection + 16 + 3 + + + BK2CMP4P + BRK2 COMP4 input polarity + 13 + 1 + + + BK2CMP3P + BRK2 COMP3 input polarity + 12 + 1 + + + BK2CMP2P + BRK2 COMP2 input polarity + 11 + 1 + + + BK2CMP1P + BRK2 COMP1 input polarity + 10 + 1 + + + BK2INP + BRK2 BKIN input polarity + 9 + 1 + + + BK2CMP7E + BRK2 COMP7 enable + 7 + 1 + + + BK2CMP6E + BRK2 COMP6 enable + 6 + 1 + + + BK2CMP5E + BRK2 COMP5 enable + 5 + 1 + + + BK2CMP4E + BRK2 COMP4 enable + 4 + 1 + + + BK2CMP3E + BRK2 COMP3 enable + 3 + 1 + + + BK2CMP2E + BRK2 COMP2 enable + 2 + 1 + + + BK2CMP1E + BRK2 COMP1 enable + 1 + 1 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + + + DCR + DCR + control register + 0x3DC + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst accesses + 0 + 32 + + + + + + + + TIM8 + 0x40013400 + + TIM8_BRK + TIM8_BRK + 43 + + + TIM8_UP + TIM8_UP + 44 + + + TIM8_TRG_COM + TIM8_TRG_COM + 45 + + + + TIM2 + Advanced-timers + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 + 28 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + DITHEN + Dithering Enable + 12 + 1 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + MMS_3 + Master mode selection - bit 3 + 25 + 1 + + + MMS2 + Master mode selection 2 + 20 + 4 + + + OIS6 + Output Idle state 6 (OC6 output) + 18 + 1 + + + OIS5 + Output Idle state 5 (OC5 output) + 16 + 1 + + + OIS4N + Output Idle state 4 (OC4N output) + 15 + 1 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + CCUS + Capture/compare control update selection + 2 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + SMSPS + SMS Preload Source + 25 + 1 + + + SMSPE + SMS Preload Enable + 24 + 1 + + + TS_4_3 + Trigger selection - bit 4:3 + 20 + 2 + + + SMS_3 + Slave mode selection - bit 3 + 16 + 1 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + OCCS + OCREF clear selection + 3 + 1 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + TERRIE + Transition Error interrupt enable + 23 + 1 + + + IERRIE + Index Error interrupt enable + 22 + 1 + + + DIRIE + Direction Change interrupt enable + 21 + 1 + + + IDXIE + Index interrupt enable + 20 + 1 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + TERRF + Transition Error interrupt flag + 23 + 1 + + + IERRF + Index Error interrupt flag + 22 + 1 + + + DIRF + Direction Change interrupt flag + 21 + 1 + + + IDXF + Index interrupt flag + 20 + 1 + + + CC6IF + Compare 6 interrupt flag + 17 + 1 + + + CC5IF + Compare 5 interrupt flag + 16 + 1 + + + SBIF + System Break interrupt flag + 13 + 1 + + + CC4OF + Capture/Compare 4 overcapture flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + B2IF + Break 2 interrupt flag + 8 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC4IF + Capture/Compare 4 interrupt flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + B2G + Break 2 generation + 8 + 1 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update generation + 5 + 1 + + + CC4G + Capture/compare 4 generation + 4 + 1 + + + CC3G + Capture/compare 3 generation + 3 + 1 + + + CC2G + Capture/compare 2 generation + 2 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M_3 + Output Compare 2 mode - bit 3 + 24 + 1 + + + OC1M_3 + Output Compare 1 mode - bit 3 + 16 + 1 + + + OC2CE + Output Compare 2 clear enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload enable + 11 + 1 + + + OC2FE + Output Compare 2 fast enable + 10 + 1 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + + OC1CE + Output Compare 1 clear enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4M_3 + Output Compare 4 mode - bit 3 + 24 + 1 + + + OC3M_3 + Output Compare 3 mode - bit 3 + 16 + 1 + + + OC4CE + Output compare 4 clear enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload enable + 11 + 1 + + + OC4FE + Output compare 4 fast enable + 10 + 1 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + OC3CE + Output compare 3 clear enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload enable + 3 + 1 + + + OC3FE + Output compare 3 fast enable + 2 + 1 + + + CC3S + Capture/Compare 3 selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC6P + Capture/Compare 6 output polarity + 21 + 1 + + + CC6E + Capture/Compare 6 output enable + 20 + 1 + + + CC5P + Capture/Compare 5 output polarity + 17 + 1 + + + CC5E + Capture/Compare 5 output enable + 16 + 1 + + + CC4NP + Capture/Compare 4 complementary output polarity + 15 + 1 + + + CC4NE + Capture/Compare 4 complementary output enable + 14 + 1 + + + CC4P + Capture/Compare 3 output Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output Polarity + 11 + 1 + + + CC3NE + Capture/Compare 3 complementary output enable + 10 + 1 + + + CC3P + Capture/Compare 3 output Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output Polarity + 7 + 1 + + + CC2NE + Capture/Compare 2 complementary output enable + 6 + 1 + + + CC2P + Capture/Compare 2 output Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + UIFCPY + UIFCPY + 31 + 1 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0xFFFFFFFF + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x00000000 + + + REP + Repetition counter value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + + + BK2ID + BK2ID + 29 + 1 + + + BKBID + BKBID + 28 + 1 + + + BK2DSRM + BK2DSRM + 27 + 1 + + + BKDSRM + BKDSRM + 26 + 1 + + + BK2P + Break 2 polarity + 25 + 1 + + + BK2E + Break 2 Enable + 24 + 1 + + + BK2F + Break 2 filter + 20 + 4 + + + BKF + Break filter + 16 + 4 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run mode + 11 + 1 + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + CCR5 + CCR5 + capture/compare register 4 + 0x48 + 0x20 + read-write + 0x00000000 + + + CCR5 + Capture/Compare value + 0 + 16 + + + GC5C1 + Group Channel 5 and Channel 1 + 29 + 1 + + + GC5C2 + Group Channel 5 and Channel 2 + 30 + 1 + + + GC5C3 + Group Channel 5 and Channel 3 + 31 + 1 + + + + + CCR6 + CCR6 + capture/compare register 4 + 0x4C + 0x20 + read-write + 0x00000000 + + + CCR6 + Capture/Compare value + 0 + 16 + + + + + CCMR3_Output + CCMR3_Output + capture/compare mode register 2 (output mode) + 0x50 + 0x20 + read-write + 0x00000000 + + + OC6M_bit3 + Output Compare 6 mode bit 3 + 24 + 1 + + + OC5M_bit3 + Output Compare 5 mode bit 3 + 16 + 3 + + + OC6CE + Output compare 6 clear enable + 15 + 1 + + + OC6M + Output compare 6 mode + 12 + 3 + + + OC6PE + Output compare 6 preload enable + 11 + 1 + + + OC6FE + Output compare 6 fast enable + 10 + 1 + + + OC5CE + Output compare 5 clear enable + 7 + 1 + + + OC5M + Output compare 5 mode + 4 + 3 + + + OC5PE + Output compare 5 preload enable + 3 + 1 + + + OC5FE + Output compare 5 fast enable + 2 + 1 + + + + + DTR2 + DTR2 + timer Deadtime Register 2 + 0x54 + 0x20 + read-write + 0x00000000 + + + DTPE + Deadtime Preload Enable + 17 + 1 + + + DTAE + Deadtime Asymmetric Enable + 16 + 1 + + + DTGF + Dead-time falling edge generator setup + 0 + 8 + + + + + ECR + ECR + DMA control register + 0x58 + 0x20 + read-write + 0x00000000 + + + IE + Index Enable + 0 + 1 + + + IDIR + Index Direction + 1 + 2 + + + IBLK + Index Blanking + 3 + 2 + + + FIDX + First Index + 5 + 1 + + + IPOS + Index Positioning + 6 + 2 + + + PW + Pulse width + 16 + 8 + + + PWPRSC + Pulse Width prescaler + 24 + 3 + + + + + TISEL + TISEL + TIM timer input selection register + 0x5C + 0x20 + read-write + 0x00000000 + + + TI1SEL + TI1[0] to TI1[15] input selection + 0 + 4 + + + TI2SEL + TI2[0] to TI2[15] input selection + 8 + 4 + + + TI3SEL + TI3[0] to TI3[15] input selection + 16 + 4 + + + TI4SEL + TI4[0] to TI4[15] input selection + 24 + 4 + + + + + AF1 + AF1 + TIM alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + ETRSEL + ETR source selection + 14 + 4 + + + BKCMP4P + BRK COMP4 input polarity + 13 + 1 + + + BKCMP3P + BRK COMP3 input polarity + 12 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP7E + BRK COMP7 enable + 7 + 1 + + + BKCMP6E + BRK COMP6 enable + 6 + 1 + + + BKCMP5E + BRK COMP5 enable + 5 + 1 + + + BKCMP4E + BRK COMP4 enable + 4 + 1 + + + BKCMP3E + BRK COMP3 enable + 3 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + + + AF2 + AF2 + TIM alternate function option register 2 + 0x64 + 0x20 + read-write + 0x00000000 + + + OCRSEL + OCREF_CLR source selection + 16 + 3 + + + BK2CMP4P + BRK2 COMP4 input polarity + 13 + 1 + + + BK2CMP3P + BRK2 COMP3 input polarity + 12 + 1 + + + BK2CMP2P + BRK2 COMP2 input polarity + 11 + 1 + + + BK2CMP1P + BRK2 COMP1 input polarity + 10 + 1 + + + BK2INP + BRK2 BKIN input polarity + 9 + 1 + + + BK2CMP7E + BRK2 COMP7 enable + 7 + 1 + + + BK2CMP6E + BRK2 COMP6 enable + 6 + 1 + + + BK2CMP5E + BRK2 COMP5 enable + 5 + 1 + + + BK2CMP4E + BRK2 COMP4 enable + 4 + 1 + + + BK2CMP3E + BRK2 COMP3 enable + 3 + 1 + + + BK2CMP2E + BRK2 COMP2 enable + 2 + 1 + + + BK2CMP1E + BRK2 COMP1 enable + 1 + 1 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + + + DCR + DCR + control register + 0x3DC + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst accesses + 0 + 32 + + + + + + + TIM3 + 0x40000400 + + TIM3 + TIM3 + 29 + + + + TIM4 + 0x40000800 + + TIM4 + TIM4 + 30 + + + + + TIM6 + Basic-timers + TIM + 0x40001000 + + 0x0 + 0x400 + registers + + + TIM6_DACUNDER + TIM6_DACUNDER + 54 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + DITHEN + Dithering Enable + 12 + 1 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + MMS + Master mode selection + 4 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + UDE + Update DMA request enable + 8 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + UG + Update generation + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + CNT + Low counter value + 0 + 16 + read-write + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + ARR + Low Auto-reload value + 0 + 16 + + + + + + + TIM7 + 0x40001400 + + TIM7 + TIM7 + 55 + + + + LPTIMER1 + Low power timer + LPTIM + 0x40007C00 + + 0x0 + 0x400 + registers + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + DOWN + Counter direction change up to down + 6 + 1 + + + UP + Counter direction change down to up + 5 + 1 + + + ARROK + Autoreload register update OK + 4 + 1 + + + CMPOK + Compare register update OK + 3 + 1 + + + EXTTRIG + External trigger edge event + 2 + 1 + + + ARRM + Autoreload match + 1 + 1 + + + CMPM + Compare match + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + DOWNCF + Direction change to down Clear Flag + 6 + 1 + + + UPCF + Direction change to UP Clear Flag + 5 + 1 + + + ARROKCF + Autoreload register update OK Clear Flag + 4 + 1 + + + CMPOKCF + Compare register update OK Clear Flag + 3 + 1 + + + EXTTRIGCF + External trigger valid edge Clear Flag + 2 + 1 + + + ARRMCF + Autoreload match Clear Flag + 1 + 1 + + + CMPMCF + compare match Clear Flag + 0 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + DOWNIE + Direction change to down Interrupt Enable + 6 + 1 + + + UPIE + Direction change to UP Interrupt Enable + 5 + 1 + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + + + CMPOKIE + Compare register update OK Interrupt Enable + 3 + 1 + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + + + CMPMIE + Compare match Interrupt Enable + 0 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + ENC + Encoder mode enable + 24 + 1 + + + COUNTMODE + counter mode enabled + 23 + 1 + + + PRELOAD + Registers update mode + 22 + 1 + + + WAVPOL + Waveform shape polarity + 21 + 1 + + + WAVE + Waveform shape + 20 + 1 + + + TIMOUT + Timeout enable + 19 + 1 + + + TRIGEN + Trigger enable and polarity + 17 + 2 + + + TRIGSEL + Trigger selector + 13 + 4 + + + PRESC + Clock prescaler + 9 + 3 + + + TRGFLT + Configurable digital filter for trigger + 6 + 2 + + + CKFLT + Configurable digital filter for external clock + 3 + 2 + + + CKPOL + Clock Polarity + 1 + 2 + + + CKSEL + Clock selector + 0 + 1 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + RSTARE + RSTARE + 4 + 1 + + + COUNTRST + COUNTRST + 3 + 1 + + + CNTSTRT + Timer start in continuous mode + 2 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + ENABLE + LPTIM Enable + 0 + 1 + + + + + CMP + CMP + Compare Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + Compare value + 0 + 16 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + OR + OR + option register + 0x20 + 0x20 + read-write + 0x00000000 + + + IN1 + IN1 + 0 + 1 + + + IN2 + IN2 + 1 + 1 + + + IN1_2_1 + IN1_2_1 + 2 + 2 + + + IN2_2_1 + IN2_2_1 + 4 + 2 + + + + + + + USART1 + Universal synchronous asynchronous receiver transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 + 37 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + RXFFIE + RXFFIE + 31 + 1 + + + TXFEIE + TXFEIE + 30 + 1 + + + FIFOEN + FIFOEN + 29 + 1 + + + M1 + M1 + 28 + 1 + + + EOBIE + End of Block interrupt enable + 27 + 1 + + + RTOIE + Receiver timeout interrupt enable + 26 + 1 + + + DEAT4 + Driver Enable assertion time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + OVER8 + Oversampling mode + 15 + 1 + + + CMIE + Character match interrupt enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + RTOEN + Receiver timeout enable + 23 + 1 + + + ABRMOD1 + Auto baud rate mode + 22 + 1 + + + ABRMOD0 + ABRMOD0 + 21 + 1 + + + ABREN + Auto baud rate enable + 20 + 1 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level inversion + 17 + 1 + + + RXINV + RX pin active level inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt enable + 6 + 1 + + + LBDL + LIN break detection length + 5 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection + 4 + 1 + + + DIS_NSS + DIS_NSS + 3 + 1 + + + SLVEN + SLVEN + 0 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x00000000 + + + TXFTCFG + TXFTCFG + 29 + 3 + + + RXFTIE + RXFTIE + 28 + 1 + + + RXFTCFG + RXFTCFG + 25 + 3 + + + TCBGTIE + TCBGTIE + 24 + 1 + + + TXFTIE + TXFTIE + 23 + 1 + + + WUFIE + Wakeup from Stop mode interrupt enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag selection + 20 + 2 + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + DEP + Driver enable polarity selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + ONEBIT + One sample bit method enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + Ir low-power + 2 + 1 + + + IREN + Ir mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x00000000 + + + DIV_Mantissa + DIV_Mantissa + 4 + 12 + + + DIV_Fraction + DIV_Fraction + 0 + 4 + + + + + GTPR + GTPR + Guard time and prescaler register + 0x10 + 0x20 + read-write + 0x00000000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + BLEN + Block Length + 24 + 8 + + + RTO + Receiver timeout value + 0 + 24 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x00000000 + + + TXFRQ + Transmit data flush request + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + ABRRQ + Auto baud rate request + 0 + 1 + + + + + ISR + ISR + Interrupt & status register + 0x1C + 0x20 + read-only + 0x00000000 + + + TXFT + TXFT + 27 + 1 + + + RXFT + RXFT + 26 + 1 + + + TCBGT + TCBGT + 25 + 1 + + + RXFF + RXFF + 24 + 1 + + + TXFE + TXFE + 23 + 1 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + ABRF + ABRF + 15 + 1 + + + ABRE + ABRE + 14 + 1 + + + UDR + UDR + 13 + 1 + + + EOBF + EOBF + 12 + 1 + + + RTOF + RTOF + 11 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + LBDF + LBDF + 8 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x00000000 + + + WUCF + Wakeup from Stop mode clear flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + UDRCF + UDRCF + 13 + 1 + + + EOBCF + End of block clear flag + 12 + 1 + + + RTOCF + Receiver timeout clear flag + 11 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + LBDCF + LIN break detection clear flag + 8 + 1 + + + TCBGTCF + TCBGTCF + 7 + 1 + + + TCCF + Transmission complete clear flag + 6 + 1 + + + TXFECF + TXFECF + 5 + 1 + + + IDLECF + Idle line detected clear flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TDR + Transmit data value + 0 + 9 + + + + + PRESC + PRESC + USART prescaler register + 0x2C + 0x20 + read-write + 0x00000000 + + + PRESCALER + PRESCALER + 0 + 4 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 + 39 + + + + UART4 + Universal synchronous asynchronous receiver transmitter + USART + 0x40004C00 + + 0x0 + 0x400 + registers + + + UART4 + UART4 + 52 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + RXFFIE + RXFFIE + 31 + 1 + + + TXFEIE + TXFEIE + 30 + 1 + + + FIFOEN + FIFOEN + 29 + 1 + + + M1 + M1 + 28 + 1 + + + EOBIE + End of Block interrupt enable + 27 + 1 + + + RTOIE + Receiver timeout interrupt enable + 26 + 1 + + + DEAT4 + Driver Enable assertion time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + OVER8 + Oversampling mode + 15 + 1 + + + CMIE + Character match interrupt enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + RTOEN + Receiver timeout enable + 23 + 1 + + + ABRMOD1 + Auto baud rate mode + 22 + 1 + + + ABRMOD0 + ABRMOD0 + 21 + 1 + + + ABREN + Auto baud rate enable + 20 + 1 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level inversion + 17 + 1 + + + RXINV + RX pin active level inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt enable + 6 + 1 + + + LBDL + LIN break detection length + 5 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection + 4 + 1 + + + DIS_NSS + DIS_NSS + 3 + 1 + + + SLVEN + SLVEN + 0 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x00000000 + + + TXFTCFG + TXFTCFG + 29 + 3 + + + RXFTIE + RXFTIE + 28 + 1 + + + RXFTCFG + RXFTCFG + 25 + 3 + + + TCBGTIE + TCBGTIE + 24 + 1 + + + TXFTIE + TXFTIE + 23 + 1 + + + WUFIE + Wakeup from Stop mode interrupt enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag selection + 20 + 2 + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + DEP + Driver enable polarity selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + ONEBIT + One sample bit method enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + Ir low-power + 2 + 1 + + + IREN + Ir mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x00000000 + + + DIV_Mantissa + DIV_Mantissa + 4 + 12 + + + DIV_Fraction + DIV_Fraction + 0 + 4 + + + + + GTPR + GTPR + Guard time and prescaler register + 0x10 + 0x20 + read-write + 0x00000000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + BLEN + Block Length + 24 + 8 + + + RTO + Receiver timeout value + 0 + 24 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x00000000 + + + TXFRQ + Transmit data flush request + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + ABRRQ + Auto baud rate request + 0 + 1 + + + + + ISR + ISR + Interrupt & status register + 0x1C + 0x20 + read-only + 0x000000C0 + + + TXFT + TXFT + 27 + 1 + + + RXFT + RXFT + 26 + 1 + + + TCBGT + TCBGT + 25 + 1 + + + RXFF + RXFF + 24 + 1 + + + TXFE + TXFE + 23 + 1 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + ABRF + ABRF + 15 + 1 + + + ABRE + ABRE + 14 + 1 + + + UDR + UDR + 13 + 1 + + + EOBF + EOBF + 12 + 1 + + + RTOF + RTOF + 11 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + LBDF + LBDF + 8 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x00000000 + + + WUCF + Wakeup from Stop mode clear flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + UDRCF + UDRCF + 13 + 1 + + + EOBCF + End of block clear flag + 12 + 1 + + + RTOCF + Receiver timeout clear flag + 11 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + LBDCF + LIN break detection clear flag + 8 + 1 + + + TCBGTCF + TCBGTCF + 7 + 1 + + + TCCF + Transmission complete clear flag + 6 + 1 + + + TXFECF + TXFECF + 5 + 1 + + + IDLECF + Idle line detected clear flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TDR + Transmit data value + 0 + 9 + + + + + PRESC + PRESC + USART prescaler register + 0x2C + 0x20 + read-write + 0x00000000 + + + PRESCALER + PRESCALER + 0 + 4 + + + + + + + + LPUART1 + Universal synchronous asynchronous receiver transmitter + USART + 0x40008000 + + 0x0 + 0x400 + registers + + + LPTIM1 + LPTIM1 + 49 + + + LPUART + LPUART + 91 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + RXFFIE + RXFFIE + 31 + 1 + + + TXFEIE + TXFEIE + 30 + 1 + + + FIFOEN + FIFOEN + 29 + 1 + + + M1 + Word length + 28 + 1 + + + DEAT4 + Driver Enable assertion time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + CMIE + Character match interrupt enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level inversion + 17 + 1 + + + RXINV + RX pin active level inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + STOP + STOP bits + 12 + 2 + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection + 4 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + TXFTCFG + TXFTCFG + 29 + 3 + + + RXFTIE + RXFTIE + 28 + 1 + + + RXFTCFG + RXFTCFG + 25 + 3 + + + TXFTIE + TXFTIE + 23 + 1 + + + WUFIE + Wakeup from Stop mode interrupt enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag selection + 20 + 2 + + + DEP + Driver enable polarity selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x0000 + + + BRR + BRR + 0 + 20 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x0000 + + + TXFRQ + TXFRQ + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + + + ISR + ISR + Interrupt & status register + 0x1C + 0x20 + read-only + 0x00C0 + + + TXFT + TXFT + 27 + 1 + + + RXFT + RXFT + 26 + 1 + + + RXFF + RXFF + 24 + 1 + + + TXFE + TXFE + 23 + 1 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x0000 + + + WUCF + Wakeup from Stop mode clear flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + TCCF + Transmission complete clear flag + 6 + 1 + + + IDLECF + Idle line detected clear flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x0000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + + + PRESC + PRESC + Prescaler register + 0x2C + 0x20 + read-write + 0x0000 + + + PRESCALER + PRESCALER + 0 + 4 + + + + + + + SPI1 + Serial peripheral interface/Inter-IC sound + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 + 35 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + BIDIMODE + Bidirectional data mode enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional mode + 14 + 1 + + + CRCEN + Hardware CRC calculation enable + 13 + 1 + + + CRCNEXT + CRC transfer next + 12 + 1 + + + DFF + Data frame format + 11 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave select + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000700 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + SSOE + SS output enable + 2 + 1 + + + NSSP + NSS pulse management + 3 + 1 + + + FRF + Frame format + 4 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + RXNEIE + RX buffer not empty interrupt enable + 6 + 1 + + + TXEIE + Tx buffer empty interrupt enable + 7 + 1 + + + DS + Data size + 8 + 4 + + + FRXTH + FIFO reception threshold + 12 + 1 + + + LDMA_RX + Last DMA transfer for reception + 13 + 1 + + + LDMA_TX + Last DMA transfer for transmission + 14 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x00000002 + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + CRCERR + CRC error flag + 4 + 1 + read-write + + + MODF + Mode fault + 5 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + BSY + Busy flag + 7 + 1 + read-only + + + TIFRFE + TI frame format error + 8 + 1 + read-only + + + FRLVL + FIFO reception level + 9 + 2 + read-only + + + FTLVL + FIFO transmission level + 11 + 2 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x00000000 + + + DR + Data register + 0 + 16 + + + + + CRCPR + CRCPR + CRC polynomial register + 0x10 + 0x20 + read-write + 0x00000007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RXCRCR + RXCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x00000000 + + + RxCRC + Rx CRC register + 0 + 16 + + + + + TXCRCR + TXCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x00000000 + + + TxCRC + Tx CRC register + 0 + 16 + + + + + I2SCFGR + I2SCFGR + configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHLEN + CHLEN + 0 + 1 + + + DATLEN + DATLEN + 1 + 2 + + + CKPOL + CKPOL + 3 + 1 + + + I2SSTD + I2SSTD + 4 + 2 + + + PCMSYNC + PCMSYNC + 7 + 1 + + + I2SCFG + I2SCFG + 8 + 2 + + + I2SE + I2SE + 10 + 1 + + + I2SMOD + I2SMOD + 11 + 1 + + + + + I2SPR + I2SPR + prescaler register + 0x20 + 0x20 + read-write + 0x00000002 + + + I2SDIV + I2SDIV + 0 + 8 + + + ODD + ODD + 8 + 1 + + + MCKOE + MCKOE + 9 + 1 + + + + + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 + 51 + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 + 36 + + + + EXTI + External interrupt/event controller + EXTI + 0x40010400 + + 0x0 + 0x400 + registers + + + PVD_PVM + PVD through EXTI line detection + 1 + + + EXTI0 + EXTI Line0 interrupt + 6 + + + EXTI1 + EXTI Line1 interrupt + 7 + + + EXTI2 + EXTI Line2 interrupt + 8 + + + EXTI3 + EXTI Line3 interrupt + 9 + + + EXTI4 + EXTI Line4 interrupt + 10 + + + USB_HP + USB_HP + 19 + + + USB_LP + USB_LP + 20 + + + EXTI9_5 + EXTI9_5 + 23 + + + EXTI15_10 + EXTI15_10 + 40 + + + USBWakeUP + USBWakeUP + 42 + + + CRS + CRS + 75 + + + + IMR1 + IMR1 + Interrupt mask register + 0x0 + 0x20 + read-write + 0xFF820000 + + + IM0 + Interrupt Mask on line 0 + 0 + 1 + + + IM1 + Interrupt Mask on line 1 + 1 + 1 + + + IM2 + Interrupt Mask on line 2 + 2 + 1 + + + IM3 + Interrupt Mask on line 3 + 3 + 1 + + + IM4 + Interrupt Mask on line 4 + 4 + 1 + + + IM5 + Interrupt Mask on line 5 + 5 + 1 + + + IM6 + Interrupt Mask on line 6 + 6 + 1 + + + IM7 + Interrupt Mask on line 7 + 7 + 1 + + + IM8 + Interrupt Mask on line 8 + 8 + 1 + + + IM9 + Interrupt Mask on line 9 + 9 + 1 + + + IM10 + Interrupt Mask on line 10 + 10 + 1 + + + IM11 + Interrupt Mask on line 11 + 11 + 1 + + + IM12 + Interrupt Mask on line 12 + 12 + 1 + + + IM13 + Interrupt Mask on line 13 + 13 + 1 + + + IM14 + Interrupt Mask on line 14 + 14 + 1 + + + IM15 + Interrupt Mask on line 15 + 15 + 1 + + + IM16 + Interrupt Mask on line 16 + 16 + 1 + + + IM17 + Interrupt Mask on line 17 + 17 + 1 + + + IM18 + Interrupt Mask on line 18 + 18 + 1 + + + IM19 + Interrupt Mask on line 19 + 19 + 1 + + + IM20 + Interrupt Mask on line 20 + 20 + 1 + + + IM21 + Interrupt Mask on line 21 + 21 + 1 + + + IM22 + Interrupt Mask on line 22 + 22 + 1 + + + IM23 + Interrupt Mask on line 23 + 23 + 1 + + + IM24 + Interrupt Mask on line 24 + 24 + 1 + + + IM25 + Interrupt Mask on line 25 + 25 + 1 + + + IM26 + Interrupt Mask on line 26 + 26 + 1 + + + IM27 + Interrupt Mask on line 27 + 27 + 1 + + + IM28 + Interrupt Mask on line 28 + 28 + 1 + + + IM29 + Interrupt Mask on line 29 + 29 + 1 + + + IM30 + Interrupt Mask on line 30 + 30 + 1 + + + IM31 + Interrupt Mask on line 31 + 31 + 1 + + + + + EMR1 + EMR1 + Event mask register + 0x4 + 0x20 + read-write + 0x00000000 + + + EM0 + Event Mask on line 0 + 0 + 1 + + + EM1 + Event Mask on line 1 + 1 + 1 + + + EM2 + Event Mask on line 2 + 2 + 1 + + + EM3 + Event Mask on line 3 + 3 + 1 + + + EM4 + Event Mask on line 4 + 4 + 1 + + + EM5 + Event Mask on line 5 + 5 + 1 + + + EM6 + Event Mask on line 6 + 6 + 1 + + + EM7 + Event Mask on line 7 + 7 + 1 + + + EM8 + Event Mask on line 8 + 8 + 1 + + + EM9 + Event Mask on line 9 + 9 + 1 + + + EM10 + Event Mask on line 10 + 10 + 1 + + + EM11 + Event Mask on line 11 + 11 + 1 + + + EM12 + Event Mask on line 12 + 12 + 1 + + + EM13 + Event Mask on line 13 + 13 + 1 + + + EM14 + Event Mask on line 14 + 14 + 1 + + + EM15 + Event Mask on line 15 + 15 + 1 + + + EM16 + Event Mask on line 16 + 16 + 1 + + + EM17 + Event Mask on line 17 + 17 + 1 + + + EM18 + Event Mask on line 18 + 18 + 1 + + + EM19 + Event Mask on line 19 + 19 + 1 + + + EM20 + Event Mask on line 20 + 20 + 1 + + + EM21 + Event Mask on line 21 + 21 + 1 + + + EM22 + Event Mask on line 22 + 22 + 1 + + + EM23 + Event Mask on line 23 + 23 + 1 + + + EM24 + Event Mask on line 24 + 24 + 1 + + + EM25 + Event Mask on line 25 + 25 + 1 + + + EM26 + Event Mask on line 26 + 26 + 1 + + + EM27 + Event Mask on line 27 + 27 + 1 + + + EM28 + Event Mask on line 28 + 28 + 1 + + + EM29 + Event Mask on line 29 + 29 + 1 + + + EM30 + Event Mask on line 30 + 30 + 1 + + + EM31 + Event Mask on line 31 + 31 + 1 + + + + + RTSR1 + RTSR1 + Rising Trigger selection register + 0x8 + 0x20 + read-write + 0x00000000 + + + RT0 + Rising trigger event configuration of line 0 + 0 + 1 + + + RT1 + Rising trigger event configuration of line 1 + 1 + 1 + + + RT2 + Rising trigger event configuration of line 2 + 2 + 1 + + + RT3 + Rising trigger event configuration of line 3 + 3 + 1 + + + RT4 + Rising trigger event configuration of line 4 + 4 + 1 + + + RT5 + Rising trigger event configuration of line 5 + 5 + 1 + + + RT6 + Rising trigger event configuration of line 6 + 6 + 1 + + + RT7 + Rising trigger event configuration of line 7 + 7 + 1 + + + RT8 + Rising trigger event configuration of line 8 + 8 + 1 + + + RT9 + Rising trigger event configuration of line 9 + 9 + 1 + + + RT10 + Rising trigger event configuration of line 10 + 10 + 1 + + + RT11 + Rising trigger event configuration of line 11 + 11 + 1 + + + RT12 + Rising trigger event configuration of line 12 + 12 + 1 + + + RT13 + Rising trigger event configuration of line 13 + 13 + 1 + + + RT14 + Rising trigger event configuration of line 14 + 14 + 1 + + + RT15 + Rising trigger event configuration of line 15 + 15 + 1 + + + RT16 + Rising trigger event configuration of line 16 + 16 + 1 + + + RT18 + Rising trigger event configuration of line 18 + 18 + 1 + + + RT19 + Rising trigger event configuration of line 19 + 19 + 1 + + + RT20 + Rising trigger event configuration of line 20 + 20 + 1 + + + RT21 + Rising trigger event configuration of line 21 + 21 + 1 + + + RT22 + Rising trigger event configuration of line 22 + 22 + 1 + + + RT + RT + 29 + 3 + + + + + FTSR1 + FTSR1 + Falling Trigger selection register + 0xC + 0x20 + read-write + 0x00000000 + + + FT0 + Falling trigger event configuration of line 0 + 0 + 1 + + + FT1 + Falling trigger event configuration of line 1 + 1 + 1 + + + FT2 + Falling trigger event configuration of line 2 + 2 + 1 + + + FT3 + Falling trigger event configuration of line 3 + 3 + 1 + + + FT4 + Falling trigger event configuration of line 4 + 4 + 1 + + + FT5 + Falling trigger event configuration of line 5 + 5 + 1 + + + FT6 + Falling trigger event configuration of line 6 + 6 + 1 + + + FT7 + Falling trigger event configuration of line 7 + 7 + 1 + + + FT8 + Falling trigger event configuration of line 8 + 8 + 1 + + + FT9 + Falling trigger event configuration of line 9 + 9 + 1 + + + FT10 + Falling trigger event configuration of line 10 + 10 + 1 + + + FT11 + Falling trigger event configuration of line 11 + 11 + 1 + + + FT12 + Falling trigger event configuration of line 12 + 12 + 1 + + + FT13 + Falling trigger event configuration of line 13 + 13 + 1 + + + FT14 + Falling trigger event configuration of line 14 + 14 + 1 + + + FT15 + Falling trigger event configuration of line 15 + 15 + 1 + + + FT16 + Falling trigger event configuration of line 16 + 16 + 1 + + + FT18 + Falling trigger event configuration of line 18 + 18 + 1 + + + FT19 + Falling trigger event configuration of line 19 + 19 + 1 + + + FT20 + Falling trigger event configuration of line 20 + 20 + 1 + + + FT21 + Falling trigger event configuration of line 21 + 21 + 1 + + + FT22 + Falling trigger event configuration of line 22 + 22 + 1 + + + + + SWIER1 + SWIER1 + Software interrupt event register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWI0 + Software Interrupt on line 0 + 0 + 1 + + + SWI1 + Software Interrupt on line 1 + 1 + 1 + + + SWI2 + Software Interrupt on line 2 + 2 + 1 + + + SWI3 + Software Interrupt on line 3 + 3 + 1 + + + SWI4 + Software Interrupt on line 4 + 4 + 1 + + + SWI5 + Software Interrupt on line 5 + 5 + 1 + + + SWI6 + Software Interrupt on line 6 + 6 + 1 + + + SWI7 + Software Interrupt on line 7 + 7 + 1 + + + SWI8 + Software Interrupt on line 8 + 8 + 1 + + + SWI9 + Software Interrupt on line 9 + 9 + 1 + + + SWI10 + Software Interrupt on line 10 + 10 + 1 + + + SWI11 + Software Interrupt on line 11 + 11 + 1 + + + SWI12 + Software Interrupt on line 12 + 12 + 1 + + + SWI13 + Software Interrupt on line 13 + 13 + 1 + + + SWI14 + Software Interrupt on line 14 + 14 + 1 + + + SWI15 + Software Interrupt on line 15 + 15 + 1 + + + SWI16 + Software Interrupt on line 16 + 16 + 1 + + + SWI18 + Software Interrupt on line 18 + 18 + 1 + + + SWI19 + Software Interrupt on line 19 + 19 + 1 + + + SWI20 + Software Interrupt on line 20 + 20 + 1 + + + SWI21 + Software Interrupt on line 21 + 21 + 1 + + + SWI22 + Software Interrupt on line 22 + 22 + 1 + + + + + PR1 + PR1 + Pending register + 0x14 + 0x20 + read-write + 0x00000000 + + + PIF0 + Pending bit 0 + 0 + 1 + + + PIF1 + Pending bit 1 + 1 + 1 + + + PIF2 + Pending bit 2 + 2 + 1 + + + PIF3 + Pending bit 3 + 3 + 1 + + + PIF4 + Pending bit 4 + 4 + 1 + + + PIF5 + Pending bit 5 + 5 + 1 + + + PIF6 + Pending bit 6 + 6 + 1 + + + PIF7 + Pending bit 7 + 7 + 1 + + + PIF8 + Pending bit 8 + 8 + 1 + + + PIF9 + Pending bit 9 + 9 + 1 + + + PIF10 + Pending bit 10 + 10 + 1 + + + PIF11 + Pending bit 11 + 11 + 1 + + + PIF12 + Pending bit 12 + 12 + 1 + + + PIF13 + Pending bit 13 + 13 + 1 + + + PIF14 + Pending bit 14 + 14 + 1 + + + PIF15 + Pending bit 15 + 15 + 1 + + + PIF16 + Pending bit 16 + 16 + 1 + + + PIF18 + Pending bit 18 + 18 + 1 + + + PIF19 + Pending bit 19 + 19 + 1 + + + PIF20 + Pending bit 20 + 20 + 1 + + + PIF21 + Pending bit 21 + 21 + 1 + + + PIF22 + Pending bit 22 + 22 + 1 + + + + + IMR2 + IMR2 + Interrupt mask register + 0x20 + 0x20 + read-write + 0xFFFFFF87 + + + IM32 + Interrupt Mask on external/internal line 32 + 0 + 1 + + + IM33 + Interrupt Mask on external/internal line 33 + 1 + 1 + + + IM34 + Interrupt Mask on external/internal line 34 + 2 + 1 + + + IM35 + Interrupt Mask on external/internal line 35 + 3 + 1 + + + IM36 + Interrupt Mask on external/internal line 36 + 4 + 1 + + + IM37 + Interrupt Mask on external/internal line 37 + 5 + 1 + + + IM38 + Interrupt Mask on external/internal line 38 + 6 + 1 + + + IM39 + Interrupt Mask on external/internal line 39 + 7 + 1 + + + IM40 + Interrupt Mask on external/internal line 40 + 8 + 1 + + + IM41 + Interrupt Mask on external/internal line 41 + 9 + 1 + + + IM42 + Interrupt Mask on external/internal line 42 + 10 + 1 + + + IM43 + Interrupt Mask on external/internal line 43 + 11 + 1 + + + + + EMR2 + EMR2 + Event mask register + 0x24 + 0x20 + read-write + 0x00000000 + + + EM32 + Event mask on external/internal line 32 + 0 + 1 + + + EM33 + Event mask on external/internal line 33 + 1 + 1 + + + EM34 + Event mask on external/internal line 34 + 2 + 1 + + + EM35 + Event mask on external/internal line 35 + 3 + 1 + + + EM36 + Event mask on external/internal line 36 + 4 + 1 + + + EM37 + Event mask on external/internal line 37 + 5 + 1 + + + EM38 + Event mask on external/internal line 38 + 6 + 1 + + + EM39 + Event mask on external/internal line 39 + 7 + 1 + + + EM40 + Event mask on external/internal line 40 + 8 + 1 + + + + + RTSR2 + RTSR2 + Rising Trigger selection register + 0x28 + 0x20 + read-write + 0x00000000 + + + RT32 + Rising trigger event configuration bit of line 32 + 0 + 1 + + + RT33 + Rising trigger event configuration bit of line 32 + 1 + 1 + + + RT38 + Rising trigger event configuration bit of line 38 + 6 + 1 + + + RT39 + Rising trigger event configuration bit of line 39 + 7 + 1 + + + RT40 + Rising trigger event configuration bit of line 40 + 8 + 1 + + + RT41 + Rising trigger event configuration bit of line 41 + 9 + 1 + + + + + FTSR2 + FTSR2 + Falling Trigger selection register + 0x2C + 0x20 + read-write + 0x00000000 + + + FT35 + Falling trigger event configuration bit of line 35 + 3 + 1 + + + FT36 + Falling trigger event configuration bit of line 36 + 4 + 1 + + + FT37 + Falling trigger event configuration bit of line 37 + 5 + 1 + + + FT38 + Falling trigger event configuration bit of line 38 + 6 + 1 + + + + + SWIER2 + SWIER2 + Software interrupt event register + 0x30 + 0x20 + read-write + 0x00000000 + + + SWI35 + Software interrupt on line 35 + 3 + 1 + + + SWI36 + Software interrupt on line 36 + 4 + 1 + + + SWI37 + Software interrupt on line 37 + 5 + 1 + + + SWI38 + Software interrupt on line 38 + 6 + 1 + + + + + PR2 + PR2 + Pending register + 0x34 + 0x20 + read-write + 0x00000000 + + + PIF35 + Pending interrupt flag on line 35 + 3 + 1 + + + PIF36 + Pending interrupt flag on line 36 + 4 + 1 + + + PIF37 + Pending interrupt flag on line 37 + 5 + 1 + + + PIF38 + Pending interrupt flag on line 38 + 6 + 1 + + + + + + + RTC + Real-time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC_TAMP_CSS_LSE + RTC_TAMP_CSS_LSE + 2 + + + RTC_WKUP + RTC Wakeup timer + 3 + + + RTC_ALARM + RTC_ALARM + 41 + + + + TR + TR + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + DR + DR + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens in BCD format + 20 + 4 + + + YU + Year units in BCD format + 16 + 4 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + SSR + SSR + sub second register + 0x8 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + ICSR + ICSR + initialization and status register + 0xC + 0x20 + 0x00000007 + + + ALRAWF + Alarm A write flag + 0 + 1 + read-only + + + ALRBWF + Alarm B write flag + 1 + 1 + read-only + + + WUTWF + Wakeup timer write flag + 2 + 1 + read-only + + + SHPF + Shift operation pending + 3 + 1 + read-write + + + INITS + Initialization status flag + 4 + 1 + read-only + + + RSF + Registers synchronization flag + 5 + 1 + read-write + + + INITF + Initialization flag + 6 + 1 + read-only + + + INIT + Initialization mode + 7 + 1 + read-write + + + RECALPF + Recalibration pending Flag + 16 + 1 + read-only + + + + + PRER + PRER + prescaler register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_A + Asynchronous prescaler factor + 16 + 7 + + + PREDIV_S + Synchronous prescaler factor + 0 + 15 + + + + + WUTR + WUTR + wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value bits + 0 + 16 + + + + + CR + CR + control register + 0x18 + 0x20 + read-write + 0x00000000 + + + WCKSEL + Wakeup clock selection + 0 + 3 + + + TSEDGE + Time-stamp event active edge + 3 + 1 + + + REFCKON + Reference clock detection enable (50 or 60 Hz) + 4 + 1 + + + BYPSHAD + Bypass the shadow registers + 5 + 1 + + + FMT + Hour format + 6 + 1 + + + ALRAE + Alarm A enable + 8 + 1 + + + ALRBE + Alarm B enable + 9 + 1 + + + WUTE + Wakeup timer enable + 10 + 1 + + + TSE + Time stamp enable + 11 + 1 + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + + + WUTIE + Wakeup timer interrupt enable + 14 + 1 + + + TSIE + Time-stamp interrupt enable + 15 + 1 + + + ADD1H + Add 1 hour (summer time change) + 16 + 1 + + + SUB1H + Subtract 1 hour (winter time change) + 17 + 1 + + + BKP + Backup + 18 + 1 + + + COSEL + Calibration output selection + 19 + 1 + + + POL + Output polarity + 20 + 1 + + + OSEL + Output selection + 21 + 2 + + + COE + Calibration output enable + 23 + 1 + + + ITSE + timestamp on internal event enable + 24 + 1 + + + TAMPTS + TAMPTS + 25 + 1 + + + TAMPOE + TAMPOE + 26 + 1 + + + TAMPALRM_PU + TAMPALRM_PU + 29 + 1 + + + TAMPALRM_TYPE + TAMPALRM_TYPE + 30 + 1 + + + OUT2EN + OUT2EN + 31 + 1 + + + + + WPR + WPR + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key + 0 + 8 + + + + + CALR + CALR + calibration register + 0x28 + 0x20 + read-write + 0x00000000 + + + CALP + Increase frequency of RTC by 488.5 ppm + 15 + 1 + + + CALW8 + Use an 8-second calibration cycle period + 14 + 1 + + + CALW16 + Use a 16-second calibration cycle period + 13 + 1 + + + CALM + Calibration minus + 0 + 9 + + + + + SHIFTR + SHIFTR + shift control register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add one second + 31 + 1 + + + SUBFS + Subtract a fraction of a second + 0 + 15 + + + + + TSTR + TSTR + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + SU + Second units in BCD format + 0 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + HU + Hour units in BCD format + 16 + 4 + + + HT + Hour tens in BCD format + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + + + TSDR + TSDR + time stamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + TSSSR + TSSSR + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + ALRMAR + ALRMAR + alarm A register + 0x40 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm A date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD format + 24 + 4 + + + MSK3 + Alarm A hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm A minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm A seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + ALRMASSR + ALRMASSR + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + ALRMBR + ALRMBR + alarm B register + 0x48 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm B date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD format + 24 + 4 + + + MSK3 + Alarm B hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm B minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm B seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + ALRMBSSR + ALRMBSSR + alarm B sub second register + 0x4C + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + SR + SR + status register + 0x50 + 0x20 + read-only + 0x00000000 + + + ALRAF + ALRAF + 0 + 1 + + + ALRBF + ALRBF + 1 + 1 + + + WUTF + WUTF + 2 + 1 + + + TSF + TSF + 3 + 1 + + + TSOVF + TSOVF + 4 + 1 + + + ITSF + ITSF + 5 + 1 + + + + + MISR + MISR + status register + 0x54 + 0x20 + read-only + 0x00000000 + + + ALRAMF + ALRAMF + 0 + 1 + + + ALRBMF + ALRBMF + 1 + 1 + + + WUTMF + WUTMF + 2 + 1 + + + TSMF + TSMF + 3 + 1 + + + TSOVMF + TSOVMF + 4 + 1 + + + ITSMF + ITSMF + 5 + 1 + + + + + SCR + SCR + status register + 0x5C + 0x20 + write-only + 0x00000000 + + + CALRAF + CALRAF + 0 + 1 + + + CALRBF + CALRBF + 1 + 1 + + + CWUTF + CWUTF + 2 + 1 + + + CTSF + CTSF + 3 + 1 + + + CTSOVF + CTSOVF + 4 + 1 + + + CITSF + CITSF + 5 + 1 + + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_CH1 + DMA1 channel 1 interrupt + 11 + + + DMA1_CH2 + DMA1 channel 2 interrupt + 12 + + + DMA1_CH3 + DMA1 channel 3 interrupt + 13 + + + DMA1_CH4 + DMA1 channel 4 interrupt + 14 + + + DMA1_CH5 + DMA1 channel 5 interrupt + 15 + + + DMA1_CH6 + DMA1 channel 6 interrupt + 16 + + + + + ISR + ISR + interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + TEIF8 + TEIF8 + 31 + 1 + + + HTIF8 + HTIF8 + 30 + 1 + + + TCIF8 + TCIF8 + 29 + 1 + + + GIF8 + GIF8 + 28 + 1 + + + TEIF7 + TEIF7 + 27 + 1 + + + HTIF7 + HTIF7 + 26 + 1 + + + TCIF7 + TCIF7 + 25 + 1 + + + GIF7 + GIF7 + 24 + 1 + + + TEIF6 + TEIF6 + 23 + 1 + + + HTIF6 + HTIF6 + 22 + 1 + + + TCIF6 + TCIF6 + 21 + 1 + + + GIF6 + GIF6 + 20 + 1 + + + TEIF5 + TEIF5 + 19 + 1 + + + HTIF5 + HTIF5 + 18 + 1 + + + TCIF5 + TCIF5 + 17 + 1 + + + GIF5 + GIF5 + 16 + 1 + + + TEIF4 + TEIF4 + 15 + 1 + + + HTIF4 + HTIF4 + 14 + 1 + + + TCIF4 + TCIF4 + 13 + 1 + + + GIF4 + GIF4 + 12 + 1 + + + TEIF3 + TEIF3 + 11 + 1 + + + HTIF3 + HTIF3 + 10 + 1 + + + TCIF3 + TCIF3 + 9 + 1 + + + GIF3 + GIF3 + 8 + 1 + + + TEIF2 + TEIF2 + 7 + 1 + + + HTIF2 + HTIF2 + 6 + 1 + + + TCIF2 + TCIF2 + 5 + 1 + + + GIF2 + GIF2 + 4 + 1 + + + TEIF1 + TEIF1 + 3 + 1 + + + HTIF1 + HTIF1 + 2 + 1 + + + TCIF1 + TCIF1 + 1 + 1 + + + GIF1 + GIF1 + 0 + 1 + + + + + IFCR + IFCR + DMA interrupt flag clear register + 0x4 + 0x20 + write-only + 0x00000000 + + + TEIF8 + TEIF8 + 31 + 1 + + + HTIF8 + HTIF8 + 30 + 1 + + + TCIF8 + TCIF8 + 29 + 1 + + + GIF8 + GIF8 + 28 + 1 + + + TEIF7 + TEIF7 + 27 + 1 + + + HTIF7 + HTIF7 + 26 + 1 + + + TCIF7 + TCIF7 + 25 + 1 + + + GIF7 + GIF7 + 24 + 1 + + + TEIF6 + TEIF6 + 23 + 1 + + + HTIF6 + HTIF6 + 22 + 1 + + + TCIF6 + TCIF6 + 21 + 1 + + + GIF6 + GIF6 + 20 + 1 + + + TEIF5 + TEIF5 + 19 + 1 + + + HTIF5 + HTIF5 + 18 + 1 + + + TCIF5 + TCIF5 + 17 + 1 + + + GIF5 + GIF5 + 16 + 1 + + + TEIF4 + TEIF4 + 15 + 1 + + + HTIF4 + HTIF4 + 14 + 1 + + + TCIF4 + TCIF4 + 13 + 1 + + + GIF4 + GIF4 + 12 + 1 + + + TEIF3 + TEIF3 + 11 + 1 + + + HTIF3 + HTIF3 + 10 + 1 + + + TCIF3 + TCIF3 + 9 + 1 + + + GIF3 + GIF3 + 8 + 1 + + + TEIF2 + TEIF2 + 7 + 1 + + + HTIF2 + HTIF2 + 6 + 1 + + + TCIF2 + TCIF2 + 5 + 1 + + + GIF2 + GIF2 + 4 + 1 + + + TEIF1 + TEIF1 + 3 + 1 + + + HTIF1 + HTIF1 + 2 + 1 + + + TCIF1 + TCIF1 + 1 + 1 + + + GIF1 + GIF1 + 0 + 1 + + + + + CCR1 + CCR1 + DMA channel 1 configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR2 + CCR2 + DMA channel 2 configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR3 + CCR3 + DMA channel 3 configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR4 + CCR4 + DMA channel 3 configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR5 + CCR5 + DMA channel 4 configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR6 + CCR6 + DMA channel 5 configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR7 + CCR7 + DMA channel 6 configuration register + 0x80 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR8 + CCR8 + DMA channel 7 configuration register + 0x94 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CNDTR1 + CNDTR1 + channel x number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR2 + CNDTR2 + channel x number of data to transfer register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR3 + CNDTR3 + channel x number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR4 + CNDTR4 + channel x number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR5 + CNDTR5 + channel x number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR6 + CNDTR6 + channel x number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR7 + CNDTR7 + channel x number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR8 + CNDTR8 + channel x number of data to transfer register + 0x98 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CPAR1 + CPAR1 + DMA channel x peripheral address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR2 + CPAR2 + DMA channel x peripheral address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR3 + CPAR3 + DMA channel x peripheral address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR4 + CPAR4 + DMA channel x peripheral address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR5 + CPAR5 + DMA channel x peripheral address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR6 + CPAR6 + DMA channel x peripheral address register + 0x74 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR7 + CPAR7 + DMA channel x peripheral address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR8 + CPAR8 + DMA channel x peripheral address register + 0x9C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR1 + CMAR1 + DMA channel x memory address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR2 + CMAR2 + DMA channel x memory address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR3 + CMAR3 + DMA channel x memory address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR4 + CMAR4 + DMA channel x memory address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR5 + CMAR5 + DMA channel x memory address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR6 + CMAR6 + DMA channel x memory address register + 0x78 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR7 + CMAR7 + DMA channel x memory address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR8 + CMAR8 + DMA channel x memory address register + 0xA0 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + + + DMA2 + 0x40020400 + + + DMA2_CH1 + DMA2_CH1 + 56 + + + DMA2_CH2 + DMA2_CH2 + 57 + + + DMA2_CH3 + DMA2_CH3 + 58 + + + DMA2_CH4 + DMA2_CH4 + 59 + + + DMA2_CH5 + DMA2_CH5 + 60 + + + DMA2_CH6 + DMA2_CH6 + 97 + + + + + DMAMUX + DMAMUX + DMAMUX + 0x40020800 + + 0x0 + 0x400 + registers + + + DMAMUX_OVR + DMAMUX_OVR + 94 + + + + C0CR + C0CR + DMAMux - DMA request line multiplexer channel x control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C1CR + C1CR + DMAMux - DMA request line multiplexer channel x control register + 0x4 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C2CR + C2CR + DMAMux - DMA request line multiplexer channel x control register + 0x8 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C3CR + C3CR + DMAMux - DMA request line multiplexer channel x control register + 0xC + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C4CR + C4CR + DMAMux - DMA request line multiplexer channel x control register + 0x10 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C5CR + C5CR + DMAMux - DMA request line multiplexer channel x control register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C6CR + C6CR + DMAMux - DMA request line multiplexer channel x control register + 0x18 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C7CR + C7CR + DMAMux - DMA request line multiplexer channel x control register + 0x1C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C8CR + C8CR + DMAMux - DMA request line multiplexer channel x control register + 0x20 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C9CR + C9CR + DMAMux - DMA request line multiplexer channel x control register + 0x24 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C10CR + C10CR + DMAMux - DMA request line multiplexer channel x control register + 0x28 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C11CR + C11CR + DMAMux - DMA request line multiplexer channel x control register + 0x2C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C12CR + C12CR + DMAMux - DMA request line multiplexer channel x control register + 0x30 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C13CR + C13CR + DMAMux - DMA request line multiplexer channel x control register + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C14CR + C14CR + DMAMux - DMA request line multiplexer channel x control register + 0x38 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C15CR + C15CR + DMAMux - DMA request line multiplexer channel x control register + 0x3C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + RG0CR + RG0CR + DMAMux - DMA request generator channel x control register + 0x100 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input selected + 0 + 5 + + + OIE + Interrupt enable at trigger event overrun + 8 + 1 + + + GE + DMA request generator channel enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. + 19 + 5 + + + + + RG1CR + RG1CR + DMAMux - DMA request generator channel x control register + 0x104 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input selected + 0 + 5 + + + OIE + Interrupt enable at trigger event overrun + 8 + 1 + + + GE + DMA request generator channel enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. + 19 + 5 + + + + + RG2CR + RG2CR + DMAMux - DMA request generator channel x control register + 0x108 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input selected + 0 + 5 + + + OIE + Interrupt enable at trigger event overrun + 8 + 1 + + + GE + DMA request generator channel enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. + 19 + 5 + + + + + RG3CR + RG3CR + DMAMux - DMA request generator channel x control register + 0x10C + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input selected + 0 + 5 + + + OIE + Interrupt enable at trigger event overrun + 8 + 1 + + + GE + DMA request generator channel enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. + 19 + 5 + + + + + RGSR + RGSR + DMAMux - DMA request generator status register + 0x140 + 0x20 + read-only + 0x00000000 + + + OF + Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + 0 + 4 + + + + + RGCFR + RGCFR + DMAMux - DMA request generator clear flag register + 0x144 + 0x20 + write-only + 0x00000000 + + + COF + Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register. + 0 + 4 + + + + + CSR + CSR + DMAMUX request line multiplexer interrupt channel status register + 0x80 + 0x20 + read-only + 0x00000000 + + + SOF + Synchronization overrun event flag + 0 + 16 + + + + + CFR + CFR + DMAMUX request line multiplexer interrupt clear flag register + 0x84 + 0x20 + write-only + 0x00000000 + + + CSOF + Clear synchronization overrun event flag + 0 + 16 + + + + + + + SYSCFG + System configuration controller + SYSCFG + 0x40010000 + + 0x0 + 0x2A + registers + + + + MEMRMP + MEMRMP + Remap Memory register + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MODE + Memory mapping selection + 0 + 3 + + + FB_mode + User Flash Bank mode + 8 + 1 + + + + + CFGR1 + CFGR1 + peripheral mode configuration register + 0x4 + 0x20 + read-write + 0x7C000001 + + + BOOSTEN + BOOSTEN + 8 + 1 + + + ANASWVDD + GPIO analog switch control voltage selection + 9 + 1 + + + I2C_PB6_FMP + FM+ drive capability on PB6 + 16 + 1 + + + I2C_PB7_FMP + FM+ drive capability on PB6 + 17 + 1 + + + I2C_PB8_FMP + FM+ drive capability on PB6 + 18 + 1 + + + I2C_PB9_FMP + FM+ drive capability on PB6 + 19 + 1 + + + I2C1_FMP + I2C1 FM+ drive capability enable + 20 + 1 + + + I2C2_FMP + I2C1 FM+ drive capability enable + 21 + 1 + + + I2C3_FMP + I2C1 FM+ drive capability enable + 22 + 1 + + + I2C4_FMP + I2C1 FM+ drive capability enable + 23 + 1 + + + FPU_IE + FPU Interrupts Enable + 26 + 6 + + + + + EXTICR1 + EXTICR1 + external interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXTI3 + EXTI x configuration (x = 0 to 3) + 12 + 4 + + + EXTI2 + EXTI x configuration (x = 0 to 3) + 8 + 4 + + + EXTI1 + EXTI x configuration (x = 0 to 3) + 4 + 4 + + + EXTI0 + EXTI x configuration (x = 0 to 3) + 0 + 4 + + + + + EXTICR2 + EXTICR2 + external interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXTI7 + EXTI x configuration (x = 4 to 7) + 12 + 4 + + + EXTI6 + EXTI x configuration (x = 4 to 7) + 8 + 4 + + + EXTI5 + EXTI x configuration (x = 4 to 7) + 4 + 4 + + + EXTI4 + EXTI x configuration (x = 4 to 7) + 0 + 4 + + + + + EXTICR3 + EXTICR3 + external interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXTI11 + EXTI x configuration (x = 8 to 11) + 12 + 4 + + + EXTI10 + EXTI10 + 8 + 4 + + + EXTI9 + EXTI x configuration (x = 8 to 11) + 4 + 4 + + + EXTI8 + EXTI x configuration (x = 8 to 11) + 0 + 4 + + + + + EXTICR4 + EXTICR4 + external interrupt configuration register 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXTI15 + EXTI x configuration (x = 12 to 15) + 12 + 4 + + + EXTI14 + EXTI x configuration (x = 12 to 15) + 8 + 4 + + + EXTI13 + EXTI x configuration (x = 12 to 15) + 4 + 4 + + + EXTI12 + EXTI x configuration (x = 12 to 15) + 0 + 4 + + + + + SCSR + SCSR + CCM SRAM control and status register + 0x18 + 0x20 + 0x00000000 + + + CCMER + CCM SRAM Erase + 0 + 1 + read-write + + + CCMBSY + CCM SRAM busy by erase operation + 1 + 1 + read-only + + + + + CFGR2 + CFGR2 + configuration register 2 + 0x1C + 0x20 + read-write + 0x00000000 + + + CLL + Core Lockup Lock + 0 + 1 + + + SPL + SRAM Parity Lock + 1 + 1 + + + PVDL + PVD Lock + 2 + 1 + + + ECCL + ECC Lock + 3 + 1 + + + SPF + SRAM Parity Flag + 8 + 1 + + + + + SWPR + SWPR + SRAM Write protection register 1 + 0x20 + 0x20 + read-write + 0x00000000 + + + Page0_WP + Write protection + 0 + 1 + + + Page1_WP + Write protection + 1 + 1 + + + Page2_WP + Write protection + 2 + 1 + + + Page3_WP + Write protection + 3 + 1 + + + Page4_WP + Write protection + 4 + 1 + + + Page5_WP + Write protection + 5 + 1 + + + Page6_WP + Write protection + 6 + 1 + + + Page7_WP + Write protection + 7 + 1 + + + Page8_WP + Write protection + 8 + 1 + + + Page9_WP + Write protection + 9 + 1 + + + Page10_WP + Write protection + 10 + 1 + + + Page11_WP + Write protection + 11 + 1 + + + Page12_WP + Write protection + 12 + 1 + + + Page13_WP + Write protection + 13 + 1 + + + Page14_WP + Write protection + 14 + 1 + + + Page15_WP + Write protection + 15 + 1 + + + Page16_WP + Write protection + 16 + 1 + + + Page17_WP + Write protection + 17 + 1 + + + Page18_WP + Write protection + 18 + 1 + + + Page19_WP + Write protection + 19 + 1 + + + Page20_WP + Write protection + 20 + 1 + + + Page21_WP + Write protection + 21 + 1 + + + Page22_WP + Write protection + 22 + 1 + + + Page23_WP + Write protection + 23 + 1 + + + Page24_WP + Write protection + 24 + 1 + + + Page25_WP + Write protection + 25 + 1 + + + Page26_WP + Write protection + 26 + 1 + + + Page27_WP + Write protection + 27 + 1 + + + Page28_WP + Write protection + 28 + 1 + + + Page29_WP + Write protection + 29 + 1 + + + Page30_WP + Write protection + 30 + 1 + + + Page31_WP + Write protection + 31 + 1 + + + + + SKR + SKR + SRAM2 Key Register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + SRAM2 Key for software erase + 0 + 8 + + + + + + + VREFBUF + Voltage reference buffer + VREFBUF + 0x40010030 + + 0x0 + 0x1D0 + registers + + + + VREFBUF_CSR + VREFBUF_CSR + VREF_BUF Control and Status Register + 0x0 + 0x20 + 0x00000002 + + + ENVR + Enable Voltage Reference + 0 + 1 + read-write + + + HIZ + High impedence mode for the VREF_BUF + 1 + 1 + read-write + + + VRR + Voltage reference buffer ready + 3 + 1 + read-only + + + VRS + Voltage reference scale + 4 + 2 + read-write + + + + + VREFBUF_CCR + VREFBUF_CCR + VREF_BUF Calibration Control Register + 0x04 + 0x20 + read-write + 0x00000000 + + + TRIM + Trimming code + 0 + 6 + + + + + + + COMP + Comparator control and status register + COMP + 0x40010200 + + 0x0 + 0x100 + registers + + + COMP1_2_3 + COMP1_2_3 + 64 + + + COMP4_5_6 + COMP4_5_6 + 65 + + + COMP7 + COMP7 + 66 + + + + COMP_C1CSR + COMP_C1CSR + Comparator control/status register + 0x0 + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + COMP_C2CSR + COMP_C2CSR + Comparator control/status register + 0x4 + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + COMP_C3CSR + COMP_C3CSR + Comparator control/status register + 0x8 + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + COMP_C4CSR + COMP_C4CSR + Comparator control/status register + 0x0C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + + + OPAMP + Operational amplifiers + OPAMP + 0x40010300 + + 0x0 + 0x100 + registers + + + + OPAMP1_CSR + OPAMP1_CSR + OPAMP1 control/status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP2_CSR + OPAMP2_CSR + OPAMP2 control/status register + 0x4 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP3_CSR + OPAMP3_CSR + OPAMP3 control/status register + 0x8 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP1_TCMR + OPAMP1_TCMR + OPAMP1 control/status register + 0x18 + 0x20 + read-write + 0x00000000 + + + VMS_SEL + VMS_SEL + 0 + 1 + + + VPS_SEL + VPS_SEL + 1 + 2 + + + T1CM_EN + T1CM_EN + 3 + 1 + + + T8CM_EN + T8CM_EN + 4 + 1 + + + T20CM_EN + T20CM_EN + 5 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP2_TCMR + OPAMP2_TCMR + OPAMP2 control/status register + 0x1C + 0x20 + read-write + 0x00000000 + + + VMS_SEL + VMS_SEL + 0 + 1 + + + VPS_SEL + VPS_SEL + 1 + 2 + + + T1CM_EN + T1CM_EN + 3 + 1 + + + T8CM_EN + T8CM_EN + 4 + 1 + + + T20CM_EN + T20CM_EN + 5 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP3_TCMR + OPAMP3_TCMR + OPAMP3 control/status register + 0x20 + 0x20 + read-write + 0x00000000 + + + VMS_SEL + VMS_SEL + 0 + 1 + + + VPS_SEL + VPS_SEL + 1 + 2 + + + T1CM_EN + T1CM_EN + 3 + 1 + + + T8CM_EN + T8CM_EN + 4 + 1 + + + T20CM_EN + T20CM_EN + 5 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + + + + DAC1 + Digital-to-analog converter + DAC + 0x50000800 + + 0x0 + 0x400 + registers + + + + DAC_CR + DAC_CR + DAC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN1 + DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1. + 0 + 1 + + + TEN1 + DAC channel1 trigger enable + 1 + 1 + + + TSEL1 + DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). + 2 + 4 + + + WAVE1 + DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). + 6 + 2 + + + MAMP1 + DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 + 8 + 4 + + + DMAEN1 + DAC channel1 DMA enable This bit is set and cleared by software. + 12 + 1 + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software. + 13 + 1 + + + CEN1 + DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. + 14 + 1 + + + EN2 + DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. + 16 + 1 + + + TEN2 + DAC channel2 trigger enable + 17 + 1 + + + TSEL2 + DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). + 18 + 4 + + + WAVE2 + DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) + 22 + 2 + + + MAMP2 + DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 + 24 + 4 + + + DMAEN2 + DAC channel2 DMA enable This bit is set and cleared by software. + 28 + 1 + + + DMAUDRIE2 + DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. + 29 + 1 + + + CEN2 + DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. + 30 + 1 + + + + + DAC_SWTRGR + DAC_SWTRGR + DAC software trigger register + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG1 + DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register. + 0 + 1 + + + SWTRIG2 + DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. + 1 + 1 + + + SWTRIGB1 + DAC channel1 software trigger B + 16 + 1 + + + SWTRIGB2 + DAC channel2 software trigger B + 17 + 1 + + + + + DAC_DHR12R1 + DAC_DHR12R1 + DAC channel1 12-bit right-aligned data holding register + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. + 0 + 12 + + + DACC1DHRB + DAC channel1 12-bit right-aligned data B + 16 + 12 + + + + + DAC_DHR12L1 + DAC_DHR12L1 + DAC channel1 12-bit left aligned data holding register + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. + 4 + 12 + + + DACC1DHRB + DAC channel1 12-bit left-aligned data B + 20 + 12 + + + + + DAC_DHR8R1 + DAC_DHR8R1 + DAC channel1 8-bit right aligned data holding register + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. + 0 + 8 + + + DACC1DHRB + DAC channel1 8-bit right-aligned data + 8 + 8 + + + + + DAC_DHR12R2 + DAC_DHR12R2 + DAC channel2 12-bit right aligned data holding register + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. + 0 + 12 + + + DACC2DHRB + DAC channel2 12-bit right-aligned data + 16 + 12 + + + + + DAC_DHR12L2 + DAC_DHR12L2 + DAC channel2 12-bit left aligned data holding register + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2. + 4 + 12 + + + DACC2DHRB + DAC channel2 12-bit left-aligned data B + 20 + 12 + + + + + DAC_DHR8R2 + DAC_DHR8R2 + DAC channel2 8-bit right-aligned data holding register + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. + 0 + 8 + + + DACC2DHRB + DAC channel2 8-bit right-aligned data + 8 + 8 + + + + + DAC_DHR12RD + DAC_DHR12RD + Dual DAC 12-bit right-aligned data holding register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. + 0 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. + 16 + 12 + + + + + DAC_DHR12LD + DAC_DHR12LD + DUAL DAC 12-bit left aligned data holding register + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. + 4 + 12 + + + DACC2DHR + DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. + 20 + 12 + + + + + DAC_DHR8RD + DAC_DHR8RD + DUAL DAC 8-bit right aligned data holding register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. + 0 + 8 + + + DACC2DHR + DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. + 8 + 8 + + + + + DAC_DOR1 + DAC_DOR1 + DAC channel1 data output register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. + 0 + 12 + + + DACC1DORB + DAC channel1 data output + 16 + 12 + + + + + DAC_DOR2 + DAC_DOR2 + DAC channel2 data output register + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output These bits are read-only, they contain data output for DAC channel2. + 0 + 12 + + + DACC2DORB + DAC channel2 data output + 16 + 12 + + + + + DAC_SR + DAC_SR + DAC status register + 0x34 + 0x20 + 0x00000000 + + + DAC1RDY + DAC channel1 ready status bit + 11 + 1 + read-write + + + DORSTAT1 + DAC channel1 output register status bit + 12 + 1 + read-write + + + DMAUDR1 + DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). + 13 + 1 + read-write + + + CAL_FLAG1 + DAC Channel 1 calibration offset status This bit is set and cleared by hardware + 14 + 1 + read-only + + + BWST1 + DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization). + 15 + 1 + read-only + + + DAC2RDY + DAC channel 2 ready status bit + 27 + 1 + read-write + + + DORSTAT2 + DAC channel 2 output register status bit + 28 + 1 + read-write + + + DMAUDR2 + DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). + 29 + 1 + read-write + + + CAL_FLAG2 + DAC Channel 2 calibration offset status This bit is set and cleared by hardware + 30 + 1 + read-only + + + BWST2 + DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). + 31 + 1 + read-only + + + + + DAC_CCR + DAC_CCR + DAC calibration control register + 0x38 + 0x20 + read-write + 0x00000000 + + + OTRIM1 + DAC Channel 1 offset trimming value + 0 + 5 + + + OTRIM2 + DAC Channel 2 offset trimming value + 16 + 5 + + + + + DAC_MCR + DAC_MCR + DAC mode control register + 0x3C + 0x20 + read-write + 0x00000000 + + + MODE1 + DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample &amp; hold mode + 0 + 3 + + + DMADOUBLE1 + DAC Channel1 DMA double data mode + 8 + 1 + + + SINFORMAT1 + Enable signed format for DAC channel1 + 9 + 1 + + + HFSEL + High frequency interface mode selection + 14 + 2 + + + MODE2 + DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample &amp; hold mode + 16 + 3 + + + DMADOUBLE2 + DAC Channel2 DMA double data mode + 24 + 1 + + + SINFORMAT2 + Enable signed format for DAC channel2 + 25 + 1 + + + + + DAC_SHSR1 + DAC_SHSR1 + DAC Sample and Hold sample time register 1 + 0x40 + 0x20 + read-write + 0x00000000 + + + TSAMPLE1 + DAC Channel 1 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored. + 0 + 10 + + + + + DAC_SHSR2 + DAC_SHSR2 + DAC Sample and Hold sample time register 2 + 0x44 + 0x20 + read-write + 0x00000000 + + + TSAMPLE2 + DAC Channel 2 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored. + 0 + 10 + + + + + DAC_SHHR + DAC_SHHR + DAC Sample and Hold hold time register + 0x48 + 0x20 + read-write + 0x00010001 + + + THOLD1 + DAC Channel 1 hold Time (only valid in sample &amp; hold mode) Hold time= (THOLD[9:0]) x T LSI + 0 + 10 + + + THOLD2 + DAC Channel 2 hold time (only valid in sample &amp; hold mode). Hold time= (THOLD[9:0]) x T LSI + 16 + 10 + + + + + DAC_SHRR + DAC_SHRR + DAC Sample and Hold refresh time register + 0x4C + 0x20 + read-write + 0x00010001 + + + TREFRESH1 + DAC Channel 1 refresh Time (only valid in sample &amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI + 0 + 8 + + + TREFRESH2 + DAC Channel 2 refresh Time (only valid in sample &amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI + 16 + 8 + + + + + DAC_STR1 + DAC_STR1 + Sawtooth register + 0x58 + 0x20 + read-write + 0x00000000 + + + STRSTDATA1 + DAC Channel 1 Sawtooth reset value + 0 + 12 + + + STDIR1 + DAC Channel1 Sawtooth direction setting + 12 + 1 + + + STINCDATA1 + DAC CH1 Sawtooth increment value (12.4 bit format) + 16 + 16 + + + + + DAC_STR2 + DAC_STR2 + Sawtooth register + 0x5C + 0x20 + read-write + 0x00000000 + + + STRSTDATA2 + DAC Channel 2 Sawtooth reset value + 0 + 12 + + + STDIR2 + DAC Channel2 Sawtooth direction setting + 12 + 1 + + + STINCDATA2 + DAC CH2 Sawtooth increment value (12.4 bit format) + 16 + 16 + + + + + DAC_STMODR + DAC_STMODR + Sawtooth Mode register + 0x60 + 0x20 + read-write + 0x00000000 + + + STRSTTRIGSEL1 + DAC Channel 1 Sawtooth Reset trigger selection + 0 + 4 + + + STINCTRIGSEL1 + DAC Channel 1 Sawtooth Increment trigger selection + 8 + 4 + + + STRSTTRIGSEL2 + DAC Channel 1 Sawtooth Reset trigger selection + 16 + 4 + + + STINCTRIGSEL2 + DAC Channel 2 Sawtooth Increment trigger selection + 24 + 4 + + + + + + + DAC2 + 0x50000C00 + + + DAC3 + 0x50001000 + + + DAC4 + 0x50001400 + + + ADC1 + Analog-to-Digital Converter + ADC + 0x50000000 + + 0x0 + 0xD0 + registers + + + ADC1_2 + ADC1 and ADC2 global interrupt + 18 + + + + ISR + ISR + interrupt and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + JQOVF + JQOVF + 10 + 1 + + + AWD3 + AWD3 + 9 + 1 + + + AWD2 + AWD2 + 8 + 1 + + + AWD1 + AWD1 + 7 + 1 + + + JEOS + JEOS + 6 + 1 + + + JEOC + JEOC + 5 + 1 + + + OVR + OVR + 4 + 1 + + + EOS + EOS + 3 + 1 + + + EOC + EOC + 2 + 1 + + + EOSMP + EOSMP + 1 + 1 + + + ADRDY + ADRDY + 0 + 1 + + + + + IER + IER + interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + JQOVFIE + JQOVFIE + 10 + 1 + + + AWD3IE + AWD3IE + 9 + 1 + + + AWD2IE + AWD2IE + 8 + 1 + + + AWD1IE + AWD1IE + 7 + 1 + + + JEOSIE + JEOSIE + 6 + 1 + + + JEOCIE + JEOCIE + 5 + 1 + + + OVRIE + OVRIE + 4 + 1 + + + EOSIE + EOSIE + 3 + 1 + + + EOCIE + EOCIE + 2 + 1 + + + EOSMPIE + EOSMPIE + 1 + 1 + + + ADRDYIE + ADRDYIE + 0 + 1 + + + + + CR + CR + control register + 0x8 + 0x20 + read-write + 0x20000000 + + + ADCAL + ADCAL + 31 + 1 + + + ADCALDIF + ADCALDIF + 30 + 1 + + + DEEPPWD + DEEPPWD + 29 + 1 + + + ADVREGEN + ADVREGEN + 28 + 1 + + + JADSTP + JADSTP + 5 + 1 + + + ADSTP + ADSTP + 4 + 1 + + + JADSTART + JADSTART + 3 + 1 + + + ADSTART + ADSTART + 2 + 1 + + + ADDIS + ADDIS + 1 + 1 + + + ADEN + ADEN + 0 + 1 + + + + + CFGR + CFGR + configuration register + 0xC + 0x20 + read-write + 0x80000000 + + + JQDIS + Injected Queue disable + 31 + 1 + + + AWD1CH + Analog watchdog 1 channel selection + 26 + 5 + + + JAUTO + JAUTO + 25 + 1 + + + JAWD1EN + JAWD1EN + 24 + 1 + + + AWD1EN + AWD1EN + 23 + 1 + + + AWD1SGL + AWD1SGL + 22 + 1 + + + JQM + JQM + 21 + 1 + + + JDISCEN + JDISCEN + 20 + 1 + + + DISCNUM + DISCNUM + 17 + 3 + + + DISCEN + DISCEN + 16 + 1 + + + ALIGN + ALIGN + 15 + 1 + + + AUTDLY + AUTDLY + 14 + 1 + + + CONT + CONT + 13 + 1 + + + OVRMOD + OVRMOD + 12 + 1 + + + EXTEN + EXTEN + 10 + 2 + + + EXTSEL + External trigger selection for regular group + 5 + 5 + + + RES + RES + 3 + 2 + + + DMACFG + DMACFG + 1 + 1 + + + DMAEN + DMAEN + 0 + 1 + + + + + CFGR2 + CFGR2 + configuration register + 0x10 + 0x20 + read-write + 0x00000000 + + + SMPTRIG + SMPTRIG + 27 + 1 + + + BULB + BULB + 26 + 1 + + + SWTRIG + SWTRIG + 25 + 1 + + + GCOMP + GCOMP + 16 + 1 + + + ROVSM + EXTEN + 10 + 1 + + + TROVS + Triggered Regular Oversampling + 9 + 1 + + + OVSS + ALIGN + 5 + 4 + + + OVSR + RES + 2 + 3 + + + JOVSE + DMACFG + 1 + 1 + + + ROVSE + DMAEN + 0 + 1 + + + + + SMPR1 + SMPR1 + sample time register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + SMP9 + SMP9 + 27 + 3 + + + SMP8 + SMP8 + 24 + 3 + + + SMP7 + SMP7 + 21 + 3 + + + SMP6 + SMP6 + 18 + 3 + + + SMP5 + SMP5 + 15 + 3 + + + SMP4 + SMP4 + 12 + 3 + + + SMP3 + SMP3 + 9 + 3 + + + SMP2 + SMP2 + 6 + 3 + + + SMP1 + SMP1 + 3 + 3 + + + SMPPLUS + Addition of one clock cycle to the sampling time + 31 + 1 + + + SMP0 + SMP0 + 0 + 3 + + + + + SMPR2 + SMPR2 + sample time register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + SMP18 + SMP18 + 24 + 3 + + + SMP17 + SMP17 + 21 + 3 + + + SMP16 + SMP16 + 18 + 3 + + + SMP15 + SMP15 + 15 + 3 + + + SMP14 + SMP14 + 12 + 3 + + + SMP13 + SMP13 + 9 + 3 + + + SMP12 + SMP12 + 6 + 3 + + + SMP11 + SMP11 + 3 + 3 + + + SMP10 + SMP10 + 0 + 3 + + + + + TR1 + TR1 + watchdog threshold register 1 + 0x20 + 0x20 + read-write + 0x0FFF0000 + + + HT1 + HT1 + 16 + 12 + + + AWDFILT + AWDFILT + 12 + 3 + + + LT1 + LT1 + 0 + 12 + + + + + TR2 + TR2 + watchdog threshold register + 0x24 + 0x20 + read-write + 0x00FF0000 + + + HT2 + HT2 + 16 + 8 + + + LT2 + LT2 + 0 + 8 + + + + + TR3 + TR3 + watchdog threshold register 3 + 0x28 + 0x20 + read-write + 0x00FF0000 + + + HT3 + HT3 + 16 + 8 + + + LT3 + LT3 + 0 + 8 + + + + + SQR1 + SQR1 + regular sequence register 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ4 + SQ4 + 24 + 5 + + + SQ3 + SQ3 + 18 + 5 + + + SQ2 + SQ2 + 12 + 5 + + + SQ1 + SQ1 + 6 + 5 + + + L + Regular channel sequence length + 0 + 4 + + + + + SQR2 + SQR2 + regular sequence register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ9 + SQ9 + 24 + 5 + + + SQ8 + SQ8 + 18 + 5 + + + SQ7 + SQ7 + 12 + 5 + + + SQ6 + SQ6 + 6 + 5 + + + SQ5 + SQ5 + 0 + 5 + + + + + SQR3 + SQR3 + regular sequence register 3 + 0x38 + 0x20 + read-write + 0x00000000 + + + SQ14 + SQ14 + 24 + 5 + + + SQ13 + SQ13 + 18 + 5 + + + SQ12 + SQ12 + 12 + 5 + + + SQ11 + SQ11 + 6 + 5 + + + SQ10 + SQ10 + 0 + 5 + + + + + SQR4 + SQR4 + regular sequence register 4 + 0x3C + 0x20 + read-write + 0x00000000 + + + SQ16 + SQ16 + 6 + 5 + + + SQ15 + SQ15 + 0 + 5 + + + + + DR + DR + regular Data Register + 0x40 + 0x20 + read-only + 0x00000000 + + + RDATA + Regular Data converted + 0 + 16 + + + + + JSQR + JSQR + injected sequence register + 0x4C + 0x20 + read-write + 0x00000000 + + + JSQ4 + JSQ4 + 27 + 5 + + + JSQ3 + JSQ3 + 21 + 5 + + + JSQ2 + JSQ2 + 15 + 5 + + + JSQ1 + JSQ1 + 9 + 5 + + + JEXTEN + JEXTEN + 7 + 2 + + + JEXTSEL + JEXTSEL + 2 + 5 + + + JL + JL + 0 + 2 + + + + + OFR1 + OFR1 + offset register 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + OFR2 + OFR2 + offset register 2 + 0x64 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + OFR3 + OFR3 + offset register 3 + 0x68 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + OFR4 + OFR4 + offset register 4 + 0x6C + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + JDR1 + JDR1 + injected data register 1 + 0x80 + 0x20 + read-only + 0x00000000 + + + JDATA1 + JDATA1 + 0 + 16 + + + + + JDR2 + JDR2 + injected data register 2 + 0x84 + 0x20 + read-only + 0x00000000 + + + JDATA2 + JDATA2 + 0 + 16 + + + + + JDR3 + JDR3 + injected data register 3 + 0x88 + 0x20 + read-only + 0x00000000 + + + JDATA3 + JDATA3 + 0 + 16 + + + + + JDR4 + JDR4 + injected data register 4 + 0x8C + 0x20 + read-only + 0x00000000 + + + JDATA4 + JDATA4 + 0 + 16 + + + + + AWD2CR + AWD2CR + Analog Watchdog 2 Configuration Register + 0xA0 + 0x20 + read-write + 0x00000000 + + + AWD2CH + AWD2CH + 0 + 19 + + + + + AWD3CR + AWD3CR + Analog Watchdog 3 Configuration Register + 0xA4 + 0x20 + read-write + 0x00000000 + + + AWD3CH + AWD3CH + 0 + 19 + + + + + DIFSEL + DIFSEL + Differential Mode Selection Register 2 + 0xB0 + 0x20 + 0x00000000 + + + DIFSEL_0 + Differential mode for channels 0 + 0 + 1 + read-only + + + DIFSEL_1_18 + Differential mode for channels 15 to 1 + 1 + 18 + read-write + + + + + CALFACT + CALFACT + Calibration Factors + 0xB4 + 0x20 + read-write + 0x00000000 + + + CALFACT_D + CALFACT_D + 16 + 7 + + + CALFACT_S + CALFACT_S + 0 + 7 + + + + + GCOMP + GCOMP + Gain compensation Register + 0xC0 + 0x20 + read-write + 0x00000000 + + + GCOMPCOEFF + GCOMPCOEFF + 0 + 14 + + + + + + + ADC2 + 0x50000100 + + + ADC12_Common + Analog-to-Digital Converter + ADC + 0x50000300 + + 0x0 + 0x11 + registers + + + + CSR + CSR + ADC Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + ADDRDY_MST + ADDRDY_MST + 0 + 1 + + + EOSMP_MST + EOSMP_MST + 1 + 1 + + + EOC_MST + EOC_MST + 2 + 1 + + + EOS_MST + EOS_MST + 3 + 1 + + + OVR_MST + OVR_MST + 4 + 1 + + + JEOC_MST + JEOC_MST + 5 + 1 + + + JEOS_MST + JEOS_MST + 6 + 1 + + + AWD1_MST + AWD1_MST + 7 + 1 + + + AWD2_MST + AWD2_MST + 8 + 1 + + + AWD3_MST + AWD3_MST + 9 + 1 + + + JQOVF_MST + JQOVF_MST + 10 + 1 + + + ADRDY_SLV + ADRDY_SLV + 16 + 1 + + + EOSMP_SLV + EOSMP_SLV + 17 + 1 + + + EOC_SLV + End of regular conversion of the slave ADC + 18 + 1 + + + EOS_SLV + End of regular sequence flag of the slave ADC + 19 + 1 + + + OVR_SLV + Overrun flag of the slave ADC + 20 + 1 + + + JEOC_SLV + End of injected conversion flag of the slave ADC + 21 + 1 + + + JEOS_SLV + End of injected sequence flag of the slave ADC + 22 + 1 + + + AWD1_SLV + Analog watchdog 1 flag of the slave ADC + 23 + 1 + + + AWD2_SLV + Analog watchdog 2 flag of the slave ADC + 24 + 1 + + + AWD3_SLV + Analog watchdog 3 flag of the slave ADC + 25 + 1 + + + JQOVF_SLV + Injected Context Queue Overflow flag of the slave ADC + 26 + 1 + + + + + CCR + CCR + ADC common control register + 0x8 + 0x20 + read-write + 0x00000000 + + + DUAL + Dual ADC mode selection + 0 + 5 + + + DELAY + Delay between 2 sampling phases + 8 + 4 + + + DMACFG + DMA configuration (for multi-ADC mode) + 13 + 1 + + + MDMA + Direct memory access mode for multi ADC mode + 14 + 2 + + + CKMODE + ADC clock mode + 16 + 2 + + + VREFEN + VREFINT enable + 22 + 1 + + + VSENSESEL + VTS selection + 23 + 1 + + + VBATSEL + VBAT selection + 24 + 1 + + + PRESC + ADC prescaler + 18 + 4 + + + + + CDR + CDR + ADC common regular data register for dual and triple modes + 0xC + 0x20 + read-only + 0x00000000 + + + RDATA_SLV + Regular data of the slave ADC + 16 + 16 + + + RDATA_MST + Regular data of the master ADC + 0 + 16 + + + + + + + ADC345_Common + 0x50000700 + + + FMAC + Filter Math Accelerator + FMAC + 0x40021400 + + 0x0 + 0xC00 + registers + + + FMAC + FMAC + 101 + + + + X1BUFCFG + X1BUFCFG + FMAC X1 Buffer Configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + X1_BASE + X1_BASE + 0 + 8 + + + X1_BUF_SIZE + X1_BUF_SIZE + 8 + 8 + + + FULL_WM + FULL_WM + 24 + 2 + + + + + X2BUFCFG + X2BUFCFG + FMAC X2 Buffer Configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + X2_BASE + X1_BASE + 0 + 8 + + + X2_BUF_SIZE + X1_BUF_SIZE + 8 + 8 + + + + + YBUFCFG + YBUFCFG + FMAC Y Buffer Configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + Y_BASE + X1_BASE + 0 + 8 + + + Y_BUF_SIZE + X1_BUF_SIZE + 8 + 8 + + + EMPTY_WM + EMPTY_WM + 24 + 2 + + + + + PARAM + PARAM + FMAC Parameter register + 0xC + 0x20 + read-write + 0x00000000 + + + START + START + 31 + 1 + + + FUNC + FUNC + 24 + 7 + + + R + R + 16 + 8 + + + Q + Q + 8 + 8 + + + P + P + 0 + 8 + + + + + CR + CR + FMAC Control register + 0x10 + 0x20 + read-write + 0x00000000 + + + RESET + RESET + 16 + 1 + + + CLIPEN + CLIPEN + 15 + 1 + + + DMAWEN + DMAWEN + 9 + 1 + + + DMAREN + DMAREN + 8 + 1 + + + SATIEN + SATIEN + 4 + 1 + + + UNFLIEN + UNFLIEN + 3 + 1 + + + OVFLIEN + OVFLIEN + 2 + 1 + + + WIEN + WIEN + 1 + 1 + + + RIEN + RIEN + 0 + 1 + + + + + SR + SR + FMAC Status register + 0x14 + 0x20 + read-only + 0x00000000 + + + YEMPTY + YEMPTY + 0 + 1 + + + X1FULL + X1FULL + 1 + 1 + + + OVFL + OVFL + 8 + 1 + + + UNFL + UNFL + 9 + 1 + + + SAT + SAT + 10 + 1 + + + + + WDATA + WDATA + FMAC Write Data register + 0x18 + 0x20 + write-only + 0x00000000 + + + WDATA + WDATA + 0 + 16 + + + + + RDATA + RDATA + FMAC Read Data register + 0x1C + 0x20 + read-only + 0x00000000 + + + RDATA + RDATA + 0 + 16 + + + + + + + CORDIC + CORDIC Co-processor + CORDIC + 0x40020C00 + + 0x0 + 0x400 + registers + + + Cordic + Cordic + 100 + + + + CSR + CSR + CORDIC Control Status register + 0x0 + 0x20 + read-write + 0x00000000 + + + FUNC + FUNC + 0 + 4 + + + PRECISION + PRECISION + 4 + 4 + + + SCALE + SCALE + 8 + 3 + + + IEN + IEN + 16 + 1 + + + DMAREN + DMAREN + 17 + 1 + + + DMAWEN + DMAWEN + 18 + 1 + + + NRES + NRES + 19 + 1 + + + NARGS + NARGS + 20 + 1 + + + RESSIZE + RESSIZE + 21 + 1 + + + ARGSIZE + ARGSIZE + 22 + 1 + + + RRDY + RRDY + 31 + 1 + + + + + WDATA + WDATA + FMAC Write Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + ARG + ARG + 0 + 32 + + + + + RDATA + RDATA + FMAC Read Data register + 0x8 + 0x20 + read-only + 0x00000000 + + + RES + RES + 0 + 32 + + + + + + + SAI + Serial audio interface + SAI + 0x40015400 + + 0x0 + 0x400 + registers + + + SAI + SAI + 76 + + + + BCR1 + BCR1 + BConfiguration register 1 + 0x24 + 0x20 + read-write + 0x00000040 + + + MCKEN + MCKEN + 27 + 1 + + + OSR + OSR + 26 + 1 + + + MCJDIV + Master clock divider + 20 + 6 + + + NODIV + No divider + 19 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + SAIBEN + Audio block B enable + 16 + 1 + + + OutDri + Output drive + 13 + 1 + + + MONO + Mono mode + 12 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + CKSTR + Clock strobing edge + 9 + 1 + + + LSBFIRST + Least significant bit first + 8 + 1 + + + DS + Data size + 5 + 3 + + + PRTCFG + Protocol configuration + 2 + 2 + + + MODE + Audio block mode + 0 + 2 + + + + + BCR2 + BCR2 + BConfiguration register 2 + 0x28 + 0x20 + read-write + 0x00000000 + + + COMP + Companding mode + 14 + 2 + + + CPL + Complement bit + 13 + 1 + + + MUTECN + Mute counter + 7 + 6 + + + MUTEVAL + Mute value + 6 + 1 + + + MUTE + Mute + 5 + 1 + + + TRIS + Tristate management on data line + 4 + 1 + + + FFLUS + FIFO flush + 3 + 1 + + + FTH + FIFO threshold + 0 + 3 + + + + + BFRCR + BFRCR + BFRCR + 0x2C + 0x20 + read-write + 0x00000007 + + + FSOFF + Frame synchronization offset + 18 + 1 + + + FSPOL + Frame synchronization polarity + 17 + 1 + + + FSDEF + Frame synchronization definition + 16 + 1 + + + FSALL + Frame synchronization active level length + 8 + 7 + + + FRL + Frame length + 0 + 8 + + + + + BSLOTR + BSLOTR + BSlot register + 0x30 + 0x20 + read-write + 0x00000000 + + + SLOTEN + Slot enable + 16 + 16 + + + NBSLOT + Number of slots in an audio frame + 8 + 4 + + + SLOTSZ + Slot size + 6 + 2 + + + FBOFF + First bit offset + 0 + 5 + + + + + BIM + BIM + BInterrupt mask register2 + 0x34 + 0x20 + read-write + 0x00000000 + + + LFSDETIE + Late frame synchronization detection interrupt enable + 6 + 1 + + + AFSDETIE + Anticipated frame synchronization detection interrupt enable + 5 + 1 + + + CNRDYIE + Codec not ready interrupt enable + 4 + 1 + + + FREQIE + FIFO request interrupt enable + 3 + 1 + + + WCKCFG + Wrong clock configuration interrupt enable + 2 + 1 + + + MUTEDET + Mute detection interrupt enable + 1 + 1 + + + OVRUDRIE + Overrun/underrun interrupt enable + 0 + 1 + + + + + BSR + BSR + BStatus register + 0x38 + 0x20 + read-only + 0x00000000 + + + FLVL + FIFO level threshold + 16 + 3 + + + LFSDET + Late frame synchronization detection + 6 + 1 + + + AFSDET + Anticipated frame synchronization detection + 5 + 1 + + + CNRDY + Codec not ready + 4 + 1 + + + FREQ + FIFO request + 3 + 1 + + + WCKCFG + Wrong clock configuration flag + 2 + 1 + + + MUTEDET + Mute detection + 1 + 1 + + + OVRUDR + Overrun / underrun + 0 + 1 + + + + + BCLRFR + BCLRFR + BClear flag register + 0x3C + 0x20 + write-only + 0x00000000 + + + LFSDET + Clear late frame synchronization detection flag + 6 + 1 + + + CAFSDET + Clear anticipated frame synchronization detection flag + 5 + 1 + + + CNRDY + Clear codec not ready flag + 4 + 1 + + + WCKCFG + Clear wrong clock configuration flag + 2 + 1 + + + MUTEDET + Mute detection flag + 1 + 1 + + + OVRUDR + Clear overrun / underrun + 0 + 1 + + + + + BDR + BDR + BData register + 0x40 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + ACR1 + ACR1 + AConfiguration register 1 + 0x4 + 0x20 + read-write + 0x00000040 + + + MCKEN + MCKEN + 27 + 1 + + + OSR + OSR + 26 + 1 + + + MCJDIV + Master clock divider + 20 + 6 + + + NODIV + No divider + 19 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + SAIAEN + Audio block A enable + 16 + 1 + + + OutDri + Output drive + 13 + 1 + + + MONO + Mono mode + 12 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + CKSTR + Clock strobing edge + 9 + 1 + + + LSBFIRST + Least significant bit first + 8 + 1 + + + DS + Data size + 5 + 3 + + + PRTCFG + Protocol configuration + 2 + 2 + + + MODE + Audio block mode + 0 + 2 + + + + + ACR2 + ACR2 + AConfiguration register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + COMP + Companding mode + 14 + 2 + + + CPL + Complement bit + 13 + 1 + + + MUTECN + Mute counter + 7 + 6 + + + MUTEVAL + Mute value + 6 + 1 + + + MUTE + Mute + 5 + 1 + + + TRIS + Tristate management on data line + 4 + 1 + + + FFLUS + FIFO flush + 3 + 1 + + + FTH + FIFO threshold + 0 + 3 + + + + + AFRCR + AFRCR + AFRCR + 0xC + 0x20 + read-write + 0x00000007 + + + FSOFF + Frame synchronization offset + 18 + 1 + + + FSPOL + Frame synchronization polarity + 17 + 1 + + + FSDEF + Frame synchronization definition + 16 + 1 + + + FSALL + Frame synchronization active level length + 8 + 7 + + + FRL + Frame length + 0 + 8 + + + + + ASLOTR + ASLOTR + ASlot register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLOTEN + Slot enable + 16 + 16 + + + NBSLOT + Number of slots in an audio frame + 8 + 4 + + + SLOTSZ + Slot size + 6 + 2 + + + FBOFF + First bit offset + 0 + 5 + + + + + AIM + AIM + AInterrupt mask register2 + 0x14 + 0x20 + read-write + 0x00000000 + + + LFSDET + Late frame synchronization detection interrupt enable + 6 + 1 + + + AFSDETIE + Anticipated frame synchronization detection interrupt enable + 5 + 1 + + + CNRDYIE + Codec not ready interrupt enable + 4 + 1 + + + FREQIE + FIFO request interrupt enable + 3 + 1 + + + WCKCFG + Wrong clock configuration interrupt enable + 2 + 1 + + + MUTEDET + Mute detection interrupt enable + 1 + 1 + + + OVRUDRIE + Overrun/underrun interrupt enable + 0 + 1 + + + + + ASR + ASR + AStatus register + 0x18 + 0x20 + read-write + 0x00000000 + + + FLVL + FIFO level threshold + 16 + 3 + + + LFSDET + Late frame synchronization detection + 6 + 1 + + + AFSDET + Anticipated frame synchronization detection + 5 + 1 + + + CNRDY + Codec not ready + 4 + 1 + + + FREQ + FIFO request + 3 + 1 + + + WCKCFG + Wrong clock configuration flag. This bit is read only + 2 + 1 + + + MUTEDET + Mute detection + 1 + 1 + + + OVRUDR + Overrun / underrun + 0 + 1 + + + + + ACLRFR + ACLRFR + AClear flag register + 0x1C + 0x20 + read-write + 0x00000000 + + + LFSDET + Clear late frame synchronization detection flag + 6 + 1 + + + CAFSDET + Clear anticipated frame synchronization detection flag + 5 + 1 + + + CNRDY + Clear codec not ready flag + 4 + 1 + + + WCKCFG + Clear wrong clock configuration flag + 2 + 1 + + + MUTEDET + Mute detection flag + 1 + 1 + + + OVRUDR + Clear overrun / underrun + 0 + 1 + + + + + ADR + ADR + AData register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + PDMCR + PDMCR + PDM control register + 0x44 + 0x20 + read-write + 0x00000000 + + + PDMEN + PDMEN + 0 + 1 + + + MICNBR + MICNBR + 4 + 2 + + + CKEN1 + CKEN1 + 8 + 1 + + + CKEN2 + CKEN2 + 9 + 1 + + + CKEN3 + CKEN3 + 10 + 1 + + + CKEN4 + CKEN4 + 11 + 1 + + + + + PDMDLY + PDMDLY + PDM delay register + 0x48 + 0x20 + read-write + 0x00000000 + + + DLYM1L + DLYM1L + 0 + 3 + + + DLYM1R + DLYM1R + 4 + 3 + + + DLYM2L + DLYM2L + 8 + 3 + + + DLYM2R + DLYM2R + 12 + 3 + + + DLYM3L + DLYM3L + 16 + 3 + + + DLYM3R + DLYM3R + 20 + 3 + + + DLYM4L + DLYM4L + 24 + 3 + + + DLYM4R + DLYM4R + 28 + 3 + + + + + + + TAMP + Tamper and backup registers + TAMP + 0x40002400 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0xFFFF0000 + + + TAMP1E + TAMP1E + 0 + 1 + + + TAMP2E + TAMP2E + 1 + 1 + + + TAMP3E + TAMP2E + 2 + 1 + + + ITAMP3E + ITAMP3E + 18 + 1 + + + ITAMP4E + ITAMP4E + 19 + 1 + + + ITAMP5E + ITAMP5E + 20 + 1 + + + ITAMP6E + ITAMP6E + 21 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + TAMP1NOER + TAMP1NOER + 0 + 1 + + + TAMP2NOER + TAMP2NOER + 1 + 1 + + + TAMP3NOER + TAMP3NOER + 2 + 1 + + + TAMP1MSK + TAMP1MSK + 16 + 1 + + + TAMP2MSK + TAMP2MSK + 17 + 1 + + + TAMP3MSK + TAMP3MSK + 18 + 1 + + + TAMP1TRG + TAMP1TRG + 24 + 1 + + + TAMP2TRG + TAMP2TRG + 25 + 1 + + + TAMP3TRG + TAMP3TRG + 26 + 1 + + + + + FLTCR + FLTCR + TAMP filter control register + 0xC + 0x20 + read-write + 0x00000000 + + + TAMPFREQ + TAMPFREQ + 0 + 3 + + + TAMPFLT + TAMPFLT + 3 + 2 + + + TAMPPRCH + TAMPPRCH + 5 + 2 + + + TAMPPUDIS + TAMPPUDIS + 7 + 1 + + + + + IER + IER + TAMP interrupt enable register + 0x2C + 0x20 + read-write + 0x00000000 + + + TAMP1IE + TAMP1IE + 0 + 1 + + + TAMP2IE + TAMP2IE + 1 + 1 + + + TAMP3IE + TAMP3IE + 2 + 1 + + + ITAMP3IE + ITAMP3IE + 18 + 1 + + + ITAMP4IE + ITAMP4IE + 19 + 1 + + + ITAMP5IE + ITAMP5IE + 20 + 1 + + + ITAMP6IE + ITAMP6IE + 21 + 1 + + + + + SR + SR + TAMP status register + 0x30 + 0x20 + read-only + 0x00000000 + + + TAMP1F + TAMP1F + 0 + 1 + + + TAMP2F + TAMP2F + 1 + 1 + + + TAMP3F + TAMP3F + 2 + 1 + + + ITAMP3F + ITAMP3F + 18 + 1 + + + ITAMP4F + ITAMP4F + 19 + 1 + + + ITAMP5F + ITAMP5F + 20 + 1 + + + ITAMP6F + ITAMP6F + 21 + 1 + + + + + MISR + MISR + TAMP masked interrupt status register + 0x34 + 0x20 + read-only + 0x00000000 + + + TAMP1MF + TAMP1MF: + 0 + 1 + + + TAMP2MF + TAMP2MF + 1 + 1 + + + TAMP3MF + TAMP3MF + 2 + 1 + + + ITAMP3MF + ITAMP3MF + 18 + 1 + + + ITAMP4MF + ITAMP4MF + 19 + 1 + + + ITAMP5MF + ITAMP5MF + 20 + 1 + + + ITAMP6MF + ITAMP6MF + 21 + 1 + + + + + SCR + SCR + TAMP status clear register + 0x3C + 0x20 + read-write + 0x00000000 + + + CTAMP1F + CTAMP1F + 0 + 1 + + + CTAMP2F + CTAMP2F + 1 + 1 + + + CTAMP3F + CTAMP3F + 2 + 1 + + + CITAMP3F + CITAMP3F + 18 + 1 + + + CITAMP4F + CITAMP4F + 19 + 1 + + + CITAMP5F + CITAMP5F + 20 + 1 + + + CITAMP6F + CITAMP6F + 21 + 1 + + + + + BKP0R + BKP0R + TAMP backup register + 0x100 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP1R + BKP1R + TAMP backup register + 0x104 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP2R + BKP2R + TAMP backup register + 0x108 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP3R + BKP3R + TAMP backup register + 0x10C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP4R + BKP4R + TAMP backup register + 0x110 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP5R + BKP5R + TAMP backup register + 0x114 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP6R + BKP6R + TAMP backup register + 0x118 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP7R + BKP7R + TAMP backup register + 0x11C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP8R + BKP8R + TAMP backup register + 0x120 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP9R + BKP9R + TAMP backup register + 0x124 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP10R + BKP10R + TAMP backup register + 0x128 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP11R + BKP11R + TAMP backup register + 0x12C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP12R + BKP12R + TAMP backup register + 0x130 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP13R + BKP13R + TAMP backup register + 0x134 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP14R + BKP14R + TAMP backup register + 0x138 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP15R + BKP15R + TAMP backup register + 0x13C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP16R + BKP16R + TAMP backup register + 0x140 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP17R + BKP17R + TAMP backup register + 0x144 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP18R + BKP18R + TAMP backup register + 0x148 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP19R + BKP19R + TAMP backup register + 0x14C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP20R + BKP20R + TAMP backup register + 0x150 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP21R + BKP21R + TAMP backup register + 0x154 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP22R + BKP22R + TAMP backup register + 0x158 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP23R + BKP23R + TAMP backup register + 0x15C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP24R + BKP24R + TAMP backup register + 0x160 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP25R + BKP25R + TAMP backup register + 0x164 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP26R + BKP26R + TAMP backup register + 0x168 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP27R + BKP27R + TAMP backup register + 0x16C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP28R + BKP28R + TAMP backup register + 0x170 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP29R + BKP29R + TAMP backup register + 0x174 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP30R + BKP30R + TAMP backup register + 0x178 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP31R + BKP31R + TAMP backup register + 0x17C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + + + FPU + Floting point unit + FPU + 0xE000EF34 + + 0x0 + 0xD + registers + + + FPU + Floating point unit interrupt + 81 + + + + FPCCR + FPCCR + Floating-point context control register + 0x0 + 0x20 + read-write + 0x00000000 + + + LSPACT + LSPACT + 0 + 1 + + + USER + USER + 1 + 1 + + + THREAD + THREAD + 3 + 1 + + + HFRDY + HFRDY + 4 + 1 + + + MMRDY + MMRDY + 5 + 1 + + + BFRDY + BFRDY + 6 + 1 + + + MONRDY + MONRDY + 8 + 1 + + + LSPEN + LSPEN + 30 + 1 + + + ASPEN + ASPEN + 31 + 1 + + + + + FPCAR + FPCAR + Floating-point context address register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Location of unpopulated floating-point + 3 + 29 + + + + + FPSCR + FPSCR + Floating-point status control register + 0x8 + 0x20 + read-write + 0x00000000 + + + IOC + Invalid operation cumulative exception bit + 0 + 1 + + + DZC + Division by zero cumulative exception bit. + 1 + 1 + + + OFC + Overflow cumulative exception bit + 2 + 1 + + + UFC + Underflow cumulative exception bit + 3 + 1 + + + IXC + Inexact cumulative exception bit + 4 + 1 + + + IDC + Input denormal cumulative exception bit. + 7 + 1 + + + RMode + Rounding Mode control field + 22 + 2 + + + FZ + Flush-to-zero mode control bit: + 24 + 1 + + + DN + Default NaN mode control bit + 25 + 1 + + + AHP + Alternative half-precision control bit + 26 + 1 + + + V + Overflow condition code flag + 28 + 1 + + + C + Carry condition code flag + 29 + 1 + + + Z + Zero condition code flag + 30 + 1 + + + N + Negative condition code flag + 31 + 1 + + + + + + + MPU + Memory protection unit + MPU + 0xE000E084 + + 0x0 + 0x15 + registers + + + + TYPER + TYPER + MPU type register + 0x0 + 0x20 + read-only + 0X00000800 + + + SEPARATE + Separate flag + 0 + 1 + + + DREGION + Number of MPU data regions + 8 + 8 + + + IREGION + Number of MPU instruction regions + 16 + 8 + + + + + CTRL + CTRL + MPU control register + 0x4 + 0x20 + read-write + 0X00000000 + + + ENABLE + Enables the MPU + 0 + 1 + + + HFNMIENA + Enables the operation of MPU during hard fault + 1 + 1 + + + PRIVDEFENA + Enable priviliged software access to default memory map + 2 + 1 + + + + + RNR + RNR + MPU region number register + 0x8 + 0x20 + read-write + 0X00000000 + + + REGION + MPU region + 0 + 8 + + + + + RBAR + RBAR + MPU region base address register + 0xC + 0x20 + read-write + 0X00000000 + + + REGION + MPU region field + 0 + 4 + + + VALID + MPU region number valid + 4 + 1 + + + ADDR + Region base address field + 5 + 27 + + + + + RASR + RASR + MPU region attribute and size register + 0x10 + 0x20 + read-write + 0X00000000 + + + ENABLE + Region enable bit. + 0 + 1 + + + SIZE + Size of the MPU protection region + 1 + 5 + + + SRD + Subregion disable bits + 8 + 8 + + + B + memory attribute + 16 + 1 + + + C + memory attribute + 17 + 1 + + + S + Shareable memory attribute + 18 + 1 + + + TEX + memory attribute + 19 + 3 + + + AP + Access permission + 24 + 3 + + + XN + Instruction access disable bit + 28 + 1 + + + + + + + STK + SysTick timer + STK + 0xE000E010 + + 0x0 + 0x11 + registers + + + + CTRL + CTRL + SysTick control and status register + 0x0 + 0x20 + read-write + 0X00000000 + + + ENABLE + Counter enable + 0 + 1 + + + TICKINT + SysTick exception request enable + 1 + 1 + + + CLKSOURCE + Clock source selection + 2 + 1 + + + COUNTFLAG + COUNTFLAG + 16 + 1 + + + + + LOAD + LOAD + SysTick reload value register + 0x4 + 0x20 + read-write + 0X00000000 + + + RELOAD + RELOAD value + 0 + 24 + + + + + VAL + VAL + SysTick current value register + 0x8 + 0x20 + read-write + 0X00000000 + + + CURRENT + Current counter value + 0 + 24 + + + + + CALIB + CALIB + SysTick calibration value register + 0xC + 0x20 + read-write + 0X00000000 + + + TENMS + Calibration value + 0 + 24 + + + SKEW + SKEW flag: Indicates whether the TENMS value is exact + 30 + 1 + + + NOREF + NOREF flag. Reads as zero + 31 + 1 + + + + + + + SCB + System control block + SCB + 0xE000ED00 + + 0x0 + 0x41 + registers + + + + CPUID + CPUID + CPUID base register + 0x0 + 0x20 + read-only + 0x410FC241 + + + Revision + Revision number + 0 + 4 + + + PartNo + Part number of the processor + 4 + 12 + + + Constant + Reads as 0xF + 16 + 4 + + + Variant + Variant number + 20 + 4 + + + Implementer + Implementer code + 24 + 8 + + + + + ICSR + ICSR + Interrupt control and state register + 0x4 + 0x20 + read-write + 0x00000000 + + + VECTACTIVE + Active vector + 0 + 9 + + + RETTOBASE + Return to base level + 11 + 1 + + + VECTPENDING + Pending vector + 12 + 7 + + + ISRPENDING + Interrupt pending flag + 22 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + + NMIPENDSET + NMI set-pending bit. + 31 + 1 + + + + + VTOR + VTOR + Vector table offset register + 0x8 + 0x20 + read-write + 0x00000000 + + + TBLOFF + Vector table base offset field + 9 + 21 + + + + + AIRCR + AIRCR + Application interrupt and reset control register + 0xC + 0x20 + read-write + 0x00000000 + + + VECTRESET + VECTRESET + 0 + 1 + + + VECTCLRACTIVE + VECTCLRACTIVE + 1 + 1 + + + SYSRESETREQ + SYSRESETREQ + 2 + 1 + + + PRIGROUP + PRIGROUP + 8 + 3 + + + ENDIANESS + ENDIANESS + 15 + 1 + + + VECTKEYSTAT + Register key + 16 + 16 + + + + + SCR + SCR + System control register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLEEPONEXIT + SLEEPONEXIT + 1 + 1 + + + SLEEPDEEP + SLEEPDEEP + 2 + 1 + + + SEVEONPEND + Send Event on Pending bit + 4 + 1 + + + + + CCR + CCR + Configuration and control register + 0x14 + 0x20 + read-write + 0x00000000 + + + NONBASETHRDENA + Configures how the processor enters Thread mode + 0 + 1 + + + USERSETMPEND + USERSETMPEND + 1 + 1 + + + UNALIGN__TRP + UNALIGN_ TRP + 3 + 1 + + + DIV_0_TRP + DIV_0_TRP + 4 + 1 + + + BFHFNMIGN + BFHFNMIGN + 8 + 1 + + + STKALIGN + STKALIGN + 9 + 1 + + + + + SHPR1 + SHPR1 + System handler priority registers + 0x18 + 0x20 + read-write + 0x00000000 + + + PRI_4 + Priority of system handler 4 + 0 + 8 + + + PRI_5 + Priority of system handler 5 + 8 + 8 + + + PRI_6 + Priority of system handler 6 + 16 + 8 + + + + + SHPR2 + SHPR2 + System handler priority registers + 0x1C + 0x20 + read-write + 0x00000000 + + + PRI_11 + Priority of system handler 11 + 24 + 8 + + + + + SHPR3 + SHPR3 + System handler priority registers + 0x20 + 0x20 + read-write + 0x00000000 + + + PRI_14 + Priority of system handler 14 + 16 + 8 + + + PRI_15 + Priority of system handler 15 + 24 + 8 + + + + + SHCSR + SHCSR + System handler control and state register + 0x24 + 0x20 + read-write + 0x00000000 + + + MEMFAULTACT + Memory management fault exception active bit + 0 + 1 + + + BUSFAULTACT + Bus fault exception active bit + 1 + 1 + + + USGFAULTACT + Usage fault exception active bit + 3 + 1 + + + SVCALLACT + SVC call active bit + 7 + 1 + + + MONITORACT + Debug monitor active bit + 8 + 1 + + + PENDSVACT + PendSV exception active bit + 10 + 1 + + + SYSTICKACT + SysTick exception active bit + 11 + 1 + + + USGFAULTPENDED + Usage fault exception pending bit + 12 + 1 + + + MEMFAULTPENDED + Memory management fault exception pending bit + 13 + 1 + + + BUSFAULTPENDED + Bus fault exception pending bit + 14 + 1 + + + SVCALLPENDED + SVC call pending bit + 15 + 1 + + + MEMFAULTENA + Memory management fault enable bit + 16 + 1 + + + BUSFAULTENA + Bus fault enable bit + 17 + 1 + + + USGFAULTENA + Usage fault enable bit + 18 + 1 + + + + + CFSR_UFSR_BFSR_MMFSR + CFSR_UFSR_BFSR_MMFSR + Configurable fault status register + 0x28 + 0x20 + read-write + 0x00000000 + + + IACCVIOL + Instruction access violation flag + 1 + 1 + + + MUNSTKERR + Memory manager fault on unstacking for a return from exception + 3 + 1 + + + MSTKERR + Memory manager fault on stacking for exception entry. + 4 + 1 + + + MLSPERR + MLSPERR + 5 + 1 + + + MMARVALID + Memory Management Fault Address Register (MMAR) valid flag + 7 + 1 + + + IBUSERR + Instruction bus error + 8 + 1 + + + PRECISERR + Precise data bus error + 9 + 1 + + + IMPRECISERR + Imprecise data bus error + 10 + 1 + + + UNSTKERR + Bus fault on unstacking for a return from exception + 11 + 1 + + + STKERR + Bus fault on stacking for exception entry + 12 + 1 + + + LSPERR + Bus fault on floating-point lazy state preservation + 13 + 1 + + + BFARVALID + Bus Fault Address Register (BFAR) valid flag + 15 + 1 + + + UNDEFINSTR + Undefined instruction usage fault + 16 + 1 + + + INVSTATE + Invalid state usage fault + 17 + 1 + + + INVPC + Invalid PC load usage fault + 18 + 1 + + + NOCP + No coprocessor usage fault. + 19 + 1 + + + UNALIGNED + Unaligned access usage fault + 24 + 1 + + + DIVBYZERO + Divide by zero usage fault + 25 + 1 + + + + + HFSR + HFSR + Hard fault status register + 0x2C + 0x20 + read-write + 0x00000000 + + + VECTTBL + Vector table hard fault + 1 + 1 + + + FORCED + Forced hard fault + 30 + 1 + + + DEBUG_VT + Reserved for Debug use + 31 + 1 + + + + + MMFAR + MMFAR + Memory management fault address register + 0x34 + 0x20 + read-write + 0x00000000 + + + MMFAR + Memory management fault address + 0 + 32 + + + + + BFAR + BFAR + Bus fault address register + 0x38 + 0x20 + read-write + 0x00000000 + + + BFAR + Bus fault address + 0 + 32 + + + + + AFSR + AFSR + Auxiliary fault status register + 0x3C + 0x20 + read-write + 0x00000000 + + + IMPDEF + Implementation defined + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + 0xE000E100 + + 0x0 + 0x400 + registers + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x0 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x4 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER2 + ISER2 + Interrupt Set-Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER3 + ISER3 + Interrupt Set-Enable Register + 0xC + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable Register + 0x80 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable Register + 0x84 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER2 + ICER2 + Interrupt Clear-Enable Register + 0x88 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER3 + ICER3 + Interrupt Clear-Enable Register + 0x8C + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR2 + ISPR2 + Interrupt Set-Pending Register + 0x108 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR3 + ISPR3 + Interrupt Set-Pending Register + 0x10C + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR2 + ICPR2 + Interrupt Clear-Pending Register + 0x188 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR3 + ICPR3 + Interrupt Clear-Pending Register + 0x18C + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x200 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x204 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR2 + IABR2 + Interrupt Active Bit Register + 0x208 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR3 + IABR3 + Interrupt Active Bit Register + 0x20C + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x300 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x304 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x308 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x30C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x310 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x314 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x318 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x31C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x320 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x324 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x328 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x32C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x330 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x334 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x338 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR15 + IPR15 + Interrupt Priority Register + 0x33C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR16 + IPR16 + Interrupt Priority Register + 0x340 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR17 + IPR17 + Interrupt Priority Register + 0x344 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR18 + IPR18 + Interrupt Priority Register + 0x348 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR19 + IPR19 + Interrupt Priority Register + 0x34C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR20 + IPR20 + Interrupt Priority Register + 0x350 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR21 + IPR21 + Interrupt Priority Register + 0x354 + 0x20 + read-write + 0x00000000 + + + IPR22 + IPR22 + Interrupt Priority Register + 0x358 + 0x20 + read-write + 0x00000000 + + + IPR23 + IPR23 + Interrupt Priority Register + 0x35C + 0x20 + read-write + 0x00000000 + + + IPR24 + IPR24 + Interrupt Priority Register + 0x360 + 0x20 + read-write + 0x00000000 + + + IPR25 + IPR25 + Interrupt Priority Register + 0x364 + 0x20 + read-write + 0x00000000 + + + + + NVIC_STIR + Nested vectored interrupt + controller + NVIC + 0xE000EF00 + + 0x0 + 0x5 + registers + + + + STIR + STIR + Software trigger interrupt + register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTID + Software generated interrupt + ID + 0 + 9 + + + + + + + FPU_CPACR + Floating point unit CPACR + FPU + 0xE000ED88 + + 0x0 + 0x5 + registers + + + + CPACR + CPACR + Coprocessor access control register + 0x0 + 0x20 + read-write + 0x0000000 + + + CP + CP + 20 + 4 + + + + + + + SCB_ACTLR + System control block ACTLR + SCB + 0xE000E008 + + 0x0 + 0x5 + registers + + + + ACTRL + ACTRL + Auxiliary control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DISMCYCINT + DISMCYCINT + 0 + 1 + + + DISDEFWBUF + DISDEFWBUF + 1 + 1 + + + DISFOLD + DISFOLD + 2 + 1 + + + DISFPCA + DISFPCA + 8 + 1 + + + DISOOFP + DISOOFP + 9 + 1 + + + + + + + FDCAN + FDCAN + FDCAN + 0x4000A400 + + 0x0 + 0x400 + registers + + + + CREL + CREL + FDCAN Core Release Register + 0x0 + 0x20 + read-only + 0x32141218 + + + DAY + DAY + 0 + 8 + + + MON + MON + 8 + 8 + + + YEAR + YEAR + 16 + 4 + + + SUBSTEP + SUBSTEP + 20 + 4 + + + STEP + STEP + 24 + 4 + + + REL + REL + 28 + 4 + + + + + ENDN + ENDN + FDCAN Core Release Register + 0x4 + 0x20 + read-only + 0x87654321 + + + ETV + ETV + 0 + 32 + + + + + DBTP + DBTP + This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. + 0xC + 0x20 + 0x00000A33 + + + DSJW + DSJW + 0 + 4 + read-write + + + DTSEG2 + DTSEG2 + 4 + 4 + read-write + + + DTSEG1 + DTSEG1 + 8 + 5 + read-write + + + DBRP + DBRP + 16 + 5 + read-write + + + TDC + TDC + 23 + 1 + read-write + + + + + TEST + TEST + Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus. + 0x10 + 0x20 + 0x00000000 + + + LBCK + LBCK + 4 + 1 + read-write + + + TX + TX + 5 + 2 + read-write + + + RX + RX + 7 + 1 + read-only + + + + + RWD + RWD + The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock. + 0x14 + 0x20 + 0x00000000 + + + WDC + WDC + 0 + 8 + read-write + + + WDV + WDV + 8 + 8 + read-only + + + + + CCCR + CCCR + For details about setting and resetting of single bits see Software initialization. + 0x18 + 0x20 + 0x00000001 + + + INIT + INIT + 0 + 1 + read-write + + + CCE + CCE + 1 + 1 + read-write + + + ASM + ASM + 2 + 1 + read-write + + + CSA + CSA + 3 + 1 + read-only + + + CSR + CSR + 4 + 1 + read-write + + + MON + MON + 5 + 1 + read-write + + + DAR + DAR + 6 + 1 + read-write + + + TEST + TEST + 7 + 1 + read-write + + + FDOE + FDOE + 8 + 1 + read-write + + + BRSE + BRSE + 9 + 1 + read-write + + + PXHD + PXHD + 12 + 1 + read-write + + + EFBI + EFBI + 13 + 1 + read-write + + + TXP + TXP + 14 + 1 + read-write + + + NISO + NISO + 15 + 1 + read-write + + + + + NBTP + NBTP + FDCAN_NBTP + 0x1C + 0x20 + read-write + 0x06000A03 + + + NTSEG2 + NTSEG2 + 0 + 7 + + + NTSEG1 + NTSEG1 + 8 + 8 + + + NBRP + NBRP + 16 + 9 + + + NSJW + NSJW + 25 + 7 + + + + + TSCC + TSCC + FDCAN Timestamp Counter Configuration Register + 0x20 + 0x20 + read-write + 0x00000000 + + + TSS + TSS + 0 + 2 + + + TCP + TCP + 16 + 4 + + + + + TSCV + TSCV + FDCAN Timestamp Counter Value Register + 0x24 + 0x20 + read-only + 0x00000000 + + + TSC + TSC + 0 + 16 + + + + + TOCC + TOCC + FDCAN Timeout Counter Configuration Register + 0x28 + 0x20 + 0xFFFF0000 + + + ETOC + ETOC + 0 + 1 + read-write + + + TOS + TOS + 1 + 2 + read-write + + + TOP + TOP + 16 + 16 + read-write + + + + + TOCV + TOCV + FDCAN Timeout Counter Value Register + 0x2C + 0x20 + read-only + 0x0000FFFF + + + TOC + TOC + 0 + 16 + + + + + ECR + ECR + FDCAN Error Counter Register + 0x40 + 0x20 + read-only + 0x00000000 + + + TEC + TEC + 0 + 8 + + + REC + TREC + 8 + 7 + + + RP + RP + 15 + 1 + + + CEL + CEL + 16 + 8 + + + + + PSR + PSR + FDCAN Protocol Status Register + 0x44 + 0x20 + 0x00000707 + + + LEC + LEC + 0 + 3 + read-write + + + ACT + ACT + 3 + 2 + read-only + + + EP + EP + 5 + 1 + read-only + + + EW + EW + 6 + 1 + read-only + + + BO + BO + 7 + 1 + read-only + + + DLEC + DLEC + 8 + 3 + read-write + + + RESI + RESI + 11 + 1 + read-write + + + RBRS + RBRS + 12 + 1 + read-write + + + REDL + REDL + 13 + 1 + read-write + + + PXE + PXE + 14 + 1 + read-write + + + TDCV + TDCV + 16 + 7 + read-write + + + + + TDCR + TDCR + FDCAN Transmitter Delay Compensation Register + 0x48 + 0x20 + read-write + 0x00000000 + + + TDCF + TDCF + 0 + 7 + + + TDCO + TDCO + 8 + 7 + + + + + IR + IR + The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled. + 0x50 + 0x20 + read-write + 0x00000000 + + + RF0N + RF0N + 0 + 1 + + + RF0F + RF0F + 1 + 1 + + + RF0L + RF0L + 2 + 1 + + + RF1N + RF1N + 3 + 1 + + + RF1F + RF1F + 4 + 1 + + + RF1L + RF1L + 5 + 1 + + + HPM + HPM + 6 + 1 + + + TC + TC + 7 + 1 + + + TCF + TCF + 8 + 1 + + + TFE + TFE + 9 + 1 + + + TEFN + TEFN + 10 + 1 + + + TEFF + TEFF + 11 + 1 + + + TEFL + TEFL + 12 + 1 + + + TSW + TSW + 13 + 1 + + + MRAF + MRAF + 14 + 1 + + + TOO + TOO + 15 + 1 + + + ELO + ELO + 16 + 1 + + + EP + EP + 17 + 1 + + + EW + EW + 18 + 1 + + + BO + BO + 19 + 1 + + + WDI + WDI + 20 + 1 + + + PEA + PEA + 21 + 1 + + + PED + PED + 22 + 1 + + + ARA + ARA + 23 + 1 + + + + + IE + IE + The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line. + 0x54 + 0x20 + read-write + 0x00000000 + + + RF0NE + RF0NE + 0 + 1 + + + RF0FE + RF0FE + 1 + 1 + + + RF0LE + RF0LE + 2 + 1 + + + RF1NE + RF1NE + 3 + 1 + + + RF1FE + RF1FE + 4 + 1 + + + RF1LE + RF1LE + 5 + 1 + + + HPME + HPME + 6 + 1 + + + TCE + TCE + 7 + 1 + + + TCFE + TCFE + 8 + 1 + + + TFEE + TFEE + 9 + 1 + + + TEFNE + TEFNE + 10 + 1 + + + TEFFE + TEFFE + 11 + 1 + + + TEFLE + TEFLE + 12 + 1 + + + TSWE + TSWE + 13 + 1 + + + MRAFE + MRAFE + 14 + 1 + + + TOOE + TOOE + 15 + 1 + + + ELOE + ELOE + 16 + 1 + + + EPE + EPE + 17 + 1 + + + EWE + EWE + 18 + 1 + + + BOE + BOE + 19 + 1 + + + WDIE + WDIE + 20 + 1 + + + PEAE + PEAE + 21 + 1 + + + PEDE + PEDE + 22 + 1 + + + ARAE + ARAE + 23 + 1 + + + + + ILS + ILS + The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1]. + 0x58 + 0x20 + read-write + 0x00000000 + + + RxFIFO0 + RxFIFO0 + 0 + 1 + + + RxFIFO1 + RxFIFO1 + 1 + 1 + + + SMSG + SMSG + 2 + 1 + + + TFERR + TFERR + 3 + 1 + + + MISC + MISC + 4 + 1 + + + BERR + BERR + 5 + 1 + + + PERR + PERR + 6 + 1 + + + + + ILE + ILE + Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1. + 0x5C + 0x20 + read-write + 0x00000000 + + + EINT0 + EINT0 + 0 + 1 + + + EINT1 + EINT1 + 1 + 1 + + + + + RXGFC + RXGFC + Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path. + 0x80 + 0x20 + 0x00000000 + + + RRFE + RRFE + 0 + 1 + read-write + + + RRFS + RRFS + 1 + 1 + read-write + + + ANFE + ANFE + 2 + 2 + read-write + + + ANFS + ANFS + 4 + 2 + read-write + + + F1OM + F1OM + 8 + 1 + read-write + + + F0OM + F0OM + 9 + 1 + read-write + + + LSS + LSS + 16 + 5 + read-write + + + LSE + LSE + 24 + 4 + read-write + + + + + XIDAM + XIDAM + FDCAN Extended ID and Mask Register + 0x84 + 0x20 + read-write + 0x1FFFFFFF + + + EIDM + EIDM + 0 + 29 + + + + + HPMS + HPMS + This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages. + 0x88 + 0x20 + read-only + 0x00000000 + + + BIDX + BIDX + 0 + 3 + + + MSI + MSI + 6 + 2 + + + FIDX + FIDX + 8 + 5 + + + FLST + FLST + 15 + 1 + + + + + RXF0S + RXF0S + FDCAN Rx FIFO 0 Status Register + 0x90 + 0x20 + read-only + 0x00000000 + + + F0FL + F0FL + 0 + 4 + + + F0GI + F0GI + 8 + 2 + + + F0PI + F0PI + 16 + 2 + + + F0F + F0F + 24 + 1 + + + RF0L + RF0L + 25 + 1 + + + + + RXF0A + RXF0A + CAN Rx FIFO 0 Acknowledge Register + 0x94 + 0x20 + read-write + 0x00000000 + + + F0AI + F0AI + 0 + 3 + + + + + RXF1S + RXF1S + FDCAN Rx FIFO 1 Status Register + 0x98 + 0x20 + read-only + 0x00000000 + + + F1FL + F1FL + 0 + 4 + + + F1GI + F1GI + 8 + 2 + + + F1PI + F1PI + 16 + 2 + + + F1F + F1F + 24 + 1 + + + RF1L + RF1L + 25 + 1 + + + + + RXF1A + RXF1A + FDCAN Rx FIFO 1 Acknowledge Register + 0x9C + 0x20 + read-write + 0x00000000 + + + F1AI + F1AI + 0 + 3 + + + + + TXBC + TXBC + FDCAN Tx Buffer Configuration Register + 0xC0 + 0x20 + read-write + 0x00000000 + + + TFQM + TFQM + 24 + 1 + + + + + TXFQS + TXFQS + The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated). + 0xC4 + 0x20 + read-only + 0x00000003 + + + TFFL + TFFL + 0 + 3 + + + TFGI + TFGI + 8 + 2 + + + TFQPI + TFQPI + 16 + 2 + + + TFQF + TFQF + 21 + 1 + + + + + TXBRP + TXBRP + FDCAN Tx Buffer Request Pending Register + 0xC8 + 0x20 + read-only + 0x00000000 + + + TRP + TRP + 0 + 3 + + + + + TXBAR + TXBAR + FDCAN Tx Buffer Add Request Register + 0xCC + 0x20 + read-write + 0x00000000 + + + AR + AR + 0 + 3 + + + + + TXBCR + TXBCR + FDCAN Tx Buffer Cancellation Request Register + 0xD0 + 0x20 + read-write + 0x00000000 + + + CR + CR + 0 + 3 + + + + + TXBTO + TXBTO + FDCAN Tx Buffer Transmission Occurred Register + 0xD4 + 0x20 + read-only + 0x00000000 + + + TO + TO + 0 + 3 + + + + + TXBCF + TXBCF + FDCAN Tx Buffer Cancellation Finished Register + 0xD8 + 0x20 + read-only + 0x00000000 + + + CF + CF + 0 + 3 + + + + + TXBTIE + TXBTIE + FDCAN Tx Buffer Transmission Interrupt Enable Register + 0xDC + 0x20 + read-write + 0x00000000 + + + TIE + TIE + 0 + 3 + + + + + TXBCIE + TXBCIE + FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register + 0xE0 + 0x20 + read-write + 0x00000000 + + + CFIE + CFIE + 0 + 3 + + + + + TXEFS + TXEFS + FDCAN Tx Event FIFO Status Register + 0xE4 + 0x20 + read-only + 0x00000000 + + + EFFL + EFFL + 0 + 3 + + + EFGI + EFGI + 8 + 2 + + + EFPI + EFPI + 16 + 2 + + + EFF + EFF + 24 + 1 + + + TEFL + TEFL + 25 + 1 + + + + + TXEFA + TXEFA + FDCAN Tx Event FIFO Acknowledge Register + 0xE8 + 0x20 + read-write + 0x00000000 + + + EFAI + EFAI + 0 + 2 + + + + + CKDIV + CKDIV + FDCAN CFG clock divider register + 0x100 + 0x20 + read-write + 0x00000000 + + + PDIV + input clock divider. the APB clock could be divided prior to be used by the CAN sub + 0 + 4 + + + + + + + FDCAN1 + 0x40006400 + + FDCAN1_IT0 + FDCAN1 interrupt 0 + 21 + + + FDCAN1_IT1 + FDCAN1 interrupt 1 + 22 + + + + UCPD1 + UCPD1 + UCPD + 0x4000A000 + + 0x0 + 0x400 + registers + + + UCPD1 + UCPD1 + 63 + + + + CFG1 + CFG1 + UCPD configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + HBITCLKDIV + HBITCLKDIV + 0 + 6 + + + IFRGAP + IFRGAP + 6 + 5 + + + TRANSWIN + TRANSWIN + 11 + 5 + + + PSC_USBPDCLK + PSC_USBPDCLK + 17 + 3 + + + RXORDSETEN + RXORDSETEN + 20 + 9 + + + TXDMAEN + TXDMAEN + 29 + 1 + + + RXDMAEN + RXDMAEN + 30 + 1 + + + UCPDEN + UCPDEN + 31 + 1 + + + + + CFG2 + CFG2 + UCPD configuration register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + RXFILTDIS + RXFILTDIS + 0 + 1 + + + RXFILT2N3 + RXFILT2N3 + 1 + 1 + + + FORCECLK + FORCECLK + 2 + 1 + + + WUPEN + WUPEN + 3 + 1 + + + + + CR + CR + UCPD configuration register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + TXMODE + TXMODE + 0 + 2 + + + TXSEND + TXSEND + 2 + 1 + + + TXHRST + TXHRST + 3 + 1 + + + RXMODE + RXMODE + 4 + 1 + + + PHYRXEN + PHYRXEN + 5 + 1 + + + PHYCCSEL + PHYCCSEL + 6 + 1 + + + ANASUBMODE + ANASUBMODE + 7 + 2 + + + ANAMODE + ANAMODE + 9 + 1 + + + CCENABLE + CCENABLE + 10 + 2 + + + FRSRXEN + FRSRXEN + 16 + 1 + + + FRSTX + FRSTX + 17 + 1 + + + RDCH + RDCH + 18 + 1 + + + CC1TCDIS + CC1TCDIS + 20 + 1 + + + CC2TCDIS + CC2TCDIS + 21 + 1 + + + + + IMR + IMR + UCPD Interrupt Mask Register + 0x10 + 0x20 + read-write + 0x00000000 + + + TXISIE + TXISIE + 0 + 1 + + + TXMSGDISCIE + TXMSGDISCIE + 1 + 1 + + + TXMSGSENTIE + TXMSGSENTIE + 2 + 1 + + + TXMSGABTIE + TXMSGABTIE + 3 + 1 + + + HRSTDISCIE + HRSTDISCIE + 4 + 1 + + + HRSTSENTIE + HRSTSENTIE + 5 + 1 + + + TXUNDIE + TXUNDIE + 6 + 1 + + + RXNEIE + RXNEIE + 8 + 1 + + + RXORDDETIE + RXORDDETIE + 9 + 1 + + + RXHRSTDETIE + RXHRSTDETIE + 10 + 1 + + + RXOVRIE + RXOVRIE + 11 + 1 + + + RXMSGENDIE + RXMSGENDIE + 12 + 1 + + + TYPECEVT1IE + TYPECEVT1IE + 14 + 1 + + + TYPECEVT2IE + TYPECEVT2IE + 15 + 1 + + + FRSEVTIE + FRSEVTIE + 20 + 1 + + + + + SR + SR + UCPD Status Register + 0x14 + 0x20 + read-write + 0x00000000 + + + TXIS + TXIS + 0 + 1 + + + TXMSGDISC + TXMSGDISC + 1 + 1 + + + TXMSGSENT + TXMSGSENT + 2 + 1 + + + TXMSGABT + TXMSGABT + 3 + 1 + + + HRSTDISC + HRSTDISC + 4 + 1 + + + HRSTSENT + HRSTSENT + 5 + 1 + + + TXUND + TXUND + 6 + 1 + + + RXNE + RXNE + 8 + 1 + + + RXORDDET + RXORDDET + 9 + 1 + + + RXHRSTDET + RXHRSTDET + 10 + 1 + + + RXOVR + RXOVR + 11 + 1 + + + RXMSGEND + RXMSGEND + 12 + 1 + + + RXERR + RXERR + 13 + 1 + + + TYPECEVT1 + TYPECEVT1 + 14 + 1 + + + TYPECEVT2 + TYPECEVT2 + 15 + 1 + + + TYPEC_VSTATE_CC1 + TYPEC_VSTATE_CC1 + 16 + 2 + + + TYPEC_VSTATE_CC2 + TYPEC_VSTATE_CC2 + 18 + 2 + + + FRSEVT + FRSEVT + 20 + 1 + + + + + ICR + ICR + UCPD Interrupt Clear Register + 0x18 + 0x20 + read-write + 0x00000000 + + + TXMSGDISCCF + TXMSGDISCCF + 1 + 1 + + + TXMSGSENTCF + TXMSGSENTCF + 2 + 1 + + + TXMSGABTCF + TXMSGABTCF + 3 + 1 + + + HRSTDISCCF + HRSTDISCCF + 4 + 1 + + + HRSTSENTCF + HRSTSENTCF + 5 + 1 + + + TXUNDCF + TXUNDCF + 6 + 1 + + + RXORDDETCF + RXORDDETCF + 9 + 1 + + + RXHRSTDETCF + RXHRSTDETCF + 10 + 1 + + + RXOVRCF + RXOVRCF + 11 + 1 + + + RXMSGENDCF + RXMSGENDCF + 12 + 1 + + + TYPECEVT1CF + TYPECEVT1CF + 14 + 1 + + + TYPECEVT2CF + TYPECEVT2CF + 15 + 1 + + + FRSEVTCF + FRSEVTCF + 20 + 1 + + + + + TX_ORDSET + TX_ORDSET + UCPD Tx Ordered Set Type Register + 0x1C + 0x20 + read-write + 0x00000000 + + + TXORDSET + TXORDSET + 0 + 20 + + + + + TX_PAYSZ + TX_PAYSZ + UCPD Tx Paysize Register + 0x20 + 0x20 + read-write + 0x00000000 + + + TXPAYSZ + TXPAYSZ + 0 + 10 + + + + + TXDR + TXDR + UCPD Tx Data Register + 0x24 + 0x20 + read-write + 0x00000000 + + + TXDATA + TXDATA + 0 + 8 + + + + + RX_ORDSET + RX_ORDSET + UCPD Rx Ordered Set Register + 0x28 + 0x20 + read-only + 0x00000000 + + + RXORDSET + RXORDSET + 0 + 3 + + + RXSOP3OF4 + RXSOP3OF4 + 3 + 1 + + + RXSOPKINVALID + RXSOPKINVALID + 4 + 3 + + + + + RX_PAYSZ + RX_PAYSZ + UCPD Rx Paysize Register + 0x2C + 0x20 + read-only + 0x00000000 + + + RXPAYSZ + RXPAYSZ + 0 + 10 + + + + + RXDR + RXDR + UCPD Rx Data Register + 0x30 + 0x20 + read-only + 0x00000000 + + + RXDATA + RXDATA + 0 + 8 + + + + + RX_ORDEXT1 + RX_ORDEXT1 + UCPD Rx Ordered Set Extension Register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + RXSOPX1 + RXSOPX1 + 0 + 20 + + + + + RX_ORDEXT2 + RX_ORDEXT2 + UCPD Rx Ordered Set Extension Register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + RXSOPX2 + RXSOPX2 + 0 + 20 + + + + + + + USB_FS_device + USB_FS_device + USB + 0x40005C00 + + 0x0 + 0x400 + registers + + + + EP0R + EP0R + USB endpoint n register + 0x0 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP1R + EP1R + USB endpoint n register + 0x4 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP2R + EP2R + USB endpoint n register + 0x8 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP3R + EP3R + USB endpoint n register + 0xC + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP4R + EP4R + USB endpoint n register + 0x10 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP5R + EP5R + USB endpoint n register + 0x14 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP6R + EP6R + USB endpoint n register + 0x18 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP7R + EP7R + USB endpoint n register + 0x1C + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + CNTR + CNTR + USB control register + 0x40 + 0x20 + read-write + 0x00000000 + + + FRES + FRES + 0 + 1 + + + PDWN + PDWN + 1 + 1 + + + LP_MODE + LP_MODE + 2 + 1 + + + FSUSP + FSUSP + 3 + 1 + + + RESUME + RESUME + 4 + 1 + + + L1RESUME + L1RESUME + 5 + 1 + + + L1REQM + L1REQM + 7 + 1 + + + ESOFM + ESOFM + 8 + 1 + + + SOFM + SOFM + 9 + 1 + + + RESETM + RESETM + 10 + 1 + + + SUSPM + SUSPM + 11 + 1 + + + WKUPM + WKUPM + 12 + 1 + + + ERRM + ERRM + 13 + 1 + + + PMAOVRM + PMAOVRM + 14 + 1 + + + CTRM + CTRM + 15 + 1 + + + + + ISTR + ISTR + USB interrupt status register + 0x44 + 0x20 + read-write + 0x00000000 + + + EP_ID + EP_ID + 0 + 4 + + + DIR + DIR + 4 + 1 + + + L1REQ + L1REQ + 7 + 1 + + + ESOF + ESOF + 8 + 1 + + + SOF + SOF + 9 + 1 + + + RESET + RESET + 10 + 1 + + + SUSP + SUSP + 11 + 1 + + + WKUP + WKUP + 12 + 1 + + + ERR + ERR + 13 + 1 + + + PMAOVR + PMAOVR + 14 + 1 + + + CTR + CTR + 15 + 1 + + + + + FNR + FNR + USB frame number register + 0x48 + 0x20 + read-only + 0x00000000 + + + FN + FN + 0 + 11 + + + LSOF + LSOF + 11 + 2 + + + LCK + LCK + 13 + 1 + + + RXDM + RXDM + 14 + 1 + + + RXDP + RXDP + 15 + 1 + + + + + DADDR + DADDR + USB device address + 0x4C + 0x20 + read-write + 0x00000000 + + + ADD + ADD + 0 + 7 + + + EF + EF + 7 + 1 + + + + + BTABLE + BTABLE + Buffer table address + 0x50 + 0x20 + read-write + 0x00000000 + + + BTABLE + BTABLE + 3 + 13 + + + + + + + CRS + CRS + CRS + 0x40002000 + + 0x0 + 0x400 + registers + + + + CR + CR + CRS control register + 0x0 + 0x20 + 0x00004000 + + + SYNCOKIE + SYNC event OK interrupt enable + 0 + 1 + read-write + + + SYNCWARNIE + SYNC warning interrupt enable + 1 + 1 + read-write + + + ERRIE + Synchronization or trimming error interrupt enable + 2 + 1 + read-write + + + ESYNCIE + Expected SYNC interrupt enable + 3 + 1 + read-write + + + CEN + Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set, the CRS_CFGR register is write-protected and cannot be modified. + 5 + 1 + read-write + + + AUTOTRIMEN + Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details. + 6 + 1 + read-write + + + SWSYNC + Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware. + 7 + 1 + read-write + + + TRIM + HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only. + 8 + 7 + read-write + + + + + CFGR + CFGR + This register can be written only when the frequency error counter is disabled (CEN bit is cleared in CRS_CR). When the counter is enabled, this register is write-protected. + 0x4 + 0x20 + read-write + 0x2022BB7F + + + RELOAD + Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section7.3.3: Frequency error measurement for more details about counter behavior. + 0 + 16 + + + FELIM + Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP evaluation. + 16 + 8 + + + SYNCDIV + SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal. + 24 + 3 + + + SYNCSRC + SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs should be used as SYNC signal. + 28 + 2 + + + SYNCPOL + SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source. + 31 + 1 + + + + + ISR + ISR + CRS interrupt and status register + 0x8 + 0x20 + read-only + 0x00000000 + + + SYNCOKF + SYNC event OK flag This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register. + 0 + 1 + + + SYNCWARNF + SYNC warning flag This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register. + 1 + 1 + + + ERRF + Error flag This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits. + 2 + 1 + + + ESYNCF + Expected SYNC flag This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register. + 3 + 1 + + + SYNCERR + SYNC error This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action should be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 8 + 1 + + + SYNCMISS + SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action should be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 9 + 1 + + + TRIMOVF + Trimming overflow or underflow This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 10 + 1 + + + FEDIR + Frequency error direction FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. + 15 + 1 + + + FECAP + Frequency error capture FECAP is the frequency error counter value latched in the time ofthe last SYNC event. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP usage. + 16 + 16 + + + + + ICR + ICR + CRS interrupt flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + SYNCOKC + SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register. + 0 + 1 + + + SYNCWARNC + SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register. + 1 + 1 + + + ERRC + Error clear flag Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register. + 2 + 1 + + + ESYNCC + Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register. + 3 + 1 + + + + + + +