-

2024-06-26 23:21:20 +03:00 · 2024-06-26 23:21:20 +03:00 · f97b7a3092
commit f97b7a3092
parent f1f51b03b2
52 changed files with 38877 additions and 2005 deletions
--- a/CHANGELOG.txt
+++ b/CHANGELOG.txt
@ -104,7 +104,7 @@ Schematic:
 -	C19 60V tag ist eher zur orientierun, ich bezweifle das wir überhaupt <100V 10n haben
 -	R46 sollte entweder 0 ohm oder 1M sein. DNP macht das nicht klar eigentlich
 -	Serienwiderstand und Pulldown an die Gates eingefügt.
-- Meine Gedanke war schon das etwas Rückwärts fließt bei D20/21. Wenn ich bin mir unsicher ob es eigentlich Sinn macht
+-- Meine Gedanke war schon das etwas Rückwärts fließt bei D20/21. PMEG -> RB751S40T5G Schottky diode
 -	Strom Sensor kann falcsh gemountet werden und dann geht V_{out} in minus, hier auch schottky 
 -	CURRENT_SENSOR_ON is V_{ref}, geplant war ein offset aber da wirds nix. man könnte es weglassen
 -	der Precharge Widerstand wird das auf keinem Fall überleben. Das ist nicht so durchgedacht.
--- a/Documentation/Datasheets/4000er
+++ b/Documentation/Datasheets/4000er
--- a/Documentation/Datasheets/FaSTTUBe
+++ b/Documentation/Datasheets/FaSTTUBe
--- a/Documentation/Pictures/Bild.png
+++ b/Documentation/Pictures/Bild.png
--- a/Documentation/Pictures/Bild1.png
+++ b/Documentation/Pictures/Bild1.png
--- a/Documentation/Pictures/Bild2.png
+++ b/Documentation/Pictures/Bild2.png
--- a/Documentation/Pictures/Bild3.png
+++ b/Documentation/Pictures/Bild3.png
--- a/Documentation/Pictures/Bild4.png
+++ b/Documentation/Pictures/Bild4.png
--- a/Documentation/Pictures/Bild5.png
+++ b/Documentation/Pictures/Bild5.png
--- a/Documentation/Pictures/Bild6.png
+++ b/Documentation/Pictures/Bild6.png
--- a/Documentation/Pictures/Bild7.png
+++ b/Documentation/Pictures/Bild7.png
--- a/Documentation/Pictures/Bild8.png
+++ b/Documentation/Pictures/Bild8.png
--- a/Documentation/Pictures/Prechargekurve
+++ b/Documentation/Pictures/Prechargekurve
--- a/Documentation/Pictures/Stack.png
+++ b/Documentation/Pictures/Stack.png
--- a/Documentation/Screenshot
+++ b/Documentation/Screenshot
--- a/Documentation/Screenshot
+++ b/Documentation/Screenshot
--- a/Documentation/mill-max-0926-0-15-20-76-14-11-0.prt
+++ b/Documentation/mill-max-0926-0-15-20-76-14-11-0.prt
--- a/MVBMS/Input_Output.kicad_sch
+++ b/MVBMS/Input_Output.kicad_sch
--- a/MVBMS/MVBMS-backups/MVBMS-2024-06-26_193056.zip
+++ b/MVBMS/MVBMS-backups/MVBMS-2024-06-26_193056.zip
--- a/MVBMS/MVBMS-backups/MVBMS-2024-06-26_193741.zip
+++ b/MVBMS/MVBMS-backups/MVBMS-2024-06-26_193741.zip
--- a/MVBMS/MVBMS-backups/MVBMS-2024-06-26_194405.zip
+++ b/MVBMS/MVBMS-backups/MVBMS-2024-06-26_194405.zip
--- a/MVBMS/MVBMS-backups/MVBMS-2024-06-26_211139.zip
+++ b/MVBMS/MVBMS-backups/MVBMS-2024-06-26_211139.zip
--- a/MVBMS/MVBMS-backups/MVBMS-2024-06-26_225108.zip
+++ b/MVBMS/MVBMS-backups/MVBMS-2024-06-26_225108.zip
--- a/MVBMS/MVBMS-backups/MVBMS-2024-06-26_230439.zip
+++ b/MVBMS/MVBMS-backups/MVBMS-2024-06-26_230439.zip
--- a/MVBMS/MVBMS-backups/MVBMS-2024-06-26_231220.zip
+++ b/MVBMS/MVBMS-backups/MVBMS-2024-06-26_231220.zip
--- a/MVBMS/MVBMS-backups/MVBMS-2024-06-26_231723.zip
+++ b/MVBMS/MVBMS-backups/MVBMS-2024-06-26_231723.zip
--- a/MVBMS/MVBMS.kicad_pcb
+++ b/MVBMS/MVBMS.kicad_pcb
--- a/MVBMS/MVBMS.kicad_prl
+++ b/MVBMS/MVBMS.kicad_prl
@ -1,6 +1,6 @@
 {
  "board": {
-    "active_layer": 31,
+    "active_layer": 0,
    "active_layer_preset": "",
    "auto_track_width": true,
    "hidden_netclasses": [],
--- a/MVBMS/MVBMS.kicad_sch
+++ b/MVBMS/MVBMS.kicad_sch
@ -1134,7 +1134,7 @@
 		)
 		(uuid "1dfc0c9b-c63b-4e5e-9291-4ff4ecd2e4c8")
 	)
-	(text "Schematic:\n-MVBMS\n-	Thermische Berechnung ist worst case scenario, habe da das max von alles genommen für eine Schätzung was da passieren könnte. Die Zahl ist für die PDU.\n-	WC kann man auf jeden Fall sparen, da werden nur Temperaturen und Spannungen geloggt. keine wichtige Daten\n-	1uF auf 100nF für NRST\n-	für das BMS auf jeden Fall. Für LED vllt schon aber wir haben auch ganz viele bestellt.\n-	Die Platine sollte da eigentlich da terminieren. DNP ist falsch für alles da\n-	Kapatizitätberechnung ist auch alt. Bei Balancingwiderstand kann jetzt nichts machen, im Notfall mit Software was machen.\n-	C19 60V tag ist eher zur orientierun, ich bezweifle das wir überhaupt <100V 10n haben\n-	R46 sollte entweder 0 ohm oder 1M sein. DNP macht das nicht klar eigentlich\n-	Serienwiderstand und Pulldown an die Gates eingefügt.\n-- Meine Gedanke war schon das etwas Rückwärts fließt bei D20/21. Wenn ich bin mir unsicher ob es eigentlich Sinn macht\n-	Strom Sensor kann falcsh gemountet werden und dann geht V_{out} in minus, hier auch schottky \n-	CURRENT_SENSOR_ON is V_{ref}, geplant war ein offset aber da wirds nix. man könnte es weglassen\n-	der Precharge Widerstand wird das auf keinem Fall überleben. Das ist nicht so durchgedacht.\n\nLayout:\n-MVBMS:\n- 	3V3 jetzt auf die innere Seite. Nach kurze Überlegung macht es schon Sinn.\n-	Der Deckel ist viel zu tief hinten bei dem MCU, man kann keine Stecker da packen.\n- 	RGB LED werde ich näher zum MCU bringen man herumschieben. \n-	Es gibt kein Grund für den L, sieht halt gut aus ig\n-	Der NRST Kondensator ist jetzt neben dem Quartz\n-   Die Traces unten werden um 1mm nach oben geschoben\n- 	Lage wechsel wird da gemacht um zu vermeiden, dass die Frontlage zu oft zu trennen. aber jetzt könnt man das machen wenn nur 3V3 auf front und back sind\n- 	Die Traces für Balancingwiderstand auf die Rückseite zu bringen wird jetzt sehr lang dauern. Das hätte ich jetzt ungern gemacht wenn der Unterschied nicht groß ist.\n-	mit dem LDO und EEPROM auf die linke Seite hat man mehr Platz auf die rechte Seite. \n\n-MV_Abnehmer:\n-	Beschriftung der Pogopins vergößert\n- 	2 Lagen habe ich schon hinbekommen, aber um mehr Steifigkeit zu erzielen habe ich 4 Lagen mit fetten Prepregs gemacht. \n-	Wir werden den PCB mit einem 3D-Teil, was den PCB runten druckt, befestigen. Schrauben sind nicht möglich.\n-	Die Pogopins sollen mit ~100g runter drucken, man hofft, dass das genug Kraft ist. Filtern werde ich noch in software mal angucken\n-	Wegen DIP switch: Johnny meinte das Regel macht das explizit, dass wir ein Sensor und ein Spannungabnehmer trennen werden können. Der DIP-Switch sollte zu diesem Zweck passen.\n- 	DIP switch footprint habe ich in mit dem Datenblatt verglichen, das passt. ein richtiges 3D-Model sollte man noch einfügen aber das reicht für die stp export\n-	Abstand zwischen SDA/SCL und 60V vergrößert\n- 	Planeabstand von Pogopins ist jetzt 1mm\n-	noch 3V3 vias gestreut. Die muss man aber coaten dann oder?"
+	(text "Schematic:\n-MVBMS\n-	Thermische Berechnung ist worst case scenario, habe da das max von alles genommen für eine Schätzung was da passieren könnte. Die Zahl ist für die PDU.\n-	WC kann man auf jeden Fall sparen, da werden nur Temperaturen und Spannungen geloggt. keine wichtige Daten\n-	1uF auf 100nF für NRST\n-	für das BMS auf jeden Fall. Für LED vllt schon aber wir haben auch ganz viele bestellt.\n-	Die Platine sollte da eigentlich da terminieren. DNP ist falsch für alles da\n-	Kapatizitätberechnung ist auch alt. Bei Balancingwiderstand kann jetzt nichts machen, im Notfall mit Software was machen.\n-	C19 60V tag ist eher zur orientierun, ich bezweifle das wir überhaupt <100V 10n haben\n-	R46 sollte entweder 0 ohm oder 1M sein. DNP macht das nicht klar eigentlich\n-	Serienwiderstand und Pulldown an die Gates eingefügt.\n-- Meine Gedanke war schon das etwas Rückwärts fließt bei D20/21. PMEG -> RB751S40T5G Schottky diode\n-	Strom Sensor kann falcsh gemountet werden und dann geht V_{out} in minus, hier auch schottky \n-	CURRENT_SENSOR_ON is V_{ref}, geplant war ein offset aber da wirds nix. man könnte es weglassen\n-	der Precharge Widerstand wird das auf keinem Fall überleben. Das ist nicht so durchgedacht.\n\nLayout:\n-MVBMS:\n- 	3V3 jetzt auf die innere Seite. Nach kurze Überlegung macht es schon Sinn.\n-	Der Deckel ist viel zu tief hinten bei dem MCU, man kann keine Stecker da packen.\n- 	RGB LED werde ich näher zum MCU bringen man herumschieben. \n-	Es gibt kein Grund für den L, sieht halt gut aus ig\n-	Der NRST Kondensator ist jetzt neben dem Quartz\n-   Die Traces unten werden um 1mm nach oben geschoben\n- 	Lage wechsel wird da gemacht um zu vermeiden, dass die Frontlage zu oft zu trennen. aber jetzt könnt man das machen wenn nur 3V3 auf front und back sind\n- 	Die Traces für Balancingwiderstand auf die Rückseite zu bringen wird jetzt sehr lang dauern. Das hätte ich jetzt ungern gemacht wenn der Unterschied nicht groß ist.\n-	mit dem LDO und EEPROM auf die linke Seite hat man mehr Platz auf die rechte Seite. \n\n-MV_Abnehmer:\n-	Beschriftung der Pogopins vergößert\n- 	2 Lagen habe ich schon hinbekommen, aber um mehr Steifigkeit zu erzielen habe ich 4 Lagen mit fetten Prepregs gemacht. \n-	Wir werden den PCB mit einem 3D-Teil, was den PCB runten druckt, befestigen. Schrauben sind nicht möglich.\n-	Die Pogopins sollen mit ~100g runter drucken, man hofft, dass das genug Kraft ist. Filtern werde ich noch in software mal angucken\n-	Wegen DIP switch: Johnny meinte das Regel macht das explizit, dass wir ein Sensor und ein Spannungabnehmer trennen werden können. Der DIP-Switch sollte zu diesem Zweck passen.\n- 	DIP switch footprint habe ich in mit dem Datenblatt verglichen, das passt. ein richtiges 3D-Model sollte man noch einfügen aber das reicht für die stp export\n-	Abstand zwischen SDA/SCL und 60V vergrößert\n- 	Planeabstand von Pogopins ist jetzt 1mm\n-	noch 3V3 vias gestreut. Die muss man aber coaten dann oder?"
 		(exclude_from_sim no)
 		(at 248.539 103.251 0)
 		(effects
--- a/MVBMS/fp-info-cache
+++ b/MVBMS/fp-info-cache
@ -1,4 +1,4 @@
-75629526530879
+75629526686843
 ADBMS6830
 QFP-80_12x12_Pitch0.5mm

--- a/MV_Abnehmerplatine/MV_Abnehmerplatine-backups/MV_Abnehmerplatine-2024-06-26_190558.zip
+++ b/MV_Abnehmerplatine/MV_Abnehmerplatine-backups/MV_Abnehmerplatine-2024-06-26_190558.zip
--- a/MV_Abnehmerplatine/MV_Abnehmerplatine-backups/MV_Abnehmerplatine-2024-06-26_191230.zip
+++ b/MV_Abnehmerplatine/MV_Abnehmerplatine-backups/MV_Abnehmerplatine-2024-06-26_191230.zip
--- a/MV_Abnehmerplatine/MV_Abnehmerplatine-backups/MV_Abnehmerplatine-2024-06-26_192241.zip
+++ b/MV_Abnehmerplatine/MV_Abnehmerplatine-backups/MV_Abnehmerplatine-2024-06-26_192241.zip
--- a/MV_Abnehmerplatine/MV_Abnehmerplatine-backups/MV_Abnehmerplatine-2024-06-26_212437.zip
+++ b/MV_Abnehmerplatine/MV_Abnehmerplatine-backups/MV_Abnehmerplatine-2024-06-26_212437.zip
--- a/MV_Abnehmerplatine/MV_Abnehmerplatine-backups/MV_Abnehmerplatine-2024-06-26_213353.zip
+++ b/MV_Abnehmerplatine/MV_Abnehmerplatine-backups/MV_Abnehmerplatine-2024-06-26_213353.zip
--- a/MV_Abnehmerplatine/MV_Abnehmerplatine-backups/MV_Abnehmerplatine-2024-06-26_232046.zip
+++ b/MV_Abnehmerplatine/MV_Abnehmerplatine-backups/MV_Abnehmerplatine-2024-06-26_232046.zip
--- a/MV_Abnehmerplatine/MV_Abnehmerplatine.kicad_pcb
+++ b/MV_Abnehmerplatine/MV_Abnehmerplatine.kicad_pcb
@ -3,7 +3,7 @@
 	(generator "pcbnew")
 	(generator_version "8.0")
 	(general
-		(thickness 2.866)
+		(thickness 1.6)
 		(legacy_teardrops no)
 	)
 	(paper "A4")
@ -54,11 +54,11 @@
 			)
 			(layer "F.Cu"
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-				(thickness 0.018)
+				(thickness 0.035)
 			)
 			(layer "dielectric 1"
 				(type "prepreg")
-				(thickness 0.188)
+				(thickness 0.1)
 				(material "FR4")
 				(epsilon_r 4.5)
 				(loss_tangent 0.02)
@ -69,7 +69,7 @@
 			)
 			(layer "dielectric 2"
 				(type "core")
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+				(thickness 1.24)
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@ -80,14 +80,14 @@
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 				(loss_tangent 0.02)
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 			(layer "B.Cu"
 				(type "copper")
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@ -9930,7 +9930,7 @@
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 		(layer "Edge.Cuts")
 		(uuid "d8899667-dc4c-4323-b8f1-51a41e9f728d")
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+	(dimension
+		(type aligned)
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+		)
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+		(gr_text "185.0000 mm"
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--- a/MV_Abnehmerplatine/MV_Abnehmerplatine.kicad_pro
+++ b/MV_Abnehmerplatine/MV_Abnehmerplatine.kicad_pro
@ -488,7 +488,7 @@
      "gencad": "",
      "idf": "",
      "netlist": "",
-      "plot": "",
+      "plot": "./gerber",
      "pos_files": "",
      "specctra_dsn": "",
      "step": "../stp/MV_Abnehmerplatine.step",
--- a/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-B_Cu.gbr
+++ b/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-B_Cu.gbr
--- a/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-B_Mask.gbr
+++ b/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-B_Mask.gbr
@ -0,0 +1,299 @@
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+0 Add a 4 corners polygon primitive as box body*
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+G04 Aperture macros list end*
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--- a/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-B_Paste.gbr
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--- a/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-B_Silkscreen.gbr
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--- a/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-Edge_Cuts.gbr
+++ b/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-Edge_Cuts.gbr
@ -0,0 +1,74 @@
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--- a/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-F_Cu.gbr
+++ b/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-F_Cu.gbr
--- a/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-F_Mask.gbr
+++ b/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-F_Mask.gbr
@ -0,0 +1,140 @@
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--- a/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-F_Paste.gbr
+++ b/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-F_Paste.gbr
@ -0,0 +1,96 @@
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--- a/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-F_Silkscreen.gbr
+++ b/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-F_Silkscreen.gbr
--- a/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-In1_Cu.gbr
+++ b/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-In1_Cu.gbr
--- a/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-In2_Cu.gbr
+++ b/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-In2_Cu.gbr
--- a/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-NPTH.drl
+++ b/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-NPTH.drl
@ -0,0 +1,12 @@
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+; DRILL file {KiCad 8.0.2} date 2024-06-26T21:14:34+0300
+; FORMAT={-:-/ absolute / inch / decimal}
+; #@! TF.CreationDate,2024-06-26T21:14:34+03:00
+; #@! TF.GenerationSoftware,Kicad,Pcbnew,8.0.2
+; #@! TF.FileFunction,NonPlated,1,4,NPTH
+FMAT,2
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+%
+G90
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--- a/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-PTH.drl
+++ b/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-PTH.drl
@ -0,0 +1,183 @@
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+; DRILL file {KiCad 8.0.2} date 2024-06-26T21:14:34+0300
+; FORMAT={-:-/ absolute / inch / decimal}
+; #@! TF.CreationDate,2024-06-26T21:14:34+03:00
+; #@! TF.GenerationSoftware,Kicad,Pcbnew,8.0.2
+; #@! TF.FileFunction,Plated,1,4,PTH
+FMAT,2
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+; #@! TA.AperFunction,Plated,PTH,ComponentDrill
+T1C0.0098
+; #@! TA.AperFunction,Plated,PTH,ViaDrill
+T2C0.0157
+; #@! TA.AperFunction,Plated,PTH,ComponentDrill
+T3C0.0689
+%
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+M30
--- a/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-job.gbrjob
+++ b/MV_Abnehmerplatine/gerber/MV_Abnehmerplatine-job.gbrjob
@ -0,0 +1,169 @@
+{
+  "Header": {
+    "GenerationSoftware": {
+      "Vendor": "KiCad",
+      "Application": "Pcbnew",
+      "Version": "8.0.2"
+    },
+    "CreationDate": "2024-06-26T21:14:32+03:00"
+  },
+  "GeneralSpecs": {
+    "ProjectId": {
+      "Name": "MV_Abnehmerplatine",
+      "GUID": "4d565f41-626e-4656-986d-6572706c6174",
+      "Revision": "rev?"
+    },
+    "Size": {
+      "X": 185.2,
+      "Y": 34.7172
+    },
+    "LayerNumber": 4,
+    "BoardThickness": 2.866,
+    "Finish": "None"
+  },
+  "DesignRules": [
+    {
+      "Layers": "Outer",
+      "PadToPad": 0.2,
+      "PadToTrack": 0.2,
+      "TrackToTrack": 0.2,
+      "MinLineWidth": 0.25,
+      "TrackToRegion": 0.5,
+      "RegionToRegion": 0.5
+    },
+    {
+      "Layers": "Inner",
+      "PadToPad": 0.0,
+      "PadToTrack": 0.0,
+      "TrackToTrack": 0.2,
+      "TrackToRegion": 0.5,
+      "RegionToRegion": 0.5
+    }
+  ],
+  "FilesAttributes": [
+    {
+      "Path": "MV_Abnehmerplatine-F_Cu.gbr",
+      "FileFunction": "Copper,L1,Top",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "MV_Abnehmerplatine-In1_Cu.gbr",
+      "FileFunction": "Copper,L2,Inr",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "MV_Abnehmerplatine-In2_Cu.gbr",
+      "FileFunction": "Copper,L3,Inr",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "MV_Abnehmerplatine-B_Cu.gbr",
+      "FileFunction": "Copper,L4,Bot",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "MV_Abnehmerplatine-F_Paste.gbr",
+      "FileFunction": "SolderPaste,Top",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "MV_Abnehmerplatine-B_Paste.gbr",
+      "FileFunction": "SolderPaste,Bot",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "MV_Abnehmerplatine-F_Silkscreen.gbr",
+      "FileFunction": "Legend,Top",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "MV_Abnehmerplatine-B_Silkscreen.gbr",
+      "FileFunction": "Legend,Bot",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "MV_Abnehmerplatine-F_Mask.gbr",
+      "FileFunction": "SolderMask,Top",
+      "FilePolarity": "Negative"
+    },
+    {
+      "Path": "MV_Abnehmerplatine-B_Mask.gbr",
+      "FileFunction": "SolderMask,Bot",
+      "FilePolarity": "Negative"
+    },
+    {
+      "Path": "MV_Abnehmerplatine-Edge_Cuts.gbr",
+      "FileFunction": "Profile",
+      "FilePolarity": "Positive"
+    }
+  ],
+  "MaterialStackup": [
+    {
+      "Type": "Legend",
+      "Name": "Top Silk Screen"
+    },
+    {
+      "Type": "SolderPaste",
+      "Name": "Top Solder Paste"
+    },
+    {
+      "Type": "SolderMask",
+      "Thickness": 0.01,
+      "Name": "Top Solder Mask"
+    },
+    {
+      "Type": "Copper",
+      "Thickness": 0.018,
+      "Name": "F.Cu"
+    },
+    {
+      "Type": "Dielectric",
+      "Thickness": 0.188,
+      "Material": "FR4",
+      "Name": "F.Cu/In1.Cu",
+      "Notes": "Type: dielectric layer 1 (from F.Cu to In1.Cu)"
+    },
+    {
+      "Type": "Copper",
+      "Thickness": 0.035,
+      "Name": "In1.Cu"
+    },
+    {
+      "Type": "Dielectric",
+      "Thickness": 2.364,
+      "Material": "FR4",
+      "Name": "In1.Cu/In2.Cu",
+      "Notes": "Type: dielectric layer 2 (from In1.Cu to In2.Cu)"
+    },
+    {
+      "Type": "Copper",
+      "Thickness": 0.035,
+      "Name": "In2.Cu"
+    },
+    {
+      "Type": "Dielectric",
+      "Thickness": 0.188,
+      "Material": "FR4",
+      "Name": "In2.Cu/B.Cu",
+      "Notes": "Type: dielectric layer 3 (from In2.Cu to B.Cu)"
+    },
+    {
+      "Type": "Copper",
+      "Thickness": 0.018,
+      "Name": "B.Cu"
+    },
+    {
+      "Type": "SolderMask",
+      "Thickness": 0.01,
+      "Name": "Bottom Solder Mask"
+    },
+    {
+      "Type": "SolderPaste",
+      "Name": "Bottom Solder Paste"
+    },
+    {
+      "Type": "Legend",
+      "Name": "Bottom Silk Screen"
+    }
+  ]
+}