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INS-VN-200/vn200/Debug/vn200.list

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vn200.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000188 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 0000457c 08000188 08000188 00010188 2**3
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000034 08004704 08004704 00014704 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08004738 08004738 0002000c 2**0
CONTENTS
4 .ARM 00000000 08004738 08004738 0002000c 2**0
CONTENTS
5 .preinit_array 00000000 08004738 08004738 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 0000000c 08004738 08004738 00014738 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 0000000c 08004744 08004744 00014744 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 0000000c 20000000 08004750 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 0000013c 2000000c 0800475c 0002000c 2**2
ALLOC
10 ._user_heap_stack 00000600 20000148 0800475c 00020148 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
12 .comment 00000033 00000000 00000000 0002003c 2**0
CONTENTS, READONLY
13 .debug_info 0000e3de 00000000 00000000 0002006f 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_abbrev 000023eb 00000000 00000000 0002e44d 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_aranges 00000ca8 00000000 00000000 00030838 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_ranges 00000af0 00000000 00000000 000314e0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_macro 0001eb3a 00000000 00000000 00031fd0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_line 00009aca 00000000 00000000 00050b0a 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .debug_str 000ac041 00000000 00000000 0005a5d4 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
20 .debug_frame 00003208 00000000 00000000 00106618 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_loc 000002e6 00000000 00000000 00109820 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000188 <deregister_tm_clones>:
8000188: 4803 ldr r0, [pc, #12] ; (8000198 <deregister_tm_clones+0x10>)
800018a: 4b04 ldr r3, [pc, #16] ; (800019c <deregister_tm_clones+0x14>)
800018c: 4283 cmp r3, r0
800018e: d002 beq.n 8000196 <deregister_tm_clones+0xe>
8000190: 4b03 ldr r3, [pc, #12] ; (80001a0 <deregister_tm_clones+0x18>)
8000192: b103 cbz r3, 8000196 <deregister_tm_clones+0xe>
8000194: 4718 bx r3
8000196: 4770 bx lr
8000198: 2000000c .word 0x2000000c
800019c: 2000000c .word 0x2000000c
80001a0: 00000000 .word 0x00000000
080001a4 <register_tm_clones>:
80001a4: 4805 ldr r0, [pc, #20] ; (80001bc <register_tm_clones+0x18>)
80001a6: 4906 ldr r1, [pc, #24] ; (80001c0 <register_tm_clones+0x1c>)
80001a8: 1a0b subs r3, r1, r0
80001aa: 0fd9 lsrs r1, r3, #31
80001ac: eb01 01a3 add.w r1, r1, r3, asr #2
80001b0: 1049 asrs r1, r1, #1
80001b2: d002 beq.n 80001ba <register_tm_clones+0x16>
80001b4: 4b03 ldr r3, [pc, #12] ; (80001c4 <register_tm_clones+0x20>)
80001b6: b103 cbz r3, 80001ba <register_tm_clones+0x16>
80001b8: 4718 bx r3
80001ba: 4770 bx lr
80001bc: 2000000c .word 0x2000000c
80001c0: 2000000c .word 0x2000000c
80001c4: 00000000 .word 0x00000000
080001c8 <__do_global_dtors_aux>:
80001c8: b510 push {r4, lr}
80001ca: 4c06 ldr r4, [pc, #24] ; (80001e4 <__do_global_dtors_aux+0x1c>)
80001cc: 7823 ldrb r3, [r4, #0]
80001ce: b943 cbnz r3, 80001e2 <__do_global_dtors_aux+0x1a>
80001d0: f7ff ffda bl 8000188 <deregister_tm_clones>
80001d4: 4b04 ldr r3, [pc, #16] ; (80001e8 <__do_global_dtors_aux+0x20>)
80001d6: b113 cbz r3, 80001de <__do_global_dtors_aux+0x16>
80001d8: 4804 ldr r0, [pc, #16] ; (80001ec <__do_global_dtors_aux+0x24>)
80001da: f3af 8000 nop.w
80001de: 2301 movs r3, #1
80001e0: 7023 strb r3, [r4, #0]
80001e2: bd10 pop {r4, pc}
80001e4: 2000000c .word 0x2000000c
80001e8: 00000000 .word 0x00000000
80001ec: 080046ec .word 0x080046ec
080001f0 <frame_dummy>:
80001f0: b508 push {r3, lr}
80001f2: 4b04 ldr r3, [pc, #16] ; (8000204 <frame_dummy+0x14>)
80001f4: b11b cbz r3, 80001fe <frame_dummy+0xe>
80001f6: 4904 ldr r1, [pc, #16] ; (8000208 <frame_dummy+0x18>)
80001f8: 4804 ldr r0, [pc, #16] ; (800020c <frame_dummy+0x1c>)
80001fa: f3af 8000 nop.w
80001fe: e8bd 4008 ldmia.w sp!, {r3, lr}
8000202: e7cf b.n 80001a4 <register_tm_clones>
8000204: 00000000 .word 0x00000000
8000208: 20000010 .word 0x20000010
800020c: 080046ec .word 0x080046ec
08000210 <__libc_init_array>:
8000210: b570 push {r4, r5, r6, lr}
8000212: 4e0d ldr r6, [pc, #52] ; (8000248 <__libc_init_array+0x38>)
8000214: 4d0d ldr r5, [pc, #52] ; (800024c <__libc_init_array+0x3c>)
8000216: 1b76 subs r6, r6, r5
8000218: 10b6 asrs r6, r6, #2
800021a: d006 beq.n 800022a <__libc_init_array+0x1a>
800021c: 2400 movs r4, #0
800021e: f855 3b04 ldr.w r3, [r5], #4
8000222: 3401 adds r4, #1
8000224: 4798 blx r3
8000226: 42a6 cmp r6, r4
8000228: d1f9 bne.n 800021e <__libc_init_array+0xe>
800022a: 4e09 ldr r6, [pc, #36] ; (8000250 <__libc_init_array+0x40>)
800022c: 4d09 ldr r5, [pc, #36] ; (8000254 <__libc_init_array+0x44>)
800022e: 1b76 subs r6, r6, r5
8000230: f004 fa5c bl 80046ec <_init>
8000234: 10b6 asrs r6, r6, #2
8000236: d006 beq.n 8000246 <__libc_init_array+0x36>
8000238: 2400 movs r4, #0
800023a: f855 3b04 ldr.w r3, [r5], #4
800023e: 3401 adds r4, #1
8000240: 4798 blx r3
8000242: 42a6 cmp r6, r4
8000244: d1f9 bne.n 800023a <__libc_init_array+0x2a>
8000246: bd70 pop {r4, r5, r6, pc}
8000248: 08004738 .word 0x08004738
800024c: 08004738 .word 0x08004738
8000250: 08004744 .word 0x08004744
8000254: 08004738 .word 0x08004738
08000258 <memcpy>:
8000258: 4684 mov ip, r0
800025a: ea41 0300 orr.w r3, r1, r0
800025e: f013 0303 ands.w r3, r3, #3
8000262: d16d bne.n 8000340 <memcpy+0xe8>
8000264: 3a40 subs r2, #64 ; 0x40
8000266: d341 bcc.n 80002ec <memcpy+0x94>
8000268: f851 3b04 ldr.w r3, [r1], #4
800026c: f840 3b04 str.w r3, [r0], #4
8000270: f851 3b04 ldr.w r3, [r1], #4
8000274: f840 3b04 str.w r3, [r0], #4
8000278: f851 3b04 ldr.w r3, [r1], #4
800027c: f840 3b04 str.w r3, [r0], #4
8000280: f851 3b04 ldr.w r3, [r1], #4
8000284: f840 3b04 str.w r3, [r0], #4
8000288: f851 3b04 ldr.w r3, [r1], #4
800028c: f840 3b04 str.w r3, [r0], #4
8000290: f851 3b04 ldr.w r3, [r1], #4
8000294: f840 3b04 str.w r3, [r0], #4
8000298: f851 3b04 ldr.w r3, [r1], #4
800029c: f840 3b04 str.w r3, [r0], #4
80002a0: f851 3b04 ldr.w r3, [r1], #4
80002a4: f840 3b04 str.w r3, [r0], #4
80002a8: f851 3b04 ldr.w r3, [r1], #4
80002ac: f840 3b04 str.w r3, [r0], #4
80002b0: f851 3b04 ldr.w r3, [r1], #4
80002b4: f840 3b04 str.w r3, [r0], #4
80002b8: f851 3b04 ldr.w r3, [r1], #4
80002bc: f840 3b04 str.w r3, [r0], #4
80002c0: f851 3b04 ldr.w r3, [r1], #4
80002c4: f840 3b04 str.w r3, [r0], #4
80002c8: f851 3b04 ldr.w r3, [r1], #4
80002cc: f840 3b04 str.w r3, [r0], #4
80002d0: f851 3b04 ldr.w r3, [r1], #4
80002d4: f840 3b04 str.w r3, [r0], #4
80002d8: f851 3b04 ldr.w r3, [r1], #4
80002dc: f840 3b04 str.w r3, [r0], #4
80002e0: f851 3b04 ldr.w r3, [r1], #4
80002e4: f840 3b04 str.w r3, [r0], #4
80002e8: 3a40 subs r2, #64 ; 0x40
80002ea: d2bd bcs.n 8000268 <memcpy+0x10>
80002ec: 3230 adds r2, #48 ; 0x30
80002ee: d311 bcc.n 8000314 <memcpy+0xbc>
80002f0: f851 3b04 ldr.w r3, [r1], #4
80002f4: f840 3b04 str.w r3, [r0], #4
80002f8: f851 3b04 ldr.w r3, [r1], #4
80002fc: f840 3b04 str.w r3, [r0], #4
8000300: f851 3b04 ldr.w r3, [r1], #4
8000304: f840 3b04 str.w r3, [r0], #4
8000308: f851 3b04 ldr.w r3, [r1], #4
800030c: f840 3b04 str.w r3, [r0], #4
8000310: 3a10 subs r2, #16
8000312: d2ed bcs.n 80002f0 <memcpy+0x98>
8000314: 320c adds r2, #12
8000316: d305 bcc.n 8000324 <memcpy+0xcc>
8000318: f851 3b04 ldr.w r3, [r1], #4
800031c: f840 3b04 str.w r3, [r0], #4
8000320: 3a04 subs r2, #4
8000322: d2f9 bcs.n 8000318 <memcpy+0xc0>
8000324: 3204 adds r2, #4
8000326: d008 beq.n 800033a <memcpy+0xe2>
8000328: 07d2 lsls r2, r2, #31
800032a: bf1c itt ne
800032c: f811 3b01 ldrbne.w r3, [r1], #1
8000330: f800 3b01 strbne.w r3, [r0], #1
8000334: d301 bcc.n 800033a <memcpy+0xe2>
8000336: 880b ldrh r3, [r1, #0]
8000338: 8003 strh r3, [r0, #0]
800033a: 4660 mov r0, ip
800033c: 4770 bx lr
800033e: bf00 nop
8000340: 2a08 cmp r2, #8
8000342: d313 bcc.n 800036c <memcpy+0x114>
8000344: 078b lsls r3, r1, #30
8000346: d08d beq.n 8000264 <memcpy+0xc>
8000348: f010 0303 ands.w r3, r0, #3
800034c: d08a beq.n 8000264 <memcpy+0xc>
800034e: f1c3 0304 rsb r3, r3, #4
8000352: 1ad2 subs r2, r2, r3
8000354: 07db lsls r3, r3, #31
8000356: bf1c itt ne
8000358: f811 3b01 ldrbne.w r3, [r1], #1
800035c: f800 3b01 strbne.w r3, [r0], #1
8000360: d380 bcc.n 8000264 <memcpy+0xc>
8000362: f831 3b02 ldrh.w r3, [r1], #2
8000366: f820 3b02 strh.w r3, [r0], #2
800036a: e77b b.n 8000264 <memcpy+0xc>
800036c: 3a04 subs r2, #4
800036e: d3d9 bcc.n 8000324 <memcpy+0xcc>
8000370: 3a01 subs r2, #1
8000372: f811 3b01 ldrb.w r3, [r1], #1
8000376: f800 3b01 strb.w r3, [r0], #1
800037a: d2f9 bcs.n 8000370 <memcpy+0x118>
800037c: 780b ldrb r3, [r1, #0]
800037e: 7003 strb r3, [r0, #0]
8000380: 784b ldrb r3, [r1, #1]
8000382: 7043 strb r3, [r0, #1]
8000384: 788b ldrb r3, [r1, #2]
8000386: 7083 strb r3, [r0, #2]
8000388: 4660 mov r0, ip
800038a: 4770 bx lr
0800038c <memset>:
800038c: 0783 lsls r3, r0, #30
800038e: b530 push {r4, r5, lr}
8000390: d048 beq.n 8000424 <memset+0x98>
8000392: 1e54 subs r4, r2, #1
8000394: 2a00 cmp r2, #0
8000396: d03f beq.n 8000418 <memset+0x8c>
8000398: b2ca uxtb r2, r1
800039a: 4603 mov r3, r0
800039c: e001 b.n 80003a2 <memset+0x16>
800039e: 3c01 subs r4, #1
80003a0: d33a bcc.n 8000418 <memset+0x8c>
80003a2: f803 2b01 strb.w r2, [r3], #1
80003a6: 079d lsls r5, r3, #30
80003a8: d1f9 bne.n 800039e <memset+0x12>
80003aa: 2c03 cmp r4, #3
80003ac: d92d bls.n 800040a <memset+0x7e>
80003ae: b2cd uxtb r5, r1
80003b0: ea45 2505 orr.w r5, r5, r5, lsl #8
80003b4: 2c0f cmp r4, #15
80003b6: ea45 4505 orr.w r5, r5, r5, lsl #16
80003ba: d936 bls.n 800042a <memset+0x9e>
80003bc: f1a4 0210 sub.w r2, r4, #16
80003c0: f022 0c0f bic.w ip, r2, #15
80003c4: f103 0e20 add.w lr, r3, #32
80003c8: 44e6 add lr, ip
80003ca: ea4f 1c12 mov.w ip, r2, lsr #4
80003ce: f103 0210 add.w r2, r3, #16
80003d2: e942 5504 strd r5, r5, [r2, #-16]
80003d6: e942 5502 strd r5, r5, [r2, #-8]
80003da: 3210 adds r2, #16
80003dc: 4572 cmp r2, lr
80003de: d1f8 bne.n 80003d2 <memset+0x46>
80003e0: f10c 0201 add.w r2, ip, #1
80003e4: f014 0f0c tst.w r4, #12
80003e8: eb03 1202 add.w r2, r3, r2, lsl #4
80003ec: f004 0c0f and.w ip, r4, #15
80003f0: d013 beq.n 800041a <memset+0x8e>
80003f2: f1ac 0304 sub.w r3, ip, #4
80003f6: f023 0303 bic.w r3, r3, #3
80003fa: 3304 adds r3, #4
80003fc: 4413 add r3, r2
80003fe: f842 5b04 str.w r5, [r2], #4
8000402: 4293 cmp r3, r2
8000404: d1fb bne.n 80003fe <memset+0x72>
8000406: f00c 0403 and.w r4, ip, #3
800040a: b12c cbz r4, 8000418 <memset+0x8c>
800040c: b2ca uxtb r2, r1
800040e: 441c add r4, r3
8000410: f803 2b01 strb.w r2, [r3], #1
8000414: 429c cmp r4, r3
8000416: d1fb bne.n 8000410 <memset+0x84>
8000418: bd30 pop {r4, r5, pc}
800041a: 4664 mov r4, ip
800041c: 4613 mov r3, r2
800041e: 2c00 cmp r4, #0
8000420: d1f4 bne.n 800040c <memset+0x80>
8000422: e7f9 b.n 8000418 <memset+0x8c>
8000424: 4603 mov r3, r0
8000426: 4614 mov r4, r2
8000428: e7bf b.n 80003aa <memset+0x1e>
800042a: 461a mov r2, r3
800042c: 46a4 mov ip, r4
800042e: e7e0 b.n 80003f2 <memset+0x66>
08000430 <__aeabi_drsub>:
8000430: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000
8000434: e002 b.n 800043c <__adddf3>
8000436: bf00 nop
08000438 <__aeabi_dsub>:
8000438: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000
0800043c <__adddf3>:
800043c: b530 push {r4, r5, lr}
800043e: ea4f 0441 mov.w r4, r1, lsl #1
8000442: ea4f 0543 mov.w r5, r3, lsl #1
8000446: ea94 0f05 teq r4, r5
800044a: bf08 it eq
800044c: ea90 0f02 teqeq r0, r2
8000450: bf1f itttt ne
8000452: ea54 0c00 orrsne.w ip, r4, r0
8000456: ea55 0c02 orrsne.w ip, r5, r2
800045a: ea7f 5c64 mvnsne.w ip, r4, asr #21
800045e: ea7f 5c65 mvnsne.w ip, r5, asr #21
8000462: f000 80e2 beq.w 800062a <__adddf3+0x1ee>
8000466: ea4f 5454 mov.w r4, r4, lsr #21
800046a: ebd4 5555 rsbs r5, r4, r5, lsr #21
800046e: bfb8 it lt
8000470: 426d neglt r5, r5
8000472: dd0c ble.n 800048e <__adddf3+0x52>
8000474: 442c add r4, r5
8000476: ea80 0202 eor.w r2, r0, r2
800047a: ea81 0303 eor.w r3, r1, r3
800047e: ea82 0000 eor.w r0, r2, r0
8000482: ea83 0101 eor.w r1, r3, r1
8000486: ea80 0202 eor.w r2, r0, r2
800048a: ea81 0303 eor.w r3, r1, r3
800048e: 2d36 cmp r5, #54 ; 0x36
8000490: bf88 it hi
8000492: bd30 pophi {r4, r5, pc}
8000494: f011 4f00 tst.w r1, #2147483648 ; 0x80000000
8000498: ea4f 3101 mov.w r1, r1, lsl #12
800049c: f44f 1c80 mov.w ip, #1048576 ; 0x100000
80004a0: ea4c 3111 orr.w r1, ip, r1, lsr #12
80004a4: d002 beq.n 80004ac <__adddf3+0x70>
80004a6: 4240 negs r0, r0
80004a8: eb61 0141 sbc.w r1, r1, r1, lsl #1
80004ac: f013 4f00 tst.w r3, #2147483648 ; 0x80000000
80004b0: ea4f 3303 mov.w r3, r3, lsl #12
80004b4: ea4c 3313 orr.w r3, ip, r3, lsr #12
80004b8: d002 beq.n 80004c0 <__adddf3+0x84>
80004ba: 4252 negs r2, r2
80004bc: eb63 0343 sbc.w r3, r3, r3, lsl #1
80004c0: ea94 0f05 teq r4, r5
80004c4: f000 80a7 beq.w 8000616 <__adddf3+0x1da>
80004c8: f1a4 0401 sub.w r4, r4, #1
80004cc: f1d5 0e20 rsbs lr, r5, #32
80004d0: db0d blt.n 80004ee <__adddf3+0xb2>
80004d2: fa02 fc0e lsl.w ip, r2, lr
80004d6: fa22 f205 lsr.w r2, r2, r5
80004da: 1880 adds r0, r0, r2
80004dc: f141 0100 adc.w r1, r1, #0
80004e0: fa03 f20e lsl.w r2, r3, lr
80004e4: 1880 adds r0, r0, r2
80004e6: fa43 f305 asr.w r3, r3, r5
80004ea: 4159 adcs r1, r3
80004ec: e00e b.n 800050c <__adddf3+0xd0>
80004ee: f1a5 0520 sub.w r5, r5, #32
80004f2: f10e 0e20 add.w lr, lr, #32
80004f6: 2a01 cmp r2, #1
80004f8: fa03 fc0e lsl.w ip, r3, lr
80004fc: bf28 it cs
80004fe: f04c 0c02 orrcs.w ip, ip, #2
8000502: fa43 f305 asr.w r3, r3, r5
8000506: 18c0 adds r0, r0, r3
8000508: eb51 71e3 adcs.w r1, r1, r3, asr #31
800050c: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000
8000510: d507 bpl.n 8000522 <__adddf3+0xe6>
8000512: f04f 0e00 mov.w lr, #0
8000516: f1dc 0c00 rsbs ip, ip, #0
800051a: eb7e 0000 sbcs.w r0, lr, r0
800051e: eb6e 0101 sbc.w r1, lr, r1
8000522: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000
8000526: d31b bcc.n 8000560 <__adddf3+0x124>
8000528: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000
800052c: d30c bcc.n 8000548 <__adddf3+0x10c>
800052e: 0849 lsrs r1, r1, #1
8000530: ea5f 0030 movs.w r0, r0, rrx
8000534: ea4f 0c3c mov.w ip, ip, rrx
8000538: f104 0401 add.w r4, r4, #1
800053c: ea4f 5244 mov.w r2, r4, lsl #21
8000540: f512 0f80 cmn.w r2, #4194304 ; 0x400000
8000544: f080 809a bcs.w 800067c <__adddf3+0x240>
8000548: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000
800054c: bf08 it eq
800054e: ea5f 0c50 movseq.w ip, r0, lsr #1
8000552: f150 0000 adcs.w r0, r0, #0
8000556: eb41 5104 adc.w r1, r1, r4, lsl #20
800055a: ea41 0105 orr.w r1, r1, r5
800055e: bd30 pop {r4, r5, pc}
8000560: ea5f 0c4c movs.w ip, ip, lsl #1
8000564: 4140 adcs r0, r0
8000566: eb41 0101 adc.w r1, r1, r1
800056a: 3c01 subs r4, #1
800056c: bf28 it cs
800056e: f5b1 1f80 cmpcs.w r1, #1048576 ; 0x100000
8000572: d2e9 bcs.n 8000548 <__adddf3+0x10c>
8000574: f091 0f00 teq r1, #0
8000578: bf04 itt eq
800057a: 4601 moveq r1, r0
800057c: 2000 moveq r0, #0
800057e: fab1 f381 clz r3, r1
8000582: bf08 it eq
8000584: 3320 addeq r3, #32
8000586: f1a3 030b sub.w r3, r3, #11
800058a: f1b3 0220 subs.w r2, r3, #32
800058e: da0c bge.n 80005aa <__adddf3+0x16e>
8000590: 320c adds r2, #12
8000592: dd08 ble.n 80005a6 <__adddf3+0x16a>
8000594: f102 0c14 add.w ip, r2, #20
8000598: f1c2 020c rsb r2, r2, #12
800059c: fa01 f00c lsl.w r0, r1, ip
80005a0: fa21 f102 lsr.w r1, r1, r2
80005a4: e00c b.n 80005c0 <__adddf3+0x184>
80005a6: f102 0214 add.w r2, r2, #20
80005aa: bfd8 it le
80005ac: f1c2 0c20 rsble ip, r2, #32
80005b0: fa01 f102 lsl.w r1, r1, r2
80005b4: fa20 fc0c lsr.w ip, r0, ip
80005b8: bfdc itt le
80005ba: ea41 010c orrle.w r1, r1, ip
80005be: 4090 lslle r0, r2
80005c0: 1ae4 subs r4, r4, r3
80005c2: bfa2 ittt ge
80005c4: eb01 5104 addge.w r1, r1, r4, lsl #20
80005c8: 4329 orrge r1, r5
80005ca: bd30 popge {r4, r5, pc}
80005cc: ea6f 0404 mvn.w r4, r4
80005d0: 3c1f subs r4, #31
80005d2: da1c bge.n 800060e <__adddf3+0x1d2>
80005d4: 340c adds r4, #12
80005d6: dc0e bgt.n 80005f6 <__adddf3+0x1ba>
80005d8: f104 0414 add.w r4, r4, #20
80005dc: f1c4 0220 rsb r2, r4, #32
80005e0: fa20 f004 lsr.w r0, r0, r4
80005e4: fa01 f302 lsl.w r3, r1, r2
80005e8: ea40 0003 orr.w r0, r0, r3
80005ec: fa21 f304 lsr.w r3, r1, r4
80005f0: ea45 0103 orr.w r1, r5, r3
80005f4: bd30 pop {r4, r5, pc}
80005f6: f1c4 040c rsb r4, r4, #12
80005fa: f1c4 0220 rsb r2, r4, #32
80005fe: fa20 f002 lsr.w r0, r0, r2
8000602: fa01 f304 lsl.w r3, r1, r4
8000606: ea40 0003 orr.w r0, r0, r3
800060a: 4629 mov r1, r5
800060c: bd30 pop {r4, r5, pc}
800060e: fa21 f004 lsr.w r0, r1, r4
8000612: 4629 mov r1, r5
8000614: bd30 pop {r4, r5, pc}
8000616: f094 0f00 teq r4, #0
800061a: f483 1380 eor.w r3, r3, #1048576 ; 0x100000
800061e: bf06 itte eq
8000620: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000
8000624: 3401 addeq r4, #1
8000626: 3d01 subne r5, #1
8000628: e74e b.n 80004c8 <__adddf3+0x8c>
800062a: ea7f 5c64 mvns.w ip, r4, asr #21
800062e: bf18 it ne
8000630: ea7f 5c65 mvnsne.w ip, r5, asr #21
8000634: d029 beq.n 800068a <__adddf3+0x24e>
8000636: ea94 0f05 teq r4, r5
800063a: bf08 it eq
800063c: ea90 0f02 teqeq r0, r2
8000640: d005 beq.n 800064e <__adddf3+0x212>
8000642: ea54 0c00 orrs.w ip, r4, r0
8000646: bf04 itt eq
8000648: 4619 moveq r1, r3
800064a: 4610 moveq r0, r2
800064c: bd30 pop {r4, r5, pc}
800064e: ea91 0f03 teq r1, r3
8000652: bf1e ittt ne
8000654: 2100 movne r1, #0
8000656: 2000 movne r0, #0
8000658: bd30 popne {r4, r5, pc}
800065a: ea5f 5c54 movs.w ip, r4, lsr #21
800065e: d105 bne.n 800066c <__adddf3+0x230>
8000660: 0040 lsls r0, r0, #1
8000662: 4149 adcs r1, r1
8000664: bf28 it cs
8000666: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000
800066a: bd30 pop {r4, r5, pc}
800066c: f514 0480 adds.w r4, r4, #4194304 ; 0x400000
8000670: bf3c itt cc
8000672: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000
8000676: bd30 popcc {r4, r5, pc}
8000678: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000
800067c: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000
8000680: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000
8000684: f04f 0000 mov.w r0, #0
8000688: bd30 pop {r4, r5, pc}
800068a: ea7f 5c64 mvns.w ip, r4, asr #21
800068e: bf1a itte ne
8000690: 4619 movne r1, r3
8000692: 4610 movne r0, r2
8000694: ea7f 5c65 mvnseq.w ip, r5, asr #21
8000698: bf1c itt ne
800069a: 460b movne r3, r1
800069c: 4602 movne r2, r0
800069e: ea50 3401 orrs.w r4, r0, r1, lsl #12
80006a2: bf06 itte eq
80006a4: ea52 3503 orrseq.w r5, r2, r3, lsl #12
80006a8: ea91 0f03 teqeq r1, r3
80006ac: f441 2100 orrne.w r1, r1, #524288 ; 0x80000
80006b0: bd30 pop {r4, r5, pc}
80006b2: bf00 nop
080006b4 <__aeabi_ui2d>:
80006b4: f090 0f00 teq r0, #0
80006b8: bf04 itt eq
80006ba: 2100 moveq r1, #0
80006bc: 4770 bxeq lr
80006be: b530 push {r4, r5, lr}
80006c0: f44f 6480 mov.w r4, #1024 ; 0x400
80006c4: f104 0432 add.w r4, r4, #50 ; 0x32
80006c8: f04f 0500 mov.w r5, #0
80006cc: f04f 0100 mov.w r1, #0
80006d0: e750 b.n 8000574 <__adddf3+0x138>
80006d2: bf00 nop
080006d4 <__aeabi_i2d>:
80006d4: f090 0f00 teq r0, #0
80006d8: bf04 itt eq
80006da: 2100 moveq r1, #0
80006dc: 4770 bxeq lr
80006de: b530 push {r4, r5, lr}
80006e0: f44f 6480 mov.w r4, #1024 ; 0x400
80006e4: f104 0432 add.w r4, r4, #50 ; 0x32
80006e8: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000
80006ec: bf48 it mi
80006ee: 4240 negmi r0, r0
80006f0: f04f 0100 mov.w r1, #0
80006f4: e73e b.n 8000574 <__adddf3+0x138>
80006f6: bf00 nop
080006f8 <__aeabi_f2d>:
80006f8: 0042 lsls r2, r0, #1
80006fa: ea4f 01e2 mov.w r1, r2, asr #3
80006fe: ea4f 0131 mov.w r1, r1, rrx
8000702: ea4f 7002 mov.w r0, r2, lsl #28
8000706: bf1f itttt ne
8000708: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000
800070c: f093 4f7f teqne r3, #4278190080 ; 0xff000000
8000710: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000
8000714: 4770 bxne lr
8000716: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000
800071a: bf08 it eq
800071c: 4770 bxeq lr
800071e: f093 4f7f teq r3, #4278190080 ; 0xff000000
8000722: bf04 itt eq
8000724: f441 2100 orreq.w r1, r1, #524288 ; 0x80000
8000728: 4770 bxeq lr
800072a: b530 push {r4, r5, lr}
800072c: f44f 7460 mov.w r4, #896 ; 0x380
8000730: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000
8000734: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000
8000738: e71c b.n 8000574 <__adddf3+0x138>
800073a: bf00 nop
0800073c <__aeabi_ul2d>:
800073c: ea50 0201 orrs.w r2, r0, r1
8000740: bf08 it eq
8000742: 4770 bxeq lr
8000744: b530 push {r4, r5, lr}
8000746: f04f 0500 mov.w r5, #0
800074a: e00a b.n 8000762 <__aeabi_l2d+0x16>
0800074c <__aeabi_l2d>:
800074c: ea50 0201 orrs.w r2, r0, r1
8000750: bf08 it eq
8000752: 4770 bxeq lr
8000754: b530 push {r4, r5, lr}
8000756: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000
800075a: d502 bpl.n 8000762 <__aeabi_l2d+0x16>
800075c: 4240 negs r0, r0
800075e: eb61 0141 sbc.w r1, r1, r1, lsl #1
8000762: f44f 6480 mov.w r4, #1024 ; 0x400
8000766: f104 0432 add.w r4, r4, #50 ; 0x32
800076a: ea5f 5c91 movs.w ip, r1, lsr #22
800076e: f43f aed8 beq.w 8000522 <__adddf3+0xe6>
8000772: f04f 0203 mov.w r2, #3
8000776: ea5f 0cdc movs.w ip, ip, lsr #3
800077a: bf18 it ne
800077c: 3203 addne r2, #3
800077e: ea5f 0cdc movs.w ip, ip, lsr #3
8000782: bf18 it ne
8000784: 3203 addne r2, #3
8000786: eb02 02dc add.w r2, r2, ip, lsr #3
800078a: f1c2 0320 rsb r3, r2, #32
800078e: fa00 fc03 lsl.w ip, r0, r3
8000792: fa20 f002 lsr.w r0, r0, r2
8000796: fa01 fe03 lsl.w lr, r1, r3
800079a: ea40 000e orr.w r0, r0, lr
800079e: fa21 f102 lsr.w r1, r1, r2
80007a2: 4414 add r4, r2
80007a4: e6bd b.n 8000522 <__adddf3+0xe6>
80007a6: bf00 nop
080007a8 <__aeabi_dmul>:
80007a8: b570 push {r4, r5, r6, lr}
80007aa: f04f 0cff mov.w ip, #255 ; 0xff
80007ae: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700
80007b2: ea1c 5411 ands.w r4, ip, r1, lsr #20
80007b6: bf1d ittte ne
80007b8: ea1c 5513 andsne.w r5, ip, r3, lsr #20
80007bc: ea94 0f0c teqne r4, ip
80007c0: ea95 0f0c teqne r5, ip
80007c4: f000 f8de bleq 8000984 <__aeabi_dmul+0x1dc>
80007c8: 442c add r4, r5
80007ca: ea81 0603 eor.w r6, r1, r3
80007ce: ea21 514c bic.w r1, r1, ip, lsl #21
80007d2: ea23 534c bic.w r3, r3, ip, lsl #21
80007d6: ea50 3501 orrs.w r5, r0, r1, lsl #12
80007da: bf18 it ne
80007dc: ea52 3503 orrsne.w r5, r2, r3, lsl #12
80007e0: f441 1180 orr.w r1, r1, #1048576 ; 0x100000
80007e4: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
80007e8: d038 beq.n 800085c <__aeabi_dmul+0xb4>
80007ea: fba0 ce02 umull ip, lr, r0, r2
80007ee: f04f 0500 mov.w r5, #0
80007f2: fbe1 e502 umlal lr, r5, r1, r2
80007f6: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000
80007fa: fbe0 e503 umlal lr, r5, r0, r3
80007fe: f04f 0600 mov.w r6, #0
8000802: fbe1 5603 umlal r5, r6, r1, r3
8000806: f09c 0f00 teq ip, #0
800080a: bf18 it ne
800080c: f04e 0e01 orrne.w lr, lr, #1
8000810: f1a4 04ff sub.w r4, r4, #255 ; 0xff
8000814: f5b6 7f00 cmp.w r6, #512 ; 0x200
8000818: f564 7440 sbc.w r4, r4, #768 ; 0x300
800081c: d204 bcs.n 8000828 <__aeabi_dmul+0x80>
800081e: ea5f 0e4e movs.w lr, lr, lsl #1
8000822: 416d adcs r5, r5
8000824: eb46 0606 adc.w r6, r6, r6
8000828: ea42 21c6 orr.w r1, r2, r6, lsl #11
800082c: ea41 5155 orr.w r1, r1, r5, lsr #21
8000830: ea4f 20c5 mov.w r0, r5, lsl #11
8000834: ea40 505e orr.w r0, r0, lr, lsr #21
8000838: ea4f 2ece mov.w lr, lr, lsl #11
800083c: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd
8000840: bf88 it hi
8000842: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700
8000846: d81e bhi.n 8000886 <__aeabi_dmul+0xde>
8000848: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000
800084c: bf08 it eq
800084e: ea5f 0e50 movseq.w lr, r0, lsr #1
8000852: f150 0000 adcs.w r0, r0, #0
8000856: eb41 5104 adc.w r1, r1, r4, lsl #20
800085a: bd70 pop {r4, r5, r6, pc}
800085c: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000
8000860: ea46 0101 orr.w r1, r6, r1
8000864: ea40 0002 orr.w r0, r0, r2
8000868: ea81 0103 eor.w r1, r1, r3
800086c: ebb4 045c subs.w r4, r4, ip, lsr #1
8000870: bfc2 ittt gt
8000872: ebd4 050c rsbsgt r5, r4, ip
8000876: ea41 5104 orrgt.w r1, r1, r4, lsl #20
800087a: bd70 popgt {r4, r5, r6, pc}
800087c: f441 1180 orr.w r1, r1, #1048576 ; 0x100000
8000880: f04f 0e00 mov.w lr, #0
8000884: 3c01 subs r4, #1
8000886: f300 80ab bgt.w 80009e0 <__aeabi_dmul+0x238>
800088a: f114 0f36 cmn.w r4, #54 ; 0x36
800088e: bfde ittt le
8000890: 2000 movle r0, #0
8000892: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000
8000896: bd70 pople {r4, r5, r6, pc}
8000898: f1c4 0400 rsb r4, r4, #0
800089c: 3c20 subs r4, #32
800089e: da35 bge.n 800090c <__aeabi_dmul+0x164>
80008a0: 340c adds r4, #12
80008a2: dc1b bgt.n 80008dc <__aeabi_dmul+0x134>
80008a4: f104 0414 add.w r4, r4, #20
80008a8: f1c4 0520 rsb r5, r4, #32
80008ac: fa00 f305 lsl.w r3, r0, r5
80008b0: fa20 f004 lsr.w r0, r0, r4
80008b4: fa01 f205 lsl.w r2, r1, r5
80008b8: ea40 0002 orr.w r0, r0, r2
80008bc: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000
80008c0: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000
80008c4: eb10 70d3 adds.w r0, r0, r3, lsr #31
80008c8: fa21 f604 lsr.w r6, r1, r4
80008cc: eb42 0106 adc.w r1, r2, r6
80008d0: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
80008d4: bf08 it eq
80008d6: ea20 70d3 biceq.w r0, r0, r3, lsr #31
80008da: bd70 pop {r4, r5, r6, pc}
80008dc: f1c4 040c rsb r4, r4, #12
80008e0: f1c4 0520 rsb r5, r4, #32
80008e4: fa00 f304 lsl.w r3, r0, r4
80008e8: fa20 f005 lsr.w r0, r0, r5
80008ec: fa01 f204 lsl.w r2, r1, r4
80008f0: ea40 0002 orr.w r0, r0, r2
80008f4: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
80008f8: eb10 70d3 adds.w r0, r0, r3, lsr #31
80008fc: f141 0100 adc.w r1, r1, #0
8000900: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
8000904: bf08 it eq
8000906: ea20 70d3 biceq.w r0, r0, r3, lsr #31
800090a: bd70 pop {r4, r5, r6, pc}
800090c: f1c4 0520 rsb r5, r4, #32
8000910: fa00 f205 lsl.w r2, r0, r5
8000914: ea4e 0e02 orr.w lr, lr, r2
8000918: fa20 f304 lsr.w r3, r0, r4
800091c: fa01 f205 lsl.w r2, r1, r5
8000920: ea43 0302 orr.w r3, r3, r2
8000924: fa21 f004 lsr.w r0, r1, r4
8000928: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
800092c: fa21 f204 lsr.w r2, r1, r4
8000930: ea20 0002 bic.w r0, r0, r2
8000934: eb00 70d3 add.w r0, r0, r3, lsr #31
8000938: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
800093c: bf08 it eq
800093e: ea20 70d3 biceq.w r0, r0, r3, lsr #31
8000942: bd70 pop {r4, r5, r6, pc}
8000944: f094 0f00 teq r4, #0
8000948: d10f bne.n 800096a <__aeabi_dmul+0x1c2>
800094a: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000
800094e: 0040 lsls r0, r0, #1
8000950: eb41 0101 adc.w r1, r1, r1
8000954: f411 1f80 tst.w r1, #1048576 ; 0x100000
8000958: bf08 it eq
800095a: 3c01 subeq r4, #1
800095c: d0f7 beq.n 800094e <__aeabi_dmul+0x1a6>
800095e: ea41 0106 orr.w r1, r1, r6
8000962: f095 0f00 teq r5, #0
8000966: bf18 it ne
8000968: 4770 bxne lr
800096a: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000
800096e: 0052 lsls r2, r2, #1
8000970: eb43 0303 adc.w r3, r3, r3
8000974: f413 1f80 tst.w r3, #1048576 ; 0x100000
8000978: bf08 it eq
800097a: 3d01 subeq r5, #1
800097c: d0f7 beq.n 800096e <__aeabi_dmul+0x1c6>
800097e: ea43 0306 orr.w r3, r3, r6
8000982: 4770 bx lr
8000984: ea94 0f0c teq r4, ip
8000988: ea0c 5513 and.w r5, ip, r3, lsr #20
800098c: bf18 it ne
800098e: ea95 0f0c teqne r5, ip
8000992: d00c beq.n 80009ae <__aeabi_dmul+0x206>
8000994: ea50 0641 orrs.w r6, r0, r1, lsl #1
8000998: bf18 it ne
800099a: ea52 0643 orrsne.w r6, r2, r3, lsl #1
800099e: d1d1 bne.n 8000944 <__aeabi_dmul+0x19c>
80009a0: ea81 0103 eor.w r1, r1, r3
80009a4: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
80009a8: f04f 0000 mov.w r0, #0
80009ac: bd70 pop {r4, r5, r6, pc}
80009ae: ea50 0641 orrs.w r6, r0, r1, lsl #1
80009b2: bf06 itte eq
80009b4: 4610 moveq r0, r2
80009b6: 4619 moveq r1, r3
80009b8: ea52 0643 orrsne.w r6, r2, r3, lsl #1
80009bc: d019 beq.n 80009f2 <__aeabi_dmul+0x24a>
80009be: ea94 0f0c teq r4, ip
80009c2: d102 bne.n 80009ca <__aeabi_dmul+0x222>
80009c4: ea50 3601 orrs.w r6, r0, r1, lsl #12
80009c8: d113 bne.n 80009f2 <__aeabi_dmul+0x24a>
80009ca: ea95 0f0c teq r5, ip
80009ce: d105 bne.n 80009dc <__aeabi_dmul+0x234>
80009d0: ea52 3603 orrs.w r6, r2, r3, lsl #12
80009d4: bf1c itt ne
80009d6: 4610 movne r0, r2
80009d8: 4619 movne r1, r3
80009da: d10a bne.n 80009f2 <__aeabi_dmul+0x24a>
80009dc: ea81 0103 eor.w r1, r1, r3
80009e0: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
80009e4: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000
80009e8: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000
80009ec: f04f 0000 mov.w r0, #0
80009f0: bd70 pop {r4, r5, r6, pc}
80009f2: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000
80009f6: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000
80009fa: bd70 pop {r4, r5, r6, pc}
080009fc <__aeabi_ddiv>:
80009fc: b570 push {r4, r5, r6, lr}
80009fe: f04f 0cff mov.w ip, #255 ; 0xff
8000a02: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700
8000a06: ea1c 5411 ands.w r4, ip, r1, lsr #20
8000a0a: bf1d ittte ne
8000a0c: ea1c 5513 andsne.w r5, ip, r3, lsr #20
8000a10: ea94 0f0c teqne r4, ip
8000a14: ea95 0f0c teqne r5, ip
8000a18: f000 f8a7 bleq 8000b6a <__aeabi_ddiv+0x16e>
8000a1c: eba4 0405 sub.w r4, r4, r5
8000a20: ea81 0e03 eor.w lr, r1, r3
8000a24: ea52 3503 orrs.w r5, r2, r3, lsl #12
8000a28: ea4f 3101 mov.w r1, r1, lsl #12
8000a2c: f000 8088 beq.w 8000b40 <__aeabi_ddiv+0x144>
8000a30: ea4f 3303 mov.w r3, r3, lsl #12
8000a34: f04f 5580 mov.w r5, #268435456 ; 0x10000000
8000a38: ea45 1313 orr.w r3, r5, r3, lsr #4
8000a3c: ea43 6312 orr.w r3, r3, r2, lsr #24
8000a40: ea4f 2202 mov.w r2, r2, lsl #8
8000a44: ea45 1511 orr.w r5, r5, r1, lsr #4
8000a48: ea45 6510 orr.w r5, r5, r0, lsr #24
8000a4c: ea4f 2600 mov.w r6, r0, lsl #8
8000a50: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000
8000a54: 429d cmp r5, r3
8000a56: bf08 it eq
8000a58: 4296 cmpeq r6, r2
8000a5a: f144 04fd adc.w r4, r4, #253 ; 0xfd
8000a5e: f504 7440 add.w r4, r4, #768 ; 0x300
8000a62: d202 bcs.n 8000a6a <__aeabi_ddiv+0x6e>
8000a64: 085b lsrs r3, r3, #1
8000a66: ea4f 0232 mov.w r2, r2, rrx
8000a6a: 1ab6 subs r6, r6, r2
8000a6c: eb65 0503 sbc.w r5, r5, r3
8000a70: 085b lsrs r3, r3, #1
8000a72: ea4f 0232 mov.w r2, r2, rrx
8000a76: f44f 1080 mov.w r0, #1048576 ; 0x100000
8000a7a: f44f 2c00 mov.w ip, #524288 ; 0x80000
8000a7e: ebb6 0e02 subs.w lr, r6, r2
8000a82: eb75 0e03 sbcs.w lr, r5, r3
8000a86: bf22 ittt cs
8000a88: 1ab6 subcs r6, r6, r2
8000a8a: 4675 movcs r5, lr
8000a8c: ea40 000c orrcs.w r0, r0, ip
8000a90: 085b lsrs r3, r3, #1
8000a92: ea4f 0232 mov.w r2, r2, rrx
8000a96: ebb6 0e02 subs.w lr, r6, r2
8000a9a: eb75 0e03 sbcs.w lr, r5, r3
8000a9e: bf22 ittt cs
8000aa0: 1ab6 subcs r6, r6, r2
8000aa2: 4675 movcs r5, lr
8000aa4: ea40 005c orrcs.w r0, r0, ip, lsr #1
8000aa8: 085b lsrs r3, r3, #1
8000aaa: ea4f 0232 mov.w r2, r2, rrx
8000aae: ebb6 0e02 subs.w lr, r6, r2
8000ab2: eb75 0e03 sbcs.w lr, r5, r3
8000ab6: bf22 ittt cs
8000ab8: 1ab6 subcs r6, r6, r2
8000aba: 4675 movcs r5, lr
8000abc: ea40 009c orrcs.w r0, r0, ip, lsr #2
8000ac0: 085b lsrs r3, r3, #1
8000ac2: ea4f 0232 mov.w r2, r2, rrx
8000ac6: ebb6 0e02 subs.w lr, r6, r2
8000aca: eb75 0e03 sbcs.w lr, r5, r3
8000ace: bf22 ittt cs
8000ad0: 1ab6 subcs r6, r6, r2
8000ad2: 4675 movcs r5, lr
8000ad4: ea40 00dc orrcs.w r0, r0, ip, lsr #3
8000ad8: ea55 0e06 orrs.w lr, r5, r6
8000adc: d018 beq.n 8000b10 <__aeabi_ddiv+0x114>
8000ade: ea4f 1505 mov.w r5, r5, lsl #4
8000ae2: ea45 7516 orr.w r5, r5, r6, lsr #28
8000ae6: ea4f 1606 mov.w r6, r6, lsl #4
8000aea: ea4f 03c3 mov.w r3, r3, lsl #3
8000aee: ea43 7352 orr.w r3, r3, r2, lsr #29
8000af2: ea4f 02c2 mov.w r2, r2, lsl #3
8000af6: ea5f 1c1c movs.w ip, ip, lsr #4
8000afa: d1c0 bne.n 8000a7e <__aeabi_ddiv+0x82>
8000afc: f411 1f80 tst.w r1, #1048576 ; 0x100000
8000b00: d10b bne.n 8000b1a <__aeabi_ddiv+0x11e>
8000b02: ea41 0100 orr.w r1, r1, r0
8000b06: f04f 0000 mov.w r0, #0
8000b0a: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000
8000b0e: e7b6 b.n 8000a7e <__aeabi_ddiv+0x82>
8000b10: f411 1f80 tst.w r1, #1048576 ; 0x100000
8000b14: bf04 itt eq
8000b16: 4301 orreq r1, r0
8000b18: 2000 moveq r0, #0
8000b1a: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd
8000b1e: bf88 it hi
8000b20: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700
8000b24: f63f aeaf bhi.w 8000886 <__aeabi_dmul+0xde>
8000b28: ebb5 0c03 subs.w ip, r5, r3
8000b2c: bf04 itt eq
8000b2e: ebb6 0c02 subseq.w ip, r6, r2
8000b32: ea5f 0c50 movseq.w ip, r0, lsr #1
8000b36: f150 0000 adcs.w r0, r0, #0
8000b3a: eb41 5104 adc.w r1, r1, r4, lsl #20
8000b3e: bd70 pop {r4, r5, r6, pc}
8000b40: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000
8000b44: ea4e 3111 orr.w r1, lr, r1, lsr #12
8000b48: eb14 045c adds.w r4, r4, ip, lsr #1
8000b4c: bfc2 ittt gt
8000b4e: ebd4 050c rsbsgt r5, r4, ip
8000b52: ea41 5104 orrgt.w r1, r1, r4, lsl #20
8000b56: bd70 popgt {r4, r5, r6, pc}
8000b58: f441 1180 orr.w r1, r1, #1048576 ; 0x100000
8000b5c: f04f 0e00 mov.w lr, #0
8000b60: 3c01 subs r4, #1
8000b62: e690 b.n 8000886 <__aeabi_dmul+0xde>
8000b64: ea45 0e06 orr.w lr, r5, r6
8000b68: e68d b.n 8000886 <__aeabi_dmul+0xde>
8000b6a: ea0c 5513 and.w r5, ip, r3, lsr #20
8000b6e: ea94 0f0c teq r4, ip
8000b72: bf08 it eq
8000b74: ea95 0f0c teqeq r5, ip
8000b78: f43f af3b beq.w 80009f2 <__aeabi_dmul+0x24a>
8000b7c: ea94 0f0c teq r4, ip
8000b80: d10a bne.n 8000b98 <__aeabi_ddiv+0x19c>
8000b82: ea50 3401 orrs.w r4, r0, r1, lsl #12
8000b86: f47f af34 bne.w 80009f2 <__aeabi_dmul+0x24a>
8000b8a: ea95 0f0c teq r5, ip
8000b8e: f47f af25 bne.w 80009dc <__aeabi_dmul+0x234>
8000b92: 4610 mov r0, r2
8000b94: 4619 mov r1, r3
8000b96: e72c b.n 80009f2 <__aeabi_dmul+0x24a>
8000b98: ea95 0f0c teq r5, ip
8000b9c: d106 bne.n 8000bac <__aeabi_ddiv+0x1b0>
8000b9e: ea52 3503 orrs.w r5, r2, r3, lsl #12
8000ba2: f43f aefd beq.w 80009a0 <__aeabi_dmul+0x1f8>
8000ba6: 4610 mov r0, r2
8000ba8: 4619 mov r1, r3
8000baa: e722 b.n 80009f2 <__aeabi_dmul+0x24a>
8000bac: ea50 0641 orrs.w r6, r0, r1, lsl #1
8000bb0: bf18 it ne
8000bb2: ea52 0643 orrsne.w r6, r2, r3, lsl #1
8000bb6: f47f aec5 bne.w 8000944 <__aeabi_dmul+0x19c>
8000bba: ea50 0441 orrs.w r4, r0, r1, lsl #1
8000bbe: f47f af0d bne.w 80009dc <__aeabi_dmul+0x234>
8000bc2: ea52 0543 orrs.w r5, r2, r3, lsl #1
8000bc6: f47f aeeb bne.w 80009a0 <__aeabi_dmul+0x1f8>
8000bca: e712 b.n 80009f2 <__aeabi_dmul+0x24a>
08000bcc <__aeabi_d2iz>:
8000bcc: ea4f 0241 mov.w r2, r1, lsl #1
8000bd0: f512 1200 adds.w r2, r2, #2097152 ; 0x200000
8000bd4: d215 bcs.n 8000c02 <__aeabi_d2iz+0x36>
8000bd6: d511 bpl.n 8000bfc <__aeabi_d2iz+0x30>
8000bd8: f46f 7378 mvn.w r3, #992 ; 0x3e0
8000bdc: ebb3 5262 subs.w r2, r3, r2, asr #21
8000be0: d912 bls.n 8000c08 <__aeabi_d2iz+0x3c>
8000be2: ea4f 23c1 mov.w r3, r1, lsl #11
8000be6: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000
8000bea: ea43 5350 orr.w r3, r3, r0, lsr #21
8000bee: f011 4f00 tst.w r1, #2147483648 ; 0x80000000
8000bf2: fa23 f002 lsr.w r0, r3, r2
8000bf6: bf18 it ne
8000bf8: 4240 negne r0, r0
8000bfa: 4770 bx lr
8000bfc: f04f 0000 mov.w r0, #0
8000c00: 4770 bx lr
8000c02: ea50 3001 orrs.w r0, r0, r1, lsl #12
8000c06: d105 bne.n 8000c14 <__aeabi_d2iz+0x48>
8000c08: f011 4000 ands.w r0, r1, #2147483648 ; 0x80000000
8000c0c: bf08 it eq
8000c0e: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000
8000c12: 4770 bx lr
8000c14: f04f 0000 mov.w r0, #0
8000c18: 4770 bx lr
8000c1a: bf00 nop
08000c1c <__aeabi_d2uiz>:
8000c1c: 004a lsls r2, r1, #1
8000c1e: d211 bcs.n 8000c44 <__aeabi_d2uiz+0x28>
8000c20: f512 1200 adds.w r2, r2, #2097152 ; 0x200000
8000c24: d211 bcs.n 8000c4a <__aeabi_d2uiz+0x2e>
8000c26: d50d bpl.n 8000c44 <__aeabi_d2uiz+0x28>
8000c28: f46f 7378 mvn.w r3, #992 ; 0x3e0
8000c2c: ebb3 5262 subs.w r2, r3, r2, asr #21
8000c30: d40e bmi.n 8000c50 <__aeabi_d2uiz+0x34>
8000c32: ea4f 23c1 mov.w r3, r1, lsl #11
8000c36: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000
8000c3a: ea43 5350 orr.w r3, r3, r0, lsr #21
8000c3e: fa23 f002 lsr.w r0, r3, r2
8000c42: 4770 bx lr
8000c44: f04f 0000 mov.w r0, #0
8000c48: 4770 bx lr
8000c4a: ea50 3001 orrs.w r0, r0, r1, lsl #12
8000c4e: d102 bne.n 8000c56 <__aeabi_d2uiz+0x3a>
8000c50: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
8000c54: 4770 bx lr
8000c56: f04f 0000 mov.w r0, #0
8000c5a: 4770 bx lr
08000c5c <_ZNSt14_Function_baseC1Ev>:
static void
_M_init_functor(_Any_data& __functor, _Functor&& __f, false_type)
{ __functor._M_access<_Functor*>() = new _Functor(std::move(__f)); }
};
_Function_base() : _M_manager(nullptr) { }
8000c5c: b480 push {r7}
8000c5e: b083 sub sp, #12
8000c60: af00 add r7, sp, #0
8000c62: 6078 str r0, [r7, #4]
8000c64: 687b ldr r3, [r7, #4]
8000c66: 2200 movs r2, #0
8000c68: 609a str r2, [r3, #8]
8000c6a: 687b ldr r3, [r7, #4]
8000c6c: 4618 mov r0, r3
8000c6e: 370c adds r7, #12
8000c70: 46bd mov sp, r7
8000c72: f85d 7b04 ldr.w r7, [sp], #4
8000c76: 4770 bx lr
08000c78 <_ZNSt14_Function_baseD1Ev>:
~_Function_base()
8000c78: b580 push {r7, lr}
8000c7a: b082 sub sp, #8
8000c7c: af00 add r7, sp, #0
8000c7e: 6078 str r0, [r7, #4]
{
if (_M_manager)
8000c80: 687b ldr r3, [r7, #4]
8000c82: 689b ldr r3, [r3, #8]
8000c84: 2b00 cmp r3, #0
8000c86: d005 beq.n 8000c94 <_ZNSt14_Function_baseD1Ev+0x1c>
_M_manager(_M_functor, _M_functor, __destroy_functor);
8000c88: 687b ldr r3, [r7, #4]
8000c8a: 689b ldr r3, [r3, #8]
8000c8c: 6878 ldr r0, [r7, #4]
8000c8e: 6879 ldr r1, [r7, #4]
8000c90: 2203 movs r2, #3
8000c92: 4798 blx r3
}
8000c94: 687b ldr r3, [r7, #4]
8000c96: 4618 mov r0, r3
8000c98: 3708 adds r7, #8
8000c9a: 46bd mov sp, r7
8000c9c: bd80 pop {r7, pc}
08000c9e <_ZNSt8functionIFv20can1_vn200_gnss_ll_tN6canlib5frame7decoded4can115vn200_gnss_ll_tEEED1Ev>:
* @ingroup functors
*
* Polymorphic function wrapper.
*/
template<typename _Res, typename... _ArgTypes>
class function<_Res(_ArgTypes...)>
8000c9e: b580 push {r7, lr}
8000ca0: b082 sub sp, #8
8000ca2: af00 add r7, sp, #0
8000ca4: 6078 str r0, [r7, #4]
8000ca6: 687b ldr r3, [r7, #4]
8000ca8: 4618 mov r0, r3
8000caa: f7ff ffe5 bl 8000c78 <_ZNSt14_Function_baseD1Ev>
8000cae: 687b ldr r3, [r7, #4]
8000cb0: 4618 mov r0, r3
8000cb2: 3708 adds r7, #8
8000cb4: 46bd mov sp, r7
8000cb6: bd80 pop {r7, pc}
08000cb8 <_ZNSt8functionIFv20can1_vn200_ins_ypr_tN6canlib5frame7decoded4can115vn200_ins_ypr_tEEED1Ev>:
8000cb8: b580 push {r7, lr}
8000cba: b082 sub sp, #8
8000cbc: af00 add r7, sp, #0
8000cbe: 6078 str r0, [r7, #4]
8000cc0: 687b ldr r3, [r7, #4]
8000cc2: 4618 mov r0, r3
8000cc4: f7ff ffd8 bl 8000c78 <_ZNSt14_Function_baseD1Ev>
8000cc8: 687b ldr r3, [r7, #4]
8000cca: 4618 mov r0, r3
8000ccc: 3708 adds r7, #8
8000cce: 46bd mov sp, r7
8000cd0: bd80 pop {r7, pc}
08000cd2 <_ZNSt8functionIFv24can1_vn200_imu_acc_lin_tN6canlib5frame7decoded4can119vn200_imu_acc_lin_tEEED1Ev>:
8000cd2: b580 push {r7, lr}
8000cd4: b082 sub sp, #8
8000cd6: af00 add r7, sp, #0
8000cd8: 6078 str r0, [r7, #4]
8000cda: 687b ldr r3, [r7, #4]
8000cdc: 4618 mov r0, r3
8000cde: f7ff ffcb bl 8000c78 <_ZNSt14_Function_baseD1Ev>
8000ce2: 687b ldr r3, [r7, #4]
8000ce4: 4618 mov r0, r3
8000ce6: 3708 adds r7, #8
8000ce8: 46bd mov sp, r7
8000cea: bd80 pop {r7, pc}
08000cec <_ZNSt8functionIFv24can1_vn200_imu_acc_ang_tN6canlib5frame7decoded4can119vn200_imu_acc_ang_tEEED1Ev>:
8000cec: b580 push {r7, lr}
8000cee: b082 sub sp, #8
8000cf0: af00 add r7, sp, #0
8000cf2: 6078 str r0, [r7, #4]
8000cf4: 687b ldr r3, [r7, #4]
8000cf6: 4618 mov r0, r3
8000cf8: f7ff ffbe bl 8000c78 <_ZNSt14_Function_baseD1Ev>
8000cfc: 687b ldr r3, [r7, #4]
8000cfe: 4618 mov r0, r3
8000d00: 3708 adds r7, #8
8000d02: 46bd mov sp, r7
8000d04: bd80 pop {r7, pc}
08000d06 <_ZNSt8functionIFv19can1_vn200_ins_ll_tN6canlib5frame7decoded4can114vn200_ins_ll_tEEED1Ev>:
8000d06: b580 push {r7, lr}
8000d08: b082 sub sp, #8
8000d0a: af00 add r7, sp, #0
8000d0c: 6078 str r0, [r7, #4]
8000d0e: 687b ldr r3, [r7, #4]
8000d10: 4618 mov r0, r3
8000d12: f7ff ffb1 bl 8000c78 <_ZNSt14_Function_baseD1Ev>
8000d16: 687b ldr r3, [r7, #4]
8000d18: 4618 mov r0, r3
8000d1a: 3708 adds r7, #8
8000d1c: 46bd mov sp, r7
8000d1e: bd80 pop {r7, pc}
08000d20 <_ZNSt8functionIFv20can1_vn200_ins_vel_tN6canlib5frame7decoded4can115vn200_ins_vel_tEEED1Ev>:
8000d20: b580 push {r7, lr}
8000d22: b082 sub sp, #8
8000d24: af00 add r7, sp, #0
8000d26: 6078 str r0, [r7, #4]
8000d28: 687b ldr r3, [r7, #4]
8000d2a: 4618 mov r0, r3
8000d2c: f7ff ffa4 bl 8000c78 <_ZNSt14_Function_baseD1Ev>
8000d30: 687b ldr r3, [r7, #4]
8000d32: 4618 mov r0, r3
8000d34: 3708 adds r7, #8
8000d36: 46bd mov sp, r7
8000d38: bd80 pop {r7, pc}
08000d3a <_ZNSt8functionIFv20can1_vn200_gnss_ll_tN6canlib5frame7decoded4can115vn200_gnss_ll_tEEEC1EDn>:
/**
* @brief Creates an empty function call wrapper.
* @post @c !(bool)*this
*/
function(nullptr_t) noexcept
8000d3a: b580 push {r7, lr}
8000d3c: b082 sub sp, #8
8000d3e: af00 add r7, sp, #0
8000d40: 6078 str r0, [r7, #4]
8000d42: 6039 str r1, [r7, #0]
: _Function_base() { }
8000d44: 687b ldr r3, [r7, #4]
8000d46: 4618 mov r0, r3
8000d48: f7ff ff88 bl 8000c5c <_ZNSt14_Function_baseC1Ev>
8000d4c: 687b ldr r3, [r7, #4]
8000d4e: 4618 mov r0, r3
8000d50: 3708 adds r7, #8
8000d52: 46bd mov sp, r7
8000d54: bd80 pop {r7, pc}
08000d56 <_ZNSt8functionIFv20can1_vn200_ins_ypr_tN6canlib5frame7decoded4can115vn200_ins_ypr_tEEEC1EDn>:
function(nullptr_t) noexcept
8000d56: b580 push {r7, lr}
8000d58: b082 sub sp, #8
8000d5a: af00 add r7, sp, #0
8000d5c: 6078 str r0, [r7, #4]
8000d5e: 6039 str r1, [r7, #0]
: _Function_base() { }
8000d60: 687b ldr r3, [r7, #4]
8000d62: 4618 mov r0, r3
8000d64: f7ff ff7a bl 8000c5c <_ZNSt14_Function_baseC1Ev>
8000d68: 687b ldr r3, [r7, #4]
8000d6a: 4618 mov r0, r3
8000d6c: 3708 adds r7, #8
8000d6e: 46bd mov sp, r7
8000d70: bd80 pop {r7, pc}
08000d72 <_ZNSt8functionIFv24can1_vn200_imu_acc_lin_tN6canlib5frame7decoded4can119vn200_imu_acc_lin_tEEEC1EDn>:
function(nullptr_t) noexcept
8000d72: b580 push {r7, lr}
8000d74: b082 sub sp, #8
8000d76: af00 add r7, sp, #0
8000d78: 6078 str r0, [r7, #4]
8000d7a: 6039 str r1, [r7, #0]
: _Function_base() { }
8000d7c: 687b ldr r3, [r7, #4]
8000d7e: 4618 mov r0, r3
8000d80: f7ff ff6c bl 8000c5c <_ZNSt14_Function_baseC1Ev>
8000d84: 687b ldr r3, [r7, #4]
8000d86: 4618 mov r0, r3
8000d88: 3708 adds r7, #8
8000d8a: 46bd mov sp, r7
8000d8c: bd80 pop {r7, pc}
08000d8e <_ZNSt8functionIFv24can1_vn200_imu_acc_ang_tN6canlib5frame7decoded4can119vn200_imu_acc_ang_tEEEC1EDn>:
function(nullptr_t) noexcept
8000d8e: b580 push {r7, lr}
8000d90: b082 sub sp, #8
8000d92: af00 add r7, sp, #0
8000d94: 6078 str r0, [r7, #4]
8000d96: 6039 str r1, [r7, #0]
: _Function_base() { }
8000d98: 687b ldr r3, [r7, #4]
8000d9a: 4618 mov r0, r3
8000d9c: f7ff ff5e bl 8000c5c <_ZNSt14_Function_baseC1Ev>
8000da0: 687b ldr r3, [r7, #4]
8000da2: 4618 mov r0, r3
8000da4: 3708 adds r7, #8
8000da6: 46bd mov sp, r7
8000da8: bd80 pop {r7, pc}
08000daa <_ZNSt8functionIFv19can1_vn200_ins_ll_tN6canlib5frame7decoded4can114vn200_ins_ll_tEEEC1EDn>:
function(nullptr_t) noexcept
8000daa: b580 push {r7, lr}
8000dac: b082 sub sp, #8
8000dae: af00 add r7, sp, #0
8000db0: 6078 str r0, [r7, #4]
8000db2: 6039 str r1, [r7, #0]
: _Function_base() { }
8000db4: 687b ldr r3, [r7, #4]
8000db6: 4618 mov r0, r3
8000db8: f7ff ff50 bl 8000c5c <_ZNSt14_Function_baseC1Ev>
8000dbc: 687b ldr r3, [r7, #4]
8000dbe: 4618 mov r0, r3
8000dc0: 3708 adds r7, #8
8000dc2: 46bd mov sp, r7
8000dc4: bd80 pop {r7, pc}
08000dc6 <_ZNSt8functionIFv20can1_vn200_ins_vel_tN6canlib5frame7decoded4can115vn200_ins_vel_tEEEC1EDn>:
function(nullptr_t) noexcept
8000dc6: b580 push {r7, lr}
8000dc8: b082 sub sp, #8
8000dca: af00 add r7, sp, #0
8000dcc: 6078 str r0, [r7, #4]
8000dce: 6039 str r1, [r7, #0]
: _Function_base() { }
8000dd0: 687b ldr r3, [r7, #4]
8000dd2: 4618 mov r0, r3
8000dd4: f7ff ff42 bl 8000c5c <_ZNSt14_Function_baseC1Ev>
8000dd8: 687b ldr r3, [r7, #4]
8000dda: 4618 mov r0, r3
8000ddc: 3708 adds r7, #8
8000dde: 46bd mov sp, r7
8000de0: bd80 pop {r7, pc}
...
08000de4 <_Z41__static_initialization_and_destruction_0ii>:
default:
break;
}
return HAL_OK;
}
8000de4: b580 push {r7, lr}
8000de6: b082 sub sp, #8
8000de8: af00 add r7, sp, #0
8000dea: 6078 str r0, [r7, #4]
8000dec: 6039 str r1, [r7, #0]
8000dee: 687b ldr r3, [r7, #4]
8000df0: 2b01 cmp r3, #1
8000df2: d170 bne.n 8000ed6 <_Z41__static_initialization_and_destruction_0ii+0xf2>
8000df4: 683b ldr r3, [r7, #0]
8000df6: f64f 72ff movw r2, #65535 ; 0xffff
8000dfa: 4293 cmp r3, r2
8000dfc: d16b bne.n 8000ed6 <_Z41__static_initialization_and_destruction_0ii+0xf2>
}
// callback structure
namespace callback {
namespace can1 {
inline std::function<void(can1_vn200_gnss_ll_t, frame::decoded::can1::vn200_gnss_ll_t)> vn200_gnss_ll = NULL;
8000dfe: 4b6f ldr r3, [pc, #444] ; (8000fbc <_Z41__static_initialization_and_destruction_0ii+0x1d8>)
8000e00: 681b ldr r3, [r3, #0]
8000e02: 3301 adds r3, #1
8000e04: 4a6d ldr r2, [pc, #436] ; (8000fbc <_Z41__static_initialization_and_destruction_0ii+0x1d8>)
8000e06: 6013 str r3, [r2, #0]
8000e08: 4b6c ldr r3, [pc, #432] ; (8000fbc <_Z41__static_initialization_and_destruction_0ii+0x1d8>)
8000e0a: 681b ldr r3, [r3, #0]
8000e0c: 2b01 cmp r3, #1
8000e0e: bf0c ite eq
8000e10: 2301 moveq r3, #1
8000e12: 2300 movne r3, #0
8000e14: b2db uxtb r3, r3
8000e16: 2b00 cmp r3, #0
8000e18: d003 beq.n 8000e22 <_Z41__static_initialization_and_destruction_0ii+0x3e>
8000e1a: 2100 movs r1, #0
8000e1c: 4868 ldr r0, [pc, #416] ; (8000fc0 <_Z41__static_initialization_and_destruction_0ii+0x1dc>)
8000e1e: f7ff ff8c bl 8000d3a <_ZNSt8functionIFv20can1_vn200_gnss_ll_tN6canlib5frame7decoded4can115vn200_gnss_ll_tEEEC1EDn>
inline std::function<void(can1_vn200_ins_ypr_t, frame::decoded::can1::vn200_ins_ypr_t)> vn200_ins_ypr = NULL;
8000e22: 4b68 ldr r3, [pc, #416] ; (8000fc4 <_Z41__static_initialization_and_destruction_0ii+0x1e0>)
8000e24: 681b ldr r3, [r3, #0]
8000e26: 3301 adds r3, #1
8000e28: 4a66 ldr r2, [pc, #408] ; (8000fc4 <_Z41__static_initialization_and_destruction_0ii+0x1e0>)
8000e2a: 6013 str r3, [r2, #0]
8000e2c: 4b65 ldr r3, [pc, #404] ; (8000fc4 <_Z41__static_initialization_and_destruction_0ii+0x1e0>)
8000e2e: 681b ldr r3, [r3, #0]
8000e30: 2b01 cmp r3, #1
8000e32: bf0c ite eq
8000e34: 2301 moveq r3, #1
8000e36: 2300 movne r3, #0
8000e38: b2db uxtb r3, r3
8000e3a: 2b00 cmp r3, #0
8000e3c: d003 beq.n 8000e46 <_Z41__static_initialization_and_destruction_0ii+0x62>
8000e3e: 2100 movs r1, #0
8000e40: 4861 ldr r0, [pc, #388] ; (8000fc8 <_Z41__static_initialization_and_destruction_0ii+0x1e4>)
8000e42: f7ff ff88 bl 8000d56 <_ZNSt8functionIFv20can1_vn200_ins_ypr_tN6canlib5frame7decoded4can115vn200_ins_ypr_tEEEC1EDn>
inline std::function<void(can1_vn200_imu_acc_lin_t, frame::decoded::can1::vn200_imu_acc_lin_t)> vn200_imu_acc_lin = NULL;
8000e46: 4b61 ldr r3, [pc, #388] ; (8000fcc <_Z41__static_initialization_and_destruction_0ii+0x1e8>)
8000e48: 681b ldr r3, [r3, #0]
8000e4a: 3301 adds r3, #1
8000e4c: 4a5f ldr r2, [pc, #380] ; (8000fcc <_Z41__static_initialization_and_destruction_0ii+0x1e8>)
8000e4e: 6013 str r3, [r2, #0]
8000e50: 4b5e ldr r3, [pc, #376] ; (8000fcc <_Z41__static_initialization_and_destruction_0ii+0x1e8>)
8000e52: 681b ldr r3, [r3, #0]
8000e54: 2b01 cmp r3, #1
8000e56: bf0c ite eq
8000e58: 2301 moveq r3, #1
8000e5a: 2300 movne r3, #0
8000e5c: b2db uxtb r3, r3
8000e5e: 2b00 cmp r3, #0
8000e60: d003 beq.n 8000e6a <_Z41__static_initialization_and_destruction_0ii+0x86>
8000e62: 2100 movs r1, #0
8000e64: 485a ldr r0, [pc, #360] ; (8000fd0 <_Z41__static_initialization_and_destruction_0ii+0x1ec>)
8000e66: f7ff ff84 bl 8000d72 <_ZNSt8functionIFv24can1_vn200_imu_acc_lin_tN6canlib5frame7decoded4can119vn200_imu_acc_lin_tEEEC1EDn>
inline std::function<void(can1_vn200_imu_acc_ang_t, frame::decoded::can1::vn200_imu_acc_ang_t)> vn200_imu_acc_ang = NULL;
8000e6a: 4b5a ldr r3, [pc, #360] ; (8000fd4 <_Z41__static_initialization_and_destruction_0ii+0x1f0>)
8000e6c: 681b ldr r3, [r3, #0]
8000e6e: 3301 adds r3, #1
8000e70: 4a58 ldr r2, [pc, #352] ; (8000fd4 <_Z41__static_initialization_and_destruction_0ii+0x1f0>)
8000e72: 6013 str r3, [r2, #0]
8000e74: 4b57 ldr r3, [pc, #348] ; (8000fd4 <_Z41__static_initialization_and_destruction_0ii+0x1f0>)
8000e76: 681b ldr r3, [r3, #0]
8000e78: 2b01 cmp r3, #1
8000e7a: bf0c ite eq
8000e7c: 2301 moveq r3, #1
8000e7e: 2300 movne r3, #0
8000e80: b2db uxtb r3, r3
8000e82: 2b00 cmp r3, #0
8000e84: d003 beq.n 8000e8e <_Z41__static_initialization_and_destruction_0ii+0xaa>
8000e86: 2100 movs r1, #0
8000e88: 4853 ldr r0, [pc, #332] ; (8000fd8 <_Z41__static_initialization_and_destruction_0ii+0x1f4>)
8000e8a: f7ff ff80 bl 8000d8e <_ZNSt8functionIFv24can1_vn200_imu_acc_ang_tN6canlib5frame7decoded4can119vn200_imu_acc_ang_tEEEC1EDn>
inline std::function<void(can1_vn200_ins_ll_t, frame::decoded::can1::vn200_ins_ll_t)> vn200_ins_ll = NULL;
8000e8e: 4b53 ldr r3, [pc, #332] ; (8000fdc <_Z41__static_initialization_and_destruction_0ii+0x1f8>)
8000e90: 681b ldr r3, [r3, #0]
8000e92: 3301 adds r3, #1
8000e94: 4a51 ldr r2, [pc, #324] ; (8000fdc <_Z41__static_initialization_and_destruction_0ii+0x1f8>)
8000e96: 6013 str r3, [r2, #0]
8000e98: 4b50 ldr r3, [pc, #320] ; (8000fdc <_Z41__static_initialization_and_destruction_0ii+0x1f8>)
8000e9a: 681b ldr r3, [r3, #0]
8000e9c: 2b01 cmp r3, #1
8000e9e: bf0c ite eq
8000ea0: 2301 moveq r3, #1
8000ea2: 2300 movne r3, #0
8000ea4: b2db uxtb r3, r3
8000ea6: 2b00 cmp r3, #0
8000ea8: d003 beq.n 8000eb2 <_Z41__static_initialization_and_destruction_0ii+0xce>
8000eaa: 2100 movs r1, #0
8000eac: 484c ldr r0, [pc, #304] ; (8000fe0 <_Z41__static_initialization_and_destruction_0ii+0x1fc>)
8000eae: f7ff ff7c bl 8000daa <_ZNSt8functionIFv19can1_vn200_ins_ll_tN6canlib5frame7decoded4can114vn200_ins_ll_tEEEC1EDn>
inline std::function<void(can1_vn200_ins_vel_t, frame::decoded::can1::vn200_ins_vel_t)> vn200_ins_vel = NULL;
8000eb2: 4b4c ldr r3, [pc, #304] ; (8000fe4 <_Z41__static_initialization_and_destruction_0ii+0x200>)
8000eb4: 681b ldr r3, [r3, #0]
8000eb6: 3301 adds r3, #1
8000eb8: 4a4a ldr r2, [pc, #296] ; (8000fe4 <_Z41__static_initialization_and_destruction_0ii+0x200>)
8000eba: 6013 str r3, [r2, #0]
8000ebc: 4b49 ldr r3, [pc, #292] ; (8000fe4 <_Z41__static_initialization_and_destruction_0ii+0x200>)
8000ebe: 681b ldr r3, [r3, #0]
8000ec0: 2b01 cmp r3, #1
8000ec2: bf0c ite eq
8000ec4: 2301 moveq r3, #1
8000ec6: 2300 movne r3, #0
8000ec8: b2db uxtb r3, r3
8000eca: 2b00 cmp r3, #0
8000ecc: d003 beq.n 8000ed6 <_Z41__static_initialization_and_destruction_0ii+0xf2>
8000ece: 2100 movs r1, #0
8000ed0: 4845 ldr r0, [pc, #276] ; (8000fe8 <_Z41__static_initialization_and_destruction_0ii+0x204>)
8000ed2: f7ff ff78 bl 8000dc6 <_ZNSt8functionIFv20can1_vn200_ins_vel_tN6canlib5frame7decoded4can115vn200_ins_vel_tEEEC1EDn>
8000ed6: 687b ldr r3, [r7, #4]
8000ed8: 2b00 cmp r3, #0
8000eda: d16a bne.n 8000fb2 <_Z41__static_initialization_and_destruction_0ii+0x1ce>
8000edc: 683b ldr r3, [r7, #0]
8000ede: f64f 72ff movw r2, #65535 ; 0xffff
8000ee2: 4293 cmp r3, r2
8000ee4: d165 bne.n 8000fb2 <_Z41__static_initialization_and_destruction_0ii+0x1ce>
8000ee6: 4b3f ldr r3, [pc, #252] ; (8000fe4 <_Z41__static_initialization_and_destruction_0ii+0x200>)
8000ee8: 681b ldr r3, [r3, #0]
8000eea: 3b01 subs r3, #1
8000eec: 4a3d ldr r2, [pc, #244] ; (8000fe4 <_Z41__static_initialization_and_destruction_0ii+0x200>)
8000eee: 6013 str r3, [r2, #0]
8000ef0: 4b3c ldr r3, [pc, #240] ; (8000fe4 <_Z41__static_initialization_and_destruction_0ii+0x200>)
8000ef2: 681b ldr r3, [r3, #0]
8000ef4: 2b00 cmp r3, #0
8000ef6: bf0c ite eq
8000ef8: 2301 moveq r3, #1
8000efa: 2300 movne r3, #0
8000efc: b2db uxtb r3, r3
8000efe: 2b00 cmp r3, #0
8000f00: d002 beq.n 8000f08 <_Z41__static_initialization_and_destruction_0ii+0x124>
8000f02: 4839 ldr r0, [pc, #228] ; (8000fe8 <_Z41__static_initialization_and_destruction_0ii+0x204>)
8000f04: f7ff ff0c bl 8000d20 <_ZNSt8functionIFv20can1_vn200_ins_vel_tN6canlib5frame7decoded4can115vn200_ins_vel_tEEED1Ev>
inline std::function<void(can1_vn200_ins_ll_t, frame::decoded::can1::vn200_ins_ll_t)> vn200_ins_ll = NULL;
8000f08: 4b34 ldr r3, [pc, #208] ; (8000fdc <_Z41__static_initialization_and_destruction_0ii+0x1f8>)
8000f0a: 681b ldr r3, [r3, #0]
8000f0c: 3b01 subs r3, #1
8000f0e: 4a33 ldr r2, [pc, #204] ; (8000fdc <_Z41__static_initialization_and_destruction_0ii+0x1f8>)
8000f10: 6013 str r3, [r2, #0]
8000f12: 4b32 ldr r3, [pc, #200] ; (8000fdc <_Z41__static_initialization_and_destruction_0ii+0x1f8>)
8000f14: 681b ldr r3, [r3, #0]
8000f16: 2b00 cmp r3, #0
8000f18: bf0c ite eq
8000f1a: 2301 moveq r3, #1
8000f1c: 2300 movne r3, #0
8000f1e: b2db uxtb r3, r3
8000f20: 2b00 cmp r3, #0
8000f22: d002 beq.n 8000f2a <_Z41__static_initialization_and_destruction_0ii+0x146>
8000f24: 482e ldr r0, [pc, #184] ; (8000fe0 <_Z41__static_initialization_and_destruction_0ii+0x1fc>)
8000f26: f7ff feee bl 8000d06 <_ZNSt8functionIFv19can1_vn200_ins_ll_tN6canlib5frame7decoded4can114vn200_ins_ll_tEEED1Ev>
inline std::function<void(can1_vn200_imu_acc_ang_t, frame::decoded::can1::vn200_imu_acc_ang_t)> vn200_imu_acc_ang = NULL;
8000f2a: 4b2a ldr r3, [pc, #168] ; (8000fd4 <_Z41__static_initialization_and_destruction_0ii+0x1f0>)
8000f2c: 681b ldr r3, [r3, #0]
8000f2e: 3b01 subs r3, #1
8000f30: 4a28 ldr r2, [pc, #160] ; (8000fd4 <_Z41__static_initialization_and_destruction_0ii+0x1f0>)
8000f32: 6013 str r3, [r2, #0]
8000f34: 4b27 ldr r3, [pc, #156] ; (8000fd4 <_Z41__static_initialization_and_destruction_0ii+0x1f0>)
8000f36: 681b ldr r3, [r3, #0]
8000f38: 2b00 cmp r3, #0
8000f3a: bf0c ite eq
8000f3c: 2301 moveq r3, #1
8000f3e: 2300 movne r3, #0
8000f40: b2db uxtb r3, r3
8000f42: 2b00 cmp r3, #0
8000f44: d002 beq.n 8000f4c <_Z41__static_initialization_and_destruction_0ii+0x168>
8000f46: 4824 ldr r0, [pc, #144] ; (8000fd8 <_Z41__static_initialization_and_destruction_0ii+0x1f4>)
8000f48: f7ff fed0 bl 8000cec <_ZNSt8functionIFv24can1_vn200_imu_acc_ang_tN6canlib5frame7decoded4can119vn200_imu_acc_ang_tEEED1Ev>
inline std::function<void(can1_vn200_imu_acc_lin_t, frame::decoded::can1::vn200_imu_acc_lin_t)> vn200_imu_acc_lin = NULL;
8000f4c: 4b1f ldr r3, [pc, #124] ; (8000fcc <_Z41__static_initialization_and_destruction_0ii+0x1e8>)
8000f4e: 681b ldr r3, [r3, #0]
8000f50: 3b01 subs r3, #1
8000f52: 4a1e ldr r2, [pc, #120] ; (8000fcc <_Z41__static_initialization_and_destruction_0ii+0x1e8>)
8000f54: 6013 str r3, [r2, #0]
8000f56: 4b1d ldr r3, [pc, #116] ; (8000fcc <_Z41__static_initialization_and_destruction_0ii+0x1e8>)
8000f58: 681b ldr r3, [r3, #0]
8000f5a: 2b00 cmp r3, #0
8000f5c: bf0c ite eq
8000f5e: 2301 moveq r3, #1
8000f60: 2300 movne r3, #0
8000f62: b2db uxtb r3, r3
8000f64: 2b00 cmp r3, #0
8000f66: d002 beq.n 8000f6e <_Z41__static_initialization_and_destruction_0ii+0x18a>
8000f68: 4819 ldr r0, [pc, #100] ; (8000fd0 <_Z41__static_initialization_and_destruction_0ii+0x1ec>)
8000f6a: f7ff feb2 bl 8000cd2 <_ZNSt8functionIFv24can1_vn200_imu_acc_lin_tN6canlib5frame7decoded4can119vn200_imu_acc_lin_tEEED1Ev>
inline std::function<void(can1_vn200_ins_ypr_t, frame::decoded::can1::vn200_ins_ypr_t)> vn200_ins_ypr = NULL;
8000f6e: 4b15 ldr r3, [pc, #84] ; (8000fc4 <_Z41__static_initialization_and_destruction_0ii+0x1e0>)
8000f70: 681b ldr r3, [r3, #0]
8000f72: 3b01 subs r3, #1
8000f74: 4a13 ldr r2, [pc, #76] ; (8000fc4 <_Z41__static_initialization_and_destruction_0ii+0x1e0>)
8000f76: 6013 str r3, [r2, #0]
8000f78: 4b12 ldr r3, [pc, #72] ; (8000fc4 <_Z41__static_initialization_and_destruction_0ii+0x1e0>)
8000f7a: 681b ldr r3, [r3, #0]
8000f7c: 2b00 cmp r3, #0
8000f7e: bf0c ite eq
8000f80: 2301 moveq r3, #1
8000f82: 2300 movne r3, #0
8000f84: b2db uxtb r3, r3
8000f86: 2b00 cmp r3, #0
8000f88: d002 beq.n 8000f90 <_Z41__static_initialization_and_destruction_0ii+0x1ac>
8000f8a: 480f ldr r0, [pc, #60] ; (8000fc8 <_Z41__static_initialization_and_destruction_0ii+0x1e4>)
8000f8c: f7ff fe94 bl 8000cb8 <_ZNSt8functionIFv20can1_vn200_ins_ypr_tN6canlib5frame7decoded4can115vn200_ins_ypr_tEEED1Ev>
inline std::function<void(can1_vn200_gnss_ll_t, frame::decoded::can1::vn200_gnss_ll_t)> vn200_gnss_ll = NULL;
8000f90: 4b0a ldr r3, [pc, #40] ; (8000fbc <_Z41__static_initialization_and_destruction_0ii+0x1d8>)
8000f92: 681b ldr r3, [r3, #0]
8000f94: 3b01 subs r3, #1
8000f96: 4a09 ldr r2, [pc, #36] ; (8000fbc <_Z41__static_initialization_and_destruction_0ii+0x1d8>)
8000f98: 6013 str r3, [r2, #0]
8000f9a: 4b08 ldr r3, [pc, #32] ; (8000fbc <_Z41__static_initialization_and_destruction_0ii+0x1d8>)
8000f9c: 681b ldr r3, [r3, #0]
8000f9e: 2b00 cmp r3, #0
8000fa0: bf0c ite eq
8000fa2: 2301 moveq r3, #1
8000fa4: 2300 movne r3, #0
8000fa6: b2db uxtb r3, r3
8000fa8: 2b00 cmp r3, #0
8000faa: d002 beq.n 8000fb2 <_Z41__static_initialization_and_destruction_0ii+0x1ce>
8000fac: 4804 ldr r0, [pc, #16] ; (8000fc0 <_Z41__static_initialization_and_destruction_0ii+0x1dc>)
8000fae: f7ff fe76 bl 8000c9e <_ZNSt8functionIFv20can1_vn200_gnss_ll_tN6canlib5frame7decoded4can115vn200_gnss_ll_tEEED1Ev>
8000fb2: bf00 nop
8000fb4: 3708 adds r7, #8
8000fb6: 46bd mov sp, r7
8000fb8: bd80 pop {r7, pc}
8000fba: bf00 nop
8000fbc: 20000088 .word 0x20000088
8000fc0: 20000028 .word 0x20000028
8000fc4: 2000008c .word 0x2000008c
8000fc8: 20000038 .word 0x20000038
8000fcc: 20000090 .word 0x20000090
8000fd0: 20000048 .word 0x20000048
8000fd4: 20000094 .word 0x20000094
8000fd8: 20000058 .word 0x20000058
8000fdc: 20000098 .word 0x20000098
8000fe0: 20000068 .word 0x20000068
8000fe4: 2000009c .word 0x2000009c
8000fe8: 20000078 .word 0x20000078
08000fec <_GLOBAL__sub_I_Converter.cpp>:
8000fec: b580 push {r7, lr}
8000fee: af00 add r7, sp, #0
8000ff0: f64f 71ff movw r1, #65535 ; 0xffff
8000ff4: 2001 movs r0, #1
8000ff6: f7ff fef5 bl 8000de4 <_Z41__static_initialization_and_destruction_0ii>
8000ffa: bd80 pop {r7, pc}
08000ffc <_GLOBAL__sub_D_Converter.cpp>:
8000ffc: b580 push {r7, lr}
8000ffe: af00 add r7, sp, #0
8001000: f64f 71ff movw r1, #65535 ; 0xffff
8001004: 2000 movs r0, #0
8001006: f7ff feed bl 8000de4 <_Z41__static_initialization_and_destruction_0ii>
800100a: bd80 pop {r7, pc}
800100c: 0000 movs r0, r0
...
08001010 <can1_vn200_ins_ypr_yaw_encode>:
return 0;
}
int16_t can1_vn200_ins_ypr_yaw_encode(double value)
{
8001010: b580 push {r7, lr}
8001012: b082 sub sp, #8
8001014: af00 add r7, sp, #0
8001016: ed87 0b00 vstr d0, [r7]
return (int16_t)(value / 0.001);
800101a: a309 add r3, pc, #36 ; (adr r3, 8001040 <can1_vn200_ins_ypr_yaw_encode+0x30>)
800101c: e9d3 2300 ldrd r2, r3, [r3]
8001020: e9d7 0100 ldrd r0, r1, [r7]
8001024: f7ff fcea bl 80009fc <__aeabi_ddiv>
8001028: 4602 mov r2, r0
800102a: 460b mov r3, r1
800102c: 4610 mov r0, r2
800102e: 4619 mov r1, r3
8001030: f7ff fdcc bl 8000bcc <__aeabi_d2iz>
8001034: 4603 mov r3, r0
8001036: b21b sxth r3, r3
}
8001038: 4618 mov r0, r3
800103a: 3708 adds r7, #8
800103c: 46bd mov sp, r7
800103e: bd80 pop {r7, pc}
8001040: d2f1a9fc .word 0xd2f1a9fc
8001044: 3f50624d .word 0x3f50624d
08001048 <can1_vn200_ins_ypr_pitch_encode>:
return (true);
}
int16_t can1_vn200_ins_ypr_pitch_encode(double value)
{
8001048: b580 push {r7, lr}
800104a: b082 sub sp, #8
800104c: af00 add r7, sp, #0
800104e: ed87 0b00 vstr d0, [r7]
return (int16_t)(value / 0.001);
8001052: a309 add r3, pc, #36 ; (adr r3, 8001078 <can1_vn200_ins_ypr_pitch_encode+0x30>)
8001054: e9d3 2300 ldrd r2, r3, [r3]
8001058: e9d7 0100 ldrd r0, r1, [r7]
800105c: f7ff fcce bl 80009fc <__aeabi_ddiv>
8001060: 4602 mov r2, r0
8001062: 460b mov r3, r1
8001064: 4610 mov r0, r2
8001066: 4619 mov r1, r3
8001068: f7ff fdb0 bl 8000bcc <__aeabi_d2iz>
800106c: 4603 mov r3, r0
800106e: b21b sxth r3, r3
}
8001070: 4618 mov r0, r3
8001072: 3708 adds r7, #8
8001074: 46bd mov sp, r7
8001076: bd80 pop {r7, pc}
8001078: d2f1a9fc .word 0xd2f1a9fc
800107c: 3f50624d .word 0x3f50624d
08001080 <can1_vn200_ins_ypr_roll_encode>:
return (true);
}
int16_t can1_vn200_ins_ypr_roll_encode(double value)
{
8001080: b580 push {r7, lr}
8001082: b082 sub sp, #8
8001084: af00 add r7, sp, #0
8001086: ed87 0b00 vstr d0, [r7]
return (int16_t)(value / 0.001);
800108a: a309 add r3, pc, #36 ; (adr r3, 80010b0 <can1_vn200_ins_ypr_roll_encode+0x30>)
800108c: e9d3 2300 ldrd r2, r3, [r3]
8001090: e9d7 0100 ldrd r0, r1, [r7]
8001094: f7ff fcb2 bl 80009fc <__aeabi_ddiv>
8001098: 4602 mov r2, r0
800109a: 460b mov r3, r1
800109c: 4610 mov r0, r2
800109e: 4619 mov r1, r3
80010a0: f7ff fd94 bl 8000bcc <__aeabi_d2iz>
80010a4: 4603 mov r3, r0
80010a6: b21b sxth r3, r3
}
80010a8: 4618 mov r0, r3
80010aa: 3708 adds r7, #8
80010ac: 46bd mov sp, r7
80010ae: bd80 pop {r7, pc}
80010b0: d2f1a9fc .word 0xd2f1a9fc
80010b4: 3f50624d .word 0x3f50624d
080010b8 <can1_vn200_ins_ypr_uncertainty_encode>:
return (true);
}
uint16_t can1_vn200_ins_ypr_uncertainty_encode(double value)
{
80010b8: b580 push {r7, lr}
80010ba: b082 sub sp, #8
80010bc: af00 add r7, sp, #0
80010be: ed87 0b00 vstr d0, [r7]
return (uint16_t)(value / 0.0001);
80010c2: a309 add r3, pc, #36 ; (adr r3, 80010e8 <can1_vn200_ins_ypr_uncertainty_encode+0x30>)
80010c4: e9d3 2300 ldrd r2, r3, [r3]
80010c8: e9d7 0100 ldrd r0, r1, [r7]
80010cc: f7ff fc96 bl 80009fc <__aeabi_ddiv>
80010d0: 4602 mov r2, r0
80010d2: 460b mov r3, r1
80010d4: 4610 mov r0, r2
80010d6: 4619 mov r1, r3
80010d8: f7ff fda0 bl 8000c1c <__aeabi_d2uiz>
80010dc: 4603 mov r3, r0
80010de: b29b uxth r3, r3
}
80010e0: 4618 mov r0, r3
80010e2: 3708 adds r7, #8
80010e4: 46bd mov sp, r7
80010e6: bd80 pop {r7, pc}
80010e8: eb1c432d .word 0xeb1c432d
80010ec: 3f1a36e2 .word 0x3f1a36e2
080010f0 <_Z14ftcan_transmitP19__CAN_HandleTypeDeftPKhj>:
}
return HAL_CAN_Start(handle);
}
HAL_StatusTypeDef ftcan_transmit(CAN_HandleTypeDef *handle, uint16_t id, const uint8_t *data, size_t datalen) {
80010f0: b580 push {r7, lr}
80010f2: b086 sub sp, #24
80010f4: af00 add r7, sp, #0
80010f6: 60f8 str r0, [r7, #12]
80010f8: 607a str r2, [r7, #4]
80010fa: 603b str r3, [r7, #0]
80010fc: 460b mov r3, r1
80010fe: 817b strh r3, [r7, #10]
static CAN_TxHeaderTypeDef header;
header.StdId = id;
8001100: 897b ldrh r3, [r7, #10]
8001102: 4a0b ldr r2, [pc, #44] ; (8001130 <_Z14ftcan_transmitP19__CAN_HandleTypeDeftPKhj+0x40>)
8001104: 6013 str r3, [r2, #0]
header.IDE = CAN_ID_STD;
8001106: 4b0a ldr r3, [pc, #40] ; (8001130 <_Z14ftcan_transmitP19__CAN_HandleTypeDeftPKhj+0x40>)
8001108: 2200 movs r2, #0
800110a: 609a str r2, [r3, #8]
header.RTR = CAN_RTR_DATA;
800110c: 4b08 ldr r3, [pc, #32] ; (8001130 <_Z14ftcan_transmitP19__CAN_HandleTypeDeftPKhj+0x40>)
800110e: 2200 movs r2, #0
8001110: 60da str r2, [r3, #12]
header.DLC = datalen;
8001112: 4a07 ldr r2, [pc, #28] ; (8001130 <_Z14ftcan_transmitP19__CAN_HandleTypeDeftPKhj+0x40>)
8001114: 683b ldr r3, [r7, #0]
8001116: 6113 str r3, [r2, #16]
uint32_t mailbox;
return HAL_CAN_AddTxMessage(handle, &header, data, &mailbox);
8001118: f107 0314 add.w r3, r7, #20
800111c: 687a ldr r2, [r7, #4]
800111e: 4904 ldr r1, [pc, #16] ; (8001130 <_Z14ftcan_transmitP19__CAN_HandleTypeDeftPKhj+0x40>)
8001120: 68f8 ldr r0, [r7, #12]
8001122: f000 fede bl 8001ee2 <HAL_CAN_AddTxMessage>
8001126: 4603 mov r3, r0
}
8001128: 4618 mov r0, r3
800112a: 3718 adds r7, #24
800112c: 46bd mov sp, r7
800112e: bd80 pop {r7, pc}
8001130: 200000a0 .word 0x200000a0
08001134 <_ZN2vn8header_t9request_tC1Ehh>:
union header_t {
struct request_t {
uint8_t Cmd = 0; /* Defined in VN_SPI_READ */
uint8_t ID = 0; /* Register ID */
uint16_t Empty = 0; /* Spacer */
request_t(uint8_t ID, uint8_t Cmd) {
8001134: b480 push {r7}
8001136: b083 sub sp, #12
8001138: af00 add r7, sp, #0
800113a: 6078 str r0, [r7, #4]
800113c: 460b mov r3, r1
800113e: 70fb strb r3, [r7, #3]
8001140: 4613 mov r3, r2
8001142: 70bb strb r3, [r7, #2]
8001144: 687b ldr r3, [r7, #4]
8001146: 2200 movs r2, #0
8001148: 701a strb r2, [r3, #0]
800114a: 687b ldr r3, [r7, #4]
800114c: 2200 movs r2, #0
800114e: 705a strb r2, [r3, #1]
8001150: 687b ldr r3, [r7, #4]
8001152: 2200 movs r2, #0
8001154: 805a strh r2, [r3, #2]
this->ID = ID;
8001156: 687b ldr r3, [r7, #4]
8001158: 78fa ldrb r2, [r7, #3]
800115a: 705a strb r2, [r3, #1]
this->Cmd = Cmd;
800115c: 687b ldr r3, [r7, #4]
800115e: 78ba ldrb r2, [r7, #2]
8001160: 701a strb r2, [r3, #0]
};
8001162: 687b ldr r3, [r7, #4]
8001164: 4618 mov r0, r3
8001166: 370c adds r7, #12
8001168: 46bd mov sp, r7
800116a: f85d 7b04 ldr.w r7, [sp], #4
800116e: 4770 bx lr
08001170 <_ZN2vn8header_t10response_tC1Ev>:
struct response_t {
uint8_t Empty1 = 0; /* Spacer */
uint8_t Cmd = 0; /* Defined in VN_SPI_READ */
uint8_t ID = 0; /* Register ID */
uint8_t Empty2 = 0; /* Spacer */
response_t(){};
8001170: b480 push {r7}
8001172: b083 sub sp, #12
8001174: af00 add r7, sp, #0
8001176: 6078 str r0, [r7, #4]
8001178: 687b ldr r3, [r7, #4]
800117a: 2200 movs r2, #0
800117c: 701a strb r2, [r3, #0]
800117e: 687b ldr r3, [r7, #4]
8001180: 2200 movs r2, #0
8001182: 705a strb r2, [r3, #1]
8001184: 687b ldr r3, [r7, #4]
8001186: 2200 movs r2, #0
8001188: 709a strb r2, [r3, #2]
800118a: 687b ldr r3, [r7, #4]
800118c: 2200 movs r2, #0
800118e: 70da strb r2, [r3, #3]
8001190: 687b ldr r3, [r7, #4]
8001192: 4618 mov r0, r3
8001194: 370c adds r7, #12
8001196: 46bd mov sp, r7
8001198: f85d 7b04 ldr.w r7, [sp], #4
800119c: 4770 bx lr
0800119e <_ZN2vn18pkg_request_read_tC1Eh>:
};
/** \brief Requests the specified register to read from */
struct pkg_request_read_t {
struct header_t::request_t header;
pkg_request_read_t(uint8_t ID) : header(ID, VN_SPI_READ){};
800119e: b580 push {r7, lr}
80011a0: b082 sub sp, #8
80011a2: af00 add r7, sp, #0
80011a4: 6078 str r0, [r7, #4]
80011a6: 460b mov r3, r1
80011a8: 70fb strb r3, [r7, #3]
80011aa: 687b ldr r3, [r7, #4]
80011ac: 78f9 ldrb r1, [r7, #3]
80011ae: 2201 movs r2, #1
80011b0: 4618 mov r0, r3
80011b2: f7ff ffbf bl 8001134 <_ZN2vn8header_t9request_tC1Ehh>
80011b6: 687b ldr r3, [r7, #4]
80011b8: 4618 mov r0, r3
80011ba: 3708 adds r7, #8
80011bc: 46bd mov sp, r7
80011be: bd80 pop {r7, pc}
080011c0 <_ZN5vec3fC1Ev>:
struct {
float c0; /**< Component 0. */
float c1; /**< Component 1. */
float c2; /**< Component 2. */
};
vec3f() { std::memset(this, 0, sizeof(vec3f)); }
80011c0: b580 push {r7, lr}
80011c2: b082 sub sp, #8
80011c4: af00 add r7, sp, #0
80011c6: 6078 str r0, [r7, #4]
80011c8: 220c movs r2, #12
80011ca: 2100 movs r1, #0
80011cc: 6878 ldr r0, [r7, #4]
80011ce: f7ff f8dd bl 800038c <memset>
80011d2: 687b ldr r3, [r7, #4]
80011d4: 4618 mov r0, r3
80011d6: 3708 adds r7, #8
80011d8: 46bd mov sp, r7
80011da: bd80 pop {r7, pc}
080011dc <_ZN5vec3dC1Ev>:
struct {
double c0; /**< Component 0. */
double c1; /**< Component 1. */
double c2; /**< Component 2. */
};
vec3d() { std::memset(this, 0, sizeof(vec3d)); }
80011dc: b580 push {r7, lr}
80011de: b082 sub sp, #8
80011e0: af00 add r7, sp, #0
80011e2: 6078 str r0, [r7, #4]
80011e4: 2218 movs r2, #24
80011e6: 2100 movs r1, #0
80011e8: 6878 ldr r0, [r7, #4]
80011ea: f7ff f8cf bl 800038c <memset>
80011ee: 687b ldr r3, [r7, #4]
80011f0: 4618 mov r0, r3
80011f2: 3708 adds r7, #8
80011f4: 46bd mov sp, r7
80011f6: bd80 pop {r7, pc}
080011f8 <_ZN2vn22InsSolutionLlaRegisterC1Ev>:
float posUncertainty;
/** \brief The VelUncertainty field. */
float velUncertainty;
InsSolutionLlaRegister(){
80011f8: b580 push {r7, lr}
80011fa: b082 sub sp, #8
80011fc: af00 add r7, sp, #0
80011fe: 6078 str r0, [r7, #4]
8001200: 687b ldr r3, [r7, #4]
8001202: 330c adds r3, #12
8001204: 4618 mov r0, r3
8001206: f7ff ffdb bl 80011c0 <_ZN5vec3fC1Ev>
800120a: 687b ldr r3, [r7, #4]
800120c: 3318 adds r3, #24
800120e: 4618 mov r0, r3
8001210: f7ff ffe4 bl 80011dc <_ZN5vec3dC1Ev>
8001214: 687b ldr r3, [r7, #4]
8001216: 3330 adds r3, #48 ; 0x30
8001218: 4618 mov r0, r3
800121a: f7ff ffd1 bl 80011c0 <_ZN5vec3fC1Ev>
time = 0.0;
800121e: 6879 ldr r1, [r7, #4]
8001220: f04f 0200 mov.w r2, #0
8001224: f04f 0300 mov.w r3, #0
8001228: e9c1 2300 strd r2, r3, [r1]
week = 0;
800122c: 687b ldr r3, [r7, #4]
800122e: 2200 movs r2, #0
8001230: 811a strh r2, [r3, #8]
status = 0;
8001232: 687b ldr r3, [r7, #4]
8001234: 2200 movs r2, #0
8001236: 815a strh r2, [r3, #10]
attUncertainty = 0.0;
8001238: 687b ldr r3, [r7, #4]
800123a: f04f 0200 mov.w r2, #0
800123e: 63da str r2, [r3, #60] ; 0x3c
posUncertainty = 0.0;
8001240: 687b ldr r3, [r7, #4]
8001242: f04f 0200 mov.w r2, #0
8001246: 641a str r2, [r3, #64] ; 0x40
}
8001248: 687b ldr r3, [r7, #4]
800124a: 4618 mov r0, r3
800124c: 3708 adds r7, #8
800124e: 46bd mov sp, r7
8001250: bd80 pop {r7, pc}
08001252 <_ZN6canlib5frame7decoded4can115vn200_ins_ypr_tC1Edddd>:
vn200_ins_ypr_t(
8001252: b480 push {r7}
8001254: b08b sub sp, #44 ; 0x2c
8001256: af00 add r7, sp, #0
8001258: 6278 str r0, [r7, #36] ; 0x24
800125a: ed87 0b06 vstr d0, [r7, #24]
800125e: ed87 1b04 vstr d1, [r7, #16]
8001262: ed87 2b02 vstr d2, [r7, #8]
8001266: ed87 3b00 vstr d3, [r7]
this->yaw = yaw;
800126a: 6a79 ldr r1, [r7, #36] ; 0x24
800126c: e9d7 2306 ldrd r2, r3, [r7, #24]
8001270: e9c1 2300 strd r2, r3, [r1]
this->pitch = pitch;
8001274: 6a79 ldr r1, [r7, #36] ; 0x24
8001276: e9d7 2304 ldrd r2, r3, [r7, #16]
800127a: e9c1 2302 strd r2, r3, [r1, #8]
this->roll = roll;
800127e: 6a79 ldr r1, [r7, #36] ; 0x24
8001280: e9d7 2302 ldrd r2, r3, [r7, #8]
8001284: e9c1 2304 strd r2, r3, [r1, #16]
this->uncertainty = uncertainty;
8001288: 6a79 ldr r1, [r7, #36] ; 0x24
800128a: e9d7 2300 ldrd r2, r3, [r7]
800128e: e9c1 2306 strd r2, r3, [r1, #24]
}
8001292: 6a7b ldr r3, [r7, #36] ; 0x24
8001294: 4618 mov r0, r3
8001296: 372c adds r7, #44 ; 0x2c
8001298: 46bd mov sp, r7
800129a: f85d 7b04 ldr.w r7, [sp], #4
800129e: 4770 bx lr
080012a0 <_ZN6canlib6encode4can113vn200_ins_yprENS_5frame7decoded4can115vn200_ins_ypr_tE>:
inline can1_vn200_ins_ypr_t vn200_ins_ypr(const frame::decoded::can1::vn200_ins_ypr_t frame_decoded) {
80012a0: b580 push {r7, lr}
80012a2: b08a sub sp, #40 ; 0x28
80012a4: af00 add r7, sp, #0
80012a6: 6278 str r0, [r7, #36] ; 0x24
80012a8: eeb0 4a40 vmov.f32 s8, s0
80012ac: eef0 4a60 vmov.f32 s9, s1
80012b0: eeb0 5a41 vmov.f32 s10, s2
80012b4: eef0 5a61 vmov.f32 s11, s3
80012b8: eeb0 6a42 vmov.f32 s12, s4
80012bc: eef0 6a62 vmov.f32 s13, s5
80012c0: eeb0 7a43 vmov.f32 s14, s6
80012c4: eef0 7a63 vmov.f32 s15, s7
80012c8: ed87 4b00 vstr d4, [r7]
80012cc: ed87 5b02 vstr d5, [r7, #8]
80012d0: ed87 6b04 vstr d6, [r7, #16]
80012d4: ed87 7b06 vstr d7, [r7, #24]
frame_encoded.yaw = can1_vn200_ins_ypr_yaw_encode(frame_decoded.yaw);
80012d8: ed97 7b00 vldr d7, [r7]
80012dc: eeb0 0a47 vmov.f32 s0, s14
80012e0: eef0 0a67 vmov.f32 s1, s15
80012e4: f7ff fe94 bl 8001010 <can1_vn200_ins_ypr_yaw_encode>
80012e8: 4603 mov r3, r0
80012ea: 461a mov r2, r3
80012ec: 6a7b ldr r3, [r7, #36] ; 0x24
80012ee: 801a strh r2, [r3, #0]
frame_encoded.pitch = can1_vn200_ins_ypr_pitch_encode(frame_decoded.pitch);
80012f0: ed97 7b02 vldr d7, [r7, #8]
80012f4: eeb0 0a47 vmov.f32 s0, s14
80012f8: eef0 0a67 vmov.f32 s1, s15
80012fc: f7ff fea4 bl 8001048 <can1_vn200_ins_ypr_pitch_encode>
8001300: 4603 mov r3, r0
8001302: 461a mov r2, r3
8001304: 6a7b ldr r3, [r7, #36] ; 0x24
8001306: 805a strh r2, [r3, #2]
frame_encoded.roll = can1_vn200_ins_ypr_roll_encode(frame_decoded.roll);
8001308: ed97 7b04 vldr d7, [r7, #16]
800130c: eeb0 0a47 vmov.f32 s0, s14
8001310: eef0 0a67 vmov.f32 s1, s15
8001314: f7ff feb4 bl 8001080 <can1_vn200_ins_ypr_roll_encode>
8001318: 4603 mov r3, r0
800131a: 461a mov r2, r3
800131c: 6a7b ldr r3, [r7, #36] ; 0x24
800131e: 809a strh r2, [r3, #4]
frame_encoded.uncertainty = can1_vn200_ins_ypr_uncertainty_encode(frame_decoded.uncertainty);
8001320: ed97 7b06 vldr d7, [r7, #24]
8001324: eeb0 0a47 vmov.f32 s0, s14
8001328: eef0 0a67 vmov.f32 s1, s15
800132c: f7ff fec4 bl 80010b8 <can1_vn200_ins_ypr_uncertainty_encode>
8001330: 4603 mov r3, r0
8001332: 461a mov r2, r3
8001334: 6a7b ldr r3, [r7, #36] ; 0x24
8001336: 80da strh r2, [r3, #6]
return frame_encoded;
8001338: bf00 nop
}
800133a: 6a78 ldr r0, [r7, #36] ; 0x24
800133c: 3728 adds r7, #40 ; 0x28
800133e: 46bd mov sp, r7
8001340: bd80 pop {r7, pc}
...
08001344 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8001344: b580 push {r7, lr}
8001346: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8001348: f000 fc46 bl 8001bd8 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
800134c: f000 f81c bl 8001388 <_Z18SystemClock_Configv>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8001350: f000 f8dc bl 800150c <_ZL12MX_GPIO_Initv>
MX_CAN_Init();
8001354: f000 f85e bl 8001414 <_ZL11MX_CAN_Initv>
MX_SPI1_Init();
8001358: f000 f896 bl 8001488 <_ZL12MX_SPI1_Initv>
/* USER CODE BEGIN 2 */
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_SET);
800135c: 2201 movs r2, #1
800135e: f44f 7100 mov.w r1, #512 ; 0x200
8001362: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
8001366: f001 fb51 bl 8002a0c <HAL_GPIO_WritePin>
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
/* USER CODE END WHILE */
spi2can<vn::InsSolutionLlaRegister>(&hspi1, &hcan, vn::InsSolutionLlaRegisterID);
800136a: 4a04 ldr r2, [pc, #16] ; (800137c <main+0x38>)
800136c: 4904 ldr r1, [pc, #16] ; (8001380 <main+0x3c>)
800136e: 4805 ldr r0, [pc, #20] ; (8001384 <main+0x40>)
8001370: f000 f911 bl 8001596 <_Z7spi2canIN2vn22InsSolutionLlaRegisterEE17HAL_StatusTypeDefP19__SPI_HandleTypeDefP19__CAN_HandleTypeDefRKt>
HAL_Delay(100);
8001374: 2064 movs r0, #100 ; 0x64
8001376: f000 fc95 bl 8001ca4 <HAL_Delay>
spi2can<vn::InsSolutionLlaRegister>(&hspi1, &hcan, vn::InsSolutionLlaRegisterID);
800137a: e7f6 b.n 800136a <main+0x26>
800137c: 08004704 .word 0x08004704
8001380: 200000b8 .word 0x200000b8
8001384: 200000e0 .word 0x200000e0
08001388 <_Z18SystemClock_Configv>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8001388: b580 push {r7, lr}
800138a: b090 sub sp, #64 ; 0x40
800138c: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
800138e: f107 0318 add.w r3, r7, #24
8001392: 2228 movs r2, #40 ; 0x28
8001394: 2100 movs r1, #0
8001396: 4618 mov r0, r3
8001398: f7fe fff8 bl 800038c <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
800139c: 1d3b adds r3, r7, #4
800139e: 2200 movs r2, #0
80013a0: 601a str r2, [r3, #0]
80013a2: 605a str r2, [r3, #4]
80013a4: 609a str r2, [r3, #8]
80013a6: 60da str r2, [r3, #12]
80013a8: 611a str r2, [r3, #16]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
80013aa: 2301 movs r3, #1
80013ac: 61bb str r3, [r7, #24]
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
80013ae: f44f 3380 mov.w r3, #65536 ; 0x10000
80013b2: 61fb str r3, [r7, #28]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
80013b4: 2301 movs r3, #1
80013b6: 62bb str r3, [r7, #40] ; 0x28
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
80013b8: 2300 movs r3, #0
80013ba: 637b str r3, [r7, #52] ; 0x34
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80013bc: f107 0318 add.w r3, r7, #24
80013c0: 4618 mov r0, r3
80013c2: f001 fb3b bl 8002a3c <HAL_RCC_OscConfig>
80013c6: 4603 mov r3, r0
80013c8: 2b00 cmp r3, #0
80013ca: bf14 ite ne
80013cc: 2301 movne r3, #1
80013ce: 2300 moveq r3, #0
80013d0: b2db uxtb r3, r3
80013d2: 2b00 cmp r3, #0
80013d4: d001 beq.n 80013da <_Z18SystemClock_Configv+0x52>
{
Error_Handler();
80013d6: f000 f8d9 bl 800158c <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80013da: 230f movs r3, #15
80013dc: 607b str r3, [r7, #4]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
80013de: 2301 movs r3, #1
80013e0: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80013e2: 2300 movs r3, #0
80013e4: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
80013e6: 2300 movs r3, #0
80013e8: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
80013ea: 2300 movs r3, #0
80013ec: 617b str r3, [r7, #20]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
80013ee: 1d3b adds r3, r7, #4
80013f0: 2100 movs r1, #0
80013f2: 4618 mov r0, r3
80013f4: f002 fb60 bl 8003ab8 <HAL_RCC_ClockConfig>
80013f8: 4603 mov r3, r0
80013fa: 2b00 cmp r3, #0
80013fc: bf14 ite ne
80013fe: 2301 movne r3, #1
8001400: 2300 moveq r3, #0
8001402: b2db uxtb r3, r3
8001404: 2b00 cmp r3, #0
8001406: d001 beq.n 800140c <_Z18SystemClock_Configv+0x84>
{
Error_Handler();
8001408: f000 f8c0 bl 800158c <Error_Handler>
}
}
800140c: bf00 nop
800140e: 3740 adds r7, #64 ; 0x40
8001410: 46bd mov sp, r7
8001412: bd80 pop {r7, pc}
08001414 <_ZL11MX_CAN_Initv>:
* @brief CAN Initialization Function
* @param None
* @retval None
*/
static void MX_CAN_Init(void)
{
8001414: b580 push {r7, lr}
8001416: af00 add r7, sp, #0
/* USER CODE END CAN_Init 0 */
/* USER CODE BEGIN CAN_Init 1 */
/* USER CODE END CAN_Init 1 */
hcan.Instance = CAN;
8001418: 4b19 ldr r3, [pc, #100] ; (8001480 <_ZL11MX_CAN_Initv+0x6c>)
800141a: 4a1a ldr r2, [pc, #104] ; (8001484 <_ZL11MX_CAN_Initv+0x70>)
800141c: 601a str r2, [r3, #0]
hcan.Init.Prescaler = 8;
800141e: 4b18 ldr r3, [pc, #96] ; (8001480 <_ZL11MX_CAN_Initv+0x6c>)
8001420: 2208 movs r2, #8
8001422: 605a str r2, [r3, #4]
hcan.Init.Mode = CAN_MODE_NORMAL;
8001424: 4b16 ldr r3, [pc, #88] ; (8001480 <_ZL11MX_CAN_Initv+0x6c>)
8001426: 2200 movs r2, #0
8001428: 609a str r2, [r3, #8]
hcan.Init.SyncJumpWidth = CAN_SJW_1TQ;
800142a: 4b15 ldr r3, [pc, #84] ; (8001480 <_ZL11MX_CAN_Initv+0x6c>)
800142c: 2200 movs r2, #0
800142e: 60da str r2, [r3, #12]
hcan.Init.TimeSeg1 = CAN_BS1_2TQ;
8001430: 4b13 ldr r3, [pc, #76] ; (8001480 <_ZL11MX_CAN_Initv+0x6c>)
8001432: f44f 3280 mov.w r2, #65536 ; 0x10000
8001436: 611a str r2, [r3, #16]
hcan.Init.TimeSeg2 = CAN_BS2_1TQ;
8001438: 4b11 ldr r3, [pc, #68] ; (8001480 <_ZL11MX_CAN_Initv+0x6c>)
800143a: 2200 movs r2, #0
800143c: 615a str r2, [r3, #20]
hcan.Init.TimeTriggeredMode = DISABLE;
800143e: 4b10 ldr r3, [pc, #64] ; (8001480 <_ZL11MX_CAN_Initv+0x6c>)
8001440: 2200 movs r2, #0
8001442: 761a strb r2, [r3, #24]
hcan.Init.AutoBusOff = DISABLE;
8001444: 4b0e ldr r3, [pc, #56] ; (8001480 <_ZL11MX_CAN_Initv+0x6c>)
8001446: 2200 movs r2, #0
8001448: 765a strb r2, [r3, #25]
hcan.Init.AutoWakeUp = DISABLE;
800144a: 4b0d ldr r3, [pc, #52] ; (8001480 <_ZL11MX_CAN_Initv+0x6c>)
800144c: 2200 movs r2, #0
800144e: 769a strb r2, [r3, #26]
hcan.Init.AutoRetransmission = DISABLE;
8001450: 4b0b ldr r3, [pc, #44] ; (8001480 <_ZL11MX_CAN_Initv+0x6c>)
8001452: 2200 movs r2, #0
8001454: 76da strb r2, [r3, #27]
hcan.Init.ReceiveFifoLocked = DISABLE;
8001456: 4b0a ldr r3, [pc, #40] ; (8001480 <_ZL11MX_CAN_Initv+0x6c>)
8001458: 2200 movs r2, #0
800145a: 771a strb r2, [r3, #28]
hcan.Init.TransmitFifoPriority = DISABLE;
800145c: 4b08 ldr r3, [pc, #32] ; (8001480 <_ZL11MX_CAN_Initv+0x6c>)
800145e: 2200 movs r2, #0
8001460: 775a strb r2, [r3, #29]
if (HAL_CAN_Init(&hcan) != HAL_OK)
8001462: 4807 ldr r0, [pc, #28] ; (8001480 <_ZL11MX_CAN_Initv+0x6c>)
8001464: f000 fc42 bl 8001cec <HAL_CAN_Init>
8001468: 4603 mov r3, r0
800146a: 2b00 cmp r3, #0
800146c: bf14 ite ne
800146e: 2301 movne r3, #1
8001470: 2300 moveq r3, #0
8001472: b2db uxtb r3, r3
8001474: 2b00 cmp r3, #0
8001476: d001 beq.n 800147c <_ZL11MX_CAN_Initv+0x68>
{
Error_Handler();
8001478: f000 f888 bl 800158c <Error_Handler>
}
/* USER CODE BEGIN CAN_Init 2 */
/* USER CODE END CAN_Init 2 */
}
800147c: bf00 nop
800147e: bd80 pop {r7, pc}
8001480: 200000b8 .word 0x200000b8
8001484: 40006400 .word 0x40006400
08001488 <_ZL12MX_SPI1_Initv>:
* @brief SPI1 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI1_Init(void)
{
8001488: b580 push {r7, lr}
800148a: af00 add r7, sp, #0
/* USER CODE BEGIN SPI1_Init 1 */
/* USER CODE END SPI1_Init 1 */
/* SPI1 parameter configuration*/
hspi1.Instance = SPI1;
800148c: 4b1d ldr r3, [pc, #116] ; (8001504 <_ZL12MX_SPI1_Initv+0x7c>)
800148e: 4a1e ldr r2, [pc, #120] ; (8001508 <_ZL12MX_SPI1_Initv+0x80>)
8001490: 601a str r2, [r3, #0]
hspi1.Init.Mode = SPI_MODE_MASTER;
8001492: 4b1c ldr r3, [pc, #112] ; (8001504 <_ZL12MX_SPI1_Initv+0x7c>)
8001494: f44f 7282 mov.w r2, #260 ; 0x104
8001498: 605a str r2, [r3, #4]
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
800149a: 4b1a ldr r3, [pc, #104] ; (8001504 <_ZL12MX_SPI1_Initv+0x7c>)
800149c: 2200 movs r2, #0
800149e: 609a str r2, [r3, #8]
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
80014a0: 4b18 ldr r3, [pc, #96] ; (8001504 <_ZL12MX_SPI1_Initv+0x7c>)
80014a2: f44f 62e0 mov.w r2, #1792 ; 0x700
80014a6: 60da str r2, [r3, #12]
hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;
80014a8: 4b16 ldr r3, [pc, #88] ; (8001504 <_ZL12MX_SPI1_Initv+0x7c>)
80014aa: 2202 movs r2, #2
80014ac: 611a str r2, [r3, #16]
hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;
80014ae: 4b15 ldr r3, [pc, #84] ; (8001504 <_ZL12MX_SPI1_Initv+0x7c>)
80014b0: 2201 movs r2, #1
80014b2: 615a str r2, [r3, #20]
hspi1.Init.NSS = SPI_NSS_SOFT;
80014b4: 4b13 ldr r3, [pc, #76] ; (8001504 <_ZL12MX_SPI1_Initv+0x7c>)
80014b6: f44f 7200 mov.w r2, #512 ; 0x200
80014ba: 619a str r2, [r3, #24]
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
80014bc: 4b11 ldr r3, [pc, #68] ; (8001504 <_ZL12MX_SPI1_Initv+0x7c>)
80014be: 2200 movs r2, #0
80014c0: 61da str r2, [r3, #28]
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
80014c2: 4b10 ldr r3, [pc, #64] ; (8001504 <_ZL12MX_SPI1_Initv+0x7c>)
80014c4: 2200 movs r2, #0
80014c6: 621a str r2, [r3, #32]
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
80014c8: 4b0e ldr r3, [pc, #56] ; (8001504 <_ZL12MX_SPI1_Initv+0x7c>)
80014ca: 2200 movs r2, #0
80014cc: 625a str r2, [r3, #36] ; 0x24
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
80014ce: 4b0d ldr r3, [pc, #52] ; (8001504 <_ZL12MX_SPI1_Initv+0x7c>)
80014d0: 2200 movs r2, #0
80014d2: 629a str r2, [r3, #40] ; 0x28
hspi1.Init.CRCPolynomial = 7;
80014d4: 4b0b ldr r3, [pc, #44] ; (8001504 <_ZL12MX_SPI1_Initv+0x7c>)
80014d6: 2207 movs r2, #7
80014d8: 62da str r2, [r3, #44] ; 0x2c
hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
80014da: 4b0a ldr r3, [pc, #40] ; (8001504 <_ZL12MX_SPI1_Initv+0x7c>)
80014dc: 2200 movs r2, #0
80014de: 631a str r2, [r3, #48] ; 0x30
hspi1.Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
80014e0: 4b08 ldr r3, [pc, #32] ; (8001504 <_ZL12MX_SPI1_Initv+0x7c>)
80014e2: 2200 movs r2, #0
80014e4: 635a str r2, [r3, #52] ; 0x34
if (HAL_SPI_Init(&hspi1) != HAL_OK)
80014e6: 4807 ldr r0, [pc, #28] ; (8001504 <_ZL12MX_SPI1_Initv+0x7c>)
80014e8: f002 fcce bl 8003e88 <HAL_SPI_Init>
80014ec: 4603 mov r3, r0
80014ee: 2b00 cmp r3, #0
80014f0: bf14 ite ne
80014f2: 2301 movne r3, #1
80014f4: 2300 moveq r3, #0
80014f6: b2db uxtb r3, r3
80014f8: 2b00 cmp r3, #0
80014fa: d001 beq.n 8001500 <_ZL12MX_SPI1_Initv+0x78>
{
Error_Handler();
80014fc: f000 f846 bl 800158c <Error_Handler>
}
/* USER CODE BEGIN SPI1_Init 2 */
/* USER CODE END SPI1_Init 2 */
}
8001500: bf00 nop
8001502: bd80 pop {r7, pc}
8001504: 200000e0 .word 0x200000e0
8001508: 40013000 .word 0x40013000
0800150c <_ZL12MX_GPIO_Initv>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
800150c: b580 push {r7, lr}
800150e: b088 sub sp, #32
8001510: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001512: f107 030c add.w r3, r7, #12
8001516: 2200 movs r2, #0
8001518: 601a str r2, [r3, #0]
800151a: 605a str r2, [r3, #4]
800151c: 609a str r2, [r3, #8]
800151e: 60da str r2, [r3, #12]
8001520: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOF_CLK_ENABLE();
8001522: 4b19 ldr r3, [pc, #100] ; (8001588 <_ZL12MX_GPIO_Initv+0x7c>)
8001524: 695b ldr r3, [r3, #20]
8001526: 4a18 ldr r2, [pc, #96] ; (8001588 <_ZL12MX_GPIO_Initv+0x7c>)
8001528: f443 0380 orr.w r3, r3, #4194304 ; 0x400000
800152c: 6153 str r3, [r2, #20]
800152e: 4b16 ldr r3, [pc, #88] ; (8001588 <_ZL12MX_GPIO_Initv+0x7c>)
8001530: 695b ldr r3, [r3, #20]
8001532: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8001536: 60bb str r3, [r7, #8]
8001538: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
800153a: 4b13 ldr r3, [pc, #76] ; (8001588 <_ZL12MX_GPIO_Initv+0x7c>)
800153c: 695b ldr r3, [r3, #20]
800153e: 4a12 ldr r2, [pc, #72] ; (8001588 <_ZL12MX_GPIO_Initv+0x7c>)
8001540: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8001544: 6153 str r3, [r2, #20]
8001546: 4b10 ldr r3, [pc, #64] ; (8001588 <_ZL12MX_GPIO_Initv+0x7c>)
8001548: 695b ldr r3, [r3, #20]
800154a: f403 3300 and.w r3, r3, #131072 ; 0x20000
800154e: 607b str r3, [r7, #4]
8001550: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, SPI1_CS_Pin|NRST_VN_Pin, GPIO_PIN_SET);
8001552: 2201 movs r2, #1
8001554: f44f 61c0 mov.w r1, #1536 ; 0x600
8001558: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
800155c: f001 fa56 bl 8002a0c <HAL_GPIO_WritePin>
/*Configure GPIO pins : SPI1_CS_Pin NRST_VN_Pin */
GPIO_InitStruct.Pin = SPI1_CS_Pin|NRST_VN_Pin;
8001560: f44f 63c0 mov.w r3, #1536 ; 0x600
8001564: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001566: 2301 movs r3, #1
8001568: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_PULLUP;
800156a: 2301 movs r3, #1
800156c: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
800156e: 2303 movs r3, #3
8001570: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001572: f107 030c add.w r3, r7, #12
8001576: 4619 mov r1, r3
8001578: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
800157c: f001 f8cc bl 8002718 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8001580: bf00 nop
8001582: 3720 adds r7, #32
8001584: 46bd mov sp, r7
8001586: bd80 pop {r7, pc}
8001588: 40021000 .word 0x40021000
0800158c <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
800158c: b480 push {r7}
800158e: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8001590: b672 cpsid i
}
8001592: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8001594: e7fe b.n 8001594 <Error_Handler+0x8>
08001596 <_Z7spi2canIN2vn22InsSolutionLlaRegisterEE17HAL_StatusTypeDefP19__SPI_HandleTypeDefP19__CAN_HandleTypeDefRKt>:
HAL_StatusTypeDef spi2can(SPI_HandleTypeDef *hspi, CAN_HandleTypeDef *hcan, const uint16_t& id){
8001596: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
800159a: b0b8 sub sp, #224 ; 0xe0
800159c: af00 add r7, sp, #0
800159e: 60f8 str r0, [r7, #12]
80015a0: 60b9 str r1, [r7, #8]
80015a2: 607a str r2, [r7, #4]
auto request = vn::pkg_request_read_t(id);
80015a4: 687b ldr r3, [r7, #4]
80015a6: 881b ldrh r3, [r3, #0]
80015a8: b2da uxtb r2, r3
80015aa: f107 03b4 add.w r3, r7, #180 ; 0xb4
80015ae: 4611 mov r1, r2
80015b0: 4618 mov r0, r3
80015b2: f7ff fdf4 bl 800119e <_ZN2vn18pkg_request_read_tC1Eh>
auto response = vn::pkg_response_t<payload_t>();
80015b6: f107 0360 add.w r3, r7, #96 ; 0x60
80015ba: 4618 mov r0, r3
80015bc: f000 f873 bl 80016a6 <_ZN2vn14pkg_response_tINS_22InsSolutionLlaRegisterEEC1Ev>
size_t datalen = 8;
80015c0: 2308 movs r3, #8
80015c2: f8c7 30dc str.w r3, [r7, #220] ; 0xdc
uint16_t can_id = 0;
80015c6: 2300 movs r3, #0
80015c8: f8a7 30da strh.w r3, [r7, #218] ; 0xda
spi_read(hspi, &request, &response);
80015cc: f107 0260 add.w r2, r7, #96 ; 0x60
80015d0: f107 03b4 add.w r3, r7, #180 ; 0xb4
80015d4: 4619 mov r1, r3
80015d6: 68f8 ldr r0, [r7, #12]
80015d8: f000 f877 bl 80016ca <_Z8spi_readIN2vn22InsSolutionLlaRegisterEE17HAL_StatusTypeDefP19__SPI_HandleTypeDefPNS0_18pkg_request_read_tEPNS0_14pkg_response_tIT_EE>
switch (id) {
80015dc: 687b ldr r3, [r7, #4]
80015de: 881b ldrh r3, [r3, #0]
80015e0: 2b40 cmp r3, #64 ; 0x40
80015e2: d159 bne.n 8001698 <_Z7spi2canIN2vn22InsSolutionLlaRegisterEE17HAL_StatusTypeDefP19__SPI_HandleTypeDefP19__CAN_HandleTypeDefRKt+0x102>
can_id = CAN1_VN200_INS_YPR_FRAME_ID;
80015e4: 2306 movs r3, #6
80015e6: f8a7 30da strh.w r3, [r7, #218] ; 0xda
vn::InsSolutionLlaRegister payload;
80015ea: f107 0310 add.w r3, r7, #16
80015ee: 4618 mov r0, r3
80015f0: f7ff fe02 bl 80011f8 <_ZN2vn22InsSolutionLlaRegisterC1Ev>
payload = response.payload;
80015f4: f107 0310 add.w r3, r7, #16
80015f8: f107 0168 add.w r1, r7, #104 ; 0x68
80015fc: 2248 movs r2, #72 ; 0x48
80015fe: 4618 mov r0, r3
8001600: f7fe fe2a bl 8000258 <memcpy>
auto data = canlib::encode::can1::vn200_ins_ypr(canlib::frame::decoded::can1::vn200_ins_ypr_t((double) payload.yawPitchRoll.x, (double) payload.yawPitchRoll.y, (double) payload.yawPitchRoll.z, (double) payload.attUncertainty));
8001604: 69fb ldr r3, [r7, #28]
8001606: 4618 mov r0, r3
8001608: f7ff f876 bl 80006f8 <__aeabi_f2d>
800160c: 4604 mov r4, r0
800160e: 460d mov r5, r1
8001610: 6a3b ldr r3, [r7, #32]
8001612: 4618 mov r0, r3
8001614: f7ff f870 bl 80006f8 <__aeabi_f2d>
8001618: 4680 mov r8, r0
800161a: 4689 mov r9, r1
800161c: 6a7b ldr r3, [r7, #36] ; 0x24
800161e: 4618 mov r0, r3
8001620: f7ff f86a bl 80006f8 <__aeabi_f2d>
8001624: 4682 mov sl, r0
8001626: 468b mov fp, r1
8001628: 6cfb ldr r3, [r7, #76] ; 0x4c
800162a: 4618 mov r0, r3
800162c: f7ff f864 bl 80006f8 <__aeabi_f2d>
8001630: f107 03b8 add.w r3, r7, #184 ; 0xb8
8001634: ec41 0b13 vmov d3, r0, r1
8001638: ec4b ab12 vmov d2, sl, fp
800163c: ec49 8b11 vmov d1, r8, r9
8001640: ec45 4b10 vmov d0, r4, r5
8001644: 4618 mov r0, r3
8001646: f7ff fe04 bl 8001252 <_ZN6canlib5frame7decoded4can115vn200_ins_ypr_tC1Edddd>
800164a: f107 0358 add.w r3, r7, #88 ; 0x58
800164e: ed97 4b2e vldr d4, [r7, #184] ; 0xb8
8001652: ed97 5b30 vldr d5, [r7, #192] ; 0xc0
8001656: ed97 6b32 vldr d6, [r7, #200] ; 0xc8
800165a: ed97 7b34 vldr d7, [r7, #208] ; 0xd0
800165e: eeb0 0a44 vmov.f32 s0, s8
8001662: eef0 0a64 vmov.f32 s1, s9
8001666: eeb0 1a45 vmov.f32 s2, s10
800166a: eef0 1a65 vmov.f32 s3, s11
800166e: eeb0 2a46 vmov.f32 s4, s12
8001672: eef0 2a66 vmov.f32 s5, s13
8001676: eeb0 3a47 vmov.f32 s6, s14
800167a: eef0 3a67 vmov.f32 s7, s15
800167e: 4618 mov r0, r3
8001680: f7ff fe0e bl 80012a0 <_ZN6canlib6encode4can113vn200_ins_yprENS_5frame7decoded4can115vn200_ins_ypr_tE>
ftcan_transmit(hcan, can_id, (uint8_t*)(&data), datalen);
8001684: f107 0258 add.w r2, r7, #88 ; 0x58
8001688: f8b7 10da ldrh.w r1, [r7, #218] ; 0xda
800168c: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
8001690: 68b8 ldr r0, [r7, #8]
8001692: f7ff fd2d bl 80010f0 <_Z14ftcan_transmitP19__CAN_HandleTypeDeftPKhj>
break;
8001696: e000 b.n 800169a <_Z7spi2canIN2vn22InsSolutionLlaRegisterEE17HAL_StatusTypeDefP19__SPI_HandleTypeDefP19__CAN_HandleTypeDefRKt+0x104>
break;
8001698: bf00 nop
return HAL_OK;
800169a: 2300 movs r3, #0
}
800169c: 4618 mov r0, r3
800169e: 37e0 adds r7, #224 ; 0xe0
80016a0: 46bd mov sp, r7
80016a2: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
080016a6 <_ZN2vn14pkg_response_tINS_22InsSolutionLlaRegisterEEC1Ev>:
/** \brief Response structure for the specified register */
template <typename payload_t> struct pkg_response_t {
struct header_t::response_t header;
payload_t payload;
pkg_response_t() : header(){};
80016a6: b580 push {r7, lr}
80016a8: b082 sub sp, #8
80016aa: af00 add r7, sp, #0
80016ac: 6078 str r0, [r7, #4]
80016ae: 687b ldr r3, [r7, #4]
80016b0: 4618 mov r0, r3
80016b2: f7ff fd5d bl 8001170 <_ZN2vn8header_t10response_tC1Ev>
80016b6: 687b ldr r3, [r7, #4]
80016b8: 3308 adds r3, #8
80016ba: 4618 mov r0, r3
80016bc: f7ff fd9c bl 80011f8 <_ZN2vn22InsSolutionLlaRegisterC1Ev>
80016c0: 687b ldr r3, [r7, #4]
80016c2: 4618 mov r0, r3
80016c4: 3708 adds r7, #8
80016c6: 46bd mov sp, r7
80016c8: bd80 pop {r7, pc}
080016ca <_Z8spi_readIN2vn22InsSolutionLlaRegisterEE17HAL_StatusTypeDefP19__SPI_HandleTypeDefPNS0_18pkg_request_read_tEPNS0_14pkg_response_tIT_EE>:
HAL_StatusTypeDef spi_read(SPI_HandleTypeDef *hspi, vn::pkg_request_read_t *pRequestMOSI, vn::pkg_response_t<payload_t> *pResponseMISO){
80016ca: b580 push {r7, lr}
80016cc: b09c sub sp, #112 ; 0x70
80016ce: af02 add r7, sp, #8
80016d0: 60f8 str r0, [r7, #12]
80016d2: 60b9 str r1, [r7, #8]
80016d4: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80016d6: 2300 movs r3, #0
80016d8: f887 3067 strb.w r3, [r7, #103] ; 0x67
vn::header_t::response_t requestMISO;
80016dc: f107 0360 add.w r3, r7, #96 ; 0x60
80016e0: 4618 mov r0, r3
80016e2: f7ff fd45 bl 8001170 <_ZN2vn8header_t10response_tC1Ev>
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_RESET);
80016e6: 2200 movs r2, #0
80016e8: f44f 7100 mov.w r1, #512 ; 0x200
80016ec: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
80016f0: f001 f98c bl 8002a0c <HAL_GPIO_WritePin>
status = HAL_SPI_TransmitReceive(hspi,
80016f4: f107 0260 add.w r2, r7, #96 ; 0x60
80016f8: 2364 movs r3, #100 ; 0x64
80016fa: 9300 str r3, [sp, #0]
80016fc: 2304 movs r3, #4
80016fe: 68b9 ldr r1, [r7, #8]
8001700: 68f8 ldr r0, [r7, #12]
8001702: f002 fc6c bl 8003fde <HAL_SPI_TransmitReceive>
8001706: 4603 mov r3, r0
8001708: f887 3067 strb.w r3, [r7, #103] ; 0x67
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_SET);
800170c: 2201 movs r2, #1
800170e: f44f 7100 mov.w r1, #512 ; 0x200
8001712: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
8001716: f001 f979 bl 8002a0c <HAL_GPIO_WritePin>
HAL_Delay(1);
800171a: 2001 movs r0, #1
800171c: f000 fac2 bl 8001ca4 <HAL_Delay>
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_RESET);
8001720: 2200 movs r2, #0
8001722: f44f 7100 mov.w r1, #512 ; 0x200
8001726: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
800172a: f001 f96f bl 8002a0c <HAL_GPIO_WritePin>
vn::pkg_response_t<payload_t> responseMOSI;
800172e: f107 0310 add.w r3, r7, #16
8001732: 4618 mov r0, r3
8001734: f7ff ffb7 bl 80016a6 <_ZN2vn14pkg_response_tINS_22InsSolutionLlaRegisterEEC1Ev>
status = HAL_SPI_TransmitReceive(hspi,
8001738: f107 0110 add.w r1, r7, #16
800173c: 2364 movs r3, #100 ; 0x64
800173e: 9300 str r3, [sp, #0]
8001740: 2350 movs r3, #80 ; 0x50
8001742: 687a ldr r2, [r7, #4]
8001744: 68f8 ldr r0, [r7, #12]
8001746: f002 fc4a bl 8003fde <HAL_SPI_TransmitReceive>
800174a: 4603 mov r3, r0
800174c: f887 3067 strb.w r3, [r7, #103] ; 0x67
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_SET);
8001750: 2201 movs r2, #1
8001752: f44f 7100 mov.w r1, #512 ; 0x200
8001756: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
800175a: f001 f957 bl 8002a0c <HAL_GPIO_WritePin>
return status;
800175e: f897 3067 ldrb.w r3, [r7, #103] ; 0x67
}
8001762: 4618 mov r0, r3
8001764: 3768 adds r7, #104 ; 0x68
8001766: 46bd mov sp, r7
8001768: bd80 pop {r7, pc}
...
0800176c <_Z41__static_initialization_and_destruction_0ii>:
{
}
/* USER CODE END Error_Handler_Debug */
}
800176c: b580 push {r7, lr}
800176e: b082 sub sp, #8
8001770: af00 add r7, sp, #0
8001772: 6078 str r0, [r7, #4]
8001774: 6039 str r1, [r7, #0]
8001776: 687b ldr r3, [r7, #4]
8001778: 2b01 cmp r3, #1
800177a: d170 bne.n 800185e <_Z41__static_initialization_and_destruction_0ii+0xf2>
800177c: 683b ldr r3, [r7, #0]
800177e: f64f 72ff movw r2, #65535 ; 0xffff
8001782: 4293 cmp r3, r2
8001784: d16b bne.n 800185e <_Z41__static_initialization_and_destruction_0ii+0xf2>
inline std::function<void(can1_vn200_gnss_ll_t, frame::decoded::can1::vn200_gnss_ll_t)> vn200_gnss_ll = NULL;
8001786: 4b6f ldr r3, [pc, #444] ; (8001944 <_Z41__static_initialization_and_destruction_0ii+0x1d8>)
8001788: 681b ldr r3, [r3, #0]
800178a: 3301 adds r3, #1
800178c: 4a6d ldr r2, [pc, #436] ; (8001944 <_Z41__static_initialization_and_destruction_0ii+0x1d8>)
800178e: 6013 str r3, [r2, #0]
8001790: 4b6c ldr r3, [pc, #432] ; (8001944 <_Z41__static_initialization_and_destruction_0ii+0x1d8>)
8001792: 681b ldr r3, [r3, #0]
8001794: 2b01 cmp r3, #1
8001796: bf0c ite eq
8001798: 2301 moveq r3, #1
800179a: 2300 movne r3, #0
800179c: b2db uxtb r3, r3
800179e: 2b00 cmp r3, #0
80017a0: d003 beq.n 80017aa <_Z41__static_initialization_and_destruction_0ii+0x3e>
80017a2: 2100 movs r1, #0
80017a4: 4868 ldr r0, [pc, #416] ; (8001948 <_Z41__static_initialization_and_destruction_0ii+0x1dc>)
80017a6: f7ff fac8 bl 8000d3a <_ZNSt8functionIFv20can1_vn200_gnss_ll_tN6canlib5frame7decoded4can115vn200_gnss_ll_tEEEC1EDn>
inline std::function<void(can1_vn200_ins_ypr_t, frame::decoded::can1::vn200_ins_ypr_t)> vn200_ins_ypr = NULL;
80017aa: 4b68 ldr r3, [pc, #416] ; (800194c <_Z41__static_initialization_and_destruction_0ii+0x1e0>)
80017ac: 681b ldr r3, [r3, #0]
80017ae: 3301 adds r3, #1
80017b0: 4a66 ldr r2, [pc, #408] ; (800194c <_Z41__static_initialization_and_destruction_0ii+0x1e0>)
80017b2: 6013 str r3, [r2, #0]
80017b4: 4b65 ldr r3, [pc, #404] ; (800194c <_Z41__static_initialization_and_destruction_0ii+0x1e0>)
80017b6: 681b ldr r3, [r3, #0]
80017b8: 2b01 cmp r3, #1
80017ba: bf0c ite eq
80017bc: 2301 moveq r3, #1
80017be: 2300 movne r3, #0
80017c0: b2db uxtb r3, r3
80017c2: 2b00 cmp r3, #0
80017c4: d003 beq.n 80017ce <_Z41__static_initialization_and_destruction_0ii+0x62>
80017c6: 2100 movs r1, #0
80017c8: 4861 ldr r0, [pc, #388] ; (8001950 <_Z41__static_initialization_and_destruction_0ii+0x1e4>)
80017ca: f7ff fac4 bl 8000d56 <_ZNSt8functionIFv20can1_vn200_ins_ypr_tN6canlib5frame7decoded4can115vn200_ins_ypr_tEEEC1EDn>
inline std::function<void(can1_vn200_imu_acc_lin_t, frame::decoded::can1::vn200_imu_acc_lin_t)> vn200_imu_acc_lin = NULL;
80017ce: 4b61 ldr r3, [pc, #388] ; (8001954 <_Z41__static_initialization_and_destruction_0ii+0x1e8>)
80017d0: 681b ldr r3, [r3, #0]
80017d2: 3301 adds r3, #1
80017d4: 4a5f ldr r2, [pc, #380] ; (8001954 <_Z41__static_initialization_and_destruction_0ii+0x1e8>)
80017d6: 6013 str r3, [r2, #0]
80017d8: 4b5e ldr r3, [pc, #376] ; (8001954 <_Z41__static_initialization_and_destruction_0ii+0x1e8>)
80017da: 681b ldr r3, [r3, #0]
80017dc: 2b01 cmp r3, #1
80017de: bf0c ite eq
80017e0: 2301 moveq r3, #1
80017e2: 2300 movne r3, #0
80017e4: b2db uxtb r3, r3
80017e6: 2b00 cmp r3, #0
80017e8: d003 beq.n 80017f2 <_Z41__static_initialization_and_destruction_0ii+0x86>
80017ea: 2100 movs r1, #0
80017ec: 485a ldr r0, [pc, #360] ; (8001958 <_Z41__static_initialization_and_destruction_0ii+0x1ec>)
80017ee: f7ff fac0 bl 8000d72 <_ZNSt8functionIFv24can1_vn200_imu_acc_lin_tN6canlib5frame7decoded4can119vn200_imu_acc_lin_tEEEC1EDn>
inline std::function<void(can1_vn200_imu_acc_ang_t, frame::decoded::can1::vn200_imu_acc_ang_t)> vn200_imu_acc_ang = NULL;
80017f2: 4b5a ldr r3, [pc, #360] ; (800195c <_Z41__static_initialization_and_destruction_0ii+0x1f0>)
80017f4: 681b ldr r3, [r3, #0]
80017f6: 3301 adds r3, #1
80017f8: 4a58 ldr r2, [pc, #352] ; (800195c <_Z41__static_initialization_and_destruction_0ii+0x1f0>)
80017fa: 6013 str r3, [r2, #0]
80017fc: 4b57 ldr r3, [pc, #348] ; (800195c <_Z41__static_initialization_and_destruction_0ii+0x1f0>)
80017fe: 681b ldr r3, [r3, #0]
8001800: 2b01 cmp r3, #1
8001802: bf0c ite eq
8001804: 2301 moveq r3, #1
8001806: 2300 movne r3, #0
8001808: b2db uxtb r3, r3
800180a: 2b00 cmp r3, #0
800180c: d003 beq.n 8001816 <_Z41__static_initialization_and_destruction_0ii+0xaa>
800180e: 2100 movs r1, #0
8001810: 4853 ldr r0, [pc, #332] ; (8001960 <_Z41__static_initialization_and_destruction_0ii+0x1f4>)
8001812: f7ff fabc bl 8000d8e <_ZNSt8functionIFv24can1_vn200_imu_acc_ang_tN6canlib5frame7decoded4can119vn200_imu_acc_ang_tEEEC1EDn>
inline std::function<void(can1_vn200_ins_ll_t, frame::decoded::can1::vn200_ins_ll_t)> vn200_ins_ll = NULL;
8001816: 4b53 ldr r3, [pc, #332] ; (8001964 <_Z41__static_initialization_and_destruction_0ii+0x1f8>)
8001818: 681b ldr r3, [r3, #0]
800181a: 3301 adds r3, #1
800181c: 4a51 ldr r2, [pc, #324] ; (8001964 <_Z41__static_initialization_and_destruction_0ii+0x1f8>)
800181e: 6013 str r3, [r2, #0]
8001820: 4b50 ldr r3, [pc, #320] ; (8001964 <_Z41__static_initialization_and_destruction_0ii+0x1f8>)
8001822: 681b ldr r3, [r3, #0]
8001824: 2b01 cmp r3, #1
8001826: bf0c ite eq
8001828: 2301 moveq r3, #1
800182a: 2300 movne r3, #0
800182c: b2db uxtb r3, r3
800182e: 2b00 cmp r3, #0
8001830: d003 beq.n 800183a <_Z41__static_initialization_and_destruction_0ii+0xce>
8001832: 2100 movs r1, #0
8001834: 484c ldr r0, [pc, #304] ; (8001968 <_Z41__static_initialization_and_destruction_0ii+0x1fc>)
8001836: f7ff fab8 bl 8000daa <_ZNSt8functionIFv19can1_vn200_ins_ll_tN6canlib5frame7decoded4can114vn200_ins_ll_tEEEC1EDn>
inline std::function<void(can1_vn200_ins_vel_t, frame::decoded::can1::vn200_ins_vel_t)> vn200_ins_vel = NULL;
800183a: 4b4c ldr r3, [pc, #304] ; (800196c <_Z41__static_initialization_and_destruction_0ii+0x200>)
800183c: 681b ldr r3, [r3, #0]
800183e: 3301 adds r3, #1
8001840: 4a4a ldr r2, [pc, #296] ; (800196c <_Z41__static_initialization_and_destruction_0ii+0x200>)
8001842: 6013 str r3, [r2, #0]
8001844: 4b49 ldr r3, [pc, #292] ; (800196c <_Z41__static_initialization_and_destruction_0ii+0x200>)
8001846: 681b ldr r3, [r3, #0]
8001848: 2b01 cmp r3, #1
800184a: bf0c ite eq
800184c: 2301 moveq r3, #1
800184e: 2300 movne r3, #0
8001850: b2db uxtb r3, r3
8001852: 2b00 cmp r3, #0
8001854: d003 beq.n 800185e <_Z41__static_initialization_and_destruction_0ii+0xf2>
8001856: 2100 movs r1, #0
8001858: 4845 ldr r0, [pc, #276] ; (8001970 <_Z41__static_initialization_and_destruction_0ii+0x204>)
800185a: f7ff fab4 bl 8000dc6 <_ZNSt8functionIFv20can1_vn200_ins_vel_tN6canlib5frame7decoded4can115vn200_ins_vel_tEEEC1EDn>
800185e: 687b ldr r3, [r7, #4]
8001860: 2b00 cmp r3, #0
8001862: d16a bne.n 800193a <_Z41__static_initialization_and_destruction_0ii+0x1ce>
8001864: 683b ldr r3, [r7, #0]
8001866: f64f 72ff movw r2, #65535 ; 0xffff
800186a: 4293 cmp r3, r2
800186c: d165 bne.n 800193a <_Z41__static_initialization_and_destruction_0ii+0x1ce>
800186e: 4b3f ldr r3, [pc, #252] ; (800196c <_Z41__static_initialization_and_destruction_0ii+0x200>)
8001870: 681b ldr r3, [r3, #0]
8001872: 3b01 subs r3, #1
8001874: 4a3d ldr r2, [pc, #244] ; (800196c <_Z41__static_initialization_and_destruction_0ii+0x200>)
8001876: 6013 str r3, [r2, #0]
8001878: 4b3c ldr r3, [pc, #240] ; (800196c <_Z41__static_initialization_and_destruction_0ii+0x200>)
800187a: 681b ldr r3, [r3, #0]
800187c: 2b00 cmp r3, #0
800187e: bf0c ite eq
8001880: 2301 moveq r3, #1
8001882: 2300 movne r3, #0
8001884: b2db uxtb r3, r3
8001886: 2b00 cmp r3, #0
8001888: d002 beq.n 8001890 <_Z41__static_initialization_and_destruction_0ii+0x124>
800188a: 4839 ldr r0, [pc, #228] ; (8001970 <_Z41__static_initialization_and_destruction_0ii+0x204>)
800188c: f7ff fa48 bl 8000d20 <_ZNSt8functionIFv20can1_vn200_ins_vel_tN6canlib5frame7decoded4can115vn200_ins_vel_tEEED1Ev>
inline std::function<void(can1_vn200_ins_ll_t, frame::decoded::can1::vn200_ins_ll_t)> vn200_ins_ll = NULL;
8001890: 4b34 ldr r3, [pc, #208] ; (8001964 <_Z41__static_initialization_and_destruction_0ii+0x1f8>)
8001892: 681b ldr r3, [r3, #0]
8001894: 3b01 subs r3, #1
8001896: 4a33 ldr r2, [pc, #204] ; (8001964 <_Z41__static_initialization_and_destruction_0ii+0x1f8>)
8001898: 6013 str r3, [r2, #0]
800189a: 4b32 ldr r3, [pc, #200] ; (8001964 <_Z41__static_initialization_and_destruction_0ii+0x1f8>)
800189c: 681b ldr r3, [r3, #0]
800189e: 2b00 cmp r3, #0
80018a0: bf0c ite eq
80018a2: 2301 moveq r3, #1
80018a4: 2300 movne r3, #0
80018a6: b2db uxtb r3, r3
80018a8: 2b00 cmp r3, #0
80018aa: d002 beq.n 80018b2 <_Z41__static_initialization_and_destruction_0ii+0x146>
80018ac: 482e ldr r0, [pc, #184] ; (8001968 <_Z41__static_initialization_and_destruction_0ii+0x1fc>)
80018ae: f7ff fa2a bl 8000d06 <_ZNSt8functionIFv19can1_vn200_ins_ll_tN6canlib5frame7decoded4can114vn200_ins_ll_tEEED1Ev>
inline std::function<void(can1_vn200_imu_acc_ang_t, frame::decoded::can1::vn200_imu_acc_ang_t)> vn200_imu_acc_ang = NULL;
80018b2: 4b2a ldr r3, [pc, #168] ; (800195c <_Z41__static_initialization_and_destruction_0ii+0x1f0>)
80018b4: 681b ldr r3, [r3, #0]
80018b6: 3b01 subs r3, #1
80018b8: 4a28 ldr r2, [pc, #160] ; (800195c <_Z41__static_initialization_and_destruction_0ii+0x1f0>)
80018ba: 6013 str r3, [r2, #0]
80018bc: 4b27 ldr r3, [pc, #156] ; (800195c <_Z41__static_initialization_and_destruction_0ii+0x1f0>)
80018be: 681b ldr r3, [r3, #0]
80018c0: 2b00 cmp r3, #0
80018c2: bf0c ite eq
80018c4: 2301 moveq r3, #1
80018c6: 2300 movne r3, #0
80018c8: b2db uxtb r3, r3
80018ca: 2b00 cmp r3, #0
80018cc: d002 beq.n 80018d4 <_Z41__static_initialization_and_destruction_0ii+0x168>
80018ce: 4824 ldr r0, [pc, #144] ; (8001960 <_Z41__static_initialization_and_destruction_0ii+0x1f4>)
80018d0: f7ff fa0c bl 8000cec <_ZNSt8functionIFv24can1_vn200_imu_acc_ang_tN6canlib5frame7decoded4can119vn200_imu_acc_ang_tEEED1Ev>
inline std::function<void(can1_vn200_imu_acc_lin_t, frame::decoded::can1::vn200_imu_acc_lin_t)> vn200_imu_acc_lin = NULL;
80018d4: 4b1f ldr r3, [pc, #124] ; (8001954 <_Z41__static_initialization_and_destruction_0ii+0x1e8>)
80018d6: 681b ldr r3, [r3, #0]
80018d8: 3b01 subs r3, #1
80018da: 4a1e ldr r2, [pc, #120] ; (8001954 <_Z41__static_initialization_and_destruction_0ii+0x1e8>)
80018dc: 6013 str r3, [r2, #0]
80018de: 4b1d ldr r3, [pc, #116] ; (8001954 <_Z41__static_initialization_and_destruction_0ii+0x1e8>)
80018e0: 681b ldr r3, [r3, #0]
80018e2: 2b00 cmp r3, #0
80018e4: bf0c ite eq
80018e6: 2301 moveq r3, #1
80018e8: 2300 movne r3, #0
80018ea: b2db uxtb r3, r3
80018ec: 2b00 cmp r3, #0
80018ee: d002 beq.n 80018f6 <_Z41__static_initialization_and_destruction_0ii+0x18a>
80018f0: 4819 ldr r0, [pc, #100] ; (8001958 <_Z41__static_initialization_and_destruction_0ii+0x1ec>)
80018f2: f7ff f9ee bl 8000cd2 <_ZNSt8functionIFv24can1_vn200_imu_acc_lin_tN6canlib5frame7decoded4can119vn200_imu_acc_lin_tEEED1Ev>
inline std::function<void(can1_vn200_ins_ypr_t, frame::decoded::can1::vn200_ins_ypr_t)> vn200_ins_ypr = NULL;
80018f6: 4b15 ldr r3, [pc, #84] ; (800194c <_Z41__static_initialization_and_destruction_0ii+0x1e0>)
80018f8: 681b ldr r3, [r3, #0]
80018fa: 3b01 subs r3, #1
80018fc: 4a13 ldr r2, [pc, #76] ; (800194c <_Z41__static_initialization_and_destruction_0ii+0x1e0>)
80018fe: 6013 str r3, [r2, #0]
8001900: 4b12 ldr r3, [pc, #72] ; (800194c <_Z41__static_initialization_and_destruction_0ii+0x1e0>)
8001902: 681b ldr r3, [r3, #0]
8001904: 2b00 cmp r3, #0
8001906: bf0c ite eq
8001908: 2301 moveq r3, #1
800190a: 2300 movne r3, #0
800190c: b2db uxtb r3, r3
800190e: 2b00 cmp r3, #0
8001910: d002 beq.n 8001918 <_Z41__static_initialization_and_destruction_0ii+0x1ac>
8001912: 480f ldr r0, [pc, #60] ; (8001950 <_Z41__static_initialization_and_destruction_0ii+0x1e4>)
8001914: f7ff f9d0 bl 8000cb8 <_ZNSt8functionIFv20can1_vn200_ins_ypr_tN6canlib5frame7decoded4can115vn200_ins_ypr_tEEED1Ev>
inline std::function<void(can1_vn200_gnss_ll_t, frame::decoded::can1::vn200_gnss_ll_t)> vn200_gnss_ll = NULL;
8001918: 4b0a ldr r3, [pc, #40] ; (8001944 <_Z41__static_initialization_and_destruction_0ii+0x1d8>)
800191a: 681b ldr r3, [r3, #0]
800191c: 3b01 subs r3, #1
800191e: 4a09 ldr r2, [pc, #36] ; (8001944 <_Z41__static_initialization_and_destruction_0ii+0x1d8>)
8001920: 6013 str r3, [r2, #0]
8001922: 4b08 ldr r3, [pc, #32] ; (8001944 <_Z41__static_initialization_and_destruction_0ii+0x1d8>)
8001924: 681b ldr r3, [r3, #0]
8001926: 2b00 cmp r3, #0
8001928: bf0c ite eq
800192a: 2301 moveq r3, #1
800192c: 2300 movne r3, #0
800192e: b2db uxtb r3, r3
8001930: 2b00 cmp r3, #0
8001932: d002 beq.n 800193a <_Z41__static_initialization_and_destruction_0ii+0x1ce>
8001934: 4804 ldr r0, [pc, #16] ; (8001948 <_Z41__static_initialization_and_destruction_0ii+0x1dc>)
8001936: f7ff f9b2 bl 8000c9e <_ZNSt8functionIFv20can1_vn200_gnss_ll_tN6canlib5frame7decoded4can115vn200_gnss_ll_tEEED1Ev>
800193a: bf00 nop
800193c: 3708 adds r7, #8
800193e: 46bd mov sp, r7
8001940: bd80 pop {r7, pc}
8001942: bf00 nop
8001944: 20000088 .word 0x20000088
8001948: 20000028 .word 0x20000028
800194c: 2000008c .word 0x2000008c
8001950: 20000038 .word 0x20000038
8001954: 20000090 .word 0x20000090
8001958: 20000048 .word 0x20000048
800195c: 20000094 .word 0x20000094
8001960: 20000058 .word 0x20000058
8001964: 20000098 .word 0x20000098
8001968: 20000068 .word 0x20000068
800196c: 2000009c .word 0x2000009c
8001970: 20000078 .word 0x20000078
08001974 <_GLOBAL__sub_I_hcan>:
8001974: b580 push {r7, lr}
8001976: af00 add r7, sp, #0
8001978: f64f 71ff movw r1, #65535 ; 0xffff
800197c: 2001 movs r0, #1
800197e: f7ff fef5 bl 800176c <_Z41__static_initialization_and_destruction_0ii>
8001982: bd80 pop {r7, pc}
08001984 <_GLOBAL__sub_D_hcan>:
8001984: b580 push {r7, lr}
8001986: af00 add r7, sp, #0
8001988: f64f 71ff movw r1, #65535 ; 0xffff
800198c: 2000 movs r0, #0
800198e: f7ff feed bl 800176c <_Z41__static_initialization_and_destruction_0ii>
8001992: bd80 pop {r7, pc}
08001994 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8001994: b480 push {r7}
8001996: b083 sub sp, #12
8001998: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
800199a: 4b0f ldr r3, [pc, #60] ; (80019d8 <HAL_MspInit+0x44>)
800199c: 699b ldr r3, [r3, #24]
800199e: 4a0e ldr r2, [pc, #56] ; (80019d8 <HAL_MspInit+0x44>)
80019a0: f043 0301 orr.w r3, r3, #1
80019a4: 6193 str r3, [r2, #24]
80019a6: 4b0c ldr r3, [pc, #48] ; (80019d8 <HAL_MspInit+0x44>)
80019a8: 699b ldr r3, [r3, #24]
80019aa: f003 0301 and.w r3, r3, #1
80019ae: 607b str r3, [r7, #4]
80019b0: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
80019b2: 4b09 ldr r3, [pc, #36] ; (80019d8 <HAL_MspInit+0x44>)
80019b4: 69db ldr r3, [r3, #28]
80019b6: 4a08 ldr r2, [pc, #32] ; (80019d8 <HAL_MspInit+0x44>)
80019b8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
80019bc: 61d3 str r3, [r2, #28]
80019be: 4b06 ldr r3, [pc, #24] ; (80019d8 <HAL_MspInit+0x44>)
80019c0: 69db ldr r3, [r3, #28]
80019c2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80019c6: 603b str r3, [r7, #0]
80019c8: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
80019ca: bf00 nop
80019cc: 370c adds r7, #12
80019ce: 46bd mov sp, r7
80019d0: f85d 7b04 ldr.w r7, [sp], #4
80019d4: 4770 bx lr
80019d6: bf00 nop
80019d8: 40021000 .word 0x40021000
080019dc <HAL_CAN_MspInit>:
* This function configures the hardware resources used in this example
* @param hcan: CAN handle pointer
* @retval None
*/
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
{
80019dc: b580 push {r7, lr}
80019de: b08a sub sp, #40 ; 0x28
80019e0: af00 add r7, sp, #0
80019e2: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80019e4: f107 0314 add.w r3, r7, #20
80019e8: 2200 movs r2, #0
80019ea: 601a str r2, [r3, #0]
80019ec: 605a str r2, [r3, #4]
80019ee: 609a str r2, [r3, #8]
80019f0: 60da str r2, [r3, #12]
80019f2: 611a str r2, [r3, #16]
if(hcan->Instance==CAN)
80019f4: 687b ldr r3, [r7, #4]
80019f6: 681b ldr r3, [r3, #0]
80019f8: 4a1c ldr r2, [pc, #112] ; (8001a6c <HAL_CAN_MspInit+0x90>)
80019fa: 4293 cmp r3, r2
80019fc: d131 bne.n 8001a62 <HAL_CAN_MspInit+0x86>
{
/* USER CODE BEGIN CAN_MspInit 0 */
/* USER CODE END CAN_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_CAN1_CLK_ENABLE();
80019fe: 4b1c ldr r3, [pc, #112] ; (8001a70 <HAL_CAN_MspInit+0x94>)
8001a00: 69db ldr r3, [r3, #28]
8001a02: 4a1b ldr r2, [pc, #108] ; (8001a70 <HAL_CAN_MspInit+0x94>)
8001a04: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
8001a08: 61d3 str r3, [r2, #28]
8001a0a: 4b19 ldr r3, [pc, #100] ; (8001a70 <HAL_CAN_MspInit+0x94>)
8001a0c: 69db ldr r3, [r3, #28]
8001a0e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001a12: 613b str r3, [r7, #16]
8001a14: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001a16: 4b16 ldr r3, [pc, #88] ; (8001a70 <HAL_CAN_MspInit+0x94>)
8001a18: 695b ldr r3, [r3, #20]
8001a1a: 4a15 ldr r2, [pc, #84] ; (8001a70 <HAL_CAN_MspInit+0x94>)
8001a1c: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8001a20: 6153 str r3, [r2, #20]
8001a22: 4b13 ldr r3, [pc, #76] ; (8001a70 <HAL_CAN_MspInit+0x94>)
8001a24: 695b ldr r3, [r3, #20]
8001a26: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001a2a: 60fb str r3, [r7, #12]
8001a2c: 68fb ldr r3, [r7, #12]
/**CAN GPIO Configuration
PA11 ------> CAN_RX
PA12 ------> CAN_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
8001a2e: f44f 53c0 mov.w r3, #6144 ; 0x1800
8001a32: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001a34: 2302 movs r3, #2
8001a36: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a38: 2300 movs r3, #0
8001a3a: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8001a3c: 2303 movs r3, #3
8001a3e: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF9_CAN;
8001a40: 2309 movs r3, #9
8001a42: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001a44: f107 0314 add.w r3, r7, #20
8001a48: 4619 mov r1, r3
8001a4a: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
8001a4e: f000 fe63 bl 8002718 <HAL_GPIO_Init>
/* CAN interrupt Init */
HAL_NVIC_SetPriority(CAN_RX1_IRQn, 0, 0);
8001a52: 2200 movs r2, #0
8001a54: 2100 movs r1, #0
8001a56: 2015 movs r0, #21
8001a58: f000 fe27 bl 80026aa <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(CAN_RX1_IRQn);
8001a5c: 2015 movs r0, #21
8001a5e: f000 fe40 bl 80026e2 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN CAN_MspInit 1 */
/* USER CODE END CAN_MspInit 1 */
}
}
8001a62: bf00 nop
8001a64: 3728 adds r7, #40 ; 0x28
8001a66: 46bd mov sp, r7
8001a68: bd80 pop {r7, pc}
8001a6a: bf00 nop
8001a6c: 40006400 .word 0x40006400
8001a70: 40021000 .word 0x40021000
08001a74 <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
8001a74: b580 push {r7, lr}
8001a76: b08a sub sp, #40 ; 0x28
8001a78: af00 add r7, sp, #0
8001a7a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001a7c: f107 0314 add.w r3, r7, #20
8001a80: 2200 movs r2, #0
8001a82: 601a str r2, [r3, #0]
8001a84: 605a str r2, [r3, #4]
8001a86: 609a str r2, [r3, #8]
8001a88: 60da str r2, [r3, #12]
8001a8a: 611a str r2, [r3, #16]
if(hspi->Instance==SPI1)
8001a8c: 687b ldr r3, [r7, #4]
8001a8e: 681b ldr r3, [r3, #0]
8001a90: 4a17 ldr r2, [pc, #92] ; (8001af0 <HAL_SPI_MspInit+0x7c>)
8001a92: 4293 cmp r3, r2
8001a94: d128 bne.n 8001ae8 <HAL_SPI_MspInit+0x74>
{
/* USER CODE BEGIN SPI1_MspInit 0 */
/* USER CODE END SPI1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI1_CLK_ENABLE();
8001a96: 4b17 ldr r3, [pc, #92] ; (8001af4 <HAL_SPI_MspInit+0x80>)
8001a98: 699b ldr r3, [r3, #24]
8001a9a: 4a16 ldr r2, [pc, #88] ; (8001af4 <HAL_SPI_MspInit+0x80>)
8001a9c: f443 5380 orr.w r3, r3, #4096 ; 0x1000
8001aa0: 6193 str r3, [r2, #24]
8001aa2: 4b14 ldr r3, [pc, #80] ; (8001af4 <HAL_SPI_MspInit+0x80>)
8001aa4: 699b ldr r3, [r3, #24]
8001aa6: f403 5380 and.w r3, r3, #4096 ; 0x1000
8001aaa: 613b str r3, [r7, #16]
8001aac: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001aae: 4b11 ldr r3, [pc, #68] ; (8001af4 <HAL_SPI_MspInit+0x80>)
8001ab0: 695b ldr r3, [r3, #20]
8001ab2: 4a10 ldr r2, [pc, #64] ; (8001af4 <HAL_SPI_MspInit+0x80>)
8001ab4: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8001ab8: 6153 str r3, [r2, #20]
8001aba: 4b0e ldr r3, [pc, #56] ; (8001af4 <HAL_SPI_MspInit+0x80>)
8001abc: 695b ldr r3, [r3, #20]
8001abe: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001ac2: 60fb str r3, [r7, #12]
8001ac4: 68fb ldr r3, [r7, #12]
/**SPI1 GPIO Configuration
PA5 ------> SPI1_SCK
PA6 ------> SPI1_MISO
PA7 ------> SPI1_MOSI
*/
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
8001ac6: 23e0 movs r3, #224 ; 0xe0
8001ac8: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001aca: 2302 movs r3, #2
8001acc: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001ace: 2300 movs r3, #0
8001ad0: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8001ad2: 2303 movs r3, #3
8001ad4: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
8001ad6: 2305 movs r3, #5
8001ad8: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001ada: f107 0314 add.w r3, r7, #20
8001ade: 4619 mov r1, r3
8001ae0: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
8001ae4: f000 fe18 bl 8002718 <HAL_GPIO_Init>
/* USER CODE BEGIN SPI1_MspInit 1 */
/* USER CODE END SPI1_MspInit 1 */
}
}
8001ae8: bf00 nop
8001aea: 3728 adds r7, #40 ; 0x28
8001aec: 46bd mov sp, r7
8001aee: bd80 pop {r7, pc}
8001af0: 40013000 .word 0x40013000
8001af4: 40021000 .word 0x40021000
08001af8 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001af8: b480 push {r7}
8001afa: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8001afc: e7fe b.n 8001afc <NMI_Handler+0x4>
08001afe <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8001afe: b480 push {r7}
8001b00: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8001b02: e7fe b.n 8001b02 <HardFault_Handler+0x4>
08001b04 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8001b04: b480 push {r7}
8001b06: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8001b08: e7fe b.n 8001b08 <MemManage_Handler+0x4>
08001b0a <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8001b0a: b480 push {r7}
8001b0c: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8001b0e: e7fe b.n 8001b0e <BusFault_Handler+0x4>
08001b10 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8001b10: b480 push {r7}
8001b12: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8001b14: e7fe b.n 8001b14 <UsageFault_Handler+0x4>
08001b16 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8001b16: b480 push {r7}
8001b18: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8001b1a: bf00 nop
8001b1c: 46bd mov sp, r7
8001b1e: f85d 7b04 ldr.w r7, [sp], #4
8001b22: 4770 bx lr
08001b24 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8001b24: b480 push {r7}
8001b26: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8001b28: bf00 nop
8001b2a: 46bd mov sp, r7
8001b2c: f85d 7b04 ldr.w r7, [sp], #4
8001b30: 4770 bx lr
08001b32 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8001b32: b480 push {r7}
8001b34: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8001b36: bf00 nop
8001b38: 46bd mov sp, r7
8001b3a: f85d 7b04 ldr.w r7, [sp], #4
8001b3e: 4770 bx lr
08001b40 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8001b40: b580 push {r7, lr}
8001b42: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8001b44: f000 f88e bl 8001c64 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8001b48: bf00 nop
8001b4a: bd80 pop {r7, pc}
08001b4c <CAN_RX1_IRQHandler>:
/**
* @brief This function handles CAN RX1 interrupt.
*/
void CAN_RX1_IRQHandler(void)
{
8001b4c: b580 push {r7, lr}
8001b4e: af00 add r7, sp, #0
/* USER CODE BEGIN CAN_RX1_IRQn 0 */
/* USER CODE END CAN_RX1_IRQn 0 */
HAL_CAN_IRQHandler(&hcan);
8001b50: 4802 ldr r0, [pc, #8] ; (8001b5c <CAN_RX1_IRQHandler+0x10>)
8001b52: f000 fa96 bl 8002082 <HAL_CAN_IRQHandler>
/* USER CODE BEGIN CAN_RX1_IRQn 1 */
/* USER CODE END CAN_RX1_IRQn 1 */
}
8001b56: bf00 nop
8001b58: bd80 pop {r7, pc}
8001b5a: bf00 nop
8001b5c: 200000b8 .word 0x200000b8
08001b60 <SystemInit>:
* @brief Setup the microcontroller system
* @param None
* @retval None
*/
void SystemInit(void)
{
8001b60: b480 push {r7}
8001b62: af00 add r7, sp, #0
/* FPU settings --------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
8001b64: 4b06 ldr r3, [pc, #24] ; (8001b80 <SystemInit+0x20>)
8001b66: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8001b6a: 4a05 ldr r2, [pc, #20] ; (8001b80 <SystemInit+0x20>)
8001b6c: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
8001b70: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
8001b74: bf00 nop
8001b76: 46bd mov sp, r7
8001b78: f85d 7b04 ldr.w r7, [sp], #4
8001b7c: 4770 bx lr
8001b7e: bf00 nop
8001b80: e000ed00 .word 0xe000ed00
08001b84 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Atollic update: set stack pointer */
8001b84: f8df d034 ldr.w sp, [pc, #52] ; 8001bbc <LoopForever+0x2>
/* Call the clock system initialization function.*/
bl SystemInit
8001b88: f7ff ffea bl 8001b60 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8001b8c: 480c ldr r0, [pc, #48] ; (8001bc0 <LoopForever+0x6>)
ldr r1, =_edata
8001b8e: 490d ldr r1, [pc, #52] ; (8001bc4 <LoopForever+0xa>)
ldr r2, =_sidata
8001b90: 4a0d ldr r2, [pc, #52] ; (8001bc8 <LoopForever+0xe>)
movs r3, #0
8001b92: 2300 movs r3, #0
b LoopCopyDataInit
8001b94: e002 b.n 8001b9c <LoopCopyDataInit>
08001b96 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8001b96: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8001b98: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8001b9a: 3304 adds r3, #4
08001b9c <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8001b9c: 18c4 adds r4, r0, r3
cmp r4, r1
8001b9e: 428c cmp r4, r1
bcc CopyDataInit
8001ba0: d3f9 bcc.n 8001b96 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8001ba2: 4a0a ldr r2, [pc, #40] ; (8001bcc <LoopForever+0x12>)
ldr r4, =_ebss
8001ba4: 4c0a ldr r4, [pc, #40] ; (8001bd0 <LoopForever+0x16>)
movs r3, #0
8001ba6: 2300 movs r3, #0
b LoopFillZerobss
8001ba8: e001 b.n 8001bae <LoopFillZerobss>
08001baa <FillZerobss>:
FillZerobss:
str r3, [r2]
8001baa: 6013 str r3, [r2, #0]
adds r2, r2, #4
8001bac: 3204 adds r2, #4
08001bae <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8001bae: 42a2 cmp r2, r4
bcc FillZerobss
8001bb0: d3fb bcc.n 8001baa <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8001bb2: f7fe fb2d bl 8000210 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8001bb6: f7ff fbc5 bl 8001344 <main>
08001bba <LoopForever>:
LoopForever:
b LoopForever
8001bba: e7fe b.n 8001bba <LoopForever>
ldr sp, =_estack /* Atollic update: set stack pointer */
8001bbc: 20008000 .word 0x20008000
ldr r0, =_sdata
8001bc0: 20000000 .word 0x20000000
ldr r1, =_edata
8001bc4: 2000000c .word 0x2000000c
ldr r2, =_sidata
8001bc8: 08004750 .word 0x08004750
ldr r2, =_sbss
8001bcc: 2000000c .word 0x2000000c
ldr r4, =_ebss
8001bd0: 20000148 .word 0x20000148
08001bd4 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8001bd4: e7fe b.n 8001bd4 <ADC1_2_IRQHandler>
...
08001bd8 <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* The tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8001bd8: b580 push {r7, lr}
8001bda: af00 add r7, sp, #0
/* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8001bdc: 4b08 ldr r3, [pc, #32] ; (8001c00 <HAL_Init+0x28>)
8001bde: 681b ldr r3, [r3, #0]
8001be0: 4a07 ldr r2, [pc, #28] ; (8001c00 <HAL_Init+0x28>)
8001be2: f043 0310 orr.w r3, r3, #16
8001be6: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8001be8: 2003 movs r0, #3
8001bea: f000 fd53 bl 8002694 <HAL_NVIC_SetPriorityGrouping>
/* Enable systick and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8001bee: 200f movs r0, #15
8001bf0: f000 f808 bl 8001c04 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8001bf4: f7ff fece bl 8001994 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8001bf8: 2300 movs r3, #0
}
8001bfa: 4618 mov r0, r3
8001bfc: bd80 pop {r7, pc}
8001bfe: bf00 nop
8001c00: 40022000 .word 0x40022000
08001c04 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8001c04: b580 push {r7, lr}
8001c06: b082 sub sp, #8
8001c08: af00 add r7, sp, #0
8001c0a: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8001c0c: 4b12 ldr r3, [pc, #72] ; (8001c58 <HAL_InitTick+0x54>)
8001c0e: 681a ldr r2, [r3, #0]
8001c10: 4b12 ldr r3, [pc, #72] ; (8001c5c <HAL_InitTick+0x58>)
8001c12: 781b ldrb r3, [r3, #0]
8001c14: 4619 mov r1, r3
8001c16: f44f 737a mov.w r3, #1000 ; 0x3e8
8001c1a: fbb3 f3f1 udiv r3, r3, r1
8001c1e: fbb2 f3f3 udiv r3, r2, r3
8001c22: 4618 mov r0, r3
8001c24: f000 fd6b bl 80026fe <HAL_SYSTICK_Config>
8001c28: 4603 mov r3, r0
8001c2a: 2b00 cmp r3, #0
8001c2c: d001 beq.n 8001c32 <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8001c2e: 2301 movs r3, #1
8001c30: e00e b.n 8001c50 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8001c32: 687b ldr r3, [r7, #4]
8001c34: 2b0f cmp r3, #15
8001c36: d80a bhi.n 8001c4e <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8001c38: 2200 movs r2, #0
8001c3a: 6879 ldr r1, [r7, #4]
8001c3c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
8001c40: f000 fd33 bl 80026aa <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8001c44: 4a06 ldr r2, [pc, #24] ; (8001c60 <HAL_InitTick+0x5c>)
8001c46: 687b ldr r3, [r7, #4]
8001c48: 6013 str r3, [r2, #0]
else
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8001c4a: 2300 movs r3, #0
8001c4c: e000 b.n 8001c50 <HAL_InitTick+0x4c>
return HAL_ERROR;
8001c4e: 2301 movs r3, #1
}
8001c50: 4618 mov r0, r3
8001c52: 3708 adds r7, #8
8001c54: 46bd mov sp, r7
8001c56: bd80 pop {r7, pc}
8001c58: 20000000 .word 0x20000000
8001c5c: 20000008 .word 0x20000008
8001c60: 20000004 .word 0x20000004
08001c64 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8001c64: b480 push {r7}
8001c66: af00 add r7, sp, #0
uwTick += uwTickFreq;
8001c68: 4b06 ldr r3, [pc, #24] ; (8001c84 <HAL_IncTick+0x20>)
8001c6a: 781b ldrb r3, [r3, #0]
8001c6c: 461a mov r2, r3
8001c6e: 4b06 ldr r3, [pc, #24] ; (8001c88 <HAL_IncTick+0x24>)
8001c70: 681b ldr r3, [r3, #0]
8001c72: 4413 add r3, r2
8001c74: 4a04 ldr r2, [pc, #16] ; (8001c88 <HAL_IncTick+0x24>)
8001c76: 6013 str r3, [r2, #0]
}
8001c78: bf00 nop
8001c7a: 46bd mov sp, r7
8001c7c: f85d 7b04 ldr.w r7, [sp], #4
8001c80: 4770 bx lr
8001c82: bf00 nop
8001c84: 20000008 .word 0x20000008
8001c88: 20000144 .word 0x20000144
08001c8c <HAL_GetTick>:
* @note The function is declared as __Weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8001c8c: b480 push {r7}
8001c8e: af00 add r7, sp, #0
return uwTick;
8001c90: 4b03 ldr r3, [pc, #12] ; (8001ca0 <HAL_GetTick+0x14>)
8001c92: 681b ldr r3, [r3, #0]
}
8001c94: 4618 mov r0, r3
8001c96: 46bd mov sp, r7
8001c98: f85d 7b04 ldr.w r7, [sp], #4
8001c9c: 4770 bx lr
8001c9e: bf00 nop
8001ca0: 20000144 .word 0x20000144
08001ca4 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8001ca4: b580 push {r7, lr}
8001ca6: b084 sub sp, #16
8001ca8: af00 add r7, sp, #0
8001caa: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8001cac: f7ff ffee bl 8001c8c <HAL_GetTick>
8001cb0: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8001cb2: 687b ldr r3, [r7, #4]
8001cb4: 60fb str r3, [r7, #12]
/* Add freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
8001cb6: 68fb ldr r3, [r7, #12]
8001cb8: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
8001cbc: d005 beq.n 8001cca <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
8001cbe: 4b0a ldr r3, [pc, #40] ; (8001ce8 <HAL_Delay+0x44>)
8001cc0: 781b ldrb r3, [r3, #0]
8001cc2: 461a mov r2, r3
8001cc4: 68fb ldr r3, [r7, #12]
8001cc6: 4413 add r3, r2
8001cc8: 60fb str r3, [r7, #12]
}
while((HAL_GetTick() - tickstart) < wait)
8001cca: bf00 nop
8001ccc: f7ff ffde bl 8001c8c <HAL_GetTick>
8001cd0: 4602 mov r2, r0
8001cd2: 68bb ldr r3, [r7, #8]
8001cd4: 1ad3 subs r3, r2, r3
8001cd6: 68fa ldr r2, [r7, #12]
8001cd8: 429a cmp r2, r3
8001cda: d8f7 bhi.n 8001ccc <HAL_Delay+0x28>
{
}
}
8001cdc: bf00 nop
8001cde: bf00 nop
8001ce0: 3710 adds r7, #16
8001ce2: 46bd mov sp, r7
8001ce4: bd80 pop {r7, pc}
8001ce6: bf00 nop
8001ce8: 20000008 .word 0x20000008
08001cec <HAL_CAN_Init>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
{
8001cec: b580 push {r7, lr}
8001cee: b084 sub sp, #16
8001cf0: af00 add r7, sp, #0
8001cf2: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Check CAN handle */
if (hcan == NULL)
8001cf4: 687b ldr r3, [r7, #4]
8001cf6: 2b00 cmp r3, #0
8001cf8: d101 bne.n 8001cfe <HAL_CAN_Init+0x12>
{
return HAL_ERROR;
8001cfa: 2301 movs r3, #1
8001cfc: e0ed b.n 8001eda <HAL_CAN_Init+0x1ee>
/* Init the low level hardware: CLOCK, NVIC */
hcan->MspInitCallback(hcan);
}
#else
if (hcan->State == HAL_CAN_STATE_RESET)
8001cfe: 687b ldr r3, [r7, #4]
8001d00: f893 3020 ldrb.w r3, [r3, #32]
8001d04: b2db uxtb r3, r3
8001d06: 2b00 cmp r3, #0
8001d08: d102 bne.n 8001d10 <HAL_CAN_Init+0x24>
{
/* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
8001d0a: 6878 ldr r0, [r7, #4]
8001d0c: f7ff fe66 bl 80019dc <HAL_CAN_MspInit>
}
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
8001d10: 687b ldr r3, [r7, #4]
8001d12: 681b ldr r3, [r3, #0]
8001d14: 681a ldr r2, [r3, #0]
8001d16: 687b ldr r3, [r7, #4]
8001d18: 681b ldr r3, [r3, #0]
8001d1a: f042 0201 orr.w r2, r2, #1
8001d1e: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8001d20: f7ff ffb4 bl 8001c8c <HAL_GetTick>
8001d24: 60f8 str r0, [r7, #12]
/* Wait initialisation acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
8001d26: e012 b.n 8001d4e <HAL_CAN_Init+0x62>
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
8001d28: f7ff ffb0 bl 8001c8c <HAL_GetTick>
8001d2c: 4602 mov r2, r0
8001d2e: 68fb ldr r3, [r7, #12]
8001d30: 1ad3 subs r3, r2, r3
8001d32: 2b0a cmp r3, #10
8001d34: d90b bls.n 8001d4e <HAL_CAN_Init+0x62>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
8001d36: 687b ldr r3, [r7, #4]
8001d38: 6a5b ldr r3, [r3, #36] ; 0x24
8001d3a: f443 3200 orr.w r2, r3, #131072 ; 0x20000
8001d3e: 687b ldr r3, [r7, #4]
8001d40: 625a str r2, [r3, #36] ; 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
8001d42: 687b ldr r3, [r7, #4]
8001d44: 2205 movs r2, #5
8001d46: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
8001d4a: 2301 movs r3, #1
8001d4c: e0c5 b.n 8001eda <HAL_CAN_Init+0x1ee>
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
8001d4e: 687b ldr r3, [r7, #4]
8001d50: 681b ldr r3, [r3, #0]
8001d52: 685b ldr r3, [r3, #4]
8001d54: f003 0301 and.w r3, r3, #1
8001d58: 2b00 cmp r3, #0
8001d5a: d0e5 beq.n 8001d28 <HAL_CAN_Init+0x3c>
}
}
/* Exit from sleep mode */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
8001d5c: 687b ldr r3, [r7, #4]
8001d5e: 681b ldr r3, [r3, #0]
8001d60: 681a ldr r2, [r3, #0]
8001d62: 687b ldr r3, [r7, #4]
8001d64: 681b ldr r3, [r3, #0]
8001d66: f022 0202 bic.w r2, r2, #2
8001d6a: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8001d6c: f7ff ff8e bl 8001c8c <HAL_GetTick>
8001d70: 60f8 str r0, [r7, #12]
/* Check Sleep mode leave acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
8001d72: e012 b.n 8001d9a <HAL_CAN_Init+0xae>
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
8001d74: f7ff ff8a bl 8001c8c <HAL_GetTick>
8001d78: 4602 mov r2, r0
8001d7a: 68fb ldr r3, [r7, #12]
8001d7c: 1ad3 subs r3, r2, r3
8001d7e: 2b0a cmp r3, #10
8001d80: d90b bls.n 8001d9a <HAL_CAN_Init+0xae>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
8001d82: 687b ldr r3, [r7, #4]
8001d84: 6a5b ldr r3, [r3, #36] ; 0x24
8001d86: f443 3200 orr.w r2, r3, #131072 ; 0x20000
8001d8a: 687b ldr r3, [r7, #4]
8001d8c: 625a str r2, [r3, #36] ; 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
8001d8e: 687b ldr r3, [r7, #4]
8001d90: 2205 movs r2, #5
8001d92: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
8001d96: 2301 movs r3, #1
8001d98: e09f b.n 8001eda <HAL_CAN_Init+0x1ee>
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
8001d9a: 687b ldr r3, [r7, #4]
8001d9c: 681b ldr r3, [r3, #0]
8001d9e: 685b ldr r3, [r3, #4]
8001da0: f003 0302 and.w r3, r3, #2
8001da4: 2b00 cmp r3, #0
8001da6: d1e5 bne.n 8001d74 <HAL_CAN_Init+0x88>
}
}
/* Set the time triggered communication mode */
if (hcan->Init.TimeTriggeredMode == ENABLE)
8001da8: 687b ldr r3, [r7, #4]
8001daa: 7e1b ldrb r3, [r3, #24]
8001dac: 2b01 cmp r3, #1
8001dae: d108 bne.n 8001dc2 <HAL_CAN_Init+0xd6>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
8001db0: 687b ldr r3, [r7, #4]
8001db2: 681b ldr r3, [r3, #0]
8001db4: 681a ldr r2, [r3, #0]
8001db6: 687b ldr r3, [r7, #4]
8001db8: 681b ldr r3, [r3, #0]
8001dba: f042 0280 orr.w r2, r2, #128 ; 0x80
8001dbe: 601a str r2, [r3, #0]
8001dc0: e007 b.n 8001dd2 <HAL_CAN_Init+0xe6>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
8001dc2: 687b ldr r3, [r7, #4]
8001dc4: 681b ldr r3, [r3, #0]
8001dc6: 681a ldr r2, [r3, #0]
8001dc8: 687b ldr r3, [r7, #4]
8001dca: 681b ldr r3, [r3, #0]
8001dcc: f022 0280 bic.w r2, r2, #128 ; 0x80
8001dd0: 601a str r2, [r3, #0]
}
/* Set the automatic bus-off management */
if (hcan->Init.AutoBusOff == ENABLE)
8001dd2: 687b ldr r3, [r7, #4]
8001dd4: 7e5b ldrb r3, [r3, #25]
8001dd6: 2b01 cmp r3, #1
8001dd8: d108 bne.n 8001dec <HAL_CAN_Init+0x100>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
8001dda: 687b ldr r3, [r7, #4]
8001ddc: 681b ldr r3, [r3, #0]
8001dde: 681a ldr r2, [r3, #0]
8001de0: 687b ldr r3, [r7, #4]
8001de2: 681b ldr r3, [r3, #0]
8001de4: f042 0240 orr.w r2, r2, #64 ; 0x40
8001de8: 601a str r2, [r3, #0]
8001dea: e007 b.n 8001dfc <HAL_CAN_Init+0x110>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
8001dec: 687b ldr r3, [r7, #4]
8001dee: 681b ldr r3, [r3, #0]
8001df0: 681a ldr r2, [r3, #0]
8001df2: 687b ldr r3, [r7, #4]
8001df4: 681b ldr r3, [r3, #0]
8001df6: f022 0240 bic.w r2, r2, #64 ; 0x40
8001dfa: 601a str r2, [r3, #0]
}
/* Set the automatic wake-up mode */
if (hcan->Init.AutoWakeUp == ENABLE)
8001dfc: 687b ldr r3, [r7, #4]
8001dfe: 7e9b ldrb r3, [r3, #26]
8001e00: 2b01 cmp r3, #1
8001e02: d108 bne.n 8001e16 <HAL_CAN_Init+0x12a>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
8001e04: 687b ldr r3, [r7, #4]
8001e06: 681b ldr r3, [r3, #0]
8001e08: 681a ldr r2, [r3, #0]
8001e0a: 687b ldr r3, [r7, #4]
8001e0c: 681b ldr r3, [r3, #0]
8001e0e: f042 0220 orr.w r2, r2, #32
8001e12: 601a str r2, [r3, #0]
8001e14: e007 b.n 8001e26 <HAL_CAN_Init+0x13a>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
8001e16: 687b ldr r3, [r7, #4]
8001e18: 681b ldr r3, [r3, #0]
8001e1a: 681a ldr r2, [r3, #0]
8001e1c: 687b ldr r3, [r7, #4]
8001e1e: 681b ldr r3, [r3, #0]
8001e20: f022 0220 bic.w r2, r2, #32
8001e24: 601a str r2, [r3, #0]
}
/* Set the automatic retransmission */
if (hcan->Init.AutoRetransmission == ENABLE)
8001e26: 687b ldr r3, [r7, #4]
8001e28: 7edb ldrb r3, [r3, #27]
8001e2a: 2b01 cmp r3, #1
8001e2c: d108 bne.n 8001e40 <HAL_CAN_Init+0x154>
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
8001e2e: 687b ldr r3, [r7, #4]
8001e30: 681b ldr r3, [r3, #0]
8001e32: 681a ldr r2, [r3, #0]
8001e34: 687b ldr r3, [r7, #4]
8001e36: 681b ldr r3, [r3, #0]
8001e38: f022 0210 bic.w r2, r2, #16
8001e3c: 601a str r2, [r3, #0]
8001e3e: e007 b.n 8001e50 <HAL_CAN_Init+0x164>
}
else
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
8001e40: 687b ldr r3, [r7, #4]
8001e42: 681b ldr r3, [r3, #0]
8001e44: 681a ldr r2, [r3, #0]
8001e46: 687b ldr r3, [r7, #4]
8001e48: 681b ldr r3, [r3, #0]
8001e4a: f042 0210 orr.w r2, r2, #16
8001e4e: 601a str r2, [r3, #0]
}
/* Set the receive FIFO locked mode */
if (hcan->Init.ReceiveFifoLocked == ENABLE)
8001e50: 687b ldr r3, [r7, #4]
8001e52: 7f1b ldrb r3, [r3, #28]
8001e54: 2b01 cmp r3, #1
8001e56: d108 bne.n 8001e6a <HAL_CAN_Init+0x17e>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
8001e58: 687b ldr r3, [r7, #4]
8001e5a: 681b ldr r3, [r3, #0]
8001e5c: 681a ldr r2, [r3, #0]
8001e5e: 687b ldr r3, [r7, #4]
8001e60: 681b ldr r3, [r3, #0]
8001e62: f042 0208 orr.w r2, r2, #8
8001e66: 601a str r2, [r3, #0]
8001e68: e007 b.n 8001e7a <HAL_CAN_Init+0x18e>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
8001e6a: 687b ldr r3, [r7, #4]
8001e6c: 681b ldr r3, [r3, #0]
8001e6e: 681a ldr r2, [r3, #0]
8001e70: 687b ldr r3, [r7, #4]
8001e72: 681b ldr r3, [r3, #0]
8001e74: f022 0208 bic.w r2, r2, #8
8001e78: 601a str r2, [r3, #0]
}
/* Set the transmit FIFO priority */
if (hcan->Init.TransmitFifoPriority == ENABLE)
8001e7a: 687b ldr r3, [r7, #4]
8001e7c: 7f5b ldrb r3, [r3, #29]
8001e7e: 2b01 cmp r3, #1
8001e80: d108 bne.n 8001e94 <HAL_CAN_Init+0x1a8>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
8001e82: 687b ldr r3, [r7, #4]
8001e84: 681b ldr r3, [r3, #0]
8001e86: 681a ldr r2, [r3, #0]
8001e88: 687b ldr r3, [r7, #4]
8001e8a: 681b ldr r3, [r3, #0]
8001e8c: f042 0204 orr.w r2, r2, #4
8001e90: 601a str r2, [r3, #0]
8001e92: e007 b.n 8001ea4 <HAL_CAN_Init+0x1b8>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
8001e94: 687b ldr r3, [r7, #4]
8001e96: 681b ldr r3, [r3, #0]
8001e98: 681a ldr r2, [r3, #0]
8001e9a: 687b ldr r3, [r7, #4]
8001e9c: 681b ldr r3, [r3, #0]
8001e9e: f022 0204 bic.w r2, r2, #4
8001ea2: 601a str r2, [r3, #0]
}
/* Set the bit timing register */
WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
8001ea4: 687b ldr r3, [r7, #4]
8001ea6: 689a ldr r2, [r3, #8]
8001ea8: 687b ldr r3, [r7, #4]
8001eaa: 68db ldr r3, [r3, #12]
8001eac: 431a orrs r2, r3
8001eae: 687b ldr r3, [r7, #4]
8001eb0: 691b ldr r3, [r3, #16]
8001eb2: 431a orrs r2, r3
8001eb4: 687b ldr r3, [r7, #4]
8001eb6: 695b ldr r3, [r3, #20]
8001eb8: ea42 0103 orr.w r1, r2, r3
8001ebc: 687b ldr r3, [r7, #4]
8001ebe: 685b ldr r3, [r3, #4]
8001ec0: 1e5a subs r2, r3, #1
8001ec2: 687b ldr r3, [r7, #4]
8001ec4: 681b ldr r3, [r3, #0]
8001ec6: 430a orrs r2, r1
8001ec8: 61da str r2, [r3, #28]
hcan->Init.TimeSeg1 |
hcan->Init.TimeSeg2 |
(hcan->Init.Prescaler - 1U)));
/* Initialize the error code */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
8001eca: 687b ldr r3, [r7, #4]
8001ecc: 2200 movs r2, #0
8001ece: 625a str r2, [r3, #36] ; 0x24
/* Initialize the CAN state */
hcan->State = HAL_CAN_STATE_READY;
8001ed0: 687b ldr r3, [r7, #4]
8001ed2: 2201 movs r2, #1
8001ed4: f883 2020 strb.w r2, [r3, #32]
/* Return function status */
return HAL_OK;
8001ed8: 2300 movs r3, #0
}
8001eda: 4618 mov r0, r3
8001edc: 3710 adds r7, #16
8001ede: 46bd mov sp, r7
8001ee0: bd80 pop {r7, pc}
08001ee2 <HAL_CAN_AddTxMessage>:
* This parameter can be a value of @arg CAN_Tx_Mailboxes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader,
const uint8_t aData[], uint32_t *pTxMailbox)
{
8001ee2: b480 push {r7}
8001ee4: b089 sub sp, #36 ; 0x24
8001ee6: af00 add r7, sp, #0
8001ee8: 60f8 str r0, [r7, #12]
8001eea: 60b9 str r1, [r7, #8]
8001eec: 607a str r2, [r7, #4]
8001eee: 603b str r3, [r7, #0]
uint32_t transmitmailbox;
HAL_CAN_StateTypeDef state = hcan->State;
8001ef0: 68fb ldr r3, [r7, #12]
8001ef2: f893 3020 ldrb.w r3, [r3, #32]
8001ef6: 77fb strb r3, [r7, #31]
uint32_t tsr = READ_REG(hcan->Instance->TSR);
8001ef8: 68fb ldr r3, [r7, #12]
8001efa: 681b ldr r3, [r3, #0]
8001efc: 689b ldr r3, [r3, #8]
8001efe: 61bb str r3, [r7, #24]
{
assert_param(IS_CAN_EXTID(pHeader->ExtId));
}
assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
if ((state == HAL_CAN_STATE_READY) ||
8001f00: 7ffb ldrb r3, [r7, #31]
8001f02: 2b01 cmp r3, #1
8001f04: d003 beq.n 8001f0e <HAL_CAN_AddTxMessage+0x2c>
8001f06: 7ffb ldrb r3, [r7, #31]
8001f08: 2b02 cmp r3, #2
8001f0a: f040 80ad bne.w 8002068 <HAL_CAN_AddTxMessage+0x186>
(state == HAL_CAN_STATE_LISTENING))
{
/* Check that all the Tx mailboxes are not full */
if (((tsr & CAN_TSR_TME0) != 0U) ||
8001f0e: 69bb ldr r3, [r7, #24]
8001f10: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
8001f14: 2b00 cmp r3, #0
8001f16: d10a bne.n 8001f2e <HAL_CAN_AddTxMessage+0x4c>
((tsr & CAN_TSR_TME1) != 0U) ||
8001f18: 69bb ldr r3, [r7, #24]
8001f1a: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
if (((tsr & CAN_TSR_TME0) != 0U) ||
8001f1e: 2b00 cmp r3, #0
8001f20: d105 bne.n 8001f2e <HAL_CAN_AddTxMessage+0x4c>
((tsr & CAN_TSR_TME2) != 0U))
8001f22: 69bb ldr r3, [r7, #24]
8001f24: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
((tsr & CAN_TSR_TME1) != 0U) ||
8001f28: 2b00 cmp r3, #0
8001f2a: f000 8095 beq.w 8002058 <HAL_CAN_AddTxMessage+0x176>
{
/* Select an empty transmit mailbox */
transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
8001f2e: 69bb ldr r3, [r7, #24]
8001f30: 0e1b lsrs r3, r3, #24
8001f32: f003 0303 and.w r3, r3, #3
8001f36: 617b str r3, [r7, #20]
/* Store the Tx mailbox */
*pTxMailbox = (uint32_t)1 << transmitmailbox;
8001f38: 2201 movs r2, #1
8001f3a: 697b ldr r3, [r7, #20]
8001f3c: 409a lsls r2, r3
8001f3e: 683b ldr r3, [r7, #0]
8001f40: 601a str r2, [r3, #0]
/* Set up the Id */
if (pHeader->IDE == CAN_ID_STD)
8001f42: 68bb ldr r3, [r7, #8]
8001f44: 689b ldr r3, [r3, #8]
8001f46: 2b00 cmp r3, #0
8001f48: d10d bne.n 8001f66 <HAL_CAN_AddTxMessage+0x84>
{
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
8001f4a: 68bb ldr r3, [r7, #8]
8001f4c: 681b ldr r3, [r3, #0]
8001f4e: 055a lsls r2, r3, #21
pHeader->RTR);
8001f50: 68bb ldr r3, [r7, #8]
8001f52: 68db ldr r3, [r3, #12]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
8001f54: 68f9 ldr r1, [r7, #12]
8001f56: 6809 ldr r1, [r1, #0]
8001f58: 431a orrs r2, r3
8001f5a: 697b ldr r3, [r7, #20]
8001f5c: 3318 adds r3, #24
8001f5e: 011b lsls r3, r3, #4
8001f60: 440b add r3, r1
8001f62: 601a str r2, [r3, #0]
8001f64: e00f b.n 8001f86 <HAL_CAN_AddTxMessage+0xa4>
}
else
{
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8001f66: 68bb ldr r3, [r7, #8]
8001f68: 685b ldr r3, [r3, #4]
8001f6a: 00da lsls r2, r3, #3
pHeader->IDE |
8001f6c: 68bb ldr r3, [r7, #8]
8001f6e: 689b ldr r3, [r3, #8]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8001f70: 431a orrs r2, r3
pHeader->RTR);
8001f72: 68bb ldr r3, [r7, #8]
8001f74: 68db ldr r3, [r3, #12]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8001f76: 68f9 ldr r1, [r7, #12]
8001f78: 6809 ldr r1, [r1, #0]
pHeader->IDE |
8001f7a: 431a orrs r2, r3
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8001f7c: 697b ldr r3, [r7, #20]
8001f7e: 3318 adds r3, #24
8001f80: 011b lsls r3, r3, #4
8001f82: 440b add r3, r1
8001f84: 601a str r2, [r3, #0]
}
/* Set up the DLC */
hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
8001f86: 68fb ldr r3, [r7, #12]
8001f88: 6819 ldr r1, [r3, #0]
8001f8a: 68bb ldr r3, [r7, #8]
8001f8c: 691a ldr r2, [r3, #16]
8001f8e: 697b ldr r3, [r7, #20]
8001f90: 3318 adds r3, #24
8001f92: 011b lsls r3, r3, #4
8001f94: 440b add r3, r1
8001f96: 3304 adds r3, #4
8001f98: 601a str r2, [r3, #0]
/* Set up the Transmit Global Time mode */
if (pHeader->TransmitGlobalTime == ENABLE)
8001f9a: 68bb ldr r3, [r7, #8]
8001f9c: 7d1b ldrb r3, [r3, #20]
8001f9e: 2b01 cmp r3, #1
8001fa0: d111 bne.n 8001fc6 <HAL_CAN_AddTxMessage+0xe4>
{
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
8001fa2: 68fb ldr r3, [r7, #12]
8001fa4: 681a ldr r2, [r3, #0]
8001fa6: 697b ldr r3, [r7, #20]
8001fa8: 3318 adds r3, #24
8001faa: 011b lsls r3, r3, #4
8001fac: 4413 add r3, r2
8001fae: 3304 adds r3, #4
8001fb0: 681b ldr r3, [r3, #0]
8001fb2: 68fa ldr r2, [r7, #12]
8001fb4: 6811 ldr r1, [r2, #0]
8001fb6: f443 7280 orr.w r2, r3, #256 ; 0x100
8001fba: 697b ldr r3, [r7, #20]
8001fbc: 3318 adds r3, #24
8001fbe: 011b lsls r3, r3, #4
8001fc0: 440b add r3, r1
8001fc2: 3304 adds r3, #4
8001fc4: 601a str r2, [r3, #0]
}
/* Set up the data field */
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
8001fc6: 687b ldr r3, [r7, #4]
8001fc8: 3307 adds r3, #7
8001fca: 781b ldrb r3, [r3, #0]
8001fcc: 061a lsls r2, r3, #24
8001fce: 687b ldr r3, [r7, #4]
8001fd0: 3306 adds r3, #6
8001fd2: 781b ldrb r3, [r3, #0]
8001fd4: 041b lsls r3, r3, #16
8001fd6: 431a orrs r2, r3
8001fd8: 687b ldr r3, [r7, #4]
8001fda: 3305 adds r3, #5
8001fdc: 781b ldrb r3, [r3, #0]
8001fde: 021b lsls r3, r3, #8
8001fe0: 4313 orrs r3, r2
8001fe2: 687a ldr r2, [r7, #4]
8001fe4: 3204 adds r2, #4
8001fe6: 7812 ldrb r2, [r2, #0]
8001fe8: 4610 mov r0, r2
8001fea: 68fa ldr r2, [r7, #12]
8001fec: 6811 ldr r1, [r2, #0]
8001fee: ea43 0200 orr.w r2, r3, r0
8001ff2: 697b ldr r3, [r7, #20]
8001ff4: 011b lsls r3, r3, #4
8001ff6: 440b add r3, r1
8001ff8: f503 73c6 add.w r3, r3, #396 ; 0x18c
8001ffc: 601a str r2, [r3, #0]
((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
8001ffe: 687b ldr r3, [r7, #4]
8002000: 3303 adds r3, #3
8002002: 781b ldrb r3, [r3, #0]
8002004: 061a lsls r2, r3, #24
8002006: 687b ldr r3, [r7, #4]
8002008: 3302 adds r3, #2
800200a: 781b ldrb r3, [r3, #0]
800200c: 041b lsls r3, r3, #16
800200e: 431a orrs r2, r3
8002010: 687b ldr r3, [r7, #4]
8002012: 3301 adds r3, #1
8002014: 781b ldrb r3, [r3, #0]
8002016: 021b lsls r3, r3, #8
8002018: 4313 orrs r3, r2
800201a: 687a ldr r2, [r7, #4]
800201c: 7812 ldrb r2, [r2, #0]
800201e: 4610 mov r0, r2
8002020: 68fa ldr r2, [r7, #12]
8002022: 6811 ldr r1, [r2, #0]
8002024: ea43 0200 orr.w r2, r3, r0
8002028: 697b ldr r3, [r7, #20]
800202a: 011b lsls r3, r3, #4
800202c: 440b add r3, r1
800202e: f503 73c4 add.w r3, r3, #392 ; 0x188
8002032: 601a str r2, [r3, #0]
((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));
/* Request transmission */
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
8002034: 68fb ldr r3, [r7, #12]
8002036: 681a ldr r2, [r3, #0]
8002038: 697b ldr r3, [r7, #20]
800203a: 3318 adds r3, #24
800203c: 011b lsls r3, r3, #4
800203e: 4413 add r3, r2
8002040: 681b ldr r3, [r3, #0]
8002042: 68fa ldr r2, [r7, #12]
8002044: 6811 ldr r1, [r2, #0]
8002046: f043 0201 orr.w r2, r3, #1
800204a: 697b ldr r3, [r7, #20]
800204c: 3318 adds r3, #24
800204e: 011b lsls r3, r3, #4
8002050: 440b add r3, r1
8002052: 601a str r2, [r3, #0]
/* Return function status */
return HAL_OK;
8002054: 2300 movs r3, #0
8002056: e00e b.n 8002076 <HAL_CAN_AddTxMessage+0x194>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
8002058: 68fb ldr r3, [r7, #12]
800205a: 6a5b ldr r3, [r3, #36] ; 0x24
800205c: f443 1200 orr.w r2, r3, #2097152 ; 0x200000
8002060: 68fb ldr r3, [r7, #12]
8002062: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
8002064: 2301 movs r3, #1
8002066: e006 b.n 8002076 <HAL_CAN_AddTxMessage+0x194>
}
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
8002068: 68fb ldr r3, [r7, #12]
800206a: 6a5b ldr r3, [r3, #36] ; 0x24
800206c: f443 2280 orr.w r2, r3, #262144 ; 0x40000
8002070: 68fb ldr r3, [r7, #12]
8002072: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
8002074: 2301 movs r3, #1
}
}
8002076: 4618 mov r0, r3
8002078: 3724 adds r7, #36 ; 0x24
800207a: 46bd mov sp, r7
800207c: f85d 7b04 ldr.w r7, [sp], #4
8002080: 4770 bx lr
08002082 <HAL_CAN_IRQHandler>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
{
8002082: b580 push {r7, lr}
8002084: b08a sub sp, #40 ; 0x28
8002086: af00 add r7, sp, #0
8002088: 6078 str r0, [r7, #4]
uint32_t errorcode = HAL_CAN_ERROR_NONE;
800208a: 2300 movs r3, #0
800208c: 627b str r3, [r7, #36] ; 0x24
uint32_t interrupts = READ_REG(hcan->Instance->IER);
800208e: 687b ldr r3, [r7, #4]
8002090: 681b ldr r3, [r3, #0]
8002092: 695b ldr r3, [r3, #20]
8002094: 623b str r3, [r7, #32]
uint32_t msrflags = READ_REG(hcan->Instance->MSR);
8002096: 687b ldr r3, [r7, #4]
8002098: 681b ldr r3, [r3, #0]
800209a: 685b ldr r3, [r3, #4]
800209c: 61fb str r3, [r7, #28]
uint32_t tsrflags = READ_REG(hcan->Instance->TSR);
800209e: 687b ldr r3, [r7, #4]
80020a0: 681b ldr r3, [r3, #0]
80020a2: 689b ldr r3, [r3, #8]
80020a4: 61bb str r3, [r7, #24]
uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);
80020a6: 687b ldr r3, [r7, #4]
80020a8: 681b ldr r3, [r3, #0]
80020aa: 68db ldr r3, [r3, #12]
80020ac: 617b str r3, [r7, #20]
uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);
80020ae: 687b ldr r3, [r7, #4]
80020b0: 681b ldr r3, [r3, #0]
80020b2: 691b ldr r3, [r3, #16]
80020b4: 613b str r3, [r7, #16]
uint32_t esrflags = READ_REG(hcan->Instance->ESR);
80020b6: 687b ldr r3, [r7, #4]
80020b8: 681b ldr r3, [r3, #0]
80020ba: 699b ldr r3, [r3, #24]
80020bc: 60fb str r3, [r7, #12]
/* Transmit Mailbox empty interrupt management *****************************/
if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U)
80020be: 6a3b ldr r3, [r7, #32]
80020c0: f003 0301 and.w r3, r3, #1
80020c4: 2b00 cmp r3, #0
80020c6: d07c beq.n 80021c2 <HAL_CAN_IRQHandler+0x140>
{
/* Transmit Mailbox 0 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP0) != 0U)
80020c8: 69bb ldr r3, [r7, #24]
80020ca: f003 0301 and.w r3, r3, #1
80020ce: 2b00 cmp r3, #0
80020d0: d023 beq.n 800211a <HAL_CAN_IRQHandler+0x98>
{
/* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
80020d2: 687b ldr r3, [r7, #4]
80020d4: 681b ldr r3, [r3, #0]
80020d6: 2201 movs r2, #1
80020d8: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK0) != 0U)
80020da: 69bb ldr r3, [r7, #24]
80020dc: f003 0302 and.w r3, r3, #2
80020e0: 2b00 cmp r3, #0
80020e2: d003 beq.n 80020ec <HAL_CAN_IRQHandler+0x6a>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox0CompleteCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox0CompleteCallback(hcan);
80020e4: 6878 ldr r0, [r7, #4]
80020e6: f000 f983 bl 80023f0 <HAL_CAN_TxMailbox0CompleteCallback>
80020ea: e016 b.n 800211a <HAL_CAN_IRQHandler+0x98>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST0) != 0U)
80020ec: 69bb ldr r3, [r7, #24]
80020ee: f003 0304 and.w r3, r3, #4
80020f2: 2b00 cmp r3, #0
80020f4: d004 beq.n 8002100 <HAL_CAN_IRQHandler+0x7e>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST0;
80020f6: 6a7b ldr r3, [r7, #36] ; 0x24
80020f8: f443 6300 orr.w r3, r3, #2048 ; 0x800
80020fc: 627b str r3, [r7, #36] ; 0x24
80020fe: e00c b.n 800211a <HAL_CAN_IRQHandler+0x98>
}
else if ((tsrflags & CAN_TSR_TERR0) != 0U)
8002100: 69bb ldr r3, [r7, #24]
8002102: f003 0308 and.w r3, r3, #8
8002106: 2b00 cmp r3, #0
8002108: d004 beq.n 8002114 <HAL_CAN_IRQHandler+0x92>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR0;
800210a: 6a7b ldr r3, [r7, #36] ; 0x24
800210c: f443 5380 orr.w r3, r3, #4096 ; 0x1000
8002110: 627b str r3, [r7, #36] ; 0x24
8002112: e002 b.n 800211a <HAL_CAN_IRQHandler+0x98>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox0AbortCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox0AbortCallback(hcan);
8002114: 6878 ldr r0, [r7, #4]
8002116: f000 f989 bl 800242c <HAL_CAN_TxMailbox0AbortCallback>
}
}
}
/* Transmit Mailbox 1 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP1) != 0U)
800211a: 69bb ldr r3, [r7, #24]
800211c: f403 7380 and.w r3, r3, #256 ; 0x100
8002120: 2b00 cmp r3, #0
8002122: d024 beq.n 800216e <HAL_CAN_IRQHandler+0xec>
{
/* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
8002124: 687b ldr r3, [r7, #4]
8002126: 681b ldr r3, [r3, #0]
8002128: f44f 7280 mov.w r2, #256 ; 0x100
800212c: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK1) != 0U)
800212e: 69bb ldr r3, [r7, #24]
8002130: f403 7300 and.w r3, r3, #512 ; 0x200
8002134: 2b00 cmp r3, #0
8002136: d003 beq.n 8002140 <HAL_CAN_IRQHandler+0xbe>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox1CompleteCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox1CompleteCallback(hcan);
8002138: 6878 ldr r0, [r7, #4]
800213a: f000 f963 bl 8002404 <HAL_CAN_TxMailbox1CompleteCallback>
800213e: e016 b.n 800216e <HAL_CAN_IRQHandler+0xec>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST1) != 0U)
8002140: 69bb ldr r3, [r7, #24]
8002142: f403 6380 and.w r3, r3, #1024 ; 0x400
8002146: 2b00 cmp r3, #0
8002148: d004 beq.n 8002154 <HAL_CAN_IRQHandler+0xd2>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST1;
800214a: 6a7b ldr r3, [r7, #36] ; 0x24
800214c: f443 5300 orr.w r3, r3, #8192 ; 0x2000
8002150: 627b str r3, [r7, #36] ; 0x24
8002152: e00c b.n 800216e <HAL_CAN_IRQHandler+0xec>
}
else if ((tsrflags & CAN_TSR_TERR1) != 0U)
8002154: 69bb ldr r3, [r7, #24]
8002156: f403 6300 and.w r3, r3, #2048 ; 0x800
800215a: 2b00 cmp r3, #0
800215c: d004 beq.n 8002168 <HAL_CAN_IRQHandler+0xe6>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR1;
800215e: 6a7b ldr r3, [r7, #36] ; 0x24
8002160: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8002164: 627b str r3, [r7, #36] ; 0x24
8002166: e002 b.n 800216e <HAL_CAN_IRQHandler+0xec>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox1AbortCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox1AbortCallback(hcan);
8002168: 6878 ldr r0, [r7, #4]
800216a: f000 f969 bl 8002440 <HAL_CAN_TxMailbox1AbortCallback>
}
}
}
/* Transmit Mailbox 2 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP2) != 0U)
800216e: 69bb ldr r3, [r7, #24]
8002170: f403 3380 and.w r3, r3, #65536 ; 0x10000
8002174: 2b00 cmp r3, #0
8002176: d024 beq.n 80021c2 <HAL_CAN_IRQHandler+0x140>
{
/* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
8002178: 687b ldr r3, [r7, #4]
800217a: 681b ldr r3, [r3, #0]
800217c: f44f 3280 mov.w r2, #65536 ; 0x10000
8002180: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK2) != 0U)
8002182: 69bb ldr r3, [r7, #24]
8002184: f403 3300 and.w r3, r3, #131072 ; 0x20000
8002188: 2b00 cmp r3, #0
800218a: d003 beq.n 8002194 <HAL_CAN_IRQHandler+0x112>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox2CompleteCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox2CompleteCallback(hcan);
800218c: 6878 ldr r0, [r7, #4]
800218e: f000 f943 bl 8002418 <HAL_CAN_TxMailbox2CompleteCallback>
8002192: e016 b.n 80021c2 <HAL_CAN_IRQHandler+0x140>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST2) != 0U)
8002194: 69bb ldr r3, [r7, #24]
8002196: f403 2380 and.w r3, r3, #262144 ; 0x40000
800219a: 2b00 cmp r3, #0
800219c: d004 beq.n 80021a8 <HAL_CAN_IRQHandler+0x126>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST2;
800219e: 6a7b ldr r3, [r7, #36] ; 0x24
80021a0: f443 4300 orr.w r3, r3, #32768 ; 0x8000
80021a4: 627b str r3, [r7, #36] ; 0x24
80021a6: e00c b.n 80021c2 <HAL_CAN_IRQHandler+0x140>
}
else if ((tsrflags & CAN_TSR_TERR2) != 0U)
80021a8: 69bb ldr r3, [r7, #24]
80021aa: f403 2300 and.w r3, r3, #524288 ; 0x80000
80021ae: 2b00 cmp r3, #0
80021b0: d004 beq.n 80021bc <HAL_CAN_IRQHandler+0x13a>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR2;
80021b2: 6a7b ldr r3, [r7, #36] ; 0x24
80021b4: f443 3380 orr.w r3, r3, #65536 ; 0x10000
80021b8: 627b str r3, [r7, #36] ; 0x24
80021ba: e002 b.n 80021c2 <HAL_CAN_IRQHandler+0x140>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox2AbortCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox2AbortCallback(hcan);
80021bc: 6878 ldr r0, [r7, #4]
80021be: f000 f949 bl 8002454 <HAL_CAN_TxMailbox2AbortCallback>
}
}
}
/* Receive FIFO 0 overrun interrupt management *****************************/
if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U)
80021c2: 6a3b ldr r3, [r7, #32]
80021c4: f003 0308 and.w r3, r3, #8
80021c8: 2b00 cmp r3, #0
80021ca: d00c beq.n 80021e6 <HAL_CAN_IRQHandler+0x164>
{
if ((rf0rflags & CAN_RF0R_FOVR0) != 0U)
80021cc: 697b ldr r3, [r7, #20]
80021ce: f003 0310 and.w r3, r3, #16
80021d2: 2b00 cmp r3, #0
80021d4: d007 beq.n 80021e6 <HAL_CAN_IRQHandler+0x164>
{
/* Set CAN error code to Rx Fifo 0 overrun error */
errorcode |= HAL_CAN_ERROR_RX_FOV0;
80021d6: 6a7b ldr r3, [r7, #36] ; 0x24
80021d8: f443 7300 orr.w r3, r3, #512 ; 0x200
80021dc: 627b str r3, [r7, #36] ; 0x24
/* Clear FIFO0 Overrun Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
80021de: 687b ldr r3, [r7, #4]
80021e0: 681b ldr r3, [r3, #0]
80021e2: 2210 movs r2, #16
80021e4: 60da str r2, [r3, #12]
}
}
/* Receive FIFO 0 full interrupt management ********************************/
if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U)
80021e6: 6a3b ldr r3, [r7, #32]
80021e8: f003 0304 and.w r3, r3, #4
80021ec: 2b00 cmp r3, #0
80021ee: d00b beq.n 8002208 <HAL_CAN_IRQHandler+0x186>
{
if ((rf0rflags & CAN_RF0R_FULL0) != 0U)
80021f0: 697b ldr r3, [r7, #20]
80021f2: f003 0308 and.w r3, r3, #8
80021f6: 2b00 cmp r3, #0
80021f8: d006 beq.n 8002208 <HAL_CAN_IRQHandler+0x186>
{
/* Clear FIFO 0 full Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
80021fa: 687b ldr r3, [r7, #4]
80021fc: 681b ldr r3, [r3, #0]
80021fe: 2208 movs r2, #8
8002200: 60da str r2, [r3, #12]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo0FullCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo0FullCallback(hcan);
8002202: 6878 ldr r0, [r7, #4]
8002204: f000 f93a bl 800247c <HAL_CAN_RxFifo0FullCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 0 message pending interrupt management *********************/
if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U)
8002208: 6a3b ldr r3, [r7, #32]
800220a: f003 0302 and.w r3, r3, #2
800220e: 2b00 cmp r3, #0
8002210: d009 beq.n 8002226 <HAL_CAN_IRQHandler+0x1a4>
{
/* Check if message is still pending */
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
8002212: 687b ldr r3, [r7, #4]
8002214: 681b ldr r3, [r3, #0]
8002216: 68db ldr r3, [r3, #12]
8002218: f003 0303 and.w r3, r3, #3
800221c: 2b00 cmp r3, #0
800221e: d002 beq.n 8002226 <HAL_CAN_IRQHandler+0x1a4>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo0MsgPendingCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo0MsgPendingCallback(hcan);
8002220: 6878 ldr r0, [r7, #4]
8002222: f000 f921 bl 8002468 <HAL_CAN_RxFifo0MsgPendingCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 1 overrun interrupt management *****************************/
if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U)
8002226: 6a3b ldr r3, [r7, #32]
8002228: f003 0340 and.w r3, r3, #64 ; 0x40
800222c: 2b00 cmp r3, #0
800222e: d00c beq.n 800224a <HAL_CAN_IRQHandler+0x1c8>
{
if ((rf1rflags & CAN_RF1R_FOVR1) != 0U)
8002230: 693b ldr r3, [r7, #16]
8002232: f003 0310 and.w r3, r3, #16
8002236: 2b00 cmp r3, #0
8002238: d007 beq.n 800224a <HAL_CAN_IRQHandler+0x1c8>
{
/* Set CAN error code to Rx Fifo 1 overrun error */
errorcode |= HAL_CAN_ERROR_RX_FOV1;
800223a: 6a7b ldr r3, [r7, #36] ; 0x24
800223c: f443 6380 orr.w r3, r3, #1024 ; 0x400
8002240: 627b str r3, [r7, #36] ; 0x24
/* Clear FIFO1 Overrun Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
8002242: 687b ldr r3, [r7, #4]
8002244: 681b ldr r3, [r3, #0]
8002246: 2210 movs r2, #16
8002248: 611a str r2, [r3, #16]
}
}
/* Receive FIFO 1 full interrupt management ********************************/
if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U)
800224a: 6a3b ldr r3, [r7, #32]
800224c: f003 0320 and.w r3, r3, #32
8002250: 2b00 cmp r3, #0
8002252: d00b beq.n 800226c <HAL_CAN_IRQHandler+0x1ea>
{
if ((rf1rflags & CAN_RF1R_FULL1) != 0U)
8002254: 693b ldr r3, [r7, #16]
8002256: f003 0308 and.w r3, r3, #8
800225a: 2b00 cmp r3, #0
800225c: d006 beq.n 800226c <HAL_CAN_IRQHandler+0x1ea>
{
/* Clear FIFO 1 full Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
800225e: 687b ldr r3, [r7, #4]
8002260: 681b ldr r3, [r3, #0]
8002262: 2208 movs r2, #8
8002264: 611a str r2, [r3, #16]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo1FullCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo1FullCallback(hcan);
8002266: 6878 ldr r0, [r7, #4]
8002268: f000 f91c bl 80024a4 <HAL_CAN_RxFifo1FullCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 1 message pending interrupt management *********************/
if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U)
800226c: 6a3b ldr r3, [r7, #32]
800226e: f003 0310 and.w r3, r3, #16
8002272: 2b00 cmp r3, #0
8002274: d009 beq.n 800228a <HAL_CAN_IRQHandler+0x208>
{
/* Check if message is still pending */
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
8002276: 687b ldr r3, [r7, #4]
8002278: 681b ldr r3, [r3, #0]
800227a: 691b ldr r3, [r3, #16]
800227c: f003 0303 and.w r3, r3, #3
8002280: 2b00 cmp r3, #0
8002282: d002 beq.n 800228a <HAL_CAN_IRQHandler+0x208>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo1MsgPendingCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo1MsgPendingCallback(hcan);
8002284: 6878 ldr r0, [r7, #4]
8002286: f000 f903 bl 8002490 <HAL_CAN_RxFifo1MsgPendingCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Sleep interrupt management *********************************************/
if ((interrupts & CAN_IT_SLEEP_ACK) != 0U)
800228a: 6a3b ldr r3, [r7, #32]
800228c: f403 3300 and.w r3, r3, #131072 ; 0x20000
8002290: 2b00 cmp r3, #0
8002292: d00b beq.n 80022ac <HAL_CAN_IRQHandler+0x22a>
{
if ((msrflags & CAN_MSR_SLAKI) != 0U)
8002294: 69fb ldr r3, [r7, #28]
8002296: f003 0310 and.w r3, r3, #16
800229a: 2b00 cmp r3, #0
800229c: d006 beq.n 80022ac <HAL_CAN_IRQHandler+0x22a>
{
/* Clear Sleep interrupt Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
800229e: 687b ldr r3, [r7, #4]
80022a0: 681b ldr r3, [r3, #0]
80022a2: 2210 movs r2, #16
80022a4: 605a str r2, [r3, #4]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->SleepCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_SleepCallback(hcan);
80022a6: 6878 ldr r0, [r7, #4]
80022a8: f000 f906 bl 80024b8 <HAL_CAN_SleepCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* WakeUp interrupt management *********************************************/
if ((interrupts & CAN_IT_WAKEUP) != 0U)
80022ac: 6a3b ldr r3, [r7, #32]
80022ae: f403 3380 and.w r3, r3, #65536 ; 0x10000
80022b2: 2b00 cmp r3, #0
80022b4: d00b beq.n 80022ce <HAL_CAN_IRQHandler+0x24c>
{
if ((msrflags & CAN_MSR_WKUI) != 0U)
80022b6: 69fb ldr r3, [r7, #28]
80022b8: f003 0308 and.w r3, r3, #8
80022bc: 2b00 cmp r3, #0
80022be: d006 beq.n 80022ce <HAL_CAN_IRQHandler+0x24c>
{
/* Clear WakeUp Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
80022c0: 687b ldr r3, [r7, #4]
80022c2: 681b ldr r3, [r3, #0]
80022c4: 2208 movs r2, #8
80022c6: 605a str r2, [r3, #4]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->WakeUpFromRxMsgCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_WakeUpFromRxMsgCallback(hcan);
80022c8: 6878 ldr r0, [r7, #4]
80022ca: f000 f8ff bl 80024cc <HAL_CAN_WakeUpFromRxMsgCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Error interrupts management *********************************************/
if ((interrupts & CAN_IT_ERROR) != 0U)
80022ce: 6a3b ldr r3, [r7, #32]
80022d0: f403 4300 and.w r3, r3, #32768 ; 0x8000
80022d4: 2b00 cmp r3, #0
80022d6: d07b beq.n 80023d0 <HAL_CAN_IRQHandler+0x34e>
{
if ((msrflags & CAN_MSR_ERRI) != 0U)
80022d8: 69fb ldr r3, [r7, #28]
80022da: f003 0304 and.w r3, r3, #4
80022de: 2b00 cmp r3, #0
80022e0: d072 beq.n 80023c8 <HAL_CAN_IRQHandler+0x346>
{
/* Check Error Warning Flag */
if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
80022e2: 6a3b ldr r3, [r7, #32]
80022e4: f403 7380 and.w r3, r3, #256 ; 0x100
80022e8: 2b00 cmp r3, #0
80022ea: d008 beq.n 80022fe <HAL_CAN_IRQHandler+0x27c>
((esrflags & CAN_ESR_EWGF) != 0U))
80022ec: 68fb ldr r3, [r7, #12]
80022ee: f003 0301 and.w r3, r3, #1
if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
80022f2: 2b00 cmp r3, #0
80022f4: d003 beq.n 80022fe <HAL_CAN_IRQHandler+0x27c>
{
/* Set CAN error code to Error Warning */
errorcode |= HAL_CAN_ERROR_EWG;
80022f6: 6a7b ldr r3, [r7, #36] ; 0x24
80022f8: f043 0301 orr.w r3, r3, #1
80022fc: 627b str r3, [r7, #36] ; 0x24
/* No need for clear of Error Warning Flag as read-only */
}
/* Check Error Passive Flag */
if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
80022fe: 6a3b ldr r3, [r7, #32]
8002300: f403 7300 and.w r3, r3, #512 ; 0x200
8002304: 2b00 cmp r3, #0
8002306: d008 beq.n 800231a <HAL_CAN_IRQHandler+0x298>
((esrflags & CAN_ESR_EPVF) != 0U))
8002308: 68fb ldr r3, [r7, #12]
800230a: f003 0302 and.w r3, r3, #2
if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
800230e: 2b00 cmp r3, #0
8002310: d003 beq.n 800231a <HAL_CAN_IRQHandler+0x298>
{
/* Set CAN error code to Error Passive */
errorcode |= HAL_CAN_ERROR_EPV;
8002312: 6a7b ldr r3, [r7, #36] ; 0x24
8002314: f043 0302 orr.w r3, r3, #2
8002318: 627b str r3, [r7, #36] ; 0x24
/* No need for clear of Error Passive Flag as read-only */
}
/* Check Bus-off Flag */
if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
800231a: 6a3b ldr r3, [r7, #32]
800231c: f403 6380 and.w r3, r3, #1024 ; 0x400
8002320: 2b00 cmp r3, #0
8002322: d008 beq.n 8002336 <HAL_CAN_IRQHandler+0x2b4>
((esrflags & CAN_ESR_BOFF) != 0U))
8002324: 68fb ldr r3, [r7, #12]
8002326: f003 0304 and.w r3, r3, #4
if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
800232a: 2b00 cmp r3, #0
800232c: d003 beq.n 8002336 <HAL_CAN_IRQHandler+0x2b4>
{
/* Set CAN error code to Bus-Off */
errorcode |= HAL_CAN_ERROR_BOF;
800232e: 6a7b ldr r3, [r7, #36] ; 0x24
8002330: f043 0304 orr.w r3, r3, #4
8002334: 627b str r3, [r7, #36] ; 0x24
/* No need for clear of Error Bus-Off as read-only */
}
/* Check Last Error Code Flag */
if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
8002336: 6a3b ldr r3, [r7, #32]
8002338: f403 6300 and.w r3, r3, #2048 ; 0x800
800233c: 2b00 cmp r3, #0
800233e: d043 beq.n 80023c8 <HAL_CAN_IRQHandler+0x346>
((esrflags & CAN_ESR_LEC) != 0U))
8002340: 68fb ldr r3, [r7, #12]
8002342: f003 0370 and.w r3, r3, #112 ; 0x70
if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
8002346: 2b00 cmp r3, #0
8002348: d03e beq.n 80023c8 <HAL_CAN_IRQHandler+0x346>
{
switch (esrflags & CAN_ESR_LEC)
800234a: 68fb ldr r3, [r7, #12]
800234c: f003 0370 and.w r3, r3, #112 ; 0x70
8002350: 2b60 cmp r3, #96 ; 0x60
8002352: d02b beq.n 80023ac <HAL_CAN_IRQHandler+0x32a>
8002354: 2b60 cmp r3, #96 ; 0x60
8002356: d82e bhi.n 80023b6 <HAL_CAN_IRQHandler+0x334>
8002358: 2b50 cmp r3, #80 ; 0x50
800235a: d022 beq.n 80023a2 <HAL_CAN_IRQHandler+0x320>
800235c: 2b50 cmp r3, #80 ; 0x50
800235e: d82a bhi.n 80023b6 <HAL_CAN_IRQHandler+0x334>
8002360: 2b40 cmp r3, #64 ; 0x40
8002362: d019 beq.n 8002398 <HAL_CAN_IRQHandler+0x316>
8002364: 2b40 cmp r3, #64 ; 0x40
8002366: d826 bhi.n 80023b6 <HAL_CAN_IRQHandler+0x334>
8002368: 2b30 cmp r3, #48 ; 0x30
800236a: d010 beq.n 800238e <HAL_CAN_IRQHandler+0x30c>
800236c: 2b30 cmp r3, #48 ; 0x30
800236e: d822 bhi.n 80023b6 <HAL_CAN_IRQHandler+0x334>
8002370: 2b10 cmp r3, #16
8002372: d002 beq.n 800237a <HAL_CAN_IRQHandler+0x2f8>
8002374: 2b20 cmp r3, #32
8002376: d005 beq.n 8002384 <HAL_CAN_IRQHandler+0x302>
case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
/* Set CAN error code to CRC error */
errorcode |= HAL_CAN_ERROR_CRC;
break;
default:
break;
8002378: e01d b.n 80023b6 <HAL_CAN_IRQHandler+0x334>
errorcode |= HAL_CAN_ERROR_STF;
800237a: 6a7b ldr r3, [r7, #36] ; 0x24
800237c: f043 0308 orr.w r3, r3, #8
8002380: 627b str r3, [r7, #36] ; 0x24
break;
8002382: e019 b.n 80023b8 <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_FOR;
8002384: 6a7b ldr r3, [r7, #36] ; 0x24
8002386: f043 0310 orr.w r3, r3, #16
800238a: 627b str r3, [r7, #36] ; 0x24
break;
800238c: e014 b.n 80023b8 <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_ACK;
800238e: 6a7b ldr r3, [r7, #36] ; 0x24
8002390: f043 0320 orr.w r3, r3, #32
8002394: 627b str r3, [r7, #36] ; 0x24
break;
8002396: e00f b.n 80023b8 <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_BR;
8002398: 6a7b ldr r3, [r7, #36] ; 0x24
800239a: f043 0340 orr.w r3, r3, #64 ; 0x40
800239e: 627b str r3, [r7, #36] ; 0x24
break;
80023a0: e00a b.n 80023b8 <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_BD;
80023a2: 6a7b ldr r3, [r7, #36] ; 0x24
80023a4: f043 0380 orr.w r3, r3, #128 ; 0x80
80023a8: 627b str r3, [r7, #36] ; 0x24
break;
80023aa: e005 b.n 80023b8 <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_CRC;
80023ac: 6a7b ldr r3, [r7, #36] ; 0x24
80023ae: f443 7380 orr.w r3, r3, #256 ; 0x100
80023b2: 627b str r3, [r7, #36] ; 0x24
break;
80023b4: e000 b.n 80023b8 <HAL_CAN_IRQHandler+0x336>
break;
80023b6: bf00 nop
}
/* Clear Last error code Flag */
CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
80023b8: 687b ldr r3, [r7, #4]
80023ba: 681b ldr r3, [r3, #0]
80023bc: 699a ldr r2, [r3, #24]
80023be: 687b ldr r3, [r7, #4]
80023c0: 681b ldr r3, [r3, #0]
80023c2: f022 0270 bic.w r2, r2, #112 ; 0x70
80023c6: 619a str r2, [r3, #24]
}
}
/* Clear ERRI Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);
80023c8: 687b ldr r3, [r7, #4]
80023ca: 681b ldr r3, [r3, #0]
80023cc: 2204 movs r2, #4
80023ce: 605a str r2, [r3, #4]
}
/* Call the Error call Back in case of Errors */
if (errorcode != HAL_CAN_ERROR_NONE)
80023d0: 6a7b ldr r3, [r7, #36] ; 0x24
80023d2: 2b00 cmp r3, #0
80023d4: d008 beq.n 80023e8 <HAL_CAN_IRQHandler+0x366>
{
/* Update error code in handle */
hcan->ErrorCode |= errorcode;
80023d6: 687b ldr r3, [r7, #4]
80023d8: 6a5a ldr r2, [r3, #36] ; 0x24
80023da: 6a7b ldr r3, [r7, #36] ; 0x24
80023dc: 431a orrs r2, r3
80023de: 687b ldr r3, [r7, #4]
80023e0: 625a str r2, [r3, #36] ; 0x24
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->ErrorCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_ErrorCallback(hcan);
80023e2: 6878 ldr r0, [r7, #4]
80023e4: f000 f87c bl 80024e0 <HAL_CAN_ErrorCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
80023e8: bf00 nop
80023ea: 3728 adds r7, #40 ; 0x28
80023ec: 46bd mov sp, r7
80023ee: bd80 pop {r7, pc}
080023f0 <HAL_CAN_TxMailbox0CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)
{
80023f0: b480 push {r7}
80023f2: b083 sub sp, #12
80023f4: af00 add r7, sp, #0
80023f6: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the
user file
*/
}
80023f8: bf00 nop
80023fa: 370c adds r7, #12
80023fc: 46bd mov sp, r7
80023fe: f85d 7b04 ldr.w r7, [sp], #4
8002402: 4770 bx lr
08002404 <HAL_CAN_TxMailbox1CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)
{
8002404: b480 push {r7}
8002406: b083 sub sp, #12
8002408: af00 add r7, sp, #0
800240a: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the
user file
*/
}
800240c: bf00 nop
800240e: 370c adds r7, #12
8002410: 46bd mov sp, r7
8002412: f85d 7b04 ldr.w r7, [sp], #4
8002416: 4770 bx lr
08002418 <HAL_CAN_TxMailbox2CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)
{
8002418: b480 push {r7}
800241a: b083 sub sp, #12
800241c: af00 add r7, sp, #0
800241e: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the
user file
*/
}
8002420: bf00 nop
8002422: 370c adds r7, #12
8002424: 46bd mov sp, r7
8002426: f85d 7b04 ldr.w r7, [sp], #4
800242a: 4770 bx lr
0800242c <HAL_CAN_TxMailbox0AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)
{
800242c: b480 push {r7}
800242e: b083 sub sp, #12
8002430: af00 add r7, sp, #0
8002432: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox0AbortCallback could be implemented in the
user file
*/
}
8002434: bf00 nop
8002436: 370c adds r7, #12
8002438: 46bd mov sp, r7
800243a: f85d 7b04 ldr.w r7, [sp], #4
800243e: 4770 bx lr
08002440 <HAL_CAN_TxMailbox1AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)
{
8002440: b480 push {r7}
8002442: b083 sub sp, #12
8002444: af00 add r7, sp, #0
8002446: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox1AbortCallback could be implemented in the
user file
*/
}
8002448: bf00 nop
800244a: 370c adds r7, #12
800244c: 46bd mov sp, r7
800244e: f85d 7b04 ldr.w r7, [sp], #4
8002452: 4770 bx lr
08002454 <HAL_CAN_TxMailbox2AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)
{
8002454: b480 push {r7}
8002456: b083 sub sp, #12
8002458: af00 add r7, sp, #0
800245a: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox2AbortCallback could be implemented in the
user file
*/
}
800245c: bf00 nop
800245e: 370c adds r7, #12
8002460: 46bd mov sp, r7
8002462: f85d 7b04 ldr.w r7, [sp], #4
8002466: 4770 bx lr
08002468 <HAL_CAN_RxFifo0MsgPendingCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan)
{
8002468: b480 push {r7}
800246a: b083 sub sp, #12
800246c: af00 add r7, sp, #0
800246e: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the
user file
*/
}
8002470: bf00 nop
8002472: 370c adds r7, #12
8002474: 46bd mov sp, r7
8002476: f85d 7b04 ldr.w r7, [sp], #4
800247a: 4770 bx lr
0800247c <HAL_CAN_RxFifo0FullCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)
{
800247c: b480 push {r7}
800247e: b083 sub sp, #12
8002480: af00 add r7, sp, #0
8002482: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo0FullCallback could be implemented in the user
file
*/
}
8002484: bf00 nop
8002486: 370c adds r7, #12
8002488: 46bd mov sp, r7
800248a: f85d 7b04 ldr.w r7, [sp], #4
800248e: 4770 bx lr
08002490 <HAL_CAN_RxFifo1MsgPendingCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan)
{
8002490: b480 push {r7}
8002492: b083 sub sp, #12
8002494: af00 add r7, sp, #0
8002496: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the
user file
*/
}
8002498: bf00 nop
800249a: 370c adds r7, #12
800249c: 46bd mov sp, r7
800249e: f85d 7b04 ldr.w r7, [sp], #4
80024a2: 4770 bx lr
080024a4 <HAL_CAN_RxFifo1FullCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)
{
80024a4: b480 push {r7}
80024a6: b083 sub sp, #12
80024a8: af00 add r7, sp, #0
80024aa: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo1FullCallback could be implemented in the user
file
*/
}
80024ac: bf00 nop
80024ae: 370c adds r7, #12
80024b0: 46bd mov sp, r7
80024b2: f85d 7b04 ldr.w r7, [sp], #4
80024b6: 4770 bx lr
080024b8 <HAL_CAN_SleepCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)
{
80024b8: b480 push {r7}
80024ba: b083 sub sp, #12
80024bc: af00 add r7, sp, #0
80024be: 6078 str r0, [r7, #4]
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_SleepCallback could be implemented in the user file
*/
}
80024c0: bf00 nop
80024c2: 370c adds r7, #12
80024c4: 46bd mov sp, r7
80024c6: f85d 7b04 ldr.w r7, [sp], #4
80024ca: 4770 bx lr
080024cc <HAL_CAN_WakeUpFromRxMsgCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)
{
80024cc: b480 push {r7}
80024ce: b083 sub sp, #12
80024d0: af00 add r7, sp, #0
80024d2: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the
user file
*/
}
80024d4: bf00 nop
80024d6: 370c adds r7, #12
80024d8: 46bd mov sp, r7
80024da: f85d 7b04 ldr.w r7, [sp], #4
80024de: 4770 bx lr
080024e0 <HAL_CAN_ErrorCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
{
80024e0: b480 push {r7}
80024e2: b083 sub sp, #12
80024e4: af00 add r7, sp, #0
80024e6: 6078 str r0, [r7, #4]
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_ErrorCallback could be implemented in the user file
*/
}
80024e8: bf00 nop
80024ea: 370c adds r7, #12
80024ec: 46bd mov sp, r7
80024ee: f85d 7b04 ldr.w r7, [sp], #4
80024f2: 4770 bx lr
080024f4 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80024f4: b480 push {r7}
80024f6: b085 sub sp, #20
80024f8: af00 add r7, sp, #0
80024fa: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80024fc: 687b ldr r3, [r7, #4]
80024fe: f003 0307 and.w r3, r3, #7
8002502: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8002504: 4b0c ldr r3, [pc, #48] ; (8002538 <__NVIC_SetPriorityGrouping+0x44>)
8002506: 68db ldr r3, [r3, #12]
8002508: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
800250a: 68ba ldr r2, [r7, #8]
800250c: f64f 03ff movw r3, #63743 ; 0xf8ff
8002510: 4013 ands r3, r2
8002512: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8002514: 68fb ldr r3, [r7, #12]
8002516: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8002518: 68bb ldr r3, [r7, #8]
800251a: 4313 orrs r3, r2
reg_value = (reg_value |
800251c: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
8002520: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8002524: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8002526: 4a04 ldr r2, [pc, #16] ; (8002538 <__NVIC_SetPriorityGrouping+0x44>)
8002528: 68bb ldr r3, [r7, #8]
800252a: 60d3 str r3, [r2, #12]
}
800252c: bf00 nop
800252e: 3714 adds r7, #20
8002530: 46bd mov sp, r7
8002532: f85d 7b04 ldr.w r7, [sp], #4
8002536: 4770 bx lr
8002538: e000ed00 .word 0xe000ed00
0800253c <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
800253c: b480 push {r7}
800253e: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8002540: 4b04 ldr r3, [pc, #16] ; (8002554 <__NVIC_GetPriorityGrouping+0x18>)
8002542: 68db ldr r3, [r3, #12]
8002544: 0a1b lsrs r3, r3, #8
8002546: f003 0307 and.w r3, r3, #7
}
800254a: 4618 mov r0, r3
800254c: 46bd mov sp, r7
800254e: f85d 7b04 ldr.w r7, [sp], #4
8002552: 4770 bx lr
8002554: e000ed00 .word 0xe000ed00
08002558 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8002558: b480 push {r7}
800255a: b083 sub sp, #12
800255c: af00 add r7, sp, #0
800255e: 4603 mov r3, r0
8002560: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8002562: f997 3007 ldrsb.w r3, [r7, #7]
8002566: 2b00 cmp r3, #0
8002568: db0b blt.n 8002582 <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
800256a: 79fb ldrb r3, [r7, #7]
800256c: f003 021f and.w r2, r3, #31
8002570: 4907 ldr r1, [pc, #28] ; (8002590 <__NVIC_EnableIRQ+0x38>)
8002572: f997 3007 ldrsb.w r3, [r7, #7]
8002576: 095b lsrs r3, r3, #5
8002578: 2001 movs r0, #1
800257a: fa00 f202 lsl.w r2, r0, r2
800257e: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8002582: bf00 nop
8002584: 370c adds r7, #12
8002586: 46bd mov sp, r7
8002588: f85d 7b04 ldr.w r7, [sp], #4
800258c: 4770 bx lr
800258e: bf00 nop
8002590: e000e100 .word 0xe000e100
08002594 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8002594: b480 push {r7}
8002596: b083 sub sp, #12
8002598: af00 add r7, sp, #0
800259a: 4603 mov r3, r0
800259c: 6039 str r1, [r7, #0]
800259e: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80025a0: f997 3007 ldrsb.w r3, [r7, #7]
80025a4: 2b00 cmp r3, #0
80025a6: db0a blt.n 80025be <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80025a8: 683b ldr r3, [r7, #0]
80025aa: b2da uxtb r2, r3
80025ac: 490c ldr r1, [pc, #48] ; (80025e0 <__NVIC_SetPriority+0x4c>)
80025ae: f997 3007 ldrsb.w r3, [r7, #7]
80025b2: 0112 lsls r2, r2, #4
80025b4: b2d2 uxtb r2, r2
80025b6: 440b add r3, r1
80025b8: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
80025bc: e00a b.n 80025d4 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80025be: 683b ldr r3, [r7, #0]
80025c0: b2da uxtb r2, r3
80025c2: 4908 ldr r1, [pc, #32] ; (80025e4 <__NVIC_SetPriority+0x50>)
80025c4: 79fb ldrb r3, [r7, #7]
80025c6: f003 030f and.w r3, r3, #15
80025ca: 3b04 subs r3, #4
80025cc: 0112 lsls r2, r2, #4
80025ce: b2d2 uxtb r2, r2
80025d0: 440b add r3, r1
80025d2: 761a strb r2, [r3, #24]
}
80025d4: bf00 nop
80025d6: 370c adds r7, #12
80025d8: 46bd mov sp, r7
80025da: f85d 7b04 ldr.w r7, [sp], #4
80025de: 4770 bx lr
80025e0: e000e100 .word 0xe000e100
80025e4: e000ed00 .word 0xe000ed00
080025e8 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80025e8: b480 push {r7}
80025ea: b089 sub sp, #36 ; 0x24
80025ec: af00 add r7, sp, #0
80025ee: 60f8 str r0, [r7, #12]
80025f0: 60b9 str r1, [r7, #8]
80025f2: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80025f4: 68fb ldr r3, [r7, #12]
80025f6: f003 0307 and.w r3, r3, #7
80025fa: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80025fc: 69fb ldr r3, [r7, #28]
80025fe: f1c3 0307 rsb r3, r3, #7
8002602: 2b04 cmp r3, #4
8002604: bf28 it cs
8002606: 2304 movcs r3, #4
8002608: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
800260a: 69fb ldr r3, [r7, #28]
800260c: 3304 adds r3, #4
800260e: 2b06 cmp r3, #6
8002610: d902 bls.n 8002618 <NVIC_EncodePriority+0x30>
8002612: 69fb ldr r3, [r7, #28]
8002614: 3b03 subs r3, #3
8002616: e000 b.n 800261a <NVIC_EncodePriority+0x32>
8002618: 2300 movs r3, #0
800261a: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
800261c: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
8002620: 69bb ldr r3, [r7, #24]
8002622: fa02 f303 lsl.w r3, r2, r3
8002626: 43da mvns r2, r3
8002628: 68bb ldr r3, [r7, #8]
800262a: 401a ands r2, r3
800262c: 697b ldr r3, [r7, #20]
800262e: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8002630: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
8002634: 697b ldr r3, [r7, #20]
8002636: fa01 f303 lsl.w r3, r1, r3
800263a: 43d9 mvns r1, r3
800263c: 687b ldr r3, [r7, #4]
800263e: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8002640: 4313 orrs r3, r2
);
}
8002642: 4618 mov r0, r3
8002644: 3724 adds r7, #36 ; 0x24
8002646: 46bd mov sp, r7
8002648: f85d 7b04 ldr.w r7, [sp], #4
800264c: 4770 bx lr
...
08002650 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8002650: b580 push {r7, lr}
8002652: b082 sub sp, #8
8002654: af00 add r7, sp, #0
8002656: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8002658: 687b ldr r3, [r7, #4]
800265a: 3b01 subs r3, #1
800265c: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
8002660: d301 bcc.n 8002666 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8002662: 2301 movs r3, #1
8002664: e00f b.n 8002686 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8002666: 4a0a ldr r2, [pc, #40] ; (8002690 <SysTick_Config+0x40>)
8002668: 687b ldr r3, [r7, #4]
800266a: 3b01 subs r3, #1
800266c: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
800266e: 210f movs r1, #15
8002670: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
8002674: f7ff ff8e bl 8002594 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8002678: 4b05 ldr r3, [pc, #20] ; (8002690 <SysTick_Config+0x40>)
800267a: 2200 movs r2, #0
800267c: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
800267e: 4b04 ldr r3, [pc, #16] ; (8002690 <SysTick_Config+0x40>)
8002680: 2207 movs r2, #7
8002682: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8002684: 2300 movs r3, #0
}
8002686: 4618 mov r0, r3
8002688: 3708 adds r7, #8
800268a: 46bd mov sp, r7
800268c: bd80 pop {r7, pc}
800268e: bf00 nop
8002690: e000e010 .word 0xe000e010
08002694 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8002694: b580 push {r7, lr}
8002696: b082 sub sp, #8
8002698: af00 add r7, sp, #0
800269a: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
800269c: 6878 ldr r0, [r7, #4]
800269e: f7ff ff29 bl 80024f4 <__NVIC_SetPriorityGrouping>
}
80026a2: bf00 nop
80026a4: 3708 adds r7, #8
80026a6: 46bd mov sp, r7
80026a8: bd80 pop {r7, pc}
080026aa <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
80026aa: b580 push {r7, lr}
80026ac: b086 sub sp, #24
80026ae: af00 add r7, sp, #0
80026b0: 4603 mov r3, r0
80026b2: 60b9 str r1, [r7, #8]
80026b4: 607a str r2, [r7, #4]
80026b6: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
80026b8: 2300 movs r3, #0
80026ba: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
80026bc: f7ff ff3e bl 800253c <__NVIC_GetPriorityGrouping>
80026c0: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
80026c2: 687a ldr r2, [r7, #4]
80026c4: 68b9 ldr r1, [r7, #8]
80026c6: 6978 ldr r0, [r7, #20]
80026c8: f7ff ff8e bl 80025e8 <NVIC_EncodePriority>
80026cc: 4602 mov r2, r0
80026ce: f997 300f ldrsb.w r3, [r7, #15]
80026d2: 4611 mov r1, r2
80026d4: 4618 mov r0, r3
80026d6: f7ff ff5d bl 8002594 <__NVIC_SetPriority>
}
80026da: bf00 nop
80026dc: 3718 adds r7, #24
80026de: 46bd mov sp, r7
80026e0: bd80 pop {r7, pc}
080026e2 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
80026e2: b580 push {r7, lr}
80026e4: b082 sub sp, #8
80026e6: af00 add r7, sp, #0
80026e8: 4603 mov r3, r0
80026ea: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
80026ec: f997 3007 ldrsb.w r3, [r7, #7]
80026f0: 4618 mov r0, r3
80026f2: f7ff ff31 bl 8002558 <__NVIC_EnableIRQ>
}
80026f6: bf00 nop
80026f8: 3708 adds r7, #8
80026fa: 46bd mov sp, r7
80026fc: bd80 pop {r7, pc}
080026fe <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80026fe: b580 push {r7, lr}
8002700: b082 sub sp, #8
8002702: af00 add r7, sp, #0
8002704: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8002706: 6878 ldr r0, [r7, #4]
8002708: f7ff ffa2 bl 8002650 <SysTick_Config>
800270c: 4603 mov r3, r0
}
800270e: 4618 mov r0, r3
8002710: 3708 adds r7, #8
8002712: 46bd mov sp, r7
8002714: bd80 pop {r7, pc}
...
08002718 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8002718: b480 push {r7}
800271a: b087 sub sp, #28
800271c: af00 add r7, sp, #0
800271e: 6078 str r0, [r7, #4]
8002720: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8002722: 2300 movs r3, #0
8002724: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
8002726: e154 b.n 80029d2 <HAL_GPIO_Init+0x2ba>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
8002728: 683b ldr r3, [r7, #0]
800272a: 681a ldr r2, [r3, #0]
800272c: 2101 movs r1, #1
800272e: 697b ldr r3, [r7, #20]
8002730: fa01 f303 lsl.w r3, r1, r3
8002734: 4013 ands r3, r2
8002736: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8002738: 68fb ldr r3, [r7, #12]
800273a: 2b00 cmp r3, #0
800273c: f000 8146 beq.w 80029cc <HAL_GPIO_Init+0x2b4>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8002740: 683b ldr r3, [r7, #0]
8002742: 685b ldr r3, [r3, #4]
8002744: f003 0303 and.w r3, r3, #3
8002748: 2b01 cmp r3, #1
800274a: d005 beq.n 8002758 <HAL_GPIO_Init+0x40>
800274c: 683b ldr r3, [r7, #0]
800274e: 685b ldr r3, [r3, #4]
8002750: f003 0303 and.w r3, r3, #3
8002754: 2b02 cmp r3, #2
8002756: d130 bne.n 80027ba <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8002758: 687b ldr r3, [r7, #4]
800275a: 689b ldr r3, [r3, #8]
800275c: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
800275e: 697b ldr r3, [r7, #20]
8002760: 005b lsls r3, r3, #1
8002762: 2203 movs r2, #3
8002764: fa02 f303 lsl.w r3, r2, r3
8002768: 43db mvns r3, r3
800276a: 693a ldr r2, [r7, #16]
800276c: 4013 ands r3, r2
800276e: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
8002770: 683b ldr r3, [r7, #0]
8002772: 68da ldr r2, [r3, #12]
8002774: 697b ldr r3, [r7, #20]
8002776: 005b lsls r3, r3, #1
8002778: fa02 f303 lsl.w r3, r2, r3
800277c: 693a ldr r2, [r7, #16]
800277e: 4313 orrs r3, r2
8002780: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8002782: 687b ldr r3, [r7, #4]
8002784: 693a ldr r2, [r7, #16]
8002786: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8002788: 687b ldr r3, [r7, #4]
800278a: 685b ldr r3, [r3, #4]
800278c: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
800278e: 2201 movs r2, #1
8002790: 697b ldr r3, [r7, #20]
8002792: fa02 f303 lsl.w r3, r2, r3
8002796: 43db mvns r3, r3
8002798: 693a ldr r2, [r7, #16]
800279a: 4013 ands r3, r2
800279c: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
800279e: 683b ldr r3, [r7, #0]
80027a0: 685b ldr r3, [r3, #4]
80027a2: 091b lsrs r3, r3, #4
80027a4: f003 0201 and.w r2, r3, #1
80027a8: 697b ldr r3, [r7, #20]
80027aa: fa02 f303 lsl.w r3, r2, r3
80027ae: 693a ldr r2, [r7, #16]
80027b0: 4313 orrs r3, r2
80027b2: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
80027b4: 687b ldr r3, [r7, #4]
80027b6: 693a ldr r2, [r7, #16]
80027b8: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
80027ba: 683b ldr r3, [r7, #0]
80027bc: 685b ldr r3, [r3, #4]
80027be: f003 0303 and.w r3, r3, #3
80027c2: 2b03 cmp r3, #3
80027c4: d017 beq.n 80027f6 <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
80027c6: 687b ldr r3, [r7, #4]
80027c8: 68db ldr r3, [r3, #12]
80027ca: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
80027cc: 697b ldr r3, [r7, #20]
80027ce: 005b lsls r3, r3, #1
80027d0: 2203 movs r2, #3
80027d2: fa02 f303 lsl.w r3, r2, r3
80027d6: 43db mvns r3, r3
80027d8: 693a ldr r2, [r7, #16]
80027da: 4013 ands r3, r2
80027dc: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2u));
80027de: 683b ldr r3, [r7, #0]
80027e0: 689a ldr r2, [r3, #8]
80027e2: 697b ldr r3, [r7, #20]
80027e4: 005b lsls r3, r3, #1
80027e6: fa02 f303 lsl.w r3, r2, r3
80027ea: 693a ldr r2, [r7, #16]
80027ec: 4313 orrs r3, r2
80027ee: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
80027f0: 687b ldr r3, [r7, #4]
80027f2: 693a ldr r2, [r7, #16]
80027f4: 60da str r2, [r3, #12]
}
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80027f6: 683b ldr r3, [r7, #0]
80027f8: 685b ldr r3, [r3, #4]
80027fa: f003 0303 and.w r3, r3, #3
80027fe: 2b02 cmp r3, #2
8002800: d123 bne.n 800284a <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
8002802: 697b ldr r3, [r7, #20]
8002804: 08da lsrs r2, r3, #3
8002806: 687b ldr r3, [r7, #4]
8002808: 3208 adds r2, #8
800280a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800280e: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
8002810: 697b ldr r3, [r7, #20]
8002812: f003 0307 and.w r3, r3, #7
8002816: 009b lsls r3, r3, #2
8002818: 220f movs r2, #15
800281a: fa02 f303 lsl.w r3, r2, r3
800281e: 43db mvns r3, r3
8002820: 693a ldr r2, [r7, #16]
8002822: 4013 ands r3, r2
8002824: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
8002826: 683b ldr r3, [r7, #0]
8002828: 691a ldr r2, [r3, #16]
800282a: 697b ldr r3, [r7, #20]
800282c: f003 0307 and.w r3, r3, #7
8002830: 009b lsls r3, r3, #2
8002832: fa02 f303 lsl.w r3, r2, r3
8002836: 693a ldr r2, [r7, #16]
8002838: 4313 orrs r3, r2
800283a: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
800283c: 697b ldr r3, [r7, #20]
800283e: 08da lsrs r2, r3, #3
8002840: 687b ldr r3, [r7, #4]
8002842: 3208 adds r2, #8
8002844: 6939 ldr r1, [r7, #16]
8002846: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
800284a: 687b ldr r3, [r7, #4]
800284c: 681b ldr r3, [r3, #0]
800284e: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
8002850: 697b ldr r3, [r7, #20]
8002852: 005b lsls r3, r3, #1
8002854: 2203 movs r2, #3
8002856: fa02 f303 lsl.w r3, r2, r3
800285a: 43db mvns r3, r3
800285c: 693a ldr r2, [r7, #16]
800285e: 4013 ands r3, r2
8002860: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
8002862: 683b ldr r3, [r7, #0]
8002864: 685b ldr r3, [r3, #4]
8002866: f003 0203 and.w r2, r3, #3
800286a: 697b ldr r3, [r7, #20]
800286c: 005b lsls r3, r3, #1
800286e: fa02 f303 lsl.w r3, r2, r3
8002872: 693a ldr r2, [r7, #16]
8002874: 4313 orrs r3, r2
8002876: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8002878: 687b ldr r3, [r7, #4]
800287a: 693a ldr r2, [r7, #16]
800287c: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
800287e: 683b ldr r3, [r7, #0]
8002880: 685b ldr r3, [r3, #4]
8002882: f403 3340 and.w r3, r3, #196608 ; 0x30000
8002886: 2b00 cmp r3, #0
8002888: f000 80a0 beq.w 80029cc <HAL_GPIO_Init+0x2b4>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
800288c: 4b58 ldr r3, [pc, #352] ; (80029f0 <HAL_GPIO_Init+0x2d8>)
800288e: 699b ldr r3, [r3, #24]
8002890: 4a57 ldr r2, [pc, #348] ; (80029f0 <HAL_GPIO_Init+0x2d8>)
8002892: f043 0301 orr.w r3, r3, #1
8002896: 6193 str r3, [r2, #24]
8002898: 4b55 ldr r3, [pc, #340] ; (80029f0 <HAL_GPIO_Init+0x2d8>)
800289a: 699b ldr r3, [r3, #24]
800289c: f003 0301 and.w r3, r3, #1
80028a0: 60bb str r3, [r7, #8]
80028a2: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2u];
80028a4: 4a53 ldr r2, [pc, #332] ; (80029f4 <HAL_GPIO_Init+0x2dc>)
80028a6: 697b ldr r3, [r7, #20]
80028a8: 089b lsrs r3, r3, #2
80028aa: 3302 adds r3, #2
80028ac: f852 3023 ldr.w r3, [r2, r3, lsl #2]
80028b0: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
80028b2: 697b ldr r3, [r7, #20]
80028b4: f003 0303 and.w r3, r3, #3
80028b8: 009b lsls r3, r3, #2
80028ba: 220f movs r2, #15
80028bc: fa02 f303 lsl.w r3, r2, r3
80028c0: 43db mvns r3, r3
80028c2: 693a ldr r2, [r7, #16]
80028c4: 4013 ands r3, r2
80028c6: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
80028c8: 687b ldr r3, [r7, #4]
80028ca: f1b3 4f90 cmp.w r3, #1207959552 ; 0x48000000
80028ce: d019 beq.n 8002904 <HAL_GPIO_Init+0x1ec>
80028d0: 687b ldr r3, [r7, #4]
80028d2: 4a49 ldr r2, [pc, #292] ; (80029f8 <HAL_GPIO_Init+0x2e0>)
80028d4: 4293 cmp r3, r2
80028d6: d013 beq.n 8002900 <HAL_GPIO_Init+0x1e8>
80028d8: 687b ldr r3, [r7, #4]
80028da: 4a48 ldr r2, [pc, #288] ; (80029fc <HAL_GPIO_Init+0x2e4>)
80028dc: 4293 cmp r3, r2
80028de: d00d beq.n 80028fc <HAL_GPIO_Init+0x1e4>
80028e0: 687b ldr r3, [r7, #4]
80028e2: 4a47 ldr r2, [pc, #284] ; (8002a00 <HAL_GPIO_Init+0x2e8>)
80028e4: 4293 cmp r3, r2
80028e6: d007 beq.n 80028f8 <HAL_GPIO_Init+0x1e0>
80028e8: 687b ldr r3, [r7, #4]
80028ea: 4a46 ldr r2, [pc, #280] ; (8002a04 <HAL_GPIO_Init+0x2ec>)
80028ec: 4293 cmp r3, r2
80028ee: d101 bne.n 80028f4 <HAL_GPIO_Init+0x1dc>
80028f0: 2304 movs r3, #4
80028f2: e008 b.n 8002906 <HAL_GPIO_Init+0x1ee>
80028f4: 2305 movs r3, #5
80028f6: e006 b.n 8002906 <HAL_GPIO_Init+0x1ee>
80028f8: 2303 movs r3, #3
80028fa: e004 b.n 8002906 <HAL_GPIO_Init+0x1ee>
80028fc: 2302 movs r3, #2
80028fe: e002 b.n 8002906 <HAL_GPIO_Init+0x1ee>
8002900: 2301 movs r3, #1
8002902: e000 b.n 8002906 <HAL_GPIO_Init+0x1ee>
8002904: 2300 movs r3, #0
8002906: 697a ldr r2, [r7, #20]
8002908: f002 0203 and.w r2, r2, #3
800290c: 0092 lsls r2, r2, #2
800290e: 4093 lsls r3, r2
8002910: 693a ldr r2, [r7, #16]
8002912: 4313 orrs r3, r2
8002914: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
8002916: 4937 ldr r1, [pc, #220] ; (80029f4 <HAL_GPIO_Init+0x2dc>)
8002918: 697b ldr r3, [r7, #20]
800291a: 089b lsrs r3, r3, #2
800291c: 3302 adds r3, #2
800291e: 693a ldr r2, [r7, #16]
8002920: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8002924: 4b38 ldr r3, [pc, #224] ; (8002a08 <HAL_GPIO_Init+0x2f0>)
8002926: 689b ldr r3, [r3, #8]
8002928: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
800292a: 68fb ldr r3, [r7, #12]
800292c: 43db mvns r3, r3
800292e: 693a ldr r2, [r7, #16]
8002930: 4013 ands r3, r2
8002932: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
8002934: 683b ldr r3, [r7, #0]
8002936: 685b ldr r3, [r3, #4]
8002938: f403 1380 and.w r3, r3, #1048576 ; 0x100000
800293c: 2b00 cmp r3, #0
800293e: d003 beq.n 8002948 <HAL_GPIO_Init+0x230>
{
temp |= iocurrent;
8002940: 693a ldr r2, [r7, #16]
8002942: 68fb ldr r3, [r7, #12]
8002944: 4313 orrs r3, r2
8002946: 613b str r3, [r7, #16]
}
EXTI->RTSR = temp;
8002948: 4a2f ldr r2, [pc, #188] ; (8002a08 <HAL_GPIO_Init+0x2f0>)
800294a: 693b ldr r3, [r7, #16]
800294c: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
800294e: 4b2e ldr r3, [pc, #184] ; (8002a08 <HAL_GPIO_Init+0x2f0>)
8002950: 68db ldr r3, [r3, #12]
8002952: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8002954: 68fb ldr r3, [r7, #12]
8002956: 43db mvns r3, r3
8002958: 693a ldr r2, [r7, #16]
800295a: 4013 ands r3, r2
800295c: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
800295e: 683b ldr r3, [r7, #0]
8002960: 685b ldr r3, [r3, #4]
8002962: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8002966: 2b00 cmp r3, #0
8002968: d003 beq.n 8002972 <HAL_GPIO_Init+0x25a>
{
temp |= iocurrent;
800296a: 693a ldr r2, [r7, #16]
800296c: 68fb ldr r3, [r7, #12]
800296e: 4313 orrs r3, r2
8002970: 613b str r3, [r7, #16]
}
EXTI->FTSR = temp;
8002972: 4a25 ldr r2, [pc, #148] ; (8002a08 <HAL_GPIO_Init+0x2f0>)
8002974: 693b ldr r3, [r7, #16]
8002976: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
8002978: 4b23 ldr r3, [pc, #140] ; (8002a08 <HAL_GPIO_Init+0x2f0>)
800297a: 685b ldr r3, [r3, #4]
800297c: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
800297e: 68fb ldr r3, [r7, #12]
8002980: 43db mvns r3, r3
8002982: 693a ldr r2, [r7, #16]
8002984: 4013 ands r3, r2
8002986: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8002988: 683b ldr r3, [r7, #0]
800298a: 685b ldr r3, [r3, #4]
800298c: f403 3300 and.w r3, r3, #131072 ; 0x20000
8002990: 2b00 cmp r3, #0
8002992: d003 beq.n 800299c <HAL_GPIO_Init+0x284>
{
temp |= iocurrent;
8002994: 693a ldr r2, [r7, #16]
8002996: 68fb ldr r3, [r7, #12]
8002998: 4313 orrs r3, r2
800299a: 613b str r3, [r7, #16]
}
EXTI->EMR = temp;
800299c: 4a1a ldr r2, [pc, #104] ; (8002a08 <HAL_GPIO_Init+0x2f0>)
800299e: 693b ldr r3, [r7, #16]
80029a0: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
80029a2: 4b19 ldr r3, [pc, #100] ; (8002a08 <HAL_GPIO_Init+0x2f0>)
80029a4: 681b ldr r3, [r3, #0]
80029a6: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
80029a8: 68fb ldr r3, [r7, #12]
80029aa: 43db mvns r3, r3
80029ac: 693a ldr r2, [r7, #16]
80029ae: 4013 ands r3, r2
80029b0: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
80029b2: 683b ldr r3, [r7, #0]
80029b4: 685b ldr r3, [r3, #4]
80029b6: f403 3380 and.w r3, r3, #65536 ; 0x10000
80029ba: 2b00 cmp r3, #0
80029bc: d003 beq.n 80029c6 <HAL_GPIO_Init+0x2ae>
{
temp |= iocurrent;
80029be: 693a ldr r2, [r7, #16]
80029c0: 68fb ldr r3, [r7, #12]
80029c2: 4313 orrs r3, r2
80029c4: 613b str r3, [r7, #16]
}
EXTI->IMR = temp;
80029c6: 4a10 ldr r2, [pc, #64] ; (8002a08 <HAL_GPIO_Init+0x2f0>)
80029c8: 693b ldr r3, [r7, #16]
80029ca: 6013 str r3, [r2, #0]
}
}
position++;
80029cc: 697b ldr r3, [r7, #20]
80029ce: 3301 adds r3, #1
80029d0: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
80029d2: 683b ldr r3, [r7, #0]
80029d4: 681a ldr r2, [r3, #0]
80029d6: 697b ldr r3, [r7, #20]
80029d8: fa22 f303 lsr.w r3, r2, r3
80029dc: 2b00 cmp r3, #0
80029de: f47f aea3 bne.w 8002728 <HAL_GPIO_Init+0x10>
}
}
80029e2: bf00 nop
80029e4: bf00 nop
80029e6: 371c adds r7, #28
80029e8: 46bd mov sp, r7
80029ea: f85d 7b04 ldr.w r7, [sp], #4
80029ee: 4770 bx lr
80029f0: 40021000 .word 0x40021000
80029f4: 40010000 .word 0x40010000
80029f8: 48000400 .word 0x48000400
80029fc: 48000800 .word 0x48000800
8002a00: 48000c00 .word 0x48000c00
8002a04: 48001000 .word 0x48001000
8002a08: 40010400 .word 0x40010400
08002a0c <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8002a0c: b480 push {r7}
8002a0e: b083 sub sp, #12
8002a10: af00 add r7, sp, #0
8002a12: 6078 str r0, [r7, #4]
8002a14: 460b mov r3, r1
8002a16: 807b strh r3, [r7, #2]
8002a18: 4613 mov r3, r2
8002a1a: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
8002a1c: 787b ldrb r3, [r7, #1]
8002a1e: 2b00 cmp r3, #0
8002a20: d003 beq.n 8002a2a <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8002a22: 887a ldrh r2, [r7, #2]
8002a24: 687b ldr r3, [r7, #4]
8002a26: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
8002a28: e002 b.n 8002a30 <HAL_GPIO_WritePin+0x24>
GPIOx->BRR = (uint32_t)GPIO_Pin;
8002a2a: 887a ldrh r2, [r7, #2]
8002a2c: 687b ldr r3, [r7, #4]
8002a2e: 629a str r2, [r3, #40] ; 0x28
}
8002a30: bf00 nop
8002a32: 370c adds r7, #12
8002a34: 46bd mov sp, r7
8002a36: f85d 7b04 ldr.w r7, [sp], #4
8002a3a: 4770 bx lr
08002a3c <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8002a3c: b580 push {r7, lr}
8002a3e: f5ad 7d00 sub.w sp, sp, #512 ; 0x200
8002a42: af00 add r7, sp, #0
8002a44: f507 7300 add.w r3, r7, #512 ; 0x200
8002a48: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002a4c: 6018 str r0, [r3, #0]
#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
uint32_t pll_config2;
#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8002a4e: f507 7300 add.w r3, r7, #512 ; 0x200
8002a52: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002a56: 681b ldr r3, [r3, #0]
8002a58: 2b00 cmp r3, #0
8002a5a: d102 bne.n 8002a62 <HAL_RCC_OscConfig+0x26>
{
return HAL_ERROR;
8002a5c: 2301 movs r3, #1
8002a5e: f001 b823 b.w 8003aa8 <HAL_RCC_OscConfig+0x106c>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8002a62: f507 7300 add.w r3, r7, #512 ; 0x200
8002a66: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002a6a: 681b ldr r3, [r3, #0]
8002a6c: 681b ldr r3, [r3, #0]
8002a6e: f003 0301 and.w r3, r3, #1
8002a72: 2b00 cmp r3, #0
8002a74: f000 817d beq.w 8002d72 <HAL_RCC_OscConfig+0x336>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8002a78: 4bbc ldr r3, [pc, #752] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002a7a: 685b ldr r3, [r3, #4]
8002a7c: f003 030c and.w r3, r3, #12
8002a80: 2b04 cmp r3, #4
8002a82: d00c beq.n 8002a9e <HAL_RCC_OscConfig+0x62>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8002a84: 4bb9 ldr r3, [pc, #740] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002a86: 685b ldr r3, [r3, #4]
8002a88: f003 030c and.w r3, r3, #12
8002a8c: 2b08 cmp r3, #8
8002a8e: d15c bne.n 8002b4a <HAL_RCC_OscConfig+0x10e>
8002a90: 4bb6 ldr r3, [pc, #728] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002a92: 685b ldr r3, [r3, #4]
8002a94: f403 3380 and.w r3, r3, #65536 ; 0x10000
8002a98: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8002a9c: d155 bne.n 8002b4a <HAL_RCC_OscConfig+0x10e>
8002a9e: f44f 3300 mov.w r3, #131072 ; 0x20000
8002aa2: f8c7 31f0 str.w r3, [r7, #496] ; 0x1f0
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002aa6: f8d7 31f0 ldr.w r3, [r7, #496] ; 0x1f0
8002aaa: fa93 f3a3 rbit r3, r3
8002aae: f8c7 31ec str.w r3, [r7, #492] ; 0x1ec
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return result;
8002ab2: f8d7 31ec ldr.w r3, [r7, #492] ; 0x1ec
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8002ab6: fab3 f383 clz r3, r3
8002aba: b2db uxtb r3, r3
8002abc: 095b lsrs r3, r3, #5
8002abe: b2db uxtb r3, r3
8002ac0: f043 0301 orr.w r3, r3, #1
8002ac4: b2db uxtb r3, r3
8002ac6: 2b01 cmp r3, #1
8002ac8: d102 bne.n 8002ad0 <HAL_RCC_OscConfig+0x94>
8002aca: 4ba8 ldr r3, [pc, #672] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002acc: 681b ldr r3, [r3, #0]
8002ace: e015 b.n 8002afc <HAL_RCC_OscConfig+0xc0>
8002ad0: f44f 3300 mov.w r3, #131072 ; 0x20000
8002ad4: f8c7 31e8 str.w r3, [r7, #488] ; 0x1e8
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002ad8: f8d7 31e8 ldr.w r3, [r7, #488] ; 0x1e8
8002adc: fa93 f3a3 rbit r3, r3
8002ae0: f8c7 31e4 str.w r3, [r7, #484] ; 0x1e4
8002ae4: f44f 3300 mov.w r3, #131072 ; 0x20000
8002ae8: f8c7 31e0 str.w r3, [r7, #480] ; 0x1e0
8002aec: f8d7 31e0 ldr.w r3, [r7, #480] ; 0x1e0
8002af0: fa93 f3a3 rbit r3, r3
8002af4: f8c7 31dc str.w r3, [r7, #476] ; 0x1dc
8002af8: 4b9c ldr r3, [pc, #624] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002afa: 6a5b ldr r3, [r3, #36] ; 0x24
8002afc: f44f 3200 mov.w r2, #131072 ; 0x20000
8002b00: f8c7 21d8 str.w r2, [r7, #472] ; 0x1d8
8002b04: f8d7 21d8 ldr.w r2, [r7, #472] ; 0x1d8
8002b08: fa92 f2a2 rbit r2, r2
8002b0c: f8c7 21d4 str.w r2, [r7, #468] ; 0x1d4
return result;
8002b10: f8d7 21d4 ldr.w r2, [r7, #468] ; 0x1d4
8002b14: fab2 f282 clz r2, r2
8002b18: b2d2 uxtb r2, r2
8002b1a: f042 0220 orr.w r2, r2, #32
8002b1e: b2d2 uxtb r2, r2
8002b20: f002 021f and.w r2, r2, #31
8002b24: 2101 movs r1, #1
8002b26: fa01 f202 lsl.w r2, r1, r2
8002b2a: 4013 ands r3, r2
8002b2c: 2b00 cmp r3, #0
8002b2e: f000 811f beq.w 8002d70 <HAL_RCC_OscConfig+0x334>
8002b32: f507 7300 add.w r3, r7, #512 ; 0x200
8002b36: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002b3a: 681b ldr r3, [r3, #0]
8002b3c: 685b ldr r3, [r3, #4]
8002b3e: 2b00 cmp r3, #0
8002b40: f040 8116 bne.w 8002d70 <HAL_RCC_OscConfig+0x334>
{
return HAL_ERROR;
8002b44: 2301 movs r3, #1
8002b46: f000 bfaf b.w 8003aa8 <HAL_RCC_OscConfig+0x106c>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8002b4a: f507 7300 add.w r3, r7, #512 ; 0x200
8002b4e: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002b52: 681b ldr r3, [r3, #0]
8002b54: 685b ldr r3, [r3, #4]
8002b56: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8002b5a: d106 bne.n 8002b6a <HAL_RCC_OscConfig+0x12e>
8002b5c: 4b83 ldr r3, [pc, #524] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002b5e: 681b ldr r3, [r3, #0]
8002b60: 4a82 ldr r2, [pc, #520] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002b62: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8002b66: 6013 str r3, [r2, #0]
8002b68: e036 b.n 8002bd8 <HAL_RCC_OscConfig+0x19c>
8002b6a: f507 7300 add.w r3, r7, #512 ; 0x200
8002b6e: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002b72: 681b ldr r3, [r3, #0]
8002b74: 685b ldr r3, [r3, #4]
8002b76: 2b00 cmp r3, #0
8002b78: d10c bne.n 8002b94 <HAL_RCC_OscConfig+0x158>
8002b7a: 4b7c ldr r3, [pc, #496] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002b7c: 681b ldr r3, [r3, #0]
8002b7e: 4a7b ldr r2, [pc, #492] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002b80: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8002b84: 6013 str r3, [r2, #0]
8002b86: 4b79 ldr r3, [pc, #484] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002b88: 681b ldr r3, [r3, #0]
8002b8a: 4a78 ldr r2, [pc, #480] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002b8c: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8002b90: 6013 str r3, [r2, #0]
8002b92: e021 b.n 8002bd8 <HAL_RCC_OscConfig+0x19c>
8002b94: f507 7300 add.w r3, r7, #512 ; 0x200
8002b98: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002b9c: 681b ldr r3, [r3, #0]
8002b9e: 685b ldr r3, [r3, #4]
8002ba0: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8002ba4: d10c bne.n 8002bc0 <HAL_RCC_OscConfig+0x184>
8002ba6: 4b71 ldr r3, [pc, #452] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002ba8: 681b ldr r3, [r3, #0]
8002baa: 4a70 ldr r2, [pc, #448] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002bac: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8002bb0: 6013 str r3, [r2, #0]
8002bb2: 4b6e ldr r3, [pc, #440] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002bb4: 681b ldr r3, [r3, #0]
8002bb6: 4a6d ldr r2, [pc, #436] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002bb8: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8002bbc: 6013 str r3, [r2, #0]
8002bbe: e00b b.n 8002bd8 <HAL_RCC_OscConfig+0x19c>
8002bc0: 4b6a ldr r3, [pc, #424] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002bc2: 681b ldr r3, [r3, #0]
8002bc4: 4a69 ldr r2, [pc, #420] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002bc6: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8002bca: 6013 str r3, [r2, #0]
8002bcc: 4b67 ldr r3, [pc, #412] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002bce: 681b ldr r3, [r3, #0]
8002bd0: 4a66 ldr r2, [pc, #408] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002bd2: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8002bd6: 6013 str r3, [r2, #0]
#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
/* Configure the HSE predivision factor --------------------------------*/
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
8002bd8: 4b64 ldr r3, [pc, #400] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002bda: 6adb ldr r3, [r3, #44] ; 0x2c
8002bdc: f023 020f bic.w r2, r3, #15
8002be0: f507 7300 add.w r3, r7, #512 ; 0x200
8002be4: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002be8: 681b ldr r3, [r3, #0]
8002bea: 689b ldr r3, [r3, #8]
8002bec: 495f ldr r1, [pc, #380] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002bee: 4313 orrs r3, r2
8002bf0: 62cb str r3, [r1, #44] ; 0x2c
#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8002bf2: f507 7300 add.w r3, r7, #512 ; 0x200
8002bf6: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002bfa: 681b ldr r3, [r3, #0]
8002bfc: 685b ldr r3, [r3, #4]
8002bfe: 2b00 cmp r3, #0
8002c00: d059 beq.n 8002cb6 <HAL_RCC_OscConfig+0x27a>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002c02: f7ff f843 bl 8001c8c <HAL_GetTick>
8002c06: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8002c0a: e00a b.n 8002c22 <HAL_RCC_OscConfig+0x1e6>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8002c0c: f7ff f83e bl 8001c8c <HAL_GetTick>
8002c10: 4602 mov r2, r0
8002c12: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
8002c16: 1ad3 subs r3, r2, r3
8002c18: 2b64 cmp r3, #100 ; 0x64
8002c1a: d902 bls.n 8002c22 <HAL_RCC_OscConfig+0x1e6>
{
return HAL_TIMEOUT;
8002c1c: 2303 movs r3, #3
8002c1e: f000 bf43 b.w 8003aa8 <HAL_RCC_OscConfig+0x106c>
8002c22: f44f 3300 mov.w r3, #131072 ; 0x20000
8002c26: f8c7 31d0 str.w r3, [r7, #464] ; 0x1d0
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002c2a: f8d7 31d0 ldr.w r3, [r7, #464] ; 0x1d0
8002c2e: fa93 f3a3 rbit r3, r3
8002c32: f8c7 31cc str.w r3, [r7, #460] ; 0x1cc
return result;
8002c36: f8d7 31cc ldr.w r3, [r7, #460] ; 0x1cc
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8002c3a: fab3 f383 clz r3, r3
8002c3e: b2db uxtb r3, r3
8002c40: 095b lsrs r3, r3, #5
8002c42: b2db uxtb r3, r3
8002c44: f043 0301 orr.w r3, r3, #1
8002c48: b2db uxtb r3, r3
8002c4a: 2b01 cmp r3, #1
8002c4c: d102 bne.n 8002c54 <HAL_RCC_OscConfig+0x218>
8002c4e: 4b47 ldr r3, [pc, #284] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002c50: 681b ldr r3, [r3, #0]
8002c52: e015 b.n 8002c80 <HAL_RCC_OscConfig+0x244>
8002c54: f44f 3300 mov.w r3, #131072 ; 0x20000
8002c58: f8c7 31c8 str.w r3, [r7, #456] ; 0x1c8
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002c5c: f8d7 31c8 ldr.w r3, [r7, #456] ; 0x1c8
8002c60: fa93 f3a3 rbit r3, r3
8002c64: f8c7 31c4 str.w r3, [r7, #452] ; 0x1c4
8002c68: f44f 3300 mov.w r3, #131072 ; 0x20000
8002c6c: f8c7 31c0 str.w r3, [r7, #448] ; 0x1c0
8002c70: f8d7 31c0 ldr.w r3, [r7, #448] ; 0x1c0
8002c74: fa93 f3a3 rbit r3, r3
8002c78: f8c7 31bc str.w r3, [r7, #444] ; 0x1bc
8002c7c: 4b3b ldr r3, [pc, #236] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002c7e: 6a5b ldr r3, [r3, #36] ; 0x24
8002c80: f44f 3200 mov.w r2, #131072 ; 0x20000
8002c84: f8c7 21b8 str.w r2, [r7, #440] ; 0x1b8
8002c88: f8d7 21b8 ldr.w r2, [r7, #440] ; 0x1b8
8002c8c: fa92 f2a2 rbit r2, r2
8002c90: f8c7 21b4 str.w r2, [r7, #436] ; 0x1b4
return result;
8002c94: f8d7 21b4 ldr.w r2, [r7, #436] ; 0x1b4
8002c98: fab2 f282 clz r2, r2
8002c9c: b2d2 uxtb r2, r2
8002c9e: f042 0220 orr.w r2, r2, #32
8002ca2: b2d2 uxtb r2, r2
8002ca4: f002 021f and.w r2, r2, #31
8002ca8: 2101 movs r1, #1
8002caa: fa01 f202 lsl.w r2, r1, r2
8002cae: 4013 ands r3, r2
8002cb0: 2b00 cmp r3, #0
8002cb2: d0ab beq.n 8002c0c <HAL_RCC_OscConfig+0x1d0>
8002cb4: e05d b.n 8002d72 <HAL_RCC_OscConfig+0x336>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002cb6: f7fe ffe9 bl 8001c8c <HAL_GetTick>
8002cba: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8002cbe: e00a b.n 8002cd6 <HAL_RCC_OscConfig+0x29a>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8002cc0: f7fe ffe4 bl 8001c8c <HAL_GetTick>
8002cc4: 4602 mov r2, r0
8002cc6: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
8002cca: 1ad3 subs r3, r2, r3
8002ccc: 2b64 cmp r3, #100 ; 0x64
8002cce: d902 bls.n 8002cd6 <HAL_RCC_OscConfig+0x29a>
{
return HAL_TIMEOUT;
8002cd0: 2303 movs r3, #3
8002cd2: f000 bee9 b.w 8003aa8 <HAL_RCC_OscConfig+0x106c>
8002cd6: f44f 3300 mov.w r3, #131072 ; 0x20000
8002cda: f8c7 31b0 str.w r3, [r7, #432] ; 0x1b0
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002cde: f8d7 31b0 ldr.w r3, [r7, #432] ; 0x1b0
8002ce2: fa93 f3a3 rbit r3, r3
8002ce6: f8c7 31ac str.w r3, [r7, #428] ; 0x1ac
return result;
8002cea: f8d7 31ac ldr.w r3, [r7, #428] ; 0x1ac
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8002cee: fab3 f383 clz r3, r3
8002cf2: b2db uxtb r3, r3
8002cf4: 095b lsrs r3, r3, #5
8002cf6: b2db uxtb r3, r3
8002cf8: f043 0301 orr.w r3, r3, #1
8002cfc: b2db uxtb r3, r3
8002cfe: 2b01 cmp r3, #1
8002d00: d102 bne.n 8002d08 <HAL_RCC_OscConfig+0x2cc>
8002d02: 4b1a ldr r3, [pc, #104] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002d04: 681b ldr r3, [r3, #0]
8002d06: e015 b.n 8002d34 <HAL_RCC_OscConfig+0x2f8>
8002d08: f44f 3300 mov.w r3, #131072 ; 0x20000
8002d0c: f8c7 31a8 str.w r3, [r7, #424] ; 0x1a8
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002d10: f8d7 31a8 ldr.w r3, [r7, #424] ; 0x1a8
8002d14: fa93 f3a3 rbit r3, r3
8002d18: f8c7 31a4 str.w r3, [r7, #420] ; 0x1a4
8002d1c: f44f 3300 mov.w r3, #131072 ; 0x20000
8002d20: f8c7 31a0 str.w r3, [r7, #416] ; 0x1a0
8002d24: f8d7 31a0 ldr.w r3, [r7, #416] ; 0x1a0
8002d28: fa93 f3a3 rbit r3, r3
8002d2c: f8c7 319c str.w r3, [r7, #412] ; 0x19c
8002d30: 4b0e ldr r3, [pc, #56] ; (8002d6c <HAL_RCC_OscConfig+0x330>)
8002d32: 6a5b ldr r3, [r3, #36] ; 0x24
8002d34: f44f 3200 mov.w r2, #131072 ; 0x20000
8002d38: f8c7 2198 str.w r2, [r7, #408] ; 0x198
8002d3c: f8d7 2198 ldr.w r2, [r7, #408] ; 0x198
8002d40: fa92 f2a2 rbit r2, r2
8002d44: f8c7 2194 str.w r2, [r7, #404] ; 0x194
return result;
8002d48: f8d7 2194 ldr.w r2, [r7, #404] ; 0x194
8002d4c: fab2 f282 clz r2, r2
8002d50: b2d2 uxtb r2, r2
8002d52: f042 0220 orr.w r2, r2, #32
8002d56: b2d2 uxtb r2, r2
8002d58: f002 021f and.w r2, r2, #31
8002d5c: 2101 movs r1, #1
8002d5e: fa01 f202 lsl.w r2, r1, r2
8002d62: 4013 ands r3, r2
8002d64: 2b00 cmp r3, #0
8002d66: d1ab bne.n 8002cc0 <HAL_RCC_OscConfig+0x284>
8002d68: e003 b.n 8002d72 <HAL_RCC_OscConfig+0x336>
8002d6a: bf00 nop
8002d6c: 40021000 .word 0x40021000
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8002d70: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8002d72: f507 7300 add.w r3, r7, #512 ; 0x200
8002d76: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002d7a: 681b ldr r3, [r3, #0]
8002d7c: 681b ldr r3, [r3, #0]
8002d7e: f003 0302 and.w r3, r3, #2
8002d82: 2b00 cmp r3, #0
8002d84: f000 817d beq.w 8003082 <HAL_RCC_OscConfig+0x646>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8002d88: 4ba6 ldr r3, [pc, #664] ; (8003024 <HAL_RCC_OscConfig+0x5e8>)
8002d8a: 685b ldr r3, [r3, #4]
8002d8c: f003 030c and.w r3, r3, #12
8002d90: 2b00 cmp r3, #0
8002d92: d00b beq.n 8002dac <HAL_RCC_OscConfig+0x370>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
8002d94: 4ba3 ldr r3, [pc, #652] ; (8003024 <HAL_RCC_OscConfig+0x5e8>)
8002d96: 685b ldr r3, [r3, #4]
8002d98: f003 030c and.w r3, r3, #12
8002d9c: 2b08 cmp r3, #8
8002d9e: d172 bne.n 8002e86 <HAL_RCC_OscConfig+0x44a>
8002da0: 4ba0 ldr r3, [pc, #640] ; (8003024 <HAL_RCC_OscConfig+0x5e8>)
8002da2: 685b ldr r3, [r3, #4]
8002da4: f403 3380 and.w r3, r3, #65536 ; 0x10000
8002da8: 2b00 cmp r3, #0
8002daa: d16c bne.n 8002e86 <HAL_RCC_OscConfig+0x44a>
8002dac: 2302 movs r3, #2
8002dae: f8c7 3190 str.w r3, [r7, #400] ; 0x190
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002db2: f8d7 3190 ldr.w r3, [r7, #400] ; 0x190
8002db6: fa93 f3a3 rbit r3, r3
8002dba: f8c7 318c str.w r3, [r7, #396] ; 0x18c
return result;
8002dbe: f8d7 318c ldr.w r3, [r7, #396] ; 0x18c
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8002dc2: fab3 f383 clz r3, r3
8002dc6: b2db uxtb r3, r3
8002dc8: 095b lsrs r3, r3, #5
8002dca: b2db uxtb r3, r3
8002dcc: f043 0301 orr.w r3, r3, #1
8002dd0: b2db uxtb r3, r3
8002dd2: 2b01 cmp r3, #1
8002dd4: d102 bne.n 8002ddc <HAL_RCC_OscConfig+0x3a0>
8002dd6: 4b93 ldr r3, [pc, #588] ; (8003024 <HAL_RCC_OscConfig+0x5e8>)
8002dd8: 681b ldr r3, [r3, #0]
8002dda: e013 b.n 8002e04 <HAL_RCC_OscConfig+0x3c8>
8002ddc: 2302 movs r3, #2
8002dde: f8c7 3188 str.w r3, [r7, #392] ; 0x188
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002de2: f8d7 3188 ldr.w r3, [r7, #392] ; 0x188
8002de6: fa93 f3a3 rbit r3, r3
8002dea: f8c7 3184 str.w r3, [r7, #388] ; 0x184
8002dee: 2302 movs r3, #2
8002df0: f8c7 3180 str.w r3, [r7, #384] ; 0x180
8002df4: f8d7 3180 ldr.w r3, [r7, #384] ; 0x180
8002df8: fa93 f3a3 rbit r3, r3
8002dfc: f8c7 317c str.w r3, [r7, #380] ; 0x17c
8002e00: 4b88 ldr r3, [pc, #544] ; (8003024 <HAL_RCC_OscConfig+0x5e8>)
8002e02: 6a5b ldr r3, [r3, #36] ; 0x24
8002e04: 2202 movs r2, #2
8002e06: f8c7 2178 str.w r2, [r7, #376] ; 0x178
8002e0a: f8d7 2178 ldr.w r2, [r7, #376] ; 0x178
8002e0e: fa92 f2a2 rbit r2, r2
8002e12: f8c7 2174 str.w r2, [r7, #372] ; 0x174
return result;
8002e16: f8d7 2174 ldr.w r2, [r7, #372] ; 0x174
8002e1a: fab2 f282 clz r2, r2
8002e1e: b2d2 uxtb r2, r2
8002e20: f042 0220 orr.w r2, r2, #32
8002e24: b2d2 uxtb r2, r2
8002e26: f002 021f and.w r2, r2, #31
8002e2a: 2101 movs r1, #1
8002e2c: fa01 f202 lsl.w r2, r1, r2
8002e30: 4013 ands r3, r2
8002e32: 2b00 cmp r3, #0
8002e34: d00a beq.n 8002e4c <HAL_RCC_OscConfig+0x410>
8002e36: f507 7300 add.w r3, r7, #512 ; 0x200
8002e3a: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002e3e: 681b ldr r3, [r3, #0]
8002e40: 691b ldr r3, [r3, #16]
8002e42: 2b01 cmp r3, #1
8002e44: d002 beq.n 8002e4c <HAL_RCC_OscConfig+0x410>
{
return HAL_ERROR;
8002e46: 2301 movs r3, #1
8002e48: f000 be2e b.w 8003aa8 <HAL_RCC_OscConfig+0x106c>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8002e4c: 4b75 ldr r3, [pc, #468] ; (8003024 <HAL_RCC_OscConfig+0x5e8>)
8002e4e: 681b ldr r3, [r3, #0]
8002e50: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8002e54: f507 7300 add.w r3, r7, #512 ; 0x200
8002e58: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002e5c: 681b ldr r3, [r3, #0]
8002e5e: 695b ldr r3, [r3, #20]
8002e60: 21f8 movs r1, #248 ; 0xf8
8002e62: f8c7 1170 str.w r1, [r7, #368] ; 0x170
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002e66: f8d7 1170 ldr.w r1, [r7, #368] ; 0x170
8002e6a: fa91 f1a1 rbit r1, r1
8002e6e: f8c7 116c str.w r1, [r7, #364] ; 0x16c
return result;
8002e72: f8d7 116c ldr.w r1, [r7, #364] ; 0x16c
8002e76: fab1 f181 clz r1, r1
8002e7a: b2c9 uxtb r1, r1
8002e7c: 408b lsls r3, r1
8002e7e: 4969 ldr r1, [pc, #420] ; (8003024 <HAL_RCC_OscConfig+0x5e8>)
8002e80: 4313 orrs r3, r2
8002e82: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8002e84: e0fd b.n 8003082 <HAL_RCC_OscConfig+0x646>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8002e86: f507 7300 add.w r3, r7, #512 ; 0x200
8002e8a: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002e8e: 681b ldr r3, [r3, #0]
8002e90: 691b ldr r3, [r3, #16]
8002e92: 2b00 cmp r3, #0
8002e94: f000 8088 beq.w 8002fa8 <HAL_RCC_OscConfig+0x56c>
8002e98: 2301 movs r3, #1
8002e9a: f8c7 3168 str.w r3, [r7, #360] ; 0x168
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002e9e: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002ea2: fa93 f3a3 rbit r3, r3
8002ea6: f8c7 3164 str.w r3, [r7, #356] ; 0x164
return result;
8002eaa: f8d7 3164 ldr.w r3, [r7, #356] ; 0x164
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8002eae: fab3 f383 clz r3, r3
8002eb2: b2db uxtb r3, r3
8002eb4: f103 5384 add.w r3, r3, #276824064 ; 0x10800000
8002eb8: f503 1384 add.w r3, r3, #1081344 ; 0x108000
8002ebc: 009b lsls r3, r3, #2
8002ebe: 461a mov r2, r3
8002ec0: 2301 movs r3, #1
8002ec2: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002ec4: f7fe fee2 bl 8001c8c <HAL_GetTick>
8002ec8: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002ecc: e00a b.n 8002ee4 <HAL_RCC_OscConfig+0x4a8>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8002ece: f7fe fedd bl 8001c8c <HAL_GetTick>
8002ed2: 4602 mov r2, r0
8002ed4: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
8002ed8: 1ad3 subs r3, r2, r3
8002eda: 2b02 cmp r3, #2
8002edc: d902 bls.n 8002ee4 <HAL_RCC_OscConfig+0x4a8>
{
return HAL_TIMEOUT;
8002ede: 2303 movs r3, #3
8002ee0: f000 bde2 b.w 8003aa8 <HAL_RCC_OscConfig+0x106c>
8002ee4: 2302 movs r3, #2
8002ee6: f8c7 3160 str.w r3, [r7, #352] ; 0x160
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002eea: f8d7 3160 ldr.w r3, [r7, #352] ; 0x160
8002eee: fa93 f3a3 rbit r3, r3
8002ef2: f8c7 315c str.w r3, [r7, #348] ; 0x15c
return result;
8002ef6: f8d7 315c ldr.w r3, [r7, #348] ; 0x15c
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002efa: fab3 f383 clz r3, r3
8002efe: b2db uxtb r3, r3
8002f00: 095b lsrs r3, r3, #5
8002f02: b2db uxtb r3, r3
8002f04: f043 0301 orr.w r3, r3, #1
8002f08: b2db uxtb r3, r3
8002f0a: 2b01 cmp r3, #1
8002f0c: d102 bne.n 8002f14 <HAL_RCC_OscConfig+0x4d8>
8002f0e: 4b45 ldr r3, [pc, #276] ; (8003024 <HAL_RCC_OscConfig+0x5e8>)
8002f10: 681b ldr r3, [r3, #0]
8002f12: e013 b.n 8002f3c <HAL_RCC_OscConfig+0x500>
8002f14: 2302 movs r3, #2
8002f16: f8c7 3158 str.w r3, [r7, #344] ; 0x158
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002f1a: f8d7 3158 ldr.w r3, [r7, #344] ; 0x158
8002f1e: fa93 f3a3 rbit r3, r3
8002f22: f8c7 3154 str.w r3, [r7, #340] ; 0x154
8002f26: 2302 movs r3, #2
8002f28: f8c7 3150 str.w r3, [r7, #336] ; 0x150
8002f2c: f8d7 3150 ldr.w r3, [r7, #336] ; 0x150
8002f30: fa93 f3a3 rbit r3, r3
8002f34: f8c7 314c str.w r3, [r7, #332] ; 0x14c
8002f38: 4b3a ldr r3, [pc, #232] ; (8003024 <HAL_RCC_OscConfig+0x5e8>)
8002f3a: 6a5b ldr r3, [r3, #36] ; 0x24
8002f3c: 2202 movs r2, #2
8002f3e: f8c7 2148 str.w r2, [r7, #328] ; 0x148
8002f42: f8d7 2148 ldr.w r2, [r7, #328] ; 0x148
8002f46: fa92 f2a2 rbit r2, r2
8002f4a: f8c7 2144 str.w r2, [r7, #324] ; 0x144
return result;
8002f4e: f8d7 2144 ldr.w r2, [r7, #324] ; 0x144
8002f52: fab2 f282 clz r2, r2
8002f56: b2d2 uxtb r2, r2
8002f58: f042 0220 orr.w r2, r2, #32
8002f5c: b2d2 uxtb r2, r2
8002f5e: f002 021f and.w r2, r2, #31
8002f62: 2101 movs r1, #1
8002f64: fa01 f202 lsl.w r2, r1, r2
8002f68: 4013 ands r3, r2
8002f6a: 2b00 cmp r3, #0
8002f6c: d0af beq.n 8002ece <HAL_RCC_OscConfig+0x492>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8002f6e: 4b2d ldr r3, [pc, #180] ; (8003024 <HAL_RCC_OscConfig+0x5e8>)
8002f70: 681b ldr r3, [r3, #0]
8002f72: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8002f76: f507 7300 add.w r3, r7, #512 ; 0x200
8002f7a: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002f7e: 681b ldr r3, [r3, #0]
8002f80: 695b ldr r3, [r3, #20]
8002f82: 21f8 movs r1, #248 ; 0xf8
8002f84: f8c7 1140 str.w r1, [r7, #320] ; 0x140
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002f88: f8d7 1140 ldr.w r1, [r7, #320] ; 0x140
8002f8c: fa91 f1a1 rbit r1, r1
8002f90: f8c7 113c str.w r1, [r7, #316] ; 0x13c
return result;
8002f94: f8d7 113c ldr.w r1, [r7, #316] ; 0x13c
8002f98: fab1 f181 clz r1, r1
8002f9c: b2c9 uxtb r1, r1
8002f9e: 408b lsls r3, r1
8002fa0: 4920 ldr r1, [pc, #128] ; (8003024 <HAL_RCC_OscConfig+0x5e8>)
8002fa2: 4313 orrs r3, r2
8002fa4: 600b str r3, [r1, #0]
8002fa6: e06c b.n 8003082 <HAL_RCC_OscConfig+0x646>
8002fa8: 2301 movs r3, #1
8002faa: f8c7 3138 str.w r3, [r7, #312] ; 0x138
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002fae: f8d7 3138 ldr.w r3, [r7, #312] ; 0x138
8002fb2: fa93 f3a3 rbit r3, r3
8002fb6: f8c7 3134 str.w r3, [r7, #308] ; 0x134
return result;
8002fba: f8d7 3134 ldr.w r3, [r7, #308] ; 0x134
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8002fbe: fab3 f383 clz r3, r3
8002fc2: b2db uxtb r3, r3
8002fc4: f103 5384 add.w r3, r3, #276824064 ; 0x10800000
8002fc8: f503 1384 add.w r3, r3, #1081344 ; 0x108000
8002fcc: 009b lsls r3, r3, #2
8002fce: 461a mov r2, r3
8002fd0: 2300 movs r3, #0
8002fd2: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002fd4: f7fe fe5a bl 8001c8c <HAL_GetTick>
8002fd8: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8002fdc: e00a b.n 8002ff4 <HAL_RCC_OscConfig+0x5b8>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8002fde: f7fe fe55 bl 8001c8c <HAL_GetTick>
8002fe2: 4602 mov r2, r0
8002fe4: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
8002fe8: 1ad3 subs r3, r2, r3
8002fea: 2b02 cmp r3, #2
8002fec: d902 bls.n 8002ff4 <HAL_RCC_OscConfig+0x5b8>
{
return HAL_TIMEOUT;
8002fee: 2303 movs r3, #3
8002ff0: f000 bd5a b.w 8003aa8 <HAL_RCC_OscConfig+0x106c>
8002ff4: 2302 movs r3, #2
8002ff6: f8c7 3130 str.w r3, [r7, #304] ; 0x130
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002ffa: f8d7 3130 ldr.w r3, [r7, #304] ; 0x130
8002ffe: fa93 f3a3 rbit r3, r3
8003002: f8c7 312c str.w r3, [r7, #300] ; 0x12c
return result;
8003006: f8d7 312c ldr.w r3, [r7, #300] ; 0x12c
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
800300a: fab3 f383 clz r3, r3
800300e: b2db uxtb r3, r3
8003010: 095b lsrs r3, r3, #5
8003012: b2db uxtb r3, r3
8003014: f043 0301 orr.w r3, r3, #1
8003018: b2db uxtb r3, r3
800301a: 2b01 cmp r3, #1
800301c: d104 bne.n 8003028 <HAL_RCC_OscConfig+0x5ec>
800301e: 4b01 ldr r3, [pc, #4] ; (8003024 <HAL_RCC_OscConfig+0x5e8>)
8003020: 681b ldr r3, [r3, #0]
8003022: e015 b.n 8003050 <HAL_RCC_OscConfig+0x614>
8003024: 40021000 .word 0x40021000
8003028: 2302 movs r3, #2
800302a: f8c7 3128 str.w r3, [r7, #296] ; 0x128
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800302e: f8d7 3128 ldr.w r3, [r7, #296] ; 0x128
8003032: fa93 f3a3 rbit r3, r3
8003036: f8c7 3124 str.w r3, [r7, #292] ; 0x124
800303a: 2302 movs r3, #2
800303c: f8c7 3120 str.w r3, [r7, #288] ; 0x120
8003040: f8d7 3120 ldr.w r3, [r7, #288] ; 0x120
8003044: fa93 f3a3 rbit r3, r3
8003048: f8c7 311c str.w r3, [r7, #284] ; 0x11c
800304c: 4bc8 ldr r3, [pc, #800] ; (8003370 <HAL_RCC_OscConfig+0x934>)
800304e: 6a5b ldr r3, [r3, #36] ; 0x24
8003050: 2202 movs r2, #2
8003052: f8c7 2118 str.w r2, [r7, #280] ; 0x118
8003056: f8d7 2118 ldr.w r2, [r7, #280] ; 0x118
800305a: fa92 f2a2 rbit r2, r2
800305e: f8c7 2114 str.w r2, [r7, #276] ; 0x114
return result;
8003062: f8d7 2114 ldr.w r2, [r7, #276] ; 0x114
8003066: fab2 f282 clz r2, r2
800306a: b2d2 uxtb r2, r2
800306c: f042 0220 orr.w r2, r2, #32
8003070: b2d2 uxtb r2, r2
8003072: f002 021f and.w r2, r2, #31
8003076: 2101 movs r1, #1
8003078: fa01 f202 lsl.w r2, r1, r2
800307c: 4013 ands r3, r2
800307e: 2b00 cmp r3, #0
8003080: d1ad bne.n 8002fde <HAL_RCC_OscConfig+0x5a2>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8003082: f507 7300 add.w r3, r7, #512 ; 0x200
8003086: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
800308a: 681b ldr r3, [r3, #0]
800308c: 681b ldr r3, [r3, #0]
800308e: f003 0308 and.w r3, r3, #8
8003092: 2b00 cmp r3, #0
8003094: f000 8110 beq.w 80032b8 <HAL_RCC_OscConfig+0x87c>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8003098: f507 7300 add.w r3, r7, #512 ; 0x200
800309c: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
80030a0: 681b ldr r3, [r3, #0]
80030a2: 699b ldr r3, [r3, #24]
80030a4: 2b00 cmp r3, #0
80030a6: d079 beq.n 800319c <HAL_RCC_OscConfig+0x760>
80030a8: 2301 movs r3, #1
80030aa: f8c7 3110 str.w r3, [r7, #272] ; 0x110
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80030ae: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110
80030b2: fa93 f3a3 rbit r3, r3
80030b6: f8c7 310c str.w r3, [r7, #268] ; 0x10c
return result;
80030ba: f8d7 310c ldr.w r3, [r7, #268] ; 0x10c
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80030be: fab3 f383 clz r3, r3
80030c2: b2db uxtb r3, r3
80030c4: 461a mov r2, r3
80030c6: 4bab ldr r3, [pc, #684] ; (8003374 <HAL_RCC_OscConfig+0x938>)
80030c8: 4413 add r3, r2
80030ca: 009b lsls r3, r3, #2
80030cc: 461a mov r2, r3
80030ce: 2301 movs r3, #1
80030d0: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80030d2: f7fe fddb bl 8001c8c <HAL_GetTick>
80030d6: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80030da: e00a b.n 80030f2 <HAL_RCC_OscConfig+0x6b6>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
80030dc: f7fe fdd6 bl 8001c8c <HAL_GetTick>
80030e0: 4602 mov r2, r0
80030e2: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
80030e6: 1ad3 subs r3, r2, r3
80030e8: 2b02 cmp r3, #2
80030ea: d902 bls.n 80030f2 <HAL_RCC_OscConfig+0x6b6>
{
return HAL_TIMEOUT;
80030ec: 2303 movs r3, #3
80030ee: f000 bcdb b.w 8003aa8 <HAL_RCC_OscConfig+0x106c>
80030f2: 2302 movs r3, #2
80030f4: f8c7 3108 str.w r3, [r7, #264] ; 0x108
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80030f8: f8d7 3108 ldr.w r3, [r7, #264] ; 0x108
80030fc: fa93 f3a3 rbit r3, r3
8003100: f8c7 3104 str.w r3, [r7, #260] ; 0x104
8003104: f507 7300 add.w r3, r7, #512 ; 0x200
8003108: f5a3 7380 sub.w r3, r3, #256 ; 0x100
800310c: 2202 movs r2, #2
800310e: 601a str r2, [r3, #0]
8003110: f507 7300 add.w r3, r7, #512 ; 0x200
8003114: f5a3 7380 sub.w r3, r3, #256 ; 0x100
8003118: 681b ldr r3, [r3, #0]
800311a: fa93 f2a3 rbit r2, r3
800311e: f507 7300 add.w r3, r7, #512 ; 0x200
8003122: f5a3 7382 sub.w r3, r3, #260 ; 0x104
8003126: 601a str r2, [r3, #0]
8003128: f507 7300 add.w r3, r7, #512 ; 0x200
800312c: f5a3 7384 sub.w r3, r3, #264 ; 0x108
8003130: 2202 movs r2, #2
8003132: 601a str r2, [r3, #0]
8003134: f507 7300 add.w r3, r7, #512 ; 0x200
8003138: f5a3 7384 sub.w r3, r3, #264 ; 0x108
800313c: 681b ldr r3, [r3, #0]
800313e: fa93 f2a3 rbit r2, r3
8003142: f507 7300 add.w r3, r7, #512 ; 0x200
8003146: f5a3 7386 sub.w r3, r3, #268 ; 0x10c
800314a: 601a str r2, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800314c: 4b88 ldr r3, [pc, #544] ; (8003370 <HAL_RCC_OscConfig+0x934>)
800314e: 6a5a ldr r2, [r3, #36] ; 0x24
8003150: f507 7300 add.w r3, r7, #512 ; 0x200
8003154: f5a3 7388 sub.w r3, r3, #272 ; 0x110
8003158: 2102 movs r1, #2
800315a: 6019 str r1, [r3, #0]
800315c: f507 7300 add.w r3, r7, #512 ; 0x200
8003160: f5a3 7388 sub.w r3, r3, #272 ; 0x110
8003164: 681b ldr r3, [r3, #0]
8003166: fa93 f1a3 rbit r1, r3
800316a: f507 7300 add.w r3, r7, #512 ; 0x200
800316e: f5a3 738a sub.w r3, r3, #276 ; 0x114
8003172: 6019 str r1, [r3, #0]
return result;
8003174: f507 7300 add.w r3, r7, #512 ; 0x200
8003178: f5a3 738a sub.w r3, r3, #276 ; 0x114
800317c: 681b ldr r3, [r3, #0]
800317e: fab3 f383 clz r3, r3
8003182: b2db uxtb r3, r3
8003184: f043 0360 orr.w r3, r3, #96 ; 0x60
8003188: b2db uxtb r3, r3
800318a: f003 031f and.w r3, r3, #31
800318e: 2101 movs r1, #1
8003190: fa01 f303 lsl.w r3, r1, r3
8003194: 4013 ands r3, r2
8003196: 2b00 cmp r3, #0
8003198: d0a0 beq.n 80030dc <HAL_RCC_OscConfig+0x6a0>
800319a: e08d b.n 80032b8 <HAL_RCC_OscConfig+0x87c>
800319c: f507 7300 add.w r3, r7, #512 ; 0x200
80031a0: f5a3 738c sub.w r3, r3, #280 ; 0x118
80031a4: 2201 movs r2, #1
80031a6: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80031a8: f507 7300 add.w r3, r7, #512 ; 0x200
80031ac: f5a3 738c sub.w r3, r3, #280 ; 0x118
80031b0: 681b ldr r3, [r3, #0]
80031b2: fa93 f2a3 rbit r2, r3
80031b6: f507 7300 add.w r3, r7, #512 ; 0x200
80031ba: f5a3 738e sub.w r3, r3, #284 ; 0x11c
80031be: 601a str r2, [r3, #0]
return result;
80031c0: f507 7300 add.w r3, r7, #512 ; 0x200
80031c4: f5a3 738e sub.w r3, r3, #284 ; 0x11c
80031c8: 681b ldr r3, [r3, #0]
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80031ca: fab3 f383 clz r3, r3
80031ce: b2db uxtb r3, r3
80031d0: 461a mov r2, r3
80031d2: 4b68 ldr r3, [pc, #416] ; (8003374 <HAL_RCC_OscConfig+0x938>)
80031d4: 4413 add r3, r2
80031d6: 009b lsls r3, r3, #2
80031d8: 461a mov r2, r3
80031da: 2300 movs r3, #0
80031dc: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80031de: f7fe fd55 bl 8001c8c <HAL_GetTick>
80031e2: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80031e6: e00a b.n 80031fe <HAL_RCC_OscConfig+0x7c2>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
80031e8: f7fe fd50 bl 8001c8c <HAL_GetTick>
80031ec: 4602 mov r2, r0
80031ee: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
80031f2: 1ad3 subs r3, r2, r3
80031f4: 2b02 cmp r3, #2
80031f6: d902 bls.n 80031fe <HAL_RCC_OscConfig+0x7c2>
{
return HAL_TIMEOUT;
80031f8: 2303 movs r3, #3
80031fa: f000 bc55 b.w 8003aa8 <HAL_RCC_OscConfig+0x106c>
80031fe: f507 7300 add.w r3, r7, #512 ; 0x200
8003202: f5a3 7390 sub.w r3, r3, #288 ; 0x120
8003206: 2202 movs r2, #2
8003208: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800320a: f507 7300 add.w r3, r7, #512 ; 0x200
800320e: f5a3 7390 sub.w r3, r3, #288 ; 0x120
8003212: 681b ldr r3, [r3, #0]
8003214: fa93 f2a3 rbit r2, r3
8003218: f507 7300 add.w r3, r7, #512 ; 0x200
800321c: f5a3 7392 sub.w r3, r3, #292 ; 0x124
8003220: 601a str r2, [r3, #0]
8003222: f507 7300 add.w r3, r7, #512 ; 0x200
8003226: f5a3 7394 sub.w r3, r3, #296 ; 0x128
800322a: 2202 movs r2, #2
800322c: 601a str r2, [r3, #0]
800322e: f507 7300 add.w r3, r7, #512 ; 0x200
8003232: f5a3 7394 sub.w r3, r3, #296 ; 0x128
8003236: 681b ldr r3, [r3, #0]
8003238: fa93 f2a3 rbit r2, r3
800323c: f507 7300 add.w r3, r7, #512 ; 0x200
8003240: f5a3 7396 sub.w r3, r3, #300 ; 0x12c
8003244: 601a str r2, [r3, #0]
8003246: f507 7300 add.w r3, r7, #512 ; 0x200
800324a: f5a3 7398 sub.w r3, r3, #304 ; 0x130
800324e: 2202 movs r2, #2
8003250: 601a str r2, [r3, #0]
8003252: f507 7300 add.w r3, r7, #512 ; 0x200
8003256: f5a3 7398 sub.w r3, r3, #304 ; 0x130
800325a: 681b ldr r3, [r3, #0]
800325c: fa93 f2a3 rbit r2, r3
8003260: f507 7300 add.w r3, r7, #512 ; 0x200
8003264: f5a3 739a sub.w r3, r3, #308 ; 0x134
8003268: 601a str r2, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
800326a: 4b41 ldr r3, [pc, #260] ; (8003370 <HAL_RCC_OscConfig+0x934>)
800326c: 6a5a ldr r2, [r3, #36] ; 0x24
800326e: f507 7300 add.w r3, r7, #512 ; 0x200
8003272: f5a3 739c sub.w r3, r3, #312 ; 0x138
8003276: 2102 movs r1, #2
8003278: 6019 str r1, [r3, #0]
800327a: f507 7300 add.w r3, r7, #512 ; 0x200
800327e: f5a3 739c sub.w r3, r3, #312 ; 0x138
8003282: 681b ldr r3, [r3, #0]
8003284: fa93 f1a3 rbit r1, r3
8003288: f507 7300 add.w r3, r7, #512 ; 0x200
800328c: f5a3 739e sub.w r3, r3, #316 ; 0x13c
8003290: 6019 str r1, [r3, #0]
return result;
8003292: f507 7300 add.w r3, r7, #512 ; 0x200
8003296: f5a3 739e sub.w r3, r3, #316 ; 0x13c
800329a: 681b ldr r3, [r3, #0]
800329c: fab3 f383 clz r3, r3
80032a0: b2db uxtb r3, r3
80032a2: f043 0360 orr.w r3, r3, #96 ; 0x60
80032a6: b2db uxtb r3, r3
80032a8: f003 031f and.w r3, r3, #31
80032ac: 2101 movs r1, #1
80032ae: fa01 f303 lsl.w r3, r1, r3
80032b2: 4013 ands r3, r2
80032b4: 2b00 cmp r3, #0
80032b6: d197 bne.n 80031e8 <HAL_RCC_OscConfig+0x7ac>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
80032b8: f507 7300 add.w r3, r7, #512 ; 0x200
80032bc: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
80032c0: 681b ldr r3, [r3, #0]
80032c2: 681b ldr r3, [r3, #0]
80032c4: f003 0304 and.w r3, r3, #4
80032c8: 2b00 cmp r3, #0
80032ca: f000 81a1 beq.w 8003610 <HAL_RCC_OscConfig+0xbd4>
{
FlagStatus pwrclkchanged = RESET;
80032ce: 2300 movs r3, #0
80032d0: f887 31ff strb.w r3, [r7, #511] ; 0x1ff
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
80032d4: 4b26 ldr r3, [pc, #152] ; (8003370 <HAL_RCC_OscConfig+0x934>)
80032d6: 69db ldr r3, [r3, #28]
80032d8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80032dc: 2b00 cmp r3, #0
80032de: d116 bne.n 800330e <HAL_RCC_OscConfig+0x8d2>
{
__HAL_RCC_PWR_CLK_ENABLE();
80032e0: 4b23 ldr r3, [pc, #140] ; (8003370 <HAL_RCC_OscConfig+0x934>)
80032e2: 69db ldr r3, [r3, #28]
80032e4: 4a22 ldr r2, [pc, #136] ; (8003370 <HAL_RCC_OscConfig+0x934>)
80032e6: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
80032ea: 61d3 str r3, [r2, #28]
80032ec: 4b20 ldr r3, [pc, #128] ; (8003370 <HAL_RCC_OscConfig+0x934>)
80032ee: 69db ldr r3, [r3, #28]
80032f0: f003 5280 and.w r2, r3, #268435456 ; 0x10000000
80032f4: f507 7300 add.w r3, r7, #512 ; 0x200
80032f8: f5a3 73fc sub.w r3, r3, #504 ; 0x1f8
80032fc: 601a str r2, [r3, #0]
80032fe: f507 7300 add.w r3, r7, #512 ; 0x200
8003302: f5a3 73fc sub.w r3, r3, #504 ; 0x1f8
8003306: 681b ldr r3, [r3, #0]
pwrclkchanged = SET;
8003308: 2301 movs r3, #1
800330a: f887 31ff strb.w r3, [r7, #511] ; 0x1ff
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
800330e: 4b1a ldr r3, [pc, #104] ; (8003378 <HAL_RCC_OscConfig+0x93c>)
8003310: 681b ldr r3, [r3, #0]
8003312: f403 7380 and.w r3, r3, #256 ; 0x100
8003316: 2b00 cmp r3, #0
8003318: d11a bne.n 8003350 <HAL_RCC_OscConfig+0x914>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
800331a: 4b17 ldr r3, [pc, #92] ; (8003378 <HAL_RCC_OscConfig+0x93c>)
800331c: 681b ldr r3, [r3, #0]
800331e: 4a16 ldr r2, [pc, #88] ; (8003378 <HAL_RCC_OscConfig+0x93c>)
8003320: f443 7380 orr.w r3, r3, #256 ; 0x100
8003324: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8003326: f7fe fcb1 bl 8001c8c <HAL_GetTick>
800332a: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
800332e: e009 b.n 8003344 <HAL_RCC_OscConfig+0x908>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8003330: f7fe fcac bl 8001c8c <HAL_GetTick>
8003334: 4602 mov r2, r0
8003336: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
800333a: 1ad3 subs r3, r2, r3
800333c: 2b64 cmp r3, #100 ; 0x64
800333e: d901 bls.n 8003344 <HAL_RCC_OscConfig+0x908>
{
return HAL_TIMEOUT;
8003340: 2303 movs r3, #3
8003342: e3b1 b.n 8003aa8 <HAL_RCC_OscConfig+0x106c>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8003344: 4b0c ldr r3, [pc, #48] ; (8003378 <HAL_RCC_OscConfig+0x93c>)
8003346: 681b ldr r3, [r3, #0]
8003348: f403 7380 and.w r3, r3, #256 ; 0x100
800334c: 2b00 cmp r3, #0
800334e: d0ef beq.n 8003330 <HAL_RCC_OscConfig+0x8f4>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8003350: f507 7300 add.w r3, r7, #512 ; 0x200
8003354: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8003358: 681b ldr r3, [r3, #0]
800335a: 68db ldr r3, [r3, #12]
800335c: 2b01 cmp r3, #1
800335e: d10d bne.n 800337c <HAL_RCC_OscConfig+0x940>
8003360: 4b03 ldr r3, [pc, #12] ; (8003370 <HAL_RCC_OscConfig+0x934>)
8003362: 6a1b ldr r3, [r3, #32]
8003364: 4a02 ldr r2, [pc, #8] ; (8003370 <HAL_RCC_OscConfig+0x934>)
8003366: f043 0301 orr.w r3, r3, #1
800336a: 6213 str r3, [r2, #32]
800336c: e03c b.n 80033e8 <HAL_RCC_OscConfig+0x9ac>
800336e: bf00 nop
8003370: 40021000 .word 0x40021000
8003374: 10908120 .word 0x10908120
8003378: 40007000 .word 0x40007000
800337c: f507 7300 add.w r3, r7, #512 ; 0x200
8003380: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8003384: 681b ldr r3, [r3, #0]
8003386: 68db ldr r3, [r3, #12]
8003388: 2b00 cmp r3, #0
800338a: d10c bne.n 80033a6 <HAL_RCC_OscConfig+0x96a>
800338c: 4bc1 ldr r3, [pc, #772] ; (8003694 <HAL_RCC_OscConfig+0xc58>)
800338e: 6a1b ldr r3, [r3, #32]
8003390: 4ac0 ldr r2, [pc, #768] ; (8003694 <HAL_RCC_OscConfig+0xc58>)
8003392: f023 0301 bic.w r3, r3, #1
8003396: 6213 str r3, [r2, #32]
8003398: 4bbe ldr r3, [pc, #760] ; (8003694 <HAL_RCC_OscConfig+0xc58>)
800339a: 6a1b ldr r3, [r3, #32]
800339c: 4abd ldr r2, [pc, #756] ; (8003694 <HAL_RCC_OscConfig+0xc58>)
800339e: f023 0304 bic.w r3, r3, #4
80033a2: 6213 str r3, [r2, #32]
80033a4: e020 b.n 80033e8 <HAL_RCC_OscConfig+0x9ac>
80033a6: f507 7300 add.w r3, r7, #512 ; 0x200
80033aa: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
80033ae: 681b ldr r3, [r3, #0]
80033b0: 68db ldr r3, [r3, #12]
80033b2: 2b05 cmp r3, #5
80033b4: d10c bne.n 80033d0 <HAL_RCC_OscConfig+0x994>
80033b6: 4bb7 ldr r3, [pc, #732] ; (8003694 <HAL_RCC_OscConfig+0xc58>)
80033b8: 6a1b ldr r3, [r3, #32]
80033ba: 4ab6 ldr r2, [pc, #728] ; (8003694 <HAL_RCC_OscConfig+0xc58>)
80033bc: f043 0304 orr.w r3, r3, #4
80033c0: 6213 str r3, [r2, #32]
80033c2: 4bb4 ldr r3, [pc, #720] ; (8003694 <HAL_RCC_OscConfig+0xc58>)
80033c4: 6a1b ldr r3, [r3, #32]
80033c6: 4ab3 ldr r2, [pc, #716] ; (8003694 <HAL_RCC_OscConfig+0xc58>)
80033c8: f043 0301 orr.w r3, r3, #1
80033cc: 6213 str r3, [r2, #32]
80033ce: e00b b.n 80033e8 <HAL_RCC_OscConfig+0x9ac>
80033d0: 4bb0 ldr r3, [pc, #704] ; (8003694 <HAL_RCC_OscConfig+0xc58>)
80033d2: 6a1b ldr r3, [r3, #32]
80033d4: 4aaf ldr r2, [pc, #700] ; (8003694 <HAL_RCC_OscConfig+0xc58>)
80033d6: f023 0301 bic.w r3, r3, #1
80033da: 6213 str r3, [r2, #32]
80033dc: 4bad ldr r3, [pc, #692] ; (8003694 <HAL_RCC_OscConfig+0xc58>)
80033de: 6a1b ldr r3, [r3, #32]
80033e0: 4aac ldr r2, [pc, #688] ; (8003694 <HAL_RCC_OscConfig+0xc58>)
80033e2: f023 0304 bic.w r3, r3, #4
80033e6: 6213 str r3, [r2, #32]
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
80033e8: f507 7300 add.w r3, r7, #512 ; 0x200
80033ec: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
80033f0: 681b ldr r3, [r3, #0]
80033f2: 68db ldr r3, [r3, #12]
80033f4: 2b00 cmp r3, #0
80033f6: f000 8081 beq.w 80034fc <HAL_RCC_OscConfig+0xac0>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80033fa: f7fe fc47 bl 8001c8c <HAL_GetTick>
80033fe: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8003402: e00b b.n 800341c <HAL_RCC_OscConfig+0x9e0>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8003404: f7fe fc42 bl 8001c8c <HAL_GetTick>
8003408: 4602 mov r2, r0
800340a: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
800340e: 1ad3 subs r3, r2, r3
8003410: f241 3288 movw r2, #5000 ; 0x1388
8003414: 4293 cmp r3, r2
8003416: d901 bls.n 800341c <HAL_RCC_OscConfig+0x9e0>
{
return HAL_TIMEOUT;
8003418: 2303 movs r3, #3
800341a: e345 b.n 8003aa8 <HAL_RCC_OscConfig+0x106c>
800341c: f507 7300 add.w r3, r7, #512 ; 0x200
8003420: f5a3 73a0 sub.w r3, r3, #320 ; 0x140
8003424: 2202 movs r2, #2
8003426: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003428: f507 7300 add.w r3, r7, #512 ; 0x200
800342c: f5a3 73a0 sub.w r3, r3, #320 ; 0x140
8003430: 681b ldr r3, [r3, #0]
8003432: fa93 f2a3 rbit r2, r3
8003436: f507 7300 add.w r3, r7, #512 ; 0x200
800343a: f5a3 73a2 sub.w r3, r3, #324 ; 0x144
800343e: 601a str r2, [r3, #0]
8003440: f507 7300 add.w r3, r7, #512 ; 0x200
8003444: f5a3 73a4 sub.w r3, r3, #328 ; 0x148
8003448: 2202 movs r2, #2
800344a: 601a str r2, [r3, #0]
800344c: f507 7300 add.w r3, r7, #512 ; 0x200
8003450: f5a3 73a4 sub.w r3, r3, #328 ; 0x148
8003454: 681b ldr r3, [r3, #0]
8003456: fa93 f2a3 rbit r2, r3
800345a: f507 7300 add.w r3, r7, #512 ; 0x200
800345e: f5a3 73a6 sub.w r3, r3, #332 ; 0x14c
8003462: 601a str r2, [r3, #0]
return result;
8003464: f507 7300 add.w r3, r7, #512 ; 0x200
8003468: f5a3 73a6 sub.w r3, r3, #332 ; 0x14c
800346c: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800346e: fab3 f383 clz r3, r3
8003472: b2db uxtb r3, r3
8003474: 095b lsrs r3, r3, #5
8003476: b2db uxtb r3, r3
8003478: f043 0302 orr.w r3, r3, #2
800347c: b2db uxtb r3, r3
800347e: 2b02 cmp r3, #2
8003480: d102 bne.n 8003488 <HAL_RCC_OscConfig+0xa4c>
8003482: 4b84 ldr r3, [pc, #528] ; (8003694 <HAL_RCC_OscConfig+0xc58>)
8003484: 6a1b ldr r3, [r3, #32]
8003486: e013 b.n 80034b0 <HAL_RCC_OscConfig+0xa74>
8003488: f507 7300 add.w r3, r7, #512 ; 0x200
800348c: f5a3 73a8 sub.w r3, r3, #336 ; 0x150
8003490: 2202 movs r2, #2
8003492: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003494: f507 7300 add.w r3, r7, #512 ; 0x200
8003498: f5a3 73a8 sub.w r3, r3, #336 ; 0x150
800349c: 681b ldr r3, [r3, #0]
800349e: fa93 f2a3 rbit r2, r3
80034a2: f507 7300 add.w r3, r7, #512 ; 0x200
80034a6: f5a3 73aa sub.w r3, r3, #340 ; 0x154
80034aa: 601a str r2, [r3, #0]
80034ac: 4b79 ldr r3, [pc, #484] ; (8003694 <HAL_RCC_OscConfig+0xc58>)
80034ae: 6a5b ldr r3, [r3, #36] ; 0x24
80034b0: f507 7200 add.w r2, r7, #512 ; 0x200
80034b4: f5a2 72ac sub.w r2, r2, #344 ; 0x158
80034b8: 2102 movs r1, #2
80034ba: 6011 str r1, [r2, #0]
80034bc: f507 7200 add.w r2, r7, #512 ; 0x200
80034c0: f5a2 72ac sub.w r2, r2, #344 ; 0x158
80034c4: 6812 ldr r2, [r2, #0]
80034c6: fa92 f1a2 rbit r1, r2
80034ca: f507 7200 add.w r2, r7, #512 ; 0x200
80034ce: f5a2 72ae sub.w r2, r2, #348 ; 0x15c
80034d2: 6011 str r1, [r2, #0]
return result;
80034d4: f507 7200 add.w r2, r7, #512 ; 0x200
80034d8: f5a2 72ae sub.w r2, r2, #348 ; 0x15c
80034dc: 6812 ldr r2, [r2, #0]
80034de: fab2 f282 clz r2, r2
80034e2: b2d2 uxtb r2, r2
80034e4: f042 0240 orr.w r2, r2, #64 ; 0x40
80034e8: b2d2 uxtb r2, r2
80034ea: f002 021f and.w r2, r2, #31
80034ee: 2101 movs r1, #1
80034f0: fa01 f202 lsl.w r2, r1, r2
80034f4: 4013 ands r3, r2
80034f6: 2b00 cmp r3, #0
80034f8: d084 beq.n 8003404 <HAL_RCC_OscConfig+0x9c8>
80034fa: e07f b.n 80035fc <HAL_RCC_OscConfig+0xbc0>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80034fc: f7fe fbc6 bl 8001c8c <HAL_GetTick>
8003500: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8003504: e00b b.n 800351e <HAL_RCC_OscConfig+0xae2>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8003506: f7fe fbc1 bl 8001c8c <HAL_GetTick>
800350a: 4602 mov r2, r0
800350c: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
8003510: 1ad3 subs r3, r2, r3
8003512: f241 3288 movw r2, #5000 ; 0x1388
8003516: 4293 cmp r3, r2
8003518: d901 bls.n 800351e <HAL_RCC_OscConfig+0xae2>
{
return HAL_TIMEOUT;
800351a: 2303 movs r3, #3
800351c: e2c4 b.n 8003aa8 <HAL_RCC_OscConfig+0x106c>
800351e: f507 7300 add.w r3, r7, #512 ; 0x200
8003522: f5a3 73b0 sub.w r3, r3, #352 ; 0x160
8003526: 2202 movs r2, #2
8003528: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800352a: f507 7300 add.w r3, r7, #512 ; 0x200
800352e: f5a3 73b0 sub.w r3, r3, #352 ; 0x160
8003532: 681b ldr r3, [r3, #0]
8003534: fa93 f2a3 rbit r2, r3
8003538: f507 7300 add.w r3, r7, #512 ; 0x200
800353c: f5a3 73b2 sub.w r3, r3, #356 ; 0x164
8003540: 601a str r2, [r3, #0]
8003542: f507 7300 add.w r3, r7, #512 ; 0x200
8003546: f5a3 73b4 sub.w r3, r3, #360 ; 0x168
800354a: 2202 movs r2, #2
800354c: 601a str r2, [r3, #0]
800354e: f507 7300 add.w r3, r7, #512 ; 0x200
8003552: f5a3 73b4 sub.w r3, r3, #360 ; 0x168
8003556: 681b ldr r3, [r3, #0]
8003558: fa93 f2a3 rbit r2, r3
800355c: f507 7300 add.w r3, r7, #512 ; 0x200
8003560: f5a3 73b6 sub.w r3, r3, #364 ; 0x16c
8003564: 601a str r2, [r3, #0]
return result;
8003566: f507 7300 add.w r3, r7, #512 ; 0x200
800356a: f5a3 73b6 sub.w r3, r3, #364 ; 0x16c
800356e: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8003570: fab3 f383 clz r3, r3
8003574: b2db uxtb r3, r3
8003576: 095b lsrs r3, r3, #5
8003578: b2db uxtb r3, r3
800357a: f043 0302 orr.w r3, r3, #2
800357e: b2db uxtb r3, r3
8003580: 2b02 cmp r3, #2
8003582: d102 bne.n 800358a <HAL_RCC_OscConfig+0xb4e>
8003584: 4b43 ldr r3, [pc, #268] ; (8003694 <HAL_RCC_OscConfig+0xc58>)
8003586: 6a1b ldr r3, [r3, #32]
8003588: e013 b.n 80035b2 <HAL_RCC_OscConfig+0xb76>
800358a: f507 7300 add.w r3, r7, #512 ; 0x200
800358e: f5a3 73b8 sub.w r3, r3, #368 ; 0x170
8003592: 2202 movs r2, #2
8003594: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003596: f507 7300 add.w r3, r7, #512 ; 0x200
800359a: f5a3 73b8 sub.w r3, r3, #368 ; 0x170
800359e: 681b ldr r3, [r3, #0]
80035a0: fa93 f2a3 rbit r2, r3
80035a4: f507 7300 add.w r3, r7, #512 ; 0x200
80035a8: f5a3 73ba sub.w r3, r3, #372 ; 0x174
80035ac: 601a str r2, [r3, #0]
80035ae: 4b39 ldr r3, [pc, #228] ; (8003694 <HAL_RCC_OscConfig+0xc58>)
80035b0: 6a5b ldr r3, [r3, #36] ; 0x24
80035b2: f507 7200 add.w r2, r7, #512 ; 0x200
80035b6: f5a2 72bc sub.w r2, r2, #376 ; 0x178
80035ba: 2102 movs r1, #2
80035bc: 6011 str r1, [r2, #0]
80035be: f507 7200 add.w r2, r7, #512 ; 0x200
80035c2: f5a2 72bc sub.w r2, r2, #376 ; 0x178
80035c6: 6812 ldr r2, [r2, #0]
80035c8: fa92 f1a2 rbit r1, r2
80035cc: f507 7200 add.w r2, r7, #512 ; 0x200
80035d0: f5a2 72be sub.w r2, r2, #380 ; 0x17c
80035d4: 6011 str r1, [r2, #0]
return result;
80035d6: f507 7200 add.w r2, r7, #512 ; 0x200
80035da: f5a2 72be sub.w r2, r2, #380 ; 0x17c
80035de: 6812 ldr r2, [r2, #0]
80035e0: fab2 f282 clz r2, r2
80035e4: b2d2 uxtb r2, r2
80035e6: f042 0240 orr.w r2, r2, #64 ; 0x40
80035ea: b2d2 uxtb r2, r2
80035ec: f002 021f and.w r2, r2, #31
80035f0: 2101 movs r1, #1
80035f2: fa01 f202 lsl.w r2, r1, r2
80035f6: 4013 ands r3, r2
80035f8: 2b00 cmp r3, #0
80035fa: d184 bne.n 8003506 <HAL_RCC_OscConfig+0xaca>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
80035fc: f897 31ff ldrb.w r3, [r7, #511] ; 0x1ff
8003600: 2b01 cmp r3, #1
8003602: d105 bne.n 8003610 <HAL_RCC_OscConfig+0xbd4>
{
__HAL_RCC_PWR_CLK_DISABLE();
8003604: 4b23 ldr r3, [pc, #140] ; (8003694 <HAL_RCC_OscConfig+0xc58>)
8003606: 69db ldr r3, [r3, #28]
8003608: 4a22 ldr r2, [pc, #136] ; (8003694 <HAL_RCC_OscConfig+0xc58>)
800360a: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
800360e: 61d3 str r3, [r2, #28]
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8003610: f507 7300 add.w r3, r7, #512 ; 0x200
8003614: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8003618: 681b ldr r3, [r3, #0]
800361a: 69db ldr r3, [r3, #28]
800361c: 2b00 cmp r3, #0
800361e: f000 8242 beq.w 8003aa6 <HAL_RCC_OscConfig+0x106a>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8003622: 4b1c ldr r3, [pc, #112] ; (8003694 <HAL_RCC_OscConfig+0xc58>)
8003624: 685b ldr r3, [r3, #4]
8003626: f003 030c and.w r3, r3, #12
800362a: 2b08 cmp r3, #8
800362c: f000 8213 beq.w 8003a56 <HAL_RCC_OscConfig+0x101a>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8003630: f507 7300 add.w r3, r7, #512 ; 0x200
8003634: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8003638: 681b ldr r3, [r3, #0]
800363a: 69db ldr r3, [r3, #28]
800363c: 2b02 cmp r3, #2
800363e: f040 8162 bne.w 8003906 <HAL_RCC_OscConfig+0xeca>
8003642: f507 7300 add.w r3, r7, #512 ; 0x200
8003646: f5a3 73c0 sub.w r3, r3, #384 ; 0x180
800364a: f04f 7280 mov.w r2, #16777216 ; 0x1000000
800364e: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003650: f507 7300 add.w r3, r7, #512 ; 0x200
8003654: f5a3 73c0 sub.w r3, r3, #384 ; 0x180
8003658: 681b ldr r3, [r3, #0]
800365a: fa93 f2a3 rbit r2, r3
800365e: f507 7300 add.w r3, r7, #512 ; 0x200
8003662: f5a3 73c2 sub.w r3, r3, #388 ; 0x184
8003666: 601a str r2, [r3, #0]
return result;
8003668: f507 7300 add.w r3, r7, #512 ; 0x200
800366c: f5a3 73c2 sub.w r3, r3, #388 ; 0x184
8003670: 681b ldr r3, [r3, #0]
#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
#endif
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8003672: fab3 f383 clz r3, r3
8003676: b2db uxtb r3, r3
8003678: f103 5384 add.w r3, r3, #276824064 ; 0x10800000
800367c: f503 1384 add.w r3, r3, #1081344 ; 0x108000
8003680: 009b lsls r3, r3, #2
8003682: 461a mov r2, r3
8003684: 2300 movs r3, #0
8003686: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8003688: f7fe fb00 bl 8001c8c <HAL_GetTick>
800368c: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8003690: e00c b.n 80036ac <HAL_RCC_OscConfig+0xc70>
8003692: bf00 nop
8003694: 40021000 .word 0x40021000
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8003698: f7fe faf8 bl 8001c8c <HAL_GetTick>
800369c: 4602 mov r2, r0
800369e: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
80036a2: 1ad3 subs r3, r2, r3
80036a4: 2b02 cmp r3, #2
80036a6: d901 bls.n 80036ac <HAL_RCC_OscConfig+0xc70>
{
return HAL_TIMEOUT;
80036a8: 2303 movs r3, #3
80036aa: e1fd b.n 8003aa8 <HAL_RCC_OscConfig+0x106c>
80036ac: f507 7300 add.w r3, r7, #512 ; 0x200
80036b0: f5a3 73c4 sub.w r3, r3, #392 ; 0x188
80036b4: f04f 7200 mov.w r2, #33554432 ; 0x2000000
80036b8: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80036ba: f507 7300 add.w r3, r7, #512 ; 0x200
80036be: f5a3 73c4 sub.w r3, r3, #392 ; 0x188
80036c2: 681b ldr r3, [r3, #0]
80036c4: fa93 f2a3 rbit r2, r3
80036c8: f507 7300 add.w r3, r7, #512 ; 0x200
80036cc: f5a3 73c6 sub.w r3, r3, #396 ; 0x18c
80036d0: 601a str r2, [r3, #0]
return result;
80036d2: f507 7300 add.w r3, r7, #512 ; 0x200
80036d6: f5a3 73c6 sub.w r3, r3, #396 ; 0x18c
80036da: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80036dc: fab3 f383 clz r3, r3
80036e0: b2db uxtb r3, r3
80036e2: 095b lsrs r3, r3, #5
80036e4: b2db uxtb r3, r3
80036e6: f043 0301 orr.w r3, r3, #1
80036ea: b2db uxtb r3, r3
80036ec: 2b01 cmp r3, #1
80036ee: d102 bne.n 80036f6 <HAL_RCC_OscConfig+0xcba>
80036f0: 4bb0 ldr r3, [pc, #704] ; (80039b4 <HAL_RCC_OscConfig+0xf78>)
80036f2: 681b ldr r3, [r3, #0]
80036f4: e027 b.n 8003746 <HAL_RCC_OscConfig+0xd0a>
80036f6: f507 7300 add.w r3, r7, #512 ; 0x200
80036fa: f5a3 73c8 sub.w r3, r3, #400 ; 0x190
80036fe: f04f 7200 mov.w r2, #33554432 ; 0x2000000
8003702: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003704: f507 7300 add.w r3, r7, #512 ; 0x200
8003708: f5a3 73c8 sub.w r3, r3, #400 ; 0x190
800370c: 681b ldr r3, [r3, #0]
800370e: fa93 f2a3 rbit r2, r3
8003712: f507 7300 add.w r3, r7, #512 ; 0x200
8003716: f5a3 73ca sub.w r3, r3, #404 ; 0x194
800371a: 601a str r2, [r3, #0]
800371c: f507 7300 add.w r3, r7, #512 ; 0x200
8003720: f5a3 73cc sub.w r3, r3, #408 ; 0x198
8003724: f04f 7200 mov.w r2, #33554432 ; 0x2000000
8003728: 601a str r2, [r3, #0]
800372a: f507 7300 add.w r3, r7, #512 ; 0x200
800372e: f5a3 73cc sub.w r3, r3, #408 ; 0x198
8003732: 681b ldr r3, [r3, #0]
8003734: fa93 f2a3 rbit r2, r3
8003738: f507 7300 add.w r3, r7, #512 ; 0x200
800373c: f5a3 73ce sub.w r3, r3, #412 ; 0x19c
8003740: 601a str r2, [r3, #0]
8003742: 4b9c ldr r3, [pc, #624] ; (80039b4 <HAL_RCC_OscConfig+0xf78>)
8003744: 6a5b ldr r3, [r3, #36] ; 0x24
8003746: f507 7200 add.w r2, r7, #512 ; 0x200
800374a: f5a2 72d0 sub.w r2, r2, #416 ; 0x1a0
800374e: f04f 7100 mov.w r1, #33554432 ; 0x2000000
8003752: 6011 str r1, [r2, #0]
8003754: f507 7200 add.w r2, r7, #512 ; 0x200
8003758: f5a2 72d0 sub.w r2, r2, #416 ; 0x1a0
800375c: 6812 ldr r2, [r2, #0]
800375e: fa92 f1a2 rbit r1, r2
8003762: f507 7200 add.w r2, r7, #512 ; 0x200
8003766: f5a2 72d2 sub.w r2, r2, #420 ; 0x1a4
800376a: 6011 str r1, [r2, #0]
return result;
800376c: f507 7200 add.w r2, r7, #512 ; 0x200
8003770: f5a2 72d2 sub.w r2, r2, #420 ; 0x1a4
8003774: 6812 ldr r2, [r2, #0]
8003776: fab2 f282 clz r2, r2
800377a: b2d2 uxtb r2, r2
800377c: f042 0220 orr.w r2, r2, #32
8003780: b2d2 uxtb r2, r2
8003782: f002 021f and.w r2, r2, #31
8003786: 2101 movs r1, #1
8003788: fa01 f202 lsl.w r2, r1, r2
800378c: 4013 ands r3, r2
800378e: 2b00 cmp r3, #0
8003790: d182 bne.n 8003698 <HAL_RCC_OscConfig+0xc5c>
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
RCC_OscInitStruct->PLL.PREDIV,
RCC_OscInitStruct->PLL.PLLMUL);
#else
/* Configure the main PLL clock source and multiplication factor. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8003792: 4b88 ldr r3, [pc, #544] ; (80039b4 <HAL_RCC_OscConfig+0xf78>)
8003794: 685b ldr r3, [r3, #4]
8003796: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000
800379a: f507 7300 add.w r3, r7, #512 ; 0x200
800379e: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
80037a2: 681b ldr r3, [r3, #0]
80037a4: 6a59 ldr r1, [r3, #36] ; 0x24
80037a6: f507 7300 add.w r3, r7, #512 ; 0x200
80037aa: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
80037ae: 681b ldr r3, [r3, #0]
80037b0: 6a1b ldr r3, [r3, #32]
80037b2: 430b orrs r3, r1
80037b4: 497f ldr r1, [pc, #508] ; (80039b4 <HAL_RCC_OscConfig+0xf78>)
80037b6: 4313 orrs r3, r2
80037b8: 604b str r3, [r1, #4]
80037ba: f507 7300 add.w r3, r7, #512 ; 0x200
80037be: f5a3 73d4 sub.w r3, r3, #424 ; 0x1a8
80037c2: f04f 7280 mov.w r2, #16777216 ; 0x1000000
80037c6: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80037c8: f507 7300 add.w r3, r7, #512 ; 0x200
80037cc: f5a3 73d4 sub.w r3, r3, #424 ; 0x1a8
80037d0: 681b ldr r3, [r3, #0]
80037d2: fa93 f2a3 rbit r2, r3
80037d6: f507 7300 add.w r3, r7, #512 ; 0x200
80037da: f5a3 73d6 sub.w r3, r3, #428 ; 0x1ac
80037de: 601a str r2, [r3, #0]
return result;
80037e0: f507 7300 add.w r3, r7, #512 ; 0x200
80037e4: f5a3 73d6 sub.w r3, r3, #428 ; 0x1ac
80037e8: 681b ldr r3, [r3, #0]
RCC_OscInitStruct->PLL.PLLMUL);
#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
80037ea: fab3 f383 clz r3, r3
80037ee: b2db uxtb r3, r3
80037f0: f103 5384 add.w r3, r3, #276824064 ; 0x10800000
80037f4: f503 1384 add.w r3, r3, #1081344 ; 0x108000
80037f8: 009b lsls r3, r3, #2
80037fa: 461a mov r2, r3
80037fc: 2301 movs r3, #1
80037fe: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8003800: f7fe fa44 bl 8001c8c <HAL_GetTick>
8003804: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8003808: e009 b.n 800381e <HAL_RCC_OscConfig+0xde2>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
800380a: f7fe fa3f bl 8001c8c <HAL_GetTick>
800380e: 4602 mov r2, r0
8003810: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
8003814: 1ad3 subs r3, r2, r3
8003816: 2b02 cmp r3, #2
8003818: d901 bls.n 800381e <HAL_RCC_OscConfig+0xde2>
{
return HAL_TIMEOUT;
800381a: 2303 movs r3, #3
800381c: e144 b.n 8003aa8 <HAL_RCC_OscConfig+0x106c>
800381e: f507 7300 add.w r3, r7, #512 ; 0x200
8003822: f5a3 73d8 sub.w r3, r3, #432 ; 0x1b0
8003826: f04f 7200 mov.w r2, #33554432 ; 0x2000000
800382a: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800382c: f507 7300 add.w r3, r7, #512 ; 0x200
8003830: f5a3 73d8 sub.w r3, r3, #432 ; 0x1b0
8003834: 681b ldr r3, [r3, #0]
8003836: fa93 f2a3 rbit r2, r3
800383a: f507 7300 add.w r3, r7, #512 ; 0x200
800383e: f5a3 73da sub.w r3, r3, #436 ; 0x1b4
8003842: 601a str r2, [r3, #0]
return result;
8003844: f507 7300 add.w r3, r7, #512 ; 0x200
8003848: f5a3 73da sub.w r3, r3, #436 ; 0x1b4
800384c: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800384e: fab3 f383 clz r3, r3
8003852: b2db uxtb r3, r3
8003854: 095b lsrs r3, r3, #5
8003856: b2db uxtb r3, r3
8003858: f043 0301 orr.w r3, r3, #1
800385c: b2db uxtb r3, r3
800385e: 2b01 cmp r3, #1
8003860: d102 bne.n 8003868 <HAL_RCC_OscConfig+0xe2c>
8003862: 4b54 ldr r3, [pc, #336] ; (80039b4 <HAL_RCC_OscConfig+0xf78>)
8003864: 681b ldr r3, [r3, #0]
8003866: e027 b.n 80038b8 <HAL_RCC_OscConfig+0xe7c>
8003868: f507 7300 add.w r3, r7, #512 ; 0x200
800386c: f5a3 73dc sub.w r3, r3, #440 ; 0x1b8
8003870: f04f 7200 mov.w r2, #33554432 ; 0x2000000
8003874: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003876: f507 7300 add.w r3, r7, #512 ; 0x200
800387a: f5a3 73dc sub.w r3, r3, #440 ; 0x1b8
800387e: 681b ldr r3, [r3, #0]
8003880: fa93 f2a3 rbit r2, r3
8003884: f507 7300 add.w r3, r7, #512 ; 0x200
8003888: f5a3 73de sub.w r3, r3, #444 ; 0x1bc
800388c: 601a str r2, [r3, #0]
800388e: f507 7300 add.w r3, r7, #512 ; 0x200
8003892: f5a3 73e0 sub.w r3, r3, #448 ; 0x1c0
8003896: f04f 7200 mov.w r2, #33554432 ; 0x2000000
800389a: 601a str r2, [r3, #0]
800389c: f507 7300 add.w r3, r7, #512 ; 0x200
80038a0: f5a3 73e0 sub.w r3, r3, #448 ; 0x1c0
80038a4: 681b ldr r3, [r3, #0]
80038a6: fa93 f2a3 rbit r2, r3
80038aa: f507 7300 add.w r3, r7, #512 ; 0x200
80038ae: f5a3 73e2 sub.w r3, r3, #452 ; 0x1c4
80038b2: 601a str r2, [r3, #0]
80038b4: 4b3f ldr r3, [pc, #252] ; (80039b4 <HAL_RCC_OscConfig+0xf78>)
80038b6: 6a5b ldr r3, [r3, #36] ; 0x24
80038b8: f507 7200 add.w r2, r7, #512 ; 0x200
80038bc: f5a2 72e4 sub.w r2, r2, #456 ; 0x1c8
80038c0: f04f 7100 mov.w r1, #33554432 ; 0x2000000
80038c4: 6011 str r1, [r2, #0]
80038c6: f507 7200 add.w r2, r7, #512 ; 0x200
80038ca: f5a2 72e4 sub.w r2, r2, #456 ; 0x1c8
80038ce: 6812 ldr r2, [r2, #0]
80038d0: fa92 f1a2 rbit r1, r2
80038d4: f507 7200 add.w r2, r7, #512 ; 0x200
80038d8: f5a2 72e6 sub.w r2, r2, #460 ; 0x1cc
80038dc: 6011 str r1, [r2, #0]
return result;
80038de: f507 7200 add.w r2, r7, #512 ; 0x200
80038e2: f5a2 72e6 sub.w r2, r2, #460 ; 0x1cc
80038e6: 6812 ldr r2, [r2, #0]
80038e8: fab2 f282 clz r2, r2
80038ec: b2d2 uxtb r2, r2
80038ee: f042 0220 orr.w r2, r2, #32
80038f2: b2d2 uxtb r2, r2
80038f4: f002 021f and.w r2, r2, #31
80038f8: 2101 movs r1, #1
80038fa: fa01 f202 lsl.w r2, r1, r2
80038fe: 4013 ands r3, r2
8003900: 2b00 cmp r3, #0
8003902: d082 beq.n 800380a <HAL_RCC_OscConfig+0xdce>
8003904: e0cf b.n 8003aa6 <HAL_RCC_OscConfig+0x106a>
8003906: f507 7300 add.w r3, r7, #512 ; 0x200
800390a: f5a3 73e8 sub.w r3, r3, #464 ; 0x1d0
800390e: f04f 7280 mov.w r2, #16777216 ; 0x1000000
8003912: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003914: f507 7300 add.w r3, r7, #512 ; 0x200
8003918: f5a3 73e8 sub.w r3, r3, #464 ; 0x1d0
800391c: 681b ldr r3, [r3, #0]
800391e: fa93 f2a3 rbit r2, r3
8003922: f507 7300 add.w r3, r7, #512 ; 0x200
8003926: f5a3 73ea sub.w r3, r3, #468 ; 0x1d4
800392a: 601a str r2, [r3, #0]
return result;
800392c: f507 7300 add.w r3, r7, #512 ; 0x200
8003930: f5a3 73ea sub.w r3, r3, #468 ; 0x1d4
8003934: 681b ldr r3, [r3, #0]
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8003936: fab3 f383 clz r3, r3
800393a: b2db uxtb r3, r3
800393c: f103 5384 add.w r3, r3, #276824064 ; 0x10800000
8003940: f503 1384 add.w r3, r3, #1081344 ; 0x108000
8003944: 009b lsls r3, r3, #2
8003946: 461a mov r2, r3
8003948: 2300 movs r3, #0
800394a: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800394c: f7fe f99e bl 8001c8c <HAL_GetTick>
8003950: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8003954: e009 b.n 800396a <HAL_RCC_OscConfig+0xf2e>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8003956: f7fe f999 bl 8001c8c <HAL_GetTick>
800395a: 4602 mov r2, r0
800395c: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
8003960: 1ad3 subs r3, r2, r3
8003962: 2b02 cmp r3, #2
8003964: d901 bls.n 800396a <HAL_RCC_OscConfig+0xf2e>
{
return HAL_TIMEOUT;
8003966: 2303 movs r3, #3
8003968: e09e b.n 8003aa8 <HAL_RCC_OscConfig+0x106c>
800396a: f507 7300 add.w r3, r7, #512 ; 0x200
800396e: f5a3 73ec sub.w r3, r3, #472 ; 0x1d8
8003972: f04f 7200 mov.w r2, #33554432 ; 0x2000000
8003976: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003978: f507 7300 add.w r3, r7, #512 ; 0x200
800397c: f5a3 73ec sub.w r3, r3, #472 ; 0x1d8
8003980: 681b ldr r3, [r3, #0]
8003982: fa93 f2a3 rbit r2, r3
8003986: f507 7300 add.w r3, r7, #512 ; 0x200
800398a: f5a3 73ee sub.w r3, r3, #476 ; 0x1dc
800398e: 601a str r2, [r3, #0]
return result;
8003990: f507 7300 add.w r3, r7, #512 ; 0x200
8003994: f5a3 73ee sub.w r3, r3, #476 ; 0x1dc
8003998: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800399a: fab3 f383 clz r3, r3
800399e: b2db uxtb r3, r3
80039a0: 095b lsrs r3, r3, #5
80039a2: b2db uxtb r3, r3
80039a4: f043 0301 orr.w r3, r3, #1
80039a8: b2db uxtb r3, r3
80039aa: 2b01 cmp r3, #1
80039ac: d104 bne.n 80039b8 <HAL_RCC_OscConfig+0xf7c>
80039ae: 4b01 ldr r3, [pc, #4] ; (80039b4 <HAL_RCC_OscConfig+0xf78>)
80039b0: 681b ldr r3, [r3, #0]
80039b2: e029 b.n 8003a08 <HAL_RCC_OscConfig+0xfcc>
80039b4: 40021000 .word 0x40021000
80039b8: f507 7300 add.w r3, r7, #512 ; 0x200
80039bc: f5a3 73f0 sub.w r3, r3, #480 ; 0x1e0
80039c0: f04f 7200 mov.w r2, #33554432 ; 0x2000000
80039c4: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80039c6: f507 7300 add.w r3, r7, #512 ; 0x200
80039ca: f5a3 73f0 sub.w r3, r3, #480 ; 0x1e0
80039ce: 681b ldr r3, [r3, #0]
80039d0: fa93 f2a3 rbit r2, r3
80039d4: f507 7300 add.w r3, r7, #512 ; 0x200
80039d8: f5a3 73f2 sub.w r3, r3, #484 ; 0x1e4
80039dc: 601a str r2, [r3, #0]
80039de: f507 7300 add.w r3, r7, #512 ; 0x200
80039e2: f5a3 73f4 sub.w r3, r3, #488 ; 0x1e8
80039e6: f04f 7200 mov.w r2, #33554432 ; 0x2000000
80039ea: 601a str r2, [r3, #0]
80039ec: f507 7300 add.w r3, r7, #512 ; 0x200
80039f0: f5a3 73f4 sub.w r3, r3, #488 ; 0x1e8
80039f4: 681b ldr r3, [r3, #0]
80039f6: fa93 f2a3 rbit r2, r3
80039fa: f507 7300 add.w r3, r7, #512 ; 0x200
80039fe: f5a3 73f6 sub.w r3, r3, #492 ; 0x1ec
8003a02: 601a str r2, [r3, #0]
8003a04: 4b2b ldr r3, [pc, #172] ; (8003ab4 <HAL_RCC_OscConfig+0x1078>)
8003a06: 6a5b ldr r3, [r3, #36] ; 0x24
8003a08: f507 7200 add.w r2, r7, #512 ; 0x200
8003a0c: f5a2 72f8 sub.w r2, r2, #496 ; 0x1f0
8003a10: f04f 7100 mov.w r1, #33554432 ; 0x2000000
8003a14: 6011 str r1, [r2, #0]
8003a16: f507 7200 add.w r2, r7, #512 ; 0x200
8003a1a: f5a2 72f8 sub.w r2, r2, #496 ; 0x1f0
8003a1e: 6812 ldr r2, [r2, #0]
8003a20: fa92 f1a2 rbit r1, r2
8003a24: f507 7200 add.w r2, r7, #512 ; 0x200
8003a28: f5a2 72fa sub.w r2, r2, #500 ; 0x1f4
8003a2c: 6011 str r1, [r2, #0]
return result;
8003a2e: f507 7200 add.w r2, r7, #512 ; 0x200
8003a32: f5a2 72fa sub.w r2, r2, #500 ; 0x1f4
8003a36: 6812 ldr r2, [r2, #0]
8003a38: fab2 f282 clz r2, r2
8003a3c: b2d2 uxtb r2, r2
8003a3e: f042 0220 orr.w r2, r2, #32
8003a42: b2d2 uxtb r2, r2
8003a44: f002 021f and.w r2, r2, #31
8003a48: 2101 movs r1, #1
8003a4a: fa01 f202 lsl.w r2, r1, r2
8003a4e: 4013 ands r3, r2
8003a50: 2b00 cmp r3, #0
8003a52: d180 bne.n 8003956 <HAL_RCC_OscConfig+0xf1a>
8003a54: e027 b.n 8003aa6 <HAL_RCC_OscConfig+0x106a>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8003a56: f507 7300 add.w r3, r7, #512 ; 0x200
8003a5a: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8003a5e: 681b ldr r3, [r3, #0]
8003a60: 69db ldr r3, [r3, #28]
8003a62: 2b01 cmp r3, #1
8003a64: d101 bne.n 8003a6a <HAL_RCC_OscConfig+0x102e>
{
return HAL_ERROR;
8003a66: 2301 movs r3, #1
8003a68: e01e b.n 8003aa8 <HAL_RCC_OscConfig+0x106c>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8003a6a: 4b12 ldr r3, [pc, #72] ; (8003ab4 <HAL_RCC_OscConfig+0x1078>)
8003a6c: 685b ldr r3, [r3, #4]
8003a6e: f8c7 31f4 str.w r3, [r7, #500] ; 0x1f4
pll_config2 = RCC->CFGR2;
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV))
#else
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8003a72: f8d7 31f4 ldr.w r3, [r7, #500] ; 0x1f4
8003a76: f403 3280 and.w r2, r3, #65536 ; 0x10000
8003a7a: f507 7300 add.w r3, r7, #512 ; 0x200
8003a7e: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8003a82: 681b ldr r3, [r3, #0]
8003a84: 6a1b ldr r3, [r3, #32]
8003a86: 429a cmp r2, r3
8003a88: d10b bne.n 8003aa2 <HAL_RCC_OscConfig+0x1066>
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL))
8003a8a: f8d7 31f4 ldr.w r3, [r7, #500] ; 0x1f4
8003a8e: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000
8003a92: f507 7300 add.w r3, r7, #512 ; 0x200
8003a96: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8003a9a: 681b ldr r3, [r3, #0]
8003a9c: 6a5b ldr r3, [r3, #36] ; 0x24
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8003a9e: 429a cmp r2, r3
8003aa0: d001 beq.n 8003aa6 <HAL_RCC_OscConfig+0x106a>
#endif
{
return HAL_ERROR;
8003aa2: 2301 movs r3, #1
8003aa4: e000 b.n 8003aa8 <HAL_RCC_OscConfig+0x106c>
}
}
}
}
return HAL_OK;
8003aa6: 2300 movs r3, #0
}
8003aa8: 4618 mov r0, r3
8003aaa: f507 7700 add.w r7, r7, #512 ; 0x200
8003aae: 46bd mov sp, r7
8003ab0: bd80 pop {r7, pc}
8003ab2: bf00 nop
8003ab4: 40021000 .word 0x40021000
08003ab8 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8003ab8: b580 push {r7, lr}
8003aba: b09e sub sp, #120 ; 0x78
8003abc: af00 add r7, sp, #0
8003abe: 6078 str r0, [r7, #4]
8003ac0: 6039 str r1, [r7, #0]
uint32_t tickstart = 0U;
8003ac2: 2300 movs r3, #0
8003ac4: 677b str r3, [r7, #116] ; 0x74
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8003ac6: 687b ldr r3, [r7, #4]
8003ac8: 2b00 cmp r3, #0
8003aca: d101 bne.n 8003ad0 <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
8003acc: 2301 movs r3, #1
8003ace: e162 b.n 8003d96 <HAL_RCC_ClockConfig+0x2de>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8003ad0: 4b90 ldr r3, [pc, #576] ; (8003d14 <HAL_RCC_ClockConfig+0x25c>)
8003ad2: 681b ldr r3, [r3, #0]
8003ad4: f003 0307 and.w r3, r3, #7
8003ad8: 683a ldr r2, [r7, #0]
8003ada: 429a cmp r2, r3
8003adc: d910 bls.n 8003b00 <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8003ade: 4b8d ldr r3, [pc, #564] ; (8003d14 <HAL_RCC_ClockConfig+0x25c>)
8003ae0: 681b ldr r3, [r3, #0]
8003ae2: f023 0207 bic.w r2, r3, #7
8003ae6: 498b ldr r1, [pc, #556] ; (8003d14 <HAL_RCC_ClockConfig+0x25c>)
8003ae8: 683b ldr r3, [r7, #0]
8003aea: 4313 orrs r3, r2
8003aec: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8003aee: 4b89 ldr r3, [pc, #548] ; (8003d14 <HAL_RCC_ClockConfig+0x25c>)
8003af0: 681b ldr r3, [r3, #0]
8003af2: f003 0307 and.w r3, r3, #7
8003af6: 683a ldr r2, [r7, #0]
8003af8: 429a cmp r2, r3
8003afa: d001 beq.n 8003b00 <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
8003afc: 2301 movs r3, #1
8003afe: e14a b.n 8003d96 <HAL_RCC_ClockConfig+0x2de>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8003b00: 687b ldr r3, [r7, #4]
8003b02: 681b ldr r3, [r3, #0]
8003b04: f003 0302 and.w r3, r3, #2
8003b08: 2b00 cmp r3, #0
8003b0a: d008 beq.n 8003b1e <HAL_RCC_ClockConfig+0x66>
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8003b0c: 4b82 ldr r3, [pc, #520] ; (8003d18 <HAL_RCC_ClockConfig+0x260>)
8003b0e: 685b ldr r3, [r3, #4]
8003b10: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8003b14: 687b ldr r3, [r7, #4]
8003b16: 689b ldr r3, [r3, #8]
8003b18: 497f ldr r1, [pc, #508] ; (8003d18 <HAL_RCC_ClockConfig+0x260>)
8003b1a: 4313 orrs r3, r2
8003b1c: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8003b1e: 687b ldr r3, [r7, #4]
8003b20: 681b ldr r3, [r3, #0]
8003b22: f003 0301 and.w r3, r3, #1
8003b26: 2b00 cmp r3, #0
8003b28: f000 80dc beq.w 8003ce4 <HAL_RCC_ClockConfig+0x22c>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8003b2c: 687b ldr r3, [r7, #4]
8003b2e: 685b ldr r3, [r3, #4]
8003b30: 2b01 cmp r3, #1
8003b32: d13c bne.n 8003bae <HAL_RCC_ClockConfig+0xf6>
8003b34: f44f 3300 mov.w r3, #131072 ; 0x20000
8003b38: 673b str r3, [r7, #112] ; 0x70
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003b3a: 6f3b ldr r3, [r7, #112] ; 0x70
8003b3c: fa93 f3a3 rbit r3, r3
8003b40: 66fb str r3, [r7, #108] ; 0x6c
return result;
8003b42: 6efb ldr r3, [r7, #108] ; 0x6c
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8003b44: fab3 f383 clz r3, r3
8003b48: b2db uxtb r3, r3
8003b4a: 095b lsrs r3, r3, #5
8003b4c: b2db uxtb r3, r3
8003b4e: f043 0301 orr.w r3, r3, #1
8003b52: b2db uxtb r3, r3
8003b54: 2b01 cmp r3, #1
8003b56: d102 bne.n 8003b5e <HAL_RCC_ClockConfig+0xa6>
8003b58: 4b6f ldr r3, [pc, #444] ; (8003d18 <HAL_RCC_ClockConfig+0x260>)
8003b5a: 681b ldr r3, [r3, #0]
8003b5c: e00f b.n 8003b7e <HAL_RCC_ClockConfig+0xc6>
8003b5e: f44f 3300 mov.w r3, #131072 ; 0x20000
8003b62: 66bb str r3, [r7, #104] ; 0x68
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003b64: 6ebb ldr r3, [r7, #104] ; 0x68
8003b66: fa93 f3a3 rbit r3, r3
8003b6a: 667b str r3, [r7, #100] ; 0x64
8003b6c: f44f 3300 mov.w r3, #131072 ; 0x20000
8003b70: 663b str r3, [r7, #96] ; 0x60
8003b72: 6e3b ldr r3, [r7, #96] ; 0x60
8003b74: fa93 f3a3 rbit r3, r3
8003b78: 65fb str r3, [r7, #92] ; 0x5c
8003b7a: 4b67 ldr r3, [pc, #412] ; (8003d18 <HAL_RCC_ClockConfig+0x260>)
8003b7c: 6a5b ldr r3, [r3, #36] ; 0x24
8003b7e: f44f 3200 mov.w r2, #131072 ; 0x20000
8003b82: 65ba str r2, [r7, #88] ; 0x58
8003b84: 6dba ldr r2, [r7, #88] ; 0x58
8003b86: fa92 f2a2 rbit r2, r2
8003b8a: 657a str r2, [r7, #84] ; 0x54
return result;
8003b8c: 6d7a ldr r2, [r7, #84] ; 0x54
8003b8e: fab2 f282 clz r2, r2
8003b92: b2d2 uxtb r2, r2
8003b94: f042 0220 orr.w r2, r2, #32
8003b98: b2d2 uxtb r2, r2
8003b9a: f002 021f and.w r2, r2, #31
8003b9e: 2101 movs r1, #1
8003ba0: fa01 f202 lsl.w r2, r1, r2
8003ba4: 4013 ands r3, r2
8003ba6: 2b00 cmp r3, #0
8003ba8: d17b bne.n 8003ca2 <HAL_RCC_ClockConfig+0x1ea>
{
return HAL_ERROR;
8003baa: 2301 movs r3, #1
8003bac: e0f3 b.n 8003d96 <HAL_RCC_ClockConfig+0x2de>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8003bae: 687b ldr r3, [r7, #4]
8003bb0: 685b ldr r3, [r3, #4]
8003bb2: 2b02 cmp r3, #2
8003bb4: d13c bne.n 8003c30 <HAL_RCC_ClockConfig+0x178>
8003bb6: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8003bba: 653b str r3, [r7, #80] ; 0x50
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003bbc: 6d3b ldr r3, [r7, #80] ; 0x50
8003bbe: fa93 f3a3 rbit r3, r3
8003bc2: 64fb str r3, [r7, #76] ; 0x4c
return result;
8003bc4: 6cfb ldr r3, [r7, #76] ; 0x4c
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8003bc6: fab3 f383 clz r3, r3
8003bca: b2db uxtb r3, r3
8003bcc: 095b lsrs r3, r3, #5
8003bce: b2db uxtb r3, r3
8003bd0: f043 0301 orr.w r3, r3, #1
8003bd4: b2db uxtb r3, r3
8003bd6: 2b01 cmp r3, #1
8003bd8: d102 bne.n 8003be0 <HAL_RCC_ClockConfig+0x128>
8003bda: 4b4f ldr r3, [pc, #316] ; (8003d18 <HAL_RCC_ClockConfig+0x260>)
8003bdc: 681b ldr r3, [r3, #0]
8003bde: e00f b.n 8003c00 <HAL_RCC_ClockConfig+0x148>
8003be0: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8003be4: 64bb str r3, [r7, #72] ; 0x48
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003be6: 6cbb ldr r3, [r7, #72] ; 0x48
8003be8: fa93 f3a3 rbit r3, r3
8003bec: 647b str r3, [r7, #68] ; 0x44
8003bee: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8003bf2: 643b str r3, [r7, #64] ; 0x40
8003bf4: 6c3b ldr r3, [r7, #64] ; 0x40
8003bf6: fa93 f3a3 rbit r3, r3
8003bfa: 63fb str r3, [r7, #60] ; 0x3c
8003bfc: 4b46 ldr r3, [pc, #280] ; (8003d18 <HAL_RCC_ClockConfig+0x260>)
8003bfe: 6a5b ldr r3, [r3, #36] ; 0x24
8003c00: f04f 7200 mov.w r2, #33554432 ; 0x2000000
8003c04: 63ba str r2, [r7, #56] ; 0x38
8003c06: 6bba ldr r2, [r7, #56] ; 0x38
8003c08: fa92 f2a2 rbit r2, r2
8003c0c: 637a str r2, [r7, #52] ; 0x34
return result;
8003c0e: 6b7a ldr r2, [r7, #52] ; 0x34
8003c10: fab2 f282 clz r2, r2
8003c14: b2d2 uxtb r2, r2
8003c16: f042 0220 orr.w r2, r2, #32
8003c1a: b2d2 uxtb r2, r2
8003c1c: f002 021f and.w r2, r2, #31
8003c20: 2101 movs r1, #1
8003c22: fa01 f202 lsl.w r2, r1, r2
8003c26: 4013 ands r3, r2
8003c28: 2b00 cmp r3, #0
8003c2a: d13a bne.n 8003ca2 <HAL_RCC_ClockConfig+0x1ea>
{
return HAL_ERROR;
8003c2c: 2301 movs r3, #1
8003c2e: e0b2 b.n 8003d96 <HAL_RCC_ClockConfig+0x2de>
8003c30: 2302 movs r3, #2
8003c32: 633b str r3, [r7, #48] ; 0x30
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003c34: 6b3b ldr r3, [r7, #48] ; 0x30
8003c36: fa93 f3a3 rbit r3, r3
8003c3a: 62fb str r3, [r7, #44] ; 0x2c
return result;
8003c3c: 6afb ldr r3, [r7, #44] ; 0x2c
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8003c3e: fab3 f383 clz r3, r3
8003c42: b2db uxtb r3, r3
8003c44: 095b lsrs r3, r3, #5
8003c46: b2db uxtb r3, r3
8003c48: f043 0301 orr.w r3, r3, #1
8003c4c: b2db uxtb r3, r3
8003c4e: 2b01 cmp r3, #1
8003c50: d102 bne.n 8003c58 <HAL_RCC_ClockConfig+0x1a0>
8003c52: 4b31 ldr r3, [pc, #196] ; (8003d18 <HAL_RCC_ClockConfig+0x260>)
8003c54: 681b ldr r3, [r3, #0]
8003c56: e00d b.n 8003c74 <HAL_RCC_ClockConfig+0x1bc>
8003c58: 2302 movs r3, #2
8003c5a: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003c5c: 6abb ldr r3, [r7, #40] ; 0x28
8003c5e: fa93 f3a3 rbit r3, r3
8003c62: 627b str r3, [r7, #36] ; 0x24
8003c64: 2302 movs r3, #2
8003c66: 623b str r3, [r7, #32]
8003c68: 6a3b ldr r3, [r7, #32]
8003c6a: fa93 f3a3 rbit r3, r3
8003c6e: 61fb str r3, [r7, #28]
8003c70: 4b29 ldr r3, [pc, #164] ; (8003d18 <HAL_RCC_ClockConfig+0x260>)
8003c72: 6a5b ldr r3, [r3, #36] ; 0x24
8003c74: 2202 movs r2, #2
8003c76: 61ba str r2, [r7, #24]
8003c78: 69ba ldr r2, [r7, #24]
8003c7a: fa92 f2a2 rbit r2, r2
8003c7e: 617a str r2, [r7, #20]
return result;
8003c80: 697a ldr r2, [r7, #20]
8003c82: fab2 f282 clz r2, r2
8003c86: b2d2 uxtb r2, r2
8003c88: f042 0220 orr.w r2, r2, #32
8003c8c: b2d2 uxtb r2, r2
8003c8e: f002 021f and.w r2, r2, #31
8003c92: 2101 movs r1, #1
8003c94: fa01 f202 lsl.w r2, r1, r2
8003c98: 4013 ands r3, r2
8003c9a: 2b00 cmp r3, #0
8003c9c: d101 bne.n 8003ca2 <HAL_RCC_ClockConfig+0x1ea>
{
return HAL_ERROR;
8003c9e: 2301 movs r3, #1
8003ca0: e079 b.n 8003d96 <HAL_RCC_ClockConfig+0x2de>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8003ca2: 4b1d ldr r3, [pc, #116] ; (8003d18 <HAL_RCC_ClockConfig+0x260>)
8003ca4: 685b ldr r3, [r3, #4]
8003ca6: f023 0203 bic.w r2, r3, #3
8003caa: 687b ldr r3, [r7, #4]
8003cac: 685b ldr r3, [r3, #4]
8003cae: 491a ldr r1, [pc, #104] ; (8003d18 <HAL_RCC_ClockConfig+0x260>)
8003cb0: 4313 orrs r3, r2
8003cb2: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8003cb4: f7fd ffea bl 8001c8c <HAL_GetTick>
8003cb8: 6778 str r0, [r7, #116] ; 0x74
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8003cba: e00a b.n 8003cd2 <HAL_RCC_ClockConfig+0x21a>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8003cbc: f7fd ffe6 bl 8001c8c <HAL_GetTick>
8003cc0: 4602 mov r2, r0
8003cc2: 6f7b ldr r3, [r7, #116] ; 0x74
8003cc4: 1ad3 subs r3, r2, r3
8003cc6: f241 3288 movw r2, #5000 ; 0x1388
8003cca: 4293 cmp r3, r2
8003ccc: d901 bls.n 8003cd2 <HAL_RCC_ClockConfig+0x21a>
{
return HAL_TIMEOUT;
8003cce: 2303 movs r3, #3
8003cd0: e061 b.n 8003d96 <HAL_RCC_ClockConfig+0x2de>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8003cd2: 4b11 ldr r3, [pc, #68] ; (8003d18 <HAL_RCC_ClockConfig+0x260>)
8003cd4: 685b ldr r3, [r3, #4]
8003cd6: f003 020c and.w r2, r3, #12
8003cda: 687b ldr r3, [r7, #4]
8003cdc: 685b ldr r3, [r3, #4]
8003cde: 009b lsls r3, r3, #2
8003ce0: 429a cmp r2, r3
8003ce2: d1eb bne.n 8003cbc <HAL_RCC_ClockConfig+0x204>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8003ce4: 4b0b ldr r3, [pc, #44] ; (8003d14 <HAL_RCC_ClockConfig+0x25c>)
8003ce6: 681b ldr r3, [r3, #0]
8003ce8: f003 0307 and.w r3, r3, #7
8003cec: 683a ldr r2, [r7, #0]
8003cee: 429a cmp r2, r3
8003cf0: d214 bcs.n 8003d1c <HAL_RCC_ClockConfig+0x264>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8003cf2: 4b08 ldr r3, [pc, #32] ; (8003d14 <HAL_RCC_ClockConfig+0x25c>)
8003cf4: 681b ldr r3, [r3, #0]
8003cf6: f023 0207 bic.w r2, r3, #7
8003cfa: 4906 ldr r1, [pc, #24] ; (8003d14 <HAL_RCC_ClockConfig+0x25c>)
8003cfc: 683b ldr r3, [r7, #0]
8003cfe: 4313 orrs r3, r2
8003d00: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8003d02: 4b04 ldr r3, [pc, #16] ; (8003d14 <HAL_RCC_ClockConfig+0x25c>)
8003d04: 681b ldr r3, [r3, #0]
8003d06: f003 0307 and.w r3, r3, #7
8003d0a: 683a ldr r2, [r7, #0]
8003d0c: 429a cmp r2, r3
8003d0e: d005 beq.n 8003d1c <HAL_RCC_ClockConfig+0x264>
{
return HAL_ERROR;
8003d10: 2301 movs r3, #1
8003d12: e040 b.n 8003d96 <HAL_RCC_ClockConfig+0x2de>
8003d14: 40022000 .word 0x40022000
8003d18: 40021000 .word 0x40021000
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8003d1c: 687b ldr r3, [r7, #4]
8003d1e: 681b ldr r3, [r3, #0]
8003d20: f003 0304 and.w r3, r3, #4
8003d24: 2b00 cmp r3, #0
8003d26: d008 beq.n 8003d3a <HAL_RCC_ClockConfig+0x282>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8003d28: 4b1d ldr r3, [pc, #116] ; (8003da0 <HAL_RCC_ClockConfig+0x2e8>)
8003d2a: 685b ldr r3, [r3, #4]
8003d2c: f423 62e0 bic.w r2, r3, #1792 ; 0x700
8003d30: 687b ldr r3, [r7, #4]
8003d32: 68db ldr r3, [r3, #12]
8003d34: 491a ldr r1, [pc, #104] ; (8003da0 <HAL_RCC_ClockConfig+0x2e8>)
8003d36: 4313 orrs r3, r2
8003d38: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8003d3a: 687b ldr r3, [r7, #4]
8003d3c: 681b ldr r3, [r3, #0]
8003d3e: f003 0308 and.w r3, r3, #8
8003d42: 2b00 cmp r3, #0
8003d44: d009 beq.n 8003d5a <HAL_RCC_ClockConfig+0x2a2>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
8003d46: 4b16 ldr r3, [pc, #88] ; (8003da0 <HAL_RCC_ClockConfig+0x2e8>)
8003d48: 685b ldr r3, [r3, #4]
8003d4a: f423 5260 bic.w r2, r3, #14336 ; 0x3800
8003d4e: 687b ldr r3, [r7, #4]
8003d50: 691b ldr r3, [r3, #16]
8003d52: 00db lsls r3, r3, #3
8003d54: 4912 ldr r1, [pc, #72] ; (8003da0 <HAL_RCC_ClockConfig+0x2e8>)
8003d56: 4313 orrs r3, r2
8003d58: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
8003d5a: f000 f829 bl 8003db0 <HAL_RCC_GetSysClockFreq>
8003d5e: 4601 mov r1, r0
8003d60: 4b0f ldr r3, [pc, #60] ; (8003da0 <HAL_RCC_ClockConfig+0x2e8>)
8003d62: 685b ldr r3, [r3, #4]
8003d64: f003 03f0 and.w r3, r3, #240 ; 0xf0
8003d68: 22f0 movs r2, #240 ; 0xf0
8003d6a: 613a str r2, [r7, #16]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003d6c: 693a ldr r2, [r7, #16]
8003d6e: fa92 f2a2 rbit r2, r2
8003d72: 60fa str r2, [r7, #12]
return result;
8003d74: 68fa ldr r2, [r7, #12]
8003d76: fab2 f282 clz r2, r2
8003d7a: b2d2 uxtb r2, r2
8003d7c: 40d3 lsrs r3, r2
8003d7e: 4a09 ldr r2, [pc, #36] ; (8003da4 <HAL_RCC_ClockConfig+0x2ec>)
8003d80: 5cd3 ldrb r3, [r2, r3]
8003d82: fa21 f303 lsr.w r3, r1, r3
8003d86: 4a08 ldr r2, [pc, #32] ; (8003da8 <HAL_RCC_ClockConfig+0x2f0>)
8003d88: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (uwTickPrio);
8003d8a: 4b08 ldr r3, [pc, #32] ; (8003dac <HAL_RCC_ClockConfig+0x2f4>)
8003d8c: 681b ldr r3, [r3, #0]
8003d8e: 4618 mov r0, r3
8003d90: f7fd ff38 bl 8001c04 <HAL_InitTick>
return HAL_OK;
8003d94: 2300 movs r3, #0
}
8003d96: 4618 mov r0, r3
8003d98: 3778 adds r7, #120 ; 0x78
8003d9a: 46bd mov sp, r7
8003d9c: bd80 pop {r7, pc}
8003d9e: bf00 nop
8003da0: 40021000 .word 0x40021000
8003da4: 08004708 .word 0x08004708
8003da8: 20000000 .word 0x20000000
8003dac: 20000004 .word 0x20000004
08003db0 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8003db0: b480 push {r7}
8003db2: b08b sub sp, #44 ; 0x2c
8003db4: af00 add r7, sp, #0
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
8003db6: 2300 movs r3, #0
8003db8: 61fb str r3, [r7, #28]
8003dba: 2300 movs r3, #0
8003dbc: 61bb str r3, [r7, #24]
8003dbe: 2300 movs r3, #0
8003dc0: 627b str r3, [r7, #36] ; 0x24
8003dc2: 2300 movs r3, #0
8003dc4: 617b str r3, [r7, #20]
uint32_t sysclockfreq = 0U;
8003dc6: 2300 movs r3, #0
8003dc8: 623b str r3, [r7, #32]
tmpreg = RCC->CFGR;
8003dca: 4b29 ldr r3, [pc, #164] ; (8003e70 <HAL_RCC_GetSysClockFreq+0xc0>)
8003dcc: 685b ldr r3, [r3, #4]
8003dce: 61fb str r3, [r7, #28]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
8003dd0: 69fb ldr r3, [r7, #28]
8003dd2: f003 030c and.w r3, r3, #12
8003dd6: 2b04 cmp r3, #4
8003dd8: d002 beq.n 8003de0 <HAL_RCC_GetSysClockFreq+0x30>
8003dda: 2b08 cmp r3, #8
8003ddc: d003 beq.n 8003de6 <HAL_RCC_GetSysClockFreq+0x36>
8003dde: e03c b.n 8003e5a <HAL_RCC_GetSysClockFreq+0xaa>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
8003de0: 4b24 ldr r3, [pc, #144] ; (8003e74 <HAL_RCC_GetSysClockFreq+0xc4>)
8003de2: 623b str r3, [r7, #32]
break;
8003de4: e03c b.n 8003e60 <HAL_RCC_GetSysClockFreq+0xb0>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)];
8003de6: 69fb ldr r3, [r7, #28]
8003de8: f403 1370 and.w r3, r3, #3932160 ; 0x3c0000
8003dec: f44f 1270 mov.w r2, #3932160 ; 0x3c0000
8003df0: 60ba str r2, [r7, #8]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003df2: 68ba ldr r2, [r7, #8]
8003df4: fa92 f2a2 rbit r2, r2
8003df8: 607a str r2, [r7, #4]
return result;
8003dfa: 687a ldr r2, [r7, #4]
8003dfc: fab2 f282 clz r2, r2
8003e00: b2d2 uxtb r2, r2
8003e02: 40d3 lsrs r3, r2
8003e04: 4a1c ldr r2, [pc, #112] ; (8003e78 <HAL_RCC_GetSysClockFreq+0xc8>)
8003e06: 5cd3 ldrb r3, [r2, r3]
8003e08: 617b str r3, [r7, #20]
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> POSITION_VAL(RCC_CFGR2_PREDIV)];
8003e0a: 4b19 ldr r3, [pc, #100] ; (8003e70 <HAL_RCC_GetSysClockFreq+0xc0>)
8003e0c: 6adb ldr r3, [r3, #44] ; 0x2c
8003e0e: f003 030f and.w r3, r3, #15
8003e12: 220f movs r2, #15
8003e14: 613a str r2, [r7, #16]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003e16: 693a ldr r2, [r7, #16]
8003e18: fa92 f2a2 rbit r2, r2
8003e1c: 60fa str r2, [r7, #12]
return result;
8003e1e: 68fa ldr r2, [r7, #12]
8003e20: fab2 f282 clz r2, r2
8003e24: b2d2 uxtb r2, r2
8003e26: 40d3 lsrs r3, r2
8003e28: 4a14 ldr r2, [pc, #80] ; (8003e7c <HAL_RCC_GetSysClockFreq+0xcc>)
8003e2a: 5cd3 ldrb r3, [r2, r3]
8003e2c: 61bb str r3, [r7, #24]
#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI)
8003e2e: 69fb ldr r3, [r7, #28]
8003e30: f403 3380 and.w r3, r3, #65536 ; 0x10000
8003e34: 2b00 cmp r3, #0
8003e36: d008 beq.n 8003e4a <HAL_RCC_GetSysClockFreq+0x9a>
{
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
8003e38: 4a0e ldr r2, [pc, #56] ; (8003e74 <HAL_RCC_GetSysClockFreq+0xc4>)
8003e3a: 69bb ldr r3, [r7, #24]
8003e3c: fbb2 f2f3 udiv r2, r2, r3
8003e40: 697b ldr r3, [r7, #20]
8003e42: fb02 f303 mul.w r3, r2, r3
8003e46: 627b str r3, [r7, #36] ; 0x24
8003e48: e004 b.n 8003e54 <HAL_RCC_GetSysClockFreq+0xa4>
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
8003e4a: 697b ldr r3, [r7, #20]
8003e4c: 4a0c ldr r2, [pc, #48] ; (8003e80 <HAL_RCC_GetSysClockFreq+0xd0>)
8003e4e: fb02 f303 mul.w r3, r2, r3
8003e52: 627b str r3, [r7, #36] ; 0x24
{
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
}
#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
sysclockfreq = pllclk;
8003e54: 6a7b ldr r3, [r7, #36] ; 0x24
8003e56: 623b str r3, [r7, #32]
break;
8003e58: e002 b.n 8003e60 <HAL_RCC_GetSysClockFreq+0xb0>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
8003e5a: 4b0a ldr r3, [pc, #40] ; (8003e84 <HAL_RCC_GetSysClockFreq+0xd4>)
8003e5c: 623b str r3, [r7, #32]
break;
8003e5e: bf00 nop
}
}
return sysclockfreq;
8003e60: 6a3b ldr r3, [r7, #32]
}
8003e62: 4618 mov r0, r3
8003e64: 372c adds r7, #44 ; 0x2c
8003e66: 46bd mov sp, r7
8003e68: f85d 7b04 ldr.w r7, [sp], #4
8003e6c: 4770 bx lr
8003e6e: bf00 nop
8003e70: 40021000 .word 0x40021000
8003e74: 00f42400 .word 0x00f42400
8003e78: 08004718 .word 0x08004718
8003e7c: 08004728 .word 0x08004728
8003e80: 003d0900 .word 0x003d0900
8003e84: 007a1200 .word 0x007a1200
08003e88 <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
8003e88: b580 push {r7, lr}
8003e8a: b084 sub sp, #16
8003e8c: af00 add r7, sp, #0
8003e8e: 6078 str r0, [r7, #4]
uint32_t frxth;
/* Check the SPI handle allocation */
if (hspi == NULL)
8003e90: 687b ldr r3, [r7, #4]
8003e92: 2b00 cmp r3, #0
8003e94: d101 bne.n 8003e9a <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
8003e96: 2301 movs r3, #1
8003e98: e09d b.n 8003fd6 <HAL_SPI_Init+0x14e>
assert_param(IS_SPI_NSS(hspi->Init.NSS));
assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
8003e9a: 687b ldr r3, [r7, #4]
8003e9c: 6a5b ldr r3, [r3, #36] ; 0x24
8003e9e: 2b00 cmp r3, #0
8003ea0: d108 bne.n 8003eb4 <HAL_SPI_Init+0x2c>
{
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
if (hspi->Init.Mode == SPI_MODE_MASTER)
8003ea2: 687b ldr r3, [r7, #4]
8003ea4: 685b ldr r3, [r3, #4]
8003ea6: f5b3 7f82 cmp.w r3, #260 ; 0x104
8003eaa: d009 beq.n 8003ec0 <HAL_SPI_Init+0x38>
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
}
else
{
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
8003eac: 687b ldr r3, [r7, #4]
8003eae: 2200 movs r2, #0
8003eb0: 61da str r2, [r3, #28]
8003eb2: e005 b.n 8003ec0 <HAL_SPI_Init+0x38>
else
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
/* Force polarity and phase to TI protocaol requirements */
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
8003eb4: 687b ldr r3, [r7, #4]
8003eb6: 2200 movs r2, #0
8003eb8: 611a str r2, [r3, #16]
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
8003eba: 687b ldr r3, [r7, #4]
8003ebc: 2200 movs r2, #0
8003ebe: 615a str r2, [r3, #20]
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8003ec0: 687b ldr r3, [r7, #4]
8003ec2: 2200 movs r2, #0
8003ec4: 629a str r2, [r3, #40] ; 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
8003ec6: 687b ldr r3, [r7, #4]
8003ec8: f893 305d ldrb.w r3, [r3, #93] ; 0x5d
8003ecc: b2db uxtb r3, r3
8003ece: 2b00 cmp r3, #0
8003ed0: d106 bne.n 8003ee0 <HAL_SPI_Init+0x58>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
8003ed2: 687b ldr r3, [r7, #4]
8003ed4: 2200 movs r2, #0
8003ed6: f883 205c strb.w r2, [r3, #92] ; 0x5c
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
8003eda: 6878 ldr r0, [r7, #4]
8003edc: f7fd fdca bl 8001a74 <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
8003ee0: 687b ldr r3, [r7, #4]
8003ee2: 2202 movs r2, #2
8003ee4: f883 205d strb.w r2, [r3, #93] ; 0x5d
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8003ee8: 687b ldr r3, [r7, #4]
8003eea: 681b ldr r3, [r3, #0]
8003eec: 681a ldr r2, [r3, #0]
8003eee: 687b ldr r3, [r7, #4]
8003ef0: 681b ldr r3, [r3, #0]
8003ef2: f022 0240 bic.w r2, r2, #64 ; 0x40
8003ef6: 601a str r2, [r3, #0]
/* Align by default the rs fifo threshold on the data size */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
8003ef8: 687b ldr r3, [r7, #4]
8003efa: 68db ldr r3, [r3, #12]
8003efc: f5b3 6fe0 cmp.w r3, #1792 ; 0x700
8003f00: d902 bls.n 8003f08 <HAL_SPI_Init+0x80>
{
frxth = SPI_RXFIFO_THRESHOLD_HF;
8003f02: 2300 movs r3, #0
8003f04: 60fb str r3, [r7, #12]
8003f06: e002 b.n 8003f0e <HAL_SPI_Init+0x86>
}
else
{
frxth = SPI_RXFIFO_THRESHOLD_QF;
8003f08: f44f 5380 mov.w r3, #4096 ; 0x1000
8003f0c: 60fb str r3, [r7, #12]
}
/* CRC calculation is valid only for 16Bit and 8 Bit */
if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
8003f0e: 687b ldr r3, [r7, #4]
8003f10: 68db ldr r3, [r3, #12]
8003f12: f5b3 6f70 cmp.w r3, #3840 ; 0xf00
8003f16: d007 beq.n 8003f28 <HAL_SPI_Init+0xa0>
8003f18: 687b ldr r3, [r7, #4]
8003f1a: 68db ldr r3, [r3, #12]
8003f1c: f5b3 6fe0 cmp.w r3, #1792 ; 0x700
8003f20: d002 beq.n 8003f28 <HAL_SPI_Init+0xa0>
{
/* CRC must be disabled */
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8003f22: 687b ldr r3, [r7, #4]
8003f24: 2200 movs r2, #0
8003f26: 629a str r2, [r3, #40] ; 0x28
}
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
8003f28: 687b ldr r3, [r7, #4]
8003f2a: 685b ldr r3, [r3, #4]
8003f2c: f403 7282 and.w r2, r3, #260 ; 0x104
8003f30: 687b ldr r3, [r7, #4]
8003f32: 689b ldr r3, [r3, #8]
8003f34: f403 4304 and.w r3, r3, #33792 ; 0x8400
8003f38: 431a orrs r2, r3
8003f3a: 687b ldr r3, [r7, #4]
8003f3c: 691b ldr r3, [r3, #16]
8003f3e: f003 0302 and.w r3, r3, #2
8003f42: 431a orrs r2, r3
8003f44: 687b ldr r3, [r7, #4]
8003f46: 695b ldr r3, [r3, #20]
8003f48: f003 0301 and.w r3, r3, #1
8003f4c: 431a orrs r2, r3
8003f4e: 687b ldr r3, [r7, #4]
8003f50: 699b ldr r3, [r3, #24]
8003f52: f403 7300 and.w r3, r3, #512 ; 0x200
8003f56: 431a orrs r2, r3
8003f58: 687b ldr r3, [r7, #4]
8003f5a: 69db ldr r3, [r3, #28]
8003f5c: f003 0338 and.w r3, r3, #56 ; 0x38
8003f60: 431a orrs r2, r3
8003f62: 687b ldr r3, [r7, #4]
8003f64: 6a1b ldr r3, [r3, #32]
8003f66: f003 0380 and.w r3, r3, #128 ; 0x80
8003f6a: ea42 0103 orr.w r1, r2, r3
8003f6e: 687b ldr r3, [r7, #4]
8003f70: 6a9b ldr r3, [r3, #40] ; 0x28
8003f72: f403 5200 and.w r2, r3, #8192 ; 0x2000
8003f76: 687b ldr r3, [r7, #4]
8003f78: 681b ldr r3, [r3, #0]
8003f7a: 430a orrs r2, r1
8003f7c: 601a str r2, [r3, #0]
}
}
#endif /* USE_SPI_CRC */
/* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
8003f7e: 687b ldr r3, [r7, #4]
8003f80: 699b ldr r3, [r3, #24]
8003f82: 0c1b lsrs r3, r3, #16
8003f84: f003 0204 and.w r2, r3, #4
8003f88: 687b ldr r3, [r7, #4]
8003f8a: 6a5b ldr r3, [r3, #36] ; 0x24
8003f8c: f003 0310 and.w r3, r3, #16
8003f90: 431a orrs r2, r3
8003f92: 687b ldr r3, [r7, #4]
8003f94: 6b5b ldr r3, [r3, #52] ; 0x34
8003f96: f003 0308 and.w r3, r3, #8
8003f9a: 431a orrs r2, r3
8003f9c: 687b ldr r3, [r7, #4]
8003f9e: 68db ldr r3, [r3, #12]
8003fa0: f403 6370 and.w r3, r3, #3840 ; 0xf00
8003fa4: ea42 0103 orr.w r1, r2, r3
8003fa8: 68fb ldr r3, [r7, #12]
8003faa: f403 5280 and.w r2, r3, #4096 ; 0x1000
8003fae: 687b ldr r3, [r7, #4]
8003fb0: 681b ldr r3, [r3, #0]
8003fb2: 430a orrs r2, r1
8003fb4: 605a str r2, [r3, #4]
}
#endif /* USE_SPI_CRC */
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
8003fb6: 687b ldr r3, [r7, #4]
8003fb8: 681b ldr r3, [r3, #0]
8003fba: 69da ldr r2, [r3, #28]
8003fbc: 687b ldr r3, [r7, #4]
8003fbe: 681b ldr r3, [r3, #0]
8003fc0: f422 6200 bic.w r2, r2, #2048 ; 0x800
8003fc4: 61da str r2, [r3, #28]
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8003fc6: 687b ldr r3, [r7, #4]
8003fc8: 2200 movs r2, #0
8003fca: 661a str r2, [r3, #96] ; 0x60
hspi->State = HAL_SPI_STATE_READY;
8003fcc: 687b ldr r3, [r7, #4]
8003fce: 2201 movs r2, #1
8003fd0: f883 205d strb.w r2, [r3, #93] ; 0x5d
return HAL_OK;
8003fd4: 2300 movs r3, #0
}
8003fd6: 4618 mov r0, r3
8003fd8: 3710 adds r7, #16
8003fda: 46bd mov sp, r7
8003fdc: bd80 pop {r7, pc}
08003fde <HAL_SPI_TransmitReceive>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
uint32_t Timeout)
{
8003fde: b580 push {r7, lr}
8003fe0: b08a sub sp, #40 ; 0x28
8003fe2: af00 add r7, sp, #0
8003fe4: 60f8 str r0, [r7, #12]
8003fe6: 60b9 str r1, [r7, #8]
8003fe8: 607a str r2, [r7, #4]
8003fea: 807b strh r3, [r7, #2]
__IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
#endif /* USE_SPI_CRC */
/* Variable used to alternate Rx and Tx during transfer */
uint32_t txallowed = 1U;
8003fec: 2301 movs r3, #1
8003fee: 627b str r3, [r7, #36] ; 0x24
HAL_StatusTypeDef errorcode = HAL_OK;
8003ff0: 2300 movs r3, #0
8003ff2: f887 3023 strb.w r3, [r7, #35] ; 0x23
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
/* Process Locked */
__HAL_LOCK(hspi);
8003ff6: 68fb ldr r3, [r7, #12]
8003ff8: f893 305c ldrb.w r3, [r3, #92] ; 0x5c
8003ffc: 2b01 cmp r3, #1
8003ffe: d101 bne.n 8004004 <HAL_SPI_TransmitReceive+0x26>
8004000: 2302 movs r3, #2
8004002: e20a b.n 800441a <HAL_SPI_TransmitReceive+0x43c>
8004004: 68fb ldr r3, [r7, #12]
8004006: 2201 movs r2, #1
8004008: f883 205c strb.w r2, [r3, #92] ; 0x5c
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
800400c: f7fd fe3e bl 8001c8c <HAL_GetTick>
8004010: 61f8 str r0, [r7, #28]
/* Init temporary variables */
tmp_state = hspi->State;
8004012: 68fb ldr r3, [r7, #12]
8004014: f893 305d ldrb.w r3, [r3, #93] ; 0x5d
8004018: 76fb strb r3, [r7, #27]
tmp_mode = hspi->Init.Mode;
800401a: 68fb ldr r3, [r7, #12]
800401c: 685b ldr r3, [r3, #4]
800401e: 617b str r3, [r7, #20]
initial_TxXferCount = Size;
8004020: 887b ldrh r3, [r7, #2]
8004022: 827b strh r3, [r7, #18]
initial_RxXferCount = Size;
8004024: 887b ldrh r3, [r7, #2]
8004026: 823b strh r3, [r7, #16]
#if (USE_SPI_CRC != 0U)
spi_cr1 = READ_REG(hspi->Instance->CR1);
spi_cr2 = READ_REG(hspi->Instance->CR2);
#endif /* USE_SPI_CRC */
if (!((tmp_state == HAL_SPI_STATE_READY) || \
8004028: 7efb ldrb r3, [r7, #27]
800402a: 2b01 cmp r3, #1
800402c: d00e beq.n 800404c <HAL_SPI_TransmitReceive+0x6e>
800402e: 697b ldr r3, [r7, #20]
8004030: f5b3 7f82 cmp.w r3, #260 ; 0x104
8004034: d106 bne.n 8004044 <HAL_SPI_TransmitReceive+0x66>
((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
8004036: 68fb ldr r3, [r7, #12]
8004038: 689b ldr r3, [r3, #8]
800403a: 2b00 cmp r3, #0
800403c: d102 bne.n 8004044 <HAL_SPI_TransmitReceive+0x66>
800403e: 7efb ldrb r3, [r7, #27]
8004040: 2b04 cmp r3, #4
8004042: d003 beq.n 800404c <HAL_SPI_TransmitReceive+0x6e>
{
errorcode = HAL_BUSY;
8004044: 2302 movs r3, #2
8004046: f887 3023 strb.w r3, [r7, #35] ; 0x23
goto error;
800404a: e1e0 b.n 800440e <HAL_SPI_TransmitReceive+0x430>
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
800404c: 68bb ldr r3, [r7, #8]
800404e: 2b00 cmp r3, #0
8004050: d005 beq.n 800405e <HAL_SPI_TransmitReceive+0x80>
8004052: 687b ldr r3, [r7, #4]
8004054: 2b00 cmp r3, #0
8004056: d002 beq.n 800405e <HAL_SPI_TransmitReceive+0x80>
8004058: 887b ldrh r3, [r7, #2]
800405a: 2b00 cmp r3, #0
800405c: d103 bne.n 8004066 <HAL_SPI_TransmitReceive+0x88>
{
errorcode = HAL_ERROR;
800405e: 2301 movs r3, #1
8004060: f887 3023 strb.w r3, [r7, #35] ; 0x23
goto error;
8004064: e1d3 b.n 800440e <HAL_SPI_TransmitReceive+0x430>
}
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
8004066: 68fb ldr r3, [r7, #12]
8004068: f893 305d ldrb.w r3, [r3, #93] ; 0x5d
800406c: b2db uxtb r3, r3
800406e: 2b04 cmp r3, #4
8004070: d003 beq.n 800407a <HAL_SPI_TransmitReceive+0x9c>
{
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
8004072: 68fb ldr r3, [r7, #12]
8004074: 2205 movs r2, #5
8004076: f883 205d strb.w r2, [r3, #93] ; 0x5d
}
/* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
800407a: 68fb ldr r3, [r7, #12]
800407c: 2200 movs r2, #0
800407e: 661a str r2, [r3, #96] ; 0x60
hspi->pRxBuffPtr = (uint8_t *)pRxData;
8004080: 68fb ldr r3, [r7, #12]
8004082: 687a ldr r2, [r7, #4]
8004084: 641a str r2, [r3, #64] ; 0x40
hspi->RxXferCount = Size;
8004086: 68fb ldr r3, [r7, #12]
8004088: 887a ldrh r2, [r7, #2]
800408a: f8a3 2046 strh.w r2, [r3, #70] ; 0x46
hspi->RxXferSize = Size;
800408e: 68fb ldr r3, [r7, #12]
8004090: 887a ldrh r2, [r7, #2]
8004092: f8a3 2044 strh.w r2, [r3, #68] ; 0x44
hspi->pTxBuffPtr = (uint8_t *)pTxData;
8004096: 68fb ldr r3, [r7, #12]
8004098: 68ba ldr r2, [r7, #8]
800409a: 639a str r2, [r3, #56] ; 0x38
hspi->TxXferCount = Size;
800409c: 68fb ldr r3, [r7, #12]
800409e: 887a ldrh r2, [r7, #2]
80040a0: 87da strh r2, [r3, #62] ; 0x3e
hspi->TxXferSize = Size;
80040a2: 68fb ldr r3, [r7, #12]
80040a4: 887a ldrh r2, [r7, #2]
80040a6: 879a strh r2, [r3, #60] ; 0x3c
/*Init field not used in handle to zero */
hspi->RxISR = NULL;
80040a8: 68fb ldr r3, [r7, #12]
80040aa: 2200 movs r2, #0
80040ac: 64da str r2, [r3, #76] ; 0x4c
hspi->TxISR = NULL;
80040ae: 68fb ldr r3, [r7, #12]
80040b0: 2200 movs r2, #0
80040b2: 651a str r2, [r3, #80] ; 0x50
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Set the Rx Fifo threshold */
if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))
80040b4: 68fb ldr r3, [r7, #12]
80040b6: 68db ldr r3, [r3, #12]
80040b8: f5b3 6fe0 cmp.w r3, #1792 ; 0x700
80040bc: d802 bhi.n 80040c4 <HAL_SPI_TransmitReceive+0xe6>
80040be: 8a3b ldrh r3, [r7, #16]
80040c0: 2b01 cmp r3, #1
80040c2: d908 bls.n 80040d6 <HAL_SPI_TransmitReceive+0xf8>
{
/* Set fiforxthreshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
80040c4: 68fb ldr r3, [r7, #12]
80040c6: 681b ldr r3, [r3, #0]
80040c8: 685a ldr r2, [r3, #4]
80040ca: 68fb ldr r3, [r7, #12]
80040cc: 681b ldr r3, [r3, #0]
80040ce: f422 5280 bic.w r2, r2, #4096 ; 0x1000
80040d2: 605a str r2, [r3, #4]
80040d4: e007 b.n 80040e6 <HAL_SPI_TransmitReceive+0x108>
}
else
{
/* Set fiforxthreshold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
80040d6: 68fb ldr r3, [r7, #12]
80040d8: 681b ldr r3, [r3, #0]
80040da: 685a ldr r2, [r3, #4]
80040dc: 68fb ldr r3, [r7, #12]
80040de: 681b ldr r3, [r3, #0]
80040e0: f442 5280 orr.w r2, r2, #4096 ; 0x1000
80040e4: 605a str r2, [r3, #4]
}
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
80040e6: 68fb ldr r3, [r7, #12]
80040e8: 681b ldr r3, [r3, #0]
80040ea: 681b ldr r3, [r3, #0]
80040ec: f003 0340 and.w r3, r3, #64 ; 0x40
80040f0: 2b40 cmp r3, #64 ; 0x40
80040f2: d007 beq.n 8004104 <HAL_SPI_TransmitReceive+0x126>
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
80040f4: 68fb ldr r3, [r7, #12]
80040f6: 681b ldr r3, [r3, #0]
80040f8: 681a ldr r2, [r3, #0]
80040fa: 68fb ldr r3, [r7, #12]
80040fc: 681b ldr r3, [r3, #0]
80040fe: f042 0240 orr.w r2, r2, #64 ; 0x40
8004102: 601a str r2, [r3, #0]
}
/* Transmit and Receive data in 16 Bit mode */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
8004104: 68fb ldr r3, [r7, #12]
8004106: 68db ldr r3, [r3, #12]
8004108: f5b3 6fe0 cmp.w r3, #1792 ; 0x700
800410c: f240 8081 bls.w 8004212 <HAL_SPI_TransmitReceive+0x234>
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
8004110: 68fb ldr r3, [r7, #12]
8004112: 685b ldr r3, [r3, #4]
8004114: 2b00 cmp r3, #0
8004116: d002 beq.n 800411e <HAL_SPI_TransmitReceive+0x140>
8004118: 8a7b ldrh r3, [r7, #18]
800411a: 2b01 cmp r3, #1
800411c: d16d bne.n 80041fa <HAL_SPI_TransmitReceive+0x21c>
{
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
800411e: 68fb ldr r3, [r7, #12]
8004120: 6b9b ldr r3, [r3, #56] ; 0x38
8004122: 881a ldrh r2, [r3, #0]
8004124: 68fb ldr r3, [r7, #12]
8004126: 681b ldr r3, [r3, #0]
8004128: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
800412a: 68fb ldr r3, [r7, #12]
800412c: 6b9b ldr r3, [r3, #56] ; 0x38
800412e: 1c9a adds r2, r3, #2
8004130: 68fb ldr r3, [r7, #12]
8004132: 639a str r2, [r3, #56] ; 0x38
hspi->TxXferCount--;
8004134: 68fb ldr r3, [r7, #12]
8004136: 8fdb ldrh r3, [r3, #62] ; 0x3e
8004138: b29b uxth r3, r3
800413a: 3b01 subs r3, #1
800413c: b29a uxth r2, r3
800413e: 68fb ldr r3, [r7, #12]
8004140: 87da strh r2, [r3, #62] ; 0x3e
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
8004142: e05a b.n 80041fa <HAL_SPI_TransmitReceive+0x21c>
{
/* Check TXE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
8004144: 68fb ldr r3, [r7, #12]
8004146: 681b ldr r3, [r3, #0]
8004148: 689b ldr r3, [r3, #8]
800414a: f003 0302 and.w r3, r3, #2
800414e: 2b02 cmp r3, #2
8004150: d11b bne.n 800418a <HAL_SPI_TransmitReceive+0x1ac>
8004152: 68fb ldr r3, [r7, #12]
8004154: 8fdb ldrh r3, [r3, #62] ; 0x3e
8004156: b29b uxth r3, r3
8004158: 2b00 cmp r3, #0
800415a: d016 beq.n 800418a <HAL_SPI_TransmitReceive+0x1ac>
800415c: 6a7b ldr r3, [r7, #36] ; 0x24
800415e: 2b01 cmp r3, #1
8004160: d113 bne.n 800418a <HAL_SPI_TransmitReceive+0x1ac>
{
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
8004162: 68fb ldr r3, [r7, #12]
8004164: 6b9b ldr r3, [r3, #56] ; 0x38
8004166: 881a ldrh r2, [r3, #0]
8004168: 68fb ldr r3, [r7, #12]
800416a: 681b ldr r3, [r3, #0]
800416c: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
800416e: 68fb ldr r3, [r7, #12]
8004170: 6b9b ldr r3, [r3, #56] ; 0x38
8004172: 1c9a adds r2, r3, #2
8004174: 68fb ldr r3, [r7, #12]
8004176: 639a str r2, [r3, #56] ; 0x38
hspi->TxXferCount--;
8004178: 68fb ldr r3, [r7, #12]
800417a: 8fdb ldrh r3, [r3, #62] ; 0x3e
800417c: b29b uxth r3, r3
800417e: 3b01 subs r3, #1
8004180: b29a uxth r2, r3
8004182: 68fb ldr r3, [r7, #12]
8004184: 87da strh r2, [r3, #62] ; 0x3e
/* Next Data is a reception (Rx). Tx not allowed */
txallowed = 0U;
8004186: 2300 movs r3, #0
8004188: 627b str r3, [r7, #36] ; 0x24
}
#endif /* USE_SPI_CRC */
}
/* Check RXNE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
800418a: 68fb ldr r3, [r7, #12]
800418c: 681b ldr r3, [r3, #0]
800418e: 689b ldr r3, [r3, #8]
8004190: f003 0301 and.w r3, r3, #1
8004194: 2b01 cmp r3, #1
8004196: d11c bne.n 80041d2 <HAL_SPI_TransmitReceive+0x1f4>
8004198: 68fb ldr r3, [r7, #12]
800419a: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46
800419e: b29b uxth r3, r3
80041a0: 2b00 cmp r3, #0
80041a2: d016 beq.n 80041d2 <HAL_SPI_TransmitReceive+0x1f4>
{
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
80041a4: 68fb ldr r3, [r7, #12]
80041a6: 681b ldr r3, [r3, #0]
80041a8: 68da ldr r2, [r3, #12]
80041aa: 68fb ldr r3, [r7, #12]
80041ac: 6c1b ldr r3, [r3, #64] ; 0x40
80041ae: b292 uxth r2, r2
80041b0: 801a strh r2, [r3, #0]
hspi->pRxBuffPtr += sizeof(uint16_t);
80041b2: 68fb ldr r3, [r7, #12]
80041b4: 6c1b ldr r3, [r3, #64] ; 0x40
80041b6: 1c9a adds r2, r3, #2
80041b8: 68fb ldr r3, [r7, #12]
80041ba: 641a str r2, [r3, #64] ; 0x40
hspi->RxXferCount--;
80041bc: 68fb ldr r3, [r7, #12]
80041be: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46
80041c2: b29b uxth r3, r3
80041c4: 3b01 subs r3, #1
80041c6: b29a uxth r2, r3
80041c8: 68fb ldr r3, [r7, #12]
80041ca: f8a3 2046 strh.w r2, [r3, #70] ; 0x46
/* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
80041ce: 2301 movs r3, #1
80041d0: 627b str r3, [r7, #36] ; 0x24
}
if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
80041d2: f7fd fd5b bl 8001c8c <HAL_GetTick>
80041d6: 4602 mov r2, r0
80041d8: 69fb ldr r3, [r7, #28]
80041da: 1ad3 subs r3, r2, r3
80041dc: 6b3a ldr r2, [r7, #48] ; 0x30
80041de: 429a cmp r2, r3
80041e0: d80b bhi.n 80041fa <HAL_SPI_TransmitReceive+0x21c>
80041e2: 6b3b ldr r3, [r7, #48] ; 0x30
80041e4: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
80041e8: d007 beq.n 80041fa <HAL_SPI_TransmitReceive+0x21c>
{
errorcode = HAL_TIMEOUT;
80041ea: 2303 movs r3, #3
80041ec: f887 3023 strb.w r3, [r7, #35] ; 0x23
hspi->State = HAL_SPI_STATE_READY;
80041f0: 68fb ldr r3, [r7, #12]
80041f2: 2201 movs r2, #1
80041f4: f883 205d strb.w r2, [r3, #93] ; 0x5d
goto error;
80041f8: e109 b.n 800440e <HAL_SPI_TransmitReceive+0x430>
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
80041fa: 68fb ldr r3, [r7, #12]
80041fc: 8fdb ldrh r3, [r3, #62] ; 0x3e
80041fe: b29b uxth r3, r3
8004200: 2b00 cmp r3, #0
8004202: d19f bne.n 8004144 <HAL_SPI_TransmitReceive+0x166>
8004204: 68fb ldr r3, [r7, #12]
8004206: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46
800420a: b29b uxth r3, r3
800420c: 2b00 cmp r3, #0
800420e: d199 bne.n 8004144 <HAL_SPI_TransmitReceive+0x166>
8004210: e0e3 b.n 80043da <HAL_SPI_TransmitReceive+0x3fc>
}
}
/* Transmit and Receive data in 8 Bit mode */
else
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
8004212: 68fb ldr r3, [r7, #12]
8004214: 685b ldr r3, [r3, #4]
8004216: 2b00 cmp r3, #0
8004218: d003 beq.n 8004222 <HAL_SPI_TransmitReceive+0x244>
800421a: 8a7b ldrh r3, [r7, #18]
800421c: 2b01 cmp r3, #1
800421e: f040 80cf bne.w 80043c0 <HAL_SPI_TransmitReceive+0x3e2>
{
if (hspi->TxXferCount > 1U)
8004222: 68fb ldr r3, [r7, #12]
8004224: 8fdb ldrh r3, [r3, #62] ; 0x3e
8004226: b29b uxth r3, r3
8004228: 2b01 cmp r3, #1
800422a: d912 bls.n 8004252 <HAL_SPI_TransmitReceive+0x274>
{
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
800422c: 68fb ldr r3, [r7, #12]
800422e: 6b9b ldr r3, [r3, #56] ; 0x38
8004230: 881a ldrh r2, [r3, #0]
8004232: 68fb ldr r3, [r7, #12]
8004234: 681b ldr r3, [r3, #0]
8004236: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
8004238: 68fb ldr r3, [r7, #12]
800423a: 6b9b ldr r3, [r3, #56] ; 0x38
800423c: 1c9a adds r2, r3, #2
800423e: 68fb ldr r3, [r7, #12]
8004240: 639a str r2, [r3, #56] ; 0x38
hspi->TxXferCount -= 2U;
8004242: 68fb ldr r3, [r7, #12]
8004244: 8fdb ldrh r3, [r3, #62] ; 0x3e
8004246: b29b uxth r3, r3
8004248: 3b02 subs r3, #2
800424a: b29a uxth r2, r3
800424c: 68fb ldr r3, [r7, #12]
800424e: 87da strh r2, [r3, #62] ; 0x3e
8004250: e0b6 b.n 80043c0 <HAL_SPI_TransmitReceive+0x3e2>
}
else
{
*(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
8004252: 68fb ldr r3, [r7, #12]
8004254: 6b9a ldr r2, [r3, #56] ; 0x38
8004256: 68fb ldr r3, [r7, #12]
8004258: 681b ldr r3, [r3, #0]
800425a: 330c adds r3, #12
800425c: 7812 ldrb r2, [r2, #0]
800425e: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr++;
8004260: 68fb ldr r3, [r7, #12]
8004262: 6b9b ldr r3, [r3, #56] ; 0x38
8004264: 1c5a adds r2, r3, #1
8004266: 68fb ldr r3, [r7, #12]
8004268: 639a str r2, [r3, #56] ; 0x38
hspi->TxXferCount--;
800426a: 68fb ldr r3, [r7, #12]
800426c: 8fdb ldrh r3, [r3, #62] ; 0x3e
800426e: b29b uxth r3, r3
8004270: 3b01 subs r3, #1
8004272: b29a uxth r2, r3
8004274: 68fb ldr r3, [r7, #12]
8004276: 87da strh r2, [r3, #62] ; 0x3e
}
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
8004278: e0a2 b.n 80043c0 <HAL_SPI_TransmitReceive+0x3e2>
{
/* Check TXE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
800427a: 68fb ldr r3, [r7, #12]
800427c: 681b ldr r3, [r3, #0]
800427e: 689b ldr r3, [r3, #8]
8004280: f003 0302 and.w r3, r3, #2
8004284: 2b02 cmp r3, #2
8004286: d134 bne.n 80042f2 <HAL_SPI_TransmitReceive+0x314>
8004288: 68fb ldr r3, [r7, #12]
800428a: 8fdb ldrh r3, [r3, #62] ; 0x3e
800428c: b29b uxth r3, r3
800428e: 2b00 cmp r3, #0
8004290: d02f beq.n 80042f2 <HAL_SPI_TransmitReceive+0x314>
8004292: 6a7b ldr r3, [r7, #36] ; 0x24
8004294: 2b01 cmp r3, #1
8004296: d12c bne.n 80042f2 <HAL_SPI_TransmitReceive+0x314>
{
if (hspi->TxXferCount > 1U)
8004298: 68fb ldr r3, [r7, #12]
800429a: 8fdb ldrh r3, [r3, #62] ; 0x3e
800429c: b29b uxth r3, r3
800429e: 2b01 cmp r3, #1
80042a0: d912 bls.n 80042c8 <HAL_SPI_TransmitReceive+0x2ea>
{
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
80042a2: 68fb ldr r3, [r7, #12]
80042a4: 6b9b ldr r3, [r3, #56] ; 0x38
80042a6: 881a ldrh r2, [r3, #0]
80042a8: 68fb ldr r3, [r7, #12]
80042aa: 681b ldr r3, [r3, #0]
80042ac: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
80042ae: 68fb ldr r3, [r7, #12]
80042b0: 6b9b ldr r3, [r3, #56] ; 0x38
80042b2: 1c9a adds r2, r3, #2
80042b4: 68fb ldr r3, [r7, #12]
80042b6: 639a str r2, [r3, #56] ; 0x38
hspi->TxXferCount -= 2U;
80042b8: 68fb ldr r3, [r7, #12]
80042ba: 8fdb ldrh r3, [r3, #62] ; 0x3e
80042bc: b29b uxth r3, r3
80042be: 3b02 subs r3, #2
80042c0: b29a uxth r2, r3
80042c2: 68fb ldr r3, [r7, #12]
80042c4: 87da strh r2, [r3, #62] ; 0x3e
80042c6: e012 b.n 80042ee <HAL_SPI_TransmitReceive+0x310>
}
else
{
*(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
80042c8: 68fb ldr r3, [r7, #12]
80042ca: 6b9a ldr r2, [r3, #56] ; 0x38
80042cc: 68fb ldr r3, [r7, #12]
80042ce: 681b ldr r3, [r3, #0]
80042d0: 330c adds r3, #12
80042d2: 7812 ldrb r2, [r2, #0]
80042d4: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr++;
80042d6: 68fb ldr r3, [r7, #12]
80042d8: 6b9b ldr r3, [r3, #56] ; 0x38
80042da: 1c5a adds r2, r3, #1
80042dc: 68fb ldr r3, [r7, #12]
80042de: 639a str r2, [r3, #56] ; 0x38
hspi->TxXferCount--;
80042e0: 68fb ldr r3, [r7, #12]
80042e2: 8fdb ldrh r3, [r3, #62] ; 0x3e
80042e4: b29b uxth r3, r3
80042e6: 3b01 subs r3, #1
80042e8: b29a uxth r2, r3
80042ea: 68fb ldr r3, [r7, #12]
80042ec: 87da strh r2, [r3, #62] ; 0x3e
}
/* Next Data is a reception (Rx). Tx not allowed */
txallowed = 0U;
80042ee: 2300 movs r3, #0
80042f0: 627b str r3, [r7, #36] ; 0x24
}
#endif /* USE_SPI_CRC */
}
/* Wait until RXNE flag is reset */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
80042f2: 68fb ldr r3, [r7, #12]
80042f4: 681b ldr r3, [r3, #0]
80042f6: 689b ldr r3, [r3, #8]
80042f8: f003 0301 and.w r3, r3, #1
80042fc: 2b01 cmp r3, #1
80042fe: d148 bne.n 8004392 <HAL_SPI_TransmitReceive+0x3b4>
8004300: 68fb ldr r3, [r7, #12]
8004302: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46
8004306: b29b uxth r3, r3
8004308: 2b00 cmp r3, #0
800430a: d042 beq.n 8004392 <HAL_SPI_TransmitReceive+0x3b4>
{
if (hspi->RxXferCount > 1U)
800430c: 68fb ldr r3, [r7, #12]
800430e: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46
8004312: b29b uxth r3, r3
8004314: 2b01 cmp r3, #1
8004316: d923 bls.n 8004360 <HAL_SPI_TransmitReceive+0x382>
{
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
8004318: 68fb ldr r3, [r7, #12]
800431a: 681b ldr r3, [r3, #0]
800431c: 68da ldr r2, [r3, #12]
800431e: 68fb ldr r3, [r7, #12]
8004320: 6c1b ldr r3, [r3, #64] ; 0x40
8004322: b292 uxth r2, r2
8004324: 801a strh r2, [r3, #0]
hspi->pRxBuffPtr += sizeof(uint16_t);
8004326: 68fb ldr r3, [r7, #12]
8004328: 6c1b ldr r3, [r3, #64] ; 0x40
800432a: 1c9a adds r2, r3, #2
800432c: 68fb ldr r3, [r7, #12]
800432e: 641a str r2, [r3, #64] ; 0x40
hspi->RxXferCount -= 2U;
8004330: 68fb ldr r3, [r7, #12]
8004332: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46
8004336: b29b uxth r3, r3
8004338: 3b02 subs r3, #2
800433a: b29a uxth r2, r3
800433c: 68fb ldr r3, [r7, #12]
800433e: f8a3 2046 strh.w r2, [r3, #70] ; 0x46
if (hspi->RxXferCount <= 1U)
8004342: 68fb ldr r3, [r7, #12]
8004344: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46
8004348: b29b uxth r3, r3
800434a: 2b01 cmp r3, #1
800434c: d81f bhi.n 800438e <HAL_SPI_TransmitReceive+0x3b0>
{
/* Set RX Fifo threshold before to switch on 8 bit data size */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
800434e: 68fb ldr r3, [r7, #12]
8004350: 681b ldr r3, [r3, #0]
8004352: 685a ldr r2, [r3, #4]
8004354: 68fb ldr r3, [r7, #12]
8004356: 681b ldr r3, [r3, #0]
8004358: f442 5280 orr.w r2, r2, #4096 ; 0x1000
800435c: 605a str r2, [r3, #4]
800435e: e016 b.n 800438e <HAL_SPI_TransmitReceive+0x3b0>
}
}
else
{
(*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
8004360: 68fb ldr r3, [r7, #12]
8004362: 681b ldr r3, [r3, #0]
8004364: f103 020c add.w r2, r3, #12
8004368: 68fb ldr r3, [r7, #12]
800436a: 6c1b ldr r3, [r3, #64] ; 0x40
800436c: 7812 ldrb r2, [r2, #0]
800436e: b2d2 uxtb r2, r2
8004370: 701a strb r2, [r3, #0]
hspi->pRxBuffPtr++;
8004372: 68fb ldr r3, [r7, #12]
8004374: 6c1b ldr r3, [r3, #64] ; 0x40
8004376: 1c5a adds r2, r3, #1
8004378: 68fb ldr r3, [r7, #12]
800437a: 641a str r2, [r3, #64] ; 0x40
hspi->RxXferCount--;
800437c: 68fb ldr r3, [r7, #12]
800437e: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46
8004382: b29b uxth r3, r3
8004384: 3b01 subs r3, #1
8004386: b29a uxth r2, r3
8004388: 68fb ldr r3, [r7, #12]
800438a: f8a3 2046 strh.w r2, [r3, #70] ; 0x46
}
/* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
800438e: 2301 movs r3, #1
8004390: 627b str r3, [r7, #36] ; 0x24
}
if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
8004392: f7fd fc7b bl 8001c8c <HAL_GetTick>
8004396: 4602 mov r2, r0
8004398: 69fb ldr r3, [r7, #28]
800439a: 1ad3 subs r3, r2, r3
800439c: 6b3a ldr r2, [r7, #48] ; 0x30
800439e: 429a cmp r2, r3
80043a0: d803 bhi.n 80043aa <HAL_SPI_TransmitReceive+0x3cc>
80043a2: 6b3b ldr r3, [r7, #48] ; 0x30
80043a4: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
80043a8: d102 bne.n 80043b0 <HAL_SPI_TransmitReceive+0x3d2>
80043aa: 6b3b ldr r3, [r7, #48] ; 0x30
80043ac: 2b00 cmp r3, #0
80043ae: d107 bne.n 80043c0 <HAL_SPI_TransmitReceive+0x3e2>
{
errorcode = HAL_TIMEOUT;
80043b0: 2303 movs r3, #3
80043b2: f887 3023 strb.w r3, [r7, #35] ; 0x23
hspi->State = HAL_SPI_STATE_READY;
80043b6: 68fb ldr r3, [r7, #12]
80043b8: 2201 movs r2, #1
80043ba: f883 205d strb.w r2, [r3, #93] ; 0x5d
goto error;
80043be: e026 b.n 800440e <HAL_SPI_TransmitReceive+0x430>
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
80043c0: 68fb ldr r3, [r7, #12]
80043c2: 8fdb ldrh r3, [r3, #62] ; 0x3e
80043c4: b29b uxth r3, r3
80043c6: 2b00 cmp r3, #0
80043c8: f47f af57 bne.w 800427a <HAL_SPI_TransmitReceive+0x29c>
80043cc: 68fb ldr r3, [r7, #12]
80043ce: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46
80043d2: b29b uxth r3, r3
80043d4: 2b00 cmp r3, #0
80043d6: f47f af50 bne.w 800427a <HAL_SPI_TransmitReceive+0x29c>
errorcode = HAL_ERROR;
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
80043da: 69fa ldr r2, [r7, #28]
80043dc: 6b39 ldr r1, [r7, #48] ; 0x30
80043de: 68f8 ldr r0, [r7, #12]
80043e0: f000 f93e bl 8004660 <SPI_EndRxTxTransaction>
80043e4: 4603 mov r3, r0
80043e6: 2b00 cmp r3, #0
80043e8: d005 beq.n 80043f6 <HAL_SPI_TransmitReceive+0x418>
{
errorcode = HAL_ERROR;
80043ea: 2301 movs r3, #1
80043ec: f887 3023 strb.w r3, [r7, #35] ; 0x23
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
80043f0: 68fb ldr r3, [r7, #12]
80043f2: 2220 movs r2, #32
80043f4: 661a str r2, [r3, #96] ; 0x60
}
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
80043f6: 68fb ldr r3, [r7, #12]
80043f8: 6e1b ldr r3, [r3, #96] ; 0x60
80043fa: 2b00 cmp r3, #0
80043fc: d003 beq.n 8004406 <HAL_SPI_TransmitReceive+0x428>
{
errorcode = HAL_ERROR;
80043fe: 2301 movs r3, #1
8004400: f887 3023 strb.w r3, [r7, #35] ; 0x23
8004404: e003 b.n 800440e <HAL_SPI_TransmitReceive+0x430>
}
else
{
hspi->State = HAL_SPI_STATE_READY;
8004406: 68fb ldr r3, [r7, #12]
8004408: 2201 movs r2, #1
800440a: f883 205d strb.w r2, [r3, #93] ; 0x5d
}
error :
__HAL_UNLOCK(hspi);
800440e: 68fb ldr r3, [r7, #12]
8004410: 2200 movs r2, #0
8004412: f883 205c strb.w r2, [r3, #92] ; 0x5c
return errorcode;
8004416: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
}
800441a: 4618 mov r0, r3
800441c: 3728 adds r7, #40 ; 0x28
800441e: 46bd mov sp, r7
8004420: bd80 pop {r7, pc}
...
08004424 <SPI_WaitFlagStateUntilTimeout>:
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
uint32_t Timeout, uint32_t Tickstart)
{
8004424: b580 push {r7, lr}
8004426: b088 sub sp, #32
8004428: af00 add r7, sp, #0
800442a: 60f8 str r0, [r7, #12]
800442c: 60b9 str r1, [r7, #8]
800442e: 603b str r3, [r7, #0]
8004430: 4613 mov r3, r2
8004432: 71fb strb r3, [r7, #7]
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
/* Adjust Timeout value in case of end of transfer */
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
8004434: f7fd fc2a bl 8001c8c <HAL_GetTick>
8004438: 4602 mov r2, r0
800443a: 6abb ldr r3, [r7, #40] ; 0x28
800443c: 1a9b subs r3, r3, r2
800443e: 683a ldr r2, [r7, #0]
8004440: 4413 add r3, r2
8004442: 61fb str r3, [r7, #28]
tmp_tickstart = HAL_GetTick();
8004444: f7fd fc22 bl 8001c8c <HAL_GetTick>
8004448: 61b8 str r0, [r7, #24]
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
800444a: 4b39 ldr r3, [pc, #228] ; (8004530 <SPI_WaitFlagStateUntilTimeout+0x10c>)
800444c: 681b ldr r3, [r3, #0]
800444e: 015b lsls r3, r3, #5
8004450: 0d1b lsrs r3, r3, #20
8004452: 69fa ldr r2, [r7, #28]
8004454: fb02 f303 mul.w r3, r2, r3
8004458: 617b str r3, [r7, #20]
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
800445a: e054 b.n 8004506 <SPI_WaitFlagStateUntilTimeout+0xe2>
{
if (Timeout != HAL_MAX_DELAY)
800445c: 683b ldr r3, [r7, #0]
800445e: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
8004462: d050 beq.n 8004506 <SPI_WaitFlagStateUntilTimeout+0xe2>
{
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
8004464: f7fd fc12 bl 8001c8c <HAL_GetTick>
8004468: 4602 mov r2, r0
800446a: 69bb ldr r3, [r7, #24]
800446c: 1ad3 subs r3, r2, r3
800446e: 69fa ldr r2, [r7, #28]
8004470: 429a cmp r2, r3
8004472: d902 bls.n 800447a <SPI_WaitFlagStateUntilTimeout+0x56>
8004474: 69fb ldr r3, [r7, #28]
8004476: 2b00 cmp r3, #0
8004478: d13d bne.n 80044f6 <SPI_WaitFlagStateUntilTimeout+0xd2>
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
800447a: 68fb ldr r3, [r7, #12]
800447c: 681b ldr r3, [r3, #0]
800447e: 685a ldr r2, [r3, #4]
8004480: 68fb ldr r3, [r7, #12]
8004482: 681b ldr r3, [r3, #0]
8004484: f022 02e0 bic.w r2, r2, #224 ; 0xe0
8004488: 605a str r2, [r3, #4]
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
800448a: 68fb ldr r3, [r7, #12]
800448c: 685b ldr r3, [r3, #4]
800448e: f5b3 7f82 cmp.w r3, #260 ; 0x104
8004492: d111 bne.n 80044b8 <SPI_WaitFlagStateUntilTimeout+0x94>
8004494: 68fb ldr r3, [r7, #12]
8004496: 689b ldr r3, [r3, #8]
8004498: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
800449c: d004 beq.n 80044a8 <SPI_WaitFlagStateUntilTimeout+0x84>
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
800449e: 68fb ldr r3, [r7, #12]
80044a0: 689b ldr r3, [r3, #8]
80044a2: f5b3 6f80 cmp.w r3, #1024 ; 0x400
80044a6: d107 bne.n 80044b8 <SPI_WaitFlagStateUntilTimeout+0x94>
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
80044a8: 68fb ldr r3, [r7, #12]
80044aa: 681b ldr r3, [r3, #0]
80044ac: 681a ldr r2, [r3, #0]
80044ae: 68fb ldr r3, [r7, #12]
80044b0: 681b ldr r3, [r3, #0]
80044b2: f022 0240 bic.w r2, r2, #64 ; 0x40
80044b6: 601a str r2, [r3, #0]
}
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
80044b8: 68fb ldr r3, [r7, #12]
80044ba: 6a9b ldr r3, [r3, #40] ; 0x28
80044bc: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
80044c0: d10f bne.n 80044e2 <SPI_WaitFlagStateUntilTimeout+0xbe>
{
SPI_RESET_CRC(hspi);
80044c2: 68fb ldr r3, [r7, #12]
80044c4: 681b ldr r3, [r3, #0]
80044c6: 681a ldr r2, [r3, #0]
80044c8: 68fb ldr r3, [r7, #12]
80044ca: 681b ldr r3, [r3, #0]
80044cc: f422 5200 bic.w r2, r2, #8192 ; 0x2000
80044d0: 601a str r2, [r3, #0]
80044d2: 68fb ldr r3, [r7, #12]
80044d4: 681b ldr r3, [r3, #0]
80044d6: 681a ldr r2, [r3, #0]
80044d8: 68fb ldr r3, [r7, #12]
80044da: 681b ldr r3, [r3, #0]
80044dc: f442 5200 orr.w r2, r2, #8192 ; 0x2000
80044e0: 601a str r2, [r3, #0]
}
hspi->State = HAL_SPI_STATE_READY;
80044e2: 68fb ldr r3, [r7, #12]
80044e4: 2201 movs r2, #1
80044e6: f883 205d strb.w r2, [r3, #93] ; 0x5d
/* Process Unlocked */
__HAL_UNLOCK(hspi);
80044ea: 68fb ldr r3, [r7, #12]
80044ec: 2200 movs r2, #0
80044ee: f883 205c strb.w r2, [r3, #92] ; 0x5c
return HAL_TIMEOUT;
80044f2: 2303 movs r3, #3
80044f4: e017 b.n 8004526 <SPI_WaitFlagStateUntilTimeout+0x102>
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
if (count == 0U)
80044f6: 697b ldr r3, [r7, #20]
80044f8: 2b00 cmp r3, #0
80044fa: d101 bne.n 8004500 <SPI_WaitFlagStateUntilTimeout+0xdc>
{
tmp_timeout = 0U;
80044fc: 2300 movs r3, #0
80044fe: 61fb str r3, [r7, #28]
}
count--;
8004500: 697b ldr r3, [r7, #20]
8004502: 3b01 subs r3, #1
8004504: 617b str r3, [r7, #20]
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
8004506: 68fb ldr r3, [r7, #12]
8004508: 681b ldr r3, [r3, #0]
800450a: 689a ldr r2, [r3, #8]
800450c: 68bb ldr r3, [r7, #8]
800450e: 4013 ands r3, r2
8004510: 68ba ldr r2, [r7, #8]
8004512: 429a cmp r2, r3
8004514: bf0c ite eq
8004516: 2301 moveq r3, #1
8004518: 2300 movne r3, #0
800451a: b2db uxtb r3, r3
800451c: 461a mov r2, r3
800451e: 79fb ldrb r3, [r7, #7]
8004520: 429a cmp r2, r3
8004522: d19b bne.n 800445c <SPI_WaitFlagStateUntilTimeout+0x38>
}
}
return HAL_OK;
8004524: 2300 movs r3, #0
}
8004526: 4618 mov r0, r3
8004528: 3720 adds r7, #32
800452a: 46bd mov sp, r7
800452c: bd80 pop {r7, pc}
800452e: bf00 nop
8004530: 20000000 .word 0x20000000
08004534 <SPI_WaitFifoStateUntilTimeout>:
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
uint32_t Timeout, uint32_t Tickstart)
{
8004534: b580 push {r7, lr}
8004536: b08a sub sp, #40 ; 0x28
8004538: af00 add r7, sp, #0
800453a: 60f8 str r0, [r7, #12]
800453c: 60b9 str r1, [r7, #8]
800453e: 607a str r2, [r7, #4]
8004540: 603b str r3, [r7, #0]
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
__IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
8004542: 2300 movs r3, #0
8004544: 75fb strb r3, [r7, #23]
/* Adjust Timeout value in case of end of transfer */
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
8004546: f7fd fba1 bl 8001c8c <HAL_GetTick>
800454a: 4602 mov r2, r0
800454c: 6b3b ldr r3, [r7, #48] ; 0x30
800454e: 1a9b subs r3, r3, r2
8004550: 683a ldr r2, [r7, #0]
8004552: 4413 add r3, r2
8004554: 627b str r3, [r7, #36] ; 0x24
tmp_tickstart = HAL_GetTick();
8004556: f7fd fb99 bl 8001c8c <HAL_GetTick>
800455a: 6238 str r0, [r7, #32]
/* Initialize the 8bit temporary pointer */
ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
800455c: 68fb ldr r3, [r7, #12]
800455e: 681b ldr r3, [r3, #0]
8004560: 330c adds r3, #12
8004562: 61fb str r3, [r7, #28]
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
8004564: 4b3d ldr r3, [pc, #244] ; (800465c <SPI_WaitFifoStateUntilTimeout+0x128>)
8004566: 681a ldr r2, [r3, #0]
8004568: 4613 mov r3, r2
800456a: 009b lsls r3, r3, #2
800456c: 4413 add r3, r2
800456e: 00da lsls r2, r3, #3
8004570: 1ad3 subs r3, r2, r3
8004572: 0d1b lsrs r3, r3, #20
8004574: 6a7a ldr r2, [r7, #36] ; 0x24
8004576: fb02 f303 mul.w r3, r2, r3
800457a: 61bb str r3, [r7, #24]
while ((hspi->Instance->SR & Fifo) != State)
800457c: e060 b.n 8004640 <SPI_WaitFifoStateUntilTimeout+0x10c>
{
if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
800457e: 68bb ldr r3, [r7, #8]
8004580: f5b3 6fc0 cmp.w r3, #1536 ; 0x600
8004584: d107 bne.n 8004596 <SPI_WaitFifoStateUntilTimeout+0x62>
8004586: 687b ldr r3, [r7, #4]
8004588: 2b00 cmp r3, #0
800458a: d104 bne.n 8004596 <SPI_WaitFifoStateUntilTimeout+0x62>
{
/* Flush Data Register by a blank read */
tmpreg8 = *ptmpreg8;
800458c: 69fb ldr r3, [r7, #28]
800458e: 781b ldrb r3, [r3, #0]
8004590: b2db uxtb r3, r3
8004592: 75fb strb r3, [r7, #23]
/* To avoid GCC warning */
UNUSED(tmpreg8);
8004594: 7dfb ldrb r3, [r7, #23]
}
if (Timeout != HAL_MAX_DELAY)
8004596: 683b ldr r3, [r7, #0]
8004598: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800459c: d050 beq.n 8004640 <SPI_WaitFifoStateUntilTimeout+0x10c>
{
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
800459e: f7fd fb75 bl 8001c8c <HAL_GetTick>
80045a2: 4602 mov r2, r0
80045a4: 6a3b ldr r3, [r7, #32]
80045a6: 1ad3 subs r3, r2, r3
80045a8: 6a7a ldr r2, [r7, #36] ; 0x24
80045aa: 429a cmp r2, r3
80045ac: d902 bls.n 80045b4 <SPI_WaitFifoStateUntilTimeout+0x80>
80045ae: 6a7b ldr r3, [r7, #36] ; 0x24
80045b0: 2b00 cmp r3, #0
80045b2: d13d bne.n 8004630 <SPI_WaitFifoStateUntilTimeout+0xfc>
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
80045b4: 68fb ldr r3, [r7, #12]
80045b6: 681b ldr r3, [r3, #0]
80045b8: 685a ldr r2, [r3, #4]
80045ba: 68fb ldr r3, [r7, #12]
80045bc: 681b ldr r3, [r3, #0]
80045be: f022 02e0 bic.w r2, r2, #224 ; 0xe0
80045c2: 605a str r2, [r3, #4]
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
80045c4: 68fb ldr r3, [r7, #12]
80045c6: 685b ldr r3, [r3, #4]
80045c8: f5b3 7f82 cmp.w r3, #260 ; 0x104
80045cc: d111 bne.n 80045f2 <SPI_WaitFifoStateUntilTimeout+0xbe>
80045ce: 68fb ldr r3, [r7, #12]
80045d0: 689b ldr r3, [r3, #8]
80045d2: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
80045d6: d004 beq.n 80045e2 <SPI_WaitFifoStateUntilTimeout+0xae>
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
80045d8: 68fb ldr r3, [r7, #12]
80045da: 689b ldr r3, [r3, #8]
80045dc: f5b3 6f80 cmp.w r3, #1024 ; 0x400
80045e0: d107 bne.n 80045f2 <SPI_WaitFifoStateUntilTimeout+0xbe>
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
80045e2: 68fb ldr r3, [r7, #12]
80045e4: 681b ldr r3, [r3, #0]
80045e6: 681a ldr r2, [r3, #0]
80045e8: 68fb ldr r3, [r7, #12]
80045ea: 681b ldr r3, [r3, #0]
80045ec: f022 0240 bic.w r2, r2, #64 ; 0x40
80045f0: 601a str r2, [r3, #0]
}
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
80045f2: 68fb ldr r3, [r7, #12]
80045f4: 6a9b ldr r3, [r3, #40] ; 0x28
80045f6: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
80045fa: d10f bne.n 800461c <SPI_WaitFifoStateUntilTimeout+0xe8>
{
SPI_RESET_CRC(hspi);
80045fc: 68fb ldr r3, [r7, #12]
80045fe: 681b ldr r3, [r3, #0]
8004600: 681a ldr r2, [r3, #0]
8004602: 68fb ldr r3, [r7, #12]
8004604: 681b ldr r3, [r3, #0]
8004606: f422 5200 bic.w r2, r2, #8192 ; 0x2000
800460a: 601a str r2, [r3, #0]
800460c: 68fb ldr r3, [r7, #12]
800460e: 681b ldr r3, [r3, #0]
8004610: 681a ldr r2, [r3, #0]
8004612: 68fb ldr r3, [r7, #12]
8004614: 681b ldr r3, [r3, #0]
8004616: f442 5200 orr.w r2, r2, #8192 ; 0x2000
800461a: 601a str r2, [r3, #0]
}
hspi->State = HAL_SPI_STATE_READY;
800461c: 68fb ldr r3, [r7, #12]
800461e: 2201 movs r2, #1
8004620: f883 205d strb.w r2, [r3, #93] ; 0x5d
/* Process Unlocked */
__HAL_UNLOCK(hspi);
8004624: 68fb ldr r3, [r7, #12]
8004626: 2200 movs r2, #0
8004628: f883 205c strb.w r2, [r3, #92] ; 0x5c
return HAL_TIMEOUT;
800462c: 2303 movs r3, #3
800462e: e010 b.n 8004652 <SPI_WaitFifoStateUntilTimeout+0x11e>
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
if (count == 0U)
8004630: 69bb ldr r3, [r7, #24]
8004632: 2b00 cmp r3, #0
8004634: d101 bne.n 800463a <SPI_WaitFifoStateUntilTimeout+0x106>
{
tmp_timeout = 0U;
8004636: 2300 movs r3, #0
8004638: 627b str r3, [r7, #36] ; 0x24
}
count--;
800463a: 69bb ldr r3, [r7, #24]
800463c: 3b01 subs r3, #1
800463e: 61bb str r3, [r7, #24]
while ((hspi->Instance->SR & Fifo) != State)
8004640: 68fb ldr r3, [r7, #12]
8004642: 681b ldr r3, [r3, #0]
8004644: 689a ldr r2, [r3, #8]
8004646: 68bb ldr r3, [r7, #8]
8004648: 4013 ands r3, r2
800464a: 687a ldr r2, [r7, #4]
800464c: 429a cmp r2, r3
800464e: d196 bne.n 800457e <SPI_WaitFifoStateUntilTimeout+0x4a>
}
}
return HAL_OK;
8004650: 2300 movs r3, #0
}
8004652: 4618 mov r0, r3
8004654: 3728 adds r7, #40 ; 0x28
8004656: 46bd mov sp, r7
8004658: bd80 pop {r7, pc}
800465a: bf00 nop
800465c: 20000000 .word 0x20000000
08004660 <SPI_EndRxTxTransaction>:
* @param Timeout Timeout duration
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
8004660: b580 push {r7, lr}
8004662: b086 sub sp, #24
8004664: af02 add r7, sp, #8
8004666: 60f8 str r0, [r7, #12]
8004668: 60b9 str r1, [r7, #8]
800466a: 607a str r2, [r7, #4]
/* Control if the TX fifo is empty */
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
800466c: 687b ldr r3, [r7, #4]
800466e: 9300 str r3, [sp, #0]
8004670: 68bb ldr r3, [r7, #8]
8004672: 2200 movs r2, #0
8004674: f44f 51c0 mov.w r1, #6144 ; 0x1800
8004678: 68f8 ldr r0, [r7, #12]
800467a: f7ff ff5b bl 8004534 <SPI_WaitFifoStateUntilTimeout>
800467e: 4603 mov r3, r0
8004680: 2b00 cmp r3, #0
8004682: d007 beq.n 8004694 <SPI_EndRxTxTransaction+0x34>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
8004684: 68fb ldr r3, [r7, #12]
8004686: 6e1b ldr r3, [r3, #96] ; 0x60
8004688: f043 0220 orr.w r2, r3, #32
800468c: 68fb ldr r3, [r7, #12]
800468e: 661a str r2, [r3, #96] ; 0x60
return HAL_TIMEOUT;
8004690: 2303 movs r3, #3
8004692: e027 b.n 80046e4 <SPI_EndRxTxTransaction+0x84>
}
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
8004694: 687b ldr r3, [r7, #4]
8004696: 9300 str r3, [sp, #0]
8004698: 68bb ldr r3, [r7, #8]
800469a: 2200 movs r2, #0
800469c: 2180 movs r1, #128 ; 0x80
800469e: 68f8 ldr r0, [r7, #12]
80046a0: f7ff fec0 bl 8004424 <SPI_WaitFlagStateUntilTimeout>
80046a4: 4603 mov r3, r0
80046a6: 2b00 cmp r3, #0
80046a8: d007 beq.n 80046ba <SPI_EndRxTxTransaction+0x5a>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
80046aa: 68fb ldr r3, [r7, #12]
80046ac: 6e1b ldr r3, [r3, #96] ; 0x60
80046ae: f043 0220 orr.w r2, r3, #32
80046b2: 68fb ldr r3, [r7, #12]
80046b4: 661a str r2, [r3, #96] ; 0x60
return HAL_TIMEOUT;
80046b6: 2303 movs r3, #3
80046b8: e014 b.n 80046e4 <SPI_EndRxTxTransaction+0x84>
}
/* Control if the RX fifo is empty */
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
80046ba: 687b ldr r3, [r7, #4]
80046bc: 9300 str r3, [sp, #0]
80046be: 68bb ldr r3, [r7, #8]
80046c0: 2200 movs r2, #0
80046c2: f44f 61c0 mov.w r1, #1536 ; 0x600
80046c6: 68f8 ldr r0, [r7, #12]
80046c8: f7ff ff34 bl 8004534 <SPI_WaitFifoStateUntilTimeout>
80046cc: 4603 mov r3, r0
80046ce: 2b00 cmp r3, #0
80046d0: d007 beq.n 80046e2 <SPI_EndRxTxTransaction+0x82>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
80046d2: 68fb ldr r3, [r7, #12]
80046d4: 6e1b ldr r3, [r3, #96] ; 0x60
80046d6: f043 0220 orr.w r2, r3, #32
80046da: 68fb ldr r3, [r7, #12]
80046dc: 661a str r2, [r3, #96] ; 0x60
return HAL_TIMEOUT;
80046de: 2303 movs r3, #3
80046e0: e000 b.n 80046e4 <SPI_EndRxTxTransaction+0x84>
}
return HAL_OK;
80046e2: 2300 movs r3, #0
}
80046e4: 4618 mov r0, r3
80046e6: 3710 adds r7, #16
80046e8: 46bd mov sp, r7
80046ea: bd80 pop {r7, pc}
080046ec <_init>:
80046ec: b5f8 push {r3, r4, r5, r6, r7, lr}
80046ee: bf00 nop
80046f0: bcf8 pop {r3, r4, r5, r6, r7}
80046f2: bc08 pop {r3}
80046f4: 469e mov lr, r3
80046f6: 4770 bx lr
080046f8 <_fini>:
80046f8: b5f8 push {r3, r4, r5, r6, r7, lr}
80046fa: bf00 nop
80046fc: bcf8 pop {r3, r4, r5, r6, r7}
80046fe: bc08 pop {r3}
8004700: 469e mov lr, r3
8004702: 4770 bx lr
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