video: Update drm_fourcc.h
To drm-misc-next at commit e252e3f3488a492, in order to include new FOURCCs for SW-decoders. Part-of: <https://gitlab.freedesktop.org/gstreamer/gstreamer/-/merge_requests/8965>
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@ -377,6 +377,42 @@ extern "C" {
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*/
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#define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
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/*
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* 3 plane YCbCr LSB aligned
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* In order to use these formats in a similar fashion to MSB aligned ones
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* implementation can multiply the values by 2^6=64. For that reason the padding
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* must only contain zeros.
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* index 0 = Y plane, [15:0] z:Y [6:10] little endian
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* index 1 = Cr plane, [15:0] z:Cr [6:10] little endian
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* index 2 = Cb plane, [15:0] z:Cb [6:10] little endian
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*/
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#define DRM_FORMAT_S010 fourcc_code('S', '0', '1', '0') /* 2x2 subsampled Cb (1) and Cr (2) planes 10 bits per channel */
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#define DRM_FORMAT_S210 fourcc_code('S', '2', '1', '0') /* 2x1 subsampled Cb (1) and Cr (2) planes 10 bits per channel */
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#define DRM_FORMAT_S410 fourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes 10 bits per channel */
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/*
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* 3 plane YCbCr LSB aligned
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* In order to use these formats in a similar fashion to MSB aligned ones
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* implementation can multiply the values by 2^4=16. For that reason the padding
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* must only contain zeros.
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* index 0 = Y plane, [15:0] z:Y [4:12] little endian
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* index 1 = Cr plane, [15:0] z:Cr [4:12] little endian
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* index 2 = Cb plane, [15:0] z:Cb [4:12] little endian
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*/
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#define DRM_FORMAT_S012 fourcc_code('S', '0', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes 12 bits per channel */
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#define DRM_FORMAT_S212 fourcc_code('S', '2', '1', '2') /* 2x1 subsampled Cb (1) and Cr (2) planes 12 bits per channel */
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#define DRM_FORMAT_S412 fourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes 12 bits per channel */
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/*
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* 3 plane YCbCr
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* index 0 = Y plane, [15:0] Y little endian
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* index 1 = Cr plane, [15:0] Cr little endian
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* index 2 = Cb plane, [15:0] Cb little endian
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*/
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#define DRM_FORMAT_S016 fourcc_code('S', '0', '1', '6') /* 2x2 subsampled Cb (1) and Cr (2) planes 16 bits per channel */
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#define DRM_FORMAT_S216 fourcc_code('S', '2', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes 16 bits per channel */
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#define DRM_FORMAT_S416 fourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes 16 bits per channel */
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/*
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* 3 plane YCbCr
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* index 0: Y plane, [7:0] Y
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@ -422,6 +458,7 @@ extern "C" {
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#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
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#define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a
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#define DRM_FORMAT_MOD_VENDOR_MTK 0x0b
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#define DRM_FORMAT_MOD_VENDOR_APPLE 0x0c
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/* add more to the end as needed */
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@ -1494,6 +1531,50 @@ drm_fourcc_canonicalize_nvidia_format_mod(guint64 modifier)
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/* alias for the most common tiling format */
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#define DRM_FORMAT_MOD_MTK_16L_32S_TILE DRM_FORMAT_MOD_MTK(MTK_FMT_MOD_TILE_16L32S)
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/*
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* Apple GPU-tiled layouts.
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*
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* Apple GPUs support nonlinear tilings with optional lossless compression.
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*
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* GPU-tiled images are divided into 16KiB tiles:
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*
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* Bytes per pixel Tile size
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* --------------- ---------
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* 1 128x128
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* 2 128x64
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* 4 64x64
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* 8 64x32
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* 16 32x32
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*
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* Tiles are raster-order. Pixels within a tile are interleaved (Morton order).
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*
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* Compressed images pad the body to 128-bytes and are immediately followed by a
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* metadata section. The metadata section rounds the image dimensions to
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* powers-of-two and contains 8 bytes for each 16x16 compression subtile.
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* Subtiles are interleaved (Morton order).
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*
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* All images are 128-byte aligned.
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*
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* These layouts fundamentally do not have meaningful strides. No matter how we
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* specify strides for these layouts, userspace unaware of Apple image layouts
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* will be unable to use correctly the specified stride for any purpose.
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* Userspace aware of the image layouts do not use strides. The most "correct"
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* convention would be setting the image stride to 0. Unfortunately, some
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* software assumes the stride is at least (width * bytes per pixel). We
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* therefore require that stride equals (width * bytes per pixel). Since the
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* stride is arbitrary here, we pick the simplest convention.
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*
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* Although containing two sections, compressed image layouts are treated in
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* software as a single plane. This is modelled after AFBC, a similar
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* scheme. Attempting to separate the sections to be "explicit" in DRM would
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* only generate more confusion, as software does not treat the image this way.
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*
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* For detailed information on the hardware image layouts, see
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* https://docs.mesa3d.org/drivers/asahi.html#image-layouts
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*/
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#define DRM_FORMAT_MOD_APPLE_GPU_TILED fourcc_mod_code(APPLE, 1)
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#define DRM_FORMAT_MOD_APPLE_GPU_TILED_COMPRESSED fourcc_mod_code(APPLE, 2)
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/*
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* AMD modifiers
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*
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